From 9c90a2c8e87414007a016b7cd099ac1e32fd301b Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 24 Apr 2009 15:34:05 -0500
Subject: i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE value

Many boards/controllers/drivers don't support an I2C slave interface,
however CONFIG_SYS_I2C_SLAVE is used in common code so provide a
default

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 include/i2c.h | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

(limited to 'include')

diff --git a/include/i2c.h b/include/i2c.h
index f8a59a6699c..668e754e2a8 100644
--- a/include/i2c.h
+++ b/include/i2c.h
@@ -78,16 +78,22 @@
 #endif
 
 #ifdef CONFIG_8xx
-/* Set default values for the I2C bus speed and slave address on 8xx. In the
+/* Set default value for the I2C bus speed on 8xx. In the
  * future, we'll define these in all 8xx board config files.
  */
 #ifndef	CONFIG_SYS_I2C_SPEED
 #define	CONFIG_SYS_I2C_SPEED	50000
 #endif
+#endif
 
+/*
+ * Many boards/controllers/drivers don't support an I2C slave interface so
+ * provide a default slave address for them for use in common code.  A real
+ * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does
+ * support a slave interface.
+ */
 #ifndef	CONFIG_SYS_I2C_SLAVE
-#define	CONFIG_SYS_I2C_SLAVE	0xFE
-#endif
+#define	CONFIG_SYS_I2C_SLAVE	0xfe
 #endif
 
 /*
-- 
cgit v1.3.1


From 8d907e79bc9babb27396e34be54cfdc36ff62fb9 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 24 Apr 2009 15:34:08 -0500
Subject: mpc7448hpc2: Add CONFIG_SYS_I2C_SPEED define

Add standard CONFIG_SYS_I2C_SPEED define for the mpc7448hpc2 so that
it can use the common 'i2c speed' command.  Note that the I2C controller
utilized by the mpc7448hpc2 has a fixed speed and cannot be changed
dynamically.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 include/configs/mpc7448hpc2.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h
index a1783b20094..7d421556e9e 100644
--- a/include/configs/mpc7448hpc2.h
+++ b/include/configs/mpc7448hpc2.h
@@ -179,6 +179,7 @@
  */
 #define CONFIG_VERSION_VARIABLE		1
 #define CONFIG_TSI108_I2C
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed */
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* I2C EEPROM page 1 */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1	/* Bytes of address */
-- 
cgit v1.3.1


From d48eb5131d287f52bb85b4c58c8680a2e8e3b641 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Sat, 18 Apr 2009 22:34:02 -0500
Subject: i2c: Remove deprecated individual i2c commands

The following individual I2C commands have been removed: imd, imm, inm,
imw, icrc32, iprobe, iloop, isdram.

The functionality of the individual commands is still available via
the 'i2c' command.

This change only has an impact on those boards which did not have
CONFIG_I2C_CMD_TREE defined.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 README                           |  5 ----
 common/cmd_i2c.c                 | 58 ----------------------------------------
 doc/feature-removal-schedule.txt | 12 ---------
 include/configs/DU405.h          |  1 -
 include/configs/DU440.h          |  1 -
 include/configs/MPC8313ERDB.h    |  1 -
 include/configs/MPC8349EMDS.h    |  1 -
 include/configs/MPC8349ITX.h     |  1 -
 include/configs/MPC8360ERDK.h    |  1 -
 include/configs/MPC8536DS.h      |  1 -
 include/configs/MPC8568MDS.h     |  1 -
 include/configs/MPC8569MDS.h     |  1 -
 include/configs/MPC8572DS.h      |  1 -
 include/configs/MVBLM7.h         |  1 -
 include/configs/PMC440.h         |  1 -
 include/configs/SIMPC8313.h      |  1 -
 include/configs/XPEDITE5200.h    |  1 -
 include/configs/XPEDITE5370.h    |  1 -
 include/configs/ads5121.h        |  1 -
 include/configs/at91rm9200ek.h   |  1 -
 include/configs/katmai.h         |  1 -
 include/configs/keymile-common.h |  1 -
 include/configs/kmeter1.h        |  1 -
 include/configs/korat.h          |  1 -
 include/configs/sbc8349.h        |  1 -
 include/configs/socrates.h       |  1 -
 26 files changed, 98 deletions(-)

(limited to 'include')

diff --git a/README b/README
index 142dbccec1a..03ad69a8b6a 100644
--- a/README
+++ b/README
@@ -1315,11 +1315,6 @@ The following options need to be configured:
 		clock chips. See common/cmd_i2c.c for a description of the
 		command line interface.
 
-		CONFIG_I2C_CMD_TREE is a recommended option that places
-		all I2C commands under a single 'i2c' root command.  The
-		older 'imm', 'imd', 'iprobe' etc. commands are considered
-		deprecated and may disappear in the future.
-
 		CONFIG_HARD_I2C selects a hardware I2C controller.
 
 		CONFIG_SOFT_I2C configures u-boot to use a software (aka
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index c071df73265..fd9f9a44f81 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -1204,7 +1204,6 @@ int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 }
 #endif
 
-#if defined(CONFIG_I2C_CMD_TREE)
 int do_i2c_reset(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
@@ -1314,11 +1313,9 @@ int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 		cmd_usage(cmdtp);
 	return 0;
 }
-#endif  /* CONFIG_I2C_CMD_TREE */
 
 /***************************************************/
 
-#if defined(CONFIG_I2C_CMD_TREE)
 U_BOOT_CMD(
 	i2c, 6, 1, do_i2c,
 	"I2C sub-system",
@@ -1341,61 +1338,6 @@ U_BOOT_CMD(
 	"i2c sdram chip - print SDRAM configuration information\n"
 #endif
 );
-#endif /* CONFIG_I2C_CMD_TREE */
-U_BOOT_CMD(
-	imd,	4,	1,	do_i2c_md,		\
-	"i2c memory display",				\
-	"chip address[.0, .1, .2] [# of objects]\n    - i2c memory display\n" \
-);
-
-U_BOOT_CMD(
-	imm,	3,	1,	do_i2c_mm,
-	"i2c memory modify (auto-incrementing)",
-	"chip address[.0, .1, .2]\n"
-	"    - memory modify, auto increment address\n"
-);
-U_BOOT_CMD(
-	inm,	3,	1,	do_i2c_nm,
-	"memory modify (constant address)",
-	"chip address[.0, .1, .2]\n    - memory modify, read and keep address\n"
-);
-
-U_BOOT_CMD(
-	imw,	5,	1,	do_i2c_mw,
-	"memory write (fill)",
-	"chip address[.0, .1, .2] value [count]\n    - memory write (fill)\n"
-);
-
-U_BOOT_CMD(
-	icrc32,	5,	1,	do_i2c_crc,
-	"checksum calculation",
-	"chip address[.0, .1, .2] count\n    - compute CRC32 checksum\n"
-);
-
-U_BOOT_CMD(
-	iprobe,	1,	1,	do_i2c_probe,
-	"probe to discover valid I2C chip addresses",
-	"\n    -discover valid I2C chip addresses\n"
-);
-
-/*
- * Require full name for "iloop" because it is an infinite loop!
- */
-U_BOOT_CMD(
-	iloop,	5,	1,	do_i2c_loop,
-	"infinite loop on address range",
-	"chip address[.0, .1, .2] [# of objects]\n"
-	"    - loop, reading a set of addresses\n"
-);
-
-#if defined(CONFIG_CMD_SDRAM)
-U_BOOT_CMD(
-	isdram,	2,	1,	do_sdram,
-	"print SDRAM configuration information",
-	"chip\n    - print SDRAM configuration information\n"
-	"      (valid chip values 50..57)\n"
-);
-#endif
 
 #if defined(CONFIG_I2C_MUX)
 
diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt
index b1f0582f7b2..9bbdc0a8322 100644
--- a/doc/feature-removal-schedule.txt
+++ b/doc/feature-removal-schedule.txt
@@ -59,18 +59,6 @@ Who:	Wolfgang Denk <wd@denx.de> and board maintainers
 
 ---------------------------
 
-What:	Individual I2C commands
-When:	April 2009
-Why:	Per the U-Boot README, individual I2C commands such as "imd", "imm",
-	"imw", etc are deprecated.  The single "i2c" command which is
-	currently enabled via CONFIG_I2C_CMD_TREE contains the same
-	functionality as the individual I2C commands.  The individual
-	I2C commands should be removed as well as any references to
-	CONFIG_I2C_CMD_TREE.
-Who:	Peter Tyser <ptyser@xes-inc.com>
-
----------------------------
-
 What:	Legacy NAND code
 When:	April 2009
 Why:	Legacy NAND code is deprecated.  Similar functionality exists in
diff --git a/include/configs/DU405.h b/include/configs/DU405.h
index d1edd244b4e..cfb30233185 100644
--- a/include/configs/DU405.h
+++ b/include/configs/DU405.h
@@ -211,7 +211,6 @@
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC08) for environment
  */
-#define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/DU440.h b/include/configs/DU440.h
index e6abbdc5f3a..e9ea1bf7d08 100644
--- a/include/configs/DU440.h
+++ b/include/configs/DU440.h
@@ -170,7 +170,6 @@
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged	        */
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_I2C_CMD_TREE     1
 #define CONFIG_I2C_MULTI_BUS    1
 
 #define CONFIG_SYS_SPD_BUS_NUM         0
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 21aedee8722..52d27a1e404 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -321,7 +321,6 @@
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}} /* Don't probe these addrs */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 2d2799e111c..35ab88f080a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -315,7 +315,6 @@
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index ab6fe55c49b..ef0a09fbd7f 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -95,7 +95,6 @@
 
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_SYS_SPD_BUS_NUM		1	/* The I2C bus for SPD */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 477a1c5821f..138750459d2 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -265,7 +265,6 @@
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0x52}} /* Don't probe these addrs */
diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index bbb448d55fd..bc1267f49fc 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -337,7 +337,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0, 0x29}}	/* Don't probe these addrs */
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index 77224d98e7b..ac340473716 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -287,7 +287,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x52
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 0ee40c61803..77946ceae44 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -239,7 +239,6 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_HARD_I2C		/* I2C with hardware support*/
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h
index b60b3641f48..2aba689664f 100644
--- a/include/configs/MPC8572DS.h
+++ b/include/configs/MPC8572DS.h
@@ -378,7 +378,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_HARD_I2C		/* I2C with hardware support */
 #undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
 #define CONFIG_SYS_I2C_SLAVE		0x7F
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 8f741f58bbf..9fd27e3d573 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -53,7 +53,6 @@
 
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 
diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h
index fc48bc1db65..012ae798d18 100644
--- a/include/configs/PMC440.h
+++ b/include/configs/PMC440.h
@@ -230,7 +230,6 @@
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address  */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_I2C_MULTI_BUS	1
 
 #define CONFIG_SYS_I2C_MULTI_EEPROMS
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 79582e16c74..88ea7c7c93b 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -223,7 +223,6 @@
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #define CONFIG_FSL_I2C
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES		{{0,0x69}} /* Don't probe these addrs */
diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h
index 370aae1c4c6..89ab69272b5 100644
--- a/include/configs/XPEDITE5200.h
+++ b/include/configs/XPEDITE5200.h
@@ -226,7 +226,6 @@
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 
 /* I2C EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h
index a353a14e7dd..536e0633858 100644
--- a/include/configs/XPEDITE5370.h
+++ b/include/configs/XPEDITE5370.h
@@ -244,7 +244,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 
 /* PEX8518 slave I2C interface */
 #define CONFIG_SYS_I2C_PEX8518_ADDR	0x70
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index d87902468ee..b1420fa8886 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -287,7 +287,6 @@
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #if 0
diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h
index a018873fd68..c898c730467 100644
--- a/include/configs/at91rm9200ek.h
+++ b/include/configs/at91rm9200ek.h
@@ -266,7 +266,6 @@
 
 #ifdef CONFIG_HARD_I2C
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		0	/* not used */
 #define CONFIG_SYS_I2C_SLAVE		0	/* not used */
 #endif
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 0d89594f203..3840267312d 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -129,7 +129,6 @@
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address	*/
 
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_SPD_BUS_NUM		0	/* The I2C bus for SPD		*/
 
 #define IIC0_BOOTPROM_ADDR	0x50
diff --git a/include/configs/keymile-common.h b/include/configs/keymile-common.h
index b2e37ec2220..0fcf692d18b 100644
--- a/include/configs/keymile-common.h
+++ b/include/configs/keymile-common.h
@@ -97,7 +97,6 @@
 #define CONFIG_SYS_SLOT_ID_MASK		(0x3f)	/* mask for slot ID bits */
 
 #define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_SYS_MAX_I2C_BUS		2
 #define CONFIG_SYS_I2C_INIT_BOARD	1
 #define CONFIG_I2C_MUX		1
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index f7fc6c5bff4..61250adfed5 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -314,7 +314,6 @@
 #define CONFIG_SYS_I2C_SLAVE	0x7F
 #define CONFIG_SYS_I2C_OFFSET	0x3000
 #define CONFIG_I2C_MULTI_BUS	1
-#define CONFIG_I2C_CMD_TREE	1
 #define CONFIG_SYS_MAX_I2C_BUS		2
 #define CONFIG_I2C_MUX		1
 
diff --git a/include/configs/korat.h b/include/configs/korat.h
index eb2c1d43b49..ea6ba8938d7 100644
--- a/include/configs/korat.h
+++ b/include/configs/korat.h
@@ -282,7 +282,6 @@
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_FAT
 #define CONFIG_CMD_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_CMD_IRQ
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_NET
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index edd928d81b5..b89fe12c566 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -279,7 +279,6 @@
 #define CONFIG_HARD_I2C			/* I2C with hardware support*/
 #undef CONFIG_SOFT_I2C			/* I2C bit-banged */
 #define CONFIG_FSL_I2C
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 #define CONFIG_SYS_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index becd13eace3..5b91b4d7c7f 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -243,7 +243,6 @@
 #define CONFIG_SYS_I2C_OFFSET		0x3000
 
 #define CONFIG_I2C_MULTI_BUS
-#define CONFIG_I2C_CMD_TREE
 #define CONFIG_SYS_I2C2_OFFSET		0x3100
 
 /* I2C RTC */
-- 
cgit v1.3.1


From 0f89c54be92773b23d66ac401ba6acb6144100c3 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Sat, 18 Apr 2009 22:34:03 -0500
Subject: i2c: Update references to individual i2c commands

The individual i2c commands imd, imm, inm, imw, icrc32, iprobe, iloop,
and isdram are no longer available so all references to them have been
updated to the new form of "i2c <cmd>".

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
---
 README                    | 15 ++++-----------
 board/esd/tasreg/tasreg.c |  4 ++--
 common/cmd_i2c.c          | 27 +++++++++++----------------
 doc/README.ebony          | 20 ++++++++++----------
 doc/README.m52277evb      |  8 +-------
 doc/README.m5373evb       |  8 +-------
 doc/README.m54455evb      |  8 +-------
 doc/README.m5475evb       |  8 +-------
 doc/README.ppc440         |  4 ++--
 doc/README.xpedite1k      |  6 +++---
 drivers/i2c/tsi108_i2c.c  |  2 +-
 include/configs/bubinga.h |  2 +-
 include/configs/sacsng.h  |  6 +++---
 include/configs/taihu.h   |  2 +-
 14 files changed, 42 insertions(+), 78 deletions(-)

(limited to 'include')

diff --git a/README b/README
index 03ad69a8b6a..75fc4b7b311 100644
--- a/README
+++ b/README
@@ -1430,9 +1430,9 @@ The following options need to be configured:
 		CONFIG_SYS_I2C_NOPROBES
 
 		This option specifies a list of I2C devices that will be skipped
-		when the 'i2c probe' command is issued (or 'iprobe' using the legacy
-		command).  If CONFIG_I2C_MULTI_BUS is set, specify a list of bus-device
-		pairs.	Otherwise, specify a 1D array of device addresses
+		when the 'i2c probe' command is issued.  If CONFIG_I2C_MULTI_BUS
+		is set, specify a list of bus-device pairs.  Otherwise, specify
+		a 1D array of device addresses
 
 		e.g.
 			#undef	CONFIG_I2C_MULTI_BUS
@@ -2866,14 +2866,7 @@ mw	- memory write (fill)
 cp	- memory copy
 cmp	- memory compare
 crc32	- checksum calculation
-imd	- i2c memory display
-imm	- i2c memory modify (auto-incrementing)
-inm	- i2c memory modify (constant address)
-imw	- i2c memory write (fill)
-icrc32	- i2c checksum calculation
-iprobe	- probe to discover valid I2C chip addresses
-iloop	- infinite loop on address range
-isdram	- print SDRAM configuration information
+i2c	- I2C sub-system
 sspi	- SPI utility commands
 base	- print or set address offset
 printenv- print environment variables
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
index 760c71d264e..9602ee59fdd 100644
--- a/board/esd/tasreg/tasreg.c
+++ b/board/esd/tasreg/tasreg.c
@@ -231,7 +231,7 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 	addr = simple_strtol (argv[1], NULL, 16);
 
-	printf("iprobe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
+	printf("i2c probe looping on addr 0x%lx (cntrl-c aborts)...\n", addr);
 
 	for (;;) {
 		i2c_probe(addr);
@@ -249,7 +249,7 @@ int do_iploop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 }
 U_BOOT_CMD(
 	iploop,	2,	1,	do_iploop,
-	"iprobe loop <addr>",
+	"i2c probe loop <addr>",
 	NULL
 	);
 
diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c
index fd9f9a44f81..903856d2d57 100644
--- a/common/cmd_i2c.c
+++ b/common/cmd_i2c.c
@@ -27,11 +27,6 @@
  * There are several parameters in many of the commands that bear further
  * explanations:
  *
- * Two of the commands (imm and imw) take a byte/word/long modifier
- * (e.g. imm.w specifies the word-length modifier).  This was done to
- * allow manipulating word-length registers.  It was not done on any other
- * commands because it was not deemed useful.
- *
  * {i2c_chip} is the I2C chip address (the first byte sent on the bus).
  *   Each I2C chip on the bus has a unique address.  On the I2C data bus,
  *   the address is the upper seven bits and the LSB is the "read/write"
@@ -69,11 +64,11 @@
  *   {addr} field (since .1 is the default, it doesn't actually have to
  *   be specified).  Examples: given a memory chip at I2C chip address
  *   0x50, the following would happen...
- *     imd 50 0 10      display 16 bytes starting at 0x000
+ *     i2c md 50 0 10   display 16 bytes starting at 0x000
  *                      On the bus: <S> A0 00 <E> <S> A1 <rd> ... <rd>
- *     imd 50 100 10    display 16 bytes starting at 0x100
+ *     i2c md 50 100 10 display 16 bytes starting at 0x100
  *                      On the bus: <S> A2 00 <E> <S> A3 <rd> ... <rd>
- *     imd 50 210 10    display 16 bytes starting at 0x210
+ *     i2c md 50 210 10 display 16 bytes starting at 0x210
  *                      On the bus: <S> A4 10 <E> <S> A5 <rd> ... <rd>
  *   This is awfully ugly.  It would be nice if someone would think up
  *   a better way of handling this.
@@ -158,7 +153,7 @@ int i2c_set_bus_speed(unsigned int)
 
 /*
  * Syntax:
- *	imd {i2c_chip} {addr}{.0, .1, .2} {len}
+ *	i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
  */
 #define DISP_LINE_LEN	16
 
@@ -275,7 +270,7 @@ int do_i2c_nm ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /* Write (fill) memory
  *
  * Syntax:
- *	imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
+ *	i2c mw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}]
  */
 int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -359,7 +354,7 @@ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /* Calculate a CRC on memory
  *
  * Syntax:
- *	icrc32 {i2c_chip} {addr}{.0, .1, .2} {count}
+ *	i2c crc32 {i2c_chip} {addr}{.0, .1, .2} {count}
  */
 int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -428,8 +423,8 @@ int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 /* Modify memory.
  *
  * Syntax:
- *	imm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
- *	inm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
+ *	i2c mm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
+ *	i2c nm{.b, .w, .l} {i2c_chip} {addr}{.0, .1, .2}
  */
 
 static int
@@ -562,7 +557,7 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[])
 
 /*
  * Syntax:
- *	iprobe {addr}{.0, .1, .2}
+ *	i2c probe {addr}{.0, .1, .2}
  */
 int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
@@ -604,7 +599,7 @@ int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 
 /*
  * Syntax:
- *	iloop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
+ *	i2c loop {i2c_chip} {addr}{.0, .1, .2} [{length}] [{delay}]
  *	{length} - Number of bytes to read
  *	{delay}  - A DECIMAL number and defaults to 1000 uSec
  */
@@ -726,7 +721,7 @@ static void decode_bits (u_char const b, char const *str[], int const do_once)
 
 /*
  * Syntax:
- *	sdram {i2c_chip}
+ *	i2c sdram {i2c_chip}
  */
 int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
diff --git a/doc/README.ebony b/doc/README.ebony
index a395a499621..a8479a4799d 100644
--- a/doc/README.ebony
+++ b/doc/README.ebony
@@ -31,17 +31,17 @@ J42: open
 All others are factory default.
 
 
-I2C iprobe
+I2C probe
 =====================
 
 The i2c utilities have been tested on both Rev B. and Rev C. and
 look good. The CONFIG_SYS_I2C_NOPROBES macro is defined to prevent
 probing the CDCV850 clock controller at address 0x69 (since reading
 it causes the i2c implementation to misbehave. The output of
-iprobe should look like this (assuming you are only using a single
+'i2c probe' should look like this (assuming you are only using a single
 SO-DIMM:
 
-=> iprobe
+=> i2c probe
 Valid chip addresses: 50 53 54
 Excluded chip addresses: 69
 
@@ -63,13 +63,13 @@ J42 - strapped
 
 This will select the default sys0 and sys1 settings (the serial
 eeproms are not used). Then power up the board and fix the serial
-eeprom using the imm command. Here are the values I currently
+eeprom using the 'i2c mm' command. Here are the values I currently
 use:
 
-=> imd 50 0 10
+=> i2c md 50 0 10
 0000: bf a2 04 01 ae 94 11 00 00 00 00 00 00 00 00 00    ................
 
-=> imd 54 0 10
+=> i2c md 54 0 10
 0000: 8f b3 24 01 4d 14 11 00 00 00 00 00 00 00 00 00    ..$.M...........
 
 Once you have the eeproms set correctly change the
@@ -83,8 +83,8 @@ the SPD to initialize the DDR SDRAM control registers. So if the SPD
 eeprom is corrupted, U-Boot will never get into ram. Here's how I got
 out of this situation:
 
-0. First, _before_ playing with the i2c utilities, do an iprobe, then
-use imd to capture the various device contents to a file. Some day
+0. First, _before_ playing with the i2c utilities, do an 'i2c probe', then
+use 'i2c md' to capture the various device contents to a file. Some day
 you may be glad you did this ... trust me :-). Otherwise try the
 following:
 
@@ -100,12 +100,12 @@ settings without using the SPD eeprom.
 
 3. Load the new U-Boot image and reboot ebony.
 
-4. Repair the SPD eeprom using the imm command. Here's the eeprom
+4. Repair the SPD eeprom using the 'i2c mm' command. Here's the eeprom
 contents that work with the default SO-DIMM that comes with the
 ebony board (micron 8VDDT164AG-265A1). Note: these are probably
 _not_ the factory settings ... but they work.
 
-=> imd 53 0 10 80
+=> i2c md 53 0 10 80
 0000: 80 08 07 0c 0a 01 40 00 04 75 75 00 80 08 00 01    ......@..uu.....
 0010: 0e 04 0c 01 02 20 00 a0 75 00 00 50 3c 50 2d 20    ..... ..u..P<P-
 0020: 90 90 50 50 00 00 00 00 00 41 4b 34 32 75 00 00    ..PP.....AK42u..
diff --git a/doc/README.m52277evb b/doc/README.m52277evb
index e002947993a..bec77b48aa5 100644
--- a/doc/README.m52277evb
+++ b/doc/README.m52277evb
@@ -204,16 +204,10 @@ erase   - erase FLASH memory
 flinfo  - print FLASH memory information
 go      - start application at address 'addr'
 help    - print online help
+i2c     - I2C sub-system
 icache  - enable or disable instruction cache
-icrc32  - checksum calculation
-iloop   - infinite loop on address range
-imd     - i2c memory display
 iminfo  - print header information for application image
 imls    - list all images found in flash
-imm     - i2c memory modify (auto-incrementing)
-imw     - memory write (fill)
-inm     - memory modify (constant address)
-iprobe  - probe to discover valid I2C chip addresses
 itest	- return true/false on integer compare
 loadb   - load binary file over serial line (kermit mode)
 loads   - load S-Record file over serial line
diff --git a/doc/README.m5373evb b/doc/README.m5373evb
index 4781d941722..0bd1101c793 100644
--- a/doc/README.m5373evb
+++ b/doc/README.m5373evb
@@ -215,16 +215,10 @@ erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 go	- start application at address 'addr'
 help	- print online help
+i2c	- I2C sub-system
 icache	- enable or disable instruction cache
-icrc32	- checksum calculation
-iloop	- infinite loop on address range
-imd	- i2c memory display
 iminfo	- print header information for application image
 imls	- list all images found in flash
-imm	- i2c memory modify (auto-incrementing)
-imw	- memory write (fill)
-inm	- memory modify (constant address)
-iprobe	- probe to discover valid I2C chip addresses
 itest	- return true/false on integer compare
 loadb	- load binary file over serial line (kermit mode)
 loads	- load S-Record file over serial line
diff --git a/doc/README.m54455evb b/doc/README.m54455evb
index f695da5f1cc..b769ff99571 100644
--- a/doc/README.m54455evb
+++ b/doc/README.m54455evb
@@ -304,17 +304,11 @@ fsinfo	- print information about filesystems
 fsload	- load binary file from a filesystem image
 go      - start application at address 'addr'
 help    - print online help
+i2c     - I2C sub-system
 icache  - enable or disable instruction cache
-icrc32  - checksum calculation
 ide     - IDE sub-system
-iloop   - infinite loop on address range
-imd     - i2c memory display
 iminfo  - print header information for application image
 imls    - list all images found in flash
-imm     - i2c memory modify (auto-incrementing)
-imw     - memory write (fill)
-inm     - memory modify (constant address)
-iprobe  - probe to discover valid I2C chip addresses
 itest	- return true/false on integer compare
 loadb   - load binary file over serial line (kermit mode)
 loads   - load S-Record file over serial line
diff --git a/doc/README.m5475evb b/doc/README.m5475evb
index dc9a6057120..936c01815a8 100644
--- a/doc/README.m5475evb
+++ b/doc/README.m5475evb
@@ -234,16 +234,10 @@ erase	- erase FLASH memory
 flinfo	- print FLASH memory information
 go	- start application at address 'addr'
 help	- print online help
+i2c	- I2C sub-system
 icache	- enable or disable instruction cache
-icrc32	- checksum calculation
-iloop	- infinite loop on address range
-imd	- i2c memory display
 iminfo	- print header information for application image
 imls	- list all images found in flash
-imm	- i2c memory modify (auto-incrementing)
-imw	- memory write (fill)
-inm	- memory modify (constant address)
-iprobe	- probe to discover valid I2C chip addresses
 itest	- return true/false on integer compare
 loadb	- load binary file over serial line (kermit mode)
 loads	- load S-Record file over serial line
diff --git a/doc/README.ppc440 b/doc/README.ppc440
index 0a5f99fb134..1b96458d9e7 100644
--- a/doc/README.ppc440
+++ b/doc/README.ppc440
@@ -88,7 +88,7 @@ I2C
 =================
 
 The i2c utilities have been tested on both Rev B. and Rev C. and
-look good. The iprobe command implementation has been updated to
+look good. The 'i2c probe' command implementation has been updated to
 allow for 'skipped' addresses. Some i2c slaves are write only and
 cause problems when a probe (read) is performed (for example the
 CDCV850 clock controller at address 0x69 on the ebony board).
@@ -97,7 +97,7 @@ To prevent probing certain addresses you can define the
 CONFIG_SYS_I2C_NOPROBES macro in your board-specific header file. When
 defined, all specified addresses are skipped during a probe.
 The addresses that are skipped will be displayed in the output
-of the iprobe command.
+of the 'i2c probe' command.
 
 For example, to prevent probing address 0x69, define the macro as
 follows:
diff --git a/doc/README.xpedite1k b/doc/README.xpedite1k
index 34bba1325b4..1da8b800bec 100644
--- a/doc/README.xpedite1k
+++ b/doc/README.xpedite1k
@@ -23,7 +23,7 @@ strappings and the 2 EMAC HW Ethernet addresses.  Be careful not to
 change the 1st page of the EEPROM!  Unpopulated jumper J560 can get you
 out of trouble as it disables the strapping read from EEPROM.
 
-I2C iprobe
+I2C probe
 =====================
 
 The i2c utilities work and have been tested on Rev B. of the 440GX. See
@@ -47,10 +47,10 @@ J560 - closed
 
 This will select the default sys0 and sys1 settings (the serial
 eeproms are not used). Then power up the board and fix the serial
-eeprom using the imm command. Here are the values I currently
+eeprom using the 'i2c mm' command. Here are the values I currently
 use:
 
-=> imd 50 0 10
+=> i2c md 50 0 10
 
 0000: 85 7d 42 06 07 80 11 00 00 00 00 00 00 00 00 00    .}B.............
 
diff --git a/drivers/i2c/tsi108_i2c.c b/drivers/i2c/tsi108_i2c.c
index 3829ef98f61..defbba40fe4 100644
--- a/drivers/i2c/tsi108_i2c.c
+++ b/drivers/i2c/tsi108_i2c.c
@@ -129,7 +129,7 @@ static int i2c_read_byte (
  *   chip_addr: I2C chip address, range 0..127
  *                  (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
  *              NOTE: The bit 7 in the chip_addr serves as a channel select.
- *              This hack is for enabling "isdram" command on Tsi108 boards
+ *              This hack is for enabling "i2c sdram" command on Tsi108 boards
  *              without changes to common code. Used for I2C reads only.
  *   byte_addr: Memory or register address within the chip
  *   alen:      Number of bytes to use for addr (typically 1, 2 for larger
diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h
index dcf5b6de05c..627060a7591 100644
--- a/include/configs/bubinga.h
+++ b/include/configs/bubinga.h
@@ -134,7 +134,7 @@
  */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 }	/* avoid iprobe hangup (why?) */
+#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 }	/* avoid i2c probe hangup (why?) */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6	/* 24C02 requires 5ms delay */
 
 #if defined(CONFIG_CMD_EEPROM)
diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h
index f4e08c689f1..0ab6fc31ea8 100644
--- a/include/configs/sacsng.h
+++ b/include/configs/sacsng.h
@@ -408,9 +408,9 @@
     "echo hostname  ${hostname}\0" \
 "ana=run adc ; run dac\0" \
 "adc=run adc-12 ; run adc-34\0" \
-"adc-12=echo ### ADC-12 ; imd.b e 81 e\0" \
-"adc-34=echo ### ADC-34 ; imd.b f 81 e\0" \
-"dac=echo ### DAC ; imd.b 11 81 5\0" \
+"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
+"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
+"dac=echo ### DAC ; i2c md 11 81 5\0" \
 "boot-hook=echo\0"
 
 /* What should the console's baud rate be? */
diff --git a/include/configs/taihu.h b/include/configs/taihu.h
index 8c48c669dcb..836081d0d51 100644
--- a/include/configs/taihu.h
+++ b/include/configs/taihu.h
@@ -139,7 +139,7 @@
  */
 #define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
 
-#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 } /* avoid iprobe hangup (why?) */
+#define CONFIG_SYS_I2C_NOPROBES	{ 0x69 } /* avoid i2c probe hangup (why?) */
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */
 
 #define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
-- 
cgit v1.3.1


From 7cc635fb35f5b94e304fa2243d56758f57f6416b Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 29 Apr 2009 09:50:57 +0200
Subject: 4xx: Remove binary cpld bitstream from CMS700 board

This patch removes the cpld binary bitstream that is
used by esd's cpld command on CMS700 boards.

Because u-boot with an external cpld bitstream may not
take more space in flash than before the u-boot binary is
shrinked a little bit. Some unused featues have been
removed therefore.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/esd/cms700/cms700.c   |    8 -
 board/esd/cms700/config.mk  |    7 +-
 board/esd/cms700/fpgadata.c | 1812 -------------------------------------------
 include/configs/CMS700.h    |   53 +-
 4 files changed, 6 insertions(+), 1874 deletions(-)
 delete mode 100644 board/esd/cms700/fpgadata.c

(limited to 'include')

diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 9a522b2c0be..658a26796a1 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -31,14 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
-
 int board_early_init_f (void)
 {
 	/*
diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk
index 5c3c01cf874..8e48bcd6cb6 100644
--- a/board/esd/cms700/config.mk
+++ b/board/esd/cms700/config.mk
@@ -20,9 +20,4 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
-#
-# esd CMS405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
+TEXT_BASE = 0xFFFC8000
diff --git a/board/esd/cms700/fpgadata.c b/board/esd/cms700/fpgadata.c
deleted file mode 100644
index 08be5e79496..00000000000
--- a/board/esd/cms700/fpgadata.c
+++ /dev/null
@@ -1,1812 +0,0 @@
-  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
-  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
-  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
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-  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
-  0x00,0x09,0x00,0x34,0x84,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x90,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x34,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x34,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x34,0xc4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x34,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,
-  0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
-  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x00,0x00,
-  0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x35,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x04,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x09,0x00,0x35,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x35,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x35,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x35,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x35,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x35,0x28,0x00,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
-  0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x00,
-  0x00,0x40,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x35,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
-  0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x1c,
-  0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x14,0x00,0x61,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x35,0xd0,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
-  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
-  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h
index 40fef88f98e..ae8494d577c 100644
--- a/include/configs/CMS700.h
+++ b/include/configs/CMS700.h
@@ -80,8 +80,6 @@
 
 #define CONFIG_CMD_DHCP
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
 #define CONFIG_CMD_NAND
 #define CONFIG_CMD_I2C
@@ -167,31 +165,6 @@
 #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
 #define CONFIG_SYS_NAND_QUIET          1
 
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -222,21 +195,16 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT		1
@@ -291,8 +259,7 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
 
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
@@ -356,17 +323,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
 #define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
 
 #endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 0bb10630364c48d9857cbf5353da609fc4dd6751 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 29 Apr 2009 09:50:58 +0200
Subject: 4xx: Remove binary cpld bitstream from PMC405 board

This patch removes the cpld binary bitstream that is
used by esd's cpld command on PMC405 boards.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/esd/pmc405/fpgadata.c | 2472 -------------------------------------------
 board/esd/pmc405/pmc405.c   |    7 -
 include/configs/PMC405.h    |    3 -
 3 files changed, 2482 deletions(-)
 delete mode 100644 board/esd/pmc405/fpgadata.c

(limited to 'include')

diff --git a/board/esd/pmc405/fpgadata.c b/board/esd/pmc405/fpgadata.c
deleted file mode 100644
index ebdf71dc787..00000000000
--- a/board/esd/pmc405/fpgadata.c
+++ /dev/null
@@ -1,2472 +0,0 @@
-  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
-  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
-  0xf9,0x60,0x20,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
-  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
-  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
-  0x08,0xea,0x08,0x00,0x00,0x00,0x22,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,
-  0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x00,0x04,0x38,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x00,0x10,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x24,0x38,0x01,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x00,0x28,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x2c,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x30,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x00,0x40,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
-  0x14,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,
-  0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x03,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,0x80,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0x84,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x09,0x00,0x00,0x88,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x8c,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x90,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x00,0xa0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa4,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xa8,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x00,0xac,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
-  0xb0,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xc0,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x00,0xc4,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x00,0xc8,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0xcc,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0xd0,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x01,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x04,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x01,0x08,0x01,0x01,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x01,0x0c,0x00,0x01,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x01,
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-  0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,
-  0x00,0x00,
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 94caa6c5e55..192a642aea0 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -34,13 +34,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
 int board_early_init_f (void)
 {
 	/*
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index c598d00cf0c..a9e71346e0f 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -282,9 +282,6 @@
 /*
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	/* using Xilinx XC95XL CPLD */
-#define CONFIG_SYS_FPGA_MAX_SIZE	(32 * 1024) /* 32kByte for CPLD */
-
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000 /* JTAG TMS pin (output) */
 #define CONFIG_SYS_FPGA_CLK		0x02000000 /* JTAG TCK pin (output) */
-- 
cgit v1.3.1


From 700d553fd3afe804086de8f73d95153315eb0c32 Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 29 Apr 2009 09:50:59 +0200
Subject: 4xx: Remove binary cpld bitstream from VOM405 board

This patch removes the cpld binary bitstream that is
used by esd's cpld command on VOM405 boards.

Because u-boot with an external cpld bitstream may not
take more space in flash than before the u-boot binary is
shrinked a little bit.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/esd/vom405/config.mk  |    8 +-
 board/esd/vom405/fpgadata.c | 1812 -------------------------------------------
 board/esd/vom405/vom405.c   |    7 -
 include/configs/VOM405.h    |   21 +-
 4 files changed, 6 insertions(+), 1842 deletions(-)
 delete mode 100644 board/esd/vom405/fpgadata.c

(limited to 'include')

diff --git a/board/esd/vom405/config.mk b/board/esd/vom405/config.mk
index 3041b772d24..8e48bcd6cb6 100644
--- a/board/esd/vom405/config.mk
+++ b/board/esd/vom405/config.mk
@@ -20,10 +20,4 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-
-#
-# esd VOH405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
+TEXT_BASE = 0xFFFC8000
diff --git a/board/esd/vom405/fpgadata.c b/board/esd/vom405/fpgadata.c
deleted file mode 100644
index 1c3a963892a..00000000000
--- a/board/esd/vom405/fpgadata.c
+++ /dev/null
@@ -1,1812 +0,0 @@
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-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x28,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x2c,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x30,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x44,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x34,0x48,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x34,0x4c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x34,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x34,0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,
-  0x00,0x09,0x00,0x34,0x84,0x00,0x00,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0x88,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x8c,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0x90,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x34,0xa4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x34,0xa8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x34,0xac,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x34,0xb0,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x34,0xc0,0x00,0x00,0x00,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x34,0xc4,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x34,0xc8,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x34,
-  0xcc,0x00,0x00,0x00,0x81,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,
-  0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x34,0xd0,0x00,0x00,0x00,
-  0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,
-  0x09,0x00,0x35,0x00,0xa0,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x04,
-  0x80,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x09,0x00,0x35,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x35,0x0c,0x20,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x35,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x35,0x20,0xc0,0x00,0x14,0x11,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x35,0x24,0x00,0x00,0x00,0x15,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x35,0x28,0x00,0x80,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
-  0x2c,0xc0,0x00,0x14,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x30,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x40,0x08,
-  0x00,0x04,0x09,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x44,0x80,0x00,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x88,0x00,0x84,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x00,0x03,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x00,
-  0x00,0x30,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x35,0x88,0x20,0x80,0x08,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
-  0x8c,0x40,0x00,0xc0,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
-  0xa0,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0x00,
-  0x00,0x20,0x0d,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0x00,0x80,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0xc0,0x1c,0x14,
-  0x85,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x48,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0xc0,0x00,0x14,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x80,0x00,0x80,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x00,0x00,0x80,0x09,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x08,0x00,0x04,0x61,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x40,0x00,0x48,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x35,0xd0,0x88,0x00,0x04,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x88,0x00,0x04,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
-  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
-  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index d67b23eae2c..a481acaea14 100644
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -31,13 +31,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 extern void lxt971_no_sleep(void);
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
 int board_early_init_f (void)
 {
 	/*
diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h
index db00c652ff2..4717869ddef 100644
--- a/include/configs/VOM405.h
+++ b/include/configs/VOM405.h
@@ -177,10 +177,10 @@
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT		1
@@ -231,8 +231,7 @@
 /*
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
+#define CONFIG_SYS_XSVF_DEFAULT_ADDR	0xfffc0000
 
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
@@ -293,17 +292,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
 #define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
 
 #endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From de47a34d4de1d007a8951efd072283516d580ffa Mon Sep 17 00:00:00 2001
From: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
Date: Wed, 29 Apr 2009 09:51:00 +0200
Subject: 4xx: Remove binary cpld bitstream from DP405 board

This patch removes the cpld binary bitstream that is
used by esd's cpld command on DP405 boards.

Because u-boot with an external cpld bitstream may not
take more space in flash than before the u-boot binary is
shrinked a little bit. Some unused featues have been
removed therefore.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 board/esd/dp405/config.mk  |    7 +-
 board/esd/dp405/dp405.c    |    8 -
 board/esd/dp405/fpgadata.c | 1812 --------------------------------------------
 include/configs/DP405.h    |   86 +--
 4 files changed, 7 insertions(+), 1906 deletions(-)
 delete mode 100644 board/esd/dp405/fpgadata.c

(limited to 'include')

diff --git a/board/esd/dp405/config.mk b/board/esd/dp405/config.mk
index 3041b772d24..9b1a8bebb2f 100644
--- a/board/esd/dp405/config.mk
+++ b/board/esd/dp405/config.mk
@@ -21,9 +21,4 @@
 # MA 02111-1307 USA
 #
 
-#
-# esd VOH405 boards
-#
-
-TEXT_BASE = 0xFFFC0000
-#TEXT_BASE = 0x00FC0000
+TEXT_BASE = 0xFFFD0000
diff --git a/board/esd/dp405/dp405.c b/board/esd/dp405/dp405.c
index c32c7c7a0fe..352b877e398 100644
--- a/board/esd/dp405/dp405.c
+++ b/board/esd/dp405/dp405.c
@@ -29,14 +29,6 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* fpga configuration data - not compressed, generated by bin2c */
-const unsigned char fpgadata[] =
-{
-#include "fpgadata.c"
-};
-int filesize = sizeof(fpgadata);
-
-
 int board_early_init_f (void)
 {
 	/*
diff --git a/board/esd/dp405/fpgadata.c b/board/esd/dp405/fpgadata.c
deleted file mode 100644
index eae8457ca2c..00000000000
--- a/board/esd/dp405/fpgadata.c
+++ /dev/null
@@ -1,1812 +0,0 @@
-  0x07,0x20,0x12,0x00,0x12,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,
-  0xfe,0x08,0x00,0x00,0x00,0x20,0x01,0x0f,0xff,0xff,0xff,0x09,0x00,0x00,0x00,0x00,
-  0xf9,0x60,0x40,0x93,0x02,0x08,0xff,0x02,0x08,0xff,0x02,0x08,0xe8,0x08,0x00,0x00,
-  0x00,0x06,0x01,0x00,0x09,0x05,0x00,0x02,0x08,0xed,0x04,0x00,0x03,0x0d,0x40,0x08,
-  0x00,0x00,0x00,0x12,0x01,0x00,0x00,0x00,0x09,0x03,0xff,0xff,0x00,0x00,0x00,0x01,
-  0x00,0x00,0x03,0x09,0x03,0xff,0xfd,0x03,0xff,0xfd,0x04,0x00,0x00,0x00,0x00,0x02,
-  0x08,0xea,0x08,0x00,0x00,0x00,0x32,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x04,0x00,0x00,0x00,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x08,0x00,0x00,0x00,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x0c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x00,0x10,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x09,0x00,0x00,0x20,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x01,0x09,0x00,0x00,0x24,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,
-  0x09,0x00,0x00,0x28,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
-  0x00,0x00,0x2c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,
-  0x00,0x30,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,
-  0x40,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x44,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x48,0x00,
-  0x40,0x00,0x21,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x00,0x4c,0x00,0x80,
-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x50,0x00,0x00,0x00,0x03,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x00,
-  0x80,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x00,0x84,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-  0x09,0x00,0x00,0x88,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,
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-  0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x48,0x00,0x00,0x00,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x4c,0x00,0x00,0x60,0x81,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x50,0x00,0x00,0x40,0x03,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0x80,0x20,
-  0x00,0xcc,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x09,0x00,0x35,0x84,0x20,0x00,0xc8,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,0x00,
-  0x35,0x88,0x20,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,
-  0x8c,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0x90,
-  0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa0,0xc0,
-  0x80,0x14,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa4,0xc0,0x80,
-  0x54,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xa8,0xc0,0x00,0x94,
-  0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xac,0x00,0x00,0x40,0x01,
-  0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xb0,0x00,0x00,0x40,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc0,0x08,0x00,0xc4,0x09,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc4,0x08,0x00,0xc4,0x01,0x00,0x00,0x00,
-  0x00,0x00,0x00,0x01,0x09,0x00,0x35,0xc8,0x08,0x00,0x00,0x01,0x00,0x00,0x00,0x00,
-  0x00,0x00,0x01,0x09,0x00,0x35,0xcc,0x00,0x00,0x00,0x01,0x00,0x00,0x00,0x00,0x00,
-  0x00,0x01,0x04,0x00,0x00,0x4e,0x20,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x09,
-  0x00,0x35,0xd0,0x00,0x00,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,
-  0x00,0x00,0x00,0x00,0x00,0x03,0x09,0x00,0x35,0xd0,0x00,0x00,0x80,0x01,0x00,0x00,
-  0x00,0x00,0x00,0x00,0x01,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x04,0x00,0x00,
-  0x00,0x64,0x02,0x08,0xf0,0x04,0x00,0x00,0x00,0x00,0x02,0x08,0xff,0x02,0x08,0xff,
-  0x08,0x00,0x00,0x00,0x01,0x01,0x00,0x09,0x00,0x00,0x00,
diff --git a/include/configs/DP405.h b/include/configs/DP405.h
index 187547d2aaf..49ecb6f36c8 100644
--- a/include/configs/DP405.h
+++ b/include/configs/DP405.h
@@ -52,39 +52,20 @@
 
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_BSP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
 #define CONFIG_CMD_ELF
-#define CONFIG_CMD_DATE
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_EEPROM
 
+#undef CONFIG_CMD_NET
 
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
-#define CONFIG_RTC_MC146818		/* DS1685 is MC146818 compatible*/
-#define CONFIG_SYS_RTC_REG_BASE_ADDR	 0xF0000500 /* RTC Base Address		*/
-
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
 
 #define CONFIG_PRAM		2	/* reserve 2 kB "protected RAM" */
@@ -134,33 +115,6 @@
 
 #define CONFIG_VERSION_VARIABLE 1	/* include version env variable */
 
-#define CONFIG_SYS_RX_ETH_BUFFER	16	/* use 16 rx buffer on 405 emac */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_HOST PCI_HOST_HOST	/* select pci host function	*/
-#undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#undef	CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: CPCI-405	*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -191,21 +145,16 @@
 
 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
 
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK	0	    /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS	1	    /* ! second bank contains U-Boot */
-#endif
-
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)	/* Reserve 256 kB for malloc()	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(~(TEXT_BASE) + 1)
+#define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
 
 #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
 # define CONFIG_SYS_RAMBOOT		1
@@ -221,9 +170,6 @@
 #define CONFIG_ENV_SIZE		0x700	/* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xF0000500		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		242			/* NVRAM size		*/
-
 /*-----------------------------------------------------------------------
  * I2C EEPROM (CAT24WC16) for environment
  */
@@ -245,18 +191,11 @@
  */
 
 #define CAN_BA		0xF0000000	    /* CAN Base Address			*/
-#define RTC_BA		0xF0000500	    /* RTC Base Address			*/
 
 /* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization			*/
 #define CONFIG_SYS_EBC_PB0AP		0x92015480
 #define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 
-#if 0 /* test-only */
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization			*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xF4018000  /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit	*/
-#endif
-
 /* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization		*/
 #define CONFIG_SYS_EBC_PB2AP		0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 #define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
@@ -264,9 +203,6 @@
 /*-----------------------------------------------------------------------
  * FPGA stuff
  */
-#define CONFIG_SYS_FPGA_XC95XL		1	    /* using Xilinx XC95XL CPLD	     */
-#define CONFIG_SYS_FPGA_MAX_SIZE	32*1024	    /* 32kByte is enough for CPLD    */
-
 /* FPGA program pin configuration */
 #define CONFIG_SYS_FPGA_PRG		0x04000000  /* JTAG TMS pin (ppc output)     */
 #define CONFIG_SYS_FPGA_CLK		0x02000000  /* JTAG TCK pin (ppc output)     */
@@ -312,7 +248,7 @@
 #define CONFIG_SYS_GPIO0_ISR1L		0x14000045  /* 16 ... 31 */
 #define CONFIG_SYS_GPIO0_TSRH		0x00000000  /*	0 ... 15 */
 #define CONFIG_SYS_GPIO0_TSRL		0x00000000  /* 16 ... 31 */
-#define CONFIG_SYS_GPIO0_TCR		0xF7FE0014  /*	0 ... 31 */
+#define CONFIG_SYS_GPIO0_TCR		0xB7FE0014  /*	0 ... 31 */
 
 /*
  * Internal Definitions
@@ -326,17 +262,7 @@
  * Default speed selection (cpu_plb_opb_ebc) in mhz.
  * This value will be set if iic boot eprom is disabled.
  */
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT	 PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT	 PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT	 PLLMR1_200_100_50_33
-#endif
-#if 1
 #define PLLMR0_DEFAULT	 PLLMR0_133_66_66_33
 #define PLLMR1_DEFAULT	 PLLMR1_133_66_66_33
-#endif
 
 #endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 18cc7afd9a153a66854af862d14ba01c5496cf07 Mon Sep 17 00:00:00 2001
From: Ben Warren <biggerbadderben@gmail.com>
Date: Tue, 28 Apr 2009 16:50:53 -0700
Subject: Enable CONFIG_NET_MULTI on all remaining PPC4xx boards

All in-tree PPC4xx boards now use CONFIG_NET_MULTI

Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/configs/AR405.h          | 1 +
 include/configs/CPCIISER4.h      | 1 +
 include/configs/CRAYL1.h         | 1 +
 include/configs/ERIC.h           | 1 +
 include/configs/EXBITGEN.h       | 1 +
 include/configs/HUB405.h         | 1 +
 include/configs/JSE.h            | 1 +
 include/configs/MIP405.h         | 1 +
 include/configs/OCRTC.h          | 1 +
 include/configs/ORSG.h           | 1 +
 include/configs/PIP405.h         | 1 +
 include/configs/W7OLMC.h         | 1 +
 include/configs/W7OLMG.h         | 1 +
 include/configs/WUH405.h         | 1 +
 include/configs/csb272.h         | 1 +
 include/configs/csb472.h         | 1 +
 include/configs/netstal-common.h | 2 +-
 include/configs/sbc405.h         | 1 +
 18 files changed, 18 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/AR405.h b/include/configs/AR405.h
index 9f19269574e..73e34bdab26 100644
--- a/include/configs/AR405.h
+++ b/include/configs/AR405.h
@@ -71,6 +71,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h
index 32637125343..b2679e58786 100644
--- a/include/configs/CPCIISER4.h
+++ b/include/configs/CPCIISER4.h
@@ -54,6 +54,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h
index 150bd29e00e..96bf161aa15 100644
--- a/include/configs/CRAYL1.h
+++ b/include/configs/CRAYL1.h
@@ -45,6 +45,7 @@
 #define	CONFIG_PHY_ADDR		1	/* PHY address; handling of ENET */
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* early setup for 405gp */
 #define CONFIG_MISC_INIT_R	1	/* so that a misc_init_r() is called */
+#define CONFIG_NET_MULTI
 
 /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
  * keep possible initrd ramdisk decompression out.  This is in k (1024 bytes)
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
index 201e62aa04d..023f33e1ebd 100644
--- a/include/configs/ERIC.h
+++ b/include/configs/ERIC.h
@@ -96,6 +96,7 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/EXBITGEN.h b/include/configs/EXBITGEN.h
index 4729464f21e..4d082433988 100644
--- a/include/configs/EXBITGEN.h
+++ b/include/configs/EXBITGEN.h
@@ -81,6 +81,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
index 0e7d2c01039..ea502d42cd0 100644
--- a/include/configs/HUB405.h
+++ b/include/configs/HUB405.h
@@ -60,6 +60,7 @@
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index 8aca1f941db..80c70e48869 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -135,6 +135,7 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h
index a3869c8747b..8315cfe62ba 100644
--- a/include/configs/MIP405.h
+++ b/include/configs/MIP405.h
@@ -341,6 +341,7 @@
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this */
 #define CONFIG_PHY_CMD_DELAY	40	/* Intel LXT971A needs this */
+#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index 2591f1deddd..860ec529216 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -54,6 +54,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h
index 13d6e0496f9..b2e2d41f2b0 100644
--- a/include/configs/ORSG.h
+++ b/include/configs/ORSG.h
@@ -54,6 +54,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 
 /*
diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h
index 5c4d69b207b..e214d70a580 100644
--- a/include/configs/PIP405.h
+++ b/include/configs/PIP405.h
@@ -281,6 +281,7 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
+#define CONFIG_NET_MULTI
 /************************************************************
  * RTC
  ***********************************************************/
diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h
index ceef76eeaf6..553845d6d98 100644
--- a/include/configs/W7OLMC.h
+++ b/include/configs/W7OLMC.h
@@ -68,6 +68,7 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1		/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0		/* PHY address			*/
+#define CONFIG_NET_MULTI
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 
diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h
index 11e063010b0..73d6d24b61d 100644
--- a/include/configs/W7OLMG.h
+++ b/include/configs/W7OLMG.h
@@ -68,6 +68,7 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1		/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0		/* PHY address			*/
+#define CONFIG_NET_MULTI
 
 #define CONFIG_RTC_M48T35A	1		/* ST Electronics M48 timekeeper */
 #define CONFIG_DTT_LM75     1                /* ON Semi's LM75 */
diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h
index 99188bc34da..5c281a1a663 100644
--- a/include/configs/WUH405.h
+++ b/include/configs/WUH405.h
@@ -58,6 +58,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
+#define CONFIG_NET_MULTI
 
 #define CONFIG_PHY_CLK_FREQ	EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 
diff --git a/include/configs/csb272.h b/include/configs/csb272.h
index 204aea0e825..aed6f50f983 100644
--- a/include/configs/csb272.h
+++ b/include/configs/csb272.h
@@ -184,6 +184,7 @@
 #define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
 					/* 32usec min. for LXT971A	*/
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+#define CONFIG_NET_MULTI
 
 /*
  * RTC configuration
diff --git a/include/configs/csb472.h b/include/configs/csb472.h
index 9b3a11c1ac8..24b961f3e13 100644
--- a/include/configs/csb472.h
+++ b/include/configs/csb472.h
@@ -183,6 +183,7 @@
 #define CONFIG_PHY_CMD_DELAY	40	/* PHY COMMAND delay		*/
 					/* 32usec min. for LXT971A	*/
 #define CONFIG_PHY_RESET_DELAY	300	/* PHY RESET recovery delay	*/
+#define CONFIG_NET_MULTI
 
 /*
  * RTC configuration
diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h
index 4d5c1ab3435..4bed7ae2673 100644
--- a/include/configs/netstal-common.h
+++ b/include/configs/netstal-common.h
@@ -61,8 +61,8 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII			/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#if defined(CONFIG_440)
 #define CONFIG_NET_MULTI	1
+#if defined(CONFIG_440)
 #define CONFIG_NETCONSOLE		/* include NetConsole support	*/
 #define CONFIG_SYS_RX_ETH_BUFFER	32	/* number of eth rx buffers	*/
 #else
diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h
index 7197aaf7922..242f42fdc32 100644
--- a/include/configs/sbc405.h
+++ b/include/configs/sbc405.h
@@ -62,6 +62,7 @@
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_PHY_RESET_DELAY	300	/* Intel LXT971A needs this	*/
+#define CONFIG_NET_MULTI
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"bootargs=emac(0,0)host:/T221ppc/target/config/sbc405/vxWorks.st " \
-- 
cgit v1.3.1


From d873133f2ba9bd613d5f6552c31cc70fb13f15d3 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 11 May 2009 13:46:14 +0200
Subject: ppc4xx: Add Sequoia RAM-booting target

This patch adds another build target for the AMCC Sequoia PPC440EPx
eval board. This RAM-booting version is targeted for boards without
NOR FLASH (NAND booting) which need a possibility to initially
program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000)
configured to setup the SDRAM, this debugger can load this RAM-
booting image to the target address in SDRAM (in this case 0x1000000)
and start it there. Then U-Boot's standard NAND commands can be
used to program the NAND FLASH (e.g. "nand write ...").

Here the commands to load and start this image from the BDI2000:

440EPX>reset halt
440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin
440EPX>go 0x1000000

Please note that this image automatically scans for an already
initialized SDRAM TLB (detected by EPN=0). This TLB will not be
cleared. This TLB doesn't need to be TLB #0, this RAM-booting
version will detect it and preserve it. So booting via BDI2000
will work and booting with a complete different TLB init via
U-Boot works as well.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 Makefile                          |  11 ++++
 board/amcc/sequoia/init.S         |   7 +++
 board/amcc/sequoia/sdram.c        |   3 +-
 board/amcc/sequoia/sequoia.c      |  10 ++-
 board/amcc/sequoia/u-boot-ram.lds | 126 ++++++++++++++++++++++++++++++++++++++
 cpu/ppc4xx/start.S                |  33 ++++++++--
 include/configs/amcc-common.h     |  11 ++++
 include/configs/sequoia.h         |  30 ++++++---
 8 files changed, 215 insertions(+), 16 deletions(-)
 create mode 100644 board/amcc/sequoia/u-boot-ram.lds

(limited to 'include')

diff --git a/Makefile b/Makefile
index 4983c0e71b9..10f6b1f49fc 100644
--- a/Makefile
+++ b/Makefile
@@ -1533,6 +1533,17 @@ rainier_nand_config: unconfig
 	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
 	@echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk
 
+sequoia_ramboot_config \
+rainier_ramboot_config: unconfig
+	@mkdir -p $(obj)include $(obj)board/amcc/sequoia
+	@echo "#define CONFIG_SYS_RAMBOOT" > $(obj)include/config.h
+	@echo "#define CONFIG_$$(echo $(subst ,,$(@:_config=)) | \
+		tr '[:lower:]' '[:upper:]')" >> $(obj)include/config.h
+	@$(MKCONFIG) -n $@ -a sequoia ppc ppc4xx sequoia amcc
+	@echo "TEXT_BASE = 0x01000000" > $(obj)board/amcc/sequoia/config.tmp
+	@echo "LDSCRIPT = board/amcc/sequoia/u-boot-ram.lds" >> \
+		$(obj)board/amcc/sequoia/config.tmp
+
 taihu_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc ppc4xx taihu amcc
 
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 4452d26cd32..3c0e400f953 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -43,12 +43,19 @@ tlbtab:
 	/* vxWorks needs this as first entry for the Machine Check interrupt */
 	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 
+	/*
+	 * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
+	 * entry is already configured for SDRAM via the JTAG debugger and mustn't
+	 * be re-initialized by this RAM-booting U-Boot version.
+	 */
+#ifndef CONFIG_SYS_RAMBOOT
 	/* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
 	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
 #else
 	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/* TLB-entry for EBC */
 	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 6df4c6d9b36..bde471c2efc 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -54,7 +54,8 @@ extern void denali_core_search_data_eye(void);
  ************************************************************************/
 phys_size_t initdram (int board_type)
 {
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+    defined(CONFIG_NAND_SPL)
 	ulong speed = get_bus_freq(0);
 
 	mtsdram(DDR0_02, 0x00000000);
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index e824b8fa4a9..246ad948439 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -33,7 +33,9 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if !defined(CONFIG_SYS_NO_FLASH)
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
+#endif
 
 extern void __ft_board_setup(void *blob, bd_t *bd);
 ulong flash_get_size(ulong base, int banknum);
@@ -122,16 +124,19 @@ int board_early_init_f(void)
 
 int misc_init_r(void)
 {
+#if !defined(CONFIG_SYS_NO_FLASH)
 	uint pbcr;
 	int size_val = 0;
-	u32 reg;
+#endif
 #ifdef CONFIG_440EPX
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
 	char *act = getenv("usbact");
 #endif
+	u32 reg;
 
+#if !defined(CONFIG_SYS_NO_FLASH)
 	/* Re-do flash sizing to get full correct info */
 
 	/* adjust flash start and offset */
@@ -171,6 +176,7 @@ int misc_init_r(void)
 			    CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 			    &flash_info[0]);
 #endif
+#endif /* CONFIG_SYS_NO_FLASH */
 
 	/*
 	 * USB suff...
@@ -515,7 +521,7 @@ int post_hotkeys_pressed(void)
 }
 #endif /* CONFIG_POST */
 
-#if defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 /*
  * On NAND-booting sequoia, we need to patch the chips select numbers
  * in the dtb (CS0 - NAND, CS3 - NOR)
diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds
new file mode 100644
index 00000000000..9393b651787
--- /dev/null
+++ b/board/amcc/sequoia/u-boot-ram.lds
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2009
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    cpu/ppc4xx/start.o	(.text)
+
+    *(.text)
+    *(.fixup)
+    *(.got1)
+  }
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata    :
+  {
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  }
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
+  __fixup_entries = (. - _FIXUP_TABLE_)>>2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+   . = ALIGN(4);
+  }
+
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S
index f2b8908b90b..ac96fc28f77 100644
--- a/cpu/ppc4xx/start.S
+++ b/cpu/ppc4xx/start.S
@@ -257,6 +257,14 @@
 	bl	board_init_f
 #endif
 
+#if defined(CONFIG_SYS_RAMBOOT)
+	/*
+	 * 4xx RAM-booting U-Boot image is started from offset 0
+	 */
+	.text
+	bl	_start_440
+#endif
+
 /*
  * 440 Startup -- on reset only the top 4k of the effective
  * address space is mapped in by an entry in the instruction
@@ -444,10 +452,17 @@ skip_debug_init:
 	addis	r0,0,0x0000
 	li	r1,0x003f	/* 64 TLB entries */
 	mtctr	r1
-rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
-	tlbwe	r0,r1,0x0001
-	tlbwe	r0,r1,0x0002
-	subi	r1,r1,0x0001
+	li	r4,0		/* Start with TLB #0 */
+rsttlb:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 to get EPN */
+	rlwinm.	r3,r3,0,0xfffffc00	/* Mask EPN */
+	beq	tlbnxt		/* Skip EPN=0 TLB, this is the SDRAM TLB */
+#endif
+	tlbwe	r0,r4,0		/* Invalidate all entries (V=0)*/
+	tlbwe	r0,r4,1
+	tlbwe	r0,r4,2
+tlbnxt:	addi	r4,r4,1		/* Next TLB */
 	bdnz	rsttlb
 
 	/*----------------------------------------------------------------*/
@@ -476,7 +491,13 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	li	r4,0		/* TLB # */
 
 	addi	r5,r5,-4
-1:	lwzu	r0,4(r5)
+1:
+#ifdef CONFIG_SYS_RAMBOOT
+	tlbre	r3,r4,0		/* Read contents from TLB word #0 */
+	rlwinm.	r3,r3,0,0x00000200	/* Mask V (valid) bit */
+	bne	tlbnx2		/* Skip V=1 TLB, this is the SDRAM TLB */
+#endif
+	lwzu	r0,4(r5)
 	cmpwi	r0,0
 	beq	2f		/* 0 marks end */
 	lwzu	r1,4(r5)
@@ -484,7 +505,7 @@ rsttlb:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	tlbwe	r0,r4,0		/* TLB Word 0 */
 	tlbwe	r1,r4,1		/* TLB Word 1 */
 	tlbwe	r2,r4,2		/* TLB Word 2 */
-	addi	r4,r4,1		/* Next TLB */
+tlbnx2:	addi	r4,r4,1		/* Next TLB */
 	bdnz	1b
 
 	/*----------------------------------------------------------------*/
diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h
index d3dc3e53367..3b733c03eeb 100644
--- a/include/configs/amcc-common.h
+++ b/include/configs/amcc-common.h
@@ -76,6 +76,17 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 
+#if defined(CONFIG_SYS_RAMBOOT)
+/*
+ * Disable NOR FLASH commands on RAM-booting version. One main reason for this
+ * RAM-booting version is boards with NAND and without NOR. This image can
+ * be used for initial NAND programming.
+ */
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#endif
+
 /*
  * Miscellaneous configurable options
  */
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index fa226b28cb5..89acacc7f6d 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -112,13 +112,26 @@
 /*
  * Environment
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environ vars	*/
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
+#define CONFIG_ENV_IS_IN_NAND		/* use NAND for environ vars	*/
+#define CONFIG_ENV_IS_EMBEDDED		/* use embedded environment	*/
+#elif defined(CONFIG_SYS_RAMBOOT)
+#define CONFIG_ENV_IS_NOWHERE		/* Store env in memory only	*/
+#define CONFIG_ENV_SIZE		(8 << 10)
+/*
+ * In RAM-booting version, we have no environment storage. So we need to
+ * provide at least preliminary MAC addresses for the 4xx EMAC driver to
+ * register the interfaces. Those two addresses are generated via the
+ * tools/gen_eth_addr tool and should only be used in a closed laboratory
+ * environment.
+ */
+#define	CONFIG_ETHADDR		4a:56:49:22:3e:43
+#define	CONFIG_ETH1ADDR		02:93:53:d5:06:98
 #else
-#define CONFIG_ENV_IS_IN_NAND	1	/* use NAND for environ vars	*/
-#define CONFIG_ENV_IS_EMBEDDED	1	/* use embedded environment	*/
+#define CONFIG_ENV_IS_IN_FLASH		/* use FLASH for environ vars	*/
 #endif
 
+#if defined(CONFIG_CMD_FLASH)
 /*
  * FLASH related
  */
@@ -148,6 +161,7 @@
 #define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
 #endif
+#endif /* CONFIG_CMD_FLASH */
 
 /*
  * IPL (Initial Program Loader, integrated inside CPU)
@@ -211,7 +225,8 @@
  * DDR SDRAM
  */
 #define CONFIG_SYS_MBYTES_SDRAM        (256)	/* 256MB			*/
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
+    !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_DDR_DATA_EYE		/* use DDR2 optimization	*/
 #endif
 #define CONFIG_SYS_MEM_TOP_HIDE	(4 << 10) /* don't use last 4kbytes	*/
@@ -306,7 +321,7 @@
  * overwrite part of the U-Boot image which is already loaded from NAND
  * to SDRAM.
  */
-#if defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_POST_MEMORY_ON	0
 #else
 #define CONFIG_SYS_POST_MEMORY_ON	CONFIG_SYS_POST_MEMORY
@@ -354,7 +369,8 @@
 /*
  * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
  */
-#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
+#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
+    !defined(CONFIG_SYS_RAMBOOT)
 #define CONFIG_SYS_NAND_CS		3	/* NAND chip connected to CSx	*/
 /* Memory Bank 0 (NOR-FLASH) initialization				*/
 #define CONFIG_SYS_EBC_PB0AP		0x03017200
-- 
cgit v1.3.1


From 7b7808ae6dace59287f565e9323cda7b098a5612 Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 15 May 2009 23:44:06 +0200
Subject: davinci: move psc support board-->cpu

Move DaVinci PSC support from board/* to cpu/* where it belongs.
The PSC module manages clocks and resets for all DaVinci-family
SoCs, and isn't at all board-specific.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 board/davinci/common/Makefile           |   2 +-
 board/davinci/common/psc.c              | 182 --------------------------------
 board/davinci/common/psc.h              |  32 ------
 board/davinci/dvevm/dvevm.c             |   1 -
 board/davinci/schmoogie/schmoogie.c     |   1 -
 board/davinci/sffsdr/sffsdr.c           |   1 -
 board/davinci/sonata/sonata.c           |   1 -
 cpu/arm926ejs/davinci/Makefile          |   2 +-
 cpu/arm926ejs/davinci/psc.c             | 182 ++++++++++++++++++++++++++++++++
 include/asm-arm/arch-davinci/hardware.h |   8 ++
 10 files changed, 192 insertions(+), 220 deletions(-)
 delete mode 100644 board/davinci/common/psc.c
 delete mode 100644 board/davinci/common/psc.h
 create mode 100644 cpu/arm926ejs/davinci/psc.c

(limited to 'include')

diff --git a/board/davinci/common/Makefile b/board/davinci/common/Makefile
index 127bb6ede9f..8d9ea00ddc3 100644
--- a/board/davinci/common/Makefile
+++ b/board/davinci/common/Makefile
@@ -29,7 +29,7 @@ endif
 
 LIB	= $(obj)lib$(VENDOR).a
 
-COBJS	:= psc.o misc.o
+COBJS	:= misc.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c
deleted file mode 100644
index 28e2a4b5b6c..00000000000
--- a/board/davinci/common/psc.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * Power and Sleep Controller (PSC) functions.
- *
- * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- * Copyright (C) 2004 Texas Instruments.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
-/*
- * The DM6446 includes two separate power domains: "Always On" and "DSP". The
- * "Always On" power domain is always on when the chip is on. The "Always On"
- * domain is powered by the VDD pins of the DM6446. The majority of the
- * DM6446's modules lie within the "Always On" power domain. A separate
- * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
- * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
- * the DM6446.
- */
-
-/* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
-{
-	dv_reg_p mdstat, mdctl;
-
-	if (id >= DAVINCI_LPSC_GEM)
-		return;			/* Don't work on DSP Power Domain */
-
-	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
-	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
-
-	while (REG(PSC_PTSTAT) & 0x01);
-
-	if ((*mdstat & 0x1f) == 0x03)
-		return;			/* Already on and enabled */
-
-	*mdctl |= 0x03;
-
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
-	switch (id) {
-	case DAVINCI_LPSC_VPSSSLV:
-	case DAVINCI_LPSC_EMAC:
-	case DAVINCI_LPSC_EMAC_WRAPPER:
-	case DAVINCI_LPSC_MDIO:
-	case DAVINCI_LPSC_USB:
-	case DAVINCI_LPSC_ATA:
-	case DAVINCI_LPSC_VLYNQ:
-	case DAVINCI_LPSC_UHPI:
-	case DAVINCI_LPSC_DDR_EMIF:
-	case DAVINCI_LPSC_AEMIF:
-	case DAVINCI_LPSC_MMC_SD:
-	case DAVINCI_LPSC_MEMSTICK:
-	case DAVINCI_LPSC_McBSP:
-	case DAVINCI_LPSC_GPIO:
-		*mdctl |= 0x200;
-		break;
-	}
-
-	REG(PSC_PTCMD) = 0x01;
-
-	while (REG(PSC_PTSTAT) & 0x03);
-	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
-}
-
-/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CONFIG_SYS_USE_DSPLINK)
-void dsp_on(void)
-{
-	int i;
-
-	if (REG(PSC_PDSTAT1) & 0x1f)
-		return;			/* Already on */
-
-	REG(PSC_GBLCTL) |= 0x01;
-	REG(PSC_PDCTL1) |= 0x01;
-	REG(PSC_PDCTL1) &= ~0x100;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
-	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
-	REG(PSC_PTCMD) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (REG(PSC_EPCPR) & 0x02)
-			break;
-	}
-
-	REG(PSC_CHP_SHRTSW) = 0x01;
-	REG(PSC_PDCTL1) |= 0x100;
-	REG(PSC_EPCCR) = 0x02;
-
-	for (i = 0; i < 100; i++) {
-		if (!(REG(PSC_PTSTAT) & 0x02))
-			break;
-	}
-
-	REG(PSC_GBLCTL) &= ~0x1f;
-}
-#endif /* CONFIG_SYS_USE_DSPLINK */
-
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x0000e003;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h
deleted file mode 100644
index b2dd7b56d47..00000000000
--- a/board/davinci/common/psc.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __PSC_H
-#define __PSC_H
-
-void lpsc_on(unsigned int id);
-void dsp_on(void);
-void davinci_enable_uart0(void);
-void davinci_enable_emac(void);
-void davinci_enable_i2c(void);
-void davinci_errata_workarounds(void);
-
-#endif /* __PSC_H */
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index 22308deeb05..162a5dcea81 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -27,7 +27,6 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/arch/hardware.h>
-#include "../common/psc.h"
 #include "../common/misc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
index 433769a608b..d6dfef58174 100644
--- a/board/davinci/schmoogie/schmoogie.c
+++ b/board/davinci/schmoogie/schmoogie.c
@@ -27,7 +27,6 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/arch/hardware.h>
-#include "../common/psc.h"
 #include "../common/misc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
index e76f86d08cb..7d855fb8360 100644
--- a/board/davinci/sffsdr/sffsdr.c
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -30,7 +30,6 @@
 #include <common.h>
 #include <i2c.h>
 #include <asm/arch/hardware.h>
-#include "../common/psc.h"
 #include "../common/misc.h"
 
 #define DAVINCI_A3CR     (0x01E00014)	/* EMIF-A CS3 config register. */
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
index d56b443b202..155fb549c04 100644
--- a/board/davinci/sonata/sonata.c
+++ b/board/davinci/sonata/sonata.c
@@ -26,7 +26,6 @@
 
 #include <common.h>
 #include <asm/arch/hardware.h>
-#include "../common/psc.h"
 #include "../common/misc.h"
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index 7f51d177758..83708d8138a 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= timer.o ether.o lxt972.o dp83848.o
+COBJS	= timer.o ether.o lxt972.o dp83848.o psc.o
 SOBJS	= reset.o
 
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c
new file mode 100644
index 00000000000..28e2a4b5b6c
--- /dev/null
+++ b/cpu/arm926ejs/davinci/psc.c
@@ -0,0 +1,182 @@
+/*
+ * Power and Sleep Controller (PSC) functions.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+/*
+ * The DM6446 includes two separate power domains: "Always On" and "DSP". The
+ * "Always On" power domain is always on when the chip is on. The "Always On"
+ * domain is powered by the VDD pins of the DM6446. The majority of the
+ * DM6446's modules lie within the "Always On" power domain. A separate
+ * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
+ * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
+ * the DM6446.
+ */
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01);
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	switch (id) {
+	case DAVINCI_LPSC_VPSSSLV:
+	case DAVINCI_LPSC_EMAC:
+	case DAVINCI_LPSC_EMAC_WRAPPER:
+	case DAVINCI_LPSC_MDIO:
+	case DAVINCI_LPSC_USB:
+	case DAVINCI_LPSC_ATA:
+	case DAVINCI_LPSC_VLYNQ:
+	case DAVINCI_LPSC_UHPI:
+	case DAVINCI_LPSC_DDR_EMIF:
+	case DAVINCI_LPSC_AEMIF:
+	case DAVINCI_LPSC_MMC_SD:
+	case DAVINCI_LPSC_MEMSTICK:
+	case DAVINCI_LPSC_McBSP:
+	case DAVINCI_LPSC_GPIO:
+		*mdctl |= 0x200;
+		break;
+	}
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03);
+	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
+}
+
+/* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
+#if !defined(CONFIG_SYS_USE_DSPLINK)
+void dsp_on(void)
+{
+	int i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+#endif /* CONFIG_SYS_USE_DSPLINK */
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable EMAC. */
+	REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= PINMUX1_I2C;
+}
+
+void davinci_errata_workarounds(void)
+{
+	/*
+	 * Workaround for TMS320DM6446 errata 1.3.22:
+	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+	 *   Revision(s) Affected: 1.3 and earlier
+	 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/*
+	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+	 * as suggested in TMS320DM6446 errata 2.1.2:
+	 *
+	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+	 * low priority modules can occupy the bus and prevent high priority
+	 * modules like the VPSS from getting the required DDR2 throughput.
+	 * A hex value of 0x20 should provide a good ARM (cache enabled)
+	 * performance and still allow good utilization by the VPSS or other
+	 * modules.
+	 */
+	REG(VBPR) = 0x20;
+}
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index ebcdcfea1e9..3f6d4834b0c 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -133,6 +133,14 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_LPSC_GEM		39
 #define DAVINCI_LPSC_IMCOP		40
 
+void lpsc_on(unsigned int id);
+void dsp_on(void);
+
+void davinci_enable_uart0(void);
+void davinci_enable_emac(void);
+void davinci_enable_i2c(void);
+void davinci_errata_workarounds(void);
+
 /* Some PSC defines */
 #define PSC_CHP_SHRTSW			(0x01c40038)
 #define PSC_GBLCTL			(0x01c41010)
-- 
cgit v1.3.1


From f79043681ff44bae435c06f830e51e1546db7e19 Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 15 May 2009 23:44:08 +0200
Subject: davinci: split out some dm644x-specific bits from psc

Split out DaVinci DM6446-specific bits from more generic bits:

 - Add a CONFIG_SOC_DM644X.  All current boards use DM6446 chips;
   DM6443 and DM6441 chips differ in available peripherals.

 - Move most DM644X-specific bits from psc.c to a new dm644x.c file,
   which is conditionally built.  It provides device-specific setup.

Plus minor coding style and comment updates with respect to the PSC.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 cpu/arm926ejs/davinci/Makefile      |   1 +
 cpu/arm926ejs/davinci/dm644x.c      |  94 ++++++++++++++++++++++++++++++++
 cpu/arm926ejs/davinci/psc.c         | 103 ++++++++++--------------------------
 include/configs/davinci_dvevm.h     |   1 +
 include/configs/davinci_schmoogie.h |   1 +
 include/configs/davinci_sffsdr.h    |   1 +
 include/configs/davinci_sonata.h    |   1 +
 7 files changed, 127 insertions(+), 75 deletions(-)
 create mode 100644 cpu/arm926ejs/davinci/dm644x.c

(limited to 'include')

diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index e09874b08d8..6052e023303 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).a
 
 COBJS-y				+= timer.o psc.o
+COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
 
 SOBJS	= reset.o
diff --git a/cpu/arm926ejs/davinci/dm644x.c b/cpu/arm926ejs/davinci/dm644x.c
new file mode 100644
index 00000000000..df382bda23a
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm644x.c
@@ -0,0 +1,94 @@
+/*
+ * SoC-specific code for tms320dm644x chips
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ * Copyright (C) 2008 Lyrtech <www.lyrtech.com>
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+#define PINMUX0_EMACEN (1 << 31)
+#define PINMUX0_AECS5  (1 << 11)
+#define PINMUX0_AECS4  (1 << 10)
+
+#define PINMUX1_I2C    (1 <<  7)
+#define PINMUX1_UART1  (1 <<  1)
+#define PINMUX1_UART0  (1 <<  0)
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable EMAC. */
+	REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= PINMUX1_I2C;
+}
+
+void davinci_errata_workarounds(void)
+{
+	/*
+	 * Workaround for TMS320DM6446 errata 1.3.22:
+	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
+	 *   Revision(s) Affected: 1.3 and earlier
+	 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/*
+	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
+	 * as suggested in TMS320DM6446 errata 2.1.2:
+	 *
+	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
+	 * low priority modules can occupy the bus and prevent high priority
+	 * modules like the VPSS from getting the required DDR2 throughput.
+	 * A hex value of 0x20 should provide a good ARM (cache enabled)
+	 * performance and still allow good utilization by the VPSS or other
+	 * modules.
+	 */
+	REG(VBPR) = 0x20;
+}
diff --git a/cpu/arm926ejs/davinci/psc.c b/cpu/arm926ejs/davinci/psc.c
index 28e2a4b5b6c..5bb972f186f 100644
--- a/cpu/arm926ejs/davinci/psc.c
+++ b/cpu/arm926ejs/davinci/psc.c
@@ -26,22 +26,22 @@
 #include <common.h>
 #include <asm/arch/hardware.h>
 
-#define PINMUX0_EMACEN (1 << 31)
-#define PINMUX0_AECS5  (1 << 11)
-#define PINMUX0_AECS4  (1 << 10)
-
-#define PINMUX1_I2C    (1 <<  7)
-#define PINMUX1_UART1  (1 <<  1)
-#define PINMUX1_UART0  (1 <<  0)
-
 /*
- * The DM6446 includes two separate power domains: "Always On" and "DSP". The
- * "Always On" power domain is always on when the chip is on. The "Always On"
- * domain is powered by the VDD pins of the DM6446. The majority of the
- * DM6446's modules lie within the "Always On" power domain. A separate
- * domain called the "DSP" domain houses the C64x+ and VICP. The "DSP" domain
- * is not always on. The "DSP" power domain is powered by the CVDDDSP pins of
- * the DM6446.
+ * The PSC manages three inputs to a "module" which may be a peripheral or
+ * CPU.  Those inputs are the module's:  clock; reset signal; and sometimes
+ * its power domain.  For our purposes, we only care whether clock and power
+ * are active, and the module is out of reset.
+ *
+ * DaVinci chips may include two separate power domains: "Always On" and "DSP".
+ * Chips without a DSP generally have only one domain.
+ *
+ * The "Always On" power domain is always on when the chip is on, and is
+ * powered by the VDD pins (on DM644X). The majority of DaVinci modules
+ * lie within the "Always On" power domain.
+ *
+ * A separate domain called the "DSP" domain houses the C64x+ and other video
+ * hardware such as VICP. In some chips, the "DSP" domain is not always on.
+ * The "DSP" power domain is powered by the CVDDDSP pins (on DM644X).
  */
 
 /* Works on Always On power domain only (no PD argument) */
@@ -55,15 +55,17 @@ void lpsc_on(unsigned int id)
 	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
 	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
 
-	while (REG(PSC_PTSTAT) & 0x01);
+	while (REG(PSC_PTSTAT) & 0x01)
+		continue;
 
 	if ((*mdstat & 0x1f) == 0x03)
 		return;			/* Already on and enabled */
 
 	*mdctl |= 0x03;
 
-	/* Special treatment for some modules as for sprue14 p.7.4.2 */
 	switch (id) {
+#ifdef CONFIG_SOC_DM644X
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
 	case DAVINCI_LPSC_VPSSSLV:
 	case DAVINCI_LPSC_EMAC:
 	case DAVINCI_LPSC_EMAC_WRAPPER:
@@ -80,14 +82,20 @@ void lpsc_on(unsigned int id)
 	case DAVINCI_LPSC_GPIO:
 		*mdctl |= 0x200;
 		break;
+#endif
 	}
 
 	REG(PSC_PTCMD) = 0x01;
 
-	while (REG(PSC_PTSTAT) & 0x03);
-	while ((*mdstat & 0x1f) != 0x03);	/* Probably an overkill... */
+	while (REG(PSC_PTSTAT) & 0x03)
+		continue;
+	while ((*mdstat & 0x1f) != 0x03)	/* Probably an overkill... */
+		continue;
 }
 
+/* Not all DaVinci chips have a DSP power domain. */
+#ifdef CONFIG_SOC_DM644X
+
 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
 #if !defined(CONFIG_SYS_USE_DSPLINK)
 void dsp_on(void)
@@ -124,59 +132,4 @@ void dsp_on(void)
 }
 #endif /* CONFIG_SYS_USE_DSPLINK */
 
-void davinci_enable_uart0(void)
-{
-	lpsc_on(DAVINCI_LPSC_UART0);
-
-	/* Bringup UART0 out of reset */
-	REG(UART0_PWREMU_MGMT) = 0x0000e003;
-
-	/* Enable UART0 MUX lines */
-	REG(PINMUX1) |= PINMUX1_UART0;
-}
-
-#ifdef CONFIG_DRIVER_TI_EMAC
-void davinci_enable_emac(void)
-{
-	lpsc_on(DAVINCI_LPSC_EMAC);
-	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
-	lpsc_on(DAVINCI_LPSC_MDIO);
-
-	/* Enable GIO3.3V cells used for EMAC */
-	REG(VDD3P3V_PWDN) = 0;
-
-	/* Enable EMAC. */
-	REG(PINMUX0) |= PINMUX0_EMACEN;
-}
-#endif
-
-void davinci_enable_i2c(void)
-{
-	lpsc_on(DAVINCI_LPSC_I2C);
-
-	/* Enable I2C pin Mux */
-	REG(PINMUX1) |= PINMUX1_I2C;
-}
-
-void davinci_errata_workarounds(void)
-{
-	/*
-	 * Workaround for TMS320DM6446 errata 1.3.22:
-	 *   PSC: PTSTAT Register Does Not Clear After Warm/Maximum Reset
-	 *   Revision(s) Affected: 1.3 and earlier
-	 */
-	REG(PSC_SILVER_BULLET) = 0;
-
-	/*
-	 * Set the PR_OLD_COUNT bits in the Bus Burst Priority Register (PBBPR)
-	 * as suggested in TMS320DM6446 errata 2.1.2:
-	 *
-	 * On DM6446 Silicon Revision 2.1 and earlier, under certain conditions
-	 * low priority modules can occupy the bus and prevent high priority
-	 * modules like the VPSS from getting the required DDR2 throughput.
-	 * A hex value of 0x20 should provide a good ARM (cache enabled)
-	 * performance and still allow good utilization by the VPSS or other
-	 * modules.
-	 */
-	REG(VBPR) = 0x20;
-}
+#endif /* have a DSP */
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 9fe4072b4b3..9be10f76cfa 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -59,6 +59,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index a16ac391b3f..d5e77f8e17b 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -34,6 +34,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*=============*/
 /* Memory Info */
 /*=============*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index c2ebd97dba1..4be5b7e4883 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -35,6 +35,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
 #define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index 0fc6012bace..a6bf8259bd0 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -59,6 +59,7 @@
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK		27000000	/* Timer Input clock freq */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM644X
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
-- 
cgit v1.3.1


From f1d944e30eb8ff89080fa03fb98d8fb5c82388d2 Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 15 May 2009 23:44:09 +0200
Subject: davinci: add basic dm355/dm350/dm335 support

Add some basic declarations for DaVinci DM355/DM350/DM335 support,
keyed on CONFIG_SOC_DM355.  (DM35X isn't quite right because the
DM357 is very different; while the DM355 is like a DM355 without
the MPEG/JPEG coprocessor).

These have different peripherals than the DM6446, and some of
the peripherals are at different addresses.  Notably for U-Boot,
there's no EMAC, and the NAND controller address is different

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 cpu/arm926ejs/davinci/Makefile          |  1 +
 cpu/arm926ejs/davinci/dm355.c           | 45 +++++++++++++++++++++++++++
 include/asm-arm/arch-davinci/hardware.h | 55 +++++++++++++++++++++++----------
 3 files changed, 84 insertions(+), 17 deletions(-)
 create mode 100644 cpu/arm926ejs/davinci/dm355.c

(limited to 'include')

diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index 6052e023303..480f19f557a 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -28,6 +28,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(SOC).a
 
 COBJS-y				+= timer.o psc.o
+COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
 
diff --git a/cpu/arm926ejs/davinci/dm355.c b/cpu/arm926ejs/davinci/dm355.c
new file mode 100644
index 00000000000..bc45b67fbeb
--- /dev/null
+++ b/cpu/arm926ejs/davinci/dm355.c
@@ -0,0 +1,45 @@
+/*
+ * SoC-specific code for tms320dm355 and similar chips
+ *
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+void davinci_enable_uart0(void)
+{
+	lpsc_on(DAVINCI_LPSC_UART0);
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x00006001;
+}
+
+
+#ifdef CONFIG_DRIVER_DAVINCI_I2C
+void davinci_enable_i2c(void)
+{
+	lpsc_on(DAVINCI_LPSC_I2C);
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX3) |= (1 << 20) | (1 << 19);
+}
+#endif
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index 3f6d4834b0c..a28cfb4ae09 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -44,13 +44,16 @@ typedef volatile unsigned int *	dv_reg_p;
 
 /*
  * Base register addresses
+ *
+ * NOTE:  some of these DM6446-specific addresses DO NOT WORK
+ * on other DaVinci chips.  Double check them before you try
+ * using the addresses ... or PSC module identifiers, etc.
  */
 #define DAVINCI_DMA_3PCC_BASE			(0x01c00000)
 #define DAVINCI_DMA_3PTC0_BASE			(0x01c10000)
 #define DAVINCI_DMA_3PTC1_BASE			(0x01c10400)
 #define DAVINCI_UART0_BASE			(0x01c20000)
 #define DAVINCI_UART1_BASE			(0x01c20400)
-#define DAVINCI_UART2_BASE			(0x01c20800)
 #define DAVINCI_I2C_BASE			(0x01c21000)
 #define DAVINCI_TIMER0_BASE			(0x01c21400)
 #define DAVINCI_TIMER1_BASE			(0x01c21800)
@@ -62,30 +65,41 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_PLL_CNTRL0_BASE			(0x01c40800)
 #define DAVINCI_PLL_CNTRL1_BASE			(0x01c40c00)
 #define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01c41000)
-#define DAVINCI_SYSTEM_DFT_BASE			(0x01c42000)
 #define DAVINCI_ARM_INTC_BASE			(0x01c48000)
-#define DAVINCI_IEEE1394_BASE			(0x01c60000)
 #define DAVINCI_USB_OTG_BASE			(0x01c64000)
 #define DAVINCI_CFC_ATA_BASE			(0x01c66000)
 #define DAVINCI_SPI_BASE			(0x01c66800)
 #define DAVINCI_GPIO_BASE			(0x01c67000)
-#define DAVINCI_UHPI_BASE			(0x01c67800)
 #define DAVINCI_VPSS_REGS_BASE			(0x01c70000)
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		(0x01c80000)
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	(0x01c81000)
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		(0x01c82000)
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		(0x01c84000)
-#define DAVINCI_IMCOP_BASE			(0x01cc0000)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		(0x01e00000)
-#define DAVINCI_VLYNQ_BASE			(0x01e01000)
-#define DAVINCI_MCBSP_BASE			(0x01e02000)
-#define DAVINCI_MMC_SD_BASE			(0x01e10000)
-#define DAVINCI_MS_BASE				(0x01e20000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#define DAVINCI_VLYNQ_REMOTE_BASE		(0x0c000000)
+
+#ifdef CONFIG_SOC_DM644X
+#define DAVINCI_UART2_BASE			0x01c20800
+#define DAVINCI_UHPI_BASE			0x01c67800
+#define DAVINCI_EMAC_CNTRL_REGS_BASE		0x01c80000
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	0x01c81000
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE		0x01c82000
+#define DAVINCI_MDIO_CNTRL_REGS_BASE		0x01c84000
+#define DAVINCI_IMCOP_BASE			0x01cc0000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e00000
+#define DAVINCI_VLYNQ_BASE			0x01e01000
+#define DAVINCI_ASP_BASE			0x01e02000
+#define DAVINCI_MMC_SD_BASE			0x01e10000
+#define DAVINCI_MS_BASE				0x01e20000
+#define DAVINCI_VLYNQ_REMOTE_BASE		0x0c000000
+
+#elif defined(CONFIG_SOC_DM355)
+#define DAVINCI_MMC_SD1_BASE			0x01e00000
+#define DAVINCI_ASP0_BASE			0x01e02000
+#define DAVINCI_ASP1_BASE			0x01e04000
+#define DAVINCI_UART2_BASE			0x01e06000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
+#define DAVINCI_MMC_SD0_BASE			0x01e11000
+
+#endif
 
 /* Power and Sleep Controller (PSC) Domains */
 #define DAVINCI_GPSC_ARMDOMAIN		0
@@ -168,7 +182,14 @@ void davinci_errata_workarounds(void);
 
 /* Miscellania... */
 #define VBPR				(0x20000020)
-#define PINMUX0				(0x01c40000)
-#define PINMUX1				(0x01c40004)
+
+/* NOTE:  system control modules are *highly* chip-specific, both
+ * as to register content (e.g. for muxing) and which registers exist.
+ */
+#define PINMUX0				0x01c40000
+#define PINMUX1				0x01c40004
+#define PINMUX2				0x01c40008
+#define PINMUX3				0x01c4000c
+#define PINMUX4				0x01c40010
 
 #endif /* __ASM_ARCH_HARDWARE_H */
-- 
cgit v1.3.1


From 8fc3bb4b0603516ad641e2de252a400b85fd869b Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri, 15 May 2009 23:45:20 +0200
Subject: arm: cleanup remaining CONFIG_INIT_CRITICAL

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/arm946es/start.S            | 4 +++-
 cpu/arm_intcm/start.S           | 4 +++-
 include/configs/SMN42.h         | 2 --
 include/configs/armadillo.h     | 2 +-
 include/configs/gcplus.h        | 2 +-
 include/configs/integratorap.h  | 2 +-
 include/configs/lpc2292sodimm.h | 2 --
 7 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'include')

diff --git a/cpu/arm946es/start.S b/cpu/arm946es/start.S
index 9375c76fd9f..627e3cb94db 100644
--- a/cpu/arm946es/start.S
+++ b/cpu/arm946es/start.S
@@ -133,7 +133,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -192,6 +192,7 @@ _start_armboot:
  */
 
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*
 	 * flush v4 I/D caches
@@ -217,6 +218,7 @@ cpu_init_crit:
 	bl	lowlevel_init	/* go setup memory */
 	mov	lr, ip		/* restore link */
 	mov	pc, lr		/* back to my caller */
+#endif
 /*
  *************************************************************************
  *
diff --git a/cpu/arm_intcm/start.S b/cpu/arm_intcm/start.S
index 00314613d53..bb1f003592a 100644
--- a/cpu/arm_intcm/start.S
+++ b/cpu/arm_intcm/start.S
@@ -131,7 +131,7 @@ reset:
 	 * we do sys-critical inits only at reboot,
 	 * not when booting from ram!
 	 */
-#ifdef CONFIG_INIT_CRITICAL
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 	bl	cpu_init_crit
 #endif
 
@@ -188,11 +188,13 @@ _start_armboot:
  *************************************************************************
  */
 
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
 cpu_init_crit:
 	/*  arm_int_generic assumes the ARM boot monitor, or user software,
 	 * has initialized the platform
 	 */
 	mov	pc, lr		/* back to my caller */
+#endif
 /*
  *************************************************************************
  *
diff --git a/include/configs/SMN42.h b/include/configs/SMN42.h
index 05f6d9fc1af..adb6ac52e12 100644
--- a/include/configs/SMN42.h
+++ b/include/configs/SMN42.h
@@ -30,8 +30,6 @@
  * If we are developing, we might want to start u-boot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-#undef CONFIG_INIT_CRITICAL		/* undef for developing */
-
 #undef CONFIG_SKIP_LOWLEVEL_INIT
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 
diff --git a/include/configs/armadillo.h b/include/configs/armadillo.h
index 7ba5e174e2d..f7eec276858 100644
--- a/include/configs/armadillo.h
+++ b/include/configs/armadillo.h
@@ -34,7 +34,7 @@
  * If we are developing, we might want to start armboot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-/*#define	CONFIG_INIT_CRITICAL*/		/* undef for developing */
+#undef  CONFIG_SKIP_LOWLEVEL_INIT
 
 /*
  * High Level Configuration Options
diff --git a/include/configs/gcplus.h b/include/configs/gcplus.h
index b2fbca2f3c2..85db4f5c773 100644
--- a/include/configs/gcplus.h
+++ b/include/configs/gcplus.h
@@ -36,7 +36,7 @@
  * e.g. bootp/tftp download of the kernel is a far more convenient
  * when testing new kernels on this target. However the ADS GCPlus Linux
  * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
- * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
+ * we use lowlevel_init (!CONFIG_SKIP_LOWLEVEL_INIT) to remedy that problem.
  */
 #undef  CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SKIP_RELOCATE_UBOOT	1
diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 38c024953ea..09270ff0a80 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -44,7 +44,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
 
-#undef CONFIG_INIT_CRITICAL
+#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_CM_INIT		1
 #define CONFIG_CM_REMAP		1
 #undef CONFIG_CM_SPD_DETECT
diff --git a/include/configs/lpc2292sodimm.h b/include/configs/lpc2292sodimm.h
index 15150387938..7ce8d6de1ff 100644
--- a/include/configs/lpc2292sodimm.h
+++ b/include/configs/lpc2292sodimm.h
@@ -30,8 +30,6 @@
  * If we are developing, we might want to start u-boot from ram
  * so we MUST NOT initialize critical regs like mem-timing ...
  */
-#undef CONFIG_INIT_CRITICAL		/* undef for developing */
-
 #undef CONFIG_SKIP_LOWLEVEL_INIT
 #undef CONFIG_SKIP_RELOCATE_UBOOT
 
-- 
cgit v1.3.1


From b54384e3ba6b5535751f317fcd3940a53eed0d3a Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri, 15 May 2009 23:47:02 +0200
Subject: arm: timer and interrupt init rework

actually the timer init use the interrupt_init as init callback
which make the interrupt and timer implementation difficult to follow

so now rename it as int timer_init(void) and use interrupt_init for interrupt

btw also remane the corresponding file to the functionnality implemented

as ixp arch implement two timer - one based on interrupt - so all the timer
related code is moved to timer.c

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 board/armltd/integratorap/integratorap.c |   2 +-
 board/armltd/integratorcp/integratorcp.c |   2 +-
 board/atmel/at91cap9adk/at91cap9adk.c    |   1 -
 board/davinci/common/misc.h              |   1 -
 board/m501sk/m501sk.c                    |   2 +-
 board/netstar/netstar.c                  |   2 +-
 board/voiceblue/voiceblue.c              |   2 +-
 cpu/arm1136/mx31/Makefile                |   3 +-
 cpu/arm1136/mx31/interrupts.c            | 171 -----------------------
 cpu/arm1136/mx31/timer.c                 | 170 +++++++++++++++++++++++
 cpu/arm1136/omap24xx/Makefile            |   3 +-
 cpu/arm1136/omap24xx/interrupts.c        | 159 ---------------------
 cpu/arm1136/omap24xx/timer.c             | 158 +++++++++++++++++++++
 cpu/arm1176/s3c64xx/Makefile             |   2 +-
 cpu/arm1176/s3c64xx/interrupts.c         | 177 ------------------------
 cpu/arm1176/s3c64xx/timer.c              | 177 ++++++++++++++++++++++++
 cpu/arm720t/interrupts.c                 |  46 ++++---
 cpu/arm920t/at91rm9200/Makefile          |   2 +-
 cpu/arm920t/at91rm9200/interrupts.c      | 160 ----------------------
 cpu/arm920t/at91rm9200/timer.c           | 160 ++++++++++++++++++++++
 cpu/arm920t/imx/Makefile                 |   4 +-
 cpu/arm920t/imx/interrupts.c             | 139 -------------------
 cpu/arm920t/imx/timer.c                  | 139 +++++++++++++++++++
 cpu/arm920t/ks8695/Makefile              |   3 +-
 cpu/arm920t/ks8695/interrupts.c          | 112 ---------------
 cpu/arm920t/ks8695/timer.c               | 108 +++++++++++++++
 cpu/arm920t/s3c24x0/Makefile             |   5 +-
 cpu/arm920t/s3c24x0/interrupts.c         | 228 -------------------------------
 cpu/arm920t/s3c24x0/timer.c              | 228 +++++++++++++++++++++++++++++++
 cpu/arm925t/Makefile                     |   5 +-
 cpu/arm925t/interrupts.c                 | 137 -------------------
 cpu/arm925t/timer.c                      | 137 +++++++++++++++++++
 cpu/arm926ejs/Makefile                   |   2 +-
 cpu/arm926ejs/interrupts.c               |  57 --------
 cpu/arm_cortexa8/omap3/Makefile          |   2 +-
 cpu/arm_cortexa8/omap3/interrupts.c      | 138 -------------------
 cpu/arm_cortexa8/omap3/timer.c           | 138 +++++++++++++++++++
 cpu/ixp/Makefile                         |   6 +-
 cpu/ixp/interrupts.c                     |  55 ++------
 cpu/ixp/timer.c                          |  54 ++++++++
 cpu/lh7a40x/Makefile                     |   2 +-
 cpu/lh7a40x/interrupts.c                 | 194 --------------------------
 cpu/lh7a40x/timer.c                      | 194 ++++++++++++++++++++++++++
 cpu/pxa/Makefile                         |   8 +-
 cpu/pxa/interrupts.c                     | 127 -----------------
 cpu/pxa/timer.c                          | 128 +++++++++++++++++
 cpu/s3c44b0/Makefile                     |   5 +-
 cpu/s3c44b0/interrupts.c                 | 136 ------------------
 cpu/s3c44b0/timer.c                      | 136 ++++++++++++++++++
 cpu/sa1100/Makefile                      |   4 +-
 cpu/sa1100/interrupts.c                  | 111 ---------------
 cpu/sa1100/timer.c                       | 110 +++++++++++++++
 include/asm-arm/u-boot-arm.h             |   3 +
 include/configs/ixdpg425.h               |   1 +
 include/configs/pdnb3.h                  |   1 +
 lib_arm/board.c                          |   3 +
 56 files changed, 2124 insertions(+), 2136 deletions(-)
 delete mode 100644 cpu/arm1136/mx31/interrupts.c
 create mode 100644 cpu/arm1136/mx31/timer.c
 delete mode 100644 cpu/arm1136/omap24xx/interrupts.c
 create mode 100644 cpu/arm1136/omap24xx/timer.c
 delete mode 100644 cpu/arm1176/s3c64xx/interrupts.c
 create mode 100644 cpu/arm1176/s3c64xx/timer.c
 delete mode 100644 cpu/arm920t/at91rm9200/interrupts.c
 create mode 100644 cpu/arm920t/at91rm9200/timer.c
 delete mode 100644 cpu/arm920t/imx/interrupts.c
 create mode 100644 cpu/arm920t/imx/timer.c
 delete mode 100644 cpu/arm920t/ks8695/interrupts.c
 create mode 100644 cpu/arm920t/ks8695/timer.c
 delete mode 100644 cpu/arm920t/s3c24x0/interrupts.c
 create mode 100644 cpu/arm920t/s3c24x0/timer.c
 delete mode 100644 cpu/arm925t/interrupts.c
 create mode 100644 cpu/arm925t/timer.c
 delete mode 100644 cpu/arm926ejs/interrupts.c
 delete mode 100644 cpu/arm_cortexa8/omap3/interrupts.c
 create mode 100644 cpu/arm_cortexa8/omap3/timer.c
 delete mode 100644 cpu/lh7a40x/interrupts.c
 create mode 100644 cpu/lh7a40x/timer.c
 delete mode 100644 cpu/pxa/interrupts.c
 create mode 100644 cpu/pxa/timer.c
 delete mode 100644 cpu/s3c44b0/interrupts.c
 create mode 100644 cpu/s3c44b0/timer.c
 delete mode 100644 cpu/sa1100/interrupts.c
 create mode 100644 cpu/sa1100/timer.c

(limited to 'include')

diff --git a/board/armltd/integratorap/integratorap.c b/board/armltd/integratorap/integratorap.c
index 9631967b071..5ececd64958 100644
--- a/board/armltd/integratorap/integratorap.c
+++ b/board/armltd/integratorap/integratorap.c
@@ -540,7 +540,7 @@ static ulong div_timer	 = 1;	/* Divisor to convert timer reading
  * - the Integrator/AP timer issues an interrupt
  *   each time it reaches zero
  */
-int interrupt_init (void)
+int timer_init (void)
 {
 	/* Load timer with initial value */
 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
diff --git a/board/armltd/integratorcp/integratorcp.c b/board/armltd/integratorcp/integratorcp.c
index 72629ce2b31..0d3afd8d244 100644
--- a/board/armltd/integratorcp/integratorcp.c
+++ b/board/armltd/integratorcp/integratorcp.c
@@ -163,7 +163,7 @@ static ulong timestamp;		/* U-Boot ticks since startup	      */
 
 /* starts up a counter
  * - the Integrator/CP timer can be set up to issue an interrupt */
-int interrupt_init (void)
+int timer_init (void)
 {
 	/* Load timer with initial value */
 	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index f52edaaa030..9f73df69033 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -61,7 +61,6 @@ static void at91cap9_slowclock_hw_init(void)
 	if (at91_sys_read(AT91_PMC_VER) == ARCH_ID_AT91CAP9_REVC) {
 		unsigned i, tmp = at91_sys_read(AT91_SCKCR);
 		if ((tmp & AT91CAP9_SCKCR_OSCSEL) == AT91CAP9_SCKCR_OSCSEL_RC) {
-			extern void timer_init(void);
 			timer_init();
 			tmp |= AT91CAP9_SCKCR_OSC32EN;
 			at91_sys_write(AT91_SCKCR, tmp);
diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h
index 4a57dbb89b6..5d29784403f 100644
--- a/board/davinci/common/misc.h
+++ b/board/davinci/common/misc.h
@@ -22,7 +22,6 @@
 #ifndef __MISC_H
 #define __MISC_H
 
-extern void timer_init(void);
 extern int eth_hw_init(void);
 
 void dv_display_clk_infos(void);
diff --git a/board/m501sk/m501sk.c b/board/m501sk/m501sk.c
index dc5b786c00b..1e6a6056722 100644
--- a/board/m501sk/m501sk.c
+++ b/board/m501sk/m501sk.c
@@ -127,7 +127,7 @@ int board_init(void)
 	m501sk_gpio_init();
 
 	/* Do interrupt init here, because flash needs timers */
-	interrupt_init();
+	timer_init();
 	flash_init();
 
 	return 0;
diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c
index ee4f2cdca7f..ffd60bfae0c 100644
--- a/board/netstar/netstar.c
+++ b/board/netstar/netstar.c
@@ -48,7 +48,7 @@ int dram_init(void)
 	/* Take the Ethernet controller out of reset and wait
 	 * for the EEPROM load to complete. */
 	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
-	udelay(10);	/* doesn't work before interrupt_init call */
+	udelay(10);	/* doesn't work before timer_init call */
 	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
 	udelay(500);
 
diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c
index c8dde3651e6..59b3310ae88 100644
--- a/board/voiceblue/voiceblue.c
+++ b/board/voiceblue/voiceblue.c
@@ -43,7 +43,7 @@ int dram_init(void)
 	/* Take the Ethernet controller out of reset and wait
 	 * for the EEPROM load to complete. */
 	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) |= 0x80;
-	udelay(10);	/* doesn't work before interrupt_init call */
+	udelay(10);	/* doesn't work before timer_init call */
 	*((volatile unsigned short *) GPIO_DATA_OUTPUT_REG) &= ~0x80;
 	udelay(500);
 
diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile
index 0e06f0a2b21..1e49e8d80f9 100644
--- a/cpu/arm1136/mx31/Makefile
+++ b/cpu/arm1136/mx31/Makefile
@@ -25,7 +25,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o generic.o
+COBJS	+= generic.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c
deleted file mode 100644
index ab7202fef2a..00000000000
--- a/cpu/arm1136/mx31/interrupts.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * (C) Copyright 2007
- * Sascha Hauer, Pengutronix
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/mx31-regs.h>
-#include <div64.h>
-
-#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
-
-/* General purpose timers registers */
-#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
-#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
-#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
-#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
-
-/* General purpose timers bitfields */
-#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
-#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
-#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
-#define GPTCR_TEN		1		/* Timer enable		*/
-
-static ulong timestamp;
-static ulong lastinc;
-
-/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
-#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
-/* ~0.4% error - measured with stop-watch on 100s boot-delay */
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, CONFIG_MX31_CLK32);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	time *= CONFIG_MX31_CLK32;
-	do_div(time, CONFIG_SYS_HZ);
-	return time;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * CONFIG_MX31_CLK32 + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-#else
-/* ~2% error */
-#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
-#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	do_div(tick, TICK_PER_TIME);
-	return tick;
-}
-
-static inline unsigned long long time_to_tick(unsigned long long time)
-{
-	return time * TICK_PER_TIME;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us += US_PER_TICK - 1;
-	do_div(us, US_PER_TICK);
-	return us;
-}
-#endif
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32768Hz 32-bit timer overruns in 131072 seconds */
-int interrupt_init (void)
-{
-	int i;
-
-	/* setup GP Timer 1 */
-	GPTCR = GPTCR_SWR;
-	for (i = 0; i < 100; i++)
-		GPTCR = 0; /* We have no udelay by now */
-	GPTPR = 0; /* 32Khz */
-	/* Freerun Mode, PERCLK1 input */
-	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
-
-	return 0;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastinc = GPTCNT; /* capture current incrementer value time */
-	timestamp = 0; /* start "advancing" time stamp from 0 */
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-unsigned long long get_ticks (void)
-{
-	ulong now = GPTCNT; /* current tick value */
-
-	if (now >= lastinc)	/* normal mode (non roll) */
-		/* move stamp forward with absolut diff ticks */
-		timestamp += (now - lastinc);
-	else			/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	/*
-	 * get_ticks() returns a long long (64 bit), it wraps in
-	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
-	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
-	 * 5 * 10^6 days - long enough.
-	 */
-	return tick_to_time(get_ticks());
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = time_to_tick(t);
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-}
-
-void reset_cpu (ulong addr)
-{
-	__REG16(WDOG_BASE) = 4;
-}
diff --git a/cpu/arm1136/mx31/timer.c b/cpu/arm1136/mx31/timer.c
new file mode 100644
index 00000000000..29b484e4482
--- /dev/null
+++ b/cpu/arm1136/mx31/timer.c
@@ -0,0 +1,170 @@
+/*
+ * (C) Copyright 2007
+ * Sascha Hauer, Pengutronix
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/mx31-regs.h>
+#include <div64.h>
+
+#define TIMER_BASE 0x53f90000 /* General purpose timer 1 */
+
+/* General purpose timers registers */
+#define GPTCR	__REG(TIMER_BASE)		/* Control register	*/
+#define GPTPR	__REG(TIMER_BASE + 0x4)		/* Prescaler register	*/
+#define GPTSR	__REG(TIMER_BASE + 0x8)		/* Status register	*/
+#define GPTCNT	__REG(TIMER_BASE + 0x24)	/* Counter register	*/
+
+/* General purpose timers bitfields */
+#define GPTCR_SWR		(1 << 15)	/* Software reset	*/
+#define GPTCR_FRR		(1 << 9)	/* Freerun / restart	*/
+#define GPTCR_CLKSOURCE_32	(4 << 6)	/* Clock source		*/
+#define GPTCR_TEN		1		/* Timer enable		*/
+
+static ulong timestamp;
+static ulong lastinc;
+
+/* "time" is measured in 1 / CONFIG_SYS_HZ seconds, "tick" is internal timer period */
+#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION
+/* ~0.4% error - measured with stop-watch on 100s boot-delay */
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, CONFIG_MX31_CLK32);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	time *= CONFIG_MX31_CLK32;
+	do_div(time, CONFIG_SYS_HZ);
+	return time;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * CONFIG_MX31_CLK32 + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+#else
+/* ~2% error */
+#define TICK_PER_TIME	((CONFIG_MX31_CLK32 + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ)
+#define US_PER_TICK	(1000000 / CONFIG_MX31_CLK32)
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	do_div(tick, TICK_PER_TIME);
+	return tick;
+}
+
+static inline unsigned long long time_to_tick(unsigned long long time)
+{
+	return time * TICK_PER_TIME;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us += US_PER_TICK - 1;
+	do_div(us, US_PER_TICK);
+	return us;
+}
+#endif
+
+/* The 32768Hz 32-bit timer overruns in 131072 seconds */
+int timer_init (void)
+{
+	int i;
+
+	/* setup GP Timer 1 */
+	GPTCR = GPTCR_SWR;
+	for (i = 0; i < 100; i++)
+		GPTCR = 0; /* We have no udelay by now */
+	GPTPR = 0; /* 32Khz */
+	/* Freerun Mode, PERCLK1 input */
+	GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
+
+	return 0;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = GPTCNT; /* capture current incrementer value time */
+	timestamp = 0; /* start "advancing" time stamp from 0 */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+unsigned long long get_ticks (void)
+{
+	ulong now = GPTCNT; /* current tick value */
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp forward with absolut diff ticks */
+		timestamp += (now - lastinc);
+	else			/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+	/*
+	 * get_ticks() returns a long long (64 bit), it wraps in
+	 * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+	 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
+	 * 5 * 10^6 days - long enough.
+	 */
+	return tick_to_time(get_ticks());
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = time_to_tick(t);
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+}
+
+void reset_cpu (ulong addr)
+{
+	__REG16(WDOG_BASE) = 4;
+}
diff --git a/cpu/arm1136/omap24xx/Makefile b/cpu/arm1136/omap24xx/Makefile
index f9afed72f66..2a79d9bbba3 100644
--- a/cpu/arm1136/omap24xx/Makefile
+++ b/cpu/arm1136/omap24xx/Makefile
@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o
 SOBJS	= start.o
 
+COBJS	= timer.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/arm1136/omap24xx/interrupts.c b/cpu/arm1136/omap24xx/interrupts.c
deleted file mode 100644
index a0c535dae8e..00000000000
--- a/cpu/arm1136/omap24xx/interrupts.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * (C) Copyright 2004
- * Texas Instruments
- * Richard Woodruff <r-woodruff2@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/bits.h>
-#include <asm/arch/omap2420.h>
-
-#define TIMER_LOAD_VAL 0
-
-/* macro to read the 32 bit timer */
-#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
-
-static ulong timestamp;
-static ulong lastinc;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
-	int32_t val;
-
-	/* Start the counter ticking up */
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
-	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
-	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
-
-	reset_timer_masked(); /* init the timestamp and lastinc value */
-
-	return(0);
-}
-/*
- * timer without interrupts
- */
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND perserve advance timstamp value */
-void udelay (unsigned long usec)
-{
-	ulong tmo, tmp;
-
-	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;			/* finish normalize. */
-	} else {					/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	tmp = get_timer (0);		/* get current timestamp */
-	if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
-		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
-	else
-		tmo	+= tmp;				/* else, set advancing stamp wake up time */
-	while (get_timer_masked () < tmo)/* loop till event */
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastinc = READ_TIMER;		/* capture current incrementer value time */
-	timestamp = 0;				/* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;		/* current tick value */
-
-	if (now >= lastinc)			/* normal mode (non roll) */
-		timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
-	else						/* we have rollover of incrementer */
-		timestamp += (0xFFFFFFFF - lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-/* waits specified delay value and resets timestamp */
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
-		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
-		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
-		tmo /= 1000;			/* finish normalize. */
-	} else {					/* else small number, don't kill it prior to HZ multiply */
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/cpu/arm1136/omap24xx/timer.c b/cpu/arm1136/omap24xx/timer.c
new file mode 100644
index 00000000000..8dd8d7b008d
--- /dev/null
+++ b/cpu/arm1136/omap24xx/timer.c
@@ -0,0 +1,158 @@
+/*
+ * (C) Copyright 2004
+ * Texas Instruments
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/bits.h>
+#include <asm/arch/omap2420.h>
+
+#define TIMER_LOAD_VAL 0
+
+/* macro to read the 32 bit timer */
+#define READ_TIMER (*((volatile ulong *)(CONFIG_SYS_TIMERBASE+TCRR)))
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+	int32_t val;
+
+	/* Start the counter ticking up */
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TLDR)) = TIMER_LOAD_VAL;	/* reload value on overflow*/
+	val = (CONFIG_SYS_PTV << 2) | BIT5 | BIT1 | BIT0;		/* mask to enable timer*/
+	*((int32_t *) (CONFIG_SYS_TIMERBASE + TCLR)) = val;	/* start timer */
+
+	reset_timer_masked(); /* init the timestamp and lastinc value */
+
+	return(0);
+}
+/*
+ * timer without interrupts
+ */
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds AND perserve advance timstamp value */
+void udelay (unsigned long usec)
+{
+	ulong tmo, tmp;
+
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	tmp = get_timer (0);		/* get current timestamp */
+	if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */
+		reset_timer_masked ();	/* reset "advancing" timestamp to 0, set lastinc value */
+	else
+		tmo	+= tmp;				/* else, set advancing stamp wake up time */
+	while (get_timer_masked () < tmo)/* loop till event */
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;		/* capture current incrementer value time */
+	timestamp = 0;				/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;		/* current tick value */
+
+	if (now >= lastinc)			/* normal mode (non roll) */
+		timestamp += (now - lastinc); /* move stamp fordward with absoulte diff ticks */
+	else						/* we have rollover of incrementer */
+		timestamp += (0xFFFFFFFF - lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+/* waits specified delay value and resets timestamp */
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {			/* if "big" number, spread normalization to seconds */
+		tmo = usec / 1000;		/* start to normalize for usec to ticks per sec */
+		tmo *= CONFIG_SYS_HZ;			/* find number of "ticks" to wait to achieve target */
+		tmo /= 1000;			/* finish normalize. */
+	} else {					/* else small number, don't kill it prior to HZ multiply */
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/cpu/arm1176/s3c64xx/Makefile b/cpu/arm1176/s3c64xx/Makefile
index fa4ee3f24e2..4656d9a8776 100644
--- a/cpu/arm1176/s3c64xx/Makefile
+++ b/cpu/arm1176/s3c64xx/Makefile
@@ -28,8 +28,8 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS-y	= interrupts.o
 COBJS-$(CONFIG_S3C6400)	+= cpu_init.o speed.o
+COBJS-y	+= timer.o
 
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
 
diff --git a/cpu/arm1176/s3c64xx/interrupts.c b/cpu/arm1176/s3c64xx/interrupts.c
deleted file mode 100644
index 7bb98486c57..00000000000
--- a/cpu/arm1176/s3c64xx/interrupts.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * (C) Copyright 2008
- * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/proc-armv/ptrace.h>
-#include <s3c6400.h>
-#include <div64.h>
-
-static ulong timer_load_val;
-
-#define PRESCALER	167
-
-static s3c64xx_timers *s3c64xx_get_base_timers(void)
-{
-	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
-}
-
-/* macro to read the 16 bit timer */
-static inline ulong read_timer(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	return timers->TCNTO4;
-}
-
-/* Internal tick units */
-/* Last decremneter snapshot */
-static unsigned long lastdec;
-/* Monotonic incrementing timer */
-static unsigned long long timestamp;
-
-int interrupt_init(void)
-{
-	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
-
-	/* use PWM Timer 4 because it has no output */
-	/*
-	 * We use the following scheme for the timer:
-	 * Prescaler is hard fixed at 167, divider at 1/4.
-	 * This gives at PCLK frequency 66MHz approx. 10us ticks
-	 * The timer is set to wrap after 100s, at 66MHz this obviously
-	 * happens after 10,000,000 ticks. A long variable can thus
-	 * keep values up to 40,000s, i.e., 11 hours. This should be
-	 * enough for most uses:-) Possible optimizations: select a
-	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
-	 * the prescaler automatically for other PCLK frequencies.
-	 */
-	timers->TCFG0 = PRESCALER << 8;
-	if (timer_load_val == 0) {
-		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
-		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timers->TCNTB4 = timer_load_val;
-	/* auto load, manual update of Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
-		TCON_4_UPDATE;
-
-	/* auto load, start Timer 4 */
-	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
-	timestamp = 0;
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	ulong now = read_timer();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	/* We overrun in 100s */
-	return (ulong)(timer_load_val / 100);
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time */
-	lastdec = read_timer();
-	timestamp = 0;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	unsigned long long res = get_ticks();
-	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
-	return res;
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
-}
-
-void udelay(unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = (usec + 9) / 10;
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)/* loop till event */
-		 /*NOP*/;
-}
diff --git a/cpu/arm1176/s3c64xx/timer.c b/cpu/arm1176/s3c64xx/timer.c
new file mode 100644
index 00000000000..22a5b77701f
--- /dev/null
+++ b/cpu/arm1176/s3c64xx/timer.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2003
+ * Texas Instruments <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002-2004
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * (C) Copyright 2004
+ * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
+ *
+ * (C) Copyright 2008
+ * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/proc-armv/ptrace.h>
+#include <s3c6400.h>
+#include <div64.h>
+
+static ulong timer_load_val;
+
+#define PRESCALER	167
+
+static s3c64xx_timers *s3c64xx_get_base_timers(void)
+{
+	return (s3c64xx_timers *)ELFIN_TIMER_BASE;
+}
+
+/* macro to read the 16 bit timer */
+static inline ulong read_timer(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	return timers->TCNTO4;
+}
+
+/* Internal tick units */
+/* Last decremneter snapshot */
+static unsigned long lastdec;
+/* Monotonic incrementing timer */
+static unsigned long long timestamp;
+
+int timer_init(void)
+{
+	s3c64xx_timers *const timers = s3c64xx_get_base_timers();
+
+	/* use PWM Timer 4 because it has no output */
+	/*
+	 * We use the following scheme for the timer:
+	 * Prescaler is hard fixed at 167, divider at 1/4.
+	 * This gives at PCLK frequency 66MHz approx. 10us ticks
+	 * The timer is set to wrap after 100s, at 66MHz this obviously
+	 * happens after 10,000,000 ticks. A long variable can thus
+	 * keep values up to 40,000s, i.e., 11 hours. This should be
+	 * enough for most uses:-) Possible optimizations: select a
+	 * binary-friendly frequency, e.g., 1ms / 128. Also calculate
+	 * the prescaler automatically for other PCLK frequencies.
+	 */
+	timers->TCFG0 = PRESCALER << 8;
+	if (timer_load_val == 0) {
+		timer_load_val = get_PCLK() / PRESCALER * (100 / 4); /* 100s */
+		timers->TCFG1 = (timers->TCFG1 & ~0xf0000) | 0x20000;
+	}
+
+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO |
+		TCON_4_UPDATE;
+
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x00700000) | TCON_4_AUTO | COUNT_4_ON;
+	timestamp = 0;
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	ulong now = read_timer();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	/* We overrun in 100s */
+	return (ulong)(timer_load_val / 100);
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	lastdec = read_timer();
+	timestamp = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	unsigned long long res = get_ticks();
+	do_div (res, (timer_load_val / (100 * CONFIG_SYS_HZ)));
+	return res;
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t * (timer_load_val / (100 * CONFIG_SYS_HZ));
+}
+
+void udelay(unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = (usec + 9) / 10;
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)/* loop till event */
+		 /*NOP*/;
+}
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index 39ed345bb76..ff21314d8e2 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -110,9 +110,34 @@ static void timer_isr( void *data) {
 static ulong timestamp;
 static ulong lastdec;
 
+#if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
 int interrupt_init (void)
 {
+	int i;
+
+	/* install default interrupt handlers */
+	for ( i = 0; i < N_IRQS; i++) {
+		IRQ_HANDLER[i].m_data = (void *)i;
+		IRQ_HANDLER[i].m_func = default_isr;
+	}
+
+	/* configure interrupts for IRQ mode */
+	PUT_REG( REG_INTMODE, 0x0);
+	/* clear any pending interrupts */
+	PUT_REG( REG_INTPEND, 0x1FFFFF);
+
+	lastdec = 0;
+
+	/* install interrupt handler for timer */
+	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
+	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
+
+	return 0;
+}
+#endif
 
+int timer_init (void)
+{
 #if defined(CONFIG_NETARM)
 	/* disable all interrupts */
 	IRQEN = 0;
@@ -137,25 +162,6 @@ int interrupt_init (void)
 	/* set timer 1 counter */
 	lastdec = IO_TC1D = TIMER_LOAD_VAL;
 #elif defined(CONFIG_S3C4510B)
-	int i;
-
-	/* install default interrupt handlers */
-	for ( i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* configure interrupts for IRQ mode */
-	PUT_REG( REG_INTMODE, 0x0);
-	/* clear any pending interrupts */
-	PUT_REG( REG_INTPEND, 0x1FFFFF);
-
-	lastdec = 0;
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[INT_TIMER0].m_data = (void *)&timestamp;
-	IRQ_HANDLER[INT_TIMER0].m_func = timer_isr;
-
 	/* configure free running timer 0 */
 	PUT_REG( REG_TMOD, 0x0);
 	/* Stop timer 0 */
@@ -187,7 +193,7 @@ int interrupt_init (void)
 	PUT32(T0TCR, 1);	/* enable timer0 */
 
 #else
-#error No interrupt_init() defined for this CPU type
+#error No timer_init() defined for this CPU type
 #endif
 	timestamp = 0;
 
diff --git a/cpu/arm920t/at91rm9200/Makefile b/cpu/arm920t/at91rm9200/Makefile
index 161ca9492fc..73aeeac39de 100644
--- a/cpu/arm920t/at91rm9200/Makefile
+++ b/cpu/arm920t/at91rm9200/Makefile
@@ -31,10 +31,10 @@ COBJS	+= bcm5221.o
 COBJS	+= dm9161.o
 COBJS	+= ether.o
 COBJS	+= i2c.o
-COBJS	+= interrupts.o
 COBJS	+= lxt972.o
 COBJS	+= reset.o
 COBJS	+= spi.o
+COBJS	+= timer.o
 COBJS	+= usb.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm920t/at91rm9200/interrupts.c b/cpu/arm920t/at91rm9200/interrupts.c
deleted file mode 100644
index 4c38a9a0c8d..00000000000
--- a/cpu/arm920t/at91rm9200/interrupts.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-/*#include <asm/io.h>*/
-#include <asm/arch/hardware.h>
-/*#include <asm/proc/ptrace.h>*/
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
-AT91PS_TC tmr;
-
-static ulong timestamp;
-static ulong lastinc;
-
-int interrupt_init (void)
-{
-	tmr = AT91C_BASE_TC0;
-
-	/* enables TC1.0 clock */
-	*AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
-
-	*AT91C_TCB0_BCR = 0;
-	*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
-	tmr->TC_CCR = AT91C_TC_CLKDIS;
-#define AT91C_TC_CMR_CPCTRG (1 << 14)
-	/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
-	tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
-
-	tmr->TC_IDR = ~0ul;
-	tmr->TC_RC = TIMER_LOAD_VAL;
-	lastinc = 0;
-	tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastinc = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_raw (void)
-{
-	ulong now = READ_TIMER;
-
-	if (now >= lastinc) {
-		/* normal mode */
-		timestamp += now - lastinc;
-	} else {
-		/* we have an overflow ... */
-		timestamp += now + TIMER_LOAD_VAL - lastinc;
-	}
-	lastinc = now;
-
-	return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-	return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-	tmo *= usec;
-	tmo /= 1000;
-
-	endtime = get_timer_raw () + tmo;
-
-	do {
-		ulong now = get_timer_raw ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/cpu/arm920t/at91rm9200/timer.c b/cpu/arm920t/at91rm9200/timer.c
new file mode 100644
index 00000000000..235d1073886
--- /dev/null
+++ b/cpu/arm920t/at91rm9200/timer.c
@@ -0,0 +1,160 @@
+/*
+ * (C) Copyright 2002
+ * Lineo, Inc. <www.lineo.com>
+ * Bernhard Kuhn <bkuhn@lineo.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+/*#include <asm/io.h>*/
+#include <asm/arch/hardware.h>
+/*#include <asm/proc/ptrace.h>*/
+
+/* the number of clocks per CONFIG_SYS_HZ */
+#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
+AT91PS_TC tmr;
+
+static ulong timestamp;
+static ulong lastinc;
+
+int timer_init (void)
+{
+	tmr = AT91C_BASE_TC0;
+
+	/* enables TC1.0 clock */
+	*AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
+
+	*AT91C_TCB0_BCR = 0;
+	*AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
+	tmr->TC_CCR = AT91C_TC_CLKDIS;
+#define AT91C_TC_CMR_CPCTRG (1 << 14)
+	/* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
+	tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
+
+	tmr->TC_IDR = ~0ul;
+	tmr->TC_RC = TIMER_LOAD_VAL;
+	lastinc = 0;
+	tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
+	timestamp = 0;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastinc = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_raw (void)
+{
+	ulong now = READ_TIMER;
+
+	if (now >= lastinc) {
+		/* normal mode */
+		timestamp += now - lastinc;
+	} else {
+		/* we have an overflow ... */
+		timestamp += now + TIMER_LOAD_VAL - lastinc;
+	}
+	lastinc = now;
+
+	return timestamp;
+}
+
+ulong get_timer_masked (void)
+{
+	return get_timer_raw()/TIMER_LOAD_VAL;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	tmo = CONFIG_SYS_HZ_CLOCK / 1000;
+	tmo *= usec;
+	tmo /= 1000;
+
+	endtime = get_timer_raw () + tmo;
+
+	do {
+		ulong now = get_timer_raw ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/cpu/arm920t/imx/Makefile b/cpu/arm920t/imx/Makefile
index d3352deb4b6..28945e22cb8 100644
--- a/cpu/arm920t/imx/Makefile
+++ b/cpu/arm920t/imx/Makefile
@@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= generic.o interrupts.o speed.o
+COBJS	+= generic.o
+COBJS	+= speed.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/imx/interrupts.c b/cpu/arm920t/imx/interrupts.c
deleted file mode 100644
index 1beaf9dcf56..00000000000
--- a/cpu/arm920t/imx/interrupts.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined (CONFIG_IMX)
-
-#include <arm920t.h>
-#include <asm/arch/imx-regs.h>
-
-int interrupt_init (void)
-{
-	int i;
-	/* setup GP Timer 1 */
-	TCTL1 = TCTL_SWR;
-	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
-	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
-	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
-
-	reset_timer_masked();
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void reset_timer_masked (void)
-{
-	TCTL1 &= ~TCTL_TEN;
-	TCTL1 |= TCTL_TEN; /* Enable timer */
-}
-
-ulong get_timer_masked (void)
-{
-	return TCN1;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong endtime = get_timer_masked() + usec;
-	signed long diff;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-void udelay (unsigned long usec)
-{
-	udelay_masked(usec);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-
-	return tbclk;
-}
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu (ulong ignored)
-{
-	/* Disable watchdog and set Time-Out field to 0 */
-	WCR = 0x00000000;
-
-	/* Write Service Sequence */
-	WSR = 0x00005555;
-	WSR = 0x0000AAAA;
-
-	/* Enable watchdog */
-	WCR = 0x00000001;
-
-	while (1);
-	/*NOTREACHED*/
-}
-
-#endif /* defined (CONFIG_IMX) */
diff --git a/cpu/arm920t/imx/timer.c b/cpu/arm920t/imx/timer.c
new file mode 100644
index 00000000000..280c6829405
--- /dev/null
+++ b/cpu/arm920t/imx/timer.c
@@ -0,0 +1,139 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined (CONFIG_IMX)
+
+#include <arm920t.h>
+#include <asm/arch/imx-regs.h>
+
+int timer_init (void)
+{
+	int i;
+	/* setup GP Timer 1 */
+	TCTL1 = TCTL_SWR;
+	for ( i=0; i<100; i++) TCTL1 = 0; /* We have no udelay by now */
+	TPRER1 = get_PERCLK1() / 1000000; /* 1 MHz */
+	TCTL1 |= TCTL_FRR | (1<<1); /* Freerun Mode, PERCLK1 input */
+
+	reset_timer_masked();
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer (ulong t)
+{
+	/* nop */
+}
+
+void reset_timer_masked (void)
+{
+	TCTL1 &= ~TCTL_TEN;
+	TCTL1 |= TCTL_TEN; /* Enable timer */
+}
+
+ulong get_timer_masked (void)
+{
+	return TCN1;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong endtime = get_timer_masked() + usec;
+	signed long diff;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked(usec);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+
+	return tbclk;
+}
+
+/*
+ * Reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	/* Disable watchdog and set Time-Out field to 0 */
+	WCR = 0x00000000;
+
+	/* Write Service Sequence */
+	WSR = 0x00005555;
+	WSR = 0x0000AAAA;
+
+	/* Enable watchdog */
+	WCR = 0x00000001;
+
+	while (1);
+	/*NOTREACHED*/
+}
+
+#endif /* defined (CONFIG_IMX) */
diff --git a/cpu/arm920t/ks8695/Makefile b/cpu/arm920t/ks8695/Makefile
index f6b006300b1..f53fdc2b251 100644
--- a/cpu/arm920t/ks8695/Makefile
+++ b/cpu/arm920t/ks8695/Makefile
@@ -25,9 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o
 SOBJS	= lowlevel_init.o
 
+COBJS	= timer.o
+
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
 
diff --git a/cpu/arm920t/ks8695/interrupts.c b/cpu/arm920t/ks8695/interrupts.c
deleted file mode 100644
index 883d689ed06..00000000000
--- a/cpu/arm920t/ks8695/interrupts.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/platform.h>
-
-/*
- * Handy KS8695 register access functions.
- */
-#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
-#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
-
-int timer_inited;
-ulong timer_ticks;
-
-int interrupt_init (void)
-{
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
-}
-
-/*
- * Initial timer set constants. Nothing complicated, just set for a 1ms
- * tick.
- */
-#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
-#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
-#define	TIMER_PULSE	TIMER_COUNT
-
-void reset_timer_masked(void)
-{
-	/* Set the hadware timer for 1ms */
-	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
-	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
-	ks8695_write(KS8695_TIMER_CTRL, 0x2);
-	timer_ticks = 0;
-	timer_inited++;
-}
-
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer_masked(void)
-{
-	/* Check for timer wrap */
-	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
-		/* Clear interrupt condition */
-		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
-		timer_ticks++;
-	}
-	return timer_ticks;
-}
-
-ulong get_timer(ulong base)
-{
-       return (get_timer_masked() - base);
-}
-
-void set_timer(ulong t)
-{
-	timer_ticks = t;
-}
-
-void udelay(ulong usec)
-{
-	ulong start = get_timer_masked();
-	ulong end;
-
-	if (!timer_inited)
-		reset_timer();
-
-	/* Only 1ms resolution :-( */
-	end = usec / 1000;
-	while (get_timer(start) < end)
-		;
-}
-
-void reset_cpu (ulong ignored)
-{
-	ulong tc;
-
-	/* Set timer0 to watchdog, and let it timeout */
-	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
-	ks8695_write(KS8695_TIMER_CTRL, tc);
-	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
-	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
-
-	/* Should only wait here till watchdog resets */
-	for (;;)
-		;
-}
diff --git a/cpu/arm920t/ks8695/timer.c b/cpu/arm920t/ks8695/timer.c
new file mode 100644
index 00000000000..22987bc48be
--- /dev/null
+++ b/cpu/arm920t/ks8695/timer.c
@@ -0,0 +1,108 @@
+/*
+ * (C) Copyright 2004-2005, Greg Ungerer <greg.ungerer@opengear.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Handy KS8695 register access functions.
+ */
+#define	ks8695_read(a)    *((volatile ulong *) (KS8695_IO_BASE + (a)))
+#define	ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v)
+
+ulong timer_ticks;
+
+int timer_init (void)
+{
+	reset_timer();
+
+	return 0;
+}
+
+/*
+ * Initial timer set constants. Nothing complicated, just set for a 1ms
+ * tick.
+ */
+#define	TIMER_INTERVAL	(TICKS_PER_uSEC * mSEC_1)
+#define	TIMER_COUNT	(TIMER_INTERVAL / 2)
+#define	TIMER_PULSE	TIMER_COUNT
+
+void reset_timer_masked(void)
+{
+	/* Set the hadware timer for 1ms */
+	ks8695_write(KS8695_TIMER1, TIMER_COUNT);
+	ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE);
+	ks8695_write(KS8695_TIMER_CTRL, 0x2);
+	timer_ticks = 0;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer_masked(void)
+{
+	/* Check for timer wrap */
+	if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) {
+		/* Clear interrupt condition */
+		ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1);
+		timer_ticks++;
+	}
+	return timer_ticks;
+}
+
+ulong get_timer(ulong base)
+{
+       return (get_timer_masked() - base);
+}
+
+void set_timer(ulong t)
+{
+	timer_ticks = t;
+}
+
+void udelay(ulong usec)
+{
+	ulong start = get_timer_masked();
+	ulong end;
+
+	/* Only 1ms resolution :-( */
+	end = usec / 1000;
+	while (get_timer(start) < end)
+		;
+}
+
+void reset_cpu (ulong ignored)
+{
+	ulong tc;
+
+	/* Set timer0 to watchdog, and let it timeout */
+	tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2;
+	ks8695_write(KS8695_TIMER_CTRL, tc);
+	ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff));
+	ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1));
+
+	/* Should only wait here till watchdog resets */
+	for (;;)
+		;
+}
diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile
index 3afe19ce9c7..5d2be2c1b29 100644
--- a/cpu/arm920t/s3c24x0/Makefile
+++ b/cpu/arm920t/s3c24x0/Makefile
@@ -25,7 +25,10 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS	= interrupts.o speed.o usb.o usb_ohci.o
+COBJS	+= speed.o
+COBJS	+= timer.o
+COBJS	+= usb.o
+COBJS	+= usb_ohci.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c
deleted file mode 100644
index b8ce6ae94a8..00000000000
--- a/cpu/arm920t/s3c24x0/interrupts.c
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
-
-#include <arm920t.h>
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
-
-int timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
-
-	return (timers->TCNTO4 & 0xffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int interrupt_init (void)
-{
-	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
-
-	/* use PWM Timer 4 because it has no output */
-	/* prescaler for Timer 4 is 16 */
-	timers->TCFG0 = 0x0f00;
-	if (timer_load_val == 0)
-	{
-		/*
-		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
-		 * (default) and prescaler = 16. Should be 10390
-		 * @33.25MHz and 15625 @ 50 MHz
-		 */
-		timer_load_val = get_PCLK()/(2 * 16 * 100);
-	}
-	/* load value for 10 ms timeout */
-	lastdec = timers->TCNTB4 = timer_load_val;
-	/* auto load, manual update of Timer 4 */
-	timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
-	/* auto load, start Timer 4 */
-	timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
-	ulong tmo;
-	ulong start = get_timer(0);
-
-	tmo = usec / 1000;
-	tmo *= (timer_load_val * 100);
-	tmo /= 1000;
-
-	while ((ulong)(get_timer_masked () - start) < tmo)
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + timer_load_val - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= (timer_load_val * 100);
-		tmo /= 1000;
-	} else {
-		tmo = usec * (timer_load_val * 100);
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
-	tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
-      defined(CONFIG_SMDK2410) || \
-      defined(CONFIG_VCMA9)
-	tbclk = CONFIG_SYS_HZ;
-#else
-#	error "tbclk not configured"
-#endif
-
-	return tbclk;
-}
-
-/*
- * reset the cpu by setting up the watchdog timer and let him time out
- */
-void reset_cpu (ulong ignored)
-{
-	volatile S3C24X0_WATCHDOG * watchdog;
-
-#ifdef CONFIG_TRAB
-	extern void disable_vfd (void);
-
-	disable_vfd();
-#endif
-
-	watchdog = S3C24X0_GetBase_WATCHDOG();
-
-	/* Disable watchdog */
-	watchdog->WTCON = 0x0000;
-
-	/* Initialize watchdog timer count register */
-	watchdog->WTCNT = 0x0001;
-
-	/* Enable watchdog timer; assert reset at timer timeout */
-	watchdog->WTCON = 0x0021;
-
-	while(1);	/* loop forever and wait for reset to happen */
-
-	/*NOTREACHED*/
-}
-
-#ifdef CONFIG_USE_IRQ
-void s3c2410_irq(void)
-{
-	S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
-	u_int32_t intpnd = irq->INTPND;
-
-}
-#endif /* USE_IRQ */
-
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
new file mode 100644
index 00000000000..f3c0ed62cc8
--- /dev/null
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+
+#include <arm920t.h>
+#if defined(CONFIG_S3C2400)
+#include <s3c2400.h>
+#elif defined(CONFIG_S3C2410)
+#include <s3c2410.h>
+#endif
+
+int timer_load_val = 0;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+	return (timers->TCNTO4 & 0xffff);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+	S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+
+	/* use PWM Timer 4 because it has no output */
+	/* prescaler for Timer 4 is 16 */
+	timers->TCFG0 = 0x0f00;
+	if (timer_load_val == 0)
+	{
+		/*
+		 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
+		 * (default) and prescaler = 16. Should be 10390
+		 * @33.25MHz and 15625 @ 50 MHz
+		 */
+		timer_load_val = get_PCLK()/(2 * 16 * 100);
+	}
+	/* load value for 10 ms timeout */
+	lastdec = timers->TCNTB4 = timer_load_val;
+	/* auto load, manual update of Timer 4 */
+	timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+	/* auto load, start Timer 4 */
+	timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+	timestamp = 0;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+	ulong tmo;
+	ulong start = get_timer(0);
+
+	tmo = usec / 1000;
+	tmo *= (timer_load_val * 100);
+	tmo /= 1000;
+
+	while ((ulong)(get_timer_masked () - start) < tmo)
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + timer_load_val - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= (timer_load_val * 100);
+		tmo /= 1000;
+	} else {
+		tmo = usec * (timer_load_val * 100);
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
+	tbclk = timer_load_val * 100;
+#elif defined(CONFIG_SBC2410X) || \
+      defined(CONFIG_SMDK2410) || \
+      defined(CONFIG_VCMA9)
+	tbclk = CONFIG_SYS_HZ;
+#else
+#	error "tbclk not configured"
+#endif
+
+	return tbclk;
+}
+
+/*
+ * reset the cpu by setting up the watchdog timer and let him time out
+ */
+void reset_cpu (ulong ignored)
+{
+	volatile S3C24X0_WATCHDOG * watchdog;
+
+#ifdef CONFIG_TRAB
+	extern void disable_vfd (void);
+
+	disable_vfd();
+#endif
+
+	watchdog = S3C24X0_GetBase_WATCHDOG();
+
+	/* Disable watchdog */
+	watchdog->WTCON = 0x0000;
+
+	/* Initialize watchdog timer count register */
+	watchdog->WTCNT = 0x0001;
+
+	/* Enable watchdog timer; assert reset at timer timeout */
+	watchdog->WTCON = 0x0021;
+
+	while(1);	/* loop forever and wait for reset to happen */
+
+	/*NOTREACHED*/
+}
+
+#ifdef CONFIG_USE_IRQ
+void s3c2410_irq(void)
+{
+	S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
+	u_int32_t intpnd = irq->INTPND;
+
+}
+#endif /* USE_IRQ */
+
+#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
diff --git a/cpu/arm925t/Makefile b/cpu/arm925t/Makefile
index 0d4912cd728..8d0e88f9026 100644
--- a/cpu/arm925t/Makefile
+++ b/cpu/arm925t/Makefile
@@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o omap925.o
+
+COBJS	+= cpu.o
+COBJS	+= omap925.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/arm925t/interrupts.c b/cpu/arm925t/interrupts.c
deleted file mode 100644
index 179992debed..00000000000
--- a/cpu/arm925t/interrupts.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * (C) Copyright 2009
- * 2N Telekomunikace, <www.2n.cz>
- *
- * (C) Copyright 2003
- * Texas Instruments, <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm925t.h>
-#include <configs/omap1510.h>
-#include <asm/io.h>
-
-#define TIMER_LOAD_VAL	0xffffffff
-#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
-
-static uint32_t timestamp;
-static uint32_t lastdec;
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
-	/* Start the decrementer ticking down from 0xffffffff */
-	__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM);
-	__raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
-		(CONFIG_SYS_PTV << MPUTIM_PTV_BIT),
-		CONFIG_SYS_TIMERBASE + CNTL_TIMER);
-
-	/* init the timestamp and lastdec value */
-	reset_timer_masked();
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds AND preserve advance timestamp value */
-void udelay (unsigned long usec)
-{
-	int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-
-	while (tmo > 0) {
-		now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
-		if (last < now) /* count down timer underflow */
-			tmo -= TIMER_LOAD_VAL - now + last;
-		else
-			tmo -= last - now;
-		last = now;
-	}
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-			(TIMER_CLOCK / CONFIG_SYS_HZ);
-	timestamp = 0;	       /* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked (void)
-{
-	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
-			(TIMER_CLOCK / CONFIG_SYS_HZ);
-	if (lastdec < now)	/* count down timer underflow */
-		timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
-				now + lastdec;
-	else
-		timestamp += lastdec - now;
-	lastdec = now;
-
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/cpu/arm925t/timer.c b/cpu/arm925t/timer.c
new file mode 100644
index 00000000000..c16ef2577f8
--- /dev/null
+++ b/cpu/arm925t/timer.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2009
+ * 2N Telekomunikace, <www.2n.cz>
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm925t.h>
+#include <configs/omap1510.h>
+#include <asm/io.h>
+
+#define TIMER_LOAD_VAL	0xffffffff
+#define TIMER_CLOCK	(CONFIG_SYS_CLK_FREQ / (2 << CONFIG_SYS_PTV))
+
+static uint32_t timestamp;
+static uint32_t lastdec;
+
+/* nothing really to do with interrupts, just starts up a counter. */
+int timer_init (void)
+{
+	/* Start the decrementer ticking down from 0xffffffff */
+	__raw_writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + LOAD_TIM);
+	__raw_writel(MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE |
+		(CONFIG_SYS_PTV << MPUTIM_PTV_BIT),
+		CONFIG_SYS_TIMERBASE + CNTL_TIMER);
+
+	/* init the timestamp and lastdec value */
+	reset_timer_masked();
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds AND preserve advance timestamp value */
+void udelay (unsigned long usec)
+{
+	int32_t tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	uint32_t now, last = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+
+	while (tmo > 0) {
+		now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM);
+		if (last < now) /* count down timer underflow */
+			tmo -= TIMER_LOAD_VAL - now + last;
+		else
+			tmo -= last - now;
+		last = now;
+	}
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
+	timestamp = 0;	       /* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked (void)
+{
+	uint32_t now = __raw_readl(CONFIG_SYS_TIMERBASE + READ_TIM) /
+			(TIMER_CLOCK / CONFIG_SYS_HZ);
+	if (lastdec < now)	/* count down timer underflow */
+		timestamp += TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ) -
+				now + lastdec;
+	else
+		timestamp += lastdec - now;
+	lastdec = now;
+
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/cpu/arm926ejs/Makefile b/cpu/arm926ejs/Makefile
index d5ac7d3fd98..7701b03bbeb 100644
--- a/cpu/arm926ejs/Makefile
+++ b/cpu/arm926ejs/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o
+COBJS	= cpu.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm926ejs/interrupts.c b/cpu/arm926ejs/interrupts.c
deleted file mode 100644
index ce979f3d87b..00000000000
--- a/cpu/arm926ejs/interrupts.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * (C) Copyright 2003
- * Texas Instruments <www.ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002-2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * (C) Copyright 2004
- * Philippe Robin, ARM Ltd. <philippe.robin@arm.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm926ejs.h>
-
-#ifdef CONFIG_INTEGRATOR
-
-	/* Timer functionality supplied by Integrator board (AP or CP) */
-
-#else
-
-/* nothing really to do with interrupts, just starts up a counter. */
-int interrupt_init (void)
-{
-	extern void timer_init(void);
-
-	timer_init();
-
-	return 0;
-}
-
-#endif /* CONFIG_INTEGRATOR */
diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index d1e658d57cb..edf5cb29a72 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -32,7 +32,7 @@ COBJS	+= clock.o
 COBJS	+= mem.o
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
-COBJS	+= interrupts.o
+COBJS	+= timer.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/omap3/interrupts.c b/cpu/arm_cortexa8/omap3/interrupts.c
deleted file mode 100644
index 3fe13fbaaf8..00000000000
--- a/cpu/arm_cortexa8/omap3/interrupts.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * (C) Copyright 2008
- * Texas Instruments
- *
- * Richard Woodruff <r-woodruff2@ti.com>
- * Syed Moahmmed Khasim <khasim@ti.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/io.h>
-
-static ulong timestamp;
-static ulong lastinc;
-static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
-
-/*
- * Nothing really to do with interrupts, just starts up a counter.
- * We run the counter with 13MHz, divided by 8, resulting in timer
- * frequency of 1.625MHz. With 32bit counter register, counter
- * overflows in ~44min
- */
-
-/* 13MHz / 8 = 1.625MHz */
-#define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
-#define TIMER_LOAD_VAL	0xffffffff
-
-int interrupt_init(void)
-{
-	/* start the counter ticking up, reload value on overflow */
-	writel(TIMER_LOAD_VAL, &timer_base->tldr);
-	/* enable timer */
-	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
-		&timer_base->tclr);
-
-	reset_timer_masked();	/* init the timestamp and lastinc value */
-
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-void reset_timer(void)
-{
-	reset_timer_masked();
-}
-
-ulong get_timer(ulong base)
-{
-	return get_timer_masked() - base;
-}
-
-void set_timer(ulong t)
-{
-	timestamp = t;
-}
-
-/* delay x useconds */
-void udelay(unsigned long usec)
-{
-	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
-	unsigned long now, last = readl(&timer_base->tcrr);
-
-	while (tmo > 0) {
-		now = readl(&timer_base->tcrr);
-		if (last > now) /* count up timer overflow */
-			tmo -= TIMER_LOAD_VAL - last + now;
-		else
-			tmo -= now - last;
-		last = now;
-	}
-}
-
-void reset_timer_masked(void)
-{
-	/* reset time, capture current incrementer value time */
-	lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-	timestamp = 0;		/* start "advancing" time stamp from 0 */
-}
-
-ulong get_timer_masked(void)
-{
-	/* current tick value */
-	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
-
-	if (now >= lastinc)	/* normal mode (non roll) */
-		/* move stamp fordward with absoulte diff ticks */
-		timestamp += (now - lastinc);
-	else	/* we have rollover of incrementer */
-		timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
-				- lastinc) + now;
-	lastinc = now;
-	return timestamp;
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
diff --git a/cpu/arm_cortexa8/omap3/timer.c b/cpu/arm_cortexa8/omap3/timer.c
new file mode 100644
index 00000000000..05cfe763aa4
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/timer.c
@@ -0,0 +1,138 @@
+/*
+ * (C) Copyright 2008
+ * Texas Instruments
+ *
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Moahmmed Khasim <khasim@ti.com>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+
+static ulong timestamp;
+static ulong lastinc;
+static gptimer_t *timer_base = (gptimer_t *)CONFIG_SYS_TIMERBASE;
+
+/*
+ * Nothing really to do with interrupts, just starts up a counter.
+ * We run the counter with 13MHz, divided by 8, resulting in timer
+ * frequency of 1.625MHz. With 32bit counter register, counter
+ * overflows in ~44min
+ */
+
+/* 13MHz / 8 = 1.625MHz */
+#define TIMER_CLOCK	(V_SCLK / (2 << CONFIG_SYS_PTV))
+#define TIMER_LOAD_VAL	0xffffffff
+
+int timer_init(void)
+{
+	/* start the counter ticking up, reload value on overflow */
+	writel(TIMER_LOAD_VAL, &timer_base->tldr);
+	/* enable timer */
+	writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST,
+		&timer_base->tclr);
+
+	reset_timer_masked();	/* init the timestamp and lastinc value */
+
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	timestamp = t;
+}
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	unsigned long now, last = readl(&timer_base->tcrr);
+
+	while (tmo > 0) {
+		now = readl(&timer_base->tcrr);
+		if (last > now) /* count up timer overflow */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		else
+			tmo -= now - last;
+		last = now;
+	}
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time, capture current incrementer value time */
+	lastinc = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+	timestamp = 0;		/* start "advancing" time stamp from 0 */
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ);
+
+	if (now >= lastinc)	/* normal mode (non roll) */
+		/* move stamp fordward with absoulte diff ticks */
+		timestamp += (now - lastinc);
+	else	/* we have rollover of incrementer */
+		timestamp += ((TIMER_LOAD_VAL / (TIMER_CLOCK / CONFIG_SYS_HZ))
+				- lastinc) + now;
+	lastinc = now;
+	return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/cpu/ixp/Makefile b/cpu/ixp/Makefile
index a673cb1b9fc..1403c4f390f 100644
--- a/cpu/ixp/Makefile
+++ b/cpu/ixp/Makefile
@@ -26,12 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
+
 COBJS-y	+= cpu.o
-ifndef CONFIG_USE_IRQ
+COBJS-$(CONFIG_USE_IRQ)	+= interrupts.o
 COBJS-y	+= timer.o
-else
-COBJS-y	+= interrupts.o
-endif
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c
index ee0129ead3f..a05e439fdb5 100644
--- a/cpu/ixp/interrupts.c
+++ b/cpu/ixp/interrupts.c
@@ -33,14 +33,6 @@
 #include <asm/arch/ixp425.h>
 #include <asm/proc-armv/ptrace.h>
 
-/*
- * When interrupts are enabled, use timer 2 for time/delay generation...
- */
-
-#define FREQ		66666666
-#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
-#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
-
 struct _irq_handler {
 	void                *m_data;
 	void (*m_func)( void *data);
@@ -48,8 +40,6 @@ struct _irq_handler {
 
 static struct _irq_handler IRQ_HANDLER[N_IRQS];
 
-static volatile ulong timestamp;
-
 static void default_isr(void *data)
 {
 	printf("default_isr():  called for IRQ %d, Interrupt Status=%x PR=%x\n",
@@ -61,33 +51,20 @@ static int next_irq(void)
 	return (((*IXP425_ICIH & 0x000000fc) >> 2) - 1);
 }
 
-static void timer_isr(void *data)
-{
-	unsigned int *pTime = (unsigned int *)data;
-
-	(*pTime)++;
-
-	/*
-	 * Reset IRQ source
-	 */
-	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
-}
-
-ulong get_timer (ulong base)
+void do_irq (struct pt_regs *pt_regs)
 {
-	return timestamp - base;
-}
+	int irq = next_irq();
 
-void reset_timer (void)
-{
-	timestamp = 0;
+	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
 }
 
-void do_irq (struct pt_regs *pt_regs)
+void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
 {
-	int irq = next_irq();
+	if (irq >= N_IRQS || !handle_irq)
+		return;
 
-	IRQ_HANDLER[irq].m_func(IRQ_HANDLER[irq].m_data);
+	IRQ_HANDLER[irq].m_data = data;
+	IRQ_HANDLER[irq].m_func = handle_irq;
 }
 
 int interrupt_init (void)
@@ -95,23 +72,11 @@ int interrupt_init (void)
 	int i;
 
 	/* install default interrupt handlers */
-	for (i = 0; i < N_IRQS; i++) {
-		IRQ_HANDLER[i].m_data = (void *)i;
-		IRQ_HANDLER[i].m_func = default_isr;
-	}
-
-	/* install interrupt handler for timer */
-	IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_data = (void *)&timestamp;
-	IRQ_HANDLER[IXP425_TIMER_2_IRQ].m_func = timer_isr;
-
-	/* setup the Timer counter value */
-	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
+	for (i = 0; i < N_IRQS; i++)
+		irq_install_handler(i, default_isr, (void *)i);
 
 	/* configure interrupts for IRQ mode */
 	*IXP425_ICLR = 0x00000000;
 
-	/* enable timer irq */
-	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
-
 	return (0);
 }
diff --git a/cpu/ixp/timer.c b/cpu/ixp/timer.c
index deb227a1a63..685614966b7 100644
--- a/cpu/ixp/timer.c
+++ b/cpu/ixp/timer.c
@@ -32,6 +32,54 @@
 #include <common.h>
 #include <asm/arch/ixp425.h>
 
+#ifdef CONFIG_TIMER_IRQ
+
+#define FREQ		66666666
+#define CLOCK_TICK_RATE	(((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
+#define LATCH		((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ)	/* For divider */
+
+/*
+ * When interrupts are enabled, use timer 2 for time/delay generation...
+ */
+
+static volatile ulong timestamp;
+
+static void timer_isr(void *data)
+{
+	unsigned int *pTime = (unsigned int *)data;
+
+	(*pTime)++;
+
+	/*
+	 * Reset IRQ source
+	 */
+	*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
+}
+
+ulong get_timer (ulong base)
+{
+	return timestamp - base;
+}
+
+void reset_timer (void)
+{
+	timestamp = 0;
+}
+
+int timer_init (void)
+{
+	/* install interrupt handler for timer */
+	irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)&timestamp);
+
+	/* setup the Timer counter value */
+	*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
+
+	/* enable timer irq */
+	*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
+
+	return 0;
+}
+#else
 ulong get_timer (ulong base)
 {
        return get_timer_masked () - base;
@@ -79,3 +127,9 @@ ulong get_timer_masked (void)
 	}
 	return (reload_constant - current);
 }
+
+int timer_init(void)
+{
+	return 0;
+}
+#endif
diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile
index bac2a640cb0..b9ae76effac 100644
--- a/cpu/lh7a40x/Makefile
+++ b/cpu/lh7a40x/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o interrupts.o serial.o
+COBJS	= cpu.o speed.o serial.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/lh7a40x/interrupts.c b/cpu/lh7a40x/interrupts.c
deleted file mode 100644
index d39e7077755..00000000000
--- a/cpu/lh7a40x/interrupts.c
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <arm920t.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int interrupt_init (void)
-{
-	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
-	lh7a40x_timer_t* timer = &timers->timer1;
-
-	/* a periodic timer using the 508kHz source */
-	timer->control = (TIMER_PER | TIMER_CLK508K);
-
-	if (timer_load_val == 0) {
-		/*
-		 * 10ms period with 508.469kHz clock = 5084
-		 */
-		timer_load_val = CONFIG_SYS_HZ/100;
-	}
-
-	/* load value for 10 ms timeout */
-	lastdec = timer->load = timer_load_val;
-
-	/* auto load, start timer */
-	timer->control = timer->control | TIMER_EN;
-	timestamp = 0;
-
-	return (0);
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return (get_timer_masked() - base);
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
-	ulong tmo,tmp;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	}
-	else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		}
-		else
-			tmo = 1;
-	}
-
-	/* check for rollover during this delay */
-	tmp = get_timer (0);
-	if ((tmp + tmo) < tmp )
-		reset_timer_masked();  /* timer would roll over */
-	else
-		tmo += tmp;
-
-	while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER();
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER();
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += (lastdec - now);
-	} else {
-		/* we have an overflow ... */
-		timestamp += ((lastdec + timer_load_val) - now);
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	/* normalize */
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		if (usec > 1) {
-			tmo = usec * CONFIG_SYS_HZ;
-			tmo /= (1000*1000);
-		} else {
-			tmo = 1;
-		}
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = timer_load_val * 100;
-
-	return tbclk;
-}
diff --git a/cpu/lh7a40x/timer.c b/cpu/lh7a40x/timer.c
new file mode 100644
index 00000000000..f0baf147379
--- /dev/null
+++ b/cpu/lh7a40x/timer.c
@@ -0,0 +1,194 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <arm920t.h>
+#include <lh7a40x.h>
+
+static ulong timer_load_val = 0;
+
+/* macro to read the 16 bit timer */
+static inline ulong READ_TIMER(void)
+{
+	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
+	lh7a40x_timer_t* timer = &timers->timer1;
+
+	return (timer->value & 0x0000ffff);
+}
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+	lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
+	lh7a40x_timer_t* timer = &timers->timer1;
+
+	/* a periodic timer using the 508kHz source */
+	timer->control = (TIMER_PER | TIMER_CLK508K);
+
+	if (timer_load_val == 0) {
+		/*
+		 * 10ms period with 508.469kHz clock = 5084
+		 */
+		timer_load_val = CONFIG_SYS_HZ/100;
+	}
+
+	/* load value for 10 ms timeout */
+	lastdec = timer->load = timer_load_val;
+
+	/* auto load, start timer */
+	timer->control = timer->control | TIMER_EN;
+	timestamp = 0;
+
+	return (0);
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return (get_timer_masked() - base);
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+	ulong tmo,tmp;
+
+	/* normalize */
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	}
+	else {
+		if (usec > 1) {
+			tmo = usec * CONFIG_SYS_HZ;
+			tmo /= (1000*1000);
+		}
+		else
+			tmo = 1;
+	}
+
+	/* check for rollover during this delay */
+	tmp = get_timer (0);
+	if ((tmp + tmo) < tmp )
+		reset_timer_masked();  /* timer would roll over */
+	else
+		tmo += tmp;
+
+	while (get_timer_masked () < tmo);
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER();
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER();
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += (lastdec - now);
+	} else {
+		/* we have an overflow ... */
+		timestamp += ((lastdec + timer_load_val) - now);
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	/* normalize */
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		if (usec > 1) {
+			tmo = usec * CONFIG_SYS_HZ;
+			tmo /= (1000*1000);
+		} else {
+			tmo = 1;
+		}
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = timer_load_val * 100;
+
+	return tbclk;
+}
diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile
index 42903b2ea4f..5dc3a52c8d5 100644
--- a/cpu/pxa/Makefile
+++ b/cpu/pxa/Makefile
@@ -26,7 +26,13 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= serial.o interrupts.o cpu.o i2c.o pxafb.o usb.o
+
+COBJS	+= cpu.o
+COBJS	+= i2c.o
+COBJS	+= pxafb.o
+COBJS	+= serial.o
+COBJS	+= timer.o
+COBJS	+= usb.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/pxa/interrupts.c b/cpu/pxa/interrupts.c
deleted file mode 100644
index 2bc5c50a917..00000000000
--- a/cpu/pxa/interrupts.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
-#include <div64.h>
-
-#ifdef CONFIG_USE_IRQ
-#error: interrupts not implemented yet
-#endif
-
-#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
-#define TIMER_FREQ_HZ 3250000
-#elif defined(CONFIG_PXA250)
-#define TIMER_FREQ_HZ 3686400
-#else
-#error "Timer frequency unknown - please config PXA CPU type"
-#endif
-
-static inline unsigned long long tick_to_time(unsigned long long tick)
-{
-	tick *= CONFIG_SYS_HZ;
-	do_div(tick, TIMER_FREQ_HZ);
-	return tick;
-}
-
-static inline unsigned long long us_to_tick(unsigned long long us)
-{
-	us = us * TIMER_FREQ_HZ + 999999;
-	do_div(us, 1000000);
-	return us;
-}
-
-int interrupt_init (void)
-{
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
-}
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void udelay (unsigned long usec)
-{
-	udelay_masked (usec);
-}
-
-
-void reset_timer_masked (void)
-{
-	OSCR = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	return tick_to_time(get_ticks());
-}
-
-void udelay_masked (unsigned long usec)
-{
-	unsigned long long tmp;
-	ulong tmo;
-
-	tmo = us_to_tick(usec);
-	tmp = get_ticks() + tmo;	/* get current timestamp */
-
-	while (get_ticks() < tmp)	/* loop till event */
-		 /*NOP*/;
-
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return OSCR;
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-	tbclk = TIMER_FREQ_HZ;
-	return tbclk;
-}
diff --git a/cpu/pxa/timer.c b/cpu/pxa/timer.c
new file mode 100644
index 00000000000..e2df3a57fcb
--- /dev/null
+++ b/cpu/pxa/timer.c
@@ -0,0 +1,128 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa-regs.h>
+#include <div64.h>
+
+#ifdef CONFIG_USE_IRQ
+#error: interrupts not implemented yet
+#endif
+
+#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
+#define TIMER_FREQ_HZ 3250000
+#elif defined(CONFIG_PXA250)
+#define TIMER_FREQ_HZ 3686400
+#else
+#error "Timer frequency unknown - please config PXA CPU type"
+#endif
+
+static inline unsigned long long tick_to_time(unsigned long long tick)
+{
+	tick *= CONFIG_SYS_HZ;
+	do_div(tick, TIMER_FREQ_HZ);
+	return tick;
+}
+
+static inline unsigned long long us_to_tick(unsigned long long us)
+{
+	us = us * TIMER_FREQ_HZ + 999999;
+	do_div(us, 1000000);
+	return us;
+}
+
+int timer_init (void)
+{
+	reset_timer();
+
+	return 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	/* nop */
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked (usec);
+}
+
+
+void reset_timer_masked (void)
+{
+	OSCR = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	return tick_to_time(get_ticks());
+}
+
+void udelay_masked (unsigned long usec)
+{
+	unsigned long long tmp;
+	ulong tmo;
+
+	tmo = us_to_tick(usec);
+	tmp = get_ticks() + tmo;	/* get current timestamp */
+
+	while (get_ticks() < tmp)	/* loop till event */
+		 /*NOP*/;
+
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return OSCR;
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+	tbclk = TIMER_FREQ_HZ;
+	return tbclk;
+}
diff --git a/cpu/s3c44b0/Makefile b/cpu/s3c44b0/Makefile
index ae909a699f6..6da2016f660 100644
--- a/cpu/s3c44b0/Makefile
+++ b/cpu/s3c44b0/Makefile
@@ -26,7 +26,10 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cache.o cpu.o interrupts.o
+
+COBJS	+= cache.o
+COBJS	+= cpu.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/s3c44b0/interrupts.c b/cpu/s3c44b0/interrupts.c
deleted file mode 100644
index eb23e6ab114..00000000000
--- a/cpu/s3c44b0/interrupts.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * (C) Copyright 2004
- * DAVE Srl
- * http://www.dave-tech.it
- * http://www.wawnet.biz
- * mailto:info@wawnet.biz
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/hardware.h>
-
-/* we always count down the max. */
-#define TIMER_LOAD_VAL 0xffff
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (TCNTO1 & 0xffff)
-
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ NOT supported
-#endif
-
-static ulong timestamp;
-static ulong lastdec;
-
-int interrupt_init (void)
-{
-	TCFG0 = 0x000000E9;
-	TCFG1 = 0x00000004;
-	TCON = 0x00000900;
-	TCNTB1 = TIMER_LOAD_VAL;
-	TCMPB1 = 0;
-	TCON = 0x00000B00;
-	TCON = 0x00000900;
-
-
-	lastdec = TCNTB1 = TIMER_LOAD_VAL;
-	timestamp = 0;
-	return 0;
-}
-
-/*
- * timer without interrupts
- */
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked () - base;
-}
-
-void set_timer (ulong t)
-{
-	timestamp = t;
-}
-
-void udelay (unsigned long usec)
-{
-	ulong tmo;
-
-	tmo = usec / 1000;
-	tmo *= CONFIG_SYS_HZ;
-	tmo /= 8;
-
-	tmo += get_timer (0);
-
-	while (get_timer_masked () < tmo)
-		/*NOP*/;
-}
-
-void reset_timer_masked (void)
-{
-	/* reset time */
-	lastdec = READ_TIMER;
-	timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	ulong now = READ_TIMER;
-
-	if (lastdec >= now) {
-		/* normal mode */
-		timestamp += lastdec - now;
-	} else {
-		/* we have an overflow ... */
-		timestamp += lastdec + TIMER_LOAD_VAL - now;
-	}
-	lastdec = now;
-
-	return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 8;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*8);
-	}
-
-	endtime = get_timer(0) + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
diff --git a/cpu/s3c44b0/timer.c b/cpu/s3c44b0/timer.c
new file mode 100644
index 00000000000..34184abb735
--- /dev/null
+++ b/cpu/s3c44b0/timer.c
@@ -0,0 +1,136 @@
+/*
+ * (C) Copyright 2004
+ * DAVE Srl
+ * http://www.dave-tech.it
+ * http://www.wawnet.biz
+ * mailto:info@wawnet.biz
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/hardware.h>
+
+/* we always count down the max. */
+#define TIMER_LOAD_VAL 0xffff
+
+/* macro to read the 16 bit timer */
+#define READ_TIMER (TCNTO1 & 0xffff)
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ NOT supported
+#endif
+
+static ulong timestamp;
+static ulong lastdec;
+
+int timer_init (void)
+{
+	TCFG0 = 0x000000E9;
+	TCFG1 = 0x00000004;
+	TCON = 0x00000900;
+	TCNTB1 = TIMER_LOAD_VAL;
+	TCMPB1 = 0;
+	TCON = 0x00000B00;
+	TCON = 0x00000900;
+
+
+	lastdec = TCNTB1 = TIMER_LOAD_VAL;
+	timestamp = 0;
+	return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked () - base;
+}
+
+void set_timer (ulong t)
+{
+	timestamp = t;
+}
+
+void udelay (unsigned long usec)
+{
+	ulong tmo;
+
+	tmo = usec / 1000;
+	tmo *= CONFIG_SYS_HZ;
+	tmo /= 8;
+
+	tmo += get_timer (0);
+
+	while (get_timer_masked () < tmo)
+		/*NOP*/;
+}
+
+void reset_timer_masked (void)
+{
+	/* reset time */
+	lastdec = READ_TIMER;
+	timestamp = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	ulong now = READ_TIMER;
+
+	if (lastdec >= now) {
+		/* normal mode */
+		timestamp += lastdec - now;
+	} else {
+		/* we have an overflow ... */
+		timestamp += lastdec + TIMER_LOAD_VAL - now;
+	}
+	lastdec = now;
+
+	return timestamp;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 8;
+	} else {
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*8);
+	}
+
+	endtime = get_timer(0) + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
diff --git a/cpu/sa1100/Makefile b/cpu/sa1100/Makefile
index fd696f7efb1..28b668267c4 100644
--- a/cpu/sa1100/Makefile
+++ b/cpu/sa1100/Makefile
@@ -26,7 +26,9 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= interrupts.o cpu.o
+
+COBJS	+= cpu.o
+COBJS	+= timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/sa1100/interrupts.c b/cpu/sa1100/interrupts.c
deleted file mode 100644
index 2eff045709f..00000000000
--- a/cpu/sa1100/interrupts.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <SA-1100.h>
-
-int interrupt_init (void)
-{
-	/* nothing happens here - we don't setup any IRQs */
-	return (0);
-}
-
-void reset_timer (void)
-{
-	reset_timer_masked ();
-}
-
-ulong get_timer (ulong base)
-{
-	return get_timer_masked ();
-}
-
-void set_timer (ulong t)
-{
-	/* nop */
-}
-
-void udelay (unsigned long usec)
-{
-	udelay_masked (usec);
-}
-
-
-void reset_timer_masked (void)
-{
-	OSCR = 0;
-}
-
-ulong get_timer_masked (void)
-{
-	return OSCR;
-}
-
-void udelay_masked (unsigned long usec)
-{
-	ulong tmo;
-	ulong endtime;
-	signed long diff;
-
-	if (usec >= 1000) {
-		tmo = usec / 1000;
-		tmo *= CONFIG_SYS_HZ;
-		tmo /= 1000;
-	} else {
-		tmo = usec * CONFIG_SYS_HZ;
-		tmo /= (1000*1000);
-	}
-
-	endtime = get_timer_masked () + tmo;
-
-	do {
-		ulong now = get_timer_masked ();
-		diff = endtime - now;
-	} while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-	ulong tbclk;
-
-	tbclk = CONFIG_SYS_HZ;
-	return tbclk;
-}
diff --git a/cpu/sa1100/timer.c b/cpu/sa1100/timer.c
new file mode 100644
index 00000000000..3f77e815cb6
--- /dev/null
+++ b/cpu/sa1100/timer.c
@@ -0,0 +1,110 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <SA-1100.h>
+
+int timer_init (void)
+{
+	return 0;
+}
+
+void reset_timer (void)
+{
+	reset_timer_masked ();
+}
+
+ulong get_timer (ulong base)
+{
+	return get_timer_masked ();
+}
+
+void set_timer (ulong t)
+{
+	/* nop */
+}
+
+void udelay (unsigned long usec)
+{
+	udelay_masked (usec);
+}
+
+
+void reset_timer_masked (void)
+{
+	OSCR = 0;
+}
+
+ulong get_timer_masked (void)
+{
+	return OSCR;
+}
+
+void udelay_masked (unsigned long usec)
+{
+	ulong tmo;
+	ulong endtime;
+	signed long diff;
+
+	if (usec >= 1000) {
+		tmo = usec / 1000;
+		tmo *= CONFIG_SYS_HZ;
+		tmo /= 1000;
+	} else {
+		tmo = usec * CONFIG_SYS_HZ;
+		tmo /= (1000*1000);
+	}
+
+	endtime = get_timer_masked () + tmo;
+
+	do {
+		ulong now = get_timer_masked ();
+		diff = endtime - now;
+	} while (diff >= 0);
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+ulong get_tbclk (void)
+{
+	ulong tbclk;
+
+	tbclk = CONFIG_SYS_HZ;
+	return tbclk;
+}
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index e7d58fe8cda..238d4085419 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -62,4 +62,7 @@ void	reset_timer_masked	(void);
 ulong	get_timer_masked	(void);
 void	udelay_masked		(unsigned long usec);
 
+/* cpu/.../timer.c */
+int	timer_init		(void);
+
 #endif	/* _U_BOOT_ARM_H_ */
diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h
index 75707e597db..0c092347ca7 100644
--- a/include/configs/ixdpg425.h
+++ b/include/configs/ixdpg425.h
@@ -55,6 +55,7 @@
  */
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 #define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
+#define CONFIG_TIMER_IRQ
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h
index edaa81b59b0..1255f21e8b0 100644
--- a/include/configs/pdnb3.h
+++ b/include/configs/pdnb3.h
@@ -51,6 +51,7 @@
  * Misc configuration options
  */
 #define CONFIG_USE_IRQ          1	/* we need IRQ stuff for timer	*/
+#define CONFIG_TIMER_IRQ
 
 #define CONFIG_BOOTCOUNT_LIMIT		/* support for bootcount limit	*/
 #define CONFIG_SYS_BOOTCOUNT_ADDR	0x60003000 /* inside qmrg sram		*/
diff --git a/lib_arm/board.c b/lib_arm/board.c
index e3040acdc62..c7768e52893 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -266,7 +266,10 @@ init_fnc_t *init_sequence[] = {
 	arch_cpu_init,		/* basic arch cpu dependent setup */
 #endif
 	board_init,		/* basic board dependent setup */
+#if defined(CONFIG_USE_IRQ)
 	interrupt_init,		/* set up exceptions */
+#endif
+	timer_init,		/* initialize timer */
 	env_init,		/* initialize environment */
 	init_baudrate,		/* initialze baudrate settings */
 	serial_init,		/* serial communications setup */
-- 
cgit v1.3.1


From 7cdf804f34378b910b4c4edd2dac7e3ca61c0825 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Fri, 15 May 2009 23:47:12 +0200
Subject: ARM Add blue colour LED to status_led.

There is exiting support for red,yellow,green but no blue.
The main LED on the zoom2 is a blue LED.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 include/status_led.h | 4 ++++
 lib_arm/board.c      | 4 ++++
 2 files changed, 8 insertions(+)

(limited to 'include')

diff --git a/include/status_led.h b/include/status_led.h
index 175972a0527..9dbf01fca8e 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -397,6 +397,8 @@ extern void	green_LED_on(void);
 extern void	green_LED_off(void);
 extern void	yellow_LED_on(void);
 extern void	yellow_LED_off(void);
+extern void	blue_LED_on(void);
+extern void	blue_LED_off(void);
 #else
 	.extern LED_init
 	.extern red_LED_on
@@ -405,6 +407,8 @@ extern void	yellow_LED_off(void);
 	.extern yellow_LED_off
 	.extern green_LED_on
 	.extern green_LED_off
+	.extern blue_LED_on
+	.extern blue_LED_off
 #endif
 
 #endif	/* CONFIG_STATUS_LED	*/
diff --git a/lib_arm/board.c b/lib_arm/board.c
index c7768e52893..d86ed22cadb 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -136,6 +136,10 @@ void inline __yellow_LED_on(void) {}
 void inline yellow_LED_on(void)__attribute__((weak, alias("__yellow_LED_on")));
 void inline __yellow_LED_off(void) {}
 void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off")));
+void inline __blue_LED_on(void) {}
+void inline blue_LED_on(void)__attribute__((weak, alias("__blue_LED_on")));
+void inline __blue_LED_off(void) {}
+void inline blue_LED_off(void)__attribute__((weak, alias("__blue_LED_off")));
 
 /************************************************************************
  * Init Utilities							*
-- 
cgit v1.3.1


From daea928829098cae3c9ec6b801e52ba616725034 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Fri, 15 May 2009 23:47:12 +0200
Subject: ZOOM1 Remove more legacy NAND defines.

These legacy NAND defines are no longer needed by this target.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 include/configs/omap3_zoom1.h | 13 -------------
 1 file changed, 13 deletions(-)

(limited to 'include')

diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h
index 50c05dcb9ea..9e000ed1c2b 100644
--- a/include/configs/omap3_zoom1.h
+++ b/include/configs/omap3_zoom1.h
@@ -138,19 +138,6 @@
 
 #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */
 							/* devices */
-#define SECTORSIZE			512
-
-#define NAND_ALLOW_ERASE_ALL
-#define ADDR_COLUMN			1
-#define ADDR_PAGE			2
-#define ADDR_COLUMN_PAGE		3
-
-#define NAND_ChipID_UNKNOWN		0x00
-#define NAND_MAX_FLOORS			1
-#define NAND_MAX_CHIPS			1
-#define NAND_NO_RB			1
-#define CONFIG_SYS_NAND_WP
-
 #define CONFIG_JFFS2_NAND
 /* nand device jffs2 lives on */
 #define CONFIG_JFFS2_DEV		"nand0"
-- 
cgit v1.3.1


From 7a4f511b59f08f51dde4ceacbd45f49b8bf2a5cc Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 15 May 2009 23:47:12 +0200
Subject: davinci: display correct clock info

Move the clock-rate dumping code into the cpu/.../davinci area
where it should have been, enabled by CONFIG_DISPLAY_CPUINFO,
updating the format and showing the DSP clock (where relevant).

Switch boards to use the cpuinfo() hook for this stuff.

Remove a few now-obsolete PLL #defines.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 board/davinci/common/misc.c             |  13 +---
 board/davinci/common/misc.h             |   1 -
 board/davinci/dvevm/dvevm.c             |   2 -
 board/davinci/schmoogie/schmoogie.c     |   2 -
 board/davinci/sffsdr/sffsdr.c           |   2 -
 board/davinci/sonata/sonata.c           |   2 -
 cpu/arm926ejs/davinci/Makefile          |   2 +-
 cpu/arm926ejs/davinci/cpu.c             | 131 ++++++++++++++++++++++++++++++++
 include/asm-arm/arch-davinci/hardware.h |   5 --
 include/configs/davinci_dvevm.h         |   1 +
 include/configs/davinci_schmoogie.h     |   1 +
 include/configs/davinci_sffsdr.h        |   4 +-
 include/configs/davinci_sonata.h        |   1 +
 13 files changed, 138 insertions(+), 29 deletions(-)
 create mode 100644 cpu/arm926ejs/davinci/cpu.c

(limited to 'include')

diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index cfab729bbbc..ffdc20b93ab 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -28,6 +28,7 @@
 #include <net.h>
 #include <asm/arch/hardware.h>
 
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
@@ -38,18 +39,6 @@ int dram_init(void)
 	return(0);
 }
 
-static int dv_get_pllm_output(uint32_t pllm)
-{
-	return (pllm + 1) * (CONFIG_SYS_HZ_CLOCK / 1000000);
-}
-
-void dv_display_clk_infos(void)
-{
-	printf("ARM Clock: %dMHz\n", dv_get_pllm_output(REG(PLL1_PLLM)) / 2);
-	printf("DDR Clock: %dMHz\n", dv_get_pllm_output(REG(PLL2_PLLM)) /
-	       ((REG(PLL2_DIV2) & 0x1f) + 1) / 2);
-}
-
 #ifdef CONFIG_DRIVER_TI_EMAC
 
 /* Read ethernet MAC address from EEPROM for DVEVM compatible boards.
diff --git a/board/davinci/common/misc.h b/board/davinci/common/misc.h
index 5d29784403f..316159a2f76 100644
--- a/board/davinci/common/misc.h
+++ b/board/davinci/common/misc.h
@@ -24,7 +24,6 @@
 
 extern int eth_hw_init(void);
 
-void dv_display_clk_infos(void);
 int dvevm_read_mac_address(uint8_t *buf);
 void dv_configure_mac_address(uint8_t *rom_enetaddr);
 
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index 162a5dcea81..8f386331e68 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -69,8 +69,6 @@ int misc_init_r(void)
 	uint8_t video_mode;
 	uint8_t eeprom_enetaddr[6];
 
-	dv_display_clk_infos();
-
 	/* Read Ethernet MAC address from EEPROM if available. */
 	if (dvevm_read_mac_address(eeprom_enetaddr))
 		dv_configure_mac_address(eeprom_enetaddr);
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
index d6dfef58174..6e0f5913359 100644
--- a/board/davinci/schmoogie/schmoogie.c
+++ b/board/davinci/schmoogie/schmoogie.c
@@ -104,8 +104,6 @@ int misc_init_r(void)
 			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
 		};
 
-	dv_display_clk_infos();
-
 	/* Set serial number from UID chip */
 	if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
 		printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
index 7d855fb8360..7f4ee361bb6 100644
--- a/board/davinci/sffsdr/sffsdr.c
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -131,8 +131,6 @@ int misc_init_r(void)
 	/* EMIF-A CS3 configuration for FPGA. */
 	REG(DAVINCI_A3CR) = DAVINCI_A3CR_VAL;
 
-	dv_display_clk_infos();
-
 	/* Configure I2C switch (PCA9543) to enable channel 0. */
 	i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
 	if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
index 155fb549c04..a0bea05177c 100644
--- a/board/davinci/sonata/sonata.c
+++ b/board/davinci/sonata/sonata.c
@@ -66,8 +66,6 @@ int misc_init_r(void)
 {
 	uint8_t eeprom_enetaddr[6];
 
-	dv_display_clk_infos();
-
 	/* Read Ethernet MAC address from EEPROM if available. */
 	if (dvevm_read_mac_address(eeprom_enetaddr))
 		dv_configure_mac_address(eeprom_enetaddr);
diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile
index 480f19f557a..6eaa89c614a 100644
--- a/cpu/arm926ejs/davinci/Makefile
+++ b/cpu/arm926ejs/davinci/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(SOC).a
 
-COBJS-y				+= timer.o psc.o
+COBJS-y				+= cpu.o timer.o psc.o
 COBJS-$(CONFIG_SOC_DM355)	+= dm355.o
 COBJS-$(CONFIG_SOC_DM644X)	+= dm644x.o
 COBJS-$(CONFIG_DRIVER_TI_EMAC)	+= ether.o lxt972.o dp83848.o
diff --git a/cpu/arm926ejs/davinci/cpu.c b/cpu/arm926ejs/davinci/cpu.c
new file mode 100644
index 00000000000..29aead6f4f5
--- /dev/null
+++ b/cpu/arm926ejs/davinci/cpu.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2004 Texas Instruments.
+ * Copyright (C) 2009 David Brownell
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <asm/arch/hardware.h>
+
+
+/* offsets from PLL controller base */
+#define PLLC_PLLCTL	0x100
+#define PLLC_PLLM	0x110
+#define PLLC_PREDIV	0x114
+#define PLLC_PLLDIV1	0x118
+#define PLLC_PLLDIV2	0x11c
+#define PLLC_PLLDIV3	0x120
+#define PLLC_POSTDIV	0x128
+#define PLLC_BPDIV	0x12c
+#define PLLC_PLLDIV4	0x160
+#define PLLC_PLLDIV5	0x164
+#define PLLC_PLLDIV6	0x168
+#define PLLC_PLLDIV8	0x170
+#define PLLC_PLLDIV9	0x174
+
+#define BIT(x)		(1 << (x))
+
+/* SOC-specific pll info */
+#ifdef CONFIG_SOC_DM355
+#define ARM_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+#ifdef CONFIG_SOC_DM644X
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV2
+#endif
+
+#ifdef CONFIG_SOC_DM6447
+#define ARM_PLLDIV	PLLC_PLLDIV2
+#define DSP_PLLDIV	PLLC_PLLDIV1
+#define DDR_PLLDIV	PLLC_PLLDIV1
+#endif
+
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+
+static unsigned pll_div(volatile void *pllbase, unsigned offset)
+{
+	u32	div;
+
+	div = REG(pllbase + offset);
+	return (div & BIT(15)) ? (1 + (div & 0x1f)) : 1;
+}
+
+static inline unsigned pll_prediv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	/* this register read seems to fail on pll0 */
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return 8;
+	else
+		return pll_div(pllbase, PLLC_PREDIV);
+#endif
+	return 1;
+}
+
+static inline unsigned pll_postdiv(volatile void *pllbase)
+{
+#ifdef CONFIG_SOC_DM355
+	return pll_div(pllbase, PLLC_POSTDIV);
+#elif defined(CONFIG_SOC_DM6446)
+	if (pllbase == (volatile void *)DAVINCI_PLL_CNTRL0_BASE)
+		return pll_div(pllbase, PLLC_POSTDIV);
+#endif
+	return 1;
+}
+
+static unsigned pll_sysclk_mhz(unsigned pll_addr, unsigned div)
+{
+	volatile void	*pllbase = (volatile void *) pll_addr;
+	unsigned	base = CONFIG_SYS_HZ_CLOCK / 1000;
+
+	/* the PLL might be bypassed */
+	if (REG(pllbase + PLLC_PLLCTL) & BIT(0)) {
+		base /= pll_prediv(pllbase);
+		base *= 1 + (REG(pllbase + PLLC_PLLM) & 0x0ff);
+		base /= pll_postdiv(pllbase);
+	}
+	return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div));
+}
+
+int print_cpuinfo(void)
+{
+	/* REVISIT fetch and display CPU ID and revision information
+	 * too ... that will matter as more revisions appear.
+	 */
+	printf("Cores: ARM %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, ARM_PLLDIV));
+
+#ifdef DSP_PLLDIV
+	printf(", DSP %d MHz",
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL0_BASE, DSP_PLLDIV));
+#endif
+
+	printf("\nDDR:   %d MHz\n",
+			/* DDR PHY uses an x2 input clock */
+			pll_sysclk_mhz(DAVINCI_PLL_CNTRL1_BASE, DDR_PLLDIV)
+				/ 2);
+	return 0;
+}
+
+#endif
+
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index a28cfb4ae09..99324e45c7e 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -175,11 +175,6 @@ void davinci_errata_workarounds(void);
 
 #define PSC_SILVER_BULLET		(0x01c41a20)
 
-/* Some PLL defines */
-#define PLL1_PLLM			(0x01c40910)
-#define PLL2_PLLM			(0x01c40d10)
-#define PLL2_DIV2			(0x01c40d1c)
-
 /* Miscellania... */
 #define VBPR				(0x20000020)
 
diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 9be10f76cfa..e936ba87be1 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -52,6 +52,7 @@
 #define DV_EVM
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NOR
+#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index d5e77f8e17b..6612cb3cbb1 100644
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -27,6 +27,7 @@
 #define SCHMOOGIE
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
+#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index 4be5b7e4883..6c1dc117dea 100644
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -28,8 +28,8 @@
 #define SFFSDR
 #define CONFIG_SYS_NAND_LARGEPAGE
 #define CONFIG_SYS_USE_NAND
-#define CONFIG_SYS_USE_DSPLINK		/* This is to prevent U-Boot from
-				 * powering ON the DSP. */
+#define CONFIG_SYS_USE_DSPLINK		/* don't power up the DSP. */
+#define CONFIG_DISPLAY_CPUINFO
 /* SoC Configuration */
 #define CONFIG_ARM926EJS			/* arm926ejs CPU core */
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index a6bf8259bd0..893729c6f24 100644
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -52,6 +52,7 @@
 #define SONATA_BOARD
 #define CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_SYS_USE_NOR
+#define CONFIG_DISPLAY_CPUINFO
 /*===================*/
 /* SoC Configuration */
 /*===================*/
-- 
cgit v1.3.1


From 269dfea017b09c5a999d3053d00505c19789c350 Mon Sep 17 00:00:00 2001
From: David Brownell <david-b@pacbell.net>
Date: Fri, 15 May 2009 23:47:13 +0200
Subject: davinci dm6446evm NAND update

This updates the optional (non-default!) NAND support for the
DaVinci DM6446 EVM:

 - include MTD partitioning, defaulting to what Linux uses

 - use a flash-based BBT, which among other things speeds bootup

This matches code that's now queued for mainline Linux, and might
even merge in an upcoming 2.6.30-rc; and the MTIDS are set up so
that the U-Boot $mtdparts environment variable can be passed as-is
on the kernel command line as a cmdlinepart override.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 include/configs/davinci_dvevm.h | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'include')

diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index e936ba87be1..6c5d0650885 100644
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -120,6 +120,12 @@
 #ifdef CONFIG_SYS_NAND_SMALLPAGE
 #define CONFIG_ENV_SECT_SIZE	512	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_16K
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+#define MTDIDS_DEFAULT		\
+	"nand0=davinci_nand.0"
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:384k(bootloader)ro,4m(kernel),-(filesystem)"
 #else
 #define CONFIG_ENV_SECT_SIZE	2048	/* Env sector Size */
 #define CONFIG_ENV_SIZE		SZ_128K
@@ -127,6 +133,7 @@
 #define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is loaded by a bootloader */
 #define CONFIG_SKIP_RELOCATE_UBOOT	/* to a proper address, init done */
 #define CONFIG_SYS_NAND_BASE		0x02000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
 #define CONFIG_SYS_NAND_HW_ECC
 #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices */
 #define CONFIG_ENV_OFFSET		0x0	/* Block 0--not used by bootcode */
-- 
cgit v1.3.1


From 2907798926ee932f453ac8538e7a6c05c18428a5 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri, 15 May 2009 23:47:13 +0200
Subject: arm920/926/926: remove non needed header

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/arm920t/cpu.c               |  1 -
 cpu/arm920t/imx/timer.c         |  1 -
 cpu/arm920t/interrupts.c        |  1 -
 cpu/arm920t/s3c24x0/timer.c     |  1 -
 cpu/arm926ejs/cpu.c             |  1 -
 cpu/arm926ejs/davinci/timer.c   |  1 -
 cpu/arm926ejs/nomadik/timer.c   |  1 -
 cpu/arm926ejs/omap/cpuinfo.c    |  1 -
 cpu/arm926ejs/omap/timer.c      |  1 -
 cpu/arm926ejs/versatile/timer.c |  1 -
 cpu/arm946es/cpu.c              |  1 -
 cpu/lh7a40x/cpu.c               |  1 -
 cpu/lh7a40x/timer.c             |  1 -
 include/arm920t.h               | 12 ------------
 include/arm926ejs.h             |  8 --------
 include/arm946es.h              |  8 --------
 16 files changed, 41 deletions(-)
 delete mode 100644 include/arm920t.h
 delete mode 100644 include/arm926ejs.h
 delete mode 100644 include/arm946es.h

(limited to 'include')

diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index 0c080fe3e4d..b6ef6bb8f5d 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -31,7 +31,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm920t.h>
 #include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
diff --git a/cpu/arm920t/imx/timer.c b/cpu/arm920t/imx/timer.c
index 280c6829405..31ec588d919 100644
--- a/cpu/arm920t/imx/timer.c
+++ b/cpu/arm920t/imx/timer.c
@@ -32,7 +32,6 @@
 #include <common.h>
 #if defined (CONFIG_IMX)
 
-#include <arm920t.h>
 #include <asm/arch/imx-regs.h>
 
 int timer_init (void)
diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c
index 1fbd1f0cc4a..ea24cdf68bd 100644
--- a/cpu/arm920t/interrupts.c
+++ b/cpu/arm920t/interrupts.c
@@ -30,7 +30,6 @@
  */
 
 #include <common.h>
-#include <arm920t.h>
 
 #ifdef CONFIG_USE_IRQ
 #include <asm/proc-armv/ptrace.h>
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index f3c0ed62cc8..f0a09cddff5 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -32,7 +32,6 @@
 #include <common.h>
 #if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
 
-#include <arm920t.h>
 #if defined(CONFIG_S3C2400)
 #include <s3c2400.h>
 #elif defined(CONFIG_S3C2410)
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 518c5e0b3fb..1f70a3603a8 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -31,7 +31,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm926ejs.h>
 #include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
diff --git a/cpu/arm926ejs/davinci/timer.c b/cpu/arm926ejs/davinci/timer.c
index 2604d57f320..80751add84e 100644
--- a/cpu/arm926ejs/davinci/timer.c
+++ b/cpu/arm926ejs/davinci/timer.c
@@ -38,7 +38,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 typedef volatile struct {
 	u_int32_t	pid12;
diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c
index 960cf52dfbc..2870d24ad54 100644
--- a/cpu/arm926ejs/nomadik/timer.c
+++ b/cpu/arm926ejs/nomadik/timer.c
@@ -37,7 +37,6 @@
 
 #include <common.h>
 #include <asm/io.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm926ejs/omap/cpuinfo.c b/cpu/arm926ejs/omap/cpuinfo.c
index 35ba7dba0f5..0052daba8ee 100644
--- a/cpu/arm926ejs/omap/cpuinfo.c
+++ b/cpu/arm926ejs/omap/cpuinfo.c
@@ -11,7 +11,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm926ejs.h>
 
 #if defined(CONFIG_DISPLAY_CPUINFO) && defined(CONFIG_OMAP)
 
diff --git a/cpu/arm926ejs/omap/timer.c b/cpu/arm926ejs/omap/timer.c
index 97f97712f4e..392b158d508 100644
--- a/cpu/arm926ejs/omap/timer.c
+++ b/cpu/arm926ejs/omap/timer.c
@@ -36,7 +36,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm926ejs/versatile/timer.c b/cpu/arm926ejs/versatile/timer.c
index 66976725747..50c13350a06 100755
--- a/cpu/arm926ejs/versatile/timer.c
+++ b/cpu/arm926ejs/versatile/timer.c
@@ -36,7 +36,6 @@
  */
 
 #include <common.h>
-#include <arm926ejs.h>
 
 #define TIMER_LOAD_VAL 0xffffffff
 
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index 04f051510df..d3195f9a22f 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -31,7 +31,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm946es.h>
 #include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 338df8769ef..be92f708b90 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -31,7 +31,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <arm920t.h>
 #include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
diff --git a/cpu/lh7a40x/timer.c b/cpu/lh7a40x/timer.c
index f0baf147379..f9b5be01042 100644
--- a/cpu/lh7a40x/timer.c
+++ b/cpu/lh7a40x/timer.c
@@ -30,7 +30,6 @@
  */
 
 #include <common.h>
-#include <arm920t.h>
 #include <lh7a40x.h>
 
 static ulong timer_load_val = 0;
diff --git a/include/arm920t.h b/include/arm920t.h
deleted file mode 100644
index 95f33235a0d..00000000000
--- a/include/arm920t.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/************************************************
- * NAME	    : arm920t.h
- * Version  : 30 April 2002			*
- *
- * empty for now
- ************************************************/
-
-#ifndef __ARM920T_H__
-#define __ARM920T_H__
-
-
-#endif /*__ARM920T_H__*/
diff --git a/include/arm926ejs.h b/include/arm926ejs.h
deleted file mode 100644
index c660265b7a7..00000000000
--- a/include/arm926ejs.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/************************************************
- * NAME                 arm926ejs.h             *
- * Version      :       23 June 2003            *
- ************************************************/
-/* Currently empty */
-#ifndef __ARM926EJS_H__
-#define __ARM926EJS_H__
-#endif /*__ARM926EJS_H__*/
diff --git a/include/arm946es.h b/include/arm946es.h
deleted file mode 100644
index c23f3e79c32..00000000000
--- a/include/arm946es.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/************************************************
- * NAME                 arm946es.h              *
- * $Version$                                    *
- ************************************************/
-/* Currently empty */
-#ifndef __ARM946ES_H__
-#define __ARM946ES_H__
-#endif /*__ARM946ES_H__*/
-- 
cgit v1.3.1


From 7893aa1eb6f52c3957efc301b436f1fa11e91a00 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Fri, 15 May 2009 23:47:13 +0200
Subject: ARM: Update mach-types

update against linux v2.6.29

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 include/asm-arm/mach-types.h | 1704 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 1697 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 2c1e69be340..9b8485d47e8 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h
@@ -1807,7 +1807,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_JADE                 1821
 #define MACH_TYPE_KS8695_SOFTPLC       1822
 #define MACH_TYPE_GPRISC3              1823
-#define MACH_TYPE_STAMP9260            1824
+#define MACH_TYPE_STAMP9G20            1824
 #define MACH_TYPE_SMDK6430             1825
 #define MACH_TYPE_SMDKC100             1826
 #define MACH_TYPE_TAVOREVB             1827
@@ -1990,6 +1990,136 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_BLAZE                2004
 #define MACH_TYPE_LINKSTATION_LS_HGL   2005
 #define MACH_TYPE_HTCVENUS             2006
+#define MACH_TYPE_SONY_PRS505          2007
+#define MACH_TYPE_HANLIN_V3            2008
+#define MACH_TYPE_SAPPHIRA             2009
+#define MACH_TYPE_DACK_SDA_01          2010
+#define MACH_TYPE_ARMBOX               2011
+#define MACH_TYPE_HARRIS_RVP           2012
+#define MACH_TYPE_RIBALDO              2013
+#define MACH_TYPE_AGORA                2014
+#define MACH_TYPE_OMAP3_MINI           2015
+#define MACH_TYPE_A9SAM6432_B          2016
+#define MACH_TYPE_USG2410              2017
+#define MACH_TYPE_PC72052_I10_REVB     2018
+#define MACH_TYPE_MX35_EXM32           2019
+#define MACH_TYPE_TOPAS910             2020
+#define MACH_TYPE_HYENA                2021
+#define MACH_TYPE_POSPAX               2022
+#define MACH_TYPE_HDL_GX               2023
+#define MACH_TYPE_CTERA_4BAY           2024
+#define MACH_TYPE_CTERA_PLUG_C         2025
+#define MACH_TYPE_CRWEA_PLUG_I         2026
+#define MACH_TYPE_EGAUGE2              2027
+#define MACH_TYPE_DIDJ                 2028
+#define MACH_TYPE_MEISTER              2029
+#define MACH_TYPE_HTCBLACKSTONE        2030
+#define MACH_TYPE_CPUAT9G20            2031
+#define MACH_TYPE_SMDK6440             2032
+#define MACH_TYPE_OMAP_35XX_MVP        2033
+#define MACH_TYPE_CTERA_PLUG_I         2034
+#define MACH_TYPE_PVG610               2035
+#define MACH_TYPE_HPRW6815             2036
+#define MACH_TYPE_OMAP3_OSWALD         2037
+#define MACH_TYPE_NAS4220B             2038
+#define MACH_TYPE_HTCRAPHAEL_CDMA      2039
+#define MACH_TYPE_HTCDIAMOND_CDMA      2040
+#define MACH_TYPE_SCALER               2041
+#define MACH_TYPE_ZYLONITE2            2042
+#define MACH_TYPE_ASPENITE             2043
+#define MACH_TYPE_TETON                2044
+#define MACH_TYPE_TTC_DKB              2045
+#define MACH_TYPE_BISHOP2              2046
+#define MACH_TYPE_IPPV5                2047
+#define MACH_TYPE_FARM926              2048
+#define MACH_TYPE_MMCCPU               2049
+#define MACH_TYPE_SGMSFL               2050
+#define MACH_TYPE_TT8000               2051
+#define MACH_TYPE_ZRN4300LP            2052
+#define MACH_TYPE_MPTC                 2053
+#define MACH_TYPE_H6051                2054
+#define MACH_TYPE_PVG610_101           2055
+#define MACH_TYPE_STAMP9261_PC_EVB     2056
+#define MACH_TYPE_PELCO_ODYSSEUS       2057
+#define MACH_TYPE_TNY_A9260            2058
+#define MACH_TYPE_TNY_A9G20            2059
+#define MACH_TYPE_AESOP_MP2530F        2060
+#define MACH_TYPE_DX900                2061
+#define MACH_TYPE_CPODC2               2062
+#define MACH_TYPE_TILT_8925            2063
+#define MACH_TYPE_DAVINCI_DM357_EVM    2064
+#define MACH_TYPE_SWORDFISH            2065
+#define MACH_TYPE_CORVUS               2066
+#define MACH_TYPE_TAURUS               2067
+#define MACH_TYPE_AXM                  2068
+#define MACH_TYPE_AXC                  2069
+#define MACH_TYPE_BABY                 2070
+#define MACH_TYPE_MP200                2071
+#define MACH_TYPE_PCM043               2072
+#define MACH_TYPE_HANLIN_V3C           2073
+#define MACH_TYPE_KBK9G20              2074
+#define MACH_TYPE_ADSTURBOG5           2075
+#define MACH_TYPE_AVENGER_LITE1        2076
+#define MACH_TYPE_SUC                  2077
+#define MACH_TYPE_AT91SAM7S256         2078
+#define MACH_TYPE_MENDOZA              2079
+#define MACH_TYPE_KIRA                 2080
+#define MACH_TYPE_MX1HBM               2081
+#define MACH_TYPE_QUATRO43XX           2082
+#define MACH_TYPE_QUATRO4230           2083
+#define MACH_TYPE_NSB400               2084
+#define MACH_TYPE_DRP255               2085
+#define MACH_TYPE_THOTH                2086
+#define MACH_TYPE_FIRESTONE            2087
+#define MACH_TYPE_ASUSP750             2088
+#define MACH_TYPE_CTERA_DL             2089
+#define MACH_TYPE_SOCR                 2090
+#define MACH_TYPE_HTCOXYGEN            2091
+#define MACH_TYPE_HEROC                2092
+#define MACH_TYPE_ZENO6800             2093
+#define MACH_TYPE_SC2MCS               2094
+#define MACH_TYPE_GENE100              2095
+#define MACH_TYPE_AS353X               2096
+#define MACH_TYPE_SHEEVAPLUG           2097
+#define MACH_TYPE_AT91SAM9G20          2098
+#define MACH_TYPE_MV88F6192GTW_FE      2099
+#define MACH_TYPE_CC9200               2100
+#define MACH_TYPE_SM9200               2101
+#define MACH_TYPE_TP9200               2102
+#define MACH_TYPE_SNAPPERDV            2103
+#define MACH_TYPE_AVENGERS_LITE        2104
+#define MACH_TYPE_AVENGERS_LITE1       2105
+#define MACH_TYPE_OMAP3AXON            2106
+#define MACH_TYPE_MA8XX                2107
+#define MACH_TYPE_MP201EK              2108
+#define MACH_TYPE_DAVINCI_TUX          2109
+#define MACH_TYPE_MPA1600              2110
+#define MACH_TYPE_PELCO_TROY           2111
+#define MACH_TYPE_NSB667               2112
+#define MACH_TYPE_ROVERS5_4MPIX        2113
+#define MACH_TYPE_TWOCOM               2114
+#define MACH_TYPE_UBISYS_P9_RCU3R2     2115
+#define MACH_TYPE_HERO_ESPRESSO        2116
+#define MACH_TYPE_AFEUSB               2117
+#define MACH_TYPE_T830                 2118
+#define MACH_TYPE_SPD8020_CC           2119
+#define MACH_TYPE_OM_3D7K              2120
+#define MACH_TYPE_PICOCOM2             2121
+#define MACH_TYPE_UWG4MX27             2122
+#define MACH_TYPE_UWG4MX31             2123
+#define MACH_TYPE_CHERRY               2124
+#define MACH_TYPE_MX51_BABBAGE         2125
+#define MACH_TYPE_S3C2440TURKIYE       2126
+#define MACH_TYPE_TX37                 2127
+#define MACH_TYPE_SBC2800_9G20         2128
+#define MACH_TYPE_BENZGLB              2129
+#define MACH_TYPE_BENZTD               2130
+#define MACH_TYPE_CARTESIO_PLUS        2131
+#define MACH_TYPE_SOLRAD_G20           2132
+#define MACH_TYPE_MX27WALLACE          2133
+#define MACH_TYPE_FMZWEBMODUL          2134
+#define MACH_TYPE_RD78X00_MASA         2135
+#define MACH_TYPE_SMALLOGGER           2136
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -23531,16 +23661,16 @@ extern unsigned int __machine_arch_type;
 # define machine_is_gprisc3()	(0)
 #endif
 
-#ifdef CONFIG_MACH_STAMP9260
+#ifdef CONFIG_MACH_STAMP9G20
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_STAMP9260
+#  define machine_arch_type	MACH_TYPE_STAMP9G20
 # endif
-# define machine_is_stamp9260()	(machine_arch_type == MACH_TYPE_STAMP9260)
+# define machine_is_stamp9g20()	(machine_arch_type == MACH_TYPE_STAMP9G20)
 #else
-# define machine_is_stamp9260()	(0)
+# define machine_is_stamp9g20()	(0)
 #endif
 
 #ifdef CONFIG_MACH_SMDK6430
@@ -25722,9 +25852,1569 @@ extern unsigned int __machine_arch_type;
 # else
 #  define machine_arch_type	MACH_TYPE_HTCVENUS
 # endif
-# define machine_is_htcvenus()	(machine_arch_type == MACH_TYPE_HTCVENUS)
+# define machine_is_htckovsky()	(machine_arch_type == MACH_TYPE_HTCVENUS)
 #else
-# define machine_is_htcvenus()	(0)
+# define machine_is_htckovsky()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SONY_PRS505
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SONY_PRS505
+# endif
+# define machine_is_sony_prs505()	(machine_arch_type == MACH_TYPE_SONY_PRS505)
+#else
+# define machine_is_sony_prs505()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HANLIN_V3
+# endif
+# define machine_is_hanlin_v3()	(machine_arch_type == MACH_TYPE_HANLIN_V3)
+#else
+# define machine_is_hanlin_v3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SAPPHIRA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SAPPHIRA
+# endif
+# define machine_is_sapphira()	(machine_arch_type == MACH_TYPE_SAPPHIRA)
+#else
+# define machine_is_sapphira()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DACK_SDA_01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DACK_SDA_01
+# endif
+# define machine_is_dack_sda_01()	(machine_arch_type == MACH_TYPE_DACK_SDA_01)
+#else
+# define machine_is_dack_sda_01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMBOX
+# endif
+# define machine_is_armbox()	(machine_arch_type == MACH_TYPE_ARMBOX)
+#else
+# define machine_is_armbox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HARRIS_RVP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HARRIS_RVP
+# endif
+# define machine_is_harris_rvp()	(machine_arch_type == MACH_TYPE_HARRIS_RVP)
+#else
+# define machine_is_harris_rvp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIBALDO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIBALDO
+# endif
+# define machine_is_ribaldo()	(machine_arch_type == MACH_TYPE_RIBALDO)
+#else
+# define machine_is_ribaldo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AGORA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AGORA
+# endif
+# define machine_is_agora()	(machine_arch_type == MACH_TYPE_AGORA)
+#else
+# define machine_is_agora()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_MINI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_MINI
+# endif
+# define machine_is_omap3_mini()	(machine_arch_type == MACH_TYPE_OMAP3_MINI)
+#else
+# define machine_is_omap3_mini()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A9SAM6432_B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A9SAM6432_B
+# endif
+# define machine_is_a9sam6432_b()	(machine_arch_type == MACH_TYPE_A9SAM6432_B)
+#else
+# define machine_is_a9sam6432_b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_USG2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_USG2410
+# endif
+# define machine_is_usg2410()	(machine_arch_type == MACH_TYPE_USG2410)
+#else
+# define machine_is_usg2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC72052_I10_REVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC72052_I10_REVB
+# endif
+# define machine_is_pc72052_i10_revb()	(machine_arch_type == MACH_TYPE_PC72052_I10_REVB)
+#else
+# define machine_is_pc72052_i10_revb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX35_EXM32
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX35_EXM32
+# endif
+# define machine_is_mx35_exm32()	(machine_arch_type == MACH_TYPE_MX35_EXM32)
+#else
+# define machine_is_mx35_exm32()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOPAS910
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOPAS910
+# endif
+# define machine_is_topas910()	(machine_arch_type == MACH_TYPE_TOPAS910)
+#else
+# define machine_is_topas910()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HYENA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HYENA
+# endif
+# define machine_is_hyena()	(machine_arch_type == MACH_TYPE_HYENA)
+#else
+# define machine_is_hyena()	(0)
+#endif
+
+#ifdef CONFIG_MACH_POSPAX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_POSPAX
+# endif
+# define machine_is_pospax()	(machine_arch_type == MACH_TYPE_POSPAX)
+#else
+# define machine_is_pospax()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HDL_GX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HDL_GX
+# endif
+# define machine_is_hdl_gx()	(machine_arch_type == MACH_TYPE_HDL_GX)
+#else
+# define machine_is_hdl_gx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_4BAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_4BAY
+# endif
+# define machine_is_ctera_4bay()	(machine_arch_type == MACH_TYPE_CTERA_4BAY)
+#else
+# define machine_is_ctera_4bay()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_C
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_C
+# endif
+# define machine_is_ctera_plug_c()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_C)
+#else
+# define machine_is_ctera_plug_c()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CRWEA_PLUG_I
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CRWEA_PLUG_I
+# endif
+# define machine_is_crwea_plug_i()	(machine_arch_type == MACH_TYPE_CRWEA_PLUG_I)
+#else
+# define machine_is_crwea_plug_i()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EGAUGE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EGAUGE2
+# endif
+# define machine_is_egauge2()	(machine_arch_type == MACH_TYPE_EGAUGE2)
+#else
+# define machine_is_egauge2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DIDJ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DIDJ
+# endif
+# define machine_is_didj()	(machine_arch_type == MACH_TYPE_DIDJ)
+#else
+# define machine_is_didj()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MEISTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MEISTER
+# endif
+# define machine_is_m_s3c2443()	(machine_arch_type == MACH_TYPE_MEISTER)
+#else
+# define machine_is_m_s3c2443()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCBLACKSTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCBLACKSTONE
+# endif
+# define machine_is_htcblackstone()	(machine_arch_type == MACH_TYPE_HTCBLACKSTONE)
+#else
+# define machine_is_htcblackstone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPUAT9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPUAT9G20
+# endif
+# define machine_is_cpuat9g20()	(machine_arch_type == MACH_TYPE_CPUAT9G20)
+#else
+# define machine_is_cpuat9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6440
+# endif
+# define machine_is_smdk6440()	(machine_arch_type == MACH_TYPE_SMDK6440)
+#else
+# define machine_is_smdk6440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_35XX_MVP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_35XX_MVP
+# endif
+# define machine_is_omap_35xx_mvp()	(machine_arch_type == MACH_TYPE_OMAP_35XX_MVP)
+#else
+# define machine_is_omap_35xx_mvp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_PLUG_I
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_PLUG_I
+# endif
+# define machine_is_ctera_plug_i()	(machine_arch_type == MACH_TYPE_CTERA_PLUG_I)
+#else
+# define machine_is_ctera_plug_i()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PVG610
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PVG610
+# endif
+# define machine_is_pvg610_100()	(machine_arch_type == MACH_TYPE_PVG610)
+#else
+# define machine_is_pvg610_100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HPRW6815
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HPRW6815
+# endif
+# define machine_is_hprw6815()	(machine_arch_type == MACH_TYPE_HPRW6815)
+#else
+# define machine_is_hprw6815()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_OSWALD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_OSWALD
+# endif
+# define machine_is_omap3_oswald()	(machine_arch_type == MACH_TYPE_OMAP3_OSWALD)
+#else
+# define machine_is_omap3_oswald()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NAS4220B
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NAS4220B
+# endif
+# define machine_is_nas4220b()	(machine_arch_type == MACH_TYPE_NAS4220B)
+#else
+# define machine_is_nas4220b()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCRAPHAEL_CDMA
+# endif
+# define machine_is_htcraphael_cdma()	(machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA)
+#else
+# define machine_is_htcraphael_cdma()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCDIAMOND_CDMA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCDIAMOND_CDMA
+# endif
+# define machine_is_htcdiamond_cdma()	(machine_arch_type == MACH_TYPE_HTCDIAMOND_CDMA)
+#else
+# define machine_is_htcdiamond_cdma()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCALER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCALER
+# endif
+# define machine_is_scaler()	(machine_arch_type == MACH_TYPE_SCALER)
+#else
+# define machine_is_scaler()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZYLONITE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZYLONITE2
+# endif
+# define machine_is_zylonite2()	(machine_arch_type == MACH_TYPE_ZYLONITE2)
+#else
+# define machine_is_zylonite2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASPENITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASPENITE
+# endif
+# define machine_is_aspenite()	(machine_arch_type == MACH_TYPE_ASPENITE)
+#else
+# define machine_is_aspenite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TETON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TETON
+# endif
+# define machine_is_teton()	(machine_arch_type == MACH_TYPE_TETON)
+#else
+# define machine_is_teton()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TTC_DKB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TTC_DKB
+# endif
+# define machine_is_ttc_dkb()	(machine_arch_type == MACH_TYPE_TTC_DKB)
+#else
+# define machine_is_ttc_dkb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BISHOP2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BISHOP2
+# endif
+# define machine_is_bishop2()	(machine_arch_type == MACH_TYPE_BISHOP2)
+#else
+# define machine_is_bishop2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IPPV5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IPPV5
+# endif
+# define machine_is_ippv5()	(machine_arch_type == MACH_TYPE_IPPV5)
+#else
+# define machine_is_ippv5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FARM926
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FARM926
+# endif
+# define machine_is_farm926()	(machine_arch_type == MACH_TYPE_FARM926)
+#else
+# define machine_is_farm926()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MMCCPU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MMCCPU
+# endif
+# define machine_is_mmccpu()	(machine_arch_type == MACH_TYPE_MMCCPU)
+#else
+# define machine_is_mmccpu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SGMSFL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SGMSFL
+# endif
+# define machine_is_sgmsfl()	(machine_arch_type == MACH_TYPE_SGMSFL)
+#else
+# define machine_is_sgmsfl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TT8000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TT8000
+# endif
+# define machine_is_tt8000()	(machine_arch_type == MACH_TYPE_TT8000)
+#else
+# define machine_is_tt8000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZRN4300LP
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZRN4300LP
+# endif
+# define machine_is_zrn4300lp()	(machine_arch_type == MACH_TYPE_ZRN4300LP)
+#else
+# define machine_is_zrn4300lp()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MPTC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPTC
+# endif
+# define machine_is_mptc()	(machine_arch_type == MACH_TYPE_MPTC)
+#else
+# define machine_is_mptc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_H6051
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_H6051
+# endif
+# define machine_is_h6051()	(machine_arch_type == MACH_TYPE_H6051)
+#else
+# define machine_is_h6051()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PVG610_101
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PVG610_101
+# endif
+# define machine_is_pvg610_101()	(machine_arch_type == MACH_TYPE_PVG610_101)
+#else
+# define machine_is_pvg610_101()	(0)
+#endif
+
+#ifdef CONFIG_MACH_STAMP9261_PC_EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_STAMP9261_PC_EVB
+# endif
+# define machine_is_stamp9261_pc_evb()	(machine_arch_type == MACH_TYPE_STAMP9261_PC_EVB)
+#else
+# define machine_is_stamp9261_pc_evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_ODYSSEUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PELCO_ODYSSEUS
+# endif
+# define machine_is_pelco_odysseus()	(machine_arch_type == MACH_TYPE_PELCO_ODYSSEUS)
+#else
+# define machine_is_pelco_odysseus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_A9260
+# endif
+# define machine_is_tny_a9260()	(machine_arch_type == MACH_TYPE_TNY_A9260)
+#else
+# define machine_is_tny_a9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNY_A9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNY_A9G20
+# endif
+# define machine_is_tny_a9g20()	(machine_arch_type == MACH_TYPE_TNY_A9G20)
+#else
+# define machine_is_tny_a9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AESOP_MP2530F
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AESOP_MP2530F
+# endif
+# define machine_is_aesop_mp2530f()	(machine_arch_type == MACH_TYPE_AESOP_MP2530F)
+#else
+# define machine_is_aesop_mp2530f()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DX900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DX900
+# endif
+# define machine_is_dx900()	(machine_arch_type == MACH_TYPE_DX900)
+#else
+# define machine_is_dx900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CPODC2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CPODC2
+# endif
+# define machine_is_cpodc2()	(machine_arch_type == MACH_TYPE_CPODC2)
+#else
+# define machine_is_cpodc2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TILT_8925
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TILT_8925
+# endif
+# define machine_is_tilt_8925()	(machine_arch_type == MACH_TYPE_TILT_8925)
+#else
+# define machine_is_tilt_8925()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_DM357_EVM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DM357_EVM
+# endif
+# define machine_is_davinci_dm357_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DM357_EVM)
+#else
+# define machine_is_davinci_dm357_evm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SWORDFISH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SWORDFISH
+# endif
+# define machine_is_swordfish()	(machine_arch_type == MACH_TYPE_SWORDFISH)
+#else
+# define machine_is_swordfish()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CORVUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CORVUS
+# endif
+# define machine_is_corvus()	(machine_arch_type == MACH_TYPE_CORVUS)
+#else
+# define machine_is_corvus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAURUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAURUS
+# endif
+# define machine_is_taurus()	(machine_arch_type == MACH_TYPE_TAURUS)
+#else
+# define machine_is_taurus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AXM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXM
+# endif
+# define machine_is_axm()	(machine_arch_type == MACH_TYPE_AXM)
+#else
+# define machine_is_axm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AXC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AXC
+# endif
+# define machine_is_axc()	(machine_arch_type == MACH_TYPE_AXC)
+#else
+# define machine_is_axc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BABY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BABY
+# endif
+# define machine_is_baby()	(machine_arch_type == MACH_TYPE_BABY)
+#else
+# define machine_is_baby()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MP200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MP200
+# endif
+# define machine_is_mp200()	(machine_arch_type == MACH_TYPE_MP200)
+#else
+# define machine_is_mp200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PCM043
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PCM043
+# endif
+# define machine_is_pcm043()	(machine_arch_type == MACH_TYPE_PCM043)
+#else
+# define machine_is_pcm043()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HANLIN_V3C
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HANLIN_V3C
+# endif
+# define machine_is_hanlin_v3c()	(machine_arch_type == MACH_TYPE_HANLIN_V3C)
+#else
+# define machine_is_hanlin_v3c()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KBK9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KBK9G20
+# endif
+# define machine_is_kbk9g20()	(machine_arch_type == MACH_TYPE_KBK9G20)
+#else
+# define machine_is_kbk9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ADSTURBOG5
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ADSTURBOG5
+# endif
+# define machine_is_adsturbog5()	(machine_arch_type == MACH_TYPE_ADSTURBOG5)
+#else
+# define machine_is_adsturbog5()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVENGER_LITE1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVENGER_LITE1
+# endif
+# define machine_is_avenger_lite1()	(machine_arch_type == MACH_TYPE_AVENGER_LITE1)
+#else
+# define machine_is_avenger_lite1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SUC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SUC
+# endif
+# define machine_is_suc82x()	(machine_arch_type == MACH_TYPE_SUC)
+#else
+# define machine_is_suc82x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM7S256
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM7S256
+# endif
+# define machine_is_at91sam7s256()	(machine_arch_type == MACH_TYPE_AT91SAM7S256)
+#else
+# define machine_is_at91sam7s256()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MENDOZA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MENDOZA
+# endif
+# define machine_is_mendoza()	(machine_arch_type == MACH_TYPE_MENDOZA)
+#else
+# define machine_is_mendoza()	(0)
+#endif
+
+#ifdef CONFIG_MACH_KIRA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_KIRA
+# endif
+# define machine_is_kira()	(machine_arch_type == MACH_TYPE_KIRA)
+#else
+# define machine_is_kira()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX1HBM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX1HBM
+# endif
+# define machine_is_mx1hbm()	(machine_arch_type == MACH_TYPE_MX1HBM)
+#else
+# define machine_is_mx1hbm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QUATRO43XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUATRO43XX
+# endif
+# define machine_is_quatro43xx()	(machine_arch_type == MACH_TYPE_QUATRO43XX)
+#else
+# define machine_is_quatro43xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_QUATRO4230
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_QUATRO4230
+# endif
+# define machine_is_quatro4230()	(machine_arch_type == MACH_TYPE_QUATRO4230)
+#else
+# define machine_is_quatro4230()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSB400
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSB400
+# endif
+# define machine_is_nsb400()	(machine_arch_type == MACH_TYPE_NSB400)
+#else
+# define machine_is_nsb400()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DRP255
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DRP255
+# endif
+# define machine_is_drp255()	(machine_arch_type == MACH_TYPE_DRP255)
+#else
+# define machine_is_drp255()	(0)
+#endif
+
+#ifdef CONFIG_MACH_THOTH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_THOTH
+# endif
+# define machine_is_thoth()	(machine_arch_type == MACH_TYPE_THOTH)
+#else
+# define machine_is_thoth()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FIRESTONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FIRESTONE
+# endif
+# define machine_is_firestone()	(machine_arch_type == MACH_TYPE_FIRESTONE)
+#else
+# define machine_is_firestone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ASUSP750
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ASUSP750
+# endif
+# define machine_is_asusp750()	(machine_arch_type == MACH_TYPE_ASUSP750)
+#else
+# define machine_is_asusp750()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CTERA_DL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CTERA_DL
+# endif
+# define machine_is_ctera_dl()	(machine_arch_type == MACH_TYPE_CTERA_DL)
+#else
+# define machine_is_ctera_dl()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOCR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOCR
+# endif
+# define machine_is_socr()	(machine_arch_type == MACH_TYPE_SOCR)
+#else
+# define machine_is_socr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCOXYGEN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCOXYGEN
+# endif
+# define machine_is_htcoxygen()	(machine_arch_type == MACH_TYPE_HTCOXYGEN)
+#else
+# define machine_is_htcoxygen()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HEROC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HEROC
+# endif
+# define machine_is_heroc()	(machine_arch_type == MACH_TYPE_HEROC)
+#else
+# define machine_is_heroc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZENO6800
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZENO6800
+# endif
+# define machine_is_zeno6800()	(machine_arch_type == MACH_TYPE_ZENO6800)
+#else
+# define machine_is_zeno6800()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SC2MCS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SC2MCS
+# endif
+# define machine_is_sc2mcs()	(machine_arch_type == MACH_TYPE_SC2MCS)
+#else
+# define machine_is_sc2mcs()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GENE100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GENE100
+# endif
+# define machine_is_gene100()	(machine_arch_type == MACH_TYPE_GENE100)
+#else
+# define machine_is_gene100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AS353X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AS353X
+# endif
+# define machine_is_as353x()	(machine_arch_type == MACH_TYPE_AS353X)
+#else
+# define machine_is_as353x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SHEEVAPLUG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SHEEVAPLUG
+# endif
+# define machine_is_sheevaplug()	(machine_arch_type == MACH_TYPE_SHEEVAPLUG)
+#else
+# define machine_is_sheevaplug()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G20
+# endif
+# define machine_is_at91sam9g20()	(machine_arch_type == MACH_TYPE_AT91SAM9G20)
+#else
+# define machine_is_at91sam9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MV88F6192GTW_FE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MV88F6192GTW_FE
+# endif
+# define machine_is_mv88f6192gtw_fe()	(machine_arch_type == MACH_TYPE_MV88F6192GTW_FE)
+#else
+# define machine_is_mv88f6192gtw_fe()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CC9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CC9200
+# endif
+# define machine_is_cc9200()	(machine_arch_type == MACH_TYPE_CC9200)
+#else
+# define machine_is_cc9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SM9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SM9200
+# endif
+# define machine_is_sm9200()	(machine_arch_type == MACH_TYPE_SM9200)
+#else
+# define machine_is_sm9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TP9200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TP9200
+# endif
+# define machine_is_tp9200()	(machine_arch_type == MACH_TYPE_TP9200)
+#else
+# define machine_is_tp9200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SNAPPERDV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SNAPPERDV
+# endif
+# define machine_is_snapperdv()	(machine_arch_type == MACH_TYPE_SNAPPERDV)
+#else
+# define machine_is_snapperdv()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVENGERS_LITE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVENGERS_LITE
+# endif
+# define machine_is_avengers_lite()	(machine_arch_type == MACH_TYPE_AVENGERS_LITE)
+#else
+# define machine_is_avengers_lite()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AVENGERS_LITE1
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AVENGERS_LITE1
+# endif
+# define machine_is_avengers_lite1()	(machine_arch_type == MACH_TYPE_AVENGERS_LITE1)
+#else
+# define machine_is_avengers_lite1()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3AXON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3AXON
+# endif
+# define machine_is_omap3axon()	(machine_arch_type == MACH_TYPE_OMAP3AXON)
+#else
+# define machine_is_omap3axon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MA8XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MA8XX
+# endif
+# define machine_is_ma8xx()	(machine_arch_type == MACH_TYPE_MA8XX)
+#else
+# define machine_is_ma8xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MP201EK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MP201EK
+# endif
+# define machine_is_mp201ek()	(machine_arch_type == MACH_TYPE_MP201EK)
+#else
+# define machine_is_mp201ek()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_TUX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_TUX
+# endif
+# define machine_is_davinci_tux()	(machine_arch_type == MACH_TYPE_DAVINCI_TUX)
+#else
+# define machine_is_davinci_tux()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MPA1600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MPA1600
+# endif
+# define machine_is_mpa1600()	(machine_arch_type == MACH_TYPE_MPA1600)
+#else
+# define machine_is_mpa1600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_TROY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PELCO_TROY
+# endif
+# define machine_is_pelco_troy()	(machine_arch_type == MACH_TYPE_PELCO_TROY)
+#else
+# define machine_is_pelco_troy()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NSB667
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NSB667
+# endif
+# define machine_is_nsb667()	(machine_arch_type == MACH_TYPE_NSB667)
+#else
+# define machine_is_nsb667()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ROVERS5_4MPIX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ROVERS5_4MPIX
+# endif
+# define machine_is_rovers5_4mpix()	(machine_arch_type == MACH_TYPE_ROVERS5_4MPIX)
+#else
+# define machine_is_rovers5_4mpix()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TWOCOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TWOCOM
+# endif
+# define machine_is_twocom()	(machine_arch_type == MACH_TYPE_TWOCOM)
+#else
+# define machine_is_twocom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UBISYS_P9_RCU3R2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UBISYS_P9_RCU3R2
+# endif
+# define machine_is_ubisys_p9_rcu3r2()	(machine_arch_type == MACH_TYPE_UBISYS_P9_RCU3R2)
+#else
+# define machine_is_ubisys_p9_rcu3r2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HERO_ESPRESSO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HERO_ESPRESSO
+# endif
+# define machine_is_hero_espresso()	(machine_arch_type == MACH_TYPE_HERO_ESPRESSO)
+#else
+# define machine_is_hero_espresso()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AFEUSB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AFEUSB
+# endif
+# define machine_is_afeusb()	(machine_arch_type == MACH_TYPE_AFEUSB)
+#else
+# define machine_is_afeusb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_T830
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_T830
+# endif
+# define machine_is_t830()	(machine_arch_type == MACH_TYPE_T830)
+#else
+# define machine_is_t830()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SPD8020_CC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SPD8020_CC
+# endif
+# define machine_is_spd8020_cc()	(machine_arch_type == MACH_TYPE_SPD8020_CC)
+#else
+# define machine_is_spd8020_cc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OM_3D7K
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OM_3D7K
+# endif
+# define machine_is_om_3d7k()	(machine_arch_type == MACH_TYPE_OM_3D7K)
+#else
+# define machine_is_om_3d7k()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PICOCOM2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PICOCOM2
+# endif
+# define machine_is_picocom2()	(machine_arch_type == MACH_TYPE_PICOCOM2)
+#else
+# define machine_is_picocom2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UWG4MX27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UWG4MX27
+# endif
+# define machine_is_uwg4mx27()	(machine_arch_type == MACH_TYPE_UWG4MX27)
+#else
+# define machine_is_uwg4mx27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_UWG4MX31
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_UWG4MX31
+# endif
+# define machine_is_uwg4mx31()	(machine_arch_type == MACH_TYPE_UWG4MX31)
+#else
+# define machine_is_uwg4mx31()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CHERRY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CHERRY
+# endif
+# define machine_is_cherry()	(machine_arch_type == MACH_TYPE_CHERRY)
+#else
+# define machine_is_cherry()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_BABBAGE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_BABBAGE
+# endif
+# define machine_is_mx51_babbage()	(machine_arch_type == MACH_TYPE_MX51_BABBAGE)
+#else
+# define machine_is_mx51_babbage()	(0)
+#endif
+
+#ifdef CONFIG_MACH_S3C2440TURKIYE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_S3C2440TURKIYE
+# endif
+# define machine_is_s3c2440turkiye()	(machine_arch_type == MACH_TYPE_S3C2440TURKIYE)
+#else
+# define machine_is_s3c2440turkiye()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TX37
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TX37
+# endif
+# define machine_is_tx37()	(machine_arch_type == MACH_TYPE_TX37)
+#else
+# define machine_is_tx37()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBC2800_9G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBC2800_9G20
+# endif
+# define machine_is_sbc2800_9g20()	(machine_arch_type == MACH_TYPE_SBC2800_9G20)
+#else
+# define machine_is_sbc2800_9g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BENZGLB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BENZGLB
+# endif
+# define machine_is_benzglb()	(machine_arch_type == MACH_TYPE_BENZGLB)
+#else
+# define machine_is_benzglb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BENZTD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BENZTD
+# endif
+# define machine_is_benztd()	(machine_arch_type == MACH_TYPE_BENZTD)
+#else
+# define machine_is_benztd()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CARTESIO_PLUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CARTESIO_PLUS
+# endif
+# define machine_is_cartesio_plus()	(machine_arch_type == MACH_TYPE_CARTESIO_PLUS)
+#else
+# define machine_is_cartesio_plus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SOLRAD_G20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SOLRAD_G20
+# endif
+# define machine_is_solrad_g20()	(machine_arch_type == MACH_TYPE_SOLRAD_G20)
+#else
+# define machine_is_solrad_g20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX27WALLACE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX27WALLACE
+# endif
+# define machine_is_mx27wallace()	(machine_arch_type == MACH_TYPE_MX27WALLACE)
+#else
+# define machine_is_mx27wallace()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FMZWEBMODUL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FMZWEBMODUL
+# endif
+# define machine_is_fmzwebmodul()	(machine_arch_type == MACH_TYPE_FMZWEBMODUL)
+#else
+# define machine_is_fmzwebmodul()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RD78X00_MASA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RD78X00_MASA
+# endif
+# define machine_is_rd78x00_masa()	(machine_arch_type == MACH_TYPE_RD78X00_MASA)
+#else
+# define machine_is_rd78x00_masa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMALLOGGER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMALLOGGER
+# endif
+# define machine_is_smallogger()	(machine_arch_type == MACH_TYPE_SMALLOGGER)
+#else
+# define machine_is_smallogger()	(0)
 #endif
 
 /*
-- 
cgit v1.3.1


From 376aee78dd66ae0dc4ce496cbe93ecc80aaad48e Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Fri, 15 May 2009 23:48:36 +0200
Subject: ZOOM2 Add initial support for Zoom2

Zoom2 is a new board from Texas Instruments and LogicPD

The logicpd web site is a good source for general information on this board.
Please start looking here if the below links are broken.
http://www.logicpd.com

This is a pdf of the product
http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
This is the product description web page
http://www.logicpd.com/products/development-kits/texas-instruments-zoom%E2%84%A2-omap34x-ii-mdp

This patch provides a zoom2 base target by copying zoom1 and by making some
obvious changes.

To configure, run
make omap3_zoom2_config

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 MAINTAINERS                   |   4 +
 MAKEALL                       |   1 +
 Makefile                      |   3 +
 board/omap3/common/Makefile   |   1 +
 board/omap3/zoom2/Makefile    |  49 +++++++++
 board/omap3/zoom2/config.mk   |  33 ++++++
 board/omap3/zoom2/zoom2.c     |  76 ++++++++++++++
 board/omap3/zoom2/zoom2.h     | 149 ++++++++++++++++++++++++++++
 doc/README.omap3              |  15 ++-
 include/configs/omap3_zoom2.h | 226 ++++++++++++++++++++++++++++++++++++++++++
 10 files changed, 555 insertions(+), 2 deletions(-)
 create mode 100644 board/omap3/zoom2/Makefile
 create mode 100644 board/omap3/zoom2/config.mk
 create mode 100644 board/omap3/zoom2/zoom2.c
 create mode 100644 board/omap3/zoom2/zoom2.h
 create mode 100644 include/configs/omap3_zoom2.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 3d5066877b4..bf076b97152 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -610,6 +610,10 @@ Stelian Pop <stelian.pop@leadtechdesign.com>
 	at91sam9263ek	ARM926EJS (AT91SAM9263 SoC)
 	at91sam9rlek	ARM926EJS (AT91SAM9RL SoC)
 
+Tom Rix <Tom.Rix@windriver.com>
+
+	omap3_zoom2	ARM CORTEX-A8 (OMAP3xx SoC)
+
 Stefan Roese <sr@denx.de>
 
 	ixdpg425	xscale
diff --git a/MAKEALL b/MAKEALL
index 57dd42539f0..9b48773bc88 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -562,6 +562,7 @@ LIST_ARM_CORTEX_A8="		\
 	omap3_evm		\
 	omap3_pandora		\
 	omap3_zoom1		\
+	omap3_zoom2		\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 10f6b1f49fc..cf140a4d33b 100644
--- a/Makefile
+++ b/Makefile
@@ -2994,6 +2994,9 @@ omap3_pandora_config :	unconfig
 omap3_zoom1_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 omap3 omap3
 
+omap3_zoom2_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 omap3 omap3
+
 #########################################################################
 ## XScale Systems
 #########################################################################
diff --git a/board/omap3/common/Makefile b/board/omap3/common/Makefile
index 7b892fab811..b8a0b14a011 100644
--- a/board/omap3/common/Makefile
+++ b/board/omap3/common/Makefile
@@ -33,6 +33,7 @@ COBJS-$(CONFIG_OMAP3_BEAGLE) += power.o
 COBJS-$(CONFIG_OMAP3_OVERO) += power.o
 COBJS-$(CONFIG_OMAP3_PANDORA) += power.o
 COBJS-$(CONFIG_OMAP3_ZOOM1) += power.o
+COBJS-$(CONFIG_OMAP3_ZOOM2) += power.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(COBJS:.o=.c)
diff --git a/board/omap3/zoom2/Makefile b/board/omap3/zoom2/Makefile
new file mode 100644
index 00000000000..088b8cb01dd
--- /dev/null
+++ b/board/omap3/zoom2/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= zoom2.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/omap3/zoom2/config.mk b/board/omap3/zoom2/config.mk
new file mode 100644
index 00000000000..33f394b85a4
--- /dev/null
+++ b/board/omap3/zoom2/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# Texas Instruments, <www.ti.com>
+#
+# Zoom II uses OMAP3 (ARM-CortexA8) CPU
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 0x80000000 (bank0)
+# 0xA0000000 (bank1)
+# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80e80000
diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c
new file mode 100644
index 00000000000..0700c56d709
--- /dev/null
+++ b/board/omap3/zoom2/zoom2.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Derived from Zoom1 code by
+ *	Nishanth Menon <nm@ti.com>
+ *	Sunil Kumar <sunilsaini05@gmail.com>
+ *	Shashi Ranjan <shashiranjanmca05@gmail.com>
+ *	Richard Woodruff <r-woodruff2@ti.com>
+ *	Syed Mohammed Khasim <khasim@ti.com>
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "zoom2.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init (void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure zoom board specific configurations
+ */
+int misc_init_r (void)
+{
+	power_init_r ();
+	dieid_num_r ();
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs (void)
+{
+	/* platform specific muxes */
+	MUX_ZOOM2 ();
+}
diff --git a/board/omap3/zoom2/zoom2.h b/board/omap3/zoom2/zoom2.h
new file mode 100644
index 00000000000..cae8a7a7fc4
--- /dev/null
+++ b/board/omap3/zoom2/zoom2.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Derived from: board/omap3/zoom1/zoom1.h
+ * Nishanth Menon <nm@ti.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _BOARD_ZOOM2_H_
+#define _BOARD_ZOOM2_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 Zoom2 ",
+	"NAND",
+};
+
+/*
+ * IEN	- Input Enable
+ * IDIS	- Input Disable
+ * PTD	- Pull type Down
+ * PTU	- Pull type Up
+ * DIS	- Pull type selection is inactive
+ * EN	- Pull type selection is active
+ * M0	- Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_ZOOM2() \
+ /* SDRC*/\
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))		/* SDRC_D0 */\
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))		/* SDRC_D1 */\
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))		/* SDRC_D2 */\
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))		/* SDRC_D3 */\
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))		/* SDRC_D4 */\
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))		/* SDRC_D5 */\
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))		/* SDRC_D6 */\
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))		/* SDRC_D7 */\
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))		/* SDRC_D8 */\
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))		/* SDRC_D9 */\
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))		/* SDRC_D10 */\
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))		/* SDRC_D11 */\
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))		/* SDRC_D12 */\
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))		/* SDRC_D13 */\
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))		/* SDRC_D14 */\
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))		/* SDRC_D15 */\
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))		/* SDRC_D16 */\
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))		/* SDRC_D17 */\
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))		/* SDRC_D18 */\
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))		/* SDRC_D19 */\
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))		/* SDRC_D20 */\
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))		/* SDRC_D21 */\
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))		/* SDRC_D22 */\
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))		/* SDRC_D23 */\
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))		/* SDRC_D24 */\
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))		/* SDRC_D25 */\
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))		/* SDRC_D26 */\
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))		/* SDRC_D27 */\
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))		/* SDRC_D28 */\
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))		/* SDRC_D29 */\
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))		/* SDRC_D30 */\
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))		/* SDRC_D31 */\
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))		/* SDRC_CLK */\
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))		/* SDRC_DQS0 */\
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))		/* SDRC_DQS1 */\
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))		/* SDRC_DQS2 */\
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))		/* SDRC_DQS3 */\
+/* GPMC */\
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0))		/* GPMC_A1 */\
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0))		/* GPMC_A2 */\
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0))		/* GPMC_A3 */\
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0))		/* GPMC_A4 */\
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0))		/* GPMC_A5 */\
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0))		/* GPMC_A6 */\
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0))		/* GPMC_A7 */\
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0))		/* GPMC_A8 */\
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0))		/* GPMC_A9 */\
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0))		/* GPMC_A10 */\
+ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0))		/* GPMC_D0 */\
+ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0))		/* GPMC_D1 */\
+ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0))		/* GPMC_D2 */\
+ MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0))		/* GPMC_D3 */\
+ MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0))		/* GPMC_D4 */\
+ MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0))		/* GPMC_D5 */\
+ MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0))		/* GPMC_D6 */\
+ MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0))		/* GPMC_D7 */\
+ MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0))		/* GPMC_D8 */\
+ MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0))		/* GPMC_D9 */\
+ MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0))		/* GPMC_D10 */\
+ MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0))		/* GPMC_D11 */\
+ MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0))		/* GPMC_D12 */\
+ MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0))		/* GPMC_D13 */\
+ MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0))		/* GPMC_D14 */\
+ MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0))		/* GPMC_D15 */\
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0))		/* GPMC_nCS0 */\
+ MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7))		/* GPMC_nCS1 */\
+ MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7))		/* GPMC_nCS2 */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7))		/* GPMC_nCS3 */\
+ MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7))		/* GPMC_nCS4 */\
+ MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7))	/* GPMC_nCS5 */\
+ MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7))		/* GPMC_nCS6 */\
+ MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7))		/* GPMC_nCS7 */\
+ MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0))		/* GPMC_CLK */\
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0))	/* GPMC_nADV_ALE */\
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0))		/* GPMC_nOE */\
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0))		/* GPMC_nWE */\
+ MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0))		/* GPMC_nWP */\
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0))	/* GPMC_nBE0_CLE */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0))		/* GPMC_nBE1 */\
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0))		/* GPMC_WAIT0 */\
+ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0))		/* GPMC_WAIT1 */\
+ MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0))		/* GPMC_WAIT2 */\
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0))		/* GPMC_WAIT3 */\
+/* IDCC modem Power On */\
+ MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4))		/* GPIO_110 */\
+ MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4))		/* GPIO_103 */\
+/* GPMC CS7 has LAN9211 device */\
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0))		/* GPMC_nCS7 */\
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4))		/* LAN9221 */\
+ MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0))		/* MCSPI1_CS2 */\
+/* GPMC CS3 has Serial TL16CP754C device */\
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0))		/* GPMC_nCS3 */\
+/* Toggle Reset pin of TL16CP754C device */\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4))	/* GPIO_152 */\
+ udelay(10);\
+ MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4))	/* GPIO_152 */\
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0))		/* SDRC_CKE1 */\
+/* LEDS */\
+ MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4))	/* GPIO_173 red  */\
+ MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4))		/* GPIO_154 blue  */\
+ MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4))		/* GPIO_61 blue2  */
+
+#endif /* _BOARD_ZOOM2_H_ */
diff --git a/doc/README.omap3 b/doc/README.omap3
index 1ba307fa02f..9ab09793ec8 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -19,6 +19,8 @@ Currently the following boards are supported:
 
 * TI/Logic PD Zoom MDK [6]
 
+* TI/Logic PD Zoom 2 [7]
+
 Toolchain
 =========
 
@@ -54,6 +56,11 @@ make
 make omap3_zoom1_config
 make
 
+* Zoom 2:
+
+make omap3_zoom2_config
+make
+
 Custom commands
 ===============
 
@@ -80,7 +87,7 @@ help
 Acknowledgements
 ================
 
-OMAP3 U-Boot is based on U-Boot tar ball [7] for BeagleBoard and EVM done by
+OMAP3 U-Boot is based on U-Boot tar ball [8] for BeagleBoard and EVM done by
 several TI employees.
 
 Links
@@ -111,6 +118,10 @@ http://openpandora.org/
 
 http://www.logicpd.com/products/devkit/ti/zoom_mobile_development_kit
 
-[7] TI OMAP3 U-Boot:
+[7] TI/Logic PD Zoom 2
+
+http://www.logicpd.com/sites/default/files/1012659A_Zoom_OMAP34x-II_MDP_Brief.pdf
+[8] TI OMAP3 U-Boot:
 
 http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz
+
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
new file mode 100644
index 00000000000..8aea4cbc074
--- /dev/null
+++ b/include/configs/omap3_zoom2.h
@@ -0,0 +1,226 @@
+/*
+ * (C) Copyright 2006-2009
+ * Texas Instruments.
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Syed Mohammed Khasim <x0khasim@ti.com>
+ * Nishanth Menon <nm@ti.com>
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * Configuration settings for the TI OMAP3430 Zoom II board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_ZOOM2	1	/* working with Zoom II */
+
+#include <asm/arch/cpu.h>	/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#undef CONFIG_USE_IRQ		/* no support for IRQs */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			SZ_128K	/* Total Size Environment */
+						/* Sector */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + SZ_128K)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
+						/* initial data */
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_FAT			/* FAT support			*/
+#define CONFIG_CMD_I2C			/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC			/* MMC support			*/
+#define CONFIG_CMD_NAND			/* NAND support			*/
+#define CONFIG_CMD_NAND_LOCK_UNLOCK	/* Enable lock/unlock support	*/
+
+#undef CONFIG_CMD_FLASH			/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA			/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI			/* iminfo			*/
+#undef CONFIG_CMD_IMLS			/* List all found images	*/
+#undef CONFIG_CMD_NET			/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_NFS			/* NFS support			*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_NAND_OMAP_GPMC
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access nand at */
+							/* CS0 */
+#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+
+/* Environment information */
+#define CONFIG_BOOTDELAY		10
+
+/*
+ * Miscellaneous configurable options
+ */
+
+#define CONFIG_SYS_PROMPT		"OMAP3 Zoom2 # "
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					 sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* Memtest from start of memory to 31MB */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + 0x01F00000)
+/* The default load address is the start of memory */
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)
+/* everything, incl board info, in Hz */
+#undef CONFIG_SYS_CLKS_IN_HZ
+/*
+ * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
+ * 32KHz clk, or from external sig. This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			7	/* 2^(PTV+1) */
+#define CONFIG_SYS_HZ			((V_SCLK) / (2 << CONFIG_SYS_PTV))
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using these settings
+ */
+#define CONFIG_STACKSIZE	SZ_128K
+#ifdef CONFIG_USE_IRQ
+#define CONFIG_STACKSIZE_IRQ	SZ_4K
+#define CONFIG_STACKSIZE_FIQ	SZ_4K
+#endif
+
+/*-----------------------------------------------------------------------
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	SZ_32M	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors on */
+						/* one chip */
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
+#define CONFIG_SYS_MONITOR_LEN		SZ_256K	/* Reserve 2 sectors */
+
+#define CONFIG_SYS_FLASH_BASE		boot_flash_base
+
+/* Monitor at start of flash */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
+
+#define CONFIG_ENV_IS_IN_NAND		1
+#define SMNAND_ENV_OFFSET		0x0c0000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	boot_flash_sec
+#define CONFIG_ENV_OFFSET		boot_flash_off
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*-----------------------------------------------------------------------
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+#ifndef __ASSEMBLY__
+extern gpmc_csx_t *nand_cs_base;
+extern gpmc_t *gpmc_cfg_base;
+extern unsigned int boot_flash_base;
+extern volatile unsigned int boot_flash_env_addr;
+extern unsigned int boot_flash_off;
+extern unsigned int boot_flash_sec;
+extern unsigned int boot_flash_type;
+#endif
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 0c872ecd01d6782ae9d37b6eb721404a4a48f356 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Fri, 15 May 2009 23:48:36 +0200
Subject: OMAP3 Port kernel omap gpio interface.

Port version 2.6.27 of the linux kernel's omap gpio interface to u-boot.
The orignal source is in linux/arch/arm/plat-omap/gpio.c

See doc/README.omap3 for instructions on use.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 cpu/arm_cortexa8/omap3/Makefile   |   1 +
 cpu/arm_cortexa8/omap3/gpio.c     | 185 ++++++++++++++++++++++++++++++++++++++
 doc/README.omap3                  |  32 +++++++
 include/asm-arm/arch-omap3/gpio.h |  86 ++++++++++++++++++
 4 files changed, 304 insertions(+)
 create mode 100644 cpu/arm_cortexa8/omap3/gpio.c
 create mode 100644 include/asm-arm/arch-omap3/gpio.h

(limited to 'include')

diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile
index edf5cb29a72..50176eeb35f 100644
--- a/cpu/arm_cortexa8/omap3/Makefile
+++ b/cpu/arm_cortexa8/omap3/Makefile
@@ -29,6 +29,7 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
+COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= syslib.o
 COBJS	+= sys_info.o
diff --git a/cpu/arm_cortexa8/omap3/gpio.c b/cpu/arm_cortexa8/omap3/gpio.c
new file mode 100644
index 00000000000..aeb6066d894
--- /dev/null
+++ b/cpu/arm_cortexa8/omap3/gpio.c
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <common.h>
+#include <asm/arch/gpio.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+static struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
+
+static inline struct gpio_bank *get_gpio_bank(int gpio)
+{
+	return &gpio_bank[gpio >> 5];
+}
+
+static inline int get_gpio_index(int gpio)
+{
+	return gpio & 0x1f;
+}
+
+static inline int gpio_valid(int gpio)
+{
+	if (gpio < 0)
+		return -1;
+	if (gpio < 192)
+		return 0;
+	return -1;
+}
+
+static int check_gpio(int gpio)
+{
+	if (gpio_valid(gpio) < 0) {
+		printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
+		return -1;
+	}
+	return 0;
+}
+
+static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+{
+	void *reg = bank->base;
+	u32 l;
+
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		reg += OMAP24XX_GPIO_OE;
+		break;
+	default:
+		return;
+	}
+	l = __raw_readl(reg);
+	if (is_input)
+		l |= 1 << gpio;
+	else
+		l &= ~(1 << gpio);
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_direction(int gpio, int is_input)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
+}
+
+static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+{
+	void *reg = bank->base;
+	u32 l = 0;
+
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		if (enable)
+			reg += OMAP24XX_GPIO_SETDATAOUT;
+		else
+			reg += OMAP24XX_GPIO_CLEARDATAOUT;
+		l = 1 << gpio;
+		break;
+	default:
+		printf("omap3-gpio unknown bank method %s %d\n",
+		       __FILE__, __LINE__);
+		return;
+	}
+	__raw_writel(l, reg);
+}
+
+void omap_set_gpio_dataout(int gpio, int enable)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+	_set_gpio_dataout(bank, get_gpio_index(gpio), enable);
+}
+
+int omap_get_gpio_datain(int gpio)
+{
+	struct gpio_bank *bank;
+	void *reg;
+
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+	bank = get_gpio_bank(gpio);
+	reg = bank->base;
+	switch (bank->method) {
+	case METHOD_GPIO_24XX:
+		reg += OMAP24XX_GPIO_DATAIN;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return (__raw_readl(reg)
+			& (1 << get_gpio_index(gpio))) != 0;
+}
+
+static void _reset_gpio(struct gpio_bank *bank, int gpio)
+{
+	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
+}
+
+int omap_request_gpio(int gpio)
+{
+	if (check_gpio(gpio) < 0)
+		return -EINVAL;
+
+	return 0;
+}
+
+void omap_free_gpio(int gpio)
+{
+	struct gpio_bank *bank;
+
+	if (check_gpio(gpio) < 0)
+		return;
+	bank = get_gpio_bank(gpio);
+
+	_reset_gpio(bank, gpio);
+}
diff --git a/doc/README.omap3 b/doc/README.omap3
index 9ab09793ec8..e05e816df4b 100644
--- a/doc/README.omap3
+++ b/doc/README.omap3
@@ -84,6 +84,38 @@ For all other commands see
 
 help
 
+Interfaces
+==========
+
+gpio
+
+To set a bit :
+
+	if (!omap_request_gpio(N)) {
+		omap_set_gpio_direction(N, 0);
+		omap_set_gpio_dataout(N, 1);
+	}
+
+To clear a bit :
+
+	if (!omap_request_gpio(N)) {
+		omap_set_gpio_direction(N, 0);
+		omap_set_gpio_dataout(N, 0);
+	}
+
+To read a bit :
+
+	if (!omap_request_gpio(N)) {
+		omap_set_gpio_direction(NULL, 1);
+		val = omap_get_gpio_datain(N);
+		omap_free_gpio(N);
+	}
+	if (val)
+		printf("GPIO N is set\n");
+	else
+		printf("GPIO N is clear\n");
+
+
 Acknowledgements
 ================
 
diff --git a/include/asm-arm/arch-omap3/gpio.h b/include/asm-arm/arch-omap3/gpio.h
new file mode 100644
index 00000000000..30f633ce964
--- /dev/null
+++ b/include/asm-arm/arch-omap3/gpio.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_H
+#define _GPIO_H
+
+#define OMAP24XX_GPIO_REVISION		0x0000
+#define OMAP24XX_GPIO_SYSCONFIG		0x0010
+#define OMAP24XX_GPIO_SYSSTATUS		0x0014
+#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
+#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
+#define OMAP24XX_GPIO_IRQENABLE2	0x002c
+#define OMAP24XX_GPIO_IRQENABLE1	0x001c
+#define OMAP24XX_GPIO_WAKE_EN		0x0020
+#define OMAP24XX_GPIO_CTRL		0x0030
+#define OMAP24XX_GPIO_OE		0x0034
+#define OMAP24XX_GPIO_DATAIN		0x0038
+#define OMAP24XX_GPIO_DATAOUT		0x003c
+#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
+#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
+#define OMAP24XX_GPIO_RISINGDETECT	0x0048
+#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
+#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
+#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
+#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
+#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
+#define OMAP24XX_GPIO_SETWKUENA		0x0084
+#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
+#define OMAP24XX_GPIO_SETDATAOUT	0x0094
+
+struct gpio_bank {
+	void *base;
+	int method;
+};
+
+#define METHOD_GPIO_24XX	4
+
+/* This is the interface */
+
+/* Request a gpio before using it */
+int omap_request_gpio(int gpio);
+/* Reset and free a gpio after using it */
+void omap_free_gpio(int gpio);
+/* Sets the gpio as input or output */
+void omap_set_gpio_direction(int gpio, int is_input);
+/* Set or clear a gpio output */
+void omap_set_gpio_dataout(int gpio, int enable);
+/* Get the value of a gpio input */
+int omap_get_gpio_datain(int gpio);
+
+#endif /* _GPIO_H_ */
-- 
cgit v1.3.1


From 1a09d05abfc6d4d4f1fce9f6bd0275bd1c08d4f5 Mon Sep 17 00:00:00 2001
From: "s-paulraj@ti.com" <s-paulraj@ti.com>
Date: Fri, 15 May 2009 23:48:36 +0200
Subject: ARM DaVinci: Minor Updates to base addresses

Patch adds base addresses for DaVinci DM365. Updated patches for DM365
will be posted soon.

Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 include/asm-arm/arch-davinci/hardware.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'include')

diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index 99324e45c7e..313b3f3dba5 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -75,6 +75,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
+#define DAVINCI_DDR_BASE			(0x80000000)
 
 #ifdef CONFIG_SOC_DM644X
 #define DAVINCI_UART2_BASE			0x01c20800
@@ -99,6 +100,11 @@ typedef volatile unsigned int *	dv_reg_p;
 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01e10000
 #define DAVINCI_MMC_SD0_BASE			0x01e11000
 
+#elif defined(CONFIG_SOC_DM365)
+#define DAVINCI_MMC_SD1_BASE			0x01d00000
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		0x01d10000
+#define DAVINCI_MMC_SD0_BASE			0x01d11000
+
 #endif
 
 /* Power and Sleep Controller (PSC) Domains */
-- 
cgit v1.3.1


From 136cf92dc9e84c9a1bf567f1fe741092bf765495 Mon Sep 17 00:00:00 2001
From: Sanjeev Premi <premi@ti.com>
Date: Fri, 15 May 2009 23:48:37 +0200
Subject: OMAP3EVM: Set default bootfile

The current configuration doesn't define default
bootfile; leading to this warning at execution:

OMAP3_EVM # dhcp
...
...
DHCP client bound to address 192.168.1.11
*** Warning: no boot file name; using 'AC18BE16.img'
TFTP from server 0.0.0.0; our IP address is 192.168.1.11;
sending through gateway 192.168.1.1
Filename 'AC18BE16.img'.
Load address: 0x82000000
Loading: *
TFTP error: 'File not found' (1)

Signed-off-by: Sanjeev Premi <premi@ti.com>
---
 include/configs/omap3_evm.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include')

diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h
index 549cef99ff9..e205c01b4b7 100644
--- a/include/configs/omap3_evm.h
+++ b/include/configs/omap3_evm.h
@@ -149,6 +149,8 @@
 /* Environment information */
 #define CONFIG_BOOTDELAY	10
 
+#define CONFIG_BOOTFILE		uImage
+
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"loadaddr=0x82000000\0" \
 	"console=ttyS2,115200n8\0" \
-- 
cgit v1.3.1


From 28b00324becf3552134ae1e086509dc9c3d6e932 Mon Sep 17 00:00:00 2001
From: David Brownell <dbrownell@users.sourceforge.net>
Date: Fri, 15 May 2009 23:48:37 +0200
Subject: dm355 evm support

Initial U-Boot support for the DaVinci DM355 EVM.  This is a board
from Spectrum Digital.  Board docs include schematic and firmware
for its microcontroller:

  http://c6000.spectrumdigital.com/evmdm355/revd/

Most of the DM355 chip is fully documented by TI, the most notable
exception being the MPEG/JPEG coprocessor (programmable using codecs
available at no cost from TI), which is omitted from its DM335 sibling:

  http://focus.ti.com/docs/prod/folders/print/tms320dm355.html

This version can boot from the on-board DM9000 Ethernet chip, after
being loaded (from NAND, MMC/SD, or UART).  In the near future, NAND
and USB support could be added ... NAND support is being held back
until the support for the 4-bit ECC hardware is ready.

Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
---
 MAKEALL                            |   1 +
 Makefile                           |   3 +
 board/davinci/dm355evm/Makefile    |  52 ++++++++++
 board/davinci/dm355evm/config.mk   |  11 +++
 board/davinci/dm355evm/dm355evm.c  | 108 +++++++++++++++++++++
 include/configs/davinci_dm355evm.h | 190 +++++++++++++++++++++++++++++++++++++
 6 files changed, 365 insertions(+)
 create mode 100644 board/davinci/dm355evm/Makefile
 create mode 100644 board/davinci/dm355evm/config.mk
 create mode 100644 board/davinci/dm355evm/dm355evm.c
 create mode 100644 include/configs/davinci_dm355evm.h

(limited to 'include')

diff --git a/MAKEALL b/MAKEALL
index 9b48773bc88..c98d03a579e 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -528,6 +528,7 @@ LIST_ARM9="			\
 	davinci_schmoogie	\
 	davinci_sffsdr		\
 	davinci_sonata		\
+	davinci_dm355evm	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index cf140a4d33b..d14678070e8 100644
--- a/Makefile
+++ b/Makefile
@@ -2801,6 +2801,9 @@ davinci_sffsdr_config :	unconfig
 davinci_sonata_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci
 
+davinci_dm355evm_config :	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci
+
 lpd7a400_config \
 lpd7a404_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x
diff --git a/board/davinci/dm355evm/Makefile b/board/davinci/dm355evm/Makefile
new file mode 100644
index 00000000000..26b07054657
--- /dev/null
+++ b/board/davinci/dm355evm/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+SOBJS	:=
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davinci/dm355evm/config.mk b/board/davinci/dm355evm/config.mk
new file mode 100644
index 00000000000..c4e6e07b7c8
--- /dev/null
+++ b/board/davinci/dm355evm/config.mk
@@ -0,0 +1,11 @@
+#
+# Spectrum Digital DM355 EVM board
+#	dm355evm board has 1 bank of 128 MB DDR RAM
+#	Physical Address: 8000'0000 to 8800'0000
+#
+# Linux Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+
+#Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c
new file mode 100644
index 00000000000..398f527759b
--- /dev/null
+++ b/board/davinci/dm355evm/dm355evm.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emif_defs.h>
+#include <asm/arch/nand_defs.h>
+#include "../common/misc.h"
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * With the DM355 EVM, u-boot is *always* a third stage loader,
+ * unless a JTAG debugger handles the first two stages:
+ *
+ *   - 1st stage is ROM Boot Loader (RBL), which searches for a
+ *     second stage loader in one of three places based on SW7:
+ *     NAND (with MMC/SD fallback), MMC/SD, or UART.
+ *
+ *   - 2nd stage is User Boot Loader (UBL), using at most 30KB
+ *     of on-chip SRAM, responsible for lowlevel init, and for
+ *     loading the third stage loader into DRAM.
+ *
+ *   - 3rd stage, that's us!
+ */
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM355_EVM;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	/* We expect the UBL to have handled "lowlevel init", which
+	 * involves setting up at least:
+	 *  - clocks
+	 *      + PLL1 (for ARM and peripherals) and PLL2 (for DDR)
+	 *      + clock divisors for those PLLs
+	 *      + LPSC_DDR module enabled
+	 *      + LPSC_TIMER0 module (still) enabled
+	 *  - EMIF
+	 *      + DDR init and timings
+	 *      + AEMIF timings (for NAND and DM9000)
+	 *  - pinmux
+	 *
+	 * Some of that is repeated here, mostly as a precaution.
+	 */
+
+	/* AEMIF:  Some "address" lines are available as GPIOs.  A3..A13
+	 * could be too if we used A12 as a GPIO during NAND chipselect
+	 * (and Linux did too), letting us control the LED on A7/GPIO61.
+	 */
+	REG(PINMUX2) = 0x0c08;
+
+	/* UART0 may still be in SyncReset if we didn't boot from UART */
+	davinci_enable_uart0();
+
+	/* EDMA may be in SyncReset too; turn it on, Linux won't (yet) */
+	lpsc_on(DAVINCI_LPSC_TPCC);
+	lpsc_on(DAVINCI_LPSC_TPTC0);
+	lpsc_on(DAVINCI_LPSC_TPTC1);
+
+	return 0;
+}
+
+#ifdef CONFIG_NAND_DAVINCI
+
+static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip	*this = mtd->priv;
+	u32			wbase = (u32) this->IO_ADDR_W;
+	u32			rbase = (u32) this->IO_ADDR_R;
+
+	if (chip == 1) {
+		__set_bit(14, &wbase);
+		__set_bit(14, &rbase);
+	} else {
+		__clear_bit(14, &wbase);
+		__clear_bit(14, &rbase);
+	}
+	this->IO_ADDR_W = (void *)wbase;
+	this->IO_ADDR_R = (void *)rbase;
+}
+
+int board_nand_init(struct nand_chip *nand)
+{
+	davinci_nand_init(nand);
+	nand->select_chip = nand_dm355evm_select_chip;
+	return 0;
+}
+
+#endif
diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
new file mode 100644
index 00000000000..9a7df083fb0
--- /dev/null
+++ b/include/configs/davinci_dm355evm.h
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2009 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/* Spectrum Digital TMS320DM355 EVM board */
+#define DAVINCI_DM355EVM
+
+#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is a 3rd stage loader */
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_SYS_NO_FLASH		/* that is, no *NOR* flash */
+#define CONFIG_SYS_CONSOLE_INFO_QUIET
+#define CONFIG_DISPLAY_CPUINFO
+
+/* SoC Configuration */
+#define CONFIG_ARM926EJS				/* arm926ejs CPU */
+#define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
+#define CONFIG_SYS_HZ_CLOCK		24000000	/* timer0 freq */
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SOC_DM355
+
+/* Memory Info */
+#define CONFIG_NR_DRAM_BANKS		1
+#define PHYS_SDRAM_1			0x80000000
+#define PHYS_SDRAM_1_SIZE		SZ_128M
+
+/* Serial Driver info: UART0 for console  */
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	-4
+#define CONFIG_SYS_NS16550_COM1		0x01c20000
+#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_HZ_CLOCK
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+/* Ethernet:  external DM9000 */
+#define CONFIG_DRIVER_DM9000		1
+#define CONFIG_DM9000_BASE		0x04014000
+#define DM9000_IO			CONFIG_DM9000_BASE
+#define DM9000_DATA			(CONFIG_DM9000_BASE + 2)
+
+/* I2C */
+#define CONFIG_HARD_I2C
+#define CONFIG_DRIVER_DAVINCI_I2C
+#define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_I2C_SLAVE		0x10	/* SMBus host address */
+
+/* NAND: socketed, two chipselects, normally 2 GBytes */
+/* NYET -- #define CONFIG_NAND_DAVINCI */
+#define CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+#define CONFIG_SYS_NAND_LARGEPAGE
+#define CONFIG_SYS_NAND_BASE_LIST	{ 0x02000000, }
+/* socket has two chipselects, nCE0 gated by address BIT(14) */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_SYS_NAND_MAX_CHIPS	2
+
+/* USB: OTG connector */
+/* NYET -- #define CONFIG_USB_DAVINCI */
+
+/* U-Boot command configuration */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_BDI
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_SAVES
+
+#ifdef CONFIG_NAND_DAVINCI
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_UBI
+#define CONFIG_RBTREE
+#endif
+
+/* TEMPORARY -- no safe place to save env, yet */
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_CMD_SAVEENV
+
+#ifdef CONFIG_USB_DAVINCI
+#define CONFIG_MUSB_HCD
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#else
+#undef CONFIG_MUSB_HCD
+#undef CONFIG_CMD_USB
+#undef CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* U-Boot general configuration */
+#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
+#define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
+#define CONFIG_SYS_PROMPT	"DM355 EVM # "	/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size  */
+#define CONFIG_SYS_PBSIZE			/* Print buffer size */ \
+		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_ENV_SIZE		SZ_16K
+
+/* NYET -- #define CONFIG_BOOTDELAY	5 */
+#define CONFIG_BOOTCOMMAND \
+		"dhcp;bootm"
+#define CONFIG_BOOTARGS \
+		"console=ttyS0,115200n8 " \
+		"root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro"
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_NET_RETRY_COUNT 10
+
+/* U-Boot memory configuration */
+#define CONFIG_STACKSIZE		SZ_256K		/* regular stack */
+#define CONFIG_SYS_MALLOC_LEN		SZ_512K		/* malloc() arena */
+#define CONFIG_SYS_GBL_DATA_SIZE	128		/* for initial data */
+#define CONFIG_SYS_MEMTEST_START	0x87000000	/* physical address */
+#define CONFIG_SYS_MEMTEST_END		0x88000000	/* test 16MB RAM */
+
+/* Linux interfacing */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_SYS_BARGSIZE	1024			/* bootarg Size */
+#define CONFIG_SYS_LOAD_ADDR	0x80700000		/* kernel address */
+
+
+/* NAND configuration ... socketed with two chipselects.  It normally comes
+ * with a 2GByte SLC part with 2KB pages (and 128KB erase blocks); other
+ * 2GByte parts may have 4KB pages, 256KB erase blocks, and use MLC.  (MLC
+ * pretty much demands the 4-bit ECC support.)  You can of course swap in
+ * other parts, including small page ones.
+ *
+ * This presents a single read-only partition for all bootloader stuff.
+ * UBL (1+ block), U-Boot (256KB+), U-Boot environment (one block), and
+ * some extra space to help cope with bad blocks in that data.  Linux
+ * shouldn't care about its detailed layout, and will probably want to use
+ * UBI/UBFS for the rest (except maybe on smallpage chips).  It's easy to
+ * override this default partitioning using MTDPARTS and cmdlinepart.
+ */
+#define MTDIDS_DEFAULT		"nand0=davinci_nand.0"
+
+#ifdef CONFIG_SYS_NAND_LARGEPAGE
+/*  Use same layout for 128K/256K blocks; allow some bad blocks */
+#define PART_BOOT		"2m(bootloader)ro,"
+#else
+/* Assume 16K erase blocks; allow a few bad ones. */
+#define PART_BOOT		"512k(bootloader)ro,"
+#endif
+
+#define PART_KERNEL		"4m(kernel),"	/* kernel + initramfs */
+#define PART_REST		"-(filesystem)"
+
+#define MTDPARTS_DEFAULT	\
+	"mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 929b79a0b5e48303ab04aae9d0abceb0c707f111 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Thu, 14 May 2009 23:18:33 +0200
Subject: TQM834x: fix environment size; add redundant env.

Also reserve more space for U-Boot as it will probably grow soon.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/TQM834x.h | 26 ++++++++++++--------------
 1 file changed, 12 insertions(+), 14 deletions(-)

(limited to 'include')

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 551073025fd..7d72fa1785d 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -159,8 +159,8 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(256 * 1024) /* Reserve 256 kB for malloc */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB = 3 sect. for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024) /* Reserve 512 kB for malloc */
 
 /*
  * Serial Port
@@ -275,22 +275,20 @@ extern int tqm834x_num_flash_banks;
 /*
  * Environment
  */
-#define CONFIG_ENV_OVERWRITE
-
-#ifndef CONFIG_SYS_RAMBOOT
-	#define CONFIG_ENV_IS_IN_FLASH	1
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
-	#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
-	#define CONFIG_ENV_SIZE		0x2000
+#ifdef CONFIG_SYS_RAMBOOT
+# define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
 #else
-	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
-	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
-	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
-	#define CONFIG_ENV_SIZE		0x2000
+# define CONFIG_ENV_IS_IN_FLASH		1
 #endif
 
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K (one sector) for env */
+#define CONFIG_ENV_SIZE			0x8000	/*  32K max size */
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
 #define CONFIG_LOADS_ECHO		1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE		1	/* allow baudrate change */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
 
 /*
  * BOOTP options
-- 
cgit v1.3.1


From 4681e673a51c48f4c096aa3c8fae5e6217ffd58d Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Thu, 14 May 2009 23:18:34 +0200
Subject: TQM834x: add FDT support

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 board/tqc/tqm834x/pci.c     | 45 ++++++++++++++++++++++++++++++++++
 board/tqc/tqm834x/tqm834x.c | 11 +++++++++
 include/configs/TQM834x.h   | 59 ++++++++++++++++++++++++++++++---------------
 3 files changed, 95 insertions(+), 20 deletions(-)

(limited to 'include')

diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index cb2cb8d32d4..6c113e3db19 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -24,7 +24,15 @@
 
 #include <asm/mmu.h>
 #include <common.h>
+#include <asm/global_data.h>
 #include <pci.h>
+#include <asm/mpc8349_pci.h>
+#if defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#include <fdt_support.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_PCI
 
@@ -217,4 +225,41 @@ pci_init_board(void)
 	 */
 	hose->last_busno = pci_hose_scan(hose);
 }
+
+#if defined(CONFIG_OF_LIBFDT)
+void ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int tmp[2];
+	const char *path;
+
+	nodeoffset = fdt_path_offset(blob, "/aliases");
+	if (nodeoffset >= 0) {
+		path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci1_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci1_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+#ifdef CONFIG_MPC83XX_PCI2
+		path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
+		if (path) {
+			tmp[0] = cpu_to_be32(pci2_hose.first_busno);
+			tmp[1] = cpu_to_be32(pci2_hose.last_busno);
+			do_fixup_by_path(blob, path, "bus-range",
+				&tmp, sizeof(tmp), 1);
+
+			tmp[0] = cpu_to_be32(gd->pci_clk);
+			do_fixup_by_path(blob, path, "clock-frequency",
+				&tmp, sizeof(tmp[0]), 1);
+		}
+#endif
+	}
+}
+#endif /* CONFIG_OF_LIBFDT */
 #endif /* CONFIG_PCI */
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 106cac2448e..4fd8cd69692 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -431,3 +431,14 @@ static void set_ddr_config(void) {
 #endif
 	}
 }
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif	/* CONFIG_PCI */
+}
+#endif	/* CONFIG_OF_BOARD_SETUP */
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 7d72fa1785d..d4b0f9c9300 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -146,9 +146,9 @@ extern int tqm834x_num_flash_banks;
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
 
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
+# define CONFIG_SYS_RAMBOOT
 #else
-#undef  CONFIG_SYS_RAMBOOT
+# undef  CONFIG_SYS_RAMBOOT
 #endif
 
 #define CONFIG_SYS_INIT_RAM_LOCK	1
@@ -275,12 +275,7 @@ extern int tqm834x_num_flash_banks;
 /*
  * Environment
  */
-#ifdef CONFIG_SYS_RAMBOOT
-# define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
-#else
-# define CONFIG_ENV_IS_IN_FLASH		1
-#endif
-
+#define CONFIG_ENV_IS_IN_FLASH		1
 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 #define CONFIG_ENV_SECT_SIZE		0x20000	/* 128K (one sector) for env */
 #define CONFIG_ENV_SIZE			0x8000	/*  32K max size */
@@ -304,14 +299,18 @@ extern int tqm834x_num_flash_banks;
  */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SNTP
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -348,6 +347,11 @@ extern int tqm834x_num_flash_banks;
 
 #undef CONFIG_WATCHDOG				/* watchdog disabled */
 
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
@@ -492,20 +496,35 @@ extern int tqm834x_num_flash_banks;
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
-	"flash_nfs=run nfsargs addip addtty;"				\
+	"addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"flash_nfs_old=run nfsargs addip addcons;"			\
 		"bootm ${kernel_addr}\0"				\
-	"flash_self=run ramargs addip addtty;"				\
+	"flash_nfs=run nfsargs addip addcons;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self_old=run ramargs addip addcons;"			\
 		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 400000 ${bootfile};run nfsargs addip addtty;"     \
-		"bootm\0"						\
+	"flash_self=run ramargs addip addcons;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs_old=tftp 400000 ${bootfile};"				\
+		"run nfsargs addip addcons;bootm\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile}; "			\
+		"tftp ${fdt_addr_r} ${fdt_file}; "			\
+		"run nfsargs addip addcons; "				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
 	"rootpath=/opt/eldk/ppc_6xx\0"					\
-	"bootfile=/tftpboot/tqm834x/uImage\0"				\
-	"kernel_addr=80060000\0"					\
-	"ramdisk_addr=80160000\0"					\
-	"load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0"		\
-	"update=protect off 80000000 8003ffff; "			\
-		"era 80000000 8003ffff; cp.b 100000 80000000 40000\0"	\
+	"bootfile=tqm834x/uImage\0"					\
+	"fdtfile=tqm834x/tqm834x.dtb\0"					\
+	"kernel_addr_r=400000\0"					\
+	"fdt_addr_r=600000\0"						\
+	"ramdisk_addr_r=800000\0"					\
+	"kernel_addr=800C0000\0"					\
+	"fdt_addr=800A0000\0"						\
+	"ramdisk_addr=80300000\0"					\
+	"u-boot=tqm834x/u-boot.bin\0"					\
+	"load=tftp 200000 ${u-boot}\0"					\
+	"update=protect off 80000000 +${filesize};"			\
+		"era 80000000 +${filesize};"				\
+		"cp.b 200000 80000000 ${filesize}\0"			\
 	"upd=run load update\0"						\
 	""
 
-- 
cgit v1.3.1


From a3455c00510c5abf1e91743c4a02d8393b6df18d Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Fri, 15 May 2009 09:19:52 +0200
Subject: TQM834x: use buffered writes to accelerate writing to flash

Also enable display of 'E'mpty sectors in "flinfo" output.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 include/configs/TQM834x.h | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index d4b0f9c9300..dbd30ac4b0f 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -78,13 +78,12 @@
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
 #undef CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_BASE		0x80000000	/* start of FLASH   */
 #define CONFIG_SYS_FLASH_SIZE		8		/* FLASH size in MB */
-
-/* buffered writes in the AMD chip set is not supported yet */
-#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_EMPTY_INFO			/* print 'E' for empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /*
  * FLASH bank number detection
-- 
cgit v1.3.1


From c358d9c3f16571e8f825e81b75eaf32e228cb669 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat, 9 May 2009 13:21:18 +0200
Subject: arm: unify interrupt init

all arm init the IRQ stack the same way
so unify it in lib_arm/interrupts.c and then call arch specific interrupt init

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/arm1136/cpu.c            | 11 -----------
 cpu/arm720t/cpu.c            |  7 -------
 cpu/arm720t/interrupts.c     |  2 +-
 cpu/arm920t/cpu.c            | 11 -----------
 cpu/arm925t/cpu.c            | 11 -----------
 cpu/arm926ejs/cpu.c          | 11 -----------
 cpu/arm946es/cpu.c           | 11 -----------
 cpu/arm_cortexa8/cpu.c       | 12 ------------
 cpu/arm_intcm/cpu.c          | 11 -----------
 cpu/ixp/cpu.c                | 12 ------------
 cpu/ixp/interrupts.c         |  2 +-
 cpu/lh7a40x/cpu.c            | 11 -----------
 cpu/pxa/cpu.c                | 11 -----------
 cpu/sa1100/cpu.c             |  7 -------
 include/asm-arm/u-boot-arm.h |  1 +
 lib_arm/interrupts.c         | 13 +++++++++++++
 16 files changed, 16 insertions(+), 128 deletions(-)

(limited to 'include')

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 7381da092c6..6104f9e38f4 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -35,21 +35,10 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 6c40903b7db..7a2b9c37bc5 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -42,13 +42,6 @@ static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm720t/interrupts.c b/cpu/arm720t/interrupts.c
index ff21314d8e2..91d552cd28a 100644
--- a/cpu/arm720t/interrupts.c
+++ b/cpu/arm720t/interrupts.c
@@ -111,7 +111,7 @@ static ulong timestamp;
 static ulong lastdec;
 
 #if defined(CONFIG_USE_IRQ) && defined(CONFIG_S3C4510B)
-int interrupt_init (void)
+int arch_interrupt_init (void)
 {
 	int i;
 
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index b6ef6bb8f5d..e4a8adb2d71 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -33,21 +33,10 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index 62828b174e2..e48f34151e4 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -34,21 +34,10 @@
 #include <arm925t.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 1f70a3603a8..0a3267385cf 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -33,21 +33,10 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index d3195f9a22f..e0f91d36c68 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -33,21 +33,10 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index ca6bf4f2342..b91cc4f3b3e 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -36,10 +36,6 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 #ifndef CONFIG_L2_OFF
 void l2cache_disable(void);
 #endif
@@ -48,14 +44,6 @@ static void cache_flush(void);
 
 int cpu_init(void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START =
-	    _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index b137f766492..488bd0c5a2d 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -33,19 +33,8 @@
 #include <common.h>
 #include <command.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 42c62f6e397..5cfc39dafad 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -38,10 +38,6 @@
 
 ulong loops_per_jiffy;
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
@@ -81,14 +77,6 @@ int print_cpuinfo (void)
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
-
 	return 0;
 }
 
diff --git a/cpu/ixp/interrupts.c b/cpu/ixp/interrupts.c
index a05e439fdb5..06a826af63e 100644
--- a/cpu/ixp/interrupts.c
+++ b/cpu/ixp/interrupts.c
@@ -67,7 +67,7 @@ void irq_install_handler (int irq, interrupt_handler_t handle_irq, void *data)
 	IRQ_HANDLER[irq].m_func = handle_irq;
 }
 
-int interrupt_init (void)
+int arch_interrupt_init (void)
 {
 	int i;
 
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index be92f708b90..3cf0824c458 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -33,21 +33,10 @@
 #include <command.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index 3a1be57f44a..8edb44eb45d 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -35,21 +35,10 @@
 #include <asm/arch/pxa-regs.h>
 #include <asm/system.h>
 
-#ifdef CONFIG_USE_IRQ
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
 static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index ed1a6f7cd30..39285a0ccaa 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -42,13 +42,6 @@ static void cache_flush(void);
 
 int cpu_init (void)
 {
-	/*
-	 * setup up stacks if necessary
-	 */
-#ifdef CONFIG_USE_IRQ
-	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
-	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
-#endif
 	return 0;
 }
 
diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index 238d4085419..76f1ffa5a2c 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -58,6 +58,7 @@ void	setup_revision_tag (struct tag **params);
 int	setenv		(char *, char *);
 
 /* cpu/.../interrupt.c */
+int	arch_interrupt_init	(void);
 void	reset_timer_masked	(void);
 ulong	get_timer_masked	(void);
 void	udelay_masked		(unsigned long usec);
diff --git a/lib_arm/interrupts.c b/lib_arm/interrupts.c
index 8bb950b12bc..1f2b815611c 100644
--- a/lib_arm/interrupts.c
+++ b/lib_arm/interrupts.c
@@ -39,6 +39,19 @@
 #include <asm/proc-armv/ptrace.h>
 
 #ifdef CONFIG_USE_IRQ
+DECLARE_GLOBAL_DATA_PTR;
+
+int interrupt_init (void)
+{
+	/*
+	 * setup up stacks if necessary
+	 */
+	IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
+	FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
+
+	return arch_interrupt_init();
+}
+
 /* enable IRQ interrupts */
 void enable_interrupts (void)
 {
-- 
cgit v1.3.1


From ad7e8aac6920f8b8a85b3cc2e93bca7458e99aa1 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat, 9 May 2009 13:21:19 +0200
Subject: arm: remove cpu_init

move s3c44b0 to arch_cpu_init and as noone use cpu_init remove it

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/arm1136/cpu.c      | 5 -----
 cpu/arm1176/cpu.c      | 5 -----
 cpu/arm720t/cpu.c      | 5 -----
 cpu/arm920t/cpu.c      | 5 -----
 cpu/arm925t/cpu.c      | 5 -----
 cpu/arm926ejs/cpu.c    | 5 -----
 cpu/arm946es/cpu.c     | 5 -----
 cpu/arm_cortexa8/cpu.c | 5 -----
 cpu/arm_intcm/cpu.c    | 5 -----
 cpu/ixp/cpu.c          | 5 -----
 cpu/lh7a40x/cpu.c      | 5 -----
 cpu/pxa/cpu.c          | 5 -----
 cpu/s3c44b0/cpu.c      | 2 +-
 cpu/sa1100/cpu.c       | 5 -----
 include/configs/B2.h   | 1 +
 lib_arm/board.c        | 1 -
 16 files changed, 2 insertions(+), 67 deletions(-)

(limited to 'include')

diff --git a/cpu/arm1136/cpu.c b/cpu/arm1136/cpu.c
index 6104f9e38f4..ade7f468007 100644
--- a/cpu/arm1136/cpu.c
+++ b/cpu/arm1136/cpu.c
@@ -37,11 +37,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm1176/cpu.c b/cpu/arm1176/cpu.c
index fbc8ea80272..c59a77b9d82 100644
--- a/cpu/arm1176/cpu.c
+++ b/cpu/arm1176/cpu.c
@@ -38,11 +38,6 @@
 
 static void cache_flush (void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c
index 7a2b9c37bc5..88c71bfe184 100644
--- a/cpu/arm720t/cpu.c
+++ b/cpu/arm720t/cpu.c
@@ -40,11 +40,6 @@
 static void cache_flush(void);
 #endif
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm920t/cpu.c b/cpu/arm920t/cpu.c
index e4a8adb2d71..34adb115350 100644
--- a/cpu/arm920t/cpu.c
+++ b/cpu/arm920t/cpu.c
@@ -35,11 +35,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm925t/cpu.c b/cpu/arm925t/cpu.c
index e48f34151e4..71700bb1751 100644
--- a/cpu/arm925t/cpu.c
+++ b/cpu/arm925t/cpu.c
@@ -36,11 +36,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm926ejs/cpu.c b/cpu/arm926ejs/cpu.c
index 0a3267385cf..5c902dfc133 100644
--- a/cpu/arm926ejs/cpu.c
+++ b/cpu/arm926ejs/cpu.c
@@ -35,11 +35,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm946es/cpu.c b/cpu/arm946es/cpu.c
index e0f91d36c68..c63c98be864 100644
--- a/cpu/arm946es/cpu.c
+++ b/cpu/arm946es/cpu.c
@@ -35,11 +35,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index b91cc4f3b3e..6fd07d0b737 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -42,11 +42,6 @@ void l2cache_disable(void);
 
 static void cache_flush(void);
 
-int cpu_init(void)
-{
-	return 0;
-}
-
 int cleanup_before_linux(void)
 {
 	unsigned int i;
diff --git a/cpu/arm_intcm/cpu.c b/cpu/arm_intcm/cpu.c
index 488bd0c5a2d..c0748e872e2 100644
--- a/cpu/arm_intcm/cpu.c
+++ b/cpu/arm_intcm/cpu.c
@@ -33,11 +33,6 @@
 #include <common.h>
 #include <command.h>
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/ixp/cpu.c b/cpu/ixp/cpu.c
index 5cfc39dafad..ce275e5f3c7 100644
--- a/cpu/ixp/cpu.c
+++ b/cpu/ixp/cpu.c
@@ -75,11 +75,6 @@ int print_cpuinfo (void)
 }
 #endif /* CONFIG_DISPLAY_CPUINFO */
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/lh7a40x/cpu.c b/cpu/lh7a40x/cpu.c
index 3cf0824c458..b193189123b 100644
--- a/cpu/lh7a40x/cpu.c
+++ b/cpu/lh7a40x/cpu.c
@@ -35,11 +35,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/pxa/cpu.c b/cpu/pxa/cpu.c
index 8edb44eb45d..800d120e718 100644
--- a/cpu/pxa/cpu.c
+++ b/cpu/pxa/cpu.c
@@ -37,11 +37,6 @@
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/cpu/s3c44b0/cpu.c b/cpu/s3c44b0/cpu.c
index 7ef4a1fdb0d..bca38f81d33 100644
--- a/cpu/s3c44b0/cpu.c
+++ b/cpu/s3c44b0/cpu.c
@@ -32,7 +32,7 @@
 #include <command.h>
 #include <asm/hardware.h>
 
-int cpu_init (void)
+int arch_cpu_init (void)
 {
 	icache_enable();
 
diff --git a/cpu/sa1100/cpu.c b/cpu/sa1100/cpu.c
index 39285a0ccaa..58e90dc9f69 100644
--- a/cpu/sa1100/cpu.c
+++ b/cpu/sa1100/cpu.c
@@ -40,11 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static void cache_flush(void);
 
-int cpu_init (void)
-{
-	return 0;
-}
-
 int cleanup_before_linux (void)
 {
 	/*
diff --git a/include/configs/B2.h b/include/configs/B2.h
index 35fad5c553b..e5439f3b54a 100644
--- a/include/configs/B2.h
+++ b/include/configs/B2.h
@@ -39,6 +39,7 @@
 #define CONFIG_ARM_THUMB	1	/* this is an ARM7TDMI */
 #undef  CONFIG_ARM7_REVD		/* disable ARM720 REV.D Workarounds */
 #define CONFIG_SYS_NO_CP15_CACHE
+#define CONFIG_ARCH_CPU_INIT
 
 #define CONFIG_S3C44B0_CLOCK_SPEED	75 /* we have a 75Mhz S3C44B0*/
 
diff --git a/lib_arm/board.c b/lib_arm/board.c
index d86ed22cadb..e081fbccb55 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -265,7 +265,6 @@ typedef int (init_fnc_t) (void);
 int print_cpuinfo (void);
 
 init_fnc_t *init_sequence[] = {
-	cpu_init,		/* basic cpu dependent setup */
 #if defined(CONFIG_ARCH_CPU_INIT)
 	arch_cpu_init,		/* basic arch cpu dependent setup */
 #endif
-- 
cgit v1.3.1


From 379be585eb2343d8814a5cee5fb3da930d846bee Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sat, 16 May 2009 22:48:46 +0200
Subject: pxa: move serial driver to drivers/serial

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/pxa/Makefile             |   1 -
 cpu/pxa/serial.c             | 385 -------------------------------------------
 drivers/serial/Makefile      |   1 +
 drivers/serial/serial_pxa.c  | 385 +++++++++++++++++++++++++++++++++++++++++++
 include/configs/cerf250.h    |   1 +
 include/configs/cradle.h     |   1 +
 include/configs/csb226.h     |   1 +
 include/configs/delta.h      |   1 +
 include/configs/innokom.h    |   1 +
 include/configs/logodl.h     |   1 +
 include/configs/lubbock.h    |   1 +
 include/configs/pleb2.h      |   1 +
 include/configs/pxa255_idp.h |   1 +
 include/configs/trizepsiv.h  |   1 +
 include/configs/wepep250.h   |   1 +
 include/configs/xaeniax.h    |   1 +
 include/configs/xm250.h      |   1 +
 include/configs/xsengine.h   |   1 +
 include/configs/zylonite.h   |   1 +
 19 files changed, 401 insertions(+), 386 deletions(-)
 delete mode 100644 cpu/pxa/serial.c
 create mode 100644 drivers/serial/serial_pxa.c

(limited to 'include')

diff --git a/cpu/pxa/Makefile b/cpu/pxa/Makefile
index 5dc3a52c8d5..07a151a1703 100644
--- a/cpu/pxa/Makefile
+++ b/cpu/pxa/Makefile
@@ -30,7 +30,6 @@ START	= start.o
 COBJS	+= cpu.o
 COBJS	+= i2c.o
 COBJS	+= pxafb.o
-COBJS	+= serial.o
 COBJS	+= timer.o
 COBJS	+= usb.o
 
diff --git a/cpu/pxa/serial.c b/cpu/pxa/serial.c
deleted file mode 100644
index 9ba457e75aa..00000000000
--- a/cpu/pxa/serial.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <serial.h>
-#include <asm/arch/pxa-regs.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define FFUART_INDEX	0
-#define BTUART_INDEX	1
-#define STUART_INDEX	2
-
-#ifndef CONFIG_SERIAL_MULTI
-#if defined (CONFIG_FFUART)
-#define UART_INDEX	FFUART_INDEX
-#elif defined (CONFIG_BTUART)
-#define UART_INDEX	BTUART_INDEX
-#elif defined (CONFIG_STUART)
-#define UART_INDEX	STUART_INDEX
-#else
-#error "Bad: you didn't configure serial ..."
-#endif
-#endif
-
-void pxa_setbrg_dev (unsigned int uart_index)
-{
-	unsigned int quot = 0;
-
-	if (gd->baudrate == 1200)
-		quot = 768;
-	else if (gd->baudrate == 9600)
-		quot = 96;
-	else if (gd->baudrate == 19200)
-		quot = 48;
-	else if (gd->baudrate == 38400)
-		quot = 24;
-	else if (gd->baudrate == 57600)
-		quot = 16;
-	else if (gd->baudrate == 115200)
-		quot = 8;
-	else
-		hang ();
-
-	switch (uart_index) {
-		case FFUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_22_FFUART;
-#else
-			CKEN |= CKEN6_FFUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-			FFIER = 0;	/* Disable for now */
-			FFFCR = 0;	/* No fifos enabled */
-
-			/* set baud rate */
-			FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
-			FFDLL = quot & 0xff;
-			FFDLH = quot >> 8;
-			FFLCR = LCR_WLS0 | LCR_WLS1;
-
-			FFIER = IER_UUE;	/* Enable FFUART */
-		break;
-
-		case BTUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_21_BTUART;
-#else
-			CKEN |= CKEN7_BTUART;
-#endif /*  CONFIG_CPU_MONAHANS */
-
-			BTIER = 0;
-			BTFCR = 0;
-
-			/* set baud rate */
-			BTLCR = LCR_DLAB;
-			BTDLL = quot & 0xff;
-			BTDLH = quot >> 8;
-			BTLCR = LCR_WLS0 | LCR_WLS1;
-
-			BTIER = IER_UUE;	/* Enable BFUART */
-
-		break;
-
-		case STUART_INDEX:
-#ifdef CONFIG_CPU_MONAHANS
-			CKENA |= CKENA_23_STUART;
-#else
-			CKEN |= CKEN5_STUART;
-#endif /* CONFIG_CPU_MONAHANS */
-
-			STIER = 0;
-			STFCR = 0;
-
-			/* set baud rate */
-			STLCR = LCR_DLAB;
-			STDLL = quot & 0xff;
-			STDLH = quot >> 8;
-			STLCR = LCR_WLS0 | LCR_WLS1;
-
-			STIER = IER_UUE;			/* Enable STUART */
-			break;
-
-		default:
-			hang();
-	}
-}
-
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int pxa_init_dev (unsigned int uart_index)
-{
-	pxa_setbrg_dev (uart_index);
-
-	return (0);
-}
-
-
-/*
- * Output a single byte to the serial port.
- */
-void pxa_putc_dev (unsigned int uart_index,const char c)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-		/* wait for room in the tx FIFO on FFUART */
-			while ((FFLSR & LSR_TEMT) == 0)
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			FFTHR = c;
-			break;
-
-		case BTUART_INDEX:
-			while ((BTLSR & LSR_TEMT ) == 0 )
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			BTTHR = c;
-			break;
-
-		case STUART_INDEX:
-			while ((STLSR & LSR_TEMT ) == 0 )
-				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			STTHR = c;
-			break;
-	}
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		pxa_putc_dev (uart_index,'\r');
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_tstc_dev (unsigned int uart_index)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-			return FFLSR & LSR_DR;
-		case BTUART_INDEX:
-			return BTLSR & LSR_DR;
-		case STUART_INDEX:
-			return STLSR & LSR_DR;
-	}
-	return -1;
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int pxa_getc_dev (unsigned int uart_index)
-{
-	switch (uart_index) {
-		case FFUART_INDEX:
-			while (!(FFLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) FFRBR & 0xff;
-
-		case BTUART_INDEX:
-			while (!(BTLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) BTRBR & 0xff;
-		case STUART_INDEX:
-			while (!(STLSR & LSR_DR))
-			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
-			return (char) STRBR & 0xff;
-	}
-	return -1;
-}
-
-void
-pxa_puts_dev (unsigned int uart_index,const char *s)
-{
-	while (*s) {
-		pxa_putc_dev (uart_index,*s++);
-	}
-}
-
-#if defined (CONFIG_FFUART)
-static int ffuart_init(void)
-{
-	return pxa_init_dev(FFUART_INDEX);
-}
-
-static void ffuart_setbrg(void)
-{
-	return pxa_setbrg_dev(FFUART_INDEX);
-}
-
-static void ffuart_putc(const char c)
-{
-	return pxa_putc_dev(FFUART_INDEX,c);
-}
-
-static void ffuart_puts(const char *s)
-{
-	return pxa_puts_dev(FFUART_INDEX,s);
-}
-
-static int ffuart_getc(void)
-{
-	return pxa_getc_dev(FFUART_INDEX);
-}
-
-static int ffuart_tstc(void)
-{
-	return pxa_tstc_dev(FFUART_INDEX);
-}
-
-struct serial_device serial_ffuart_device =
-{
-	"serial_ffuart",
-	"PXA",
-	ffuart_init,
-	ffuart_setbrg,
-	ffuart_getc,
-	ffuart_tstc,
-	ffuart_putc,
-	ffuart_puts,
-};
-#endif
-
-#if defined (CONFIG_BTUART)
-static int btuart_init(void)
-{
-	return pxa_init_dev(BTUART_INDEX);
-}
-
-static void btuart_setbrg(void)
-{
-	return pxa_setbrg_dev(BTUART_INDEX);
-}
-
-static void btuart_putc(const char c)
-{
-	return pxa_putc_dev(BTUART_INDEX,c);
-}
-
-static void btuart_puts(const char *s)
-{
-	return pxa_puts_dev(BTUART_INDEX,s);
-}
-
-static int btuart_getc(void)
-{
-	return pxa_getc_dev(BTUART_INDEX);
-}
-
-static int btuart_tstc(void)
-{
-	return pxa_tstc_dev(BTUART_INDEX);
-}
-
-struct serial_device serial_btuart_device =
-{
-	"serial_btuart",
-	"PXA",
-	btuart_init,
-	btuart_setbrg,
-	btuart_getc,
-	btuart_tstc,
-	btuart_putc,
-	btuart_puts,
-};
-#endif
-
-#if defined (CONFIG_STUART)
-static int stuart_init(void)
-{
-	return pxa_init_dev(STUART_INDEX);
-}
-
-static void stuart_setbrg(void)
-{
-	return pxa_setbrg_dev(STUART_INDEX);
-}
-
-static void stuart_putc(const char c)
-{
-	return pxa_putc_dev(STUART_INDEX,c);
-}
-
-static void stuart_puts(const char *s)
-{
-	return pxa_puts_dev(STUART_INDEX,s);
-}
-
-static int stuart_getc(void)
-{
-	return pxa_getc_dev(STUART_INDEX);
-}
-
-static int stuart_tstc(void)
-{
-	return pxa_tstc_dev(STUART_INDEX);
-}
-
-struct serial_device serial_stuart_device =
-{
-	"serial_stuart",
-	"PXA",
-	stuart_init,
-	stuart_setbrg,
-	stuart_getc,
-	stuart_tstc,
-	stuart_putc,
-	stuart_puts,
-};
-#endif
-
-
-#ifndef CONFIG_SERIAL_MULTI
-inline int serial_init(void) {
-	return (pxa_init_dev(UART_INDEX));
-}
-void serial_setbrg(void) {
-	pxa_setbrg_dev(UART_INDEX);
-}
-int serial_getc(void) {
-	return(pxa_getc_dev(UART_INDEX));
-}
-int serial_tstc(void) {
-	return(pxa_tstc_dev(UART_INDEX));
-}
-void serial_putc(const char c) {
-	pxa_putc_dev(UART_INDEX,c);
-}
-void serial_puts(const char *s) {
-	pxa_puts_dev(UART_INDEX,s);
-}
-#endif	/* CONFIG_SERIAL_MULTI */
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 14c818decc4..4a35703d222 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -44,6 +44,7 @@ COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
 COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
 COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
 COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o
+COBJS-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 COBJS-$(CONFIG_SA1100_SERIAL) += serial_sa1100.o
 COBJS-$(CONFIG_S3C24X0_SERIAL) += serial_s3c24x0.o
 COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o
diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c
new file mode 100644
index 00000000000..9ba457e75aa
--- /dev/null
+++ b/drivers/serial/serial_pxa.c
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Marius Groeger <mgroeger@sysgo.de>
+ *
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Alex Zuepke <azu@sysgo.de>
+ *
+ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <watchdog.h>
+#include <serial.h>
+#include <asm/arch/pxa-regs.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FFUART_INDEX	0
+#define BTUART_INDEX	1
+#define STUART_INDEX	2
+
+#ifndef CONFIG_SERIAL_MULTI
+#if defined (CONFIG_FFUART)
+#define UART_INDEX	FFUART_INDEX
+#elif defined (CONFIG_BTUART)
+#define UART_INDEX	BTUART_INDEX
+#elif defined (CONFIG_STUART)
+#define UART_INDEX	STUART_INDEX
+#else
+#error "Bad: you didn't configure serial ..."
+#endif
+#endif
+
+void pxa_setbrg_dev (unsigned int uart_index)
+{
+	unsigned int quot = 0;
+
+	if (gd->baudrate == 1200)
+		quot = 768;
+	else if (gd->baudrate == 9600)
+		quot = 96;
+	else if (gd->baudrate == 19200)
+		quot = 48;
+	else if (gd->baudrate == 38400)
+		quot = 24;
+	else if (gd->baudrate == 57600)
+		quot = 16;
+	else if (gd->baudrate == 115200)
+		quot = 8;
+	else
+		hang ();
+
+	switch (uart_index) {
+		case FFUART_INDEX:
+#ifdef CONFIG_CPU_MONAHANS
+			CKENA |= CKENA_22_FFUART;
+#else
+			CKEN |= CKEN6_FFUART;
+#endif /* CONFIG_CPU_MONAHANS */
+
+			FFIER = 0;	/* Disable for now */
+			FFFCR = 0;	/* No fifos enabled */
+
+			/* set baud rate */
+			FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB;
+			FFDLL = quot & 0xff;
+			FFDLH = quot >> 8;
+			FFLCR = LCR_WLS0 | LCR_WLS1;
+
+			FFIER = IER_UUE;	/* Enable FFUART */
+		break;
+
+		case BTUART_INDEX:
+#ifdef CONFIG_CPU_MONAHANS
+			CKENA |= CKENA_21_BTUART;
+#else
+			CKEN |= CKEN7_BTUART;
+#endif /*  CONFIG_CPU_MONAHANS */
+
+			BTIER = 0;
+			BTFCR = 0;
+
+			/* set baud rate */
+			BTLCR = LCR_DLAB;
+			BTDLL = quot & 0xff;
+			BTDLH = quot >> 8;
+			BTLCR = LCR_WLS0 | LCR_WLS1;
+
+			BTIER = IER_UUE;	/* Enable BFUART */
+
+		break;
+
+		case STUART_INDEX:
+#ifdef CONFIG_CPU_MONAHANS
+			CKENA |= CKENA_23_STUART;
+#else
+			CKEN |= CKEN5_STUART;
+#endif /* CONFIG_CPU_MONAHANS */
+
+			STIER = 0;
+			STFCR = 0;
+
+			/* set baud rate */
+			STLCR = LCR_DLAB;
+			STDLL = quot & 0xff;
+			STDLH = quot >> 8;
+			STLCR = LCR_WLS0 | LCR_WLS1;
+
+			STIER = IER_UUE;			/* Enable STUART */
+			break;
+
+		default:
+			hang();
+	}
+}
+
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int pxa_init_dev (unsigned int uart_index)
+{
+	pxa_setbrg_dev (uart_index);
+
+	return (0);
+}
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void pxa_putc_dev (unsigned int uart_index,const char c)
+{
+	switch (uart_index) {
+		case FFUART_INDEX:
+		/* wait for room in the tx FIFO on FFUART */
+			while ((FFLSR & LSR_TEMT) == 0)
+				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			FFTHR = c;
+			break;
+
+		case BTUART_INDEX:
+			while ((BTLSR & LSR_TEMT ) == 0 )
+				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			BTTHR = c;
+			break;
+
+		case STUART_INDEX:
+			while ((STLSR & LSR_TEMT ) == 0 )
+				WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			STTHR = c;
+			break;
+	}
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		pxa_putc_dev (uart_index,'\r');
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int pxa_tstc_dev (unsigned int uart_index)
+{
+	switch (uart_index) {
+		case FFUART_INDEX:
+			return FFLSR & LSR_DR;
+		case BTUART_INDEX:
+			return BTLSR & LSR_DR;
+		case STUART_INDEX:
+			return STLSR & LSR_DR;
+	}
+	return -1;
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int pxa_getc_dev (unsigned int uart_index)
+{
+	switch (uart_index) {
+		case FFUART_INDEX:
+			while (!(FFLSR & LSR_DR))
+			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			return (char) FFRBR & 0xff;
+
+		case BTUART_INDEX:
+			while (!(BTLSR & LSR_DR))
+			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			return (char) BTRBR & 0xff;
+		case STUART_INDEX:
+			while (!(STLSR & LSR_DR))
+			WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
+			return (char) STRBR & 0xff;
+	}
+	return -1;
+}
+
+void
+pxa_puts_dev (unsigned int uart_index,const char *s)
+{
+	while (*s) {
+		pxa_putc_dev (uart_index,*s++);
+	}
+}
+
+#if defined (CONFIG_FFUART)
+static int ffuart_init(void)
+{
+	return pxa_init_dev(FFUART_INDEX);
+}
+
+static void ffuart_setbrg(void)
+{
+	return pxa_setbrg_dev(FFUART_INDEX);
+}
+
+static void ffuart_putc(const char c)
+{
+	return pxa_putc_dev(FFUART_INDEX,c);
+}
+
+static void ffuart_puts(const char *s)
+{
+	return pxa_puts_dev(FFUART_INDEX,s);
+}
+
+static int ffuart_getc(void)
+{
+	return pxa_getc_dev(FFUART_INDEX);
+}
+
+static int ffuart_tstc(void)
+{
+	return pxa_tstc_dev(FFUART_INDEX);
+}
+
+struct serial_device serial_ffuart_device =
+{
+	"serial_ffuart",
+	"PXA",
+	ffuart_init,
+	ffuart_setbrg,
+	ffuart_getc,
+	ffuart_tstc,
+	ffuart_putc,
+	ffuart_puts,
+};
+#endif
+
+#if defined (CONFIG_BTUART)
+static int btuart_init(void)
+{
+	return pxa_init_dev(BTUART_INDEX);
+}
+
+static void btuart_setbrg(void)
+{
+	return pxa_setbrg_dev(BTUART_INDEX);
+}
+
+static void btuart_putc(const char c)
+{
+	return pxa_putc_dev(BTUART_INDEX,c);
+}
+
+static void btuart_puts(const char *s)
+{
+	return pxa_puts_dev(BTUART_INDEX,s);
+}
+
+static int btuart_getc(void)
+{
+	return pxa_getc_dev(BTUART_INDEX);
+}
+
+static int btuart_tstc(void)
+{
+	return pxa_tstc_dev(BTUART_INDEX);
+}
+
+struct serial_device serial_btuart_device =
+{
+	"serial_btuart",
+	"PXA",
+	btuart_init,
+	btuart_setbrg,
+	btuart_getc,
+	btuart_tstc,
+	btuart_putc,
+	btuart_puts,
+};
+#endif
+
+#if defined (CONFIG_STUART)
+static int stuart_init(void)
+{
+	return pxa_init_dev(STUART_INDEX);
+}
+
+static void stuart_setbrg(void)
+{
+	return pxa_setbrg_dev(STUART_INDEX);
+}
+
+static void stuart_putc(const char c)
+{
+	return pxa_putc_dev(STUART_INDEX,c);
+}
+
+static void stuart_puts(const char *s)
+{
+	return pxa_puts_dev(STUART_INDEX,s);
+}
+
+static int stuart_getc(void)
+{
+	return pxa_getc_dev(STUART_INDEX);
+}
+
+static int stuart_tstc(void)
+{
+	return pxa_tstc_dev(STUART_INDEX);
+}
+
+struct serial_device serial_stuart_device =
+{
+	"serial_stuart",
+	"PXA",
+	stuart_init,
+	stuart_setbrg,
+	stuart_getc,
+	stuart_tstc,
+	stuart_putc,
+	stuart_puts,
+};
+#endif
+
+
+#ifndef CONFIG_SERIAL_MULTI
+inline int serial_init(void) {
+	return (pxa_init_dev(UART_INDEX));
+}
+void serial_setbrg(void) {
+	pxa_setbrg_dev(UART_INDEX);
+}
+int serial_getc(void) {
+	return(pxa_getc_dev(UART_INDEX));
+}
+int serial_tstc(void) {
+	return(pxa_tstc_dev(UART_INDEX));
+}
+void serial_putc(const char c) {
+	pxa_putc_dev(UART_INDEX,c);
+}
+void serial_puts(const char *s) {
+	pxa_puts_dev(UART_INDEX,s);
+}
+#endif	/* CONFIG_SERIAL_MULTI */
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index 82d14014692..b924758dc29 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -60,6 +60,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	     1	/* we use FFUART on CERF PXA */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 75c5f9bb3e0..b150c221a3d 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -57,6 +57,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index ed1845009e2..12bab4702a1 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -53,6 +53,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART		1	/* we use FFUART on CSB226          */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/delta.h b/include/configs/delta.h
index bacbd90b5dc..e7186e83990 100644
--- a/include/configs/delta.h
+++ b/include/configs/delta.h
@@ -82,6 +82,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART		1
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index 69654c7c0f5..ed03ad32a07 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -50,6 +50,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART		1	/* we use FFUART on CSB226 */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/logodl.h b/include/configs/logodl.h
index 889a9a344d4..5b903f0dcb6 100644
--- a/include/configs/logodl.h
+++ b/include/configs/logodl.h
@@ -50,6 +50,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART		1	/* we use FFUART                    */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index 2cf9c028159..43913cada96 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -64,6 +64,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index ed873faca7f..635ef71bc92 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -62,6 +62,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index 7485f7241ce..2cae8ca9b39 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -100,6 +100,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART on LUBBOCK */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 49173181fb5..49045fd069d 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -65,6 +65,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_SERIAL_MULTI
 #define CONFIG_FFUART	       1       /* we use FFUART on Conxs */
 #define CONFIG_BTUART	       1       /* we use BTUART on Conxs */
diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h
index 197ac0bbd6a..9a20cce457b 100644
--- a/include/configs/wepep250.h
+++ b/include/configs/wepep250.h
@@ -33,6 +33,7 @@
 /*
  * Select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_BTUART          1       /* BTUART is default on WEP dev board */
 #define CONFIG_BAUDRATE   115200
 
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 1632d29622a..83883f6fd5e 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -55,6 +55,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
 
 
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index c8bdf3186bb..f18701abf57 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -77,6 +77,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h
index 7e2abbf3464..2697ccaf62a 100644
--- a/include/configs/xsengine.h
+++ b/include/configs/xsengine.h
@@ -99,6 +99,7 @@
 #define CONFIG_SMC_USE_32_BIT		1
 
 /* select serial console configuration */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART			1
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h
index 217636a6183..15c37087f65 100644
--- a/include/configs/zylonite.h
+++ b/include/configs/zylonite.h
@@ -72,6 +72,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1
 
 /* allow to overwrite serial and ethaddr */
-- 
cgit v1.3.1


From 3ea201b016ab259a5ac8824af767569522768c47 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun, 31 May 2009 12:44:27 +0200
Subject: lh7a40x: move serial driver to drivers/serial

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 cpu/lh7a40x/Makefile            |   2 +-
 cpu/lh7a40x/serial.c            | 184 ----------------------------------------
 drivers/serial/Makefile         |   1 +
 drivers/serial/serial_lh7a40x.c | 184 ++++++++++++++++++++++++++++++++++++++++
 include/configs/lpd7a400.h      |   1 +
 include/configs/lpd7a404.h      |   1 +
 6 files changed, 188 insertions(+), 185 deletions(-)
 delete mode 100644 cpu/lh7a40x/serial.c
 create mode 100644 drivers/serial/serial_lh7a40x.c

(limited to 'include')

diff --git a/cpu/lh7a40x/Makefile b/cpu/lh7a40x/Makefile
index b9ae76effac..1b3f58abb93 100644
--- a/cpu/lh7a40x/Makefile
+++ b/cpu/lh7a40x/Makefile
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-COBJS	= cpu.o speed.o serial.o timer.o
+COBJS	= cpu.o speed.o timer.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/lh7a40x/serial.c b/cpu/lh7a40x/serial.c
deleted file mode 100644
index 4767489aef0..00000000000
--- a/cpu/lh7a40x/serial.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONSOLE_UART1)
-# define UART_CONSOLE 1
-#elif defined(CONFIG_CONSOLE_UART2)
-# define UART_CONSOLE 2
-#elif defined(CONFIG_CONSOLE_UART3)
-# define UART_CONSOLE 3
-#else
-# error "No console configured ... "
-#endif
-
-void serial_setbrg (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-	int i;
-	unsigned int reg = 0;
-
-	/*
-	 * userguide 15.1.2.4
-	 *
-	 * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
-	 *
-	 *   UART_REF_FREQ = external system clock input / 2 (Hz)
-	 *   BAUD is desired baudrate (bits/s)
-	 *
-	 *   NOTE: we add (divisor/2) to numerator to round for
-	 *         more precision
-	 */
-	reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
-	uart->brcon = reg;
-
-	for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* UART must be enabled before writing to any config registers */
-	uart->con |= (UART_EN);
-
-#ifdef CONFIG_CONSOLE_UART1
-	/* infrared disabled */
-	uart->con |= UART_SIRD;
-#endif
-	/* loopback disabled */
-	uart->con &= ~(UART_LBE);
-
-	/* modem lines and tx/rx polarities */
-	uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
-
-	/* FIFO enable, N81 */
-	uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
-
-	/* set baudrate */
-	serial_setbrg ();
-
-	/* enable rx interrupt */
-	uart->inten |= UART_RI;
-
-	return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	/* wait for character to arrive */
-	while (uart->status & UART_RXFE);
-
-	return(uart->data & 0xff);
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
-	switch(on) {
-	case 0:
-	default:
-		break; /* return current */
-	case 1:
-		hwflow = 1; /* turn on */
-		break;
-	case -1:
-		hwflow = 0; /* turn off */
-		break;
-	}
-	return hwflow;
-}
-#endif
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet = 0;
-void disable_putc(void)
-{
-	be_quiet = 1;
-}
-
-void enable_putc(void)
-{
-	be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-#ifdef CONFIG_MODEM_SUPPORT
-	if (be_quiet)
-		return;
-#endif
-
-	/* wait for room in the tx FIFO */
-	while (!(uart->status & UART_TXFE));
-
-#ifdef CONFIG_HWFLOW
-	/* Wait for CTS up */
-	while(hwflow && !(uart->status & UART_CTS));
-#endif
-
-	uart->data = c;
-
-	/* If \n, also do \r */
-	if (c == '\n')
-		serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
-	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-	return(!(uart->status & UART_RXFE));
-}
-
-void
-serial_puts (const char *s)
-{
-	while (*s) {
-		serial_putc (*s++);
-	}
-}
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 4a35703d222..ab5d5654d62 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -39,6 +39,7 @@ COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
 COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
 COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
 COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
+COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
 COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
 COBJS-$(CONFIG_MX31_UART) += serial_mx31.o
 COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
new file mode 100644
index 00000000000..4767489aef0
--- /dev/null
+++ b/drivers/serial/serial_lh7a40x.c
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <common.h>
+#include <lh7a40x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_CONSOLE_UART1)
+# define UART_CONSOLE 1
+#elif defined(CONFIG_CONSOLE_UART2)
+# define UART_CONSOLE 2
+#elif defined(CONFIG_CONSOLE_UART3)
+# define UART_CONSOLE 3
+#else
+# error "No console configured ... "
+#endif
+
+void serial_setbrg (void)
+{
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
+	int i;
+	unsigned int reg = 0;
+
+	/*
+	 * userguide 15.1.2.4
+	 *
+	 * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
+	 *
+	 *   UART_REF_FREQ = external system clock input / 2 (Hz)
+	 *   BAUD is desired baudrate (bits/s)
+	 *
+	 *   NOTE: we add (divisor/2) to numerator to round for
+	 *         more precision
+	 */
+	reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
+	uart->brcon = reg;
+
+	for (i = 0; i < 100; i++);
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ *
+ */
+int serial_init (void)
+{
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
+
+	/* UART must be enabled before writing to any config registers */
+	uart->con |= (UART_EN);
+
+#ifdef CONFIG_CONSOLE_UART1
+	/* infrared disabled */
+	uart->con |= UART_SIRD;
+#endif
+	/* loopback disabled */
+	uart->con &= ~(UART_LBE);
+
+	/* modem lines and tx/rx polarities */
+	uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
+
+	/* FIFO enable, N81 */
+	uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
+
+	/* set baudrate */
+	serial_setbrg ();
+
+	/* enable rx interrupt */
+	uart->inten |= UART_RI;
+
+	return (0);
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc (void)
+{
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
+
+	/* wait for character to arrive */
+	while (uart->status & UART_RXFE);
+
+	return(uart->data & 0xff);
+}
+
+#ifdef CONFIG_HWFLOW
+static int hwflow = 0; /* turned off by default */
+int hwflow_onoff(int on)
+{
+	switch(on) {
+	case 0:
+	default:
+		break; /* return current */
+	case 1:
+		hwflow = 1; /* turn on */
+		break;
+	case -1:
+		hwflow = 0; /* turn off */
+		break;
+	}
+	return hwflow;
+}
+#endif
+
+#ifdef CONFIG_MODEM_SUPPORT
+static int be_quiet = 0;
+void disable_putc(void)
+{
+	be_quiet = 1;
+}
+
+void enable_putc(void)
+{
+	be_quiet = 0;
+}
+#endif
+
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc (const char c)
+{
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
+
+#ifdef CONFIG_MODEM_SUPPORT
+	if (be_quiet)
+		return;
+#endif
+
+	/* wait for room in the tx FIFO */
+	while (!(uart->status & UART_TXFE));
+
+#ifdef CONFIG_HWFLOW
+	/* Wait for CTS up */
+	while(hwflow && !(uart->status & UART_CTS));
+#endif
+
+	uart->data = c;
+
+	/* If \n, also do \r */
+	if (c == '\n')
+		serial_putc ('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc (void)
+{
+	lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
+
+	return(!(uart->status & UART_RXFE));
+}
+
+void
+serial_puts (const char *s)
+{
+	while (*s) {
+		serial_putc (*s++);
+	}
+}
diff --git a/include/configs/lpd7a400.h b/include/configs/lpd7a400.h
index b1bd74fc6fb..bf4a57d249b 100644
--- a/include/configs/lpd7a400.h
+++ b/include/configs/lpd7a400.h
@@ -43,6 +43,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_LH7A40X_SERIAL
 #define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
 
 /* allow to overwrite serial and ethaddr */
diff --git a/include/configs/lpd7a404.h b/include/configs/lpd7a404.h
index b197674d47a..102c0af3b9f 100644
--- a/include/configs/lpd7a404.h
+++ b/include/configs/lpd7a404.h
@@ -43,6 +43,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_LH7A40X_SERIAL
 #define CONFIG_CONSOLE_UART2	/* UART2 LH7A40x for console */
 
 /* allow to overwrite serial and ethaddr */
-- 
cgit v1.3.1


From 660888b7fb8840ce169dcd2589e49ab44c46b87b Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Sun, 31 May 2009 12:44:37 +0200
Subject: ZOOM2 Add serial support.

Zoom2 serial is in general supplied by one of the 4 UARTS on the debug board.
The default serial is from the USB connector on left side of the debug board.
The USB connector will produce 2 of the 4 UARTS.  On your host pick the first
enumeration.

The details of the setting of the serial gpmc setup are not available.
The values were provided by another party.

The serial port set up is the same with Zoom1.
Baud rate 115200, 8 bit data, no parity, 1 stop bit, no flow.

The kernel bootargs are
console=ttyS3,115200n8

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 board/omap3/zoom2/Makefile       |   3 +-
 board/omap3/zoom2/zoom2.c        |  38 ++++++++++++
 board/omap3/zoom2/zoom2_serial.c | 130 +++++++++++++++++++++++++++++++++++++++
 board/omap3/zoom2/zoom2_serial.h |  75 ++++++++++++++++++++++
 common/serial.c                  |   2 +
 drivers/serial/ns16550.c         |   4 +-
 include/configs/omap3_zoom2.h    |  26 ++++----
 include/serial.h                 |   7 +++
 8 files changed, 269 insertions(+), 16 deletions(-)
 create mode 100644 board/omap3/zoom2/zoom2_serial.c
 create mode 100644 board/omap3/zoom2/zoom2_serial.h

(limited to 'include')

diff --git a/board/omap3/zoom2/Makefile b/board/omap3/zoom2/Makefile
index b8fa5a78bbe..d27990c9938 100644
--- a/board/omap3/zoom2/Makefile
+++ b/board/omap3/zoom2/Makefile
@@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS	:= zoom2.o \
-	debug_board.o
+	debug_board.o \
+	zoom2_serial.o
 
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c
index 0700c56d709..83e02f6b46d 100644
--- a/board/omap3/zoom2/zoom2.c
+++ b/board/omap3/zoom2/zoom2.c
@@ -30,10 +30,32 @@
  */
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-types.h>
 #include "zoom2.h"
+#include "zoom2_serial.h"
+
+/*
+ * This the the zoom2, board specific, gpmc configuration for the
+ * quad uart on the debug board.   The more general gpmc configurations
+ * are setup at the cpu level in cpu/arm_cortexa8/omap3/mem.c
+ *
+ * The details of the setting of the serial gpmc setup are not available.
+ * The values were provided by another party.
+ */
+extern void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base,
+			       u32 base, u32 size);
+
+static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
+	0x00011000,
+	0x001F1F01,
+	0x00080803,
+	0x1D091D09,
+	0x041D1F1F,
+	0x1D0904C4, 0
+};
 
 /*
  * Routine: board_init
@@ -42,13 +64,29 @@
 int board_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	gpmc_csx_t *serial_cs_base;
+	u32 *gpmc_config;
 
 	gpmc_init ();		/* in SRAM or SDRAM, finish GPMC */
+
+	/* Configure console support on zoom2 */
+	gpmc_config = gpmc_serial_TL16CP754C;
+	serial_cs_base = (gpmc_csx_t *) (GPMC_CONFIG_CS0_BASE +
+					 (3 * GPMC_CONFIG_WIDTH));
+	enable_gpmc_config(gpmc_config,
+			   serial_cs_base,
+			   SERIAL_TL16CP754C_BASE,
+			   GPMC_SIZE_16M);
+
 	/* board id for Linux */
 	gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
 	/* boot param addr */
 	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
 
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
 	return 0;
 }
 
diff --git a/board/omap3/zoom2/zoom2_serial.c b/board/omap3/zoom2/zoom2_serial.c
new file mode 100644
index 00000000000..a3d777dfadd
--- /dev/null
+++ b/board/omap3/zoom2/zoom2_serial.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This file was adapted from cpu/mpc5xxx/serial.c
+ *
+ */
+
+#include <common.h>
+#include <serial.h>
+#include <ns16550.h>
+#include <asm/arch/cpu.h>
+#include "zoom2_serial.h"
+
+int quad_init_dev (unsigned long base)
+{
+	/*
+	 * The Quad UART is on the debug board.
+	 * Check if the debug board is attached before using the UART
+	 */
+	if (zoom2_debug_board_connected ()) {
+		NS16550_t com_port = (NS16550_t) base;
+		int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+
+		/*
+		 * Zoom2 has a board specific initialization of its UART.
+		 * This generic initialization has been copied from
+		 * drivers/serial/ns16550.c. The macros have been expanded.
+		 *
+		 * Do the following instead of
+		 *
+		 * NS16550_init (com_port, clock_divisor);
+		 */
+		com_port->ier = 0x00;
+
+		/*
+		 * On Zoom2 board Set pre-scalar to 1
+		 * CLKSEL is GND => MCR[7] is 1 => preslr is 4
+		 * So change the prescl to 1
+		 */
+		com_port->lcr = 0xBF;
+		com_port->fcr |= 0x10;
+		com_port->mcr &= 0x7F;
+
+		/* This is generic ns16550.c setup */
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = 0;
+		com_port->dlm = 0;
+		com_port->lcr = UART_LCR_8N1;
+		com_port->mcr = UART_MCR_DTR | UART_MCR_RTS;
+		com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR |
+			UART_FCR_TXSR;
+		com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1;
+		com_port->dll = baud_divisor & 0xff;
+		com_port->dlm = (baud_divisor >> 8) & 0xff;
+		com_port->lcr = UART_LCR_8N1;
+	}
+	/*
+	 * We have to lie here, otherwise the board init code will hang
+	 * on the check
+	 */
+	return 0;
+}
+
+void quad_putc_dev (unsigned long base, const char c)
+{
+	if (zoom2_debug_board_connected ()) {
+
+		if (c == '\n')
+			quad_putc_dev (base, '\r');
+
+		NS16550_putc ((NS16550_t) base, c);
+	}
+}
+
+void quad_puts_dev (unsigned long base, const char *s)
+{
+	if (zoom2_debug_board_connected ()) {
+		while ((s != NULL) && (*s != '\0'))
+			quad_putc_dev (base, *s++);
+	}
+}
+
+int quad_getc_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ())
+		return NS16550_getc ((NS16550_t) base);
+	else
+		return 0;
+}
+
+int quad_tstc_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ())
+		return NS16550_tstc ((NS16550_t) base);
+	else
+		return 0;
+}
+
+void quad_setbrg_dev (unsigned long base)
+{
+	if (zoom2_debug_board_connected ()) {
+
+		int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 /
+			CONFIG_BAUDRATE;
+
+		NS16550_reinit ((NS16550_t) base, clock_divisor);
+	}
+}
+
+QUAD_INIT (0)
+QUAD_INIT (1)
+QUAD_INIT (2)
+QUAD_INIT (3)
diff --git a/board/omap3/zoom2/zoom2_serial.h b/board/omap3/zoom2/zoom2_serial.h
new file mode 100644
index 00000000000..c98158f1ba6
--- /dev/null
+++ b/board/omap3/zoom2/zoom2_serial.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef ZOOM2_SERIAL_H
+#define ZOOM2_SERIAL_H
+
+extern int zoom2_debug_board_connected (void);
+
+#define SERIAL_TL16CP754C_BASE	0x10000000	/* Zoom2 Serial chip address */
+
+#define QUAD_BASE_0	SERIAL_TL16CP754C_BASE
+#define QUAD_BASE_1	(SERIAL_TL16CP754C_BASE + 0x100)
+#define QUAD_BASE_2	(SERIAL_TL16CP754C_BASE + 0x200)
+#define QUAD_BASE_3	(SERIAL_TL16CP754C_BASE + 0x300)
+
+#define S(a) #a
+#define N(a) S(quad##a)
+#define U(a) S(UART##a)
+
+#define QUAD_INIT(n)				\
+int quad_init_##n(void)				\
+{						\
+	return quad_init_dev(QUAD_BASE_##n);	\
+}						\
+void quad_setbrg_##n(void)			\
+{						\
+	quad_setbrg_dev(QUAD_BASE_##n);		\
+}						\
+void quad_putc_##n(const char c)		\
+{						\
+	quad_putc_dev(QUAD_BASE_##n, c);	\
+}						\
+void quad_puts_##n(const char *s)		\
+{						\
+	quad_puts_dev(QUAD_BASE_##n, s);	\
+}						\
+int quad_getc_##n(void)				\
+{						\
+	return quad_getc_dev(QUAD_BASE_##n);	\
+}						\
+int quad_tstc_##n(void)				\
+{						\
+	return quad_tstc_dev(QUAD_BASE_##n);	\
+}						\
+struct serial_device zoom2_serial_device##n =	\
+{						\
+	N(n),					\
+	U(n),					\
+	quad_init_##n,				\
+	quad_setbrg_##n,			\
+	quad_getc_##n,				\
+	quad_tstc_##n,				\
+	quad_putc_##n,				\
+	quad_puts_##n,				\
+};
+
+#endif /* ZOOM2_SERIAL_H */
diff --git a/common/serial.c b/common/serial.c
index 09385d017d4..dd80e7c863e 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -68,6 +68,8 @@ struct serial_device *__default_serial_console (void)
 #else
 #error "CONFIG_SERIAL? missing."
 #endif
+#elif defined(CONFIG_OMAP3_ZOOM2)
+		return ZOOM2_DEFAULT_SERIAL_DEVICE;
 #else
 #error No default console
 #endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 657c9dadf9c..2fcc8c31633 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -17,7 +17,7 @@
 void NS16550_init (NS16550_t com_port, int baud_divisor)
 {
 	com_port->ier = 0x00;
-#ifdef CONFIG_OMAP
+#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
 	com_port->mdr1 = 0x7;	/* mode select reset TL16C750*/
 #endif
 	com_port->lcr = UART_LCR_BKSE | UART_LCRVAL;
@@ -30,7 +30,7 @@ void NS16550_init (NS16550_t com_port, int baud_divisor)
 	com_port->dll = baud_divisor & 0xff;
 	com_port->dlm = (baud_divisor >> 8) & 0xff;
 	com_port->lcr = UART_LCRVAL;
-#if defined(CONFIG_OMAP)
+#if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2)
 #if defined(CONFIG_APTIX)
 	com_port->mdr1 = 3;	/* /13 mode so Aptix 6MHz can hit 115200 */
 #else
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 8aea4cbc074..d9a9c1a830b 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -69,26 +69,26 @@
 
 /*
  * NS16550 Configuration
+ * Zoom2 uses the TL16CP754C on the debug board
  */
-#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+#define CONFIG_SERIAL_MULTI		1
+/*
+ * 0 - 1 : first  USB with respect to the left edge of the debug board
+ * 2 - 3 : second USB with respect to the left edge of the debug board
+ */
+#define ZOOM2_DEFAULT_SERIAL_DEVICE	(&zoom2_serial_device0)
+
+#define V_NS16550_CLK			(1843200)	/* 1.8432 Mhz */
 
 #define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_REG_SIZE	(-2)
 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
-
-/*
- * select serial console configuration
- */
-#define CONFIG_CONS_INDEX		3
-#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
-#define CONFIG_SERIAL3			3	/* UART3 */
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200}
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
-					115200}
+
 #define CONFIG_MMC			1
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
diff --git a/include/serial.h b/include/serial.h
index e3d8b3679b5..aca5221044f 100644
--- a/include/serial.h
+++ b/include/serial.h
@@ -42,6 +42,13 @@ extern struct serial_device s3c24xx_serial1_device;
 extern struct serial_device s3c24xx_serial2_device;
 #endif
 
+#if defined(CONFIG_OMAP3_ZOOM2)
+extern struct serial_device zoom2_serial_device0;
+extern struct serial_device zoom2_serial_device1;
+extern struct serial_device zoom2_serial_device2;
+extern struct serial_device zoom2_serial_device3;
+#endif
+
 extern struct serial_device serial_ffuart_device;
 extern struct serial_device serial_btuart_device;
 extern struct serial_device serial_stuart_device;
-- 
cgit v1.3.1


From 83ae698ff26b81b569ca32f7f2b008ad0da15e66 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Sun, 31 May 2009 12:44:39 +0200
Subject: ZOOM2 Add led support.

This patch controls the large LED on the top left of the zoom2.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
---
 board/omap3/zoom2/Makefile    |   8 ++-
 board/omap3/zoom2/led.c       | 129 ++++++++++++++++++++++++++++++++++++++++++
 board/omap3/zoom2/zoom2.c     |   4 +-
 include/configs/omap3_zoom2.h |  16 ++++++
 4 files changed, 153 insertions(+), 4 deletions(-)
 create mode 100644 board/omap3/zoom2/led.c

(limited to 'include')

diff --git a/board/omap3/zoom2/Makefile b/board/omap3/zoom2/Makefile
index d27990c9938..2feafbee1df 100644
--- a/board/omap3/zoom2/Makefile
+++ b/board/omap3/zoom2/Makefile
@@ -25,10 +25,12 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= zoom2.o \
-	debug_board.o \
-	zoom2_serial.o
+COBJS-y := $(BOARD).o
+COBJS-y += debug_board.o
+COBJS-y += zoom2_serial.o
+COBJS-$(CONFIG_STATUS_LED) += led.o
 
+COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
 
diff --git a/board/omap3/zoom2/led.c b/board/omap3/zoom2/led.c
new file mode 100644
index 00000000000..4e14c58f0b1
--- /dev/null
+++ b/board/omap3/zoom2/led.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix <Tom.Rix@windriver.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <status_led.h>
+#include <asm/arch/cpu.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
+
+static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF};
+
+/*
+ * GPIO LEDs
+ * 173 red
+ * 154 blue
+ * 61  blue2
+ */
+#define ZOOM2_LED_RED	173
+#define ZOOM2_LED_BLUE	154
+#define ZOOM2_LED_BLUE2	61
+
+void red_LED_off (void)
+{
+	/* red */
+	if (!omap_request_gpio(ZOOM2_LED_RED)) {
+		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_RED, 0);
+	}
+	saved_state[STATUS_LED_RED] = STATUS_LED_OFF;
+}
+
+void blue_LED_off (void)
+{
+	/* blue */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 0);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 0);
+	}
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF;
+}
+
+void red_LED_on (void)
+{
+	blue_LED_off ();
+
+	/* red */
+	if (!omap_request_gpio(ZOOM2_LED_RED)) {
+		omap_set_gpio_direction(ZOOM2_LED_RED, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_RED, 1);
+	}
+	saved_state[STATUS_LED_RED] = STATUS_LED_ON;
+}
+
+void blue_LED_on (void)
+{
+	red_LED_off ();
+
+	/* blue */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE, 1);
+	}
+
+	/* blue 2 */
+	if (!omap_request_gpio(ZOOM2_LED_BLUE2)) {
+		omap_set_gpio_direction(ZOOM2_LED_BLUE2, 0);
+		omap_set_gpio_dataout(ZOOM2_LED_BLUE2, 1);
+	}
+
+	saved_state[STATUS_LED_BLUE] = STATUS_LED_ON;
+}
+
+void __led_init (led_id_t mask, int state)
+{
+	__led_set (mask, state);
+}
+
+void __led_toggle (led_id_t mask)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE])
+			blue_LED_off ();
+		else
+			blue_LED_on ();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == saved_state[STATUS_LED_RED])
+			red_LED_off ();
+		else
+			red_LED_on ();
+	}
+}
+
+void __led_set (led_id_t mask, int state)
+{
+	if (STATUS_LED_BLUE == mask) {
+		if (STATUS_LED_ON == state)
+			blue_LED_on ();
+		else
+			blue_LED_off ();
+	} else if (STATUS_LED_RED == mask) {
+		if (STATUS_LED_ON == state)
+			red_LED_on ();
+		else
+			red_LED_off ();
+	}
+}
diff --git a/board/omap3/zoom2/zoom2.c b/board/omap3/zoom2/zoom2.c
index 83e02f6b46d..e5c248de711 100644
--- a/board/omap3/zoom2/zoom2.c
+++ b/board/omap3/zoom2/zoom2.c
@@ -29,6 +29,9 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#ifdef CONFIG_STATUS_LED
+#include <status_led.h>
+#endif
 #include <asm/io.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/mux.h>
@@ -86,7 +89,6 @@ int board_init (void)
 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
 	status_led_set (STATUS_LED_BOOT, STATUS_LED_ON);
 #endif
-
 	return 0;
 }
 
diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index d9a9c1a830b..1d696b6e154 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -93,6 +93,22 @@
 #define CONFIG_OMAP3_MMC		1
 #define CONFIG_DOS_PARTITION		1
 
+/* Status LED */
+#define CONFIG_STATUS_LED		1 /* Status LED enabled	*/
+#define CONFIG_BOARD_SPECIFIC_LED	1
+#define STATUS_LED_BLUE			0
+#define STATUS_LED_RED			1
+/* Blue */
+#define STATUS_LED_BIT			STATUS_LED_BLUE
+#define STATUS_LED_STATE		STATUS_LED_ON
+#define STATUS_LED_PERIOD		(CONFIG_SYS_HZ / 2)
+/* Red */
+#define STATUS_LED_BIT1			STATUS_LED_RED
+#define STATUS_LED_STATE1		STATUS_LED_OFF
+#define STATUS_LED_PERIOD1		(CONFIG_SYS_HZ / 2)
+/* Optional value */
+#define STATUS_LED_BOOT			STATUS_LED_BIT
+
 /* commands to include */
 #include <config_cmd_default.h>
 
-- 
cgit v1.3.1


From 3962c4f9fc4482a6547f3c3d3d5e986e625abb8a Mon Sep 17 00:00:00 2001
From: Dirk Behme <dirk.behme@googlemail.com>
Date: Sun, 31 May 2009 12:44:41 +0200
Subject: OMAP3: Zoom2: Enable Board and CPU info

With other OMAP3 boards we recently switched to CPU and Board
info API. From parallel merge, this is missing for Zoom2.
Enable it for Zoom2, too.

Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
Acked-by: Tom Rix <Tom.Rix@windriver.com>
---
 include/configs/omap3_zoom2.h | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'include')

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index 1d696b6e154..e2574192cf7 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -43,6 +43,12 @@
 #include <asm/arch/cpu.h>	/* get chip and board defs */
 #include <asm/arch/omap3.h>
 
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
 /* Clock Defines */
 #define V_OSCK			26000000	/* Clock output from T2 */
 #define V_SCLK			(V_OSCK >> 1)
-- 
cgit v1.3.1


From b32e189079fa16e1b647ac6b949fd4e0a9435343 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun, 31 May 2009 12:44:46 +0200
Subject: at91: move cpu name define to arm/arch/ cpu header

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 include/asm-arm/arch-at91/at91cap9.h    | 5 +++++
 include/asm-arm/arch-at91/at91sam9260.h | 9 +++++++++
 include/asm-arm/arch-at91/at91sam9261.h | 4 ++++
 include/asm-arm/arch-at91/at91sam9263.h | 4 ++++
 include/asm-arm/arch-at91/at91sam9rl.h  | 5 +++++
 include/configs/at91cap9adk.h           | 1 -
 include/configs/at91sam9260ek.h         | 2 --
 include/configs/at91sam9261ek.h         | 1 -
 include/configs/at91sam9263ek.h         | 1 -
 include/configs/at91sam9rlek.h          | 1 -
 include/configs/pm9263.h                | 2 --
 11 files changed, 27 insertions(+), 8 deletions(-)

(limited to 'include')

diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index 0b522281386..b128ac5a393 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -134,4 +134,9 @@
 
 #define CONFIG_DRAM_BASE	AT91_CHIPSELECT_6
 
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME	"AT91CAP9"
+
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 920a7f3c9ff..73975f484ec 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -121,4 +121,13 @@
 #define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
 #define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
 
+/*
+ * Cpu Name
+ */
+#if defined(CONFIG_AT91SAM9260)
+#define AT91_CPU_NAME	"AT91SAM9260"
+#elif defined(CONFIG_AT91SAM9G20)
+#define AT91_CPU_NAME	"AT91SAM9G20"
+#endif
+
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 752d81dfe3f..b303e07bbc4 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -101,5 +101,9 @@
 #define AT91SAM9261_UHP_BASE	0x00500000	/* USB Host controller */
 #define AT91SAM9261_LCDC_BASE	0x00600000	/* LDC controller */
 
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME	"AT91SAM9261"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index 07b265f23a1..966a6836fe9 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -124,5 +124,9 @@
 #define AT91SAM9263_DMAC_BASE	0x00800000	/* DMA Controller */
 #define AT91SAM9263_UHP_BASE	0x00a00000	/* USB Host controller */
 
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME	"AT91SAM9263"
 
 #endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 215bbc8d6a7..4dd8037c6e6 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -112,4 +112,9 @@
 #define AT91SAM9RL_LCDC_BASE	0x00500000	/* LCD Controller */
 #define AT91SAM9RL_UDPHS_BASE	0x00600000	/* USB Device HS controller */
 
+/*
+ * Cpu Name
+ */
+#define AT91_CPU_NAME	"AT91SAM9RL"
+
 #endif
diff --git a/include/configs/at91cap9adk.h b/include/configs/at91cap9adk.h
index b2e6d7d02c9..526cd60ae09 100644
--- a/include/configs/at91cap9adk.h
+++ b/include/configs/at91cap9adk.h
@@ -28,7 +28,6 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91CAP9"
 #define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h
index e46c9d6ae65..1828c63afd9 100644
--- a/include/configs/at91sam9260ek.h
+++ b/include/configs/at91sam9260ek.h
@@ -34,10 +34,8 @@
 #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
 
 #ifdef CONFIG_AT91SAM9G20EK
-#define AT91_CPU_NAME		"AT91SAM9G20"
 #define CONFIG_AT91SAM9G20	1	/* It's an Atmel AT91SAM9G20 SoC*/
 #else
-#define AT91_CPU_NAME		"AT91SAM9260"
 #define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
 #endif
 
diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h
index 9621b7cb324..4f6b64011dc 100644
--- a/include/configs/at91sam9261ek.h
+++ b/include/configs/at91sam9261ek.h
@@ -28,7 +28,6 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9261"
 #define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h
index d03ecee3f61..c212d11d0d2 100644
--- a/include/configs/at91sam9263ek.h
+++ b/include/configs/at91sam9263ek.h
@@ -28,7 +28,6 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9263"
 #define AT91_MAIN_CLOCK		16367660	/* 16.367 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h
index 846d1658e07..c4668236c2b 100644
--- a/include/configs/at91sam9rlek.h
+++ b/include/configs/at91sam9rlek.h
@@ -28,7 +28,6 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9RL"
 #define AT91_MAIN_CLOCK		12000000	/* 12 MHz crystal */
 #define CONFIG_SYS_HZ		1000
 
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index 0db17b3545a..d60c417a113 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -29,8 +29,6 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
-#define AT91_CPU_NAME		"AT91SAM9263"
-
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
-- 
cgit v1.3.1


From b2403589b4d9996394bafc73eca3623f43ac2c31 Mon Sep 17 00:00:00 2001
From: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Date: Sun, 31 May 2009 14:53:18 +0200
Subject: at91: move cpu info print to cpu

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
---
 board/ronetix/pm9263/pm9263.c |  7 -------
 cpu/arm926ejs/at91/cpu.c      | 27 ++++++++++++++++++++++-----
 include/configs/pm9263.h      |  1 +
 3 files changed, 23 insertions(+), 12 deletions(-)

(limited to 'include')

diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index d24ef9a76ee..d2598a06807 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -382,15 +382,8 @@ int board_eth_init(bd_t *bis)
 int checkboard (void)
 {
 	char *ss;
-	char buf[32];
 
 	printf ("Board : Ronetix PM9263\n");
-	printf ("Crystal frequency: %8s MHz\n",
-					strmhz(buf, get_main_clk_rate()));
-	printf ("CPU clock        : %8s MHz\n",
-					strmhz(buf, get_cpu_clk_rate()));
-	printf ("Master clock     : %8s MHz\n",
-					strmhz(buf, get_mck_clk_rate()));
 
 	switch (gd->fb_base) {
 	case PHYS_PSRAM:
diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
index 2ae97fe497c..f2f7b625509 100644
--- a/cpu/arm926ejs/at91/cpu.c
+++ b/cpu/arm926ejs/at91/cpu.c
@@ -21,17 +21,34 @@
  * MA 02111-1307 USA
  */
 
-#include <config.h>
+#include <common.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/io.h>
 
+#ifndef AT91_MAIN_CLOCK
+#define AT91_MAIN_CLOCK 0
+#endif
+
 int arch_cpu_init(void)
 {
-#ifdef AT91_MAIN_CLOCK
 	return at91_clock_init(AT91_MAIN_CLOCK);
-#else
-	return at91_clock_init(0);
-#endif
 }
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	char buf[32];
+
+	printf("CPU: %s\n", AT91_CPU_NAME);
+	printf("Crystal frequency: %8s MHz\n",
+					strmhz(buf, get_main_clk_rate()));
+	printf("CPU clock        : %8s MHz\n",
+					strmhz(buf, get_cpu_clk_rate()));
+	printf("Master clock     : %8s MHz\n",
+					strmhz(buf, get_mck_clk_rate()));
+
+	return 0;
+}
+#endif
diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h
index d60c417a113..f0dbe81d140 100644
--- a/include/configs/pm9263.h
+++ b/include/configs/pm9263.h
@@ -29,6 +29,7 @@
 #define __CONFIG_H
 
 /* ARM asynchronous clock */
+#define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
-- 
cgit v1.3.1


From a24d96e40e1ca66dde6e6c158e7ecffafc5a2199 Mon Sep 17 00:00:00 2001
From: Prafulla Wadaskar <prafulla@marvell.com>
Date: Sun, 31 May 2009 14:53:20 +0200
Subject: arch_misc_init support for ARM architectures

This patch is required for Kirkwood support
may be used by other ARM architectures

Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
---
 include/asm-arm/u-boot-arm.h | 1 +
 lib_arm/board.c              | 4 ++++
 2 files changed, 5 insertions(+)

(limited to 'include')

diff --git a/include/asm-arm/u-boot-arm.h b/include/asm-arm/u-boot-arm.h
index 76f1ffa5a2c..6d2f8bccb50 100644
--- a/include/asm-arm/u-boot-arm.h
+++ b/include/asm-arm/u-boot-arm.h
@@ -42,6 +42,7 @@ int	cleanup_before_linux(void);
 
 /* cpu/.../arch/cpu.c */
 int	arch_cpu_init(void);
+int	arch_misc_init(void);
 
 /* board/.../... */
 int	board_init(void);
diff --git a/lib_arm/board.c b/lib_arm/board.c
index e081fbccb55..5c3bfecead3 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -399,6 +399,10 @@ void start_armboot (void)
 
 	console_init_r ();	/* fully init console as a device */
 
+#if defined(CONFIG_ARCH_MISC_INIT)
+	/* miscellaneous arch dependent initialisations */
+	arch_misc_init ();
+#endif
 #if defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
 	misc_init_r ();
-- 
cgit v1.3.1


From 59272620c24549b5bcd03c94ba12ec302c1476a2 Mon Sep 17 00:00:00 2001
From: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Date: Thu, 26 Mar 2009 15:26:01 -0400
Subject: Coldfire M5271: Activate u-boot system timer interrupt.

This patch assigns the u-boot system timer interrupt to
interrupt level 3, priority 6. Without this patch the interrupt
will be a level 0, priority 0, which disables it and cause
u-boot functions that relies on the timer (e.g. sleep command)
to never return.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
---
 include/asm-m68k/immap.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-m68k/immap.h b/include/asm-m68k/immap.h
index 93f730f6d4a..6a3ef03288d 100644
--- a/include/asm-m68k/immap.h
+++ b/include/asm-m68k/immap.h
@@ -149,7 +149,7 @@
 #define CONFIG_SYS_TMRINTR_NO		(INT0_LO_DTMR3)
 #define CONFIG_SYS_TMRINTR_MASK	(INTC_IPRL_INT22)
 #define CONFIG_SYS_TMRINTR_PEND	(CONFIG_SYS_TMRINTR_MASK)
-#define CONFIG_SYS_TMRINTR_PRI		(0)		/* Level must include inorder to work */
+#define CONFIG_SYS_TMRINTR_PRI		(0x1E) /* Interrupt level 3, priority 6 */
 #define CONFIG_SYS_TIMER_PRESCALER	(((gd->bus_clk / 1000000) - 1) << 8)
 #endif
 
-- 
cgit v1.3.1


From 0c9520efd651ce13451654a35307ec87d4a13a69 Mon Sep 17 00:00:00 2001
From: Tom Rix <Tom.Rix@windriver.com>
Date: Fri, 29 May 2009 18:57:32 -0500
Subject: ZOOM2 Define GPIO banks used.

Enable the function and interface clocks for banks 2,3,5 and 6.

Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
Acked-by: Dirk Behme <dirk.behme@googlemail.com>
---
 include/configs/omap3_zoom2.h | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'include')

diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h
index e2574192cf7..c2ad5bf199b 100644
--- a/include/configs/omap3_zoom2.h
+++ b/include/configs/omap3_zoom2.h
@@ -115,6 +115,14 @@
 /* Optional value */
 #define STATUS_LED_BOOT			STATUS_LED_BIT
 
+/* GPIO banks */
+#ifdef CONFIG_STATUS_LED
+#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */
+#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */
+#endif
+#define CONFIG_OMAP3_GPIO_3 /* board revision */
+#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */
+
 /* commands to include */
 #include <config_cmd_default.h>
 
-- 
cgit v1.3.1


From 0a57265533c412adf6024f4b4955141f4346b2b9 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 12 May 2009 14:29:39 +0200
Subject: mtd: Add MTD concat support to concatenate multiple MTD NOR devices

This patch adds concatenation support to the U-Boot MTD infrastructure.
By enabling CONFIG_MTD_CONCAT this MTD CFI wrapper will concatenate
all found NOR devices into one single MTD device. This can be used by
e.g by UBI to access a partition that spans over multiple NOR chips.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 drivers/mtd/Makefile       |   1 +
 drivers/mtd/cfi_mtd.c      |  79 ++++-
 drivers/mtd/mtdconcat.c    | 807 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mtd/compat.h |  12 +-
 include/linux/mtd/concat.h |  21 ++
 5 files changed, 915 insertions(+), 5 deletions(-)
 create mode 100644 drivers/mtd/mtdconcat.c
 create mode 100644 include/linux/mtd/concat.h

(limited to 'include')

diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index ed3f91e2a4e..19dc02b0c30 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	:= $(obj)libmtd.a
 
 COBJS-$(CONFIG_MTD_PARTITIONS) += mtdcore.o mtdpart.o
+COBJS-$(CONFIG_MTD_CONCAT) += mtdconcat.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
 COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
 COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index 4a76917ac39..300517e869d 100644
--- a/drivers/mtd/cfi_mtd.c
+++ b/drivers/mtd/cfi_mtd.c
@@ -25,14 +25,19 @@
 
 #include <common.h>
 #include <flash.h>
+#include <malloc.h>
 
 #include <asm/errno.h>
 #include <linux/mtd/mtd.h>
+#include <linux/mtd/concat.h>
 
 extern flash_info_t flash_info[];
 
 static struct mtd_info cfi_mtd_info[CONFIG_SYS_MAX_FLASH_BANKS];
 static char cfi_mtd_names[CONFIG_SYS_MAX_FLASH_BANKS][16];
+#ifdef CONFIG_MTD_CONCAT
+static char c_mtd_name[16];
+#endif
 
 static int cfi_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
@@ -145,16 +150,68 @@ static int cfi_mtd_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
 static int cfi_mtd_set_erasesize(struct mtd_info *mtd, flash_info_t *fi)
 {
 	int sect_size = 0;
+	int sect_size_old = 0;
 	int sect;
+	int regions = 0;
+	int numblocks = 0;
+	ulong offset = 0;
+	ulong base_addr = fi->start[0];
 
 	/*
-	 * Select the largest sector size as erasesize (e.g. for UBI)
+	 * First detect the number of eraseregions so that we can allocate
+	 * the array of eraseregions correctly
 	 */
 	for (sect = 0; sect < fi->sector_count; sect++) {
+		if (sect_size_old != flash_sector_size(fi, sect))
+			regions++;
+		sect_size_old = flash_sector_size(fi, sect);
+	}
+
+	mtd->eraseregions = malloc(sizeof(struct mtd_erase_region_info) * regions);
+
+	/*
+	 * Now detect the largest sector and fill the eraseregions
+	 */
+	sect_size_old = 0;
+	regions = 0;
+	for (sect = 0; sect < fi->sector_count; sect++) {
+		if ((sect_size_old != flash_sector_size(fi, sect)) &&
+		    (sect_size_old != 0)) {
+			mtd->eraseregions[regions].offset = offset - base_addr;
+			mtd->eraseregions[regions].erasesize = sect_size_old;
+			mtd->eraseregions[regions].numblocks = numblocks;
+
+			/* Now start counting the next eraseregions */
+			numblocks = 0;
+			regions++;
+		} else {
+			numblocks++;
+		}
+
+		if (sect_size_old != flash_sector_size(fi, sect))
+			offset = fi->start[sect];
+
+		/*
+		 * Select the largest sector size as erasesize (e.g. for UBI)
+		 */
 		if (flash_sector_size(fi, sect) > sect_size)
 			sect_size = flash_sector_size(fi, sect);
+
+		sect_size_old = flash_sector_size(fi, sect);
 	}
 
+	/*
+	 * Set the last region
+	 */
+	mtd->eraseregions[regions].offset = offset - base_addr;
+	mtd->eraseregions[regions].erasesize = sect_size_old;
+	mtd->eraseregions[regions].numblocks = numblocks + 1;
+
+	if (regions)
+		mtd->numeraseregions = regions + 1;
+	else
+		mtd->numeraseregions = 0;
+
 	mtd->erasesize = sect_size;
 
 	return 0;
@@ -165,6 +222,8 @@ int cfi_mtd_init(void)
 	struct mtd_info *mtd;
 	flash_info_t *fi;
 	int error, i;
+	int devices_found = 0;
+	struct mtd_info *mtd_list[CONFIG_SYS_MAX_FLASH_BANKS];
 
 	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		fi = &flash_info[i];
@@ -193,7 +252,25 @@ int cfi_mtd_init(void)
 
 		if (add_mtd_device(mtd))
 			return -ENOMEM;
+
+		mtd_list[devices_found++] = mtd;
+	}
+
+#ifdef CONFIG_MTD_CONCAT
+	if (devices_found > 1) {
+		/*
+		 * We detected multiple devices. Concatenate them together.
+		 */
+		sprintf(c_mtd_name, "nor%d", devices_found);
+		mtd = mtd_concat_create(mtd_list, devices_found, c_mtd_name);
+
+		if (mtd == NULL)
+			return -ENXIO;
+
+		if (add_mtd_device(mtd))
+			return -ENOMEM;
 	}
+#endif /* CONFIG_MTD_CONCAT */
 
 	return 0;
 }
diff --git a/drivers/mtd/mtdconcat.c b/drivers/mtd/mtdconcat.c
new file mode 100644
index 00000000000..fc2270127ae
--- /dev/null
+++ b/drivers/mtd/mtdconcat.c
@@ -0,0 +1,807 @@
+/*
+ * MTD device concatenation layer
+ *
+ * (C) 2002 Robert Kaiser <rkaiser@sysgo.de>
+ *
+ * NAND support by Christian Gan <cgan@iders.ca>
+ *
+ * This code is GPL
+ */
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/concat.h>
+#include <ubi_uboot.h>
+
+/*
+ * Our storage structure:
+ * Subdev points to an array of pointers to struct mtd_info objects
+ * which is allocated along with this structure
+ *
+ */
+struct mtd_concat {
+	struct mtd_info mtd;
+	int num_subdev;
+	struct mtd_info **subdev;
+};
+
+/*
+ * how to calculate the size required for the above structure,
+ * including the pointer array subdev points to:
+ */
+#define SIZEOF_STRUCT_MTD_CONCAT(num_subdev)	\
+	((sizeof(struct mtd_concat) + (num_subdev) * sizeof(struct mtd_info *)))
+
+/*
+ * Given a pointer to the MTD object in the mtd_concat structure,
+ * we can retrieve the pointer to that structure with this macro.
+ */
+#define CONCAT(x)  ((struct mtd_concat *)(x))
+
+/*
+ * MTD methods which look up the relevant subdevice, translate the
+ * effective address and pass through to the subdevice.
+ */
+
+static int
+concat_read(struct mtd_info *mtd, loff_t from, size_t len,
+	    size_t * retlen, u_char * buf)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int ret = 0, err;
+	int i;
+
+	*retlen = 0;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+		size_t size, retsize;
+
+		if (from >= subdev->size) {
+			/* Not destined for this subdev */
+			size = 0;
+			from -= subdev->size;
+			continue;
+		}
+		if (from + len > subdev->size)
+			/* First part goes into this subdev */
+			size = subdev->size - from;
+		else
+			/* Entire transaction goes into this subdev */
+			size = len;
+
+		err = subdev->read(subdev, from, size, &retsize, buf);
+
+		/* Save information about bitflips! */
+		if (unlikely(err)) {
+			if (err == -EBADMSG) {
+				mtd->ecc_stats.failed++;
+				ret = err;
+			} else if (err == -EUCLEAN) {
+				mtd->ecc_stats.corrected++;
+				/* Do not overwrite -EBADMSG !! */
+				if (!ret)
+					ret = err;
+			} else
+				return err;
+		}
+
+		*retlen += retsize;
+		len -= size;
+		if (len == 0)
+			return ret;
+
+		buf += size;
+		from = 0;
+	}
+	return -EINVAL;
+}
+
+static int
+concat_write(struct mtd_info *mtd, loff_t to, size_t len,
+	     size_t * retlen, const u_char * buf)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int err = -EINVAL;
+	int i;
+
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+
+	*retlen = 0;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+		size_t size, retsize;
+
+		if (to >= subdev->size) {
+			size = 0;
+			to -= subdev->size;
+			continue;
+		}
+		if (to + len > subdev->size)
+			size = subdev->size - to;
+		else
+			size = len;
+
+		if (!(subdev->flags & MTD_WRITEABLE))
+			err = -EROFS;
+		else
+			err = subdev->write(subdev, to, size, &retsize, buf);
+
+		if (err)
+			break;
+
+		*retlen += retsize;
+		len -= size;
+		if (len == 0)
+			break;
+
+		err = -EINVAL;
+		buf += size;
+		to = 0;
+	}
+	return err;
+}
+
+static int
+concat_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	struct mtd_oob_ops devops = *ops;
+	int i, err, ret = 0;
+
+	ops->retlen = ops->oobretlen = 0;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+
+		if (from >= subdev->size) {
+			from -= subdev->size;
+			continue;
+		}
+
+		/* partial read ? */
+		if (from + devops.len > subdev->size)
+			devops.len = subdev->size - from;
+
+		err = subdev->read_oob(subdev, from, &devops);
+		ops->retlen += devops.retlen;
+		ops->oobretlen += devops.oobretlen;
+
+		/* Save information about bitflips! */
+		if (unlikely(err)) {
+			if (err == -EBADMSG) {
+				mtd->ecc_stats.failed++;
+				ret = err;
+			} else if (err == -EUCLEAN) {
+				mtd->ecc_stats.corrected++;
+				/* Do not overwrite -EBADMSG !! */
+				if (!ret)
+					ret = err;
+			} else
+				return err;
+		}
+
+		if (devops.datbuf) {
+			devops.len = ops->len - ops->retlen;
+			if (!devops.len)
+				return ret;
+			devops.datbuf += devops.retlen;
+		}
+		if (devops.oobbuf) {
+			devops.ooblen = ops->ooblen - ops->oobretlen;
+			if (!devops.ooblen)
+				return ret;
+			devops.oobbuf += ops->oobretlen;
+		}
+
+		from = 0;
+	}
+	return -EINVAL;
+}
+
+static int
+concat_write_oob(struct mtd_info *mtd, loff_t to, struct mtd_oob_ops *ops)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	struct mtd_oob_ops devops = *ops;
+	int i, err;
+
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+
+	ops->retlen = 0;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+
+		if (to >= subdev->size) {
+			to -= subdev->size;
+			continue;
+		}
+
+		/* partial write ? */
+		if (to + devops.len > subdev->size)
+			devops.len = subdev->size - to;
+
+		err = subdev->write_oob(subdev, to, &devops);
+		ops->retlen += devops.retlen;
+		if (err)
+			return err;
+
+		if (devops.datbuf) {
+			devops.len = ops->len - ops->retlen;
+			if (!devops.len)
+				return 0;
+			devops.datbuf += devops.retlen;
+		}
+		if (devops.oobbuf) {
+			devops.ooblen = ops->ooblen - ops->oobretlen;
+			if (!devops.ooblen)
+				return 0;
+			devops.oobbuf += devops.oobretlen;
+		}
+		to = 0;
+	}
+	return -EINVAL;
+}
+
+static void concat_erase_callback(struct erase_info *instr)
+{
+	/* Nothing to do here in U-Boot */
+}
+
+static int concat_dev_erase(struct mtd_info *mtd, struct erase_info *erase)
+{
+	int err;
+	wait_queue_head_t waitq;
+	DECLARE_WAITQUEUE(wait, current);
+
+	/*
+	 * This code was stol^H^H^H^Hinspired by mtdchar.c
+	 */
+	init_waitqueue_head(&waitq);
+
+	erase->mtd = mtd;
+	erase->callback = concat_erase_callback;
+	erase->priv = (unsigned long) &waitq;
+
+	/*
+	 * FIXME: Allow INTERRUPTIBLE. Which means
+	 * not having the wait_queue head on the stack.
+	 */
+	err = mtd->erase(mtd, erase);
+	if (!err) {
+		set_current_state(TASK_UNINTERRUPTIBLE);
+		add_wait_queue(&waitq, &wait);
+		if (erase->state != MTD_ERASE_DONE
+		    && erase->state != MTD_ERASE_FAILED)
+			schedule();
+		remove_wait_queue(&waitq, &wait);
+		set_current_state(TASK_RUNNING);
+
+		err = (erase->state == MTD_ERASE_FAILED) ? -EIO : 0;
+	}
+	return err;
+}
+
+static int concat_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	struct mtd_info *subdev;
+	int i, err;
+	uint64_t length, offset = 0;
+	struct erase_info *erase;
+
+	if (!(mtd->flags & MTD_WRITEABLE))
+		return -EROFS;
+
+	if (instr->addr > concat->mtd.size)
+		return -EINVAL;
+
+	if (instr->len + instr->addr > concat->mtd.size)
+		return -EINVAL;
+
+	/*
+	 * Check for proper erase block alignment of the to-be-erased area.
+	 * It is easier to do this based on the super device's erase
+	 * region info rather than looking at each particular sub-device
+	 * in turn.
+	 */
+	if (!concat->mtd.numeraseregions) {
+		/* the easy case: device has uniform erase block size */
+		if (instr->addr & (concat->mtd.erasesize - 1))
+			return -EINVAL;
+		if (instr->len & (concat->mtd.erasesize - 1))
+			return -EINVAL;
+	} else {
+		/* device has variable erase size */
+		struct mtd_erase_region_info *erase_regions =
+		    concat->mtd.eraseregions;
+
+		/*
+		 * Find the erase region where the to-be-erased area begins:
+		 */
+		for (i = 0; i < concat->mtd.numeraseregions &&
+		     instr->addr >= erase_regions[i].offset; i++) ;
+		--i;
+
+		/*
+		 * Now erase_regions[i] is the region in which the
+		 * to-be-erased area begins. Verify that the starting
+		 * offset is aligned to this region's erase size:
+		 */
+		if (instr->addr & (erase_regions[i].erasesize - 1))
+			return -EINVAL;
+
+		/*
+		 * now find the erase region where the to-be-erased area ends:
+		 */
+		for (; i < concat->mtd.numeraseregions &&
+		     (instr->addr + instr->len) >= erase_regions[i].offset;
+		     ++i) ;
+		--i;
+		/*
+		 * check if the ending offset is aligned to this region's erase size
+		 */
+		if ((instr->addr + instr->len) & (erase_regions[i].erasesize -
+						  1))
+			return -EINVAL;
+	}
+
+	instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN;
+
+	/* make a local copy of instr to avoid modifying the caller's struct */
+	erase = kmalloc(sizeof (struct erase_info), GFP_KERNEL);
+
+	if (!erase)
+		return -ENOMEM;
+
+	*erase = *instr;
+	length = instr->len;
+
+	/*
+	 * find the subdevice where the to-be-erased area begins, adjust
+	 * starting offset to be relative to the subdevice start
+	 */
+	for (i = 0; i < concat->num_subdev; i++) {
+		subdev = concat->subdev[i];
+		if (subdev->size <= erase->addr) {
+			erase->addr -= subdev->size;
+			offset += subdev->size;
+		} else {
+			break;
+		}
+	}
+
+	/* must never happen since size limit has been verified above */
+	BUG_ON(i >= concat->num_subdev);
+
+	/* now do the erase: */
+	err = 0;
+	for (; length > 0; i++) {
+		/* loop for all subdevices affected by this request */
+		subdev = concat->subdev[i];	/* get current subdevice */
+
+		/* limit length to subdevice's size: */
+		if (erase->addr + length > subdev->size)
+			erase->len = subdev->size - erase->addr;
+		else
+			erase->len = length;
+
+		if (!(subdev->flags & MTD_WRITEABLE)) {
+			err = -EROFS;
+			break;
+		}
+		length -= erase->len;
+		if ((err = concat_dev_erase(subdev, erase))) {
+			/* sanity check: should never happen since
+			 * block alignment has been checked above */
+			BUG_ON(err == -EINVAL);
+			if (erase->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
+				instr->fail_addr = erase->fail_addr + offset;
+			break;
+		}
+		/*
+		 * erase->addr specifies the offset of the area to be
+		 * erased *within the current subdevice*. It can be
+		 * non-zero only the first time through this loop, i.e.
+		 * for the first subdevice where blocks need to be erased.
+		 * All the following erases must begin at the start of the
+		 * current subdevice, i.e. at offset zero.
+		 */
+		erase->addr = 0;
+		offset += subdev->size;
+	}
+	instr->state = erase->state;
+	kfree(erase);
+	if (err)
+		return err;
+
+	if (instr->callback)
+		instr->callback(instr);
+	return 0;
+}
+
+static int concat_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int i, err = -EINVAL;
+
+	if ((len + ofs) > mtd->size)
+		return -EINVAL;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+		uint64_t size;
+
+		if (ofs >= subdev->size) {
+			size = 0;
+			ofs -= subdev->size;
+			continue;
+		}
+		if (ofs + len > subdev->size)
+			size = subdev->size - ofs;
+		else
+			size = len;
+
+		err = subdev->lock(subdev, ofs, size);
+
+		if (err)
+			break;
+
+		len -= size;
+		if (len == 0)
+			break;
+
+		err = -EINVAL;
+		ofs = 0;
+	}
+
+	return err;
+}
+
+static int concat_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int i, err = 0;
+
+	if ((len + ofs) > mtd->size)
+		return -EINVAL;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+		uint64_t size;
+
+		if (ofs >= subdev->size) {
+			size = 0;
+			ofs -= subdev->size;
+			continue;
+		}
+		if (ofs + len > subdev->size)
+			size = subdev->size - ofs;
+		else
+			size = len;
+
+		err = subdev->unlock(subdev, ofs, size);
+
+		if (err)
+			break;
+
+		len -= size;
+		if (len == 0)
+			break;
+
+		err = -EINVAL;
+		ofs = 0;
+	}
+
+	return err;
+}
+
+static void concat_sync(struct mtd_info *mtd)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int i;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+		subdev->sync(subdev);
+	}
+}
+
+static int concat_block_isbad(struct mtd_info *mtd, loff_t ofs)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int i, res = 0;
+
+	if (!concat->subdev[0]->block_isbad)
+		return res;
+
+	if (ofs > mtd->size)
+		return -EINVAL;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+
+		if (ofs >= subdev->size) {
+			ofs -= subdev->size;
+			continue;
+		}
+
+		res = subdev->block_isbad(subdev, ofs);
+		break;
+	}
+
+	return res;
+}
+
+static int concat_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+	struct mtd_concat *concat = CONCAT(mtd);
+	int i, err = -EINVAL;
+
+	if (!concat->subdev[0]->block_markbad)
+		return 0;
+
+	if (ofs > mtd->size)
+		return -EINVAL;
+
+	for (i = 0; i < concat->num_subdev; i++) {
+		struct mtd_info *subdev = concat->subdev[i];
+
+		if (ofs >= subdev->size) {
+			ofs -= subdev->size;
+			continue;
+		}
+
+		err = subdev->block_markbad(subdev, ofs);
+		if (!err)
+			mtd->ecc_stats.badblocks++;
+		break;
+	}
+
+	return err;
+}
+
+/*
+ * This function constructs a virtual MTD device by concatenating
+ * num_devs MTD devices. A pointer to the new device object is
+ * stored to *new_dev upon success. This function does _not_
+ * register any devices: this is the caller's responsibility.
+ */
+struct mtd_info *mtd_concat_create(struct mtd_info *subdev[],	/* subdevices to concatenate */
+				   int num_devs,	/* number of subdevices      */
+				   const char *name)
+{				/* name for the new device   */
+	int i;
+	size_t size;
+	struct mtd_concat *concat;
+	uint32_t max_erasesize, curr_erasesize;
+	int num_erase_region;
+
+	debug("Concatenating MTD devices:\n");
+	for (i = 0; i < num_devs; i++)
+		debug("(%d): \"%s\"\n", i, subdev[i]->name);
+	debug("into device \"%s\"\n", name);
+
+	/* allocate the device structure */
+	size = SIZEOF_STRUCT_MTD_CONCAT(num_devs);
+	concat = kzalloc(size, GFP_KERNEL);
+	if (!concat) {
+		printk
+		    ("memory allocation error while creating concatenated device \"%s\"\n",
+		     name);
+		return NULL;
+	}
+	concat->subdev = (struct mtd_info **) (concat + 1);
+
+	/*
+	 * Set up the new "super" device's MTD object structure, check for
+	 * incompatibilites between the subdevices.
+	 */
+	concat->mtd.type = subdev[0]->type;
+	concat->mtd.flags = subdev[0]->flags;
+	concat->mtd.size = subdev[0]->size;
+	concat->mtd.erasesize = subdev[0]->erasesize;
+	concat->mtd.writesize = subdev[0]->writesize;
+	concat->mtd.subpage_sft = subdev[0]->subpage_sft;
+	concat->mtd.oobsize = subdev[0]->oobsize;
+	concat->mtd.oobavail = subdev[0]->oobavail;
+	if (subdev[0]->read_oob)
+		concat->mtd.read_oob = concat_read_oob;
+	if (subdev[0]->write_oob)
+		concat->mtd.write_oob = concat_write_oob;
+	if (subdev[0]->block_isbad)
+		concat->mtd.block_isbad = concat_block_isbad;
+	if (subdev[0]->block_markbad)
+		concat->mtd.block_markbad = concat_block_markbad;
+
+	concat->mtd.ecc_stats.badblocks = subdev[0]->ecc_stats.badblocks;
+
+	concat->subdev[0] = subdev[0];
+
+	for (i = 1; i < num_devs; i++) {
+		if (concat->mtd.type != subdev[i]->type) {
+			kfree(concat);
+			printk("Incompatible device type on \"%s\"\n",
+			       subdev[i]->name);
+			return NULL;
+		}
+		if (concat->mtd.flags != subdev[i]->flags) {
+			/*
+			 * Expect all flags except MTD_WRITEABLE to be
+			 * equal on all subdevices.
+			 */
+			if ((concat->mtd.flags ^ subdev[i]->
+			     flags) & ~MTD_WRITEABLE) {
+				kfree(concat);
+				printk("Incompatible device flags on \"%s\"\n",
+				       subdev[i]->name);
+				return NULL;
+			} else
+				/* if writeable attribute differs,
+				   make super device writeable */
+				concat->mtd.flags |=
+				    subdev[i]->flags & MTD_WRITEABLE;
+		}
+
+		concat->mtd.size += subdev[i]->size;
+		concat->mtd.ecc_stats.badblocks +=
+			subdev[i]->ecc_stats.badblocks;
+		if (concat->mtd.writesize   !=  subdev[i]->writesize ||
+		    concat->mtd.subpage_sft != subdev[i]->subpage_sft ||
+		    concat->mtd.oobsize    !=  subdev[i]->oobsize ||
+		    !concat->mtd.read_oob  != !subdev[i]->read_oob ||
+		    !concat->mtd.write_oob != !subdev[i]->write_oob) {
+			kfree(concat);
+			printk("Incompatible OOB or ECC data on \"%s\"\n",
+			       subdev[i]->name);
+			return NULL;
+		}
+		concat->subdev[i] = subdev[i];
+
+	}
+
+	concat->mtd.ecclayout = subdev[0]->ecclayout;
+
+	concat->num_subdev = num_devs;
+	concat->mtd.name = name;
+
+	concat->mtd.erase = concat_erase;
+	concat->mtd.read = concat_read;
+	concat->mtd.write = concat_write;
+	concat->mtd.sync = concat_sync;
+	concat->mtd.lock = concat_lock;
+	concat->mtd.unlock = concat_unlock;
+
+	/*
+	 * Combine the erase block size info of the subdevices:
+	 *
+	 * first, walk the map of the new device and see how
+	 * many changes in erase size we have
+	 */
+	max_erasesize = curr_erasesize = subdev[0]->erasesize;
+	num_erase_region = 1;
+	for (i = 0; i < num_devs; i++) {
+		if (subdev[i]->numeraseregions == 0) {
+			/* current subdevice has uniform erase size */
+			if (subdev[i]->erasesize != curr_erasesize) {
+				/* if it differs from the last subdevice's erase size, count it */
+				++num_erase_region;
+				curr_erasesize = subdev[i]->erasesize;
+				if (curr_erasesize > max_erasesize)
+					max_erasesize = curr_erasesize;
+			}
+		} else {
+			/* current subdevice has variable erase size */
+			int j;
+			for (j = 0; j < subdev[i]->numeraseregions; j++) {
+
+				/* walk the list of erase regions, count any changes */
+				if (subdev[i]->eraseregions[j].erasesize !=
+				    curr_erasesize) {
+					++num_erase_region;
+					curr_erasesize =
+					    subdev[i]->eraseregions[j].
+					    erasesize;
+					if (curr_erasesize > max_erasesize)
+						max_erasesize = curr_erasesize;
+				}
+			}
+		}
+	}
+
+	if (num_erase_region == 1) {
+		/*
+		 * All subdevices have the same uniform erase size.
+		 * This is easy:
+		 */
+		concat->mtd.erasesize = curr_erasesize;
+		concat->mtd.numeraseregions = 0;
+	} else {
+		uint64_t tmp64;
+
+		/*
+		 * erase block size varies across the subdevices: allocate
+		 * space to store the data describing the variable erase regions
+		 */
+		struct mtd_erase_region_info *erase_region_p;
+		uint64_t begin, position;
+
+		concat->mtd.erasesize = max_erasesize;
+		concat->mtd.numeraseregions = num_erase_region;
+		concat->mtd.eraseregions = erase_region_p =
+		    kmalloc(num_erase_region *
+			    sizeof (struct mtd_erase_region_info), GFP_KERNEL);
+		if (!erase_region_p) {
+			kfree(concat);
+			printk
+			    ("memory allocation error while creating erase region list"
+			     " for device \"%s\"\n", name);
+			return NULL;
+		}
+
+		/*
+		 * walk the map of the new device once more and fill in
+		 * in erase region info:
+		 */
+		curr_erasesize = subdev[0]->erasesize;
+		begin = position = 0;
+		for (i = 0; i < num_devs; i++) {
+			if (subdev[i]->numeraseregions == 0) {
+				/* current subdevice has uniform erase size */
+				if (subdev[i]->erasesize != curr_erasesize) {
+					/*
+					 *  fill in an mtd_erase_region_info structure for the area
+					 *  we have walked so far:
+					 */
+					erase_region_p->offset = begin;
+					erase_region_p->erasesize =
+					    curr_erasesize;
+					tmp64 = position - begin;
+					do_div(tmp64, curr_erasesize);
+					erase_region_p->numblocks = tmp64;
+					begin = position;
+
+					curr_erasesize = subdev[i]->erasesize;
+					++erase_region_p;
+				}
+				position += subdev[i]->size;
+			} else {
+				/* current subdevice has variable erase size */
+				int j;
+				for (j = 0; j < subdev[i]->numeraseregions; j++) {
+					/* walk the list of erase regions, count any changes */
+					if (subdev[i]->eraseregions[j].
+					    erasesize != curr_erasesize) {
+						erase_region_p->offset = begin;
+						erase_region_p->erasesize =
+						    curr_erasesize;
+						tmp64 = position - begin;
+						do_div(tmp64, curr_erasesize);
+						erase_region_p->numblocks = tmp64;
+						begin = position;
+
+						curr_erasesize =
+						    subdev[i]->eraseregions[j].
+						    erasesize;
+						++erase_region_p;
+					}
+					position +=
+					    subdev[i]->eraseregions[j].
+					    numblocks * (uint64_t)curr_erasesize;
+				}
+			}
+		}
+		/* Now write the final entry */
+		erase_region_p->offset = begin;
+		erase_region_p->erasesize = curr_erasesize;
+		tmp64 = position - begin;
+		do_div(tmp64, curr_erasesize);
+		erase_region_p->numblocks = tmp64;
+	}
+
+	return &concat->mtd;
+}
diff --git a/include/linux/mtd/compat.h b/include/linux/mtd/compat.h
index 9036b74f86e..f0c8464db5a 100644
--- a/include/linux/mtd/compat.h
+++ b/include/linux/mtd/compat.h
@@ -19,11 +19,15 @@
 
 #define kmalloc(size, flags)	malloc(size)
 #define kzalloc(size, flags)	calloc(size, 1)
-#define vmalloc(size)			malloc(size)
-#define kfree(ptr)				free(ptr)
-#define vfree(ptr)				free(ptr)
+#define vmalloc(size)		malloc(size)
+#define kfree(ptr)		free(ptr)
+#define vfree(ptr)		free(ptr)
 
-#define KERNEL_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
+#define DECLARE_WAITQUEUE(...)	do { } while (0)
+#define add_wait_queue(...)	do { } while (0)
+#define remove_wait_queue(...)	do { } while (0)
+
+#define KERNEL_VERSION(a,b,c)	(((a) << 16) + ((b) << 8) + (c))
 
 /*
  * ..and if you can't take the strict
diff --git a/include/linux/mtd/concat.h b/include/linux/mtd/concat.h
new file mode 100644
index 00000000000..e80c674daeb
--- /dev/null
+++ b/include/linux/mtd/concat.h
@@ -0,0 +1,21 @@
+/*
+ * MTD device concatenation layer definitions
+ *
+ * (C) 2002 Robert Kaiser <rkaiser@sysgo.de>
+ *
+ * This code is GPL
+ */
+
+#ifndef MTD_CONCAT_H
+#define MTD_CONCAT_H
+
+
+struct mtd_info *mtd_concat_create(
+    struct mtd_info *subdev[],  /* subdevices to concatenate */
+    int num_devs,               /* number of subdevices      */
+    const char *name);          /* name for the new device   */
+
+void mtd_concat_destroy(struct mtd_info *mtd);
+
+#endif
+
-- 
cgit v1.3.1


From 8d2effea23e938631126a7888008a0637e13b389 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Mon, 11 May 2009 16:03:55 +0200
Subject: mtd: Update MTD infrastructure to support 64bit device size

This patch brings the U-Boot MTD infrastructure in sync with the current
Linux MTD version (2.6.30-rc3). Biggest change is the 64bit device size
support and a resync of the mtdpart.c file which has seen multiple fixes
meanwhile.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Kyungmin Park <kmpark@infradead.org>
---
 common/cmd_onenand.c         |   6 +-
 common/env_onenand.c         |   2 +-
 drivers/mtd/cfi_mtd.c        |   4 +-
 drivers/mtd/mtdpart.c        | 488 +++++++++++++++++++------------------------
 drivers/mtd/nand/nand_util.c |  11 +-
 include/linux/mtd/mtd.h      |  29 ++-
 6 files changed, 256 insertions(+), 284 deletions(-)

(limited to 'include')

diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c
index 5832ff8d36b..e8f06d7f433 100644
--- a/common/cmd_onenand.c
+++ b/common/cmd_onenand.c
@@ -19,6 +19,10 @@
 
 #include <asm/io.h>
 
+#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
+#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
+#endif
+
 static struct mtd_info *mtd;
 
 static loff_t next_ofs;
@@ -53,7 +57,7 @@ static int arg_off_size(int argc, char *argv[], ulong *off, size_t *size)
 	}
 
 	if ((*off + *size) > mtd->size) {
-		printf("total chip size (0x%x) exceeded!\n", mtd->size);
+		printf("total chip size (0x%llx) exceeded!\n", mtd->size);
 		return -1;
 	}
 
diff --git a/common/env_onenand.c b/common/env_onenand.c
index dbccc791258..ed77051724d 100644
--- a/common/env_onenand.c
+++ b/common/env_onenand.c
@@ -109,7 +109,7 @@ int saveenv(void)
 
 	if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.writesize, &retlen,
 	     (u_char *) env_ptr)) {
-		printf("OneNAND: write failed at 0x%08x\n", instr.addr);
+		printf("OneNAND: write failed at 0x%llx\n", instr.addr);
 		return 2;
 	}
 
diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c
index 300517e869d..c7e357b7f2a 100644
--- a/drivers/mtd/cfi_mtd.c
+++ b/drivers/mtd/cfi_mtd.c
@@ -123,7 +123,7 @@ static void cfi_mtd_sync(struct mtd_info *mtd)
 	 */
 }
 
-static int cfi_mtd_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
+static int cfi_mtd_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	flash_info_t *fi = mtd->priv;
 
@@ -135,7 +135,7 @@ static int cfi_mtd_lock(struct mtd_info *mtd, loff_t ofs, size_t len)
 	return 0;
 }
 
-static int cfi_mtd_unlock(struct mtd_info *mtd, loff_t ofs, size_t len)
+static int cfi_mtd_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	flash_info_t *fi = mtd->priv;
 
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index f010f5e3ac5..e2e43eaec4a 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -26,7 +26,7 @@ struct list_head mtd_partitions;
 struct mtd_part {
 	struct mtd_info mtd;
 	struct mtd_info *master;
-	u_int32_t offset;
+	uint64_t offset;
 	int index;
 	struct list_head list;
 	int registered;
@@ -44,50 +44,32 @@ struct mtd_part {
  * to the _real_ device.
  */
 
-static int part_read (struct mtd_info *mtd, loff_t from, size_t len,
-			size_t *retlen, u_char *buf)
+static int part_read(struct mtd_info *mtd, loff_t from, size_t len,
+		size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
+	struct mtd_ecc_stats stats;
 	int res;
 
+	stats = part->master->ecc_stats;
+
 	if (from >= mtd->size)
 		len = 0;
 	else if (from + len > mtd->size)
 		len = mtd->size - from;
-	res = part->master->read (part->master, from + part->offset,
+	res = part->master->read(part->master, from + part->offset,
 				   len, retlen, buf);
 	if (unlikely(res)) {
 		if (res == -EUCLEAN)
-			mtd->ecc_stats.corrected++;
+			mtd->ecc_stats.corrected += part->master->ecc_stats.corrected - stats.corrected;
 		if (res == -EBADMSG)
-			mtd->ecc_stats.failed++;
+			mtd->ecc_stats.failed += part->master->ecc_stats.failed - stats.failed;
 	}
 	return res;
 }
 
-#ifdef MTD_LINUX
-static int part_point (struct mtd_info *mtd, loff_t from, size_t len,
-			size_t *retlen, void **virt, resource_size_t *phys)
-{
-	struct mtd_part *part = PART(mtd);
-	if (from >= mtd->size)
-		len = 0;
-	else if (from + len > mtd->size)
-		len = mtd->size - from;
-	return part->master->point (part->master, from + part->offset,
-				    len, retlen, virt, phys);
-}
-
-static void part_unpoint(struct mtd_info *mtd, loff_t from, size_t len)
-{
-	struct mtd_part *part = PART(mtd);
-
-	part->master->unpoint(part->master, from + part->offset, len);
-}
-#endif
-
 static int part_read_oob(struct mtd_info *mtd, loff_t from,
-			 struct mtd_oob_ops *ops)
+		struct mtd_oob_ops *ops)
 {
 	struct mtd_part *part = PART(mtd);
 	int res;
@@ -107,38 +89,38 @@ static int part_read_oob(struct mtd_info *mtd, loff_t from,
 	return res;
 }
 
-static int part_read_user_prot_reg (struct mtd_info *mtd, loff_t from, size_t len,
-			size_t *retlen, u_char *buf)
+static int part_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
+		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->read_user_prot_reg (part->master, from,
+	return part->master->read_user_prot_reg(part->master, from,
 					len, retlen, buf);
 }
 
-static int part_get_user_prot_info (struct mtd_info *mtd,
-				    struct otp_info *buf, size_t len)
+static int part_get_user_prot_info(struct mtd_info *mtd,
+		struct otp_info *buf, size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->get_user_prot_info (part->master, buf, len);
+	return part->master->get_user_prot_info(part->master, buf, len);
 }
 
-static int part_read_fact_prot_reg (struct mtd_info *mtd, loff_t from, size_t len,
-			size_t *retlen, u_char *buf)
+static int part_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
+		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->read_fact_prot_reg (part->master, from,
+	return part->master->read_fact_prot_reg(part->master, from,
 					len, retlen, buf);
 }
 
-static int part_get_fact_prot_info (struct mtd_info *mtd,
-				    struct otp_info *buf, size_t len)
+static int part_get_fact_prot_info(struct mtd_info *mtd, struct otp_info *buf,
+		size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->get_fact_prot_info (part->master, buf, len);
+	return part->master->get_fact_prot_info(part->master, buf, len);
 }
 
-static int part_write (struct mtd_info *mtd, loff_t to, size_t len,
-			size_t *retlen, const u_char *buf)
+static int part_write(struct mtd_info *mtd, loff_t to, size_t len,
+		size_t *retlen, const u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
 	if (!(mtd->flags & MTD_WRITEABLE))
@@ -147,13 +129,12 @@ static int part_write (struct mtd_info *mtd, loff_t to, size_t len,
 		len = 0;
 	else if (to + len > mtd->size)
 		len = mtd->size - to;
-	return part->master->write (part->master, to + part->offset,
+	return part->master->write(part->master, to + part->offset,
 				    len, retlen, buf);
 }
 
-#ifdef MTD_LINUX
-static int part_panic_write (struct mtd_info *mtd, loff_t to, size_t len,
-			size_t *retlen, const u_char *buf)
+static int part_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
+		size_t *retlen, const u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
 	if (!(mtd->flags & MTD_WRITEABLE))
@@ -162,13 +143,12 @@ static int part_panic_write (struct mtd_info *mtd, loff_t to, size_t len,
 		len = 0;
 	else if (to + len > mtd->size)
 		len = mtd->size - to;
-	return part->master->panic_write (part->master, to + part->offset,
+	return part->master->panic_write(part->master, to + part->offset,
 				    len, retlen, buf);
 }
-#endif
 
 static int part_write_oob(struct mtd_info *mtd, loff_t to,
-			 struct mtd_oob_ops *ops)
+		struct mtd_oob_ops *ops)
 {
 	struct mtd_part *part = PART(mtd);
 
@@ -182,33 +162,22 @@ static int part_write_oob(struct mtd_info *mtd, loff_t to,
 	return part->master->write_oob(part->master, to + part->offset, ops);
 }
 
-static int part_write_user_prot_reg (struct mtd_info *mtd, loff_t from, size_t len,
-			size_t *retlen, u_char *buf)
+static int part_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
+		size_t len, size_t *retlen, u_char *buf)
 {
 	struct mtd_part *part = PART(mtd);
-	return part->master->write_user_prot_reg (part->master, from,
+	return part->master->write_user_prot_reg(part->master, from,
 					len, retlen, buf);
 }
 
-static int part_lock_user_prot_reg (struct mtd_info *mtd, loff_t from, size_t len)
-{
-	struct mtd_part *part = PART(mtd);
-	return part->master->lock_user_prot_reg (part->master, from, len);
-}
-
-#ifdef MTD_LINUX
-static int part_writev (struct mtd_info *mtd,  const struct kvec *vecs,
-			 unsigned long count, loff_t to, size_t *retlen)
+static int part_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
+		size_t len)
 {
 	struct mtd_part *part = PART(mtd);
-	if (!(mtd->flags & MTD_WRITEABLE))
-		return -EROFS;
-	return part->master->writev (part->master, vecs, count,
-					to + part->offset, retlen);
+	return part->master->lock_user_prot_reg(part->master, from, len);
 }
-#endif
 
-static int part_erase (struct mtd_info *mtd, struct erase_info *instr)
+static int part_erase(struct mtd_info *mtd, struct erase_info *instr)
 {
 	struct mtd_part *part = PART(mtd);
 	int ret;
@@ -219,7 +188,7 @@ static int part_erase (struct mtd_info *mtd, struct erase_info *instr)
 	instr->addr += part->offset;
 	ret = part->master->erase(part->master, instr);
 	if (ret) {
-		if (instr->fail_addr != 0xffffffff)
+		if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
 			instr->fail_addr -= part->offset;
 		instr->addr -= part->offset;
 	}
@@ -231,19 +200,15 @@ void mtd_erase_callback(struct erase_info *instr)
 	if (instr->mtd->erase == part_erase) {
 		struct mtd_part *part = PART(instr->mtd);
 
-		if (instr->fail_addr != 0xffffffff)
+		if (instr->fail_addr != MTD_FAIL_ADDR_UNKNOWN)
 			instr->fail_addr -= part->offset;
 		instr->addr -= part->offset;
 	}
 	if (instr->callback)
 		instr->callback(instr);
 }
-#ifdef MTD_LINUX
-EXPORT_SYMBOL_GPL(mtd_erase_callback);
-#endif
 
-#ifdef MTD_LINUX
-static int part_lock (struct mtd_info *mtd, loff_t ofs, size_t len)
+static int part_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	struct mtd_part *part = PART(mtd);
 	if ((len + ofs) > mtd->size)
@@ -251,14 +216,13 @@ static int part_lock (struct mtd_info *mtd, loff_t ofs, size_t len)
 	return part->master->lock(part->master, ofs + part->offset, len);
 }
 
-static int part_unlock (struct mtd_info *mtd, loff_t ofs, size_t len)
+static int part_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
 {
 	struct mtd_part *part = PART(mtd);
 	if ((len + ofs) > mtd->size)
 		return -EINVAL;
 	return part->master->unlock(part->master, ofs + part->offset, len);
 }
-#endif
 
 static void part_sync(struct mtd_info *mtd)
 {
@@ -266,7 +230,6 @@ static void part_sync(struct mtd_info *mtd)
 	part->master->sync(part->master);
 }
 
-#ifdef MTD_LINUX
 static int part_suspend(struct mtd_info *mtd)
 {
 	struct mtd_part *part = PART(mtd);
@@ -278,9 +241,8 @@ static void part_resume(struct mtd_info *mtd)
 	struct mtd_part *part = PART(mtd);
 	part->master->resume(part->master);
 }
-#endif
 
-static int part_block_isbad (struct mtd_info *mtd, loff_t ofs)
+static int part_block_isbad(struct mtd_info *mtd, loff_t ofs)
 {
 	struct mtd_part *part = PART(mtd);
 	if (ofs >= mtd->size)
@@ -289,7 +251,7 @@ static int part_block_isbad (struct mtd_info *mtd, loff_t ofs)
 	return part->master->block_isbad(part->master, ofs);
 }
 
-static int part_block_markbad (struct mtd_info *mtd, loff_t ofs)
+static int part_block_markbad(struct mtd_info *mtd, loff_t ofs)
 {
 	struct mtd_part *part = PART(mtd);
 	int res;
@@ -300,10 +262,8 @@ static int part_block_markbad (struct mtd_info *mtd, loff_t ofs)
 		return -EINVAL;
 	ofs += part->offset;
 	res = part->master->block_markbad(part->master, ofs);
-#ifdef MTD_LINUX
 	if (!res)
 		mtd->ecc_stats.badblocks++;
-#endif
 	return res;
 }
 
@@ -314,31 +274,193 @@ static int part_block_markbad (struct mtd_info *mtd, loff_t ofs)
 
 int del_mtd_partitions(struct mtd_info *master)
 {
-	struct list_head *node;
-	struct mtd_part *slave;
+	struct mtd_part *slave, *next;
 
-	for (node = mtd_partitions.next;
-	     node != &mtd_partitions;
-	     node = node->next) {
-		slave = list_entry(node, struct mtd_part, list);
+	list_for_each_entry_safe(slave, next, &mtd_partitions, list)
 		if (slave->master == master) {
-			struct list_head *prev = node->prev;
-			__list_del(prev, node->next);
-			if(slave->registered)
+			list_del(&slave->list);
+			if (slave->registered)
 				del_mtd_device(&slave->mtd);
 			kfree(slave);
-			node = prev;
 		}
-	}
 
 	return 0;
 }
 
+static struct mtd_part *add_one_partition(struct mtd_info *master,
+		const struct mtd_partition *part, int partno,
+		uint64_t cur_offset)
+{
+	struct mtd_part *slave;
+
+	/* allocate the partition structure */
+	slave = kzalloc(sizeof(*slave), GFP_KERNEL);
+	if (!slave) {
+		printk(KERN_ERR"memory allocation error while creating partitions for \"%s\"\n",
+			master->name);
+		del_mtd_partitions(master);
+		return NULL;
+	}
+	list_add(&slave->list, &mtd_partitions);
+
+	/* set up the MTD object for this partition */
+	slave->mtd.type = master->type;
+	slave->mtd.flags = master->flags & ~part->mask_flags;
+	slave->mtd.size = part->size;
+	slave->mtd.writesize = master->writesize;
+	slave->mtd.oobsize = master->oobsize;
+	slave->mtd.oobavail = master->oobavail;
+	slave->mtd.subpage_sft = master->subpage_sft;
+
+	slave->mtd.name = part->name;
+	slave->mtd.owner = master->owner;
+
+	slave->mtd.read = part_read;
+	slave->mtd.write = part_write;
+
+	if (master->panic_write)
+		slave->mtd.panic_write = part_panic_write;
+
+	if (master->read_oob)
+		slave->mtd.read_oob = part_read_oob;
+	if (master->write_oob)
+		slave->mtd.write_oob = part_write_oob;
+	if (master->read_user_prot_reg)
+		slave->mtd.read_user_prot_reg = part_read_user_prot_reg;
+	if (master->read_fact_prot_reg)
+		slave->mtd.read_fact_prot_reg = part_read_fact_prot_reg;
+	if (master->write_user_prot_reg)
+		slave->mtd.write_user_prot_reg = part_write_user_prot_reg;
+	if (master->lock_user_prot_reg)
+		slave->mtd.lock_user_prot_reg = part_lock_user_prot_reg;
+	if (master->get_user_prot_info)
+		slave->mtd.get_user_prot_info = part_get_user_prot_info;
+	if (master->get_fact_prot_info)
+		slave->mtd.get_fact_prot_info = part_get_fact_prot_info;
+	if (master->sync)
+		slave->mtd.sync = part_sync;
+	if (!partno && master->suspend && master->resume) {
+			slave->mtd.suspend = part_suspend;
+			slave->mtd.resume = part_resume;
+	}
+	if (master->lock)
+		slave->mtd.lock = part_lock;
+	if (master->unlock)
+		slave->mtd.unlock = part_unlock;
+	if (master->block_isbad)
+		slave->mtd.block_isbad = part_block_isbad;
+	if (master->block_markbad)
+		slave->mtd.block_markbad = part_block_markbad;
+	slave->mtd.erase = part_erase;
+	slave->master = master;
+	slave->offset = part->offset;
+	slave->index = partno;
+
+	if (slave->offset == MTDPART_OFS_APPEND)
+		slave->offset = cur_offset;
+	if (slave->offset == MTDPART_OFS_NXTBLK) {
+		slave->offset = cur_offset;
+		if (mtd_mod_by_eb(cur_offset, master) != 0) {
+			/* Round up to next erasesize */
+			slave->offset = (mtd_div_by_eb(cur_offset, master) + 1) * master->erasesize;
+			printk(KERN_NOTICE "Moving partition %d: "
+			       "0x%012llx -> 0x%012llx\n", partno,
+			       (unsigned long long)cur_offset, (unsigned long long)slave->offset);
+		}
+	}
+	if (slave->mtd.size == MTDPART_SIZ_FULL)
+		slave->mtd.size = master->size - slave->offset;
+
+	printk(KERN_NOTICE "0x%012llx-0x%012llx : \"%s\"\n", (unsigned long long)slave->offset,
+		(unsigned long long)(slave->offset + slave->mtd.size), slave->mtd.name);
+
+	/* let's do some sanity checks */
+	if (slave->offset >= master->size) {
+		/* let's register it anyway to preserve ordering */
+		slave->offset = 0;
+		slave->mtd.size = 0;
+		printk(KERN_ERR"mtd: partition \"%s\" is out of reach -- disabled\n",
+			part->name);
+		goto out_register;
+	}
+	if (slave->offset + slave->mtd.size > master->size) {
+		slave->mtd.size = master->size - slave->offset;
+		printk(KERN_WARNING"mtd: partition \"%s\" extends beyond the end of device \"%s\" -- size truncated to %#llx\n",
+			part->name, master->name, (unsigned long long)slave->mtd.size);
+	}
+	if (master->numeraseregions > 1) {
+		/* Deal with variable erase size stuff */
+		int i, max = master->numeraseregions;
+		u64 end = slave->offset + slave->mtd.size;
+		struct mtd_erase_region_info *regions = master->eraseregions;
+
+		/* Find the first erase regions which is part of this
+		 * partition. */
+		for (i = 0; i < max && regions[i].offset <= slave->offset; i++)
+			;
+		/* The loop searched for the region _behind_ the first one */
+		i--;
+
+		/* Pick biggest erasesize */
+		for (; i < max && regions[i].offset < end; i++) {
+			if (slave->mtd.erasesize < regions[i].erasesize) {
+				slave->mtd.erasesize = regions[i].erasesize;
+			}
+		}
+		BUG_ON(slave->mtd.erasesize == 0);
+	} else {
+		/* Single erase size */
+		slave->mtd.erasesize = master->erasesize;
+	}
+
+	if ((slave->mtd.flags & MTD_WRITEABLE) &&
+	    mtd_mod_by_eb(slave->offset, &slave->mtd)) {
+		/* Doesn't start on a boundary of major erase size */
+		/* FIXME: Let it be writable if it is on a boundary of
+		 * _minor_ erase size though */
+		slave->mtd.flags &= ~MTD_WRITEABLE;
+		printk(KERN_WARNING"mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n",
+			part->name);
+	}
+	if ((slave->mtd.flags & MTD_WRITEABLE) &&
+	    mtd_mod_by_eb(slave->mtd.size, &slave->mtd)) {
+		slave->mtd.flags &= ~MTD_WRITEABLE;
+		printk(KERN_WARNING"mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n",
+			part->name);
+	}
+
+	slave->mtd.ecclayout = master->ecclayout;
+	if (master->block_isbad) {
+		uint64_t offs = 0;
+
+		while (offs < slave->mtd.size) {
+			if (master->block_isbad(master,
+						offs + slave->offset))
+				slave->mtd.ecc_stats.badblocks++;
+			offs += slave->mtd.erasesize;
+		}
+	}
+
+out_register:
+	if (part->mtdp) {
+		/* store the object pointer (caller may or may not register it*/
+		*part->mtdp = &slave->mtd;
+		slave->registered = 0;
+	} else {
+		/* register our partition */
+		add_mtd_device(&slave->mtd);
+		slave->registered = 1;
+	}
+	return slave;
+}
+
 /*
  * This function, given a master MTD object and a partition table, creates
  * and registers slave MTD objects which are bound to the master according to
  * the partition definitions.
- * (Q: should we register the master MTD object as well?)
+ *
+ * We don't register the master, or expect the caller to have done so,
+ * for reasons of data integrity.
  */
 
 int add_mtd_partitions(struct mtd_info *master,
@@ -346,7 +468,7 @@ int add_mtd_partitions(struct mtd_info *master,
 		       int nbparts)
 {
 	struct mtd_part *slave;
-	u_int32_t cur_offset = 0;
+	uint64_t cur_offset = 0;
 	int i;
 
 	/*
@@ -357,184 +479,14 @@ int add_mtd_partitions(struct mtd_info *master,
 	if (mtd_partitions.next == NULL)
 		INIT_LIST_HEAD(&mtd_partitions);
 
-	printk (KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name);
+	printk(KERN_NOTICE "Creating %d MTD partitions on \"%s\":\n", nbparts, master->name);
 
 	for (i = 0; i < nbparts; i++) {
-
-		/* allocate the partition structure */
-		slave = kzalloc (sizeof(*slave), GFP_KERNEL);
-		if (!slave) {
-			printk ("memory allocation error while creating partitions for \"%s\"\n",
-				master->name);
-			del_mtd_partitions(master);
+		slave = add_one_partition(master, parts + i, i, cur_offset);
+		if (!slave)
 			return -ENOMEM;
-		}
-		list_add(&slave->list, &mtd_partitions);
-
-		/* set up the MTD object for this partition */
-		slave->mtd.type = master->type;
-		slave->mtd.flags = master->flags & ~parts[i].mask_flags;
-		slave->mtd.size = parts[i].size;
-		slave->mtd.writesize = master->writesize;
-		slave->mtd.oobsize = master->oobsize;
-		slave->mtd.oobavail = master->oobavail;
-		slave->mtd.subpage_sft = master->subpage_sft;
-
-		slave->mtd.name = parts[i].name;
-		slave->mtd.owner = master->owner;
-
-		slave->mtd.read = part_read;
-		slave->mtd.write = part_write;
-
-#ifdef MTD_LINUX
-		if (master->panic_write)
-			slave->mtd.panic_write = part_panic_write;
-
-		if(master->point && master->unpoint){
-			slave->mtd.point = part_point;
-			slave->mtd.unpoint = part_unpoint;
-		}
-#endif
-
-		if (master->read_oob)
-			slave->mtd.read_oob = part_read_oob;
-		if (master->write_oob)
-			slave->mtd.write_oob = part_write_oob;
-		if(master->read_user_prot_reg)
-			slave->mtd.read_user_prot_reg = part_read_user_prot_reg;
-		if(master->read_fact_prot_reg)
-			slave->mtd.read_fact_prot_reg = part_read_fact_prot_reg;
-		if(master->write_user_prot_reg)
-			slave->mtd.write_user_prot_reg = part_write_user_prot_reg;
-		if(master->lock_user_prot_reg)
-			slave->mtd.lock_user_prot_reg = part_lock_user_prot_reg;
-		if(master->get_user_prot_info)
-			slave->mtd.get_user_prot_info = part_get_user_prot_info;
-		if(master->get_fact_prot_info)
-			slave->mtd.get_fact_prot_info = part_get_fact_prot_info;
-		if (master->sync)
-			slave->mtd.sync = part_sync;
-#ifdef MTD_LINUX
-		if (!i && master->suspend && master->resume) {
-				slave->mtd.suspend = part_suspend;
-				slave->mtd.resume = part_resume;
-		}
-		if (master->writev)
-			slave->mtd.writev = part_writev;
-		if (master->lock)
-			slave->mtd.lock = part_lock;
-		if (master->unlock)
-			slave->mtd.unlock = part_unlock;
-#endif
-		if (master->block_isbad)
-			slave->mtd.block_isbad = part_block_isbad;
-		if (master->block_markbad)
-			slave->mtd.block_markbad = part_block_markbad;
-		slave->mtd.erase = part_erase;
-		slave->master = master;
-		slave->offset = parts[i].offset;
-		slave->index = i;
-
-		if (slave->offset == MTDPART_OFS_APPEND)
-			slave->offset = cur_offset;
-		if (slave->offset == MTDPART_OFS_NXTBLK) {
-			slave->offset = cur_offset;
-			if ((cur_offset % master->erasesize) != 0) {
-				/* Round up to next erasesize */
-				slave->offset = ((cur_offset / master->erasesize) + 1) * master->erasesize;
-				printk(KERN_NOTICE "Moving partition %d: "
-				       "0x%08x -> 0x%08x\n", i,
-				       cur_offset, slave->offset);
-			}
-		}
-		if (slave->mtd.size == MTDPART_SIZ_FULL)
-			slave->mtd.size = master->size - slave->offset;
 		cur_offset = slave->offset + slave->mtd.size;
-
-		printk (KERN_NOTICE "0x%08x-0x%08x : \"%s\"\n", slave->offset,
-			slave->offset + slave->mtd.size, slave->mtd.name);
-
-		/* let's do some sanity checks */
-		if (slave->offset >= master->size) {
-				/* let's register it anyway to preserve ordering */
-			slave->offset = 0;
-			slave->mtd.size = 0;
-			printk ("mtd: partition \"%s\" is out of reach -- disabled\n",
-				parts[i].name);
-		}
-		if (slave->offset + slave->mtd.size > master->size) {
-			slave->mtd.size = master->size - slave->offset;
-			printk ("mtd: partition \"%s\" extends beyond the end of device \"%s\" -- size truncated to %#x\n",
-				parts[i].name, master->name, slave->mtd.size);
-		}
-		if (master->numeraseregions>1) {
-			/* Deal with variable erase size stuff */
-			int i;
-			struct mtd_erase_region_info *regions = master->eraseregions;
-
-			/* Find the first erase regions which is part of this partition. */
-			for (i=0; i < master->numeraseregions && slave->offset >= regions[i].offset; i++)
-				;
-
-			for (i--; i < master->numeraseregions && slave->offset + slave->mtd.size > regions[i].offset; i++) {
-				if (slave->mtd.erasesize < regions[i].erasesize) {
-					slave->mtd.erasesize = regions[i].erasesize;
-				}
-			}
-		} else {
-			/* Single erase size */
-			slave->mtd.erasesize = master->erasesize;
-		}
-
-		if ((slave->mtd.flags & MTD_WRITEABLE) &&
-		    (slave->offset % slave->mtd.erasesize)) {
-			/* Doesn't start on a boundary of major erase size */
-			/* FIXME: Let it be writable if it is on a boundary of _minor_ erase size though */
-			slave->mtd.flags &= ~MTD_WRITEABLE;
-			printk ("mtd: partition \"%s\" doesn't start on an erase block boundary -- force read-only\n",
-				parts[i].name);
-		}
-		if ((slave->mtd.flags & MTD_WRITEABLE) &&
-		    (slave->mtd.size % slave->mtd.erasesize)) {
-			slave->mtd.flags &= ~MTD_WRITEABLE;
-			printk ("mtd: partition \"%s\" doesn't end on an erase block -- force read-only\n",
-				parts[i].name);
-		}
-
-		slave->mtd.ecclayout = master->ecclayout;
-		if (master->block_isbad) {
-			uint32_t offs = 0;
-
-			while(offs < slave->mtd.size) {
-				if (master->block_isbad(master,
-							offs + slave->offset))
-					slave->mtd.ecc_stats.badblocks++;
-				offs += slave->mtd.erasesize;
-			}
-		}
-
-#ifdef MTD_LINUX
-		if (parts[i].mtdp) {
-			/* store the object pointer
-			 * (caller may or may not register it */
-			*parts[i].mtdp = &slave->mtd;
-			slave->registered = 0;
-		} else {
-			/* register our partition */
-			add_mtd_device(&slave->mtd);
-			slave->registered = 1;
-		}
-#else
-		/* register our partition */
-		add_mtd_device(&slave->mtd);
-		slave->registered = 1;
-#endif
 	}
 
 	return 0;
 }
-
-#ifdef MTD_LINUX
-EXPORT_SYMBOL(add_mtd_partitions);
-EXPORT_SYMBOL(del_mtd_partitions);
-#endif
diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c
index 6ba52b30c0a..88206d067a6 100644
--- a/drivers/mtd/nand/nand_util.c
+++ b/drivers/mtd/nand/nand_util.c
@@ -36,12 +36,15 @@
 #include <malloc.h>
 #include <div64.h>
 
-
 #include <asm/errno.h>
 #include <linux/mtd/mtd.h>
 #include <nand.h>
 #include <jffs2/jffs2.h>
 
+#if !defined(CONFIG_SYS_64BIT_VSPRINTF)
+#warning Please define CONFIG_SYS_64BIT_VSPRINTF for correct output!
+#endif
+
 typedef struct erase_info erase_info_t;
 typedef struct mtd_info	  mtd_info_t;
 
@@ -127,7 +130,7 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			if (ret > 0) {
 				if (!opts->quiet)
 					printf("\rSkipping bad block at  "
-					       "0x%08x                   "
+					       "0x%08llx                 "
 					       "                         \n",
 					       erase.addr);
 				continue;
@@ -181,11 +184,11 @@ int nand_erase_opts(nand_info_t *meminfo, const nand_erase_options_t *opts)
 			if (percent != percent_complete) {
 				percent_complete = percent;
 
-				printf("\rErasing at 0x%x -- %3d%% complete.",
+				printf("\rErasing at 0x%llx -- %3d%% complete.",
 				       erase.addr, percent);
 
 				if (opts->jffs2 && result == 0)
-					printf(" Cleanmarker written at 0x%x.",
+					printf(" Cleanmarker written at 0x%llx.",
 					       erase.addr);
 			}
 		}
diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h
index 354e3a0bc47..c884567b965 100644
--- a/include/linux/mtd/mtd.h
+++ b/include/linux/mtd/mtd.h
@@ -8,6 +8,7 @@
 #define __MTD_MTD_H__
 
 #include <linux/types.h>
+#include <div64.h>
 #include <linux/mtd/mtd-abi.h>
 
 #define MTD_CHAR_MAJOR 90
@@ -20,6 +21,8 @@
 #define MTD_ERASE_DONE          0x08
 #define MTD_ERASE_FAILED        0x10
 
+#define MTD_FAIL_ADDR_UNKNOWN	-1LL
+
 /*
  * Enumeration for NAND/OneNAND flash chip state
  */
@@ -37,13 +40,13 @@ enum {
 };
 
 /* If the erase fails, fail_addr might indicate exactly which block failed.  If
-   fail_addr = 0xffffffff, the failure was not at the device level or was not
+   fail_addr = MTD_FAIL_ADDR_UNKNOWN, the failure was not at the device level or was not
    specific to any particular block. */
 struct erase_info {
 	struct mtd_info *mtd;
-	u_int32_t addr;
-	u_int32_t len;
-	u_int32_t fail_addr;
+	uint64_t addr;
+	uint64_t len;
+	uint64_t fail_addr;
 	u_long time;
 	u_long retries;
 	u_int dev;
@@ -55,7 +58,7 @@ struct erase_info {
 };
 
 struct mtd_erase_region_info {
-	u_int32_t offset;			/* At which this region starts, from the beginning of the MTD */
+	uint64_t offset;			/* At which this region starts, from the beginning of the MTD */
 	u_int32_t erasesize;		/* For this region */
 	u_int32_t numblocks;		/* Number of blocks of erasesize in this region */
 	unsigned long *lockmap;		/* If keeping bitmap of locks */
@@ -110,7 +113,7 @@ struct mtd_oob_ops {
 struct mtd_info {
 	u_char type;
 	u_int32_t flags;
-	u_int32_t size;	 /* Total size of the MTD */
+	uint64_t size;	 // Total size of the MTD
 
 	/* "Major" erase size for the device. Naïve users may take this
 	 * to be the only erase size available, or may use the more detailed
@@ -202,8 +205,8 @@ struct mtd_info {
 	void (*sync) (struct mtd_info *mtd);
 
 	/* Chip-supported device locking */
-	int (*lock) (struct mtd_info *mtd, loff_t ofs, size_t len);
-	int (*unlock) (struct mtd_info *mtd, loff_t ofs, size_t len);
+	int (*lock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
+	int (*unlock) (struct mtd_info *mtd, loff_t ofs, uint64_t len);
 
 	/* Power Management functions */
 	int (*suspend) (struct mtd_info *mtd);
@@ -236,6 +239,16 @@ struct mtd_info {
 	void (*put_device) (struct mtd_info *mtd);
 };
 
+static inline uint32_t mtd_div_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	do_div(sz, mtd->erasesize);
+	return sz;
+}
+
+static inline uint32_t mtd_mod_by_eb(uint64_t sz, struct mtd_info *mtd)
+{
+	return do_div(sz, mtd->erasesize);
+}
 
 	/* Kernel-side ioctl definitions */
 
-- 
cgit v1.3.1


From 942556a92a8c1eb1bd76584a5143f6f57dcb25ad Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 12 May 2009 14:32:58 +0200
Subject: mtd: MTD related config header changes (mtdparts command)

By changing the cmd_mtdparts to only use the MTD infrastructure and
not the direct interface to the CFI NOR FLASH driver we now need
to add the MTD infrastructure to all boards using those mtdparts
commands. This patch adds those components:

CONFIG_MTD_DEVICE (for all FLASH types)

plus

CONFIG_FLASH_CFI_MTD (for NOR FLASH)

To all board maintainers: Please test this on your platforms and
report any problems/issues found. Thanks.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ron Madrid <info@sheldoninst.com>
Cc: Georg Schardt <schardt@team-ctech.de>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Martin Krause <martin.krause@tqs.de>
Cc: Gary Jennejohn <garyj@denx.de>
Cc: Ricardo Ribalda <ricardo.ribalda@uam.es>
---
 include/configs/BC3450.h             | 2 ++
 include/configs/FPS850L.h            | 2 ++
 include/configs/FPS860L.h            | 2 ++
 include/configs/SIMPC8313.h          | 1 +
 include/configs/TB5200.h             | 2 ++
 include/configs/TQM5200.h            | 2 ++
 include/configs/TQM823L.h            | 2 ++
 include/configs/TQM823M.h            | 2 ++
 include/configs/TQM834x.h            | 2 ++
 include/configs/TQM850L.h            | 2 ++
 include/configs/TQM850M.h            | 2 ++
 include/configs/TQM855L.h            | 2 ++
 include/configs/TQM855M.h            | 2 ++
 include/configs/TQM85xx.h            | 2 ++
 include/configs/TQM860L.h            | 2 ++
 include/configs/TQM860M.h            | 2 ++
 include/configs/TQM862L.h            | 2 ++
 include/configs/TQM862M.h            | 2 ++
 include/configs/TQM866M.h            | 2 ++
 include/configs/apollon.h            | 1 +
 include/configs/cm5200.h             | 2 ++
 include/configs/fx12mm.h             | 2 ++
 include/configs/idmr.h               | 2 ++
 include/configs/microblaze-generic.h | 2 ++
 include/configs/motionpro.h          | 2 ++
 include/configs/mx1fs2.h             | 2 ++
 include/configs/netstar.h            | 2 ++
 include/configs/omap3_beagle.h       | 1 +
 include/configs/qong.h               | 2 ++
 include/configs/smmaco4.h            | 2 ++
 include/configs/trab.h               | 2 ++
 include/configs/vct.h                | 1 +
 include/configs/virtlab2.h           | 2 ++
 include/configs/voiceblue.h          | 2 ++
 include/configs/xilinx-ppc.h         | 2 ++
 35 files changed, 66 insertions(+)

(limited to 'include')

diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h
index 9934f29b7fa..8c5a742290e 100644
--- a/include/configs/BC3450.h
+++ b/include/configs/BC3450.h
@@ -347,6 +347,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
 #define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"1408k(kernel),"	\
diff --git a/include/configs/FPS850L.h b/include/configs/FPS850L.h
index f152230da72..aceecd86d44 100644
--- a/include/configs/FPS850L.h
+++ b/include/configs/FPS850L.h
@@ -217,6 +217,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/FPS860L.h b/include/configs/FPS860L.h
index 5eaed842bf7..4a61d7c7594 100644
--- a/include/configs/FPS860L.h
+++ b/include/configs/FPS860L.h
@@ -217,6 +217,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 88ea7c7c93b..8d1e95b5539 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -190,6 +190,7 @@
 
 /* mtdparts command line support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
 #define MTDIDS_DEFAULT		"nand0=nand0"
 #define MTDPARTS_DEFAULT	"mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
 
diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h
index 92b4fa503ef..3438abaeaae 100644
--- a/include/configs/TB5200.h
+++ b/include/configs/TB5200.h
@@ -276,6 +276,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
 #if defined(CONFIG_TQM5200_B)
 #define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:768k(firmware),"	\
diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h
index fe1d10290be..a4336a75004 100644
--- a/include/configs/TQM5200.h
+++ b/include/configs/TQM5200.h
@@ -408,6 +408,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
 
 #ifdef CONFIG_STK52XX
diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h
index 87e5a650d22..1f816f35a13 100644
--- a/include/configs/TQM823L.h
+++ b/include/configs/TQM823L.h
@@ -232,6 +232,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h
index f6664437d36..42dcbfc2a31 100644
--- a/include/configs/TQM823M.h
+++ b/include/configs/TQM823M.h
@@ -228,6 +228,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index dbd30ac4b0f..70f222ca0f5 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -534,6 +534,8 @@ extern int tqm834x_num_flash_banks;
  */
 /* mtdparts command line support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM834x-0"
 
 /* default mtd partition table */
diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h
index dc80b4746d4..290e211ad17 100644
--- a/include/configs/TQM850L.h
+++ b/include/configs/TQM850L.h
@@ -217,6 +217,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h
index 22894432cbd..2170df5dcb1 100644
--- a/include/configs/TQM850M.h
+++ b/include/configs/TQM850M.h
@@ -217,6 +217,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h
index 999bdaadcb6..3d7dc4233bb 100644
--- a/include/configs/TQM855L.h
+++ b/include/configs/TQM855L.h
@@ -222,6 +222,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index b54967dae78..35cfa088227 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -257,6 +257,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index 08465010e04..6f13c63f5c9 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -567,6 +567,8 @@
 #define	CONFIG_JFFS2_NAND	1
 
 #ifdef CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nand0=TQM85xx-nand"
 #define MTDPARTS_DEFAULT	"mtdparts=TQM85xx-nand:-"
 #else
diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h
index 2e2a165b8a5..4ac485d3215 100644
--- a/include/configs/TQM860L.h
+++ b/include/configs/TQM860L.h
@@ -221,6 +221,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h
index 1148f2e4efb..39da0bbd6ed 100644
--- a/include/configs/TQM860M.h
+++ b/include/configs/TQM860M.h
@@ -222,6 +222,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h
index 577f982c5a3..1f79b170dbe 100644
--- a/include/configs/TQM862L.h
+++ b/include/configs/TQM862L.h
@@ -225,6 +225,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h
index 69070e64597..86d5b016365 100644
--- a/include/configs/TQM862M.h
+++ b/include/configs/TQM862M.h
@@ -226,6 +226,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
index bb6861470ff..04f538ce517 100644
--- a/include/configs/TQM866M.h
+++ b/include/configs/TQM866M.h
@@ -266,6 +266,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxM-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxM-0:512k(u-boot),"	\
diff --git a/include/configs/apollon.h b/include/configs/apollon.h
index 925079d0c47..fa5a7a9e22d 100644
--- a/include/configs/apollon.h
+++ b/include/configs/apollon.h
@@ -124,6 +124,7 @@
 #define	CONFIG_CMD_JFFS2
 #define	CONFIG_CMD_UBI
 #define	CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS
 #endif
 
diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h
index 54cf40d67fc..72cf941ab55 100644
--- a/include/configs/cm5200.h
+++ b/include/configs/cm5200.h
@@ -223,6 +223,8 @@
  * MTD configuration
  */
 #define CONFIG_CMD_MTDPARTS	1
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=cm5200-0"
 #define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
 					"384k(uboot),128k(env),"	\
diff --git a/include/configs/fx12mm.h b/include/configs/fx12mm.h
index 27c6e7d4a7d..e825c215017 100644
--- a/include/configs/fx12mm.h
+++ b/include/configs/fx12mm.h
@@ -38,6 +38,8 @@
 /* cmd config */
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #undef CONFIG_CMD_NET
 
 /* sdram */
diff --git a/include/configs/idmr.h b/include/configs/idmr.h
index 944d06fbfc0..841affb7cce 100644
--- a/include/configs/idmr.h
+++ b/include/configs/idmr.h
@@ -230,6 +230,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=idmr-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=idmr-0:128k(u-boot),"	\
diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h
index aa117c8f713..72715f6ed9d 100644
--- a/include/configs/microblaze-generic.h
+++ b/include/configs/microblaze-generic.h
@@ -260,6 +260,8 @@
 #if defined(CONFIG_CMD_JFFS2)
 /* JFFS2 partitions */
 #define CONFIG_CMD_MTDPARTS	/* mtdparts command line support */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=ml401-0"
 
 /* default mtd partition table */
diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h
index 99a02cc2234..fa4310b79fe 100644
--- a/include/configs/motionpro.h
+++ b/include/configs/motionpro.h
@@ -276,6 +276,8 @@
  * MTD configuration
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=motionpro-0"
 #define MTDPARTS_DEFAULT	"mtdparts=motionpro-0:"			  \
 					"13m(fs),2m(kernel),256k(uboot)," \
diff --git a/include/configs/mx1fs2.h b/include/configs/mx1fs2.h
index 24fa144ec66..90a8d8405b5 100644
--- a/include/configs/mx1fs2.h
+++ b/include/configs/mx1fs2.h
@@ -183,6 +183,8 @@
 /* mtdparts command line support */
 /* Note: fake mtd_id used, no linux mtd map file */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=mx1fs2-0"
 
 #ifdef BUS32BIT_VERSION
diff --git a/include/configs/netstar.h b/include/configs/netstar.h
index 5cfee66229b..5062cdb167c 100644
--- a/include/configs/netstar.h
+++ b/include/configs/netstar.h
@@ -130,6 +130,8 @@
  * partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=omapflash.0,nand0=omapnand.0"
 #define MTDPARTS_DEFAULT	"mtdparts=" \
 	"omapflash.0:8k@16k(env),8k(r_env),448k@576k(u-boot);" \
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index a3d9cf69454..c2bd7e67e30 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -105,6 +105,7 @@
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
 #define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands */
+#define CONFIG_MTD_DEVICE	/* needed for mtdparts commands */
 #define MTDIDS_DEFAULT			"nand0=nand"
 #define MTDPARTS_DEFAULT		"mtdparts=nand:512k(x-loader),"\
 					"1920k(u-boot),128k(u-boot-env),"\
diff --git a/include/configs/qong.h b/include/configs/qong.h
index a67006aa2d6..7e6718503ee 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -213,6 +213,8 @@
  * JFFS2 partitions
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
 #define MTDPARTS_DEFAULT	\
 	"mtdparts=physmap-flash.0:256k(U-Boot),128k(env1),"	\
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
index 35f3e3a0223..5a2ef3aa8c3 100644
--- a/include/configs/smmaco4.h
+++ b/include/configs/smmaco4.h
@@ -215,6 +215,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM5200-0"
 #define MTDPARTS_DEFAULT	"mtdparts=TQM5200-0:640k(firmware),"	\
 						"1408k(kernel),"	\
diff --git a/include/configs/trab.h b/include/configs/trab.h
index 51ad3cadaf6..7687ee6dcba 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -375,6 +375,8 @@
 
 /* Dynamic MTD partition support */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=0"
 
 /* production flash layout */
diff --git a/include/configs/vct.h b/include/configs/vct.h
index fe679974c0c..e72b5045494 100644
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -296,6 +296,7 @@ int vct_gpio_get(int pin);
 #define	CONFIG_CMD_JFFS2
 #define	CONFIG_CMD_UBI
 #define	CONFIG_RBTREE
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
 #define CONFIG_MTD_PARTITIONS
 #define CONFIG_CMD_MTDPARTS
 
diff --git a/include/configs/virtlab2.h b/include/configs/virtlab2.h
index 021012d0f95..9ebafcccbca 100644
--- a/include/configs/virtlab2.h
+++ b/include/configs/virtlab2.h
@@ -226,6 +226,8 @@
  * Dynamic MTD partition support
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=TQM8xxL-0"
 
 #define MTDPARTS_DEFAULT	"mtdparts=TQM8xxL-0:256k(u-boot),"	\
diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h
index aa8efaad5ad..c9c31323553 100644
--- a/include/configs/voiceblue.h
+++ b/include/configs/voiceblue.h
@@ -190,6 +190,8 @@
  * JFFS2 partitions (mtdparts command line support)
  */
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #define MTDIDS_DEFAULT		"nor0=omapflash.0"
 #define MTDPARTS_DEFAULT	"mtdparts=omapflash.0:256k(u-boot),64k(env),64k(r_env),16192k(data0),-(data1)"
 
diff --git a/include/configs/xilinx-ppc.h b/include/configs/xilinx-ppc.h
index e3ea84b3159..6efe3421fc0 100644
--- a/include/configs/xilinx-ppc.h
+++ b/include/configs/xilinx-ppc.h
@@ -109,6 +109,8 @@
 #define	CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
+#define CONFIG_FLASH_CFI_MTD
 #else
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_SYS_NO_FLASH
-- 
cgit v1.3.1


From ecb1dc892297d5d99876907328fed732feefeab2 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 20 May 2009 04:35:14 -0400
Subject: Add support for Linux-like kallsysms

The kernel stores address<->symbol names in it so things can be decoded at
runtime.  Do it in U-Boot, and we get nice symbol decoding when crashing.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 Makefile                          | 17 +++++++++++----
 common/Makefile                   |  1 +
 common/kallsyms.c                 | 44 +++++++++++++++++++++++++++++++++++++++
 common/system_map.c               |  8 +++++++
 cpu/blackfin/system_map.S         | 18 ----------------
 cpu/blackfin/traps.c              | 35 +++++--------------------------
 include/common.h                  |  3 +++
 include/configs/bfin_adi_common.h |  2 +-
 8 files changed, 75 insertions(+), 53 deletions(-)
 create mode 100644 common/kallsyms.c
 create mode 100644 common/system_map.c
 delete mode 100644 cpu/blackfin/system_map.S

(limited to 'include')

diff --git a/Makefile b/Makefile
index d14678070e8..4445b4b6a35 100644
--- a/Makefile
+++ b/Makefile
@@ -344,12 +344,19 @@ $(obj)u-boot.sha1:	$(obj)u-boot.bin
 $(obj)u-boot.dis:	$(obj)u-boot
 		$(OBJDUMP) -d $< > $@
 
-$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
+GEN_UBOOT = \
 		UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
 		sed  -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
 		cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
 			--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
 			-Map u-boot.map -o u-boot
+$(obj)u-boot:		depend $(SUBDIRS) $(OBJS) $(LIBBOARD) $(LIBS) $(LDSCRIPT)
+		$(GEN_UBOOT)
+ifeq ($(CONFIG_KALLSYMS),y)
+		smap=`$(call SYSTEM_MAP,u-boot) | awk '$$2 ~ /[tTwW]/ {printf $$1 $$3 "\\0"}'` ; \
+		$(CC) $(CFLAGS) -DSYSTEM_MAP="\"$${smap}\"" -c common/system_map.c -o $(obj)common/system_map.o
+		$(GEN_UBOOT) $(obj)common/system_map.o
+endif
 
 $(OBJS):	depend
 		$(MAKE) -C cpu/$(CPU) $(if $(REMOTE_BUILD),$@,$(notdir $@))
@@ -448,10 +455,12 @@ cscope:
 						> cscope.files
 		cscope -b -q -k
 
-$(obj)System.map:	$(obj)u-boot
-		@$(NM) $< | \
+SYSTEM_MAP = \
+		$(NM) $1 | \
 		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
-		sort > $(obj)System.map
+		LC_ALL=C sort
+$(obj)System.map:	$(obj)u-boot
+		@$(call SYSTEM_MAP,$<) > $(obj)System.map
 
 #
 # Auto-generate the autoconf.mk file (which is included by all makefiles)
diff --git a/common/Makefile b/common/Makefile
index 2ca10264c2b..ee0cb33aca3 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -153,6 +153,7 @@ COBJS-$(CONFIG_CMD_DOC) += docecc.o
 COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
 COBJS-y += flash.o
 COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-$(CONFIG_KALLSYMS) += kallsyms.o
 COBJS-$(CONFIG_LCD) += lcd.o
 COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
 COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
diff --git a/common/kallsyms.c b/common/kallsyms.c
new file mode 100644
index 00000000000..ce42a932bb8
--- /dev/null
+++ b/common/kallsyms.c
@@ -0,0 +1,44 @@
+/*
+ * Helper functions for working with the builtin symbol table
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+
+/* We need the weak marking as this symbol is provided specially */
+extern const char system_map[] __attribute__((weak));
+
+/* Given an address, return a pointer to the symbol name and store
+ * the base address in caddr.  So if the symbol map had an entry:
+ *		03fb9b7c_spi_cs_deactivate
+ * Then the following call:
+ *		unsigned long base;
+ *		const char *sym = symbol_lookup(0x03fb9b80, &base);
+ * Would end up setting the variables like so:
+ *		base = 0x03fb9b7c;
+ *		sym = "_spi_cs_deactivate";
+ */
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+{
+	const char *sym, *csym;
+	char *esym;
+	unsigned long sym_addr;
+
+	sym = system_map;
+	csym = NULL;
+	*caddr = 0;
+
+	while (*sym) {
+		sym_addr = simple_strtoul(sym, &esym, 16);
+		sym = esym;
+		if (sym_addr > addr)
+			break;
+		*caddr = sym_addr;
+		csym = sym;
+		sym += strlen(sym) + 1;
+	}
+
+	return csym;
+}
diff --git a/common/system_map.c b/common/system_map.c
new file mode 100644
index 00000000000..8307293bf3a
--- /dev/null
+++ b/common/system_map.c
@@ -0,0 +1,8 @@
+/*
+ * The builtin symbol table for use with kallsyms
+ *
+ * Copyright (c) 2008-2009 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+const char const system_map[] = SYSTEM_MAP;
diff --git a/cpu/blackfin/system_map.S b/cpu/blackfin/system_map.S
deleted file mode 100644
index 286d7f34a0f..00000000000
--- a/cpu/blackfin/system_map.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * system_map.S - optional symbol lookup for debugging
- *
- * Copyright (c) 2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-
-#ifdef CONFIG_DEBUG_DUMP_SYMS
-.data
-.global _system_map
-.type _system_map,@object
-_system_map:
-#include SYM_FILE
-.asciz ""
-.size _system_map,.-_system_map
-#endif
diff --git a/cpu/blackfin/traps.c b/cpu/blackfin/traps.c
index 2121b0e4cbc..7e7c74ce473 100644
--- a/cpu/blackfin/traps.c
+++ b/cpu/blackfin/traps.c
@@ -171,38 +171,13 @@ void trap_c(struct pt_regs *regs)
 # define ENABLE_DUMP 0
 #endif
 
-#ifdef CONFIG_DEBUG_DUMP_SYMS
-# define ENABLE_DUMP_SYMS 1
-#else
-# define ENABLE_DUMP_SYMS 0
-#endif
-
-static const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
+#ifndef CONFIG_KALLSYMS
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
 {
-	if (!ENABLE_DUMP_SYMS)
-		return NULL;
-
-	extern const char system_map[] __attribute__((__weak__));
-	const char *sym, *csym;
-	char *esym;
-	unsigned long sym_addr;
-
-	sym = system_map;
-	csym = NULL;
-	*caddr = 0;
-
-	while (*sym) {
-		sym_addr = simple_strtoul(sym, &esym, 16);
-		sym = esym;
-		if (sym_addr > addr)
-			break;
-		*caddr = sym_addr;
-		csym = sym;
-		sym += strlen(sym) + 1;
-	}
-
-	return csym;
+	*caddr = addr;
+	return "N/A";
 }
+#endif
 
 static void decode_address(char *buf, unsigned long address)
 {
diff --git a/include/common.h b/include/common.h
index 30fff7d65ee..df0f5a01e1a 100644
--- a/include/common.h
+++ b/include/common.h
@@ -300,6 +300,9 @@ int	misc_init_r   (void);
 /* common/exports.c */
 void	jumptable_init(void);
 
+/* common/kallsysm.c */
+const char *symbol_lookup(unsigned long addr, unsigned long *caddr);
+
 /* api/api.c */
 void	api_init (void);
 
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index bfe53762c39..e0be07b477e 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -91,7 +91,7 @@
  */
 #define CONFIG_ENV_OVERWRITE	1
 #define CONFIG_DEBUG_DUMP	1
-#define CONFIG_DEBUG_DUMP_SYMS	1
+#define CONFIG_KALLSYMS		1
 #define CONFIG_PANIC_HANG	1
 
 /*
-- 
cgit v1.3.1


From 94796d8544d4248028141bad11c6a74b840e9d6e Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Sun, 24 May 2009 19:17:29 +0200
Subject: Make "usage" messages more helpful.

In case of incorrect command invocations U-Boot used to print pretty
useless "usage" messages, for example:

	=> nand markbad
	Usage:
	nand - NAND sub-system

In the result, the user would have to run the "help" command to get
the (available) information about correct command usage. Change this,
so that this information gets always printed.

Note that this changes the user interface of all commands, but
hopefully to the better.

Signed-off-by: Wolfgang Denk <wd@denx.de>
---
 common/command.c  | 33 ++++++++++++++++-----------------
 include/command.h |  2 +-
 2 files changed, 17 insertions(+), 18 deletions(-)

(limited to 'include')

diff --git a/common/command.c b/common/command.c
index c9a3f5bf6b5..16f3afe3947 100644
--- a/common/command.c
+++ b/common/command.c
@@ -286,21 +286,7 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
 	 */
 	for (i = 1; i < argc; ++i) {
 		if ((cmdtp = find_cmd_tbl (argv[i], cmd_start, cmd_items )) != NULL) {
-#ifdef	CONFIG_SYS_LONGHELP
-			/* found - print (long) help info */
-			puts (cmdtp->name);
-			putc (' ');
-			if (cmdtp->help) {
-				puts (cmdtp->help);
-			} else {
-				puts ("- No help available.\n");
-				rcode = 1;
-			}
-			putc ('\n');
-#else	/* no long help available */
-			if (cmdtp->usage)
-				printf ("%s - %s\n", cmdtp->name, cmdtp->usage);
-#endif	/* CONFIG_SYS_LONGHELP */
+			rcode |= cmd_usage(cmdtp);
 		} else {
 			printf ("Unknown command '%s' - try 'help'"
 				" without arguments for list of all"
@@ -386,9 +372,22 @@ cmd_tbl_t *find_cmd (const char *cmd)
 	return find_cmd_tbl(cmd, &__u_boot_cmd_start, len);
 }
 
-void cmd_usage(cmd_tbl_t *cmdtp)
+int cmd_usage(cmd_tbl_t *cmdtp)
 {
-	printf("Usage:\n%s - %s\n\n", cmdtp->name, cmdtp->usage);
+	printf("%s - %s\n\n", cmdtp->name, cmdtp->usage);
+
+#ifdef	CONFIG_SYS_LONGHELP
+	printf("Usage:\n%s ", cmdtp->name);
+
+	if (!cmdtp->help) {
+		puts ("- No additional help available.\n");
+		return 1;
+	}
+
+	puts (cmdtp->help);
+	putc ('\n');
+#endif	/* CONFIG_SYS_LONGHELP */
+	return 0;
 }
 
 #ifdef CONFIG_AUTO_COMPLETE
diff --git a/include/command.h b/include/command.h
index bd478539250..55caa6eaf88 100644
--- a/include/command.h
+++ b/include/command.h
@@ -71,7 +71,7 @@ int _do_help (cmd_tbl_t *cmd_start, int cmd_items, cmd_tbl_t * cmdtp, int
 cmd_tbl_t *find_cmd(const char *cmd);
 cmd_tbl_t *find_cmd_tbl (const char *cmd, cmd_tbl_t *table, int table_len);
 
-extern void cmd_usage(cmd_tbl_t *cmdtp);
+extern int cmd_usage(cmd_tbl_t *cmdtp);
 
 #ifdef CONFIG_AUTO_COMPLETE
 extern void install_auto_complete(void);
-- 
cgit v1.3.1


From 72601d04fdfdd4c7597afcf1f6aab654bd99366c Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Sat, 16 May 2009 10:47:41 +0200
Subject: Rename ads5121 board into mpc5121ads

We rename the board so we use a consistent name in U-Boot and in
Linux.  Also, we use this opportunity to move the board into the
Freecale vendor directory.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
---
 MAKEALL                                 |   2 +-
 Makefile                                |   6 +-
 board/ads5121/Makefile                  |  53 ---
 board/ads5121/README                    |   7 -
 board/ads5121/ads5121.c                 | 331 -------------------
 board/ads5121/config.mk                 |  23 --
 board/freescale/mpc5121ads/Makefile     |  53 +++
 board/freescale/mpc5121ads/README       |   7 +
 board/freescale/mpc5121ads/config.mk    |  23 ++
 board/freescale/mpc5121ads/mpc5121ads.c | 332 +++++++++++++++++++
 include/configs/ads5121.h               | 550 --------------------------------
 include/configs/mpc5121ads.h            | 550 ++++++++++++++++++++++++++++++++
 12 files changed, 969 insertions(+), 968 deletions(-)
 delete mode 100644 board/ads5121/Makefile
 delete mode 100644 board/ads5121/README
 delete mode 100644 board/ads5121/ads5121.c
 delete mode 100644 board/ads5121/config.mk
 create mode 100644 board/freescale/mpc5121ads/Makefile
 create mode 100644 board/freescale/mpc5121ads/README
 create mode 100644 board/freescale/mpc5121ads/config.mk
 create mode 100644 board/freescale/mpc5121ads/mpc5121ads.c
 delete mode 100644 include/configs/ads5121.h
 create mode 100644 include/configs/mpc5121ads.h

(limited to 'include')

diff --git a/MAKEALL b/MAKEALL
index c98d03a579e..0e5f31531cb 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -77,7 +77,7 @@ LIST_5xxx="		\
 #########################################################################
 
 LIST_512x="		\
-	ads5121		\
+	mpc5121ads	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 4445b4b6a35..a43617e8ec1 100644
--- a/Makefile
+++ b/Makefile
@@ -821,14 +821,14 @@ v38b_config: unconfig
 ## MPC512x Systems
 #########################################################################
 
-ads5121_config \
-ads5121_rev2_config	\
+mpc5121ads_config \
+mpc5121ads_rev2_config	\
 	: unconfig
 	@mkdir -p $(obj)include
 	@if [ "$(findstring rev2,$@)" ] ; then \
 		echo "#define CONFIG_ADS5121_REV2 1" > $(obj)include/config.h; \
 	fi
-	@$(MKCONFIG) -a ads5121 ppc mpc512x ads5121
+	@$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale
 
 
 #########################################################################
diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile
deleted file mode 100644
index 20fbf6e9aeb..00000000000
--- a/board/ads5121/Makefile
+++ /dev/null
@@ -1,53 +0,0 @@
-#
-# (C) Copyright 2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-$(shell mkdir -p $(OBJTREE)/board/freescale/common)
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS-y	:= $(BOARD).o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/ads5121/README b/board/ads5121/README
deleted file mode 100644
index defcd6b469a..00000000000
--- a/board/ads5121/README
+++ /dev/null
@@ -1,7 +0,0 @@
-To configure for the current (Rev 3.x) ADS5121
-	make ads5121_config
-This will automatically include PCI, the Real Time CLock, add backup flash
-ability and set the correct frequency and memory configuration.
-
-To configure for the older Rev 2 ADS5121 type (this will not have PCI)
-	make ads5121_rev2_config
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
deleted file mode 100644
index 405432c527e..00000000000
--- a/board/ads5121/ads5121.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/*
- * (C) Copyright 2007 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <mpc512x.h>
-#include <asm/bitops.h>
-#include <command.h>
-#include <asm/processor.h>
-#include <fdt_support.h>
-#ifdef CONFIG_MISC_INIT_R
-#include <i2c.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Clocks in use */
-#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
-			 CLOCK_SCCR1_DDR_EN |				\
-			 CLOCK_SCCR1_FEC_EN |				\
-			 CLOCK_SCCR1_PATA_EN |				\
-			 CLOCK_SCCR1_PCI_EN |				\
-			 CLOCK_SCCR1_TPR_EN)
-
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
-
-#define CSAW_START(start)	((start) & 0xFFFF0000)
-#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
-
-long int fixed_sdram(void);
-
-int board_early_init_f (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 lpcaw;
-
-	/*
-	 * Initialize Local Window for the CPLD registers access (CS2 selects
-	 * the CPLD chip)
-	 */
-	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
-			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
-	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
-
-	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	lpcaw = im->sysconf.lpcs2aw;
-	__asm__ __volatile__ ("isync");
-
-	/*
-	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
-	 *
-	 * Without this the flash identification routine fails, as it needs to issue
-	 * write commands in order to establish the device ID.
-	 */
-
-#ifdef CONFIG_ADS5121_REV2
-	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
-#else
-	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
-		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
-	} else {
-		/* running from Backup flash */
-		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
-	}
-#endif
-	/*
-	 * Configure Flash Speed
-	 */
-	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
-	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
-	}
-	/*
-	 * Enable clocks
-	 */
-	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
-	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
-#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
-	im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
-#endif
-
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	u32 msize = 0;
-
-	msize = fixed_sdram ();
-
-	return msize;
-}
-
-/*
- * fixed sdram init -- the board doesn't use memory modules that have serial presence
- * detect or similar mechanism for discovery of the DRAM settings
- */
-long int fixed_sdram (void)
-{
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
-	u32 msize_log2 = __ilog2 (msize);
-	u32 i;
-
-	/* Initialize IO Control */
-	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
-
-	/* Initialize DDR Local Window */
-	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
-	im->sysconf.ddrlaw.ar = msize_log2 - 1;
-
-	/*
-	 * According to MPC5121e RM, configuring local access windows should
-	 * be followed by a dummy read of the config register that was
-	 * modified last and an isync
-	 */
-	i = im->sysconf.ddrlaw.ar;
-	__asm__ __volatile__ ("isync");
-
-	/* Enable DDR */
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
-
-	/* Initialize DDR Priority Manager */
-	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
-	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
-	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
-	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
-	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
-	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
-	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
-	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
-	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
-	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
-	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
-	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
-	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
-	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
-	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
-	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
-	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
-	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
-	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
-	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
-	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
-	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
-	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
-
-	/* Initialize MDDRC */
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
-	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
-	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
-	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
-
-	/* Initialize DDR */
-	for (i = 0; i < 10; i++)
-		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
-
-	/* Start MDDRC */
-	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
-	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
-
-	return msize;
-}
-
-int misc_init_r(void)
-{
-	u8 tmp_val;
-	extern int mpc5121_diu_init(void);
-
-	/* Using this for DIU init before the driver in linux takes over
-	 *  Enable the TFP410 Encoder (I2C address 0x38)
-	 */
-
-	i2c_set_bus_num(2);
-	tmp_val = 0xBF;
-	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
-
-	tmp_val = 0x10;
-	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	/* Verify if enabled */
-	tmp_val = 0;
-	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
-	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
-
-#ifdef CONFIG_FSL_DIU_FB
-#if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
-	mpc5121_diu_init();
-#endif
-#endif
-
-	return 0;
-}
-static  iopin_t ioregs_init[] = {
-	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
-	{
-		IOCTL_SPDIF_TXCLK, 3, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* Set highest Slew on 9 PATA pins */
-	{
-		IOCTL_PATA_CE1, 9, 1,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
-	{
-		IOCTL_PSC0_0, 15, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC1=SPDIF_TXCLK */
-	{
-		IOCTL_LPC_CS1, 1, 0,
-		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
-	{
-		IOCTL_I2C1_SCL, 2, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU CLK */
-	{
-		IOCTL_PSC6_0, 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIU_HSYNC */
-	{
-		IOCTL_PSC6_1, 1, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	},
-	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
-	{
-		IOCTL_PSC6_4, 26, 0,
-		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
-		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
-	}
-};
-
-static  iopin_t rev2_silicon_pci_ioregs_init[] = {
-	/* FUNC0=PCI Sets next 54 to PCI pads */
-	{
-		IOCTL_PCI_AD31, 54, 0,
-		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
-	}
-};
-
-int checkboard (void)
-{
-	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
-	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
-	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
-		brd_rev, cpld_rev);
-	/* initialize function mux & slew rate IO inter alia on IO Pins  */
-
-	iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
-	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/ads5121/config.mk b/board/ads5121/config.mk
deleted file mode 100644
index 14998f47506..00000000000
--- a/board/ads5121/config.mk
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# (C) Copyright 2007 DENX Software Engineering
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE  =   0xFFF00000
diff --git a/board/freescale/mpc5121ads/Makefile b/board/freescale/mpc5121ads/Makefile
new file mode 100644
index 00000000000..20fbf6e9aeb
--- /dev/null
+++ b/board/freescale/mpc5121ads/Makefile
@@ -0,0 +1,53 @@
+#
+# (C) Copyright 2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+$(shell mkdir -p $(OBJTREE)/board/freescale/common)
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc5121ads/README b/board/freescale/mpc5121ads/README
new file mode 100644
index 00000000000..defcd6b469a
--- /dev/null
+++ b/board/freescale/mpc5121ads/README
@@ -0,0 +1,7 @@
+To configure for the current (Rev 3.x) ADS5121
+	make ads5121_config
+This will automatically include PCI, the Real Time CLock, add backup flash
+ability and set the correct frequency and memory configuration.
+
+To configure for the older Rev 2 ADS5121 type (this will not have PCI)
+	make ads5121_rev2_config
diff --git a/board/freescale/mpc5121ads/config.mk b/board/freescale/mpc5121ads/config.mk
new file mode 100644
index 00000000000..14998f47506
--- /dev/null
+++ b/board/freescale/mpc5121ads/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2007 DENX Software Engineering
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
new file mode 100644
index 00000000000..e8eb491e3b4
--- /dev/null
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -0,0 +1,332 @@
+/*
+ * (C) Copyright 2007 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <mpc512x.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int mpc5121_diu_init(void);
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+long int fixed_sdram(void);
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 lpcaw;
+
+	/*
+	 * Initialize Local Window for the CPLD registers access (CS2 selects
+	 * the CPLD chip)
+	 */
+	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
+			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
+	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	lpcaw = im->sysconf.lpcs2aw;
+	__asm__ __volatile__ ("isync");
+
+	/*
+	 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
+	 *
+	 * Without this the flash identification routine fails, as it needs to issue
+	 * write commands in order to establish the device ID.
+	 */
+
+#ifdef CONFIG_ADS5121_REV2
+	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
+#else
+	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
+	} else {
+		/* running from Backup flash */
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
+	}
+#endif
+	/*
+	 * Configure Flash Speed
+	 */
+	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
+	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
+		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
+	}
+	/*
+	 * Enable clocks
+	 */
+	im->clk.sccr[0] = SCCR1_CLOCKS_EN;
+	im->clk.sccr[1] = SCCR2_CLOCKS_EN;
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	u32 msize = 0;
+
+	msize = fixed_sdram ();
+
+	return msize;
+}
+
+/*
+ * fixed sdram init -- the board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2 (msize);
+	u32 i;
+
+	/* Initialize IO Control */
+	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
+
+	/* Initialize DDR Local Window */
+	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
+	im->sysconf.ddrlaw.ar = msize_log2 - 1;
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	i = im->sysconf.ddrlaw.ar;
+	__asm__ __volatile__ ("isync");
+
+	/* Enable DDR */
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
+
+	/* Initialize DDR Priority Manager */
+	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
+	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
+	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
+	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
+	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
+	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
+	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
+	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
+	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
+	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
+	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
+	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
+	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
+	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
+	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
+	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
+	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
+	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
+	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
+	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
+	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
+	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
+	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
+
+	/* Initialize MDDRC */
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
+	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
+	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
+
+	/* Initialize DDR */
+	for (i = 0; i < 10; i++)
+		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+
+	/* Start MDDRC */
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
+
+	return msize;
+}
+
+int misc_init_r(void)
+{
+	u8 tmp_val;
+
+	/* Using this for DIU init before the driver in linux takes over
+	 *  Enable the TFP410 Encoder (I2C address 0x38)
+	 */
+
+	i2c_set_bus_num(2);
+	tmp_val = 0xBF;
+	i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+	tmp_val = 0x10;
+	i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	/* Verify if enabled */
+	tmp_val = 0;
+	i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
+	debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
+
+#ifdef CONFIG_FSL_DIU_FB
+# if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+	mpc5121_diu_init();
+# endif
+#endif
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		IOCTL_SPDIF_TXCLK, 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* Set highest Slew on 9 PATA pins */
+	{
+		IOCTL_PATA_CE1, 9, 1,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		IOCTL_PSC0_0, 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SPDIF_TXCLK */
+	{
+		IOCTL_LPC_CS1, 1, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
+	{
+		IOCTL_I2C1_SCL, 2, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU CLK */
+	{
+		IOCTL_PSC6_0, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		IOCTL_PSC6_1, 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		IOCTL_PSC6_4, 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static  iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		IOCTL_PCI_AD31, 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard (void)
+{
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+
+	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
+		brd_rev, cpld_rev);
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	if (SVR_MJREV (im->sysconf.spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
deleted file mode 100644
index b1420fa8886..00000000000
--- a/include/configs/ads5121.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * (C) Copyright 2007, 2008 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * ADS5121 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ADS5121 1
-/*
- * Memory map for the ADS5121 board:
- *
- * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
- * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
- * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
- * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
- * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
- * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
- * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
- * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
- */
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC512X		1	/* MPC512X family */
-#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
-#undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
-
-/* video */
-#undef CONFIG_VIDEO
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_CFB_CONSOLE
-#define CONFIG_VGA_AS_SINGLE_DEVICE
-#endif
-
-/* CONFIG_PCI is defined at config time */
-
-#ifdef CONFIG_ADS5121_REV2
-#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
-#else
-#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
-#define CONFIG_PCI
-#endif
-
-#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_SYS_IMMR		0x80000000
-#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
-
-#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
-#define CONFIG_SYS_MEMTEST_END		0x00400000
-
-/*
- * DDR Setup - manually set all parameters as there's no SPD etc.
- */
-#ifdef CONFIG_ADS5121_REV2
-#define CONFIG_SYS_DDR_SIZE		256		/* MB */
-#else
-#define CONFIG_SYS_DDR_SIZE		512		/* MB */
-#endif
-#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-
-/* DDR Controller Configuration
- *
- * SYS_CFG:
- *	[31:31]	MDDRC Soft Reset:	Diabled
- *	[30:30]	DRAM CKE pin:		Enabled
- *	[29:29]	DRAM CLK:		Enabled
- *	[28:28]	Command Mode:		Enabled (For initialization only)
- *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
- *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
- *	[20:19]	Read Test:		DON'T USE
- *	[18:18]	Self Refresh:		Enabled
- *	[17:17]	16bit Mode:		Disabled
- *	[16:13] Ready Delay:		2
- *	[12:12]	Half DQS Delay:		Disabled
- *	[11:11]	Quarter DQS Delay:	Disabled
- *	[10:08]	Write Delay:		2
- *	[07:07]	Early ODT:		Disabled
- *	[06:06]	On DIE Termination:	Disabled
- *	[05:05]	FIFO Overflow Clear:	DON'T USE here
- *	[04:04]	FIFO Underflow Clear:	DON'T USE here
- *	[03:03]	FIFO Overflow Pending:	DON'T USE here
- *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
- *	[01:01]	FIFO Overlfow Enabled:	Enabled
- *	[00:00]	FIFO Underflow Enabled:	Enabled
- * TIME_CFG0
- *	[31:16]	DRAM Refresh Time:	0 CSB clocks
- *	[15:8]	DRAM Command Time:	0 CSB clocks
- *	[07:00]	DRAM Precharge Time:	0 CSB clocks
- * TIME_CFG1
- *	[31:26]	DRAM tRFC:
- *	[25:21]	DRAM tWR1:
- *	[20:17]	DRAM tWRT1:
- *	[16:11]	DRAM tDRR:
- *	[10:05]	DRAM tRC:
- *	[04:00]	DRAM tRAS:
- * TIME_CFG2
- *	[31:28]	DRAM tRCD:
- *	[27:23]	DRAM tFAW:
- *	[22:19]	DRAM tRTW1:
- *	[18:15]	DRAM tCCD:
- *	[14:10] DRAM tRTP:
- *	[09:05]	DRAM tRP:
- *	[04:00] DRAM tRPA
- */
-#ifdef CONFIG_ADS5121_REV2
-#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
-#else
-#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
-#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
-#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
-#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
-#endif
-#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
-#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
-#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
-
-#define CONFIG_SYS_MICRON_NOP		0x01380000
-#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
-#define CONFIG_SYS_MICRON_EM2		0x01020000
-#define CONFIG_SYS_MICRON_EM3		0x01030000
-#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
-#define CONFIG_SYS_MICRON_RFSH		0x01080000
-#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
-#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
-
-/* DDR Priority Manager Configuration */
-#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
-#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
-#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
-#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
-#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
-#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
-#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
-#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
-#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
-#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
-#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
-#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
-#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
-
-/*
- * NOR FLASH on the Local Bus
- */
-#undef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
-#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
-#else
-#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
-#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
-#endif
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-
-/*
- * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
- * window is 64KB
- */
-#define CONFIG_SYS_CPLD_BASE		0x82000000
-#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
-
-#define CONFIG_SYS_SRAM_BASE		0x30000000
-#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
-
-#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
-#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
-#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
-
-/* Use SRAM for initial stack */
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#ifdef	CONFIG_FSL_DIU_FB
-#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
-#else
-#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
-#endif
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX     1
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
-#if CONFIG_PSC_CONSOLE != 3
-#error CONFIG_PSC_CONSOLE must be 3
-#endif
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE  \
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
-#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
-#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
-#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef  CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*
- * PCI
- */
-#ifdef CONFIG_PCI
-
-/*
- * General PCI
- */
-#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
-#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
-#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
-#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
-#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCI_IO_BASE		0x00000000
-#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
-#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
-
-
-#define CONFIG_PCI_PNP			/* do pci plug-and-play */
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#endif
-
-/* I2C */
-#define CONFIG_HARD_I2C			/* I2C with hardware support */
-#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
-#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-#if 0
-#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
-#endif
-
-/*
- * IIM - IC Identification Module
- */
-#undef CONFIG_IIM
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC512x_FEC	1
-#define CONFIG_NET_MULTI
-#define CONFIG_PHY_ADDR		0x1
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_FEC_AN_TIMEOUT	1
-#define CONFIG_HAS_ETH0
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-/* This has to be a multiple of the Flash sector size */
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SIZE		0x2000
-#ifdef CONFIG_BKUP_FLASH
-#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
-#else
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
-#endif
-
-/* Address and size of Redundant Environment Sector	*/
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DATE
-#undef CONFIG_CMD_FUSE
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_EXT2
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_CMD_IDE)
-#define CONFIG_DOS_PARTITION
-#define CONFIG_MAC_PARTITION
-#define CONFIG_ISO_PARTITION
-#endif /* defined(CONFIG_CMD_IDE) */
-
-/*
- * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
- * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
- * to 0xFFFF, watchdog timeouts after about 64s. For details refer
- * to chapter 36 of the MPC5121e Reference Manual.
- */
-/* #define CONFIG_WATCHDOG */		/* enable watchdog */
-#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
-
- /*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
-
-#ifdef CONFIG_CMD_KGDB
-	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
-#else
-	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
-#endif
-
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
-
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE		32768
-#define CONFIG_SYS_CACHELINE_SIZE	32
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
-#endif
-
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
-#define CONFIG_SYS_HID2	HID2_HBE
-
-#define CONFIG_HIGH_BATS	1	/* High BATs supported */
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM		0x02	/* Software reboot */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_TIMESTAMP
-
-#define CONFIG_HOSTNAME		ads5121
-#define CONFIG_BOOTFILE		ads5121/uImage
-#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
-
-#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
-
-#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
-#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	"u-boot_addr_r=200000\0"					\
-	"kernel_addr_r=600000\0"					\
-	"fdt_addr_r=880000\0"						\
-	"ramdisk_addr_r=900000\0"					\
-	"u-boot_addr=FFF00000\0"					\
-	"kernel_addr=FFC40000\0"					\
-	"fdt_addr=FFEC0000\0"						\
-	"ramdisk_addr=FC040000\0"					\
-	"ramdiskfile=ads5121/uRamdisk\0"				\
-	"u-boot=ads5121/u-boot.bin\0"					\
-	"bootfile=ads5121/uImage\0"					\
-	"fdtfile=ads5121/ads5121.dtb\0"					\
-	"rootpath=/opt/eldk/ppc_6xx\n"					\
-	"netdev=eth0\0"							\
-	"consdev=ttyPSC0\0"						\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=${serverip}:${rootpath}\0"			\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs ${bootargs} "				\
-		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
-		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} "				\
-		"console=${consdev},${baudrate}\0"			\
-	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
-	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
-	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
-	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
-		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
-		"tftp ${fdt_addr_r} ${fdtfile};"			\
-		"run ramargs addip addtty;"				\
-		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
-	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
-	"update=protect off ${u-boot_addr} +${filesize};"		\
-		"era ${u-boot_addr} +${filesize};"			\
-		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
-	"upd=run load update\0"						\
-	""
-
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#define CONFIG_OF_LIBFDT	1
-#define CONFIG_OF_BOARD_SETUP	1
-#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
-
-#define OF_CPU			"PowerPC,5121@0"
-#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
-#define OF_TBCLK		(bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
-
-/*-----------------------------------------------------------------------
- * IDE/ATA stuff
- *-----------------------------------------------------------------------
- */
-
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
-#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
-
-#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
-#define CONFIG_IDE_PREINIT
-
-#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
-#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
-
-/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
-
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-
-/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
-
-/* Interval between registers	*/
-#define CONFIG_SYS_ATA_STRIDE		4
-
-#define ATA_BASE_ADDR		MPC512X_PATA
-
-/*
- * Control register bit definitions
- */
-#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
-#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
-#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
-#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
-#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
-#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
-#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
-#define FSL_ATA_CTRL_IORDY_EN		0x01000000
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
new file mode 100644
index 00000000000..9e3b0b7317d
--- /dev/null
+++ b/include/configs/mpc5121ads.h
@@ -0,0 +1,550 @@
+/*
+ * (C) Copyright 2007, 2008 DENX Software Engineering
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * MPC5121ADS board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MPC5121ADS 1
+/*
+ * Memory map for the MPC5121ADS board:
+ *
+ * 0x0000_0000 - 0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
+ * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+#undef CONFIG_FSL_DIU_LOGO_BMP		/* Don't include FSL DIU binary bmp */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+/* CONFIG_PCI is defined at config time */
+
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_MPC512X_CLKIN	66000000	/* in Hz */
+#else
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+#define CONFIG_PCI
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR		0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#else
+#define CONFIG_SYS_DDR_SIZE		512		/* MB */
+#endif
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#ifdef CONFIG_MPC5121ADS_REV2
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
+#else
+#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
+#endif
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
+
+#define CONFIG_SYS_MICRON_NOP		0x01380000
+#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EM2		0x01020000
+#define CONFIG_SYS_MICRON_EM3		0x01030000
+#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
+#define CONFIG_SYS_MICRON_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#undef CONFIG_BKUP_FLASH
+#define CONFIG_SYS_FLASH_CFI				/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#ifdef CONFIG_BKUP_FLASH
+#define CONFIG_SYS_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* max flash size in bytes */
+#else
+#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of FLASH   */
+#define CONFIG_SYS_FLASH_SIZE		0x04000000	/* max flash size in bytes */
+#endif
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
+ * window is 64KB
+ */
+#define CONFIG_SYS_CPLD_BASE		0x82000000
+#define CONFIG_SYS_CPLD_SIZE		0x00010000	/* 64 KB */
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+#define CONFIG_SYS_CS0_CFG		0x05059310	/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS2_CFG		0x05059010	/* ALE active low, data size 1byte */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005	/* Use alternative CS timing for CS0 and CS2 */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE		/* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_SRAM_SIZE		/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100			/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+/*
+ * General PCI
+ */
+#define CONFIG_SYS_PCI_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
+
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#endif
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* 32-Byte Page Write Mode */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the Flash sector size */
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE		0x2000
+#ifdef CONFIG_BKUP_FLASH
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
+#else
+#define CONFIG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
+#endif
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_EXT2
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+	#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
+#else
+	#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#endif
+
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		mpc5121ads
+#define CONFIG_BOOTFILE		mpc5121ads/uImage
+#define CONFIG_ROOTPATH		/opt/eldk/ppc_6xx
+
+#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFC40000\0"					\
+	"fdt_addr=FFEC0000\0"						\
+	"ramdisk_addr=FC040000\0"					\
+	"ramdiskfile=mpc5121ads/uRamdisk\0"				\
+	"u-boot=mpc5121ads/u-boot.bin\0"				\
+	"bootfile=mpc5121ads/uImage\0"					\
+	"fdtfile=mpc5121ads/mpc5121ads.dtb\0"				\
+	"rootpath=/opt/eldk/ppc_6xx\n"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR		MPC512X_PATA
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 19dc7e179268be148e550c36203208c662610d76 Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Sat, 16 May 2009 10:47:42 +0200
Subject: MPC512x: add more hardware description to immap_512x.h

- add GPIO module description
- add Address Latch Timing Register description
- add IO Control Memory Map
- add FEC Memory Map

Also change board/freescale/mpc5121ads/mpc5121ads.c and
cpu/mpc512x/iopin.c as needed.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
---
 board/freescale/mpc5121ads/mpc5121ads.c |   2 +-
 cpu/mpc512x/iopin.c                     |   6 +-
 include/asm-ppc/immap_512x.h            | 253 +++++++++++++++++++++++++++++++-
 3 files changed, 252 insertions(+), 9 deletions(-)

(limited to 'include')

diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index e8eb491e3b4..4ff03cad982 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -134,7 +134,7 @@ long int fixed_sdram (void)
 	u32 i;
 
 	/* Initialize IO Control */
-	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
+	im->io_ctrl.io_control_mem = IOCTRL_MUX_DDR;
 
 	/* Initialize DDR Local Window */
 	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c
index 78f4fa1e8cc..befa586a3f0 100644
--- a/cpu/mpc512x/iopin.c
+++ b/cpu/mpc512x/iopin.c
@@ -23,15 +23,15 @@
 
 #include <common.h>
 #include <linux/types.h>
-#include <mpc512x.h>
+#include <asm/immap_512x.h>
 
 void iopin_initialize(iopin_t *ioregs_init, int len)
 {
 	short i, j, p;
-	u_long *reg;
+	u32 *reg;
 	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
-	reg = (u_long *)&(im->io_ctrl.regs[0]);
+	reg = (u32 *)&(im->io_ctrl);
 
 	if (sizeof(ioregs_init) == 0)
 		return;
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 808786985e5..bd40c04e143 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007-2009 DENX Software Engineering
  *
  * MPC512x Internal Memory Map
  *
@@ -151,7 +151,14 @@ typedef struct pmc512x {
  * General purpose I/O module
  */
 typedef struct gpio512x {
-	u8 fixme[0x100];
+	u32 gpdir;
+	u32 gpodr;
+	u32 gpdat;
+	u32 gpier;
+	u32 gpimr;
+	u32 gpicr1;
+	u32 gpicr2;
+	u8 res0[0xE4];
 } gpio512x_t;
 
 /*
@@ -380,7 +387,49 @@ typedef struct cfm512x {
  * FEC
  */
 typedef struct fec512x {
-	u8 fixme[0x800];
+	u32	fec_id;		/* FEC_ID register */
+	u32	ievent;		/* Interrupt event register */
+	u32	imask;		/* Interrupt mask register */
+	u32	reserved_01;
+	u32	r_des_active;	/* Receive ring updated flag */
+	u32	x_des_active;	/* Transmit ring updated flag */
+	u32	reserved_02[3];
+	u32	ecntrl;		/* Ethernet control register */
+	u32	reserved_03[6];
+	u32	mii_data;	/* MII data register */
+	u32	mii_speed;	/* MII speed register */
+	u32	reserved_04[7];
+	u32	mib_control;	/* MIB control/status register */
+	u32	reserved_05[7];
+	u32	r_cntrl;	/* Receive control register */
+	u32	r_hash;		/* Receive hash */
+	u32	reserved_06[14];
+	u32	x_cntrl;	/* Transmit control register */
+	u32	reserved_07[7];
+	u32	paddr1;		/* Physical address low */
+	u32	paddr2;		/* Physical address high + type field */
+	u32	op_pause;	/* Opcode + pause duration */
+	u32	reserved_08[10];
+	u32	iaddr1;		/* Upper 32 bits of individual hash table */
+	u32	iaddr2;		/* Lower 32 bits of individual hash table */
+	u32	gaddr1;		/* Upper 32 bits of group hash table */
+	u32	gaddr2;		/* Lower 32 bits of group hash table */
+	u32	reserved_09[7];
+	u32	x_wmrk;		/* Transmit FIFO watermark */
+	u32	reserved_10;
+	u32	r_bound;	/* End of RAM */
+	u32	r_fstart;	/* Receive FIFO start address */
+	u32	reserved_11[11];
+	u32	r_des_start;	/* Beginning of receive descriptor ring */
+	u32	x_des_start;	/* Pointer to beginning of transmit descriptor ring */
+	u32	r_buff_size;	/* Receive buffer size */
+	u32	reserved_12[26];
+	u32	dma_control;	/* DMA control for IP bus, AMBA IF + DMA revision */
+	u32	reserved_13[2];
+
+	u32	mib[128];	/* MIB Block Counters */
+
+	u32	fifo[256];	/*  used by FEC, can only be accessed by DMA */
 } fec512x_t;
 
 /*
@@ -408,7 +457,200 @@ typedef struct pcidma512x {
  * IO Control
  */
 typedef struct ioctrl512x {
-	u32 regs[0x400];
+	u32	io_control_mem;			/* MEM pad ctrl reg */
+	u32	io_control_gp;			/* GP pad ctrl reg */
+	u32	io_control_lpc_clk;		/* LPC_CLK pad ctrl reg */
+	u32	io_control_lpc_oe;		/* LPC_OE pad ctrl reg */
+	u32	io_control_lpc_rw;		/* LPC_R/W pad ctrl reg */
+	u32	io_control_lpc_ack;		/* LPC_ACK pad ctrl reg */
+	u32	io_control_lpc_cs0;		/* LPC_CS0 pad ctrl reg */
+	u32	io_control_nfc_ce0;		/* NFC_CE0 pad ctrl reg */
+	u32	io_control_lpc_cs1;		/* LPC_CS1 pad ctrl reg */
+	u32	io_control_lpc_cs2;		/* LPC_CS2 pad ctrl reg */
+	u32	io_control_lpc_ax03;		/* LPC_AX03 pad ctrl reg */
+	u32	io_control_emb_ax02;		/* EMB_AX02 pad ctrl reg */
+	u32	io_control_emb_ax01;		/* EMB_AX01 pad ctrl reg */
+	u32	io_control_emb_ax00;		/* EMB_AX00 pad ctrl reg */
+	u32	io_control_emb_ad31;		/* EMB_AD31 pad ctrl reg */
+	u32	io_control_emb_ad30;		/* EMB_AD30 pad ctrl reg */
+	u32	io_control_emb_ad29;		/* EMB_AD29 pad ctrl reg */
+	u32	io_control_emb_ad28;		/* EMB_AD28 pad ctrl reg */
+	u32	io_control_emb_ad27;		/* EMB_AD27 pad ctrl reg */
+	u32	io_control_emb_ad26;		/* EMB_AD26 pad ctrl reg */
+	u32	io_control_emb_ad25;		/* EMB_AD25 pad ctrl reg */
+	u32	io_control_emb_ad24;		/* EMB_AD24 pad ctrl reg */
+	u32	io_control_emb_ad23;		/* EMB_AD23 pad ctrl reg */
+	u32	io_control_emb_ad22;		/* EMB_AD22 pad ctrl reg */
+	u32	io_control_emb_ad21;		/* EMB_AD21 pad ctrl reg */
+	u32	io_control_emb_ad20;		/* EMB_AD20 pad ctrl reg */
+	u32	io_control_emb_ad19;		/* EMB_AD19 pad ctrl reg */
+	u32	io_control_emb_ad18;		/* EMB_AD18 pad ctrl reg */
+	u32	io_control_emb_ad17;		/* EMB_AD17 pad ctrl reg */
+	u32	io_control_emb_ad16;		/* EMB_AD16 pad ctrl reg */
+	u32	io_control_emb_ad15;		/* EMB_AD15 pad ctrl reg */
+	u32	io_control_emb_ad14;		/* EMB_AD14 pad ctrl reg */
+	u32	io_control_emb_ad13;		/* EMB_AD13 pad ctrl reg */
+	u32	io_control_emb_ad12;		/* EMB_AD12 pad ctrl reg */
+	u32	io_control_emb_ad11;		/* EMB_AD11 pad ctrl reg */
+	u32	io_control_emb_ad10;		/* EMB_AD10 pad ctrl reg */
+	u32	io_control_emb_ad09;		/* EMB_AD09 pad ctrl reg */
+	u32	io_control_emb_ad08;		/* EMB_AD08 pad ctrl reg */
+	u32	io_control_emb_ad07;		/* EMB_AD07 pad ctrl reg */
+	u32	io_control_emb_ad06;		/* EMB_AD06 pad ctrl reg */
+	u32	io_control_emb_ad05;		/* EMB_AD05 pad ctrl reg */
+	u32	io_control_emb_ad04;		/* EMB_AD04 pad ctrl reg */
+	u32	io_control_emb_ad03;		/* EMB_AD03 pad ctrl reg */
+	u32	io_control_emb_ad02;		/* EMB_AD02 pad ctrl reg */
+	u32	io_control_emb_ad01;		/* EMB_AD01 pad ctrl reg */
+	u32	io_control_emb_ad00;		/* EMB_AD00 pad ctrl reg */
+	u32	io_control_pata_ce1;		/* PATA_CE1 pad ctrl reg */
+	u32	io_control_pata_ce2;		/* PATA_CE2 pad ctrl reg */
+	u32	io_control_pata_isolate;	/* PATA_ISOLATE pad ctrl reg */
+	u32	io_control_pata_ior;		/* PATA_IOR pad ctrl reg */
+	u32	io_control_pata_iow;		/* PATA_IOW pad ctrl reg */
+	u32	io_control_pata_iochrdy;	/* PATA_IOCHRDY pad ctrl reg */
+	u32	io_control_pata_intrq;		/* PATA_INTRQ pad ctrl reg */
+	u32	io_control_pata_drq;		/* PATA_DRQ pad ctrl reg */
+	u32	io_control_pata_dack;		/* PATA_DACK pad ctrl reg */
+	u32	io_control_nfc_wp;		/* NFC_WP pad ctrl reg */
+	u32	io_control_nfc_rb;		/* NFC_RB pad ctrl reg */
+	u32	io_control_nfc_ale;		/* NFC_ALE pad ctrl reg */
+	u32	io_control_nfc_cle;		/* NFC_CLE pad ctrl reg */
+	u32	io_control_nfc_we;		/* NFC_WE pad ctrl reg */
+	u32	io_control_nfc_re;		/* NFC_RE pad ctrl reg */
+	u32	io_control_pci_ad31;		/* PCI_AD31 pad ctrl reg */
+	u32	io_control_pci_ad30;		/* PCI_AD30 pad ctrl reg */
+	u32	io_control_pci_ad29;		/* PCI_AD29 pad ctrl reg */
+	u32	io_control_pci_ad28;		/* PCI_AD28 pad ctrl reg */
+	u32	io_control_pci_ad27;		/* PCI_AD27 pad ctrl reg */
+	u32	io_control_pci_ad26;		/* PCI_AD26 pad ctrl reg */
+	u32	io_control_pci_ad25;		/* PCI_AD25 pad ctrl reg */
+	u32	io_control_pci_ad24;		/* PCI_AD24 pad ctrl reg */
+	u32	io_control_pci_ad23;		/* PCI_AD23 pad ctrl reg */
+	u32	io_control_pci_ad22;		/* PCI_AD22 pad ctrl reg */
+	u32	io_control_pci_ad21;		/* PCI_AD21 pad ctrl reg */
+	u32	io_control_pci_ad20;		/* PCI_AD20 pad ctrl reg */
+	u32	io_control_pci_ad19;		/* PCI_AD19 pad ctrl reg */
+	u32	io_control_pci_ad18;		/* PCI_AD18 pad ctrl reg */
+	u32	io_control_pci_ad17;		/* PCI_AD17 pad ctrl reg */
+	u32	io_control_pci_ad16;		/* PCI_AD16 pad ctrl reg */
+	u32	io_control_pci_ad15;		/* PCI_AD15 pad ctrl reg */
+	u32	io_control_pci_ad14;		/* PCI_AD14 pad ctrl reg */
+	u32	io_control_pci_ad13;		/* PCI_AD13 pad ctrl reg */
+	u32	io_control_pci_ad12;		/* PCI_AD12 pad ctrl reg */
+	u32	io_control_pci_ad11;		/* PCI_AD11 pad ctrl reg */
+	u32	io_control_pci_ad10;		/* PCI_AD10 pad ctrl reg */
+	u32	io_control_pci_ad09;		/* PCI_AD09 pad ctrl reg */
+	u32	io_control_pci_ad08;		/* PCI_AD08 pad ctrl reg */
+	u32	io_control_pci_ad07;		/* PCI_AD07 pad ctrl reg */
+	u32	io_control_pci_ad06;		/* PCI_AD06 pad ctrl reg */
+	u32	io_control_pci_ad05;		/* PCI_AD05 pad ctrl reg */
+	u32	io_control_pci_ad04;		/* PCI_AD04 pad ctrl reg */
+	u32	io_control_pci_ad03;		/* PCI_AD03 pad ctrl reg */
+	u32	io_control_pci_ad02;		/* PCI_AD02 pad ctrl reg */
+	u32	io_control_pci_ad01;		/* PCI_AD01 pad ctrl reg */
+	u32	io_control_pci_ad00;		/* PCI_AD00 pad ctrl reg */
+	u32	io_control_pci_cbe0;		/* PCI_CBE0 pad ctrl reg */
+	u32	io_control_pci_cbe1;		/* PCI_CBE1 pad ctrl reg */
+	u32	io_control_pci_cbe2;		/* PCI_CBE2 pad ctrl reg */
+	u32	io_control_pci_cbe3;		/* PCI_CBE3 pad ctrl reg */
+	u32	io_control_pci_grant2;		/* PCI_GRANT2 pad ctrl reg */
+	u32	io_control_pci_req2;		/* PCI_REQ2 pad ctrl reg */
+	u32	io_control_pci_grant1;		/* PCI_GRANT1 pad ctrl reg */
+	u32	io_control_pci_req1;		/* PCI_REQ1 pad ctrl reg */
+	u32	io_control_pci_grant0;		/* PCI_GRANT0 pad ctrl reg */
+	u32	io_control_pci_req0;		/* PCI_REQ0 pad ctrl reg */
+	u32	io_control_pci_inta;		/* PCI_INTA pad ctrl reg */
+	u32	io_control_pci_clk;		/* PCI_CLK pad ctrl reg */
+	u32	io_control_pci_rst;		/* PCI_RST- pad ctrl reg */
+	u32	io_control_pci_frame;		/* PCI_FRAME pad ctrl reg */
+	u32	io_control_pci_idsel;		/* PCI_IDSEL pad ctrl reg */
+	u32	io_control_pci_devsel;		/* PCI_DEVSEL pad ctrl reg */
+	u32	io_control_pci_irdy;		/* PCI_IRDY pad ctrl reg */
+	u32	io_control_pci_trdy;		/* PCI_TRDY pad ctrl reg */
+	u32	io_control_pci_stop;		/* PCI_STOP pad ctrl reg */
+	u32	io_control_pci_par;		/* PCI_PAR pad ctrl reg */
+	u32	io_control_pci_perr;		/* PCI_PERR pad ctrl reg */
+	u32	io_control_pci_serr;		/* PCI_SERR pad ctrl reg */
+	u32	io_control_spdif_txclk;		/* SPDIF_TXCLK pad ctrl reg */
+	u32	io_control_spdif_tx;		/* SPDIF_TX pad ctrl reg */
+	u32	io_control_spdif_rx;		/* SPDIF_RX pad ctrl reg */
+	u32	io_control_i2c0_scl;		/* I2C0_SCL pad ctrl reg */
+	u32	io_control_i2c0_sda;		/* I2C0_SDA pad ctrl reg */
+	u32	io_control_i2c1_scl;		/* I2C1_SCL pad ctrl reg */
+	u32	io_control_i2c1_sda;		/* I2C1_SDA pad ctrl reg */
+	u32	io_control_i2c2_scl;		/* I2C2_SCL pad ctrl reg */
+	u32	io_control_i2c2_sda;		/* I2C2_SDA pad ctrl reg */
+	u32	io_control_irq0;		/* IRQ0 pad ctrl reg */
+	u32	io_control_irq1;		/* IRQ1 pad ctrl reg */
+	u32	io_control_can1_tx;		/* CAN1_TX pad ctrl reg */
+	u32	io_control_can2_tx;		/* CAN2_TX pad ctrl reg */
+	u32	io_control_j1850_tx;		/* J1850_TX pad ctrl reg */
+	u32	io_control_j1850_rx;		/* J1850_RX pad ctrl reg */
+	u32	io_control_psc_mclk_in;		/* PSC_MCLK_IN pad ctrl reg */
+	u32	io_control_psc0_0;		/* PSC0_0 pad ctrl reg */
+	u32	io_control_psc0_1;		/* PSC0_1 pad ctrl reg */
+	u32	io_control_psc0_2;		/* PSC0_2 pad ctrl reg */
+	u32	io_control_psc0_3;		/* PSC0_3 pad ctrl reg */
+	u32	io_control_psc0_4;		/* PSC0_4 pad ctrl reg */
+	u32	io_control_psc1_0;		/* PSC1_0 pad ctrl reg */
+	u32	io_control_psc1_1;		/* PSC1_1 pad ctrl reg */
+	u32	io_control_psc1_2;		/* PSC1_2 pad ctrl reg */
+	u32	io_control_psc1_3;		/* PSC1_3 pad ctrl reg */
+	u32	io_control_psc1_4;		/* PSC1_4 pad ctrl reg */
+	u32	io_control_psc2_0;		/* PSC2_0 pad ctrl reg */
+	u32	io_control_psc2_1;		/* PSC2_1 pad ctrl reg */
+	u32	io_control_psc2_2;		/* PSC2_2 pad ctrl reg */
+	u32	io_control_psc2_3;		/* PSC2_3 pad ctrl reg */
+	u32	io_control_psc2_4;		/* PSC2_4 pad ctrl reg */
+	u32	io_control_psc3_0;		/* PSC3_0 pad ctrl reg */
+	u32	io_control_psc3_1;		/* PSC3_1 pad ctrl reg */
+	u32	io_control_psc3_2;		/* PSC3_2 pad ctrl reg */
+	u32	io_control_psc3_3;		/* PSC3_3 pad ctrl reg */
+	u32	io_control_psc3_4;		/* PSC3_4 pad ctrl reg */
+	u32	io_control_psc4_0;		/* PSC4_0 pad ctrl reg */
+	u32	io_control_psc4_1;		/* PSC4_1 pad ctrl reg */
+	u32	io_control_psc4_2;		/* PSC4_2 pad ctrl reg */
+	u32	io_control_psc4_3;		/* PSC4_3 pad ctrl reg */
+	u32	io_control_psc4_4;		/* PSC4_4 pad ctrl reg */
+	u32	io_control_psc5_0;		/* PSC5_0 pad ctrl reg */
+	u32	io_control_psc5_1;		/* PSC5_1 pad ctrl reg */
+	u32	io_control_psc5_2;		/* PSC5_2 pad ctrl reg */
+	u32	io_control_psc5_3;		/* PSC5_3 pad ctrl reg */
+	u32	io_control_psc5_4;		/* PSC5_4 pad ctrl reg */
+	u32	io_control_psc6_0;		/* PSC6_0 pad ctrl reg */
+	u32	io_control_psc6_1;		/* PSC6_1 pad ctrl reg */
+	u32	io_control_psc6_2;		/* PSC6_2 pad ctrl reg */
+	u32	io_control_psc6_3;		/* PSC6_3 pad ctrl reg */
+	u32	io_control_psc6_4;		/* PSC6_4 pad ctrl reg */
+	u32	io_control_psc7_0;		/* PSC7_0 pad ctrl reg */
+	u32	io_control_psc7_1;		/* PSC7_1 pad ctrl reg */
+	u32	io_control_psc7_2;		/* PSC7_2 pad ctrl reg */
+	u32	io_control_psc7_3;		/* PSC7_3 pad ctrl reg */
+	u32	io_control_psc7_4;		/* PSC7_4 pad ctrl reg */
+	u32	io_control_psc8_0;		/* PSC8_0 pad ctrl reg */
+	u32	io_control_psc8_1;		/* PSC8_1 pad ctrl reg */
+	u32	io_control_psc8_2;		/* PSC8_2 pad ctrl reg */
+	u32	io_control_psc8_3;		/* PSC8_3 pad ctrl reg */
+	u32	io_control_psc8_4;		/* PSC8_4 pad ctrl reg */
+	u32	io_control_psc9_0;		/* PSC9_0 pad ctrl reg */
+	u32	io_control_psc9_1;		/* PSC9_1 pad ctrl reg */
+	u32	io_control_psc9_2;		/* PSC9_2 pad ctrl reg */
+	u32	io_control_psc9_3;		/* PSC9_3 pad ctrl reg */
+	u32	io_control_psc9_4;		/* PSC9_4 pad ctrl reg */
+	u32	io_control_psc10_0;		/* PSC10_0 pad ctrl reg */
+	u32	io_control_psc10_1;		/* PSC10_1 pad ctrl reg */
+	u32	io_control_psc10_2;		/* PSC10_2 pad ctrl reg */
+	u32	io_control_psc10_3;		/* PSC10_3 pad ctrl reg */
+	u32	io_control_psc10_4;		/* PSC10_4 pad ctrl reg */
+	u32	io_control_psc11_0;		/* PSC11_0 pad ctrl reg */
+	u32	io_control_psc11_1;		/* PSC11_1 pad ctrl reg */
+	u32	io_control_psc11_2;		/* PSC11_2 pad ctrl reg */
+	u32	io_control_psc11_3;		/* PSC11_3 pad ctrl reg */
+	u32	io_control_psc11_4;		/* PSC11_4 pad ctrl reg */
+	u32	io_control_ckstp_out;		/* CKSTP_OUT pad ctrl reg */
+	u32	io_control_usb_phy_drvvbus;	/* USB2_DRVVBUS pad ctrl reg */
+	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
 } ioctrl512x_t;
 
 /*
@@ -447,7 +689,8 @@ typedef struct lpc512x {
 	u32	cs_bcr;		/* Chip Select Burst Control Register */
 	u32	cs_dccr;	/* Chip Select Deadcycle Control Register */
 	u32	cs_hccr;	/* Chip Select Holdcycle Control Register */
-	u8	res0[0xcc];
+	u32	altr;		/* Address Latch Timing Register */
+	u8	res0[0xc8];
 	u32	sclpc_psr;	/* SCLPC Packet Size Register */
 	u32	sclpc_sar;	/* SCLPC Start Address Register */
 	u32	sclpc_cr;	/* SCLPC Control Register */
-- 
cgit v1.3.1


From 3b74e7ec58e2cc352b0a396a614065cfeb8d138f Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Sat, 16 May 2009 10:47:45 +0200
Subject: MPC512x: remove include/mpc512x.h

Move needed definitions (register descriptions etc.) from
include/mpc512x.h  into  include/asm-ppc/immap_512x.h.

Instead of using a #define'd register offset, use a function that
provides the PATA controller's base address.

All the rest of include/mpc512x.h are register offset definitions
which can be eliminated by proper use of C structures.

There are only a few register offsets remaining that are needed in
cpu/mpc512x/start.S; for these we provide cpu/mpc512x/asm-offsets.h
which is intended as a temporary workaround only. In a later patch
this file will be removed, too, and then auto-generated from the
respective C structs.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
---
 common/cmd_ide.c             |   4 -
 cpu/mpc512x/asm-offsets.h    |  15 +
 cpu/mpc512x/cpu.c            |   1 -
 cpu/mpc512x/cpu_init.c       |   1 -
 cpu/mpc512x/i2c.c            |   1 -
 cpu/mpc512x/speed.c          |   1 -
 cpu/mpc512x/start.S          |   6 +-
 drivers/net/mpc512x_fec.c    |  52 ++--
 drivers/net/mpc512x_fec.h    |  27 +-
 include/asm-ppc/immap_512x.h | 324 +++++++++++++++++++-
 include/common.h             |   3 +-
 include/configs/mpc5121ads.h |   6 +-
 include/mpc512x.h            | 702 -------------------------------------------
 13 files changed, 383 insertions(+), 760 deletions(-)
 create mode 100644 cpu/mpc512x/asm-offsets.h
 delete mode 100644 include/mpc512x.h

(limited to 'include')

diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index feda773beef..4d7a0ac9e46 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -45,10 +45,6 @@
 #include <mpc5xxx.h>
 #endif
 
-#ifdef CONFIG_MPC512X
-#include <mpc512x.h>
-#endif
-
 #include <ide.h>
 #include <ata.h>
 
diff --git a/cpu/mpc512x/asm-offsets.h b/cpu/mpc512x/asm-offsets.h
new file mode 100644
index 00000000000..4b147783fb3
--- /dev/null
+++ b/cpu/mpc512x/asm-offsets.h
@@ -0,0 +1,15 @@
+/*
+ * needed for cpu/mpc512x/start.S
+ *
+ * These should be auto-generated
+ */
+#define LPCS0AW			0x0024
+#define SRAMBAR			0x00C4
+#define SWCRR			0x0904
+#define LPC_OFFSET		0x10000
+#define CS0_CONFIG		0x00000
+#define CS_CTRL			0x00020
+#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
+
+#define EXC_OFF_SYS_RESET	0x0100
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c
index 8021bc15e39..42ccd81e769 100644
--- a/cpu/mpc512x/cpu.c
+++ b/cpu/mpc512x/cpu.c
@@ -29,7 +29,6 @@
 
 #include <common.h>
 #include <command.h>
-#include <mpc512x.h>
 #include <net.h>
 #include <netdev.h>
 #include <asm/processor.h>
diff --git a/cpu/mpc512x/cpu_init.c b/cpu/mpc512x/cpu_init.c
index 69ec8719957..fe6beaf84d2 100644
--- a/cpu/mpc512x/cpu_init.c
+++ b/cpu/mpc512x/cpu_init.c
@@ -25,7 +25,6 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 
diff --git a/cpu/mpc512x/i2c.c b/cpu/mpc512x/i2c.c
index 4a3f9a0873b..97bda0d84ec 100644
--- a/cpu/mpc512x/i2c.c
+++ b/cpu/mpc512x/i2c.c
@@ -30,7 +30,6 @@ DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_HARD_I2C
 
-#include <mpc512x.h>
 #include <i2c.h>
 
 /* by default set I2C bus 0 active */
diff --git a/cpu/mpc512x/speed.c b/cpu/mpc512x/speed.c
index 0fec00461cc..ce8d0949b2f 100644
--- a/cpu/mpc512x/speed.c
+++ b/cpu/mpc512x/speed.c
@@ -26,7 +26,6 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <command.h>
 #include <asm/io.h>
 #include <asm/processor.h>
diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S
index 360682dafcf..178e5d1b3c4 100644
--- a/cpu/mpc512x/start.S
+++ b/cpu/mpc512x/start.S
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 1998  Dan Malek <dmalek@jlc.net>
  * Copyright (C) 1999  Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
- * Copyright (C) 2000, 2001, 2002, 2007 Wolfgang Denk <wd@denx.de>
+ * Copyright (C) 2000-2009 Wolfgang Denk <wd@denx.de>
  * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
  *
  * See file CREDITS for list of people who contributed to this
@@ -30,12 +30,14 @@
  */
 
 #include <config.h>
-#include <mpc512x.h>
 #include <timestamp.h>
 #include <version.h>
 
 #define CONFIG_521X	1		/* needed for Linux kernel header files*/
 
+#include <asm/immap_512x.h>
+#include "asm-offsets.h"
+
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
diff --git a/drivers/net/mpc512x_fec.c b/drivers/net/mpc512x_fec.c
index 62931d1c998..fb2c19a71b8 100644
--- a/drivers/net/mpc512x_fec.c
+++ b/drivers/net/mpc512x_fec.c
@@ -7,7 +7,6 @@
  */
 
 #include <common.h>
-#include <mpc512x.h>
 #include <malloc.h>
 #include <net.h>
 #include <netdev.h>
@@ -27,11 +26,11 @@ DECLARE_GLOBAL_DATA_PTR;
 #endif
 
 #if (DEBUG & 0x40)
-static uint32 local_crc32(char *string, unsigned int crc_value, int len);
+static u32 local_crc32(char *string, unsigned int crc_value, int len);
 #endif
 
-int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
-int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
+int fec512x_miiphy_read(char *devname, u8 phyAddr, u8 regAddr, u16 * retVal);
+int fec512x_miiphy_write(char *devname, u8 phyAddr, u8 regAddr, u16 data);
 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
 
 static uchar rx_buff[FEC_BUFFER_SIZE];
@@ -41,9 +40,9 @@ static int rx_buff_idx = 0;
 #if (DEBUG & 0x2)
 static void mpc512x_fec_phydump (char *devname)
 {
-	uint16 phyStatus, i;
-	uint8 phyAddr = CONFIG_PHY_ADDR;
-	uint8 reg_mask[] = {
+	u16 phyStatus, i;
+	u8 phyAddr = CONFIG_PHY_ADDR;
+	u8 reg_mask[] = {
 		/* regs to print: 0...8, 21,27,31 */
 		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
 		0, 0, 0, 0,  0, 1, 0, 0,     0, 0, 0, 1,  0, 0, 0, 1,
@@ -68,7 +67,7 @@ static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
 	 */
 	for (ix = 0; ix < FEC_RBD_NUM; ix++) {
 		fec->bdBase->rbd[ix].dataPointer =
-				(uint32)&fec->bdBase->recv_frames[ix];
+				(u32)&fec->bdBase->recv_frames[ix];
 		fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
 		fec->bdBase->rbd[ix].dataLength = 0;
 	}
@@ -167,10 +166,10 @@ static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
 /********************************************************************/
 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
 {
-	uint8 currByte;			/* byte for which to compute the CRC */
+	u8 currByte;			/* byte for which to compute the CRC */
 	int byte;			/* loop - counter */
 	int bit;			/* loop - counter */
-	uint32 crc = 0xffffffff;	/* initial value */
+	u32 crc = 0xffffffff;		/* initial value */
 
 	/*
 	 * The algorithm used is the following:
@@ -257,8 +256,8 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 	out_be32(&fec->eth->r_buff_size, FEC_BUFFER_SIZE);
 
 	/* Setup BD base addresses */
-	out_be32(&fec->eth->r_des_start, (uint32)fec->bdBase->rbd);
-	out_be32(&fec->eth->x_des_start, (uint32)fec->bdBase->tbd);
+	out_be32(&fec->eth->r_des_start, (u32)fec->bdBase->rbd);
+	out_be32(&fec->eth->x_des_start, (u32)fec->bdBase->tbd);
 
 	/* DMA Control */
 	out_be32(&fec->eth->dma_control, 0xc0000000);
@@ -282,9 +281,9 @@ static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
 {
 	mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
-	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
+	const u8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 	int timeout = 1;
-	uint16 phyStatus;
+	u16 phyStatus;
 
 #if (DEBUG & 0x1)
 	printf ("mpc512x_fec_init_phy... Begin\n");
@@ -495,7 +494,7 @@ static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
 	 */
 	pTbd = &fec->bdBase->tbd[fec->tbdIndex];
 	pTbd->dataLength = data_length;
-	pTbd->dataPointer = (uint32)eth_data;
+	pTbd->dataPointer = (u32)eth_data;
 	pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
 	fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
 
@@ -581,7 +580,7 @@ static int mpc512x_fec_recv (struct eth_device *dev)
 				printf ("recv data length 0x%08x data hdr: ",
 					pRbd->dataLength);
 				for (i = 0; i < 14; i++)
-					printf ("%x ", *((uint8*)pRbd->dataPointer + i));
+					printf ("%x ", *((u8*)pRbd->dataPointer + i));
 				printf("\n");
 			}
 #endif
@@ -647,14 +646,15 @@ int mpc512x_fec_initialize (bd_t * bis)
 #endif
 
 	/* Clean up space FEC's MIB and FIFO RAM ...*/
-	memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
+	memset ((void *)&im->fec.mib,  0x00, sizeof(im->fec.mib));
+	memset ((void *)&im->fec.fifo, 0x00, sizeof(im->fec.fifo));
 
 	/*
 	 * Malloc space for BDs  (must be quad word-aligned)
 	 * this pointer is lost, so cannot be freed
 	 */
 	bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
-	fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
+	fec->bdBase = (mpc512x_buff_descs*)((u32)bd & 0xfffffff0);
 	memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
 
 	/*
@@ -691,12 +691,12 @@ int mpc512x_fec_initialize (bd_t * bis)
 
 /* MII-interface related functions */
 /********************************************************************/
-int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
+int fec512x_miiphy_read (char *devname, u8 phyAddr, u8 regAddr, u16 * retVal)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile fec512x_t *eth = &im->fec;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
+	u32 reg;		/* convenient holder for the PHY register */
+	u32 phy;		/* convenient holder for the PHY */
 	int timeout = 0xffff;
 
 	/*
@@ -732,18 +732,18 @@ int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * r
 	/*
 	 * it's now safe to read the PHY's register
 	 */
-	*retVal = (uint16) in_be32(&eth->mii_data);
+	*retVal = (u16) in_be32(&eth->mii_data);
 
 	return 0;
 }
 
 /********************************************************************/
-int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
+int fec512x_miiphy_write (char *devname, u8 phyAddr, u8 regAddr, u16 data)
 {
 	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile fec512x_t *eth = &im->fec;
-	uint32 reg;		/* convenient holder for the PHY register */
-	uint32 phy;		/* convenient holder for the PHY */
+	u32 reg;		/* convenient holder for the PHY register */
+	u32 phy;		/* convenient holder for the PHY */
 	int timeout = 0xffff;
 
 	reg = regAddr << FEC_MII_DATA_RA_SHIFT;
@@ -776,7 +776,7 @@ int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 da
 }
 
 #if (DEBUG & 0x40)
-static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
+static u32 local_crc32 (char *string, unsigned int crc_value, int len)
 {
 	int i;
 	char c;
diff --git a/drivers/net/mpc512x_fec.h b/drivers/net/mpc512x_fec.h
index f24f529a793..a083cca2f8b 100644
--- a/drivers/net/mpc512x_fec.h
+++ b/drivers/net/mpc512x_fec.h
@@ -9,23 +9,18 @@
 #define __MPC512X_FEC_H
 
 #include <common.h>
-#include <mpc512x.h>
-
-typedef unsigned long uint32;
-typedef unsigned short uint16;
-typedef unsigned char uint8;
 
 /* Receive & Transmit Buffer Descriptor definitions */
 typedef struct BufferDescriptor {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
+	u16 status;
+	u16 dataLength;
+	u32 dataPointer;
 } FEC_RBD;
 
 typedef struct {
-	uint16 status;
-	uint16 dataLength;
-	uint32 dataPointer;
+	u16 status;
+	u16 dataLength;
+	u32 dataPointer;
 } FEC_TBD;
 
 /* private structure */
@@ -46,7 +41,7 @@ typedef enum {
 #define FEC_BUFFER_SIZE		((FEC_MAX_FRAME_LEN + 0x10) & (~0xf))
 
 typedef struct {
-	uint8 frame[FEC_BUFFER_SIZE];
+	u8 frame[FEC_BUFFER_SIZE];
 } mpc512x_frame;
 
 typedef struct {
@@ -59,10 +54,10 @@ typedef struct {
 	volatile fec512x_t *eth;
 	xceiver_type xcv_type;		/* transceiver type */
 	mpc512x_buff_descs *bdBase;	/* BD rings and recv buffer */
-	uint16 rbdIndex;		/* next receive BD to read */
-	uint16 tbdIndex;		/* next transmit BD to send */
-	uint16 usedTbdIndex;		/* next transmit BD to clean */
-	uint16 cleanTbdNum;		/* the number of available transmit BDs */
+	u16 rbdIndex;			/* next receive BD to read */
+	u16 tbdIndex;			/* next transmit BD to send */
+	u16 usedTbdIndex;		/* next transmit BD to clean */
+	u16 cleanTbdNum;		/* the number of available transmit BDs */
 } mpc512x_fec_priv;
 
 /* RBD bits definitions */
diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index bd40c04e143..444e0288855 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -25,7 +25,28 @@
 #define __IMMAP_512x__
 
 #include <asm/types.h>
+#if defined(CONFIG_E300)
+#include <asm/e300.h>
+#endif
 
+/*
+ * System reset offset (PowerPC standard)
+ */
+#define EXC_OFF_SYS_RESET	0x0100
+#define	_START_OFFSET		EXC_OFF_SYS_RESET
+
+#define SPR_5121E		0x80180000
+
+/*
+ * IMMRBAR - Internal Memory Register Base Address
+ */
+#define CONFIG_DEFAULT_IMMR	0xFF400000	/* Default IMMR base address */
+#define IMMRBAR			0x0000		/* Register offset to immr */
+#define IMMRBAR_BASE_ADDR	0xFFF00000	/* Base address mask */
+#define IMMRBAR_RES		~(IMMRBAR_BASE_ADDR)
+
+
+#ifndef __ASSEMBLY__
 typedef struct law512x {
 	u32 bar;	/* Base Addr Register */
 	u32 ar;		/* Attributes Register */
@@ -60,6 +81,8 @@ typedef struct sysconf512x {
 	u8 res5[0xf8];
 } sysconf512x_t;
 
+#define LAWBAR_BAR	0xFFFFF000	/* Base address mask */
+
 /*
  * Watch Dog Timer (WDT) Registers
  */
@@ -124,6 +147,34 @@ typedef struct reset512x {
 	u8 res1[0xDC];
 } reset512x_t;
 
+/* RSR - Reset Status Register */
+#define RSR_SWSR	0x00002000	/* software soft reset */
+#define RSR_SWHR	0x00001000	/* software hard reset */
+#define RSR_JHRS	0x00000200	/* jtag hreset */
+#define RSR_JSRS	0x00000100	/* jtag sreset status */
+#define RSR_CSHR	0x00000010	/* checkstop reset status */
+#define RSR_SWRS	0x00000008	/* software watchdog reset status */
+#define RSR_BMRS	0x00000004	/* bus monitop reset status */
+#define RSR_SRS		0x00000002	/* soft reset status */
+#define RSR_HRS		0x00000001	/* hard reset status */
+#define RSR_RES		~(RSR_SWSR | RSR_SWHR |\
+			 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
+			 RSR_BMRS | RSR_SRS | RSR_HRS)
+
+/* RMR - Reset Mode Register */
+#define RMR_CSRE	0x00000001	/* checkstop reset enable */
+#define RMR_CSRE_SHIFT	0
+#define RMR_RES		(~(RMR_CSRE))
+
+/* RCR - Reset Control Register */
+#define RCR_SWHR	0x00000002	/* software hard reset */
+#define RCR_SWSR	0x00000001	/* software soft reset */
+#define RCR_RES		(~(RCR_SWHR | RCR_SWSR))
+
+/* RCER - Reset Control Enable Register */
+#define RCER_CRE	0x00000001	/* software hard reset */
+#define RCER_RES	(~(RCER_CRE))
+
 /*
  * Clock Module
  */
@@ -140,6 +191,56 @@ typedef struct clk512x {
 	u8 res1[0xa8];
 } clk512x_t;
 
+/* SPMR - System PLL Mode Register */
+#define SPMR_SPMF		0x0F000000
+#define SPMR_SPMF_SHIFT		24
+#define SPMR_CPMF		0x000F0000
+#define SPMR_CPMF_SHIFT		16
+
+/* System Clock Control Register 1 commands */
+#define CLOCK_SCCR1_CFG_EN		0x80000000
+#define CLOCK_SCCR1_LPC_EN		0x40000000
+#define CLOCK_SCCR1_NFC_EN		0x20000000
+#define CLOCK_SCCR1_PATA_EN		0x10000000
+#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
+#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
+#define CLOCK_SCCR1_SATA_EN		0x00004000
+#define CLOCK_SCCR1_FEC_EN		0x00002000
+#define CLOCK_SCCR1_TPR_EN		0x00001000
+#define CLOCK_SCCR1_PCI_EN		0x00000800
+#define CLOCK_SCCR1_DDR_EN		0x00000400
+
+/* System Clock Control Register 2 commands */
+#define CLOCK_SCCR2_DIU_EN		0x80000000
+#define CLOCK_SCCR2_AXE_EN		0x40000000
+#define CLOCK_SCCR2_MEM_EN		0x20000000
+#define CLOCK_SCCR2_USB2_EN		0x10000000
+#define CLOCK_SCCR2_USB1_EN		0x08000000
+#define CLOCK_SCCR2_I2C_EN		0x04000000
+#define CLOCK_SCCR2_BDLC_EN		0x02000000
+#define CLOCK_SCCR2_SDHC_EN		0x01000000
+#define CLOCK_SCCR2_SPDIF_EN		0x00800000
+#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
+#define CLOCK_SCCR2_MBX_EN		0x00200000
+#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
+#define CLOCK_SCCR2_IIM_EN		0x00080000
+
+/* SCFR1 System Clock Frequency Register 1 */
+#define SCFR1_IPS_DIV		0x3
+#define SCFR1_IPS_DIV_MASK	0x03800000
+#define SCFR1_IPS_DIV_SHIFT	23
+
+#define SCFR1_PCI_DIV		0x6
+#define SCFR1_PCI_DIV_MASK	0x00700000
+#define SCFR1_PCI_DIV_SHIFT	20
+
+/* SCFR2 System Clock Frequency Register 2 */
+#define SCFR2_SYS_DIV		0xFC000000
+#define SCFR2_SYS_DIV_SHIFT	26
+
+/* SPCR - System Priority Configuration Register */
+#define SPCR_TBEN	0x00400000	/* E300 core time base unit enable */
+
 /*
  * Power Management Control Module
  */
@@ -266,6 +367,40 @@ typedef struct pci_outbound_window {
 	u8 res2[4];
 } pot512x_t;
 
+/* POTAR - PCI Outbound Translation Address Register */
+#define POTAR_TA_MASK	0x000fffff
+
+/* POBAR - PCI Outbound Base Address Register */
+#define POBAR_BA_MASK	0x000fffff
+
+/* POCMR - PCI Outbound Comparision Mask Register */
+#define POCMR_EN	0x80000000
+#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
+#define POCMR_PRE	0x20000000	/* prefetch enable */
+#define POCMR_SBS	0x00100000	/* special byte swap enable */
+#define POCMR_CM_MASK	0x000fffff
+#define POCMR_CM_4G	0x00000000
+#define POCMR_CM_2G	0x00080000
+#define POCMR_CM_1G	0x000C0000
+#define POCMR_CM_512M	0x000E0000
+#define POCMR_CM_256M	0x000F0000
+#define POCMR_CM_128M	0x000F8000
+#define POCMR_CM_64M	0x000FC000
+#define POCMR_CM_32M	0x000FE000
+#define POCMR_CM_16M	0x000FF000
+#define POCMR_CM_8M	0x000FF800
+#define POCMR_CM_4M	0x000FFC00
+#define POCMR_CM_2M	0x000FFE00
+#define POCMR_CM_1M	0x000FFF00
+#define POCMR_CM_512K	0x000FFF80
+#define POCMR_CM_256K	0x000FFFC0
+#define POCMR_CM_128K	0x000FFFE0
+#define POCMR_CM_64K	0x000FFFF0
+#define POCMR_CM_32K	0x000FFFF8
+#define POCMR_CM_16K	0x000FFFFC
+#define POCMR_CM_8K	0x000FFFFE
+#define POCMR_CM_4K	0x000FFFFF
+
 /*
  * Sequencer
  */
@@ -315,6 +450,27 @@ typedef struct pcictrl512x {
 } pcictrl512x_t;
 
 
+/* PITAR - PCI Inbound Translation Address Register
+ */
+#define PITAR_TA_MASK	0x000fffff
+
+/* PIBAR - PCI Inbound Base/Extended Address Register
+ */
+#define PIBAR_MASK	0xffffffff
+#define PIEBAR_EBA_MASK	0x000fffff
+
+/* PIWAR - PCI Inbound Windows Attributes Register
+ */
+#define PIWAR_EN	0x80000000
+#define PIWAR_SBS	0x40000000
+#define PIWAR_PF	0x20000000
+#define PIWAR_RTT_MASK	0x000f0000
+#define PIWAR_RTT_NO_SNOOP 0x00040000
+#define PIWAR_RTT_SNOOP	0x00050000
+#define PIWAR_WTT_MASK	0x0000f000
+#define PIWAR_WTT_NO_SNOOP 0x00004000
+#define PIWAR_WTT_SNOOP	0x00005000
+
 /*
  * MSCAN
  */
@@ -355,13 +511,34 @@ typedef struct i2c512x_dev {
 	u8 res0[0x0C];
 } i2c512x_dev_t;
 
+/* Number of I2C buses */
+#define I2C_BUS_CNT	3
+
 typedef struct i2c512x {
-	i2c512x_dev_t dev[3];
+	i2c512x_dev_t dev[I2C_BUS_CNT];
 	volatile u32 icr;
 	volatile u32 mifr;
 	u8 res0[0x98];
 } i2c512x_t;
 
+/* I2Cn control register bits */
+#define I2C_EN		0x80
+#define I2C_IEN		0x40
+#define I2C_STA		0x20
+#define I2C_TX		0x10
+#define I2C_TXAK	0x08
+#define I2C_RSTA	0x04
+#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
+
+/* I2Cn status register bits */
+#define I2C_CF		0x80
+#define I2C_AAS		0x40
+#define I2C_BB		0x20
+#define I2C_AL		0x10
+#define I2C_SRW		0x04
+#define I2C_IF		0x02
+#define I2C_RXAK	0x01
+
 /*
  * AXE
  */
@@ -653,6 +830,27 @@ typedef struct ioctrl512x {
 	u8	reserved[0x0cfc];		/* fill to 4096 bytes size */
 } ioctrl512x_t;
 
+/* Indexes in regs array */
+/* Set for DDR */
+#define IOCTRL_MUX_DDR		0x00000036
+
+/* IO pin fields */
+#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
+#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
+#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
+#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
+#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
+#define IO_PIN_DS(v)	((v))		/* slew rate */
+
+typedef struct iopin_t {
+	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
+	int nr_pins;		/* number of pins to set this way */
+	int bit_or;		/* or in the value instead of overwrite */
+	u_long val;		/* value to write or or */
+}iopin_t;
+
+void iopin_initialize(iopin_t *,int);
+
 /*
  * IIM
  */
@@ -834,6 +1032,51 @@ typedef struct psc512x {
 #define rfdata_32	rfdata_buffer.buffer_32
 } psc512x_t;
 
+/* PSC FIFO Command values */
+#define PSC_FIFO_RESET_SLICE		0x80
+#define PSC_FIFO_ENABLE_SLICE		0x01
+
+/* PSC FIFO Controller Command values */
+#define FIFOC_ENABLE_CLOCK_GATE		0x01
+#define FIFOC_DISABLE_CLOCK_GATE	0x00
+
+/* PSC FIFO status */
+#define PSC_FIFO_EMPTY			0x01
+
+/* PSC Command values */
+#define PSC_RX_ENABLE		0x01
+#define PSC_RX_DISABLE		0x02
+#define PSC_TX_ENABLE		0x04
+#define PSC_TX_DISABLE		0x08
+#define PSC_SEL_MODE_REG_1	0x10
+#define PSC_RST_RX		0x20
+#define PSC_RST_TX		0x30
+#define PSC_RST_ERR_STAT	0x40
+#define PSC_RST_BRK_CHG_INT	0x50
+#define PSC_START_BRK		0x60
+#define PSC_STOP_BRK		0x70
+
+/* PSC status register bits */
+#define PSC_SR_CDE		0x0080
+#define PSC_SR_TXEMP		0x0800
+#define PSC_SR_OE		0x1000
+#define PSC_SR_PE		0x2000
+#define PSC_SR_FE		0x4000
+#define PSC_SR_RB		0x8000
+
+/* PSC mode fields */
+#define PSC_MODE_5_BITS		0x00
+#define PSC_MODE_6_BITS		0x01
+#define PSC_MODE_7_BITS		0x02
+#define PSC_MODE_8_BITS		0x03
+#define PSC_MODE_PAREVEN	0x00
+#define PSC_MODE_PARODD		0x04
+#define PSC_MODE_PARFORCE	0x08
+#define PSC_MODE_PARNONE	0x10
+#define PSC_MODE_ENTIMEOUT	0x20
+#define PSC_MODE_RXRTS		0x80
+#define PSC_MODE_1_STOPBIT	0x07
+
 /*
  * FIFOC
  */
@@ -846,6 +1089,76 @@ typedef struct fifoc512x {
 	u8 fixme[0xEC];
 } fifoc512x_t;
 
+/*
+ * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
+ *
+ * NOTE: individual PSC units are free to use whatever area (and size) of the
+ * FIFOC internal memory, so make sure memory areas for FIFO slices used by
+ * different PSCs do not overlap!
+ *
+ * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
+ * tests indicate that it is 1024 words total.
+ */
+#define FIFOC_PSC0_TX_SIZE	0x0	/* number of 4-byte words for FIFO slice */
+#define FIFOC_PSC0_TX_ADDR	0x0
+#define FIFOC_PSC0_RX_SIZE	0x0
+#define FIFOC_PSC0_RX_ADDR	0x0
+
+#define FIFOC_PSC1_TX_SIZE	0x0
+#define FIFOC_PSC1_TX_ADDR	0x0
+#define FIFOC_PSC1_RX_SIZE	0x0
+#define FIFOC_PSC1_RX_ADDR	0x0
+
+#define FIFOC_PSC2_TX_SIZE	0x0
+#define FIFOC_PSC2_TX_ADDR	0x0
+#define FIFOC_PSC2_RX_SIZE	0x0
+#define FIFOC_PSC2_RX_ADDR	0x0
+
+#define FIFOC_PSC3_TX_SIZE	0x04
+#define FIFOC_PSC3_TX_ADDR	0x0
+#define FIFOC_PSC3_RX_SIZE	0x04
+#define FIFOC_PSC3_RX_ADDR	0x10
+
+#define FIFOC_PSC4_TX_SIZE	0x0
+#define FIFOC_PSC4_TX_ADDR	0x0
+#define FIFOC_PSC4_RX_SIZE	0x0
+#define FIFOC_PSC4_RX_ADDR	0x0
+
+#define FIFOC_PSC5_TX_SIZE	0x0
+#define FIFOC_PSC5_TX_ADDR	0x0
+#define FIFOC_PSC5_RX_SIZE	0x0
+#define FIFOC_PSC5_RX_ADDR	0x0
+
+#define FIFOC_PSC6_TX_SIZE	0x0
+#define FIFOC_PSC6_TX_ADDR	0x0
+#define FIFOC_PSC6_RX_SIZE	0x0
+#define FIFOC_PSC6_RX_ADDR	0x0
+
+#define FIFOC_PSC7_TX_SIZE	0x0
+#define FIFOC_PSC7_TX_ADDR	0x0
+#define FIFOC_PSC7_RX_SIZE	0x0
+#define FIFOC_PSC7_RX_ADDR	0x0
+
+#define FIFOC_PSC8_TX_SIZE	0x0
+#define FIFOC_PSC8_TX_ADDR	0x0
+#define FIFOC_PSC8_RX_SIZE	0x0
+#define FIFOC_PSC8_RX_ADDR	0x0
+
+#define FIFOC_PSC9_TX_SIZE	0x0
+#define FIFOC_PSC9_TX_ADDR	0x0
+#define FIFOC_PSC9_RX_SIZE	0x0
+#define FIFOC_PSC9_RX_ADDR	0x0
+
+#define FIFOC_PSC10_TX_SIZE	0x0
+#define FIFOC_PSC10_TX_ADDR	0x0
+#define FIFOC_PSC10_RX_SIZE	0x0
+#define FIFOC_PSC10_RX_ADDR	0x0
+
+#define FIFOC_PSC11_TX_SIZE	0x0
+#define FIFOC_PSC11_TX_ADDR	0x0
+#define FIFOC_PSC11_RX_SIZE	0x0
+#define FIFOC_PSC11_RX_ADDR	0x0
+
 /*
  * SATA
  */
@@ -903,4 +1216,13 @@ typedef struct immap {
 	sata512x_t		sata;		/* Serial ATA */
 	u8			res13[0xde000];
 } immap_t;
+
+/* provide interface to get PATA base address */
+static inline u32 get_pata_base (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	return (u32)(&im->pata);
+}
+#endif	/* __ASSEMBLY__ */
+
 #endif /* __IMMAP_512x__ */
diff --git a/include/common.h b/include/common.h
index df0f5a01e1a..4c004916855 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2007
+ * (C) Copyright 2000-2009
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -66,7 +66,6 @@ typedef volatile unsigned char	vu_char;
 #elif defined(CONFIG_MPC5xxx)
 #include <mpc5xxx.h>
 #elif defined(CONFIG_MPC512X)
-#include <mpc512x.h>
 #include <asm/immap_512x.h>
 #elif defined(CONFIG_MPC8220)
 #include <asm/immap_8220.h>
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index 9e3b0b7317d..dff7f1a4f12 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007, 2008 DENX Software Engineering
+ * (C) Copyright 2007-2009 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -519,7 +519,7 @@
 #define CONFIG_SYS_IDE_MAXDEVICE	2	/* max. 1 drive per IDE bus	*/
 
 #define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC512X_PATA
+#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
 
 /* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
 #define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
@@ -533,7 +533,7 @@
 /* Interval between registers	*/
 #define CONFIG_SYS_ATA_STRIDE		4
 
-#define ATA_BASE_ADDR		MPC512X_PATA
+#define ATA_BASE_ADDR			get_pata_base()
 
 /*
  * Control register bit definitions
diff --git a/include/mpc512x.h b/include/mpc512x.h
deleted file mode 100644
index 0f022939da6..00000000000
--- a/include/mpc512x.h
+++ /dev/null
@@ -1,702 +0,0 @@
-/*
- * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
- * (C) Copyright 2007 DENX Software Engineering
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * Derived from the MPC83xx header.
- */
-
-#ifndef __MPC512X_H__
-#define __MPC512X_H__
-
-#include <config.h>
-#if defined(CONFIG_E300)
-#include <asm/e300.h>
-#endif
-
-/* System reset offset (PowerPC standard)
- */
-#define EXC_OFF_SYS_RESET		0x0100
-#define	_START_OFFSET			EXC_OFF_SYS_RESET
-
-
-/* IMMRBAR - Internal Memory Register Base Address
- */
-#define CONFIG_DEFAULT_IMMR		0xFF400000	/* Default IMMR base address */
-#define IMMRBAR				0x0000		/* Register offset to immr */
-#define IMMRBAR_BASE_ADDR		0xFFF00000	/* Base address mask */
-#define IMMRBAR_RES			~(IMMRBAR_BASE_ADDR)
-
-/* LAWBAR - Local Access Window Base Address Register
- */
-#define LPBAW			0x0020		/* Register offset to immr */
-#define LPCS0AW			0x0024
-#define LPCS1AW			0x0028
-#define LPCS2AW			0x002C
-#define LPCS3AW			0x0030
-#define LPCS4AW			0x0034
-#define LPCS5AW			0x0038
-#define LPCS6AW			0x003C
-#define LPCA7AW			0x0040
-#define SRAMBAR			0x00C4
-#define LAWBAR_BAR		0xFFFFF000	/* Base address mask */
-
-#define LPC_OFFSET		0x10000
-
-#define CS0_CONFIG		0x00000
-#define CS1_CONFIG		0x00004
-#define CS2_CONFIG		0x00008
-#define CS3_CONFIG		0x0000C
-#define CS4_CONFIG		0x00010
-#define CS5_CONFIG		0x00014
-#define CS6_CONFIG		0x00018
-#define CS7_CONFIG		0x0001C
-#define CS_ALE_TIMING_CONFIG	0x00034
-
-#define CS_CTRL			0x00020
-#define CS_CTRL_ME		0x01000000	/* CS Master Enable bit */
-#define CS_CTRL_IE		0x08000000	/* CS Interrupt Enable bit */
-
-/* SPRIDR - System Part and Revision ID Register
- */
-#define SPRIDR_PARTID		0xFFFF0000	/* Part Identification */
-#define SPRIDR_REVID		0x0000FFFF	/* Revision Identification */
-
-#define SPR_5121E		0x80180000
-
-/* SPCR - System Priority Configuration Register
- */
-#define SPCR_PCIHPE			0x10000000	/* PCI Highest Priority Enable */
-#define SPCR_PCIHPE_SHIFT		(31-3)
-#define SPCR_PCIPR			0x03000000	/* PCI bridge system bus request priority */
-#define SPCR_PCIPR_SHIFT		(31-7)
-#define SPCR_TBEN			0x00400000	/* E300 PowerPC core time base unit enable */
-#define SPCR_TBEN_SHIFT			(31-9)
-#define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
-#define SPCR_COREPR_SHIFT		(31-11)
-
-/* SWCRR - System Watchdog Control Register
- */
-#define SWCRR				0x0904		/* Register offset to immr */
-#define SWCRR_SWTC			0xFFFF0000	/* Software Watchdog Time Count */
-#define SWCRR_SWEN			0x00000004	/* Watchdog Enable bit */
-#define SWCRR_SWRI			0x00000002	/* Software Watchdog Reset/Interrupt Select bit */
-#define SWCRR_SWPR			0x00000001	/* Software Watchdog Counter Prescale bit */
-#define SWCRR_RES			~(SWCRR_SWTC | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
-
-/* SWCNR - System Watchdog Counter Register
- */
-#define SWCNR				0x0908		/* Register offset to immr */
-#define SWCNR_SWCN			0x0000FFFF	/* Software Watchdog Count mask */
-#define SWCNR_RES			~(SWCNR_SWCN)
-
-/* SWSRR - System Watchdog Service Register
- */
-#define SWSRR				0x090E		/* Register offset to immr */
-
-/* ACR - Arbiter Configuration Register
- */
-#define ACR_COREDIS			0x10000000	/* Core disable */
-#define ACR_COREDIS_SHIFT		(31-7)
-#define ACR_PIPE_DEP			0x00070000	/* Pipeline depth */
-#define ACR_PIPE_DEP_SHIFT		(31-15)
-#define ACR_PCI_RPTCNT			0x00007000	/* PCI repeat count */
-#define ACR_PCI_RPTCNT_SHIFT		(31-19)
-#define ACR_RPTCNT			0x00000700	/* Repeat count */
-#define ACR_RPTCNT_SHIFT		(31-23)
-#define ACR_APARK			0x00000030	/* Address parking */
-#define ACR_APARK_SHIFT			(31-27)
-#define ACR_PARKM			0x0000000F	/* Parking master */
-#define ACR_PARKM_SHIFT			(31-31)
-
-/* ATR - Arbiter Timers Register
- */
-#define ATR_DTO				0x00FF0000	/* Data time out */
-#define ATR_ATO				0x000000FF	/* Address time out */
-
-/* AER - Arbiter Event Register
- */
-#define AER_ETEA			0x00000020	/* Transfer error */
-#define AER_RES				0x00000010	/* Reserved transfer type */
-#define AER_ECW				0x00000008	/* External control word transfer type */
-#define AER_AO				0x00000004	/* Address Only transfer type */
-#define AER_DTO				0x00000002	/* Data time out */
-#define AER_ATO				0x00000001	/* Address time out */
-
-/* AEATR - Arbiter Event Address Register
- */
-#define AEATR_EVENT			0x07000000	/* Event type */
-#define AEATR_MSTR_ID			0x001F0000	/* Master Id */
-#define AEATR_TBST			0x00000800	/* Transfer burst */
-#define AEATR_TSIZE			0x00000700	/* Transfer Size */
-#define AEATR_TTYPE			0x0000001F	/* Transfer Type */
-
-/* RSR - Reset Status Register
- */
-#define RSR_SWSR			0x00002000	/* software soft reset */
-#define RSR_SWSR_SHIFT			13
-#define RSR_SWHR			0x00001000	/* software hard reset */
-#define RSR_SWHR_SHIFT			12
-#define RSR_JHRS			0x00000200	/* jtag hreset */
-#define RSR_JHRS_SHIFT			9
-#define RSR_JSRS			0x00000100	/* jtag sreset status */
-#define RSR_JSRS_SHIFT			8
-#define RSR_CSHR			0x00000010	/* checkstop reset status */
-#define RSR_CSHR_SHIFT			4
-#define RSR_SWRS			0x00000008	/* software watchdog reset status */
-#define RSR_SWRS_SHIFT			3
-#define RSR_BMRS			0x00000004	/* bus monitop reset status */
-#define RSR_BMRS_SHIFT			2
-#define RSR_SRS				0x00000002	/* soft reset status */
-#define RSR_SRS_SHIFT			1
-#define RSR_HRS				0x00000001	/* hard reset status */
-#define RSR_HRS_SHIFT			0
-#define RSR_RES				~(RSR_SWSR | RSR_SWHR |\
-					 RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS |\
-					 RSR_BMRS | RSR_SRS | RSR_HRS)
-/* RMR - Reset Mode Register
- */
-#define RMR_CSRE			0x00000001	/* checkstop reset enable */
-#define RMR_CSRE_SHIFT			0
-#define RMR_RES				~(RMR_CSRE)
-
-/* RCR - Reset Control Register
- */
-#define RCR_SWHR			0x00000002	/* software hard reset */
-#define RCR_SWSR			0x00000001	/* software soft reset */
-#define RCR_RES				~(RCR_SWHR | RCR_SWSR)
-
-/* RCER - Reset Control Enable Register
- */
-#define RCER_CRE			0x00000001	/* software hard reset */
-#define RCER_RES			~(RCER_CRE)
-
-/* SPMR - System PLL Mode Register
- */
-#define SPMR_SPMF			0x0F000000
-#define SPMR_SPMF_SHIFT			24
-#define SPMR_CPMF			0x000F0000
-#define SPMR_CPMF_SHIFT			16
-
-/* SCFR1 System Clock Frequency Register 1
- */
-#define SCFR1_IPS_DIV			0x3
-#define SCFR1_IPS_DIV_MASK		0x03800000
-#define SCFR1_IPS_DIV_SHIFT		23
-
-#define SCFR1_PCI_DIV			0x6
-#define SCFR1_PCI_DIV_MASK		0x00700000
-#define SCFR1_PCI_DIV_SHIFT		20
-
-/* SCFR2 System Clock Frequency Register 2
- */
-#define SCFR2_SYS_DIV			0xFC000000
-#define SCFR2_SYS_DIV_SHIFT		26
-
-/* SCCR - System Clock Control Registers
- */
-
-/* System Clock Control Register 1 commands */
-#define CLOCK_SCCR1_CFG_EN		0x80000000
-#define CLOCK_SCCR1_LPC_EN		0x40000000
-#define CLOCK_SCCR1_NFC_EN		0x20000000
-#define CLOCK_SCCR1_PATA_EN		0x10000000
-#define CLOCK_SCCR1_PSC_EN(cn)		(0x08000000 >> (cn))
-#define CLOCK_SCCR1_PSCFIFO_EN		0x00008000
-#define CLOCK_SCCR1_SATA_EN		0x00004000
-#define CLOCK_SCCR1_FEC_EN		0x00002000
-#define CLOCK_SCCR1_TPR_EN		0x00001000
-#define CLOCK_SCCR1_PCI_EN		0x00000800
-#define CLOCK_SCCR1_DDR_EN		0x00000400
-
-/* System Clock Control Register 2 commands */
-#define CLOCK_SCCR2_DIU_EN		0x80000000
-#define CLOCK_SCCR2_AXE_EN		0x40000000
-#define CLOCK_SCCR2_MEM_EN		0x20000000
-#define CLOCK_SCCR2_USB2_EN		0x10000000
-#define CLOCK_SCCR2_USB1_EN		0x08000000
-#define CLOCK_SCCR2_I2C_EN		0x04000000
-#define CLOCK_SCCR2_BDLC_EN		0x02000000
-#define CLOCK_SCCR2_SDHC_EN		0x01000000
-#define CLOCK_SCCR2_SPDIF_EN		0x00800000
-#define CLOCK_SCCR2_MBX_BUS_EN		0x00400000
-#define CLOCK_SCCR2_MBX_EN		0x00200000
-#define CLOCK_SCCR2_MBX_3D_EN		0x00100000
-#define CLOCK_SCCR2_IIM_EN		0x00080000
-
-/* PSC FIFO Command values */
-#define PSC_FIFO_RESET_SLICE		0x80
-#define PSC_FIFO_ENABLE_SLICE		0x01
-
-/* PSC FIFO Controller Command values */
-#define FIFOC_ENABLE_CLOCK_GATE		0x01
-#define FIFOC_DISABLE_CLOCK_GATE	0x00
-
-/* PSC FIFO status */
-#define PSC_FIFO_EMPTY			0x01
-
-/* PSC Command values */
-#define PSC_RX_ENABLE		0x01
-#define PSC_RX_DISABLE		0x02
-#define PSC_TX_ENABLE		0x04
-#define PSC_TX_DISABLE		0x08
-#define PSC_SEL_MODE_REG_1	0x10
-#define PSC_RST_RX		0x20
-#define PSC_RST_TX		0x30
-#define PSC_RST_ERR_STAT	0x40
-#define PSC_RST_BRK_CHG_INT	0x50
-#define PSC_START_BRK		0x60
-#define PSC_STOP_BRK		0x70
-
-/* PSC status register bits */
-#define PSC_SR_CDE		0x0080
-#define PSC_SR_TXEMP		0x0800
-#define PSC_SR_OE		0x1000
-#define PSC_SR_PE		0x2000
-#define PSC_SR_FE		0x4000
-#define PSC_SR_RB		0x8000
-
-/* PSC mode fields */
-#define PSC_MODE_5_BITS		0x00
-#define PSC_MODE_6_BITS		0x01
-#define PSC_MODE_7_BITS		0x02
-#define PSC_MODE_8_BITS		0x03
-#define PSC_MODE_PAREVEN	0x00
-#define PSC_MODE_PARODD		0x04
-#define PSC_MODE_PARFORCE	0x08
-#define PSC_MODE_PARNONE	0x10
-#define PSC_MODE_ENTIMEOUT	0x20
-#define PSC_MODE_RXRTS		0x80
-#define PSC_MODE_1_STOPBIT	0x07
-
-/*
- * Centralized FIFO Controller has internal memory for all 12 PSCs FIFOs
- *
- * NOTE: individual PSC units are free to use whatever area (and size) of the
- * FIFOC internal memory, so make sure memory areas for FIFO slices used by
- * different PSCs do not overlap!
- *
- * Overall size of FIFOC memory is not documented in the MPC5121e RM, but
- * tests indicate that it is 1024 words total.
- */
-#define FIFOC_PSC0_TX_SIZE	0x0	/* number of 4-byte words for FIFO slice */
-#define FIFOC_PSC0_TX_ADDR	0x0
-#define FIFOC_PSC0_RX_SIZE	0x0
-#define FIFOC_PSC0_RX_ADDR	0x0
-
-#define FIFOC_PSC1_TX_SIZE	0x0
-#define FIFOC_PSC1_TX_ADDR	0x0
-#define FIFOC_PSC1_RX_SIZE	0x0
-#define FIFOC_PSC1_RX_ADDR	0x0
-
-#define FIFOC_PSC2_TX_SIZE	0x0
-#define FIFOC_PSC2_TX_ADDR	0x0
-#define FIFOC_PSC2_RX_SIZE	0x0
-#define FIFOC_PSC2_RX_ADDR	0x0
-
-#define FIFOC_PSC3_TX_SIZE	0x04
-#define FIFOC_PSC3_TX_ADDR	0x0
-#define FIFOC_PSC3_RX_SIZE	0x04
-#define FIFOC_PSC3_RX_ADDR	0x10
-
-#define FIFOC_PSC4_TX_SIZE	0x0
-#define FIFOC_PSC4_TX_ADDR	0x0
-#define FIFOC_PSC4_RX_SIZE	0x0
-#define FIFOC_PSC4_RX_ADDR	0x0
-
-#define FIFOC_PSC5_TX_SIZE	0x0
-#define FIFOC_PSC5_TX_ADDR	0x0
-#define FIFOC_PSC5_RX_SIZE	0x0
-#define FIFOC_PSC5_RX_ADDR	0x0
-
-#define FIFOC_PSC6_TX_SIZE	0x0
-#define FIFOC_PSC6_TX_ADDR	0x0
-#define FIFOC_PSC6_RX_SIZE	0x0
-#define FIFOC_PSC6_RX_ADDR	0x0
-
-#define FIFOC_PSC7_TX_SIZE	0x0
-#define FIFOC_PSC7_TX_ADDR	0x0
-#define FIFOC_PSC7_RX_SIZE	0x0
-#define FIFOC_PSC7_RX_ADDR	0x0
-
-#define FIFOC_PSC8_TX_SIZE	0x0
-#define FIFOC_PSC8_TX_ADDR	0x0
-#define FIFOC_PSC8_RX_SIZE	0x0
-#define FIFOC_PSC8_RX_ADDR	0x0
-
-#define FIFOC_PSC9_TX_SIZE	0x0
-#define FIFOC_PSC9_TX_ADDR	0x0
-#define FIFOC_PSC9_RX_SIZE	0x0
-#define FIFOC_PSC9_RX_ADDR	0x0
-
-#define FIFOC_PSC10_TX_SIZE	0x0
-#define FIFOC_PSC10_TX_ADDR	0x0
-#define FIFOC_PSC10_RX_SIZE	0x0
-#define FIFOC_PSC10_RX_ADDR	0x0
-
-#define FIFOC_PSC11_TX_SIZE	0x0
-#define FIFOC_PSC11_TX_ADDR	0x0
-#define FIFOC_PSC11_RX_SIZE	0x0
-#define FIFOC_PSC11_RX_ADDR	0x0
-
-/* IO Control Register
- */
-#define IOCTL_MEM		0x000
-#define IOCTL_GP		0x004
-#define IOCTL_LPC_CLK		0x008
-#define IOCTL_LPC_OE		0x00C
-#define IOCTL_LPC_RWB		0x010
-#define IOCTL_LPC_ACK		0x014
-#define IOCTL_LPC_CS0		0x018
-#define IOCTL_NFC_CE0		0x01C
-#define IOCTL_LPC_CS1		0x020
-#define IOCTL_LPC_CS2		0x024
-#define IOCTL_LPC_AX03		0x028
-#define IOCTL_EMB_AX02		0x02C
-#define IOCTL_EMB_AX01		0x030
-#define IOCTL_EMB_AX00		0x034
-#define IOCTL_EMB_AD31		0x038
-#define IOCTL_EMB_AD30		0x03C
-#define IOCTL_EMB_AD29		0x040
-#define IOCTL_EMB_AD28		0x044
-#define IOCTL_EMB_AD27		0x048
-#define IOCTL_EMB_AD26		0x04C
-#define IOCTL_EMB_AD25		0x050
-#define IOCTL_EMB_AD24		0x054
-#define IOCTL_EMB_AD23		0x058
-#define IOCTL_EMB_AD22		0x05C
-#define IOCTL_EMB_AD21		0x060
-#define IOCTL_EMB_AD20		0x064
-#define IOCTL_EMB_AD19		0x068
-#define IOCTL_EMB_AD18		0x06C
-#define IOCTL_EMB_AD17		0x070
-#define IOCTL_EMB_AD16		0x074
-#define IOCTL_EMB_AD15		0x078
-#define IOCTL_EMB_AD14		0x07C
-#define IOCTL_EMB_AD13		0x080
-#define IOCTL_EMB_AD12		0x084
-#define IOCTL_EMB_AD11		0x088
-#define IOCTL_EMB_AD10		0x08C
-#define IOCTL_EMB_AD09		0x090
-#define IOCTL_EMB_AD08		0x094
-#define IOCTL_EMB_AD07		0x098
-#define IOCTL_EMB_AD06		0x09C
-#define IOCTL_EMB_AD05		0x0A0
-#define IOCTL_EMB_AD04		0x0A4
-#define IOCTL_EMB_AD03		0x0A8
-#define IOCTL_EMB_AD02		0x0AC
-#define IOCTL_EMB_AD01		0x0B0
-#define IOCTL_EMB_AD00		0x0B4
-#define IOCTL_PATA_CE1		0x0B8
-#define IOCTL_PATA_CE2		0x0BC
-#define IOCTL_PATA_ISOLATE	0x0C0
-#define IOCTL_PATA_IOR		0x0C4
-#define IOCTL_PATA_IOW		0x0C8
-#define IOCTL_PATA_IOCHRDY	0x0CC
-#define IOCTL_PATA_INTRQ	0x0D0
-#define IOCTL_PATA_DRQ		0x0D4
-#define IOCTL_PATA_DACK		0x0D8
-#define IOCTL_NFC_WP		0x0DC
-#define IOCTL_NFC_RB		0x0E0
-#define IOCTL_NFC_ALE		0x0E4
-#define IOCTL_NFC_CLE		0x0E8
-#define IOCTL_NFC_WE		0x0EC
-#define IOCTL_NFC_RE		0x0F0
-#define IOCTL_PCI_AD31		0x0F4
-#define IOCTL_PCI_AD30		0x0F8
-#define IOCTL_PCI_AD29		0x0FC
-#define IOCTL_PCI_AD28		0x100
-#define IOCTL_PCI_AD27		0x104
-#define IOCTL_PCI_AD26		0x108
-#define IOCTL_PCI_AD25		0x10C
-#define IOCTL_PCI_AD24		0x110
-#define IOCTL_PCI_AD23		0x114
-#define IOCTL_PCI_AD22		0x118
-#define IOCTL_PCI_AD21		0x11C
-#define IOCTL_PCI_AD20		0x120
-#define IOCTL_PCI_AD19		0x124
-#define IOCTL_PCI_AD18		0x128
-#define IOCTL_PCI_AD17		0x12C
-#define IOCTL_PCI_AD16		0x130
-#define IOCTL_PCI_AD15		0x134
-#define IOCTL_PCI_AD14		0x138
-#define IOCTL_PCI_AD13		0x13C
-#define IOCTL_PCI_AD12		0x140
-#define IOCTL_PCI_AD11		0x144
-#define IOCTL_PCI_AD10		0x148
-#define IOCTL_PCI_AD09		0x14C
-#define IOCTL_PCI_AD08		0x150
-#define IOCTL_PCI_AD07		0x154
-#define IOCTL_PCI_AD06		0x158
-#define IOCTL_PCI_AD05		0x15C
-#define IOCTL_PCI_AD04		0x160
-#define IOCTL_PCI_AD03		0x164
-#define IOCTL_PCI_AD02		0x168
-#define IOCTL_PCI_AD01		0x16C
-#define IOCTL_PCI_AD00		0x170
-#define IOCTL_PCI_CBE0		0x174
-#define IOCTL_PCI_CBE1		0x178
-#define IOCTL_PCI_CBE2		0x17C
-#define IOCTL_PCI_CBE3		0x180
-#define IOCTL_PCI_GNT2		0x184
-#define IOCTL_PCI_REQ2		0x188
-#define IOCTL_PCI_GNT1		0x18C
-#define IOCTL_PCI_REQ1		0x190
-#define IOCTL_PCI_GNT0		0x194
-#define IOCTL_PCI_REQ0		0x198
-#define IOCTL_PCI_INTA		0x19C
-#define IOCTL_PCI_CLK		0x1A0
-#define IOCTL_PCI_RST_OUT	0x1A4
-#define IOCTL_PCI_FRAME		0x1A8
-#define IOCTL_PCI_IDSEL		0x1AC
-#define IOCTL_PCI_DEVSEL	0x1B0
-#define IOCTL_PCI_IRDY		0x1B4
-#define IOCTL_PCI_TRDY		0x1B8
-#define IOCTL_PCI_STOP		0x1BC
-#define IOCTL_PCI_PAR		0x1C0
-#define IOCTL_PCI_PERR		0x1C4
-#define IOCTL_PCI_SERR		0x1C8
-#define IOCTL_SPDIF_TXCLK	0x1CC
-#define IOCTL_SPDIF_TX		0x1D0
-#define IOCTL_SPDIF_RX		0x1D4
-#define IOCTL_I2C0_SCL		0x1D8
-#define IOCTL_I2C0_SDA		0x1DC
-#define IOCTL_I2C1_SCL		0x1E0
-#define IOCTL_I2C1_SDA		0x1E4
-#define IOCTL_I2C2_SCL		0x1E8
-#define IOCTL_I2C2_SDA		0x1EC
-#define IOCTL_IRQ0		0x1F0
-#define IOCTL_IRQ1		0x1F4
-#define IOCTL_CAN1_TX		0x1F8
-#define IOCTL_CAN2_TX		0x1FC
-#define IOCTL_J1850_TX		0x200
-#define IOCTL_J1850_RX		0x204
-#define IOCTL_PSC_MCLK_IN	0x208
-#define IOCTL_PSC0_0		0x20C
-#define IOCTL_PSC0_1		0x210
-#define IOCTL_PSC0_2		0x214
-#define IOCTL_PSC0_3		0x218
-#define IOCTL_PSC0_4		0x21C
-#define IOCTL_PSC1_0		0x220
-#define IOCTL_PSC1_1		0x224
-#define IOCTL_PSC1_2		0x228
-#define IOCTL_PSC1_3		0x22C
-#define IOCTL_PSC1_4		0x230
-#define IOCTL_PSC2_0		0x234
-#define IOCTL_PSC2_1		0x238
-#define IOCTL_PSC2_2		0x23C
-#define IOCTL_PSC2_3		0x240
-#define IOCTL_PSC2_4		0x244
-#define IOCTL_PSC3_0		0x248
-#define IOCTL_PSC3_1		0x24C
-#define IOCTL_PSC3_2		0x250
-#define IOCTL_PSC3_3		0x254
-#define IOCTL_PSC3_4		0x258
-#define IOCTL_PSC4_0		0x25C
-#define IOCTL_PSC4_1		0x260
-#define IOCTL_PSC4_2		0x264
-#define IOCTL_PSC4_3		0x268
-#define IOCTL_PSC4_4		0x26C
-#define IOCTL_PSC5_0		0x270
-#define IOCTL_PSC5_1		0x274
-#define IOCTL_PSC5_2		0x278
-#define IOCTL_PSC5_3		0x27C
-#define IOCTL_PSC5_4		0x280
-#define IOCTL_PSC6_0		0x284
-#define IOCTL_PSC6_1		0x288
-#define IOCTL_PSC6_2		0x28C
-#define IOCTL_PSC6_3		0x290
-#define IOCTL_PSC6_4		0x294
-#define IOCTL_PSC7_0		0x298
-#define IOCTL_PSC7_1		0x29C
-#define IOCTL_PSC7_2		0x2A0
-#define IOCTL_PSC7_3		0x2A4
-#define IOCTL_PSC7_4		0x2A8
-#define IOCTL_PSC8_0		0x2AC
-#define IOCTL_PSC8_1		0x2B0
-#define IOCTL_PSC8_2		0x2B4
-#define IOCTL_PSC8_3		0x2B8
-#define IOCTL_PSC8_4		0x2BC
-#define IOCTL_PSC9_0		0x2C0
-#define IOCTL_PSC9_1		0x2C4
-#define IOCTL_PSC9_2		0x2C8
-#define IOCTL_PSC9_3		0x2CC
-#define IOCTL_PSC9_4		0x2D0
-#define IOCTL_PSC10_0		0x2D4
-#define IOCTL_PSC10_1		0x2D8
-#define IOCTL_PSC10_2		0x2DC
-#define IOCTL_PSC10_3		0x2E0
-#define IOCTL_PSC10_4		0x2E4
-#define IOCTL_PSC11_0		0x2E8
-#define IOCTL_PSC11_1		0x2EC
-#define IOCTL_PSC11_2		0x2F0
-#define IOCTL_PSC11_3		0x2F4
-#define IOCTL_PSC11_4		0x2F8
-#define IOCTL_HRESET		0x2FC
-#define IOCTL_SRESET		0x300
-#define IOCTL_CKSTP_OUT		0x304
-#define IOCTL_USB2_VBUS_PWR_FAULT	0x308
-#define IOCTL_USB2_VBUS_PWR_SELECT	0x30C
-#define IOCTL_USB2_PHY_DRVV_BUS		0x310
-
-#ifndef __ASSEMBLY__
-
-
-/* IO pin fields */
-#define IO_PIN_FMUX(v)	((v) << 7)	/* pin function */
-#define IO_PIN_HOLD(v)	((v) << 5)	/* hold time, pci only */
-#define IO_PIN_PUD(v)	((v) << 4)	/* if PUE, 0=pull-down, 1=pull-up */
-#define IO_PIN_PUE(v)	((v) << 3)	/* pull up/down enable */
-#define IO_PIN_ST(v)	((v) << 2)	/* schmitt trigger */
-#define IO_PIN_DS(v)	((v))		/* slew rate */
-
-typedef struct iopin_t {
-	int p_offset;		/* offset from IOCTL_MEM_OFFSET */
-	int nr_pins;		/* number of pins to set this way */
-	int bit_or;		/* or in the value instead of overwrite */
-	u_long val;		/* value to write or or */
-}iopin_t;
-
-void iopin_initialize(iopin_t *,int);
-#endif
-
-/* Indexes in regs array */
-/* Set for DDR */
-#define IOCTRL_MUX_DDR		0x00000036
-
- /* Register Offset Base */
-#define MPC512X_FEC		(CONFIG_SYS_IMMR + 0x02800)
-#define MPC512X_PATA		(CONFIG_SYS_IMMR + 0x10200)
-
-/* IIM control */
-#define IIM_SET_UA(bk, f)	((bk << 3) | (f >> 5))
-#define IIM_SET_LA(f, bit)	(((f & 0x0000001f) << 3) | bit)
-#define IIM_STAT_BUSY		0x00000080
-#define IIM_STAT_PRGD		0x00000002
-#define IIM_STAT_SNSD		0x00000001
-#define IIM_ERR_WPE		0x00000040
-#define IIM_ERR_OPE		0x00000020
-#define IIM_ERR_RPE		0x00000010
-#define IIM_ERR_WLRE		0x00000008
-#define IIM_ERR_SNSE		0x00000004
-#define IIM_ERR_PARITYE		0x00000002
-#define IIM_PRG_P_SET		0x000000aa
-#define IIM_PRG_P_UNSET		0
-#define IIM_FCTL_PROG_PULSE	0x00000020
-#define IIM_FCTL_PROG		0x00000001
-#define IIM_FCTL_ESNS_N		0x00000008
-#define	IIM_FBAC_FBWP		0x00000080
-#define IIM_FBAC_FBOP		0x00000040
-#define IIM_FBAC_FBRP		0x00000020
-#define	IIM_FBAC_FBESP		0x00000008
-#define IIM_PROTECTION		0x000000e8
-#define IIM_FMAX			31
-
-/* Number of I2C buses */
-#define I2C_BUS_CNT	3
-
-/* I2Cn control register bits */
-#define I2C_EN		0x80
-#define I2C_IEN		0x40
-#define I2C_STA		0x20
-#define I2C_TX		0x10
-#define I2C_TXAK	0x08
-#define I2C_RSTA	0x04
-#define I2C_INIT_MASK	(I2C_EN | I2C_STA | I2C_TX | I2C_RSTA)
-
-/* I2Cn status register bits */
-#define I2C_CF		0x80
-#define I2C_AAS		0x40
-#define I2C_BB		0x20
-#define I2C_AL		0x10
-#define I2C_SRW		0x04
-#define I2C_IF		0x02
-#define I2C_RXAK	0x01
-
-/* POTAR - PCI Outbound Translation Address Register
- */
-#define POTAR_TA_MASK			0x000fffff
-
-/* POBAR - PCI Outbound Base Address Register
- */
-#define POBAR_BA_MASK			0x000fffff
-
-/* POCMR - PCI Outbound Comparision Mask Register
- */
-#define POCMR_EN	0x80000000
-#define POCMR_IO	0x40000000	/* 0-memory space 1-I/O space */
-#define POCMR_PRE	0x20000000	/* prefetch enable */
-#define POCMR_SBS	0x00100000	/* special byte swap enable */
-#define POCMR_CM_MASK	0x000fffff
-#define POCMR_CM_4G	0x00000000
-#define POCMR_CM_2G	0x00080000
-#define POCMR_CM_1G	0x000C0000
-#define POCMR_CM_512M	0x000E0000
-#define POCMR_CM_256M	0x000F0000
-#define POCMR_CM_128M	0x000F8000
-#define POCMR_CM_64M	0x000FC000
-#define POCMR_CM_32M	0x000FE000
-#define POCMR_CM_16M	0x000FF000
-#define POCMR_CM_8M	0x000FF800
-#define POCMR_CM_4M	0x000FFC00
-#define POCMR_CM_2M	0x000FFE00
-#define POCMR_CM_1M	0x000FFF00
-#define POCMR_CM_512K	0x000FFF80
-#define POCMR_CM_256K	0x000FFFC0
-#define POCMR_CM_128K	0x000FFFE0
-#define POCMR_CM_64K	0x000FFFF0
-#define POCMR_CM_32K	0x000FFFF8
-#define POCMR_CM_16K	0x000FFFFC
-#define POCMR_CM_8K	0x000FFFFE
-#define POCMR_CM_4K	0x000FFFFF
-
-/* PITAR - PCI Inbound Translation Address Register
- */
-#define PITAR_TA_MASK			0x000fffff
-
-/* PIBAR - PCI Inbound Base/Extended Address Register
- */
-#define PIBAR_MASK			0xffffffff
-#define PIEBAR_EBA_MASK			0x000fffff
-
-/* PIWAR - PCI Inbound Windows Attributes Register
- */
-#define PIWAR_EN			0x80000000
-#define PIWAR_SBS			0x40000000
-#define PIWAR_PF			0x20000000
-#define PIWAR_RTT_MASK			0x000f0000
-#define PIWAR_RTT_NO_SNOOP		0x00040000
-#define PIWAR_RTT_SNOOP			0x00050000
-#define PIWAR_WTT_MASK			0x0000f000
-#define PIWAR_WTT_NO_SNOOP		0x00004000
-#define PIWAR_WTT_SNOOP			0x00005000
-#define PIWAR_IWS_MASK			0x0000003F
-#define PIWAR_IWS_4K			0x0000000B
-#define PIWAR_IWS_8K			0x0000000C
-#define PIWAR_IWS_16K			0x0000000D
-#define PIWAR_IWS_32K			0x0000000E
-#define PIWAR_IWS_64K			0x0000000F
-#define PIWAR_IWS_128K			0x00000010
-#define PIWAR_IWS_256K			0x00000011
-#define PIWAR_IWS_512K			0x00000012
-#define PIWAR_IWS_1M			0x00000013
-#define PIWAR_IWS_2M			0x00000014
-#define PIWAR_IWS_4M			0x00000015
-#define PIWAR_IWS_8M			0x00000016
-#define PIWAR_IWS_16M			0x00000017
-#define PIWAR_IWS_32M			0x00000018
-#define PIWAR_IWS_64M			0x00000019
-#define PIWAR_IWS_128M			0x0000001A
-#define PIWAR_IWS_256M			0x0000001B
-#define PIWAR_IWS_512M			0x0000001C
-#define PIWAR_IWS_1G			0x0000001D
-#define PIWAR_IWS_2G			0x0000001E
-
-#endif	/* __MPC512X_H__ */
-- 
cgit v1.3.1


From 52568c3654b2b257016d52167805ae132faac14e Mon Sep 17 00:00:00 2001
From: Wolfgang Denk <wd@denx.de>
Date: Sat, 16 May 2009 10:47:46 +0200
Subject: MPC512x: add support for ARIA board

ARIA is a MPC5121E based COM Express module by Dave/DENX.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: John Rigby <jcrigby@gmail.com>
---
 MAINTAINERS                   |   2 +
 MAKEALL                       |   1 +
 Makefile                      |   4 +-
 board/davedenx/aria/Makefile  |  50 ++++
 board/davedenx/aria/aria.c    | 316 ++++++++++++++++++++++++
 board/davedenx/aria/config.mk |  23 ++
 include/configs/aria.h        | 554 ++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 949 insertions(+), 1 deletion(-)
 create mode 100644 board/davedenx/aria/Makefile
 create mode 100644 board/davedenx/aria/aria.c
 create mode 100644 board/davedenx/aria/config.mk
 create mode 100644 include/configs/aria.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index bf076b97152..bba6ce99421 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -75,6 +75,8 @@ Wolfgang Denk <wd@denx.de>
 	IceCube_5100	MGT5100
 	IceCube_5200	MPC5200
 
+	ARIA		MPC5121e
+
 	AMX860		MPC860
 	ETX094		MPC850
 	FPS850L		MPC850
diff --git a/MAKEALL b/MAKEALL
index 0e5f31531cb..fd312529b1c 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -77,6 +77,7 @@ LIST_5xxx="		\
 #########################################################################
 
 LIST_512x="		\
+	aria		\
 	mpc5121ads	\
 "
 
diff --git a/Makefile b/Makefile
index a43617e8ec1..3c9d8532924 100644
--- a/Makefile
+++ b/Makefile
@@ -821,6 +821,9 @@ v38b_config: unconfig
 ## MPC512x Systems
 #########################################################################
 
+aria_config:	unconfig
+	@$(MKCONFIG) -a aria ppc mpc512x aria davedenx
+
 mpc5121ads_config \
 mpc5121ads_rev2_config	\
 	: unconfig
@@ -830,7 +833,6 @@ mpc5121ads_rev2_config	\
 	fi
 	@$(MKCONFIG) -a mpc5121ads ppc mpc512x mpc5121ads freescale
 
-
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
diff --git a/board/davedenx/aria/Makefile b/board/davedenx/aria/Makefile
new file mode 100644
index 00000000000..2e3d73a3513
--- /dev/null
+++ b/board/davedenx/aria/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/davedenx/aria/aria.c b/board/davedenx/aria/aria.c
new file mode 100644
index 00000000000..f44c3524939
--- /dev/null
+++ b/board/davedenx/aria/aria.c
@@ -0,0 +1,316 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+#ifdef CONFIG_MISC_INIT_R
+#include <i2c.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int mpc5121_diu_init(void);
+extern void ide_set_reset(int idereset);
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_PATA_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN |		\
+			 CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN)
+
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+long int fixed_sdram(void);
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	/*
+	 * Initialize Local Window for the On Board FPGA access
+	 */
+	out_be32(&im->sysconf.lpcs2aw,
+		CSAW_START(CONFIG_SYS_ARIA_FPGA_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_FPGA_BASE, CONFIG_SYS_ARIA_FPGA_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	in_be32(&im->sysconf.lpcs2aw);
+	__asm__ __volatile__ ("isync");
+
+	/*
+	 * Initialize Local Window for the On Board SRAM access
+	 */
+	out_be32(&im->sysconf.lpcs6aw,
+		CSAW_START(CONFIG_SYS_ARIA_SRAM_BASE) |
+		CSAW_STOP(CONFIG_SYS_ARIA_SRAM_BASE, CONFIG_SYS_ARIA_SRAM_SIZE)
+	);
+	out_be32(&im->lpc.cs_cfg[6], CONFIG_SYS_CS6_CFG);
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	in_be32(&im->sysconf.lpcs6aw);
+	__asm__ __volatile__ ("isync");
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+
+	if (SVR_MJREV(spridr) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	return 0;
+}
+
+phys_size_t initdram (int board_type)
+{
+	return fixed_sdram();
+}
+
+/*
+ * fixed sdram init:
+ * The board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram (void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+	u32 i;
+
+	/* Initialize IO Control */
+	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+
+	/* Initialize DDR Local Window */
+	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+
+	/*
+	 * According to MPC5121e RM, configuring local access windows should
+	 * be followed by a dummy read of the config register that was
+	 * modified last and an isync
+	 */
+	in_be32(&im->sysconf.ddrlaw.ar);
+	__asm__ __volatile__ ("isync");
+
+	/* Enable DDR */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
+
+	/* Initialize DDR Priority Manager */
+	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+	/* Initialize MDDRC */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
+
+	/* Initialize DDR */
+	for (i = 0; i < 10; i++)
+		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	/* Start MDDRC */
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+
+	return msize;
+}
+
+int misc_init_r(void)
+{
+	u32 tmp;
+
+	/* we use I2C-2 for on-board eeprom */
+	i2c_set_bus_num(2);
+
+	tmp = in_be32((u32*)CONFIG_SYS_ARIA_FPGA_BASE);
+	printf("FPGA:  %u-%u.%u.%u\n",
+		(tmp & 0xFF000000) >> 24,
+		(tmp & 0x00FF0000) >> 16,
+		(tmp & 0x0000FF00) >>  8,
+		 tmp & 0x000000FF
+	);
+
+#ifdef CONFIG_FSL_DIU_FB
+# if	!(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
+	mpc5121_diu_init();
+# endif
+#endif
+	return 0;
+}
+
+static  iopin_t ioregs_init[] = {
+	/*
+	 * FEC
+	 */
+
+	/* FEC on PSCx_x*/
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 5, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_psc1_0), 10, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+
+	/*
+	 * DIU
+	 */
+	/* FUNC2=DIU CLK */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIU_HSYNC */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/*
+	 * On board SRAM
+	 */
+	/* FUNC2=/LPC CS6 */
+	{
+		offsetof(struct ioctrl512x, io_control_j1850_rx), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(1) | IO_PIN_ST(1) | IO_PIN_DS(3)
+	},
+};
+
+
+int checkboard (void)
+{
+	puts("Board: ARIA\n");
+
+	/* initialize function mux & slew rate IO inter alia on IO Pins  */
+
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/board/davedenx/aria/config.mk b/board/davedenx/aria/config.mk
new file mode 100644
index 00000000000..838a0184973
--- /dev/null
+++ b/board/davedenx/aria/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/include/configs/aria.h b/include/configs/aria.h
new file mode 100644
index 00000000000..58f67a4f0a1
--- /dev/null
+++ b/include/configs/aria.h
@@ -0,0 +1,554 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009, DAVE Srl <www.dave.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Aria board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_ARIA 1
+/*
+ * Memory map for the ARIA board:
+ *
+ * 0x0000_0000-0x0FFF_FFFF	DDR RAM (256 MB)
+ * 0x3000_0000-0x3001_FFFF	On Chip SRAM (128 KB)
+ * 0x3010_0000-0x3011_FFFF	On Board SRAM (128 KB) - CS6
+ * 0x3020_0000-0x3021_FFFF	FPGA (128 KB) - CS2
+ * 0x8000_0000-0x803F_FFFF	IMMR (4 MB)
+ * 0x8400_0000-0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000-0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000-0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
+ * 0xFC00_0000-0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+#define CONFIG_FSL_DIU_LOGO_BMP	1	/* Don't include FSL DIU binary bmp */
+
+/* video */
+#undef CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
+
+/* CONFIG_PCI is defined at config time */
+
+#define CONFIG_SYS_MPC512X_CLKIN	33000000	/* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR			0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		256		/* MB */
+#define CONFIG_SYS_DDR_BASE		0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
+/*#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168 */
+  #define CONFIG_SYS_MDDRC_TIME_CFG1	0x55D81189
+/*#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864 */
+  #define CONFIG_SYS_MDDRC_TIME_CFG2	0x34790863
+
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
+/*#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E */
+#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x030C3D2E
+
+#define CONFIG_SYS_MICRON_NOP		0x01380000
+#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EM2		0x01020000
+#define CONFIG_SYS_MICRON_EM3		0x01030000
+#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
+#define CONFIG_SYS_MICRON_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI				/* use the CFI code */
+#define CONFIG_FLASH_CFI_DRIVER				/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xF8000000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x08000000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* max sectors */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+#define CONFIG_SYS_ARIA_SRAM_BASE	0x30020000
+#define CONFIG_SYS_ARIA_SRAM_SIZE	0x20000		/* 128 KB */
+
+#define CONFIG_SYS_ARIA_FPGA_BASE	(CONFIG_SYS_ARIA_SRAM_BASE + \
+					 CONFIG_SYS_ARIA_SRAM_SIZE)
+#define CONFIG_SYS_ARIA_FPGA_SIZE	0x20000		/* 128 KB */
+
+#define CONFIG_SYS_CS0_CFG		0x05059150
+#define CONFIG_SYS_CS2_CFG		(	(5 << 24) | \
+						(5 << 16) | \
+						(1 << 15) | \
+						(0 << 14) | \
+						(0 << 13) | \
+						(1 << 12) | \
+						(0 << 10) | \
+						(3 <<  8) | /* 32 bit */ \
+						(0 <<  7) | \
+						(1 <<  6) | \
+						(1 <<  4) | \
+						(0 <<  3) | \
+						(0 <<  2) | \
+						(0 <<  1) | \
+						(0 <<  0)   \
+					)
+#define CONFIG_SYS_CS6_CFG		0x05059150
+
+/* Use alternative CS timing for CS0 and CS2 */
+#define CONFIG_SYS_CS_ALETIMING	0x00000005
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
+
+#ifdef	CONFIG_FSL_DIU_FB
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)
+#else
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+#endif
+
+/* FPGA */
+#define CONFIG_ARIA_FPGA		1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX		1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE		3	/* console on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+
+#define CONFIG_BAUDRATE			115200	/* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONSOLE_FIFO_TX_SIZE		FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR		FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE		FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR		FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING		1	/* command line history */
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#endif
+
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+#define CONFIG_SYS_PCI_MEM_BASE		0xA0000000
+#define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
+#define CONFIG_SYS_PCI_MEM_SIZE		0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_MMIO_BASE	(CONFIG_SYS_PCI_MEM_BASE + \
+					 CONFIG_SYS_PCI_MEM_SIZE)
+#define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
+#define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI_IO_BASE		0x00000000
+#define CONFIG_SYS_PCI_IO_PHYS		0x84000000
+#define CONFIG_SYS_PCI_IO_SIZE		0x01000000	/* 16M */
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+
+/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#if 0
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
+#endif
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
+ * EEPROM configuration for Atmel AT24C32A-10TQ-2.7:
+ * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC		1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR			0x17
+#define CONFIG_MII			1	/* MII PHY management */
+#define CONFIG_FEC_AN_TIMEOUT		1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+/* This has to be a multiple of the flash sector size */
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_MONITOR_BASE + \
+					 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_SECT_SIZE		0x20000	/* one sector (256K) */
+
+/* Address and size of Redundant Environment Sector	*/
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_ENV_ADDR + \
+					 CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO		1
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_FUSE
+#define CONFIG_CMD_I2C
+#undef CONFIG_CMD_IDE
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#endif
+
+#if defined(CONFIG_CMD_IDE)
+#define CONFIG_DOS_PARTITION
+#define CONFIG_MAC_PARTITION
+#define CONFIG_ISO_PARTITION
+#endif /* defined(CONFIG_CMD_IDE) */
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE
+ * is set to 0xFFFF, watchdog timeouts after about 64s. For details
+ * refer to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of 32 */
+#endif
+
+#define CONFIG_SYS_HID0_INIT		0x000000000
+#define CONFIG_SYS_HID0_FINAL		(HID0_ENABLE_MACHINE_CHECK | \
+					 HID0_ICE)
+#define CONFIG_SYS_HID2	HID2_HBE
+
+#define CONFIG_HIGH_BATS		1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD			0x01
+#define BOOTFLAG_WARM			0x02
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE		230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX		2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME			aria
+#define CONFIG_BOOTFILE			aria/uImage
+#define CONFIG_ROOTPATH			/opt/eldk/ppc_6xx
+
+#define CONFIG_LOADADDR			400000	/* default load addr */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE		115200
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFC40000\0"					\
+	"fdt_addr=FFEC0000\0"						\
+	"ramdisk_addr=FC040000\0"					\
+	"ramdiskfile=aria/uRamdisk\0"				\
+	"u-boot=aria/u-boot.bin\0"					\
+	"fdtfile=aria/aria.dtb\0"					\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff
+ *-----------------------------------------------------------------------
+ */
+
+#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for IDE not supported	*/
+
+#define CONFIG_IDE_RESET		/* reset for IDE supported	*/
+#define CONFIG_IDE_PREINIT
+
+#define CONFIG_SYS_IDE_MAXBUS		1	/* 1 IDE bus		*/
+#define CONFIG_SYS_IDE_MAXDEVICE	2	/* 1 drive per IDE bus	*/
+
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	get_pata_base()
+
+/* Offset for data I/O			RefMan MPC5121EE Table 28-10	*/
+#define CONFIG_SYS_ATA_DATA_OFFSET	(0x00A0)
+
+/* Offset for normal register accesses	*/
+#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
+
+/* Offset for alternate registers	RefMan MPC5121EE Table 28-23	*/
+#define CONFIG_SYS_ATA_ALT_OFFSET	(0x00D8)
+
+/* Interval between registers	*/
+#define CONFIG_SYS_ATA_STRIDE		4
+
+#define ATA_BASE_ADDR			get_pata_base()
+
+/*
+ * Control register bit definitions
+ */
+#define FSL_ATA_CTRL_FIFO_RST_B		0x80000000
+#define FSL_ATA_CTRL_ATA_RST_B		0x40000000
+#define FSL_ATA_CTRL_FIFO_TX_EN		0x20000000
+#define FSL_ATA_CTRL_FIFO_RCV_EN	0x10000000
+#define FSL_ATA_CTRL_DMA_PENDING	0x08000000
+#define FSL_ATA_CTRL_DMA_ULTRA		0x04000000
+#define FSL_ATA_CTRL_DMA_WRITE		0x02000000
+#define FSL_ATA_CTRL_IORDY_EN		0x01000000
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 0f898604945af4543c1525fc33b6bae621a3b805 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 22 May 2009 17:23:24 -0500
Subject: 83xx: Replace CONFIG_MPC83XX with CONFIG_MPC83xx

Use the standard lowercase "xx" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 api/api_platform-ppc.c                    | 2 +-
 board/freescale/mpc8349emds/mpc8349emds.c | 2 +-
 board/sbc8349/sbc8349.c                   | 2 +-
 common/fdt_support.c                      | 4 ++--
 cpu/mpc83xx/config.mk                     | 2 +-
 doc/README.mpc832xemds                    | 2 +-
 doc/README.mpc8349itx                     | 2 +-
 doc/README.mpc8360emds                    | 2 +-
 doc/README.mpc837xemds                    | 2 +-
 doc/README.mpc837xerdb                    | 2 +-
 include/asm-ppc/global_data.h             | 6 +++---
 include/asm-ppc/processor.h               | 4 ++--
 include/asm-ppc/u-boot.h                  | 2 +-
 include/common.h                          | 8 ++++----
 include/configs/MPC8313ERDB.h             | 2 +-
 include/configs/MPC8315ERDB.h             | 2 +-
 include/configs/MPC8323ERDB.h             | 2 +-
 include/configs/MPC832XEMDS.h             | 2 +-
 include/configs/MPC8349EMDS.h             | 2 +-
 include/configs/MPC8360EMDS.h             | 2 +-
 include/configs/MPC8360ERDK.h             | 2 +-
 include/configs/MPC837XEMDS.h             | 2 +-
 include/configs/MPC837XERDB.h             | 2 +-
 include/configs/MVBLM7.h                  | 2 +-
 include/configs/SIMPC8313.h               | 2 +-
 include/configs/TQM834x.h                 | 2 +-
 include/configs/kmeter1.h                 | 2 +-
 include/configs/sbc8349.h                 | 2 +-
 include/fdt_support.h                     | 2 +-
 include/tsec.h                            | 2 +-
 lib_ppc/board.c                           | 8 ++++----
 31 files changed, 41 insertions(+), 41 deletions(-)

(limited to 'include')

diff --git a/api/api_platform-ppc.c b/api/api_platform-ppc.c
index bfcc4175b61..a3d981f9e38 100644
--- a/api/api_platform-ppc.c
+++ b/api/api_platform-ppc.c
@@ -53,7 +53,7 @@ int platform_sys_info(struct sys_info *si)
 #define bi_bar	bi_immr_base
 #elif defined(CONFIG_MPC5xxx)
 #define bi_bar	bi_mbar_base
-#elif defined(CONFIG_MPC83XX)
+#elif defined(CONFIG_MPC83xx)
 #define bi_bar	bi_immrbar
 #elif defined(CONFIG_MPC8220)
 #define bi_bar	bi_mbar_base
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index 06064d97008..61d124960ff 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -38,7 +38,7 @@
 int fixed_sdram(void);
 void sdram_init(void);
 
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
 void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index e01cb037fd8..34861d4e157 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -39,7 +39,7 @@
 int fixed_sdram(void);
 void sdram_init(void);
 
-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
 void ddr_enable_ecc(unsigned int dram_size);
 #endif
 
diff --git a/common/fdt_support.c b/common/fdt_support.c
index b54f8868d9d..fc077e82927 100644
--- a/common/fdt_support.c
+++ b/common/fdt_support.c
@@ -495,7 +495,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
 }
 #endif /* CONFIG_HAS_FSL_DR_USB */
 
-#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
 /*
  * update crypto node properties to a specified revision of the SEC
  * called with sec_rev == 0 if not on an mpc8xxxE processor
@@ -580,7 +580,7 @@ void fdt_fixup_crypto_node(void *blob, int sec_rev)
 		printf("WARNING: could not set crypto property: %s\n",
 		       fdt_strerror(err));
 }
-#endif /* defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) */
+#endif /* defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) */
 
 /* Resize the fdt to its actual size + a bit of padding */
 int fdt_resize(void *blob)
diff --git a/cpu/mpc83xx/config.mk b/cpu/mpc83xx/config.mk
index 2f0f1ce1efb..d6194263be7 100644
--- a/cpu/mpc83xx/config.mk
+++ b/cpu/mpc83xx/config.mk
@@ -22,7 +22,7 @@
 
 PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
-PLATFORM_CPPFLAGS += -DCONFIG_MPC83XX -DCONFIG_E300 \
+PLATFORM_CPPFLAGS += -DCONFIG_MPC83xx -DCONFIG_E300 \
 			-ffixed-r2 -msoft-float
 
 # Use default linker script.  Board port can override in board/*/config.mk
diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds
index b63cc7912e9..9f7409cad95 100644
--- a/doc/README.mpc832xemds
+++ b/doc/README.mpc832xemds
@@ -83,7 +83,7 @@ Freescale MPC832XEMDS Board
 
 	include/configs/MPC832XEPB.h
 
-    CONFIG_MPC83XX	MPC83XX family for MPC8349, MPC8360 and MPC832X
+    CONFIG_MPC83xx	MPC83XX family for MPC8349, MPC8360 and MPC832X
     CONFIG_MPC832X	MPC832X specific
     CONFIG_MPC832XEMDS	MPC832XEMDS board specific
 
diff --git a/doc/README.mpc8349itx b/doc/README.mpc8349itx
index 7f24623f76f..48bbd50356e 100644
--- a/doc/README.mpc8349itx
+++ b/doc/README.mpc8349itx
@@ -88,7 +88,7 @@ Freescale MPC8349E-mITX and MPC8349E-mITX-GP Boards
 
 	include/configs/MPC8349ITX.h
 
-	CONFIG_MPC83XX		MPC83xx family
+	CONFIG_MPC83xx		MPC83xx family
 	CONFIG_MPC8349		MPC8349 specific
 	CONFIG_MPC8349ITX		MPC8349E-mITX
 	CONFIG_MPC8349ITXGP		MPC8349E-mITX-GP
diff --git a/doc/README.mpc8360emds b/doc/README.mpc8360emds
index 7c841cec06c..d65a2a48a9d 100644
--- a/doc/README.mpc8360emds
+++ b/doc/README.mpc8360emds
@@ -81,7 +81,7 @@ Freescale MPC8360EMDS Board
 
 	include/configs/MPC8360EMDS.h
 
-    CONFIG_MPC83XX	    MPC83xx family for both MPC8349 and MPC8360
+    CONFIG_MPC83xx	    MPC83xx family for both MPC8349 and MPC8360
     CONFIG_MPC8360	    MPC8360 specific
     CONFIG_MPC8360EMDS	    MPC8360EMDS board specific
 
diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds
index a14da0f0244..d8500c2d233 100644
--- a/doc/README.mpc837xemds
+++ b/doc/README.mpc837xemds
@@ -60,7 +60,7 @@ Freescale MPC837xEMDS Board
 
 	include/configs/MPC837XEMDS.h
 
-    CONFIG_MPC83XX	    MPC83xx family for both MPC837x and MPC8360
+    CONFIG_MPC83xx	    MPC83xx family for both MPC837x and MPC8360
     CONFIG_MPC837X	    MPC837x specific
     CONFIG_MPC837XEMDS	    MPC837XEMDS board specific
 
diff --git a/doc/README.mpc837xerdb b/doc/README.mpc837xerdb
index 510e3bb9b15..25ea65b118b 100644
--- a/doc/README.mpc837xerdb
+++ b/doc/README.mpc837xerdb
@@ -52,7 +52,7 @@ Freescale MPC837xE-RDB Board
 
 	include/configs/MPC837XERDB.h
 
-    CONFIG_MPC83XX	    MPC83xx family for both MPC8349 and MPC8360
+    CONFIG_MPC83xx	    MPC83xx family for both MPC8349 and MPC8360
     CONFIG_MPC837X	    MPC837x specific
     CONFIG_MPC837XERDB	    MPC837xE-RDB board specific
 
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index e5a3b2c170a..c188199ae64 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -56,7 +56,7 @@ typedef	struct	global_data {
 #endif
 #endif
 	unsigned long   mem_clk;
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
@@ -92,7 +92,7 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 lbc_clk;
 #endif /* CONFIG_MPC85xx || CONFIG_MPC86xx */
-#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 	u32 i2c1_clk;
 	u32 i2c2_clk;
 #endif
@@ -125,7 +125,7 @@ typedef	struct	global_data {
 	phys_size_t	ram_size;	/* RAM size */
 	unsigned long	reloc_off;	/* Relocation Offset */
 	unsigned long	reset_status;	/* reset status register at boot	*/
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 	unsigned long	arbiter_event_attributes;
 	unsigned long	arbiter_event_address;
 #endif
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 83e3581f39a..8f73c69e76f 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -923,7 +923,7 @@
 #if defined(CONFIG_MPC85xx)
 #define IS_E_PROCESSOR(svr)	(svr & 0x80000)
 #else
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 #define IS_E_PROCESSOR(spridr)	(!(spridr & 0x00010000))
 #endif
 #endif
@@ -1023,7 +1023,7 @@ struct cpu_type *identify_cpu(u32 ver);
 #define CPU_TYPE_ENTRY(n, v) \
 	{ .name = #n, .soc_ver = SVR_##v, }
 #else
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 #define CPU_TYPE_ENTRY(x) {#x, SPR_##x}
 #endif
 #endif
diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h
index e6c56e91bff..ea2d22df272 100644
--- a/include/asm-ppc/u-boot.h
+++ b/include/asm-ppc/u-boot.h
@@ -51,7 +51,7 @@ typedef struct bd_info {
 #if defined(CONFIG_MPC5xxx)
 	unsigned long	bi_mbar_base;	/* base of internal registers */
 #endif
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 	unsigned long	bi_immrbar;
 #endif
 #if defined(CONFIG_MPC8220)
diff --git a/include/common.h b/include/common.h
index 4c004916855..ff4f821dd25 100644
--- a/include/common.h
+++ b/include/common.h
@@ -89,7 +89,7 @@ typedef volatile unsigned char	vu_char;
 #include <mpc85xx.h>
 #include <asm/immap_85xx.h>
 #endif
-#ifdef CONFIG_MPC83XX
+#ifdef CONFIG_MPC83xx
 #include <mpc83xx.h>
 #include <asm/immap_83xx.h>
 #endif
@@ -412,7 +412,7 @@ void	trap_init     (ulong);
     defined (CONFIG_MPC8220)	|| \
     defined (CONFIG_MPC85xx)	|| \
     defined (CONFIG_MPC86xx)	|| \
-    defined (CONFIG_MPC83XX)
+    defined (CONFIG_MPC83xx)
 unsigned char	in8(unsigned int);
 void		out8(unsigned int, unsigned char);
 unsigned short	in16(unsigned int);
@@ -433,7 +433,7 @@ unsigned short	in16(unsigned int);
 void		out16(unsigned int, unsigned short value);
 #endif
 
-#if defined (CONFIG_MPC83XX)
+#if defined (CONFIG_MPC83xx)
 void		ppcDWload(unsigned int *addr, unsigned int *ret);
 void		ppcDWstore(unsigned int *addr, unsigned int *value);
 #endif
@@ -550,7 +550,7 @@ void	cpu_init_f    (void);
 int	cpu_init_r    (void);
 #if defined(CONFIG_8260)
 int	prt_8260_rsr  (void);
-#elif defined(CONFIG_MPC83XX)
+#elif defined(CONFIG_MPC83xx)
 int	prt_83xx_rsr  (void);
 #endif
 
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 52d27a1e404..f0592a80783 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -30,7 +30,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1
-#define CONFIG_MPC83XX		1
+#define CONFIG_MPC83xx		1
 #define CONFIG_MPC831X		1
 #define CONFIG_MPC8313		1
 #define CONFIG_MPC8313ERDB	1
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index 9fa91f4f6d5..b5f5a0bc91e 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -29,7 +29,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83XX		1 /* MPC83xx family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC831X		1 /* MPC831x CPU family */
 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 9b8b0333ed2..7d5bca664de 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -14,7 +14,7 @@
  */
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC83XX		1	/* MPC83xx family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC832X		1	/* MPC832x CPU specific */
 
 #define CONFIG_PCI		1
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index c82cda2dd01..6b3b1989a18 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -25,7 +25,7 @@
  */
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
-#define CONFIG_MPC83XX		1	/* MPC83xx family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC832X		1	/* MPC832x CPU specific */
 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 35ab88f080a..b970cc9605a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -33,7 +33,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834X		1	/* MPC834X family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 4b09de17fca..3497ba07e70 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -27,7 +27,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h
index 138750459d2..f5844356d2b 100644
--- a/include/configs/MPC8360ERDK.h
+++ b/include/configs/MPC8360ERDK.h
@@ -22,7 +22,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360ERDK	1 /* MPC8360ERDK board specific */
 
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index a62d805a9ae..8596470057b 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -25,7 +25,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC837X		1 /* MPC837X CPU specific */
 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 8d0c93b7158..5f2bd990716 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -26,7 +26,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC83xx		1 /* MPC83XX family */
 #define CONFIG_MPC837X		1 /* MPC837X CPU specific */
 #define CONFIG_MPC837XERDB	1
 
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index 9fd27e3d573..e6aba865b39 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -33,7 +33,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300	1
-#define CONFIG_MPC83XX	1
+#define CONFIG_MPC83xx	1
 #define CONFIG_MPC834X	1
 #define CONFIG_MPC8343	1
 
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 8d1e95b5539..995f9044c6f 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -32,7 +32,7 @@
 #define CONFIG_NAND_U_BOOT
 
 #define CONFIG_E300			1
-#define CONFIG_MPC83XX			1
+#define CONFIG_MPC83xx			1
 #define CONFIG_MPC831X			1
 #define CONFIG_MPC8313			1
 
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 70f222ca0f5..14e6c0f11f6 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -32,7 +32,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834X		1	/* MPC834X specific */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 61250adfed5..19da1337e7f 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -25,7 +25,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_QE		1 /* Has QE */
-#define CONFIG_MPC83XX		1 /* MPC83XX family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_KMETER1		1 /* KMETER1 board specific */
 #define CONFIG_HOSTNAME		kmeter1
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index b89fe12c566..7e31de68862 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -35,7 +35,7 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1	/* E300 Family */
-#define CONFIG_MPC83XX		1	/* MPC83XX family */
+#define CONFIG_MPC83xx		1	/* MPC83xx family */
 #define CONFIG_MPC834X		1	/* MPC834X family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
diff --git a/include/fdt_support.h b/include/fdt_support.h
index 6062df97642..16734c53528 100644
--- a/include/fdt_support.h
+++ b/include/fdt_support.h
@@ -59,7 +59,7 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd);
 static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
 #endif /* CONFIG_HAS_FSL_DR_USB */
 
-#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
 void fdt_fixup_crypto_node(void *blob, int sec_rev);
 #else
 static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
diff --git a/include/tsec.h b/include/tsec.h
index 7b52e06ab00..9184256b577 100644
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -28,7 +28,7 @@
 
 /* FIXME:  Should these be pushed back to 83xx and 85xx config files? */
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \
-	|| defined(CONFIG_MPC83XX)
+	|| defined(CONFIG_MPC83xx)
     #define TSEC_BASE_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #endif
 
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index e0d9ba4ef41..155171d6b12 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -321,7 +321,7 @@ init_fnc_t *init_sequence[] = {
 	prt_8260_rsr,
 	prt_8260_clks,
 #endif /* CONFIG_8260 */
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 	prt_83xx_rsr,
 #endif
 	checkcpu,
@@ -408,7 +408,7 @@ void board_init_f (ulong bootflag)
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) && \
+#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83xx) && \
     !defined(CONFIG_MPC85xx) && !defined(CONFIG_MPC86xx)
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
@@ -570,7 +570,7 @@ void board_init_f (ulong bootflag)
 #if defined(CONFIG_MPC5xxx)
 	bd->bi_mbar_base = CONFIG_SYS_MBAR;	/* base of internal registers */
 #endif
-#if defined(CONFIG_MPC83XX)
+#if defined(CONFIG_MPC83xx)
 	bd->bi_immrbar = CONFIG_SYS_IMMR;
 #endif
 #if defined(CONFIG_MPC8220)
@@ -750,7 +750,7 @@ void board_init_r (gd_t *id, ulong dest_addr)
 
 	WATCHDOG_RESET();
 
-#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83XX)
+#if defined(CONFIG_SYS_DELAYED_ICACHE) || defined(CONFIG_MPC83xx)
 	icache_enable ();	/* it's time to enable the instruction cache */
 #endif
 
-- 
cgit v1.3.1


From 2c7920afaf96d9779304202cd8a355b4f7576a83 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 22 May 2009 17:23:25 -0500
Subject: 83xx: Replace CONFIG_MPC83[0-9]X with MPC83[0-9]x

Use the standard lowercase "x" capitalization that other Freescale
architectures use for CPU defines to prevent confusion and errors

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 cpu/mpc83xx/cpu_init.c        |  2 +-
 cpu/mpc83xx/speed.c           | 66 +++++++++++++++++++++----------------------
 doc/README.mpc832xemds        |  6 ++--
 doc/README.mpc837xemds        |  2 +-
 doc/README.mpc837xerdb        |  2 +-
 drivers/pci/pci_auto.c        |  2 +-
 include/asm-ppc/fsl_lbc.h     |  4 +--
 include/asm-ppc/global_data.h | 12 ++++----
 include/asm-ppc/immap_83xx.h  |  6 ++--
 include/asm-ppc/immap_qe.h    |  2 +-
 include/asm-ppc/mpc8xxx_spi.h |  4 +--
 include/configs/MPC8313ERDB.h |  2 +-
 include/configs/MPC8315ERDB.h |  2 +-
 include/configs/MPC8323ERDB.h |  2 +-
 include/configs/MPC832XEMDS.h |  2 +-
 include/configs/MPC8349EMDS.h |  2 +-
 include/configs/MPC8349ITX.h  |  2 +-
 include/configs/MPC837XEMDS.h |  2 +-
 include/configs/MPC837XERDB.h |  4 +--
 include/configs/MVBLM7.h      |  2 +-
 include/configs/SIMPC8313.h   |  2 +-
 include/configs/TQM834x.h     |  2 +-
 include/configs/sbc8349.h     |  2 +-
 include/mpc83xx.h             | 36 +++++++++++------------
 24 files changed, 85 insertions(+), 85 deletions(-)

(limited to 'include')

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 8e9c875599e..d9b96b57fec 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -185,7 +185,7 @@ void cpu_init_f (volatile immap_t * im)
 
 	/* System General Purpose Register */
 #ifdef CONFIG_SYS_SICRH
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
 	/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
 	im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
 #else
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 95b558f926f..bde7e920a27 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -100,23 +100,23 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
 #endif
-#ifdef CONFIG_MPC834X
+#ifdef CONFIG_MPC834x
 	u32 usbmph_clk;
 #endif
 	u32 core_clk;
 	u32 i2c1_clk;
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	u32 i2c2_clk;
 #endif
 #if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	u32 sdhc_clk;
 #endif
 	u32 enc_clk;
@@ -126,17 +126,17 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	u32 mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	u32 qepmf;
 	u32 qepdf;
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
 #endif
 
@@ -164,7 +164,7 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -202,7 +202,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -229,7 +229,7 @@ int get_clocks(void)
 		tsec2_clk = 0;
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 	case 0:
 		usbmph_clk = 0;
@@ -274,7 +274,7 @@ int get_clocks(void)
 		return -7;
 	}
 
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
 	case 0:
 		sdhc_clk = 0;
@@ -313,22 +313,22 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	i2c1_clk = tsec2_clk;
 #elif defined(CONFIG_MPC8360)
 	i2c1_clk = csb_clk;
-#elif defined(CONFIG_MPC832X)
+#elif defined(CONFIG_MPC832x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831X)
+#elif defined(CONFIG_MPC831x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 	i2c1_clk = sdhc_clk;
 #endif
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 	case 0:
 		pciexp1_clk = 0;
@@ -366,7 +366,7 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 	case 0:
 		sata_clk = 0;
@@ -436,7 +436,7 @@ int get_clocks(void)
 		return -13;
 	}
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
 	qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
 	qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -444,23 +444,23 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	gd->usbmph_clk = usbmph_clk;
 #endif
 #if defined(CONFIG_MPC8315)
 	gd->tdm_clk = tdm_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	gd->sdhc_clk = sdhc_clk;
 #endif
 	gd->core_clk = core_clk;
 	gd->i2c1_clk = i2c1_clk;
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	gd->i2c2_clk = i2c2_clk;
 #endif
 	gd->enc_clk = enc_clk;
@@ -470,15 +470,15 @@ int get_clocks(void)
 #if defined(CONFIG_MPC8360)
 	gd->mem_sec_clk = mem_sec_clk;
 #endif
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	gd->pciexp1_clk = pciexp1_clk;
 	gd->pciexp2_clk = pciexp2_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	gd->sata_clk = sata_clk;
 #endif
 	gd->pci_clk = pci_sync_in;
@@ -504,7 +504,7 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 	printf("Clock configuration:\n");
 	printf("  Core:                %-4s MHz\n", strmhz(buf, gd->core_clk));
 	printf("  Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 	printf("  QE:                  %-4s MHz\n", strmhz(buf, gd->qe_clk));
 	printf("  BRG:                 %-4s MHz\n", strmhz(buf, gd->brg_clk));
 #endif
@@ -516,28 +516,28 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 #endif
 	printf("  SEC:                 %-4s MHz\n", strmhz(buf, gd->enc_clk));
 	printf("  I2C1:                %-4s MHz\n", strmhz(buf, gd->i2c1_clk));
-#if !defined(CONFIG_MPC832X)
+#if !defined(CONFIG_MPC832x)
 	printf("  I2C2:                %-4s MHz\n", strmhz(buf, gd->i2c2_clk));
 #endif
 #if defined(CONFIG_MPC8315)
 	printf("  TDM:                 %-4s MHz\n", strmhz(buf, gd->tdm_clk));
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
 #endif
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 	printf("  USB MPH:             %-4s MHz\n", strmhz(buf, gd->usbmph_clk));
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 	printf("  PCIEXP1:             %-4s MHz\n", strmhz(buf, gd->pciexp1_clk));
 	printf("  PCIEXP2:             %-4s MHz\n", strmhz(buf, gd->pciexp2_clk));
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	printf("  SATA:                %-4s MHz\n", strmhz(buf, gd->sata_clk));
 #endif
 	return 0;
diff --git a/doc/README.mpc832xemds b/doc/README.mpc832xemds
index 9f7409cad95..688bdbb201b 100644
--- a/doc/README.mpc832xemds
+++ b/doc/README.mpc832xemds
@@ -83,8 +83,8 @@ Freescale MPC832XEMDS Board
 
 	include/configs/MPC832XEPB.h
 
-    CONFIG_MPC83xx	MPC83XX family for MPC8349, MPC8360 and MPC832X
-    CONFIG_MPC832X	MPC832X specific
+    CONFIG_MPC83xx	MPC83xx family for MPC8349, MPC8360 and MPC832x
+    CONFIG_MPC832x	MPC832x specific
     CONFIG_MPC832XEMDS	MPC832XEMDS board specific
 
 4. Compilation
@@ -97,7 +97,7 @@ Freescale MPC832XEMDS Board
 		make MPC832XEMDS_config
 		make
 
-	MPC832X support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
+	MPC832x support PCI 33MHz and PCI 66MHz, to make u-boot support PCI:
 
 		1)Make sure the DIP SW support PCI mode as described in Section 1.1.
 
diff --git a/doc/README.mpc837xemds b/doc/README.mpc837xemds
index d8500c2d233..aa767ae7d84 100644
--- a/doc/README.mpc837xemds
+++ b/doc/README.mpc837xemds
@@ -61,7 +61,7 @@ Freescale MPC837xEMDS Board
 	include/configs/MPC837XEMDS.h
 
     CONFIG_MPC83xx	    MPC83xx family for both MPC837x and MPC8360
-    CONFIG_MPC837X	    MPC837x specific
+    CONFIG_MPC837x	    MPC837x specific
     CONFIG_MPC837XEMDS	    MPC837XEMDS board specific
 
 4. Compilation
diff --git a/doc/README.mpc837xerdb b/doc/README.mpc837xerdb
index 25ea65b118b..cfb6efa27e4 100644
--- a/doc/README.mpc837xerdb
+++ b/doc/README.mpc837xerdb
@@ -53,7 +53,7 @@ Freescale MPC837xE-RDB Board
 	include/configs/MPC837XERDB.h
 
     CONFIG_MPC83xx	    MPC83xx family for both MPC8349 and MPC8360
-    CONFIG_MPC837X	    MPC837x specific
+    CONFIG_MPC837x	    MPC837x specific
     CONFIG_MPC837XERDB	    MPC837xE-RDB board specific
 
 
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index c20b981b89c..35c82b97f15 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -403,7 +403,7 @@ int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
 		       PCI_DEV(dev));
 		break;
 #endif
-#ifdef CONFIG_MPC834X
+#ifdef CONFIG_MPC834x
 	case PCI_CLASS_BRIDGE_OTHER:
 		/*
 		 * The host/PCI bridge 1 seems broken in 8349 - it presents
diff --git a/include/asm-ppc/fsl_lbc.h b/include/asm-ppc/fsl_lbc.h
index bc1ebe6e312..a28082e56e6 100644
--- a/include/asm-ppc/fsl_lbc.h
+++ b/include/asm-ppc/fsl_lbc.h
@@ -54,7 +54,7 @@
 #define BR_MS_UPMA			0x00000080	/* UPMA */
 #define BR_MS_UPMB			0x000000A0	/* UPMB */
 #define BR_MS_UPMC			0x000000C0	/* UPMC */
-#if !defined(CONFIG_MPC834X)
+#if !defined(CONFIG_MPC834x)
 #define BR_ATOM				0x0000000C
 #define BR_ATOM_SHIFT			2
 #endif
@@ -65,7 +65,7 @@
 #define UPMB			1
 #define UPMC			2
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_V)
 #else
 #define BR_RES				~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V)
diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h
index c188199ae64..244c161580e 100644
--- a/include/asm-ppc/global_data.h
+++ b/include/asm-ppc/global_data.h
@@ -59,14 +59,14 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
 #endif
-#if defined (CONFIG_MPC834X)
+#if defined (CONFIG_MPC834x)
 	u32 usbmph_clk;
-#endif /* CONFIG_MPC834X */
+#endif /* CONFIG_MPC834x */
 #if defined(CONFIG_MPC8315)
 	u32 tdm_clk;
 #endif
@@ -75,18 +75,18 @@ typedef	struct	global_data {
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 pci_clk;
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC831X)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
 	u32 sata_clk;
 #endif
 #if defined(CONFIG_MPC8360)
 	u32  mem_sec_clk;
 #endif /* CONFIG_MPC8360 */
 #endif
-#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8536)
+#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8536)
 	u32 sdhc_clk;
 #endif
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 7b847f80225..1e67de6c918 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -656,7 +656,7 @@ typedef struct tdmdmac83xx {
 	u8 fixme[0x2000];
 } tdmdmac83xx_t;
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
@@ -773,7 +773,7 @@ typedef struct immap {
 	u8			res12[0x1CF00];
 } immap_t;
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
@@ -857,7 +857,7 @@ typedef struct immap {
 	u8			qe[0x100000];	/* QE block */
 } immap_t;
 
-#elif defined(CONFIG_MPC832X)
+#elif defined(CONFIG_MPC832x)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 55667ca8d5e..44c0c0aa12a 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -603,7 +603,7 @@ extern qe_map_t *qe_immr;
 #define QE_MURAM_SIZE		0x20000UL
 #elif defined(CONFIG_MPC8360)
 #define QE_MURAM_SIZE		0xc000UL
-#elif defined(CONFIG_MPC832X)
+#elif defined(CONFIG_MPC832x)
 #define QE_MURAM_SIZE		0x4000UL
 #endif
 
diff --git a/include/asm-ppc/mpc8xxx_spi.h b/include/asm-ppc/mpc8xxx_spi.h
index 48b15e4f33b..41737d3c694 100644
--- a/include/asm-ppc/mpc8xxx_spi.h
+++ b/include/asm-ppc/mpc8xxx_spi.h
@@ -27,10 +27,10 @@
 
 #include <asm/types.h>
 
-#if defined(CONFIG_MPC834X) || \
+#if defined(CONFIG_MPC834x) || \
 	defined(CONFIG_MPC8313) || \
 	defined(CONFIG_MPC8315) || \
-	defined(CONFIG_MPC837X)
+	defined(CONFIG_MPC837x)
 
 typedef struct spi8xxx {
 	u8 res0[0x20];	/* 0x0-0x01f reserved */
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index f0592a80783..2308568695a 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -31,7 +31,7 @@
  */
 #define CONFIG_E300		1
 #define CONFIG_MPC83xx		1
-#define CONFIG_MPC831X		1
+#define CONFIG_MPC831x		1
 #define CONFIG_MPC8313		1
 #define CONFIG_MPC8313ERDB	1
 
diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index b5f5a0bc91e..d9888f58c60 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -30,7 +30,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC831X		1 /* MPC831x CPU family */
+#define CONFIG_MPC831x		1 /* MPC831x CPU family */
 #define CONFIG_MPC8315		1 /* MPC8315 CPU specific */
 #define CONFIG_MPC8315ERDB	1 /* MPC8315ERDB board specific */
 
diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h
index 7d5bca664de..24f37e7cb2b 100644
--- a/include/configs/MPC8323ERDB.h
+++ b/include/configs/MPC8323ERDB.h
@@ -15,7 +15,7 @@
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
 #define CONFIG_MPC83xx		1	/* MPC83xx family */
-#define CONFIG_MPC832X		1	/* MPC832x CPU specific */
+#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
 
 #define CONFIG_PCI		1
 #define CONFIG_83XX_GENERIC_PCI	1
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index 6b3b1989a18..669577ef107 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -26,7 +26,7 @@
 #define CONFIG_E300		1	/* E300 family */
 #define CONFIG_QE		1	/* Has QE */
 #define CONFIG_MPC83xx		1	/* MPC83xx family */
-#define CONFIG_MPC832X		1	/* MPC832x CPU specific */
+#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
 #undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
 #undef CONFIG_PQ_MDS_PIB_ATM	/* QOC3 ATM card */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index b970cc9605a..ea5fbff305f 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -34,7 +34,7 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83xx		1	/* MPC83xx family */
-#define CONFIG_MPC834X		1	/* MPC834X family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_MPC8349EMDS	1	/* MPC8349EMDS board specific */
 
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index ef0a09fbd7f..f2e574b7375 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -63,7 +63,7 @@
 /*
  * High Level Configuration Options
  */
-#define CONFIG_MPC834X		/* MPC834x family (8343, 8347, 8349) */
+#define CONFIG_MPC834x		/* MPC834x family (8343, 8347, 8349) */
 #define CONFIG_MPC8349		/* MPC8349 specific */
 
 #define CONFIG_SYS_IMMR		0xE0000000	/* The IMMR is relocated to here */
diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h
index 8596470057b..4befcab4119 100644
--- a/include/configs/MPC837XEMDS.h
+++ b/include/configs/MPC837XEMDS.h
@@ -26,7 +26,7 @@
  */
 #define CONFIG_E300		1 /* E300 family */
 #define CONFIG_MPC83xx		1 /* MPC83xx family */
-#define CONFIG_MPC837X		1 /* MPC837X CPU specific */
+#define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XEMDS	1 /* MPC837XEMDS board specific */
 
 /*
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index 5f2bd990716..2b7d62954bc 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -26,8 +26,8 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83XX family */
-#define CONFIG_MPC837X		1 /* MPC837X CPU specific */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC837x		1 /* MPC837x CPU specific */
 #define CONFIG_MPC837XERDB	1
 
 #define CONFIG_PCI	1
diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h
index e6aba865b39..967520587ac 100644
--- a/include/configs/MVBLM7.h
+++ b/include/configs/MVBLM7.h
@@ -34,7 +34,7 @@
  */
 #define CONFIG_E300	1
 #define CONFIG_MPC83xx	1
-#define CONFIG_MPC834X	1
+#define CONFIG_MPC834x	1
 #define CONFIG_MPC8343	1
 
 #define CONFIG_SYS_IMMR		0xE0000000
diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h
index 995f9044c6f..72fe115886c 100644
--- a/include/configs/SIMPC8313.h
+++ b/include/configs/SIMPC8313.h
@@ -33,7 +33,7 @@
 
 #define CONFIG_E300			1
 #define CONFIG_MPC83xx			1
-#define CONFIG_MPC831X			1
+#define CONFIG_MPC831x			1
 #define CONFIG_MPC8313			1
 
 #define CONFIG_PCI
diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h
index 14e6c0f11f6..efade69ca21 100644
--- a/include/configs/TQM834x.h
+++ b/include/configs/TQM834x.h
@@ -33,7 +33,7 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83xx		1	/* MPC83xx family */
-#define CONFIG_MPC834X		1	/* MPC834X specific */
+#define CONFIG_MPC834x		1	/* MPC834x specific */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_TQM834X		1	/* TQM834X board specific */
 
diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h
index 7e31de68862..84a251a06aa 100644
--- a/include/configs/sbc8349.h
+++ b/include/configs/sbc8349.h
@@ -36,7 +36,7 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC83xx		1	/* MPC83xx family */
-#define CONFIG_MPC834X		1	/* MPC834X family */
+#define CONFIG_MPC834x		1	/* MPC834x family */
 #define CONFIG_MPC8349		1	/* MPC8349 specific */
 #define CONFIG_SBC8349		1	/* WRS SBC8349 board specific */
 
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index fab37516cf8..c5bd6cb16ab 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -54,7 +54,7 @@
 #define SPRIDR_PARTID			0xFFFF0000	/* Part Id */
 #define SPRIDR_REVID			0x0000FFFF	/* Revision Id */
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define REVID_MAJOR(spridr)		((spridr & 0x0000FF00) >> 8)
 #define REVID_MINOR(spridr)		(spridr & 0x000000FF)
 #else
@@ -100,7 +100,7 @@
 #define SPCR_COREPR			0x00300000	/* E300 PowerPC Core system bus request priority */
 #define SPCR_COREPR_SHIFT		(31-11)
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SPCR bits - MPC8349 specific */
 #define SPCR_TSEC1DP			0x00003000	/* TSEC1 data priority */
 #define SPCR_TSEC1DP_SHIFT		(31-19)
@@ -115,7 +115,7 @@
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
 
-#elif defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 /* SPCR bits - MPC831x and MPC837x specific */
 #define SPCR_TSECDP			0x00003000	/* TSEC data priority */
 #define SPCR_TSECDP_SHIFT		(31-19)
@@ -127,7 +127,7 @@
 
 /* SICRL/H - System I/O Configuration Register Low/High
  */
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SICRL bits - MPC8349 specific */
 #define SICRL_LDP_A			0x80000000
 #define SICRL_USB1			0x40000000
@@ -190,8 +190,8 @@
 #define SICRH_UC2E1OBI			0x00000002
 #define SICRH_UC2E2OBI			0x00000001
 
-#elif defined(CONFIG_MPC832X)
-/* SICRL bits - MPC832X specific */
+#elif defined(CONFIG_MPC832x)
+/* SICRL bits - MPC832x specific */
 #define SICRL_LDP_LCS_A			0x80000000
 #define SICRL_IRQ_CKS			0x20000000
 #define SICRL_PCI_MSRC			0x10000000
@@ -262,7 +262,7 @@
 #define SICRH_TSOBI1			0x00000002
 #define SICRH_TSOBI2			0x00000001
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 /* SICRL bits - MPC837x specific */
 #define SICRL_USB_A			0xC0000000
 #define SICRL_USB_B			0x30000000
@@ -424,7 +424,7 @@
 #define HRCWL_CORE_TO_CSB_2_5X1		0x00050000
 #define HRCWL_CORE_TO_CSB_3X1		0x00060000
 
-#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832x)
 #define HRCWL_CEVCOD			0x000000C0
 #define HRCWL_CEVCOD_SHIFT		6
 #define HRCWL_CE_PLL_VCO_DIV_4		0x00000000
@@ -478,7 +478,7 @@
 #define HRCWL_SVCOD_DIV_8		0x20000000
 #define HRCWL_SVCOD_DIV_1		0x30000000
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 #define HRCWL_SVCOD			0x30000000
 #define HRCWL_SVCOD_SHIFT		28
 #define HRCWL_SVCOD_DIV_4		0x00000000
@@ -493,7 +493,7 @@
 #define HRCWH_PCI_HOST_SHIFT		31
 #define HRCWH_PCI_AGENT			0x00000000
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_32_BIT_PCI		0x00000000
 #define HRCWH_64_BIT_PCI		0x40000000
 #endif
@@ -504,7 +504,7 @@
 #define HRCWH_PCI_ARBITER_DISABLE	0x00000000
 #define HRCWH_PCI_ARBITER_ENABLE	0x20000000
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_PCI2_ARBITER_DISABLE	0x00000000
 #define HRCWH_PCI2_ARBITER_ENABLE	0x10000000
 
@@ -528,17 +528,17 @@
 
 #define HRCWH_ROM_LOC_DDR_SDRAM		0x00000000
 #define HRCWH_ROM_LOC_PCI1		0x00100000
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_ROM_LOC_PCI2		0x00200000
 #endif
-#if defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_ON_CHIP_ROM	0x00300000
 #endif
 #define HRCWH_ROM_LOC_LOCAL_8BIT	0x00500000
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
-#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
@@ -562,7 +562,7 @@
 #define HRCWH_TSEC2M_IN_SGMII		0x00001800
 #endif
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 #define HRCWH_TSEC1M_IN_RGMII		0x00000000
 #define HRCWH_TSEC1M_IN_RTBI		0x00004000
 #define HRCWH_TSEC1M_IN_GMII		0x00008000
@@ -589,7 +589,7 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
+#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
 #define RSR_RSTSRC			0xF0000000	/* Reset source */
 #define RSR_RSTSRC_SHIFT		28
 #else
@@ -682,7 +682,7 @@
 #define SCCR_PCICM			0x00010000
 #define SCCR_PCICM_SHIFT		16
 
-#if defined(CONFIG_MPC834X)
+#if defined(CONFIG_MPC834x)
 /* SCCR bits - MPC834x specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
@@ -770,7 +770,7 @@
 #define SCCR_TDMCM_2			0x00000020
 #define SCCR_TDMCM_3			0x00000030
 
-#elif defined(CONFIG_MPC837X)
+#elif defined(CONFIG_MPC837x)
 /* SCCR bits - MPC837x specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
-- 
cgit v1.3.1


From ed90d2c87158e5114b6009fa95bb6417e4b27b3e Mon Sep 17 00:00:00 2001
From: Vivek Mahajan <vivek.mahajan@freescale.com>
Date: Thu, 21 May 2009 17:32:27 +0530
Subject: mpc8xxx: USB: Relocates ehci-fsl.h to include/usb

The following patch moves 8xxx-specifc USB #defines from
drivers/usb/host/ehci-fsl.h to include/usb.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
---
 drivers/usb/host/ehci-fsl.c |  2 +-
 drivers/usb/host/ehci-fsl.h | 86 ---------------------------------------------
 include/usb/ehci-fsl.h      | 86 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 87 insertions(+), 87 deletions(-)
 delete mode 100644 drivers/usb/host/ehci-fsl.h
 create mode 100644 include/usb/ehci-fsl.h

(limited to 'include')

diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index cff6024537b..39ef4354ec7 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -27,7 +27,7 @@
 #include <asm/bitops.h>
 
 #include "ehci.h"
-#include "ehci-fsl.h"
+#include <usb/ehci-fsl.h>
 #include "ehci-core.h"
 
 /*
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
deleted file mode 100644
index c429af12534..00000000000
--- a/drivers/usb/host/ehci-fsl.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * Copyright (c) 2005 freescale semiconductor
- * Copyright (c) 2005 MontaVista Software
- * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef _EHCI_FSL_H
-#define _EHCI_FSL_H
-
-/* Global offsets */
-#define FSL_SKIP_PCI		0x100
-
-/* offsets for the non-ehci registers in the FSL SOC USB controller */
-#define FSL_SOC_USB_ULPIVP	0x170
-#define FSL_SOC_USB_PORTSC1	0x184
-#define PORT_PTS_MSK		(3 << 30)
-#define PORT_PTS_UTMI		(0 << 30)
-#define PORT_PTS_ULPI		(2 << 30)
-#define PORT_PTS_SERIAL		(3 << 30)
-#define PORT_PTS_PTW		(1 << 28)
-
-/* USBMODE Register bits */
-#define CM_IDLE			(0 << 0)
-#define CM_RESERVED		(1 << 0)
-#define CM_DEVICE		(2 << 0)
-#define CM_HOST			(3 << 0)
-#define USBMODE_RESERVED_2	(0 << 2)
-#define SLOM			(1 << 3)
-#define SDIS			(1 << 4)
-
-/* CONTROL Register bits */
-#define ULPI_INT_EN		(1 << 0)
-#define WU_INT_EN		(1 << 1)
-#define USB_EN			(1 << 2)
-#define LSF_EN			(1 << 3)
-#define KEEP_OTG_ON		(1 << 4)
-#define OTG_PORT		(1 << 5)
-#define REFSEL_12MHZ		(0 << 6)
-#define REFSEL_16MHZ		(1 << 6)
-#define REFSEL_48MHZ		(2 << 6)
-#define PLL_RESET		(1 << 8)
-#define UTMI_PHY_EN		(1 << 9)
-#define PHY_CLK_SEL_UTMI	(0 << 10)
-#define PHY_CLK_SEL_ULPI	(1 << 10)
-#define CLKIN_SEL_USB_CLK	(0 << 11)
-#define CLKIN_SEL_USB_CLK2	(1 << 11)
-#define CLKIN_SEL_SYS_CLK	(2 << 11)
-#define CLKIN_SEL_SYS_CLK2	(3 << 11)
-#define RESERVED_18		(0 << 13)
-#define RESERVED_17		(0 << 14)
-#define RESERVED_16		(0 << 15)
-#define WU_INT			(1 << 16)
-#define PHY_CLK_VALID		(1 << 17)
-
-#define FSL_SOC_USB_PORTSC2	0x188
-#define FSL_SOC_USB_USBMODE	0x1a8
-#define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
-#define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
-#define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
-#define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
-#define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
-#define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
-#define SNOOP_SIZE_2GB		0x1e
-
-/* System Clock Control Register */
-#define MPC83XX_SCCR_USB_MASK		0x00f00000
-#define MPC83XX_SCCR_USB_DRCM_11	0x00300000
-#define MPC83XX_SCCR_USB_DRCM_01	0x00100000
-#define MPC83XX_SCCR_USB_DRCM_10	0x00200000
-
-#endif /* _EHCI_FSL_H */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
new file mode 100644
index 00000000000..c429af12534
--- /dev/null
+++ b/include/usb/ehci-fsl.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2005 freescale semiconductor
+ * Copyright (c) 2005 MontaVista Software
+ * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EHCI_FSL_H
+#define _EHCI_FSL_H
+
+/* Global offsets */
+#define FSL_SKIP_PCI		0x100
+
+/* offsets for the non-ehci registers in the FSL SOC USB controller */
+#define FSL_SOC_USB_ULPIVP	0x170
+#define FSL_SOC_USB_PORTSC1	0x184
+#define PORT_PTS_MSK		(3 << 30)
+#define PORT_PTS_UTMI		(0 << 30)
+#define PORT_PTS_ULPI		(2 << 30)
+#define PORT_PTS_SERIAL		(3 << 30)
+#define PORT_PTS_PTW		(1 << 28)
+
+/* USBMODE Register bits */
+#define CM_IDLE			(0 << 0)
+#define CM_RESERVED		(1 << 0)
+#define CM_DEVICE		(2 << 0)
+#define CM_HOST			(3 << 0)
+#define USBMODE_RESERVED_2	(0 << 2)
+#define SLOM			(1 << 3)
+#define SDIS			(1 << 4)
+
+/* CONTROL Register bits */
+#define ULPI_INT_EN		(1 << 0)
+#define WU_INT_EN		(1 << 1)
+#define USB_EN			(1 << 2)
+#define LSF_EN			(1 << 3)
+#define KEEP_OTG_ON		(1 << 4)
+#define OTG_PORT		(1 << 5)
+#define REFSEL_12MHZ		(0 << 6)
+#define REFSEL_16MHZ		(1 << 6)
+#define REFSEL_48MHZ		(2 << 6)
+#define PLL_RESET		(1 << 8)
+#define UTMI_PHY_EN		(1 << 9)
+#define PHY_CLK_SEL_UTMI	(0 << 10)
+#define PHY_CLK_SEL_ULPI	(1 << 10)
+#define CLKIN_SEL_USB_CLK	(0 << 11)
+#define CLKIN_SEL_USB_CLK2	(1 << 11)
+#define CLKIN_SEL_SYS_CLK	(2 << 11)
+#define CLKIN_SEL_SYS_CLK2	(3 << 11)
+#define RESERVED_18		(0 << 13)
+#define RESERVED_17		(0 << 14)
+#define RESERVED_16		(0 << 15)
+#define WU_INT			(1 << 16)
+#define PHY_CLK_VALID		(1 << 17)
+
+#define FSL_SOC_USB_PORTSC2	0x188
+#define FSL_SOC_USB_USBMODE	0x1a8
+#define FSL_SOC_USB_SNOOP1	0x400	/* NOTE: big-endian */
+#define FSL_SOC_USB_SNOOP2	0x404	/* NOTE: big-endian */
+#define FSL_SOC_USB_AGECNTTHRSH	0x408	/* NOTE: big-endian */
+#define FSL_SOC_USB_PRICTRL	0x40c	/* NOTE: big-endian */
+#define FSL_SOC_USB_SICTRL	0x410	/* NOTE: big-endian */
+#define FSL_SOC_USB_CTRL	0x500	/* NOTE: big-endian */
+#define SNOOP_SIZE_2GB		0x1e
+
+/* System Clock Control Register */
+#define MPC83XX_SCCR_USB_MASK		0x00f00000
+#define MPC83XX_SCCR_USB_DRCM_11	0x00300000
+#define MPC83XX_SCCR_USB_DRCM_01	0x00100000
+#define MPC83XX_SCCR_USB_DRCM_10	0x00200000
+
+#endif /* _EHCI_FSL_H */
-- 
cgit v1.3.1


From 4ef01010aa4799c759d75e67007fdd3a38c88c8a Mon Sep 17 00:00:00 2001
From: Vivek Mahajan <vivek.mahajan@freescale.com>
Date: Mon, 25 May 2009 17:23:16 +0530
Subject: mpc83xx: USB: Reorganized its support

The following patch reorganizes/reworks the USB support for mpc83xx
as under:-

  * Moves the 83xx USB clock init from drivers/usb/host/ehci-fsl.c to
    cpu/mpx83xx/cpu_init.c

  * Board specific usb_phy_type is read from the environment

  * Adds USB EHCI specific structure in include/usb/ehci-fsl.h

  * Copyrights revamped in most of the following files

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
---
 cpu/mpc83xx/cpu_init.c       | 19 ++++++++++++-
 drivers/usb/host/ehci-fsl.c  | 53 +++++++++++++------------------------
 include/asm-ppc/immap_83xx.h |  5 +++-
 include/usb/ehci-fsl.h       | 63 +++++++++++++++++++++++++++++++++++++++++++-
 4 files changed, 102 insertions(+), 38 deletions(-)

(limited to 'include')

diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index d9b96b57fec..414565cb65b 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -23,6 +23,10 @@
 #include <common.h>
 #include <mpc83xx.h>
 #include <ioports.h>
+#ifdef CONFIG_USB_EHCI_FSL
+#include <asm/io.h>
+#include <usb/ehci-fsl.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -294,6 +298,19 @@ void cpu_init_f (volatile immap_t * im)
 	im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
 	im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
 #endif
+#ifdef CONFIG_USB_EHCI_FSL
+	uint32_t temp;
+	struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+
+	/* Configure interface. */
+	setbits_be32((void *)ehci->control, REFSEL_16MHZ | UTMI_PHY_EN);
+
+	/* Wait for clock to stabilize */
+	do {
+		temp = in_be32((void *)ehci->control);
+		udelay(1000);
+	} while (!(temp & PHY_CLK_VALID));
+#endif
 }
 
 int cpu_init_r (void)
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 39ef4354ec7..bf148c4e242 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -1,4 +1,6 @@
 /*
+ * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ *
  * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
  *
  * Author: Tor Krill tor@excito.com
@@ -22,12 +24,10 @@
 #include <common.h>
 #include <pci.h>
 #include <usb.h>
-#include <mpc83xx.h>
 #include <asm/io.h>
-#include <asm/bitops.h>
+#include <usb/ehci-fsl.h>
 
 #include "ehci.h"
-#include <usb/ehci-fsl.h>
 #include "ehci-core.h"
 
 /*
@@ -38,50 +38,33 @@
  */
 int ehci_hcd_init(void)
 {
-	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	uint32_t addr, temp;
+	struct usb_ehci *ehci;
 
-	addr = (uint32_t)&(im->usb[0]);
-	hccr = (struct ehci_hccr *)(addr + FSL_SKIP_PCI);
+	ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR;
+	hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength);
 	hcor = (struct ehci_hcor *)((uint32_t) hccr +
 			HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
 
-	/* Configure clock */
-	clrsetbits_be32(&(im->clk.sccr), MPC83XX_SCCR_USB_MASK,
-			MPC83XX_SCCR_USB_DRCM_11);
-
-	/* Confgure interface. */
-	temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
-	out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp
-		 | REFSEL_16MHZ | UTMI_PHY_EN);
-
-	/* Wait for clock to stabilize */
-	do {
-		temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
-		udelay(1000);
-	} while (!(temp & PHY_CLK_VALID));
-
 	/* Set to Host mode */
-	temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
-	out_le32((void *)(addr + FSL_SOC_USB_USBMODE), temp | CM_HOST);
+	setbits_le32((void *)ehci->usbmode, CM_HOST);
 
-	out_be32((void *)(addr + FSL_SOC_USB_SNOOP1), SNOOP_SIZE_2GB);
-	out_be32((void *)(addr + FSL_SOC_USB_SNOOP2),
-		 0x80000000 | SNOOP_SIZE_2GB);
+	out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB);
+	out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
 
 	/* Init phy */
-	/* TODO: handle different phys? */
-	out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
+	if (!strcmp(getenv("usb_phy_type"), "utmi"))
+		out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
+	else
+		out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
 
 	/* Enable interface. */
-	temp = in_be32((void *)(addr + FSL_SOC_USB_CTRL));
-	out_be32((void *)(addr + FSL_SOC_USB_CTRL), temp | USB_EN);
+	setbits_be32((void *)ehci->control, USB_EN);
 
-	out_be32((void *)(addr + FSL_SOC_USB_PRICTRL), 0x0000000c);
-	out_be32((void *)(addr + FSL_SOC_USB_AGECNTTHRSH), 0x00000040);
-	out_be32((void *)(addr + FSL_SOC_USB_SICTRL), 0x00000001);
+	out_be32((void *)ehci->prictrl, 0x0000000c);
+	out_be32((void *)ehci->age_cnt_limit, 0x00000040);
+	out_be32((void *)ehci->sictrl, 0x00000001);
 
-	temp = in_le32((void *)(addr + FSL_SOC_USB_USBMODE));
+	in_le32((void *)ehci->usbmode);
 
 	return 0;
 }
diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h
index 1e67de6c918..8f945a15196 100644
--- a/include/asm-ppc/immap_83xx.h
+++ b/include/asm-ppc/immap_83xx.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
+ * (C) Copyright 2004-2009 Freescale Semiconductor, Inc.
  *
  * MPC83xx Internal Memory Map
  *
@@ -897,4 +897,7 @@ typedef struct immap {
 
 #define CONFIG_SYS_MPC83xx_ESDHC_OFFSET	(0x2e000)
 #define CONFIG_SYS_MPC83xx_ESDHC_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET)
+#define CONFIG_SYS_MPC83xx_USB_OFFSET	0x23000
+#define CONFIG_SYS_MPC83xx_USB_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
 #endif				/* __IMMAP_83xx__ */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index c429af12534..7ae948c670c 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2005 freescale semiconductor
+ * Copyright (c) 2005, 2009 Freescale Semiconductor, Inc
  * Copyright (c) 2005 MontaVista Software
  * Copyright (c) 2008 Excito Elektronik i Sk=E5ne AB
  *
@@ -22,6 +22,8 @@
 #ifndef _EHCI_FSL_H
 #define _EHCI_FSL_H
 
+#include <asm/processor.h>
+
 /* Global offsets */
 #define FSL_SKIP_PCI		0x100
 
@@ -83,4 +85,63 @@
 #define MPC83XX_SCCR_USB_DRCM_01	0x00100000
 #define MPC83XX_SCCR_USB_DRCM_10	0x00200000
 
+#if defined(CONFIG_MPC83XX)
+#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#endif
+
+/*
+ * USB Registers
+ */
+struct usb_ehci {
+	u8	res1[0x100];
+	u16	caplength;	/* 0x100 - Capability Register Length */
+	u16	hciversion;	/* 0x102 - Host Interface Version */
+	u32	hcsparams;	/* 0x104 - Host Structural Parameters */
+	u32	hccparams;	/* 0x108 - Host Capability Parameters */
+	u8	res2[0x14];
+	u32	dciversion;	/* 0x120 - Device Interface Version */
+	u32	dciparams;	/* 0x124 - Device Controller Params */
+	u8	res3[0x18];
+	u32	usbcmd;		/* 0x140 - USB Command */
+	u32	usbsts;		/* 0x144 - USB Status */
+	u32	usbintr;	/* 0x148 - USB Interrupt Enable */
+	u32	frindex;	/* 0x14C - USB Frame Index */
+	u8	res4[0x4];
+	u32	perlistbase;	/* 0x154 - Periodic List Base
+					 - USB Device Address */
+	u32	ep_list_addr;	/* 0x158 - Next Asynchronous List
+					 - End Point Address */
+	u8	res5[0x4];
+	u32	burstsize;	/* 0x160 - Programmable Burst Size */
+	u32	txfilltuning;	/* 0x164 - Host TT Transmit
+					   pre-buffer packet tuning */
+	u8	res6[0x8];
+	u32	ulpi_viewpoint;	/* 0x170 - ULPI Reister Access */
+	u8	res7[0xc];
+	u32	config_flag;	/* 0x180 - Configured Flag Register */
+	u32	portsc;		/* 0x184 - Port status/control */
+	u8	res8[0x20];
+	u32	usbmode;	/* 0x1a8 - USB Device Mode */
+	u32	epsetupstat;	/* 0x1ac - End Point Setup Status */
+	u32	epprime;	/* 0x1b0 - End Point Init Status */
+	u32	epflush;	/* 0x1b4 - End Point De-initlialize */
+	u32	epstatus;	/* 0x1b8 - End Point Status */
+	u32	epcomplete;	/* 0x1bc - End Point Complete */
+	u32	epctrl0;	/* 0x1c0 - End Point Control 0 */
+	u32	epctrl1;	/* 0x1c4 - End Point Control 1 */
+	u32	epctrl2;	/* 0x1c8 - End Point Control 2 */
+	u32	epctrl3;	/* 0x1cc - End Point Control 3 */
+	u32	epctrl4;	/* 0x1d0 - End Point Control 4 */
+	u32	epctrl5;	/* 0x1d4 - End Point Control 5 */
+	u8	res9[0x228];
+	u32	snoop1;		/* 0x400 - Snoop 1 */
+	u32	snoop2;		/* 0x404 - Snoop 2 */
+	u32	age_cnt_limit;	/* 0x408 - Age Count Threshold */
+	u32	prictrl;	/* 0x40c - Priority Control */
+	u32	sictrl;		/* 0x410 - System Interface Control */
+	u8	res10[0xEC];
+	u32	control;	/* 0x500 - Control */
+	u8	res11[0xafc];
+};
+
 #endif /* _EHCI_FSL_H */
-- 
cgit v1.3.1


From a07bf180efc3c0de4a89a3bd49a7c7584dfb95a8 Mon Sep 17 00:00:00 2001
From: Vivek Mahajan <vivek.mahajan@freescale.com>
Date: Thu, 21 May 2009 17:32:48 +0530
Subject: mpc85xx: USB: Add support

The following patch adds 85xx-specific USB support and also
revamps Copyright in immap_85xx.h

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
---
 include/asm-ppc/immap_85xx.h | 5 ++++-
 include/usb/ehci-fsl.h       | 2 ++
 2 files changed, 6 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index d3c6b86d2b1..06b4dc31f47 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007 Freescale Semiconductor.
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -1732,5 +1732,8 @@ typedef struct ccsr_gur {
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	(0xE3100)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+#define CONFIG_SYS_MPC85xx_USB_OFFSET		0x22000
+#define CONFIG_SYS_MPC85xx_USB_ADDR \
+			(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET)
 
 #endif /*__IMMAP_85xx__*/
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index 7ae948c670c..114056177c2 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -87,6 +87,8 @@
 
 #if defined(CONFIG_MPC83XX)
 #define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR
+#elif defined(CONFIG_MPC85xx)
+#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR
 #endif
 
 /*
-- 
cgit v1.3.1


From 6823e9b01290977c4d9c90381459c01f66e12e79 Mon Sep 17 00:00:00 2001
From: Vivek Mahajan <vivek.mahajan@freescale.com>
Date: Mon, 25 May 2009 17:23:17 +0530
Subject: mpc83xx: 8315erdb: Add USB related CONFIGs

This patch adds CONFIGs for enabling USB in mpc8315erdb and also
adds usb_phy_type in CONFIG_EXTRA_ENV_SETTINGS. Also revamps its
Copyright.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
---
 include/configs/MPC8315ERDB.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h
index d9888f58c60..e03a1077ff5 100644
--- a/include/configs/MPC8315ERDB.h
+++ b/include/configs/MPC8315ERDB.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
@@ -345,6 +345,14 @@
 #endif
 
 #define CONFIG_HAS_FSL_DR_USB
+#define CONFIG_SYS_SCCR_USBDRCM		3
+
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_USB_PHY_TYPE 	"utmi"
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 
 /*
  * TSEC
@@ -569,6 +577,7 @@
    "ramdiskfile=ramfs.83xx\0"						\
    "fdtaddr=400000\0"							\
    "fdtfile=mpc8315erdb.dtb\0"						\
+   "usb_phy_type=utmi\0"						\
    ""
 
 #define CONFIG_NFSBOOTCOMMAND						\
-- 
cgit v1.3.1


From 4bc6eb79be2a7317425575184324b94e3b43fbc2 Mon Sep 17 00:00:00 2001
From: Vivek Mahajan <vivek.mahajan@freescale.com>
Date: Mon, 25 May 2009 17:23:18 +0530
Subject: mpc85xx: 8536ds: Add USB related CONFIGs

This patch adds CONFIGs for enabling USB in mpc8536ds and also
adds usb_phy_type in CONFIG_EXTRA_ENV_SETTINGS. Also revamps its
Copyright.

Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com>
Signed-off-by: Remy Bohmer <linux@bohmer.net>
---
 include/configs/MPC8536DS.h | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h
index bc1267f49fc..9e00b898621 100644
--- a/include/configs/MPC8536DS.h
+++ b/include/configs/MPC8536DS.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -462,6 +462,15 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
 #define CONFIG_CMD_EXT2
 #endif
 
+/*
+ * USB
+ */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+
 #if defined(CONFIG_TSEC_ENET)
 
 #ifndef CONFIG_NET_MULTI
@@ -627,7 +636,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
  "ramdiskfile=8536ds/ramdisk.uboot\0"		\
  "fdtaddr=c00000\0"				\
  "fdtfile=8536ds/mpc8536ds.dtb\0"		\
- "bdev=sda3\0"
+ "bdev=sda3\0"					\
+ "usb_phy_type=ulpi\0"
 
 #define CONFIG_HDBOOT				\
  "setenv bootargs root=/dev/$bdev rw "		\
-- 
cgit v1.3.1


From 0a14d6b8f4d21ff59a9b7686a49a77069a9fcd2a Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 4 Jun 2009 13:35:35 +0200
Subject: 74xx_7xx: CPCI750: Add commandline editing/history

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---
 include/configs/CPCI750.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 8494faac29c..3b0b888f7eb 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -76,7 +76,8 @@
 
 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
-#define CONFIG_AUTO_COMPLETE 1
+#define CONFIG_CMDLINE_EDITING		/* add command line history	*/
+#define CONFIG_AUTO_COMPLETE		/* add autocompletion support	*/
 
 /* Define which ETH port will be used for connecting the network */
 #define CONFIG_SYS_ETH_PORT		ETH_0
-- 
cgit v1.3.1


From 58f10460b05e0928d986b15edd4f2e1e99403f7e Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Thu, 4 Jun 2009 13:35:39 +0200
Subject: 74xx_7xx: CPCI750: Add CPCI adapter/target support

The CPCI750 can be built as CPCI host or adapter/target board. This patch
adds support for runtime detection of those variants.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---
 board/esd/cpci750/cpci750.c |  9 +++++++++
 board/esd/cpci750/ide.c     |  4 +++-
 board/esd/cpci750/pci.c     | 49 ++++++++++++++++++++++++++++++++-------------
 include/configs/CPCI750.h   |  2 ++
 4 files changed, 49 insertions(+), 15 deletions(-)

(limited to 'include')

diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 4ac1ff480d3..2ae4cbd6c0b 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -140,6 +140,15 @@ void board_prebootm_init (void);
 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
+/*
+ * Skip video initialization on slave variant.
+ * This function will overwrite the weak default in cfb_console.c
+ */
+int board_video_skip(void)
+{
+	return CPCI750_SLAVE_TEST;
+}
+
 /* ------------------------------------------------------------------------- */
 
 /*
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 9bdc5234534..638219f65ec 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -39,6 +39,8 @@ int ide_preinit (void)
 	int l;
 
 	status = 1;
+	if (CPCI750_SLAVE_TEST != 0)
+		return status;
 	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
@@ -57,7 +59,7 @@ int ide_preinit (void)
 		ide_bus_offset[1] &= 0xfffffffe;
 		ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
 	}
-	return (status);
+	return status;
 }
 
 void ide_set_reset (int flag) {
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index 3b59b16b1ca..a2c1c506244 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -795,7 +795,6 @@ static int gt_write_config_dword (struct pci_controller *hose,
 					     PCI_DEV (dev), bus,
 					     value);
 	}
-
 	return 0;
 }
 
@@ -807,6 +806,9 @@ static void gt_setup_ide (struct pci_controller *hose,
 	u32 bar_response, bar_value;
 	int bar;
 
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
 	for (bar = 0; bar < 6; bar++) {
 		/*ronen different function for 3rd bank. */
 		unsigned int offset =
@@ -833,6 +835,9 @@ static void gt_setup_cpcidvi (struct pci_controller *hose,
 {
 	u32		  bar_value, pci_response;
 
+	if (CPCI750_SLAVE_TEST != 0)
+		return;
+
 	pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
 	pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
 	pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
@@ -911,6 +916,7 @@ struct pci_controller pci1_hose = {
 void pci_init_board (void)
 {
 	unsigned int command;
+	unsigned int slave;
 #ifdef CONFIG_PCI_PNP
 	unsigned int bar;
 #endif
@@ -922,6 +928,8 @@ void pci_init_board (void)
 	gt_cpcidvi_rom.base = 0;
 #endif
 
+	slave = CPCI750_SLAVE_TEST;
+
 	pci0_hose.config_table = gt_config_table;
 	pci1_hose.config_table = gt_config_table;
 
@@ -957,27 +965,40 @@ void pci_init_board (void)
 	pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
 
 	pci_register_hose (&pci0_hose);
-	pciArbiterEnable (PCI_HOST0);
-	pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MASTER;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
-	command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
-	command |= PCI_COMMAND_MEMORY;
-	pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+	if (slave == 0) {
+		pciArbiterEnable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
 
 #ifdef CONFIG_PCI_PNP
-	pciauto_config_init(&pci0_hose);
-	pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
+		pciauto_config_init(&pci0_hose);
+		pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
 #endif
 #ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
+		printf("PCI:   Bus Dev VenId DevId Class Int\n");
 #endif
-	pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
+		pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose,
+							  pci0_hose.first_busno);
 
 #ifdef DEBUG
-	gt_pci_bus_mode_display (PCI_HOST1);
+		gt_pci_bus_mode_display (PCI_HOST1);
 #endif
+	} else {
+		pciArbiterDisable (PCI_HOST0);
+		pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MASTER;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
+		command |= PCI_COMMAND_MEMORY;
+		pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
+		pci0_hose.last_busno = pci0_hose.first_busno;
+	}
 	pci1_hose.first_busno = pci0_hose.last_busno + 1;
 	pci1_hose.last_busno = 0xff;
 	pci1_hose.current_busno = pci1_hose.first_busno;
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 3b0b888f7eb..d516c3cb812 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -627,4 +627,6 @@
 
 #define CONFIG_SYS_BOARD_ASM_INIT	1
 
+#define CPCI750_SLAVE_TEST	(((in8(0xf0300000) & 0x80) == 0) ? 0 : 1)
+
 #endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 6bd55cc65d0c3aa84d719518254fb3c650239ed9 Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 9 Jun 2009 11:50:05 +0200
Subject: mcp512x: Add macros for SCFR LPC divisor access

Thos macros will be used by the esd mecp5123 board.

Signed-off-by: Stefan Roese <sr@denx.de>
---
 include/asm-ppc/immap_512x.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'include')

diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h
index 444e0288855..3648a05f8cb 100644
--- a/include/asm-ppc/immap_512x.h
+++ b/include/asm-ppc/immap_512x.h
@@ -234,6 +234,9 @@ typedef struct clk512x {
 #define SCFR1_PCI_DIV_MASK	0x00700000
 #define SCFR1_PCI_DIV_SHIFT	20
 
+#define SCFR1_LPC_DIV_MASK	0x00003800
+#define SCFR1_LPC_DIV_SHIFT	11
+
 /* SCFR2 System Clock Frequency Register 2 */
 #define SCFR2_SYS_DIV		0xFC000000
 #define SCFR2_SYS_DIV_SHIFT	26
-- 
cgit v1.3.1


From e53b507cee5d976953134a565c72fd32c967d7dd Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 9 Jun 2009 11:50:40 +0200
Subject: mpc512x: Add esd gmbh mecp5123 board support

MECP5123 is a MPC5121E based module by esd gmbh.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
---
 MAINTAINERS                   |   1 +
 MAKEALL                       |   1 +
 Makefile                      |   3 +
 board/esd/mecp5123/Makefile   |  50 +++++
 board/esd/mecp5123/config.mk  |  23 +++
 board/esd/mecp5123/mecp5123.c | 381 +++++++++++++++++++++++++++++++++++
 include/configs/mecp5123.h    | 458 ++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 917 insertions(+)
 create mode 100644 board/esd/mecp5123/Makefile
 create mode 100644 board/esd/mecp5123/config.mk
 create mode 100644 board/esd/mecp5123/mecp5123.c
 create mode 100644 include/configs/mecp5123.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index bba6ce99421..1f6008f747e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -28,6 +28,7 @@ Pantelis Antoniou <panto@intracom.gr>
 Reinhard Arlt <reinhard.arlt@esd-electronics.com>
 
 	cpci5200	MPC5200
+	mecp5123	MPC5121
 	mecp5200	MPC5200
 	pf5200		MPC5200
 
diff --git a/MAKEALL b/MAKEALL
index fd312529b1c..f48a08e579b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -78,6 +78,7 @@ LIST_5xxx="		\
 
 LIST_512x="		\
 	aria		\
+	mecp5123	\
 	mpc5121ads	\
 "
 
diff --git a/Makefile b/Makefile
index 3c9d8532924..aa4646f4c16 100644
--- a/Makefile
+++ b/Makefile
@@ -824,6 +824,9 @@ v38b_config: unconfig
 aria_config:	unconfig
 	@$(MKCONFIG) -a aria ppc mpc512x aria davedenx
 
+mecp5123_config:	unconfig
+	@$(MKCONFIG) -a mecp5123 ppc mpc512x mecp5123 esd
+
 mpc5121ads_config \
 mpc5121ads_rev2_config	\
 	: unconfig
diff --git a/board/esd/mecp5123/Makefile b/board/esd/mecp5123/Makefile
new file mode 100644
index 00000000000..2e3d73a3513
--- /dev/null
+++ b/board/esd/mecp5123/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+COBJS	:= $(COBJS-y)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/esd/mecp5123/config.mk b/board/esd/mecp5123/config.mk
new file mode 100644
index 00000000000..838a0184973
--- /dev/null
+++ b/board/esd/mecp5123/config.mk
@@ -0,0 +1,23 @@
+#
+# (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TEXT_BASE  =   0xFFF00000
diff --git a/board/esd/mecp5123/mecp5123.c b/board/esd/mecp5123/mecp5123.c
new file mode 100644
index 00000000000..909b45869e5
--- /dev/null
+++ b/board/esd/mecp5123/mecp5123.c
@@ -0,0 +1,381 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009 Dave Srl www.dave.eu
+ * (C) Copyright 2009 Stefan Roese <sr@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/bitops.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <fdt_support.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Clocks in use */
+#define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
+			 CLOCK_SCCR1_DDR_EN |				\
+			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
+			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_TPR_EN)
+
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |	\
+			 CLOCK_SCCR2_I2C_EN)
+
+#define CSAW_START(start)	((start) & 0xFFFF0000)
+#define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
+
+int eeprom_write_enable(unsigned dev_addr, int state)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
+		return -1;
+
+	if (state == 0)
+		setbits_be32(&im->gpio.gpdat, 0x00100000);
+	else
+		clrbits_be32(&im->gpio.gpdat, 0x00100000);
+
+return 0;
+}
+
+/*
+ * According to MPC5121e RM, configuring local access windows should
+ * be followed by a dummy read of the config register that was
+ * modified last and an isync.
+ */
+static inline void sync_law(volatile void *addr)
+{
+	in_be32(addr);
+	__asm__ __volatile__ ("isync");
+}
+
+int board_early_init_f(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	/*
+	 * Initialize Local Window for NOR FLASH access
+	 */
+	out_be32(&im->sysconf.lpcs0aw,
+		 CSAW_START(CONFIG_SYS_FLASH_BASE) |
+		 CSAW_STOP(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
+	sync_law(&im->sysconf.lpcs0aw);
+
+	/*
+	 * Initialize Local Window for boot access
+	 */
+	out_be32(&im->sysconf.lpbaw,
+		 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
+	sync_law(&im->sysconf.lpbaw);
+
+	/*
+	 * Initialize Local Window for VPC3 access
+	 */
+	out_be32(&im->sysconf.lpcs1aw,
+		 CSAW_START(CONFIG_SYS_VPC3_BASE) |
+		 CSAW_STOP(CONFIG_SYS_VPC3_BASE, CONFIG_SYS_VPC3_SIZE));
+	sync_law(&im->sysconf.lpcs1aw);
+
+	/*
+	 * Configure Flash Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
+
+	/*
+	 * Configure VPC3 Speed
+	 */
+	out_be32(&im->lpc.cs_cfg[1], CONFIG_SYS_CS1_CFG);
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		out_be32(&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
+
+	/*
+	 * Enable clocks
+	 */
+	out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
+	out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
+#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
+	setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
+#endif
+
+	/*
+	 * Configure MSCAN clocks
+	 */
+	out_be32(&im->clk.m1ccr, 0x00300000);
+	out_be32(&im->clk.m2ccr, 0x00300000);
+	out_be32(&im->clk.m3ccr, 0x00300000);
+	out_be32(&im->clk.m4ccr, 0x00300000);
+	out_be32(&im->clk.m1ccr, 0x00310000);
+	out_be32(&im->clk.m2ccr, 0x00310000);
+	out_be32(&im->clk.m3ccr, 0x00310000);
+	out_be32(&im->clk.m4ccr, 0x00310000);
+
+	/*
+	 * Configure GPIO's
+	 */
+	clrbits_be32(&im->gpio.gpodr, 0x000000e0);
+	clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
+	setbits_be32(&im->gpio.gpdir, 0x001000e0);
+	setbits_be32(&im->gpio.gpdat, 0x00100000);
+
+	return 0;
+}
+
+/*
+ * fixed sdram init:
+ * The board doesn't use memory modules that have serial presence
+ * detect or similar mechanism for discovery of the DRAM settings
+ */
+long int fixed_sdram(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+	u32 i;
+
+	/* Initialize IO Control */
+	out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
+
+	/* Initialize DDR Local Window */
+	out_be32(&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
+	out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
+	sync_law(&im->sysconf.ddrlaw.ar);
+
+	/* Enable DDR */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
+
+	/* Initialize DDR Priority Manager */
+	out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
+	out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
+	out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
+	out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
+	out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
+	out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
+	out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
+	out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
+	out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
+	out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
+	out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
+	out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
+	out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
+	out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
+	out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
+	out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
+	out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
+	out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
+	out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
+	out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
+	out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
+	out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
+	out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
+
+	/* Initialize MDDRC */
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
+	out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
+	out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
+
+	/* Initialize DDR */
+	for (i = 0; i < 10; i++)
+		out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
+	out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
+
+	/* Start MDDRC */
+	out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
+	out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return get_ram_size(0, fixed_sdram());
+}
+
+int misc_init_r(void)
+{
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 val;
+
+	/*
+	 * Optimize access to profibus chip (VPC3) on the local bus
+	 */
+
+	/*
+	 * Select 1:1 for LPC_DIV
+	 */
+	val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
+	out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
+
+	/*
+	 * Configure LPC Chips Select Deadcycle Control Register
+	 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
+	 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
+
+	/*
+	 * Configure LPC Chips Select Holdcycle Control Register
+	 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
+	 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
+	 */
+	clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
+	setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
+
+	return 0;
+}
+
+static iopin_t ioregs_init[] = {
+	/* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=FEC_COL Sets Next 15 to FEC pads */
+	{
+		offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
+		IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC1=SELECT LPC_CS1 */
+	{
+		offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_2 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
+		IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC5_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC7_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC9_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC10_3 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC3=SELECT PSC11_0 */
+	{
+		offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
+		IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	},
+	/* FUNC0=SELECT IRQ0 */
+	{
+		offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
+		IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
+	}
+};
+
+static iopin_t rev2_silicon_pci_ioregs_init[] = {
+	/* FUNC0=PCI Sets next 54 to PCI pads */
+	{
+		offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
+		IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
+	}
+};
+
+int checkboard(void)
+{
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 spridr;
+
+	puts("Board: MECP_5123\n");
+
+	/*
+	 * Initialize function mux & slew rate IO inter alia on IO
+	 * Pins
+	 */
+	iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
+
+	spridr = in_be32(&im->sysconf.spridr);
+	if (SVR_MJREV(spridr) >= 2)
+		iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
+
+	return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
+}
+#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h
new file mode 100644
index 00000000000..083184316a8
--- /dev/null
+++ b/include/configs/mecp5123.h
@@ -0,0 +1,458 @@
+/*
+ * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
+ * (C) Copyright 2009, DAVE Srl <www.dave.eu>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * modifications for the MECP5123 by reinhard.arlt@esd-electronics.com
+ *
+ */
+
+/*
+ * MECP5123 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MECP5123 1
+/*
+ * Memory map for the MECP5123 board:
+ *
+ * 0x0000_0000 - 0x1FFF_FFFF	DDR RAM (512 MB)
+ * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
+ * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
+ * 0x8200_0000 - 0x8200_FFFF	VPC-3 (64 KB)
+ * 0xFFC0_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
+ */
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1	/* E300 Family */
+#define CONFIG_MPC512X		1	/* MPC512X family */
+
+#define CONFIG_SYS_MPC512X_CLKIN	33333333	/* in Hz */
+
+#define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_SYS_IMMR		        0x80000000
+#define CONFIG_SYS_DIU_ADDR		(CONFIG_SYS_IMMR+0x2100)
+
+#define CONFIG_SYS_MEMTEST_START	0x00200000      /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+
+/*
+ * DDR Setup - manually set all parameters as there's no SPD etc.
+ */
+#define CONFIG_SYS_DDR_SIZE		512		/* MB */
+
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is sys memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+
+/* DDR Controller Configuration
+ *
+ * SYS_CFG:
+ *	[31:31]	MDDRC Soft Reset:	Diabled
+ *	[30:30]	DRAM CKE pin:		Enabled
+ *	[29:29]	DRAM CLK:		Enabled
+ *	[28:28]	Command Mode:		Enabled (For initialization only)
+ *	[27:25]	DRAM Row Select:	dram_row[15:0] = magenta_address[25:10]
+ *	[24:21]	DRAM Bank Select:	dram_bank[1:0] = magenta_address[11:10]
+ *	[20:19]	Read Test:		DON'T USE
+ *	[18:18]	Self Refresh:		Enabled
+ *	[17:17]	16bit Mode:		Disabled
+ *	[16:13] Ready Delay:		2
+ *	[12:12]	Half DQS Delay:		Disabled
+ *	[11:11]	Quarter DQS Delay:	Disabled
+ *	[10:08]	Write Delay:		2
+ *	[07:07]	Early ODT:		Disabled
+ *	[06:06]	On DIE Termination:	Disabled
+ *	[05:05]	FIFO Overflow Clear:	DON'T USE here
+ *	[04:04]	FIFO Underflow Clear:	DON'T USE here
+ *	[03:03]	FIFO Overflow Pending:	DON'T USE here
+ *	[02:02]	FIFO Underlfow Pending:	DON'T USE here
+ *	[01:01]	FIFO Overlfow Enabled:	Enabled
+ *	[00:00]	FIFO Underflow Enabled:	Enabled
+ * TIME_CFG0
+ *	[31:16]	DRAM Refresh Time:	0 CSB clocks
+ *	[15:8]	DRAM Command Time:	0 CSB clocks
+ *	[07:00]	DRAM Precharge Time:	0 CSB clocks
+ * TIME_CFG1
+ *	[31:26]	DRAM tRFC:
+ *	[25:21]	DRAM tWR1:
+ *	[20:17]	DRAM tWRT1:
+ *	[16:11]	DRAM tDRR:
+ *	[10:05]	DRAM tRC:
+ *	[04:00]	DRAM tRAS:
+ * TIME_CFG2
+ *	[31:28]	DRAM tRCD:
+ *	[27:23]	DRAM tFAW:
+ *	[22:19]	DRAM tRTW1:
+ *	[18:15]	DRAM tCCD:
+ *	[14:10] DRAM tRTP:
+ *	[09:05]	DRAM tRP:
+ *	[04:00] DRAM tRPA
+ */
+#ifdef CONFIG_ADS5121_REV2
+#define CONFIG_SYS_MDDRC_SYS_CFG	0xF8604A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	0xE8604A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	0x54EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	0x35210864
+#else
+#define CONFIG_SYS_MDDRC_SYS_CFG	 0xFA804A00
+#define CONFIG_SYS_MDDRC_SYS_CFG_RUN	 0xEA804A00
+#define CONFIG_SYS_MDDRC_TIME_CFG1	 0x68EC1168
+#define CONFIG_SYS_MDDRC_TIME_CFG2	 0x34310864
+#endif
+#define CONFIG_SYS_MDDRC_SYS_CFG_EN	0xF0000000
+#define CONFIG_SYS_MDDRC_TIME_CFG0	0x00003D2E
+#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN	0x06183D2E
+
+#define CONFIG_SYS_MICRON_NOP		0x01380000
+#define CONFIG_SYS_MICRON_PCHG_ALL	0x01100400
+#define CONFIG_SYS_MICRON_EM2		0x01020000
+#define CONFIG_SYS_MICRON_EM3		0x01030000
+#define CONFIG_SYS_MICRON_EN_DLL	0x01010000
+#define CONFIG_SYS_MICRON_RFSH		0x01080000
+#define CONFIG_SYS_MICRON_INIT_DEV_OP	0x01000432
+#define CONFIG_SYS_MICRON_OCD_DEFAULT	0x01010780
+
+/* DDR Priority Manager Configuration */
+#define CONFIG_SYS_MDDRCGRP_PM_CFG1	0x00077777
+#define CONFIG_SYS_MDDRCGRP_PM_CFG2	0x00000000
+#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CONFIG_SYS_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CONFIG_SYS_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CONFIG_SYS_MDDRCGRP_LUT1_MU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_ML	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT2_MU	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT2_ML	0x44444444
+#define CONFIG_SYS_MDDRCGRP_LUT3_MU	0x55555555
+#define CONFIG_SYS_MDDRCGRP_LUT3_ML	0x55555558
+#define CONFIG_SYS_MDDRCGRP_LUT4_MU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_ML	0x11111122
+#define CONFIG_SYS_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CONFIG_SYS_MDDRCGRP_LUT1_AU	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT1_AL	0x66666666
+#define CONFIG_SYS_MDDRCGRP_LUT2_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT2_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT3_AL	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AU	0x11111111
+#define CONFIG_SYS_MDDRCGRP_LUT4_AL	0x11111111
+
+/*
+ * NOR FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+
+#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of FLASH */
+#define CONFIG_SYS_FLASH_SIZE		0x00400000	/* max flash size */
+
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
+#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max sectors per device */
+
+#undef CONFIG_SYS_FLASH_CHECKSUM
+
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE            0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE      1
+#define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH		1
+#define CONFIG_FSL_NFC_WRITE_SIZE	2048
+#define CONFIG_FSL_NFC_SPARE_SIZE	64
+#define CONFIG_FSL_NFC_CHIPS		1
+
+#define CONFIG_SYS_SRAM_BASE		0x30000000
+#define CONFIG_SYS_SRAM_SIZE		0x00020000	/* 128 KB */
+
+/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS0_CFG		0x05051150
+
+/* Use not alternative CS timing */
+#define CONFIG_SYS_CS_ALETIMING		0x00000000
+
+/* ALE active low, data size 4bytes */
+#define CONFIG_SYS_CS1_CFG		0x1f1f3090
+#define CONFIG_SYS_VPC3_BASE		0x82000000	/* start of VPC3 space */
+#define CONFIG_SYS_VPC3_SIZE		0x00010000	/* max VPC3 size */
+
+/* Use SRAM for initial stack */
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_SRAM_BASE /* Init RAM addr */
+#define CONFIG_SYS_INIT_RAM_END		CONFIG_SYS_SRAM_SIZE
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100		/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE	/* Start of monitor */
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Monitor length */
+#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024) /* Malloc size */
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX     1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE	3	/* console is on PSC3 */
+#if CONFIG_PSC_CONSOLE != 3
+#error CONFIG_PSC_CONSOLE must be 3
+#endif
+#define CONFIG_BAUDRATE		9600	/* ... at 9600 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONSOLE_FIFO_TX_SIZE	FIFOC_PSC3_TX_SIZE
+#define CONSOLE_FIFO_TX_ADDR	FIFOC_PSC3_TX_ADDR
+#define CONSOLE_FIFO_RX_SIZE	FIFOC_PSC3_RX_SIZE
+#define CONSOLE_FIFO_RX_ADDR	FIFOC_PSC3_RX_ADDR
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef  CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/* I2C */
+#define CONFIG_HARD_I2C			/* I2C with hardware support */
+#undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed */
+#define CONFIG_SYS_I2C_SLAVE		0x7F	/* slave address */
+
+/*
+ * IIM - IC Identification Module
+ */
+#undef CONFIG_IIM
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* 16-bit EEPROM address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* Atmel: AT24C32A-10TQ-2.7 */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10	/* 10ms of delay */
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5	/* 32-Byte Page Write Mode */
+#define CONFIG_SYS_EEPROM_WREN			/* Use EEPROM write protect */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC512x_FEC	1
+#define CONFIG_NET_MULTI
+#define CONFIG_PHY_ADDR		0x1
+#define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
+
+/*
+ * Configure on-board RTC
+ */
+#define CONFIG_SYS_RTC_BUS_NUM  0x01
+#define CONFIG_SYS_I2C_RTC_ADDR 0x32
+#define CONFIG_RTC_RX8025
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_EEPROM		/* Store env in I2C EEPROM	*/
+#define CONFIG_ENV_SIZE		0x1000
+#define CONFIG_ENV_OFFSET       0x0000	/* environment starts here	*/
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download	*/
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change	*/
+
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
+#undef CONFIG_CMD_FUSE
+#undef CONFIG_CMD_IDE
+#undef CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_ELF
+#define CONFIG_DOS_PARTITION
+
+/*
+ * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
+ * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
+ * to 0xFFFF, watchdog timeouts after about 64s. For details refer
+ * to chapter 36 of the MPC5121e Reference Manual.
+ */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
+#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
+
+ /*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+
+#ifdef CONFIG_CMD_KGDB
+# define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+# define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
+				 sizeof(CONFIG_SYS_PROMPT) + 16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS	32
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_HZ		1000
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Linux initial memory map */
+
+/* Cache Configuration */
+#define CONFIG_SYS_DCACHE_SIZE		32768
+#define CONFIG_SYS_CACHELINE_SIZE	32
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CACHELINE_SHIFT	5
+#endif
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
+#define CONFIG_SYS_HID2		HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_TIMESTAMP
+
+#define CONFIG_HOSTNAME		mecp512x
+#define CONFIG_BOOTFILE		/tftpboot/mecp512x/uImage
+#define CONFIG_ROOTPATH		/tftpboot/mecp512x/target_root
+
+#define CONFIG_LOADADDR		400000	/* def. location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS			/* the boot command will set bootargs*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Welcome to MECP5123" \
+	"echo"
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=600000\0"					\
+	"fdt_addr_r=880000\0"						\
+	"ramdisk_addr_r=900000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FFC40000\0"					\
+	"fdt_addr=FFEC0000\0"						\
+	"ramdisk_addr=FC040000\0"					\
+	"ramdiskfile=/tftpboot/mecp512x/uRamdisk\0"			\
+	"u-boot=/tftpboot/mecp512x/u-boot.bin\0"			\
+	"bootfile=/tftpboot/mecp512x/uImage\0"				\
+	"fdtfile=/tftpboot/mecp512x/mecp512x.dtb\0"			\
+	"rootpath=/tftpboot/mecp512x/target_root\n"	      		\
+	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
+	"flash_nfs=run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"flash_self=run ramargs addip addtty;"				\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 229549a56d9ae413c00f64fd7c728c6879a1b54b Mon Sep 17 00:00:00 2001
From: Stefan Roese <sr@denx.de>
Date: Tue, 9 Jun 2009 16:57:47 +0200
Subject: mpc512x: MPC5121ADS: Add NAND support

This patch adds NAND support to the MPC5121ADS board. Please
note that the image size increased since NAND support didn't
fit in the current image size (256k).

Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
---
 board/freescale/mpc5121ads/mpc5121ads.c | 41 +++++++++++++++++++++++++++------
 include/configs/mpc5121ads.h            | 22 +++++++++++++++++-
 2 files changed, 55 insertions(+), 8 deletions(-)

(limited to 'include')

diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c
index 102e6ff8be9..ec74fd35d2d 100644
--- a/board/freescale/mpc5121ads/mpc5121ads.c
+++ b/board/freescale/mpc5121ads/mpc5121ads.c
@@ -31,6 +31,9 @@
 #include <i2c.h>
 #endif
 
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+
 DECLARE_GLOBAL_DATA_PTR;
 
 extern int mpc5121_diu_init(void);
@@ -38,24 +41,48 @@ extern void ide_set_reset(int idereset);
 
 /* Clocks in use */
 #define SCCR1_CLOCKS_EN	(CLOCK_SCCR1_CFG_EN |				\
-			 CLOCK_SCCR1_LPC_EN |				\
-			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
-			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_DDR_EN |				\
 			 CLOCK_SCCR1_FEC_EN |				\
+			 CLOCK_SCCR1_LPC_EN |				\
+			 CLOCK_SCCR1_NFC_EN |				\
 			 CLOCK_SCCR1_PATA_EN |				\
 			 CLOCK_SCCR1_PCI_EN |				\
+			 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |	\
+			 CLOCK_SCCR1_PSCFIFO_EN |			\
 			 CLOCK_SCCR1_TPR_EN)
 
-#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_MEM_EN |		\
-			 CLOCK_SCCR2_SPDIF_EN |		\
-			 CLOCK_SCCR2_DIU_EN |		\
-			 CLOCK_SCCR2_I2C_EN)
+#define SCCR2_CLOCKS_EN	(CLOCK_SCCR2_DIU_EN |		\
+			 CLOCK_SCCR2_I2C_EN |		\
+			 CLOCK_SCCR2_MEM_EN |		\
+			 CLOCK_SCCR2_SPDIF_EN)
 
 #define CSAW_START(start)	((start) & 0xFFFF0000)
 #define CSAW_STOP(start, size)	(((start) + (size) - 1) >> 16)
 
 long int fixed_sdram(void);
+void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip);
+
+/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */
+extern int mpc5121_nfc_chip;
+
+/* Control chips select signal on MPC5121ADS board */
+void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09;
+	u8 v;
+
+	v = in_8(csreg);
+	v |= 0x0F;
+
+	if (chip >= 0) {
+		__mpc5121_nfc_select_chip(mtd, 0);
+		v &= ~(1 << mpc5121_nfc_chip);
+	} else {
+		__mpc5121_nfc_select_chip(mtd, -1);
+	}
+
+	out_8(csreg, v);
+}
 
 int board_early_init_f (void)
 {
diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h
index dff7f1a4f12..45a004eb2c2 100644
--- a/include/configs/mpc5121ads.h
+++ b/include/configs/mpc5121ads.h
@@ -199,6 +199,26 @@
 
 #undef CONFIG_SYS_FLASH_CHECKSUM
 
+/*
+ * NAND FLASH
+ * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only)
+ */
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_MPC5121_NFC
+#define CONFIG_SYS_NAND_BASE            0x40000000
+
+#define CONFIG_SYS_MAX_NAND_DEVICE      2
+#define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
+#define CONFIG_SYS_NAND_SELECT_DEVICE	/* driver supports mutipl. chips */
+
+/*
+ * Configuration parameters for MPC5121 NAND driver
+ */
+#define CONFIG_FSL_NFC_WIDTH 1
+#define CONFIG_FSL_NFC_WRITE_SIZE 2048
+#define CONFIG_FSL_NFC_SPARE_SIZE 64
+#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
+
 /*
  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
  * window is 64KB
@@ -222,7 +242,7 @@
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)		/* Reserve 512 kB for Mon */
 #ifdef	CONFIG_FSL_DIU_FB
 #define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
 #else
-- 
cgit v1.3.1


From feb7838f979ec2b581df3c791b9ae3284c36bb47 Mon Sep 17 00:00:00 2001
From: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Date: Fri, 3 Apr 2009 15:36:13 -0500
Subject: 85xx: Add P2020DS support

The patch adds support for P2020DS reference platform.
DDR3 interface uses hard-coded initialization rather than SPD
for now and was tested at 667Mhz. Some PIXIS register
definitions and associated code sections need to be fixed.
TSEC1/2/3, NOR flash, MAC/SYS ID EEPROM, PCIE1/2/3 are all
tested under u-boot.

Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 MAKEALL                            |   2 +
 Makefile                           |   9 +
 board/freescale/p2020ds/Makefile   |  54 +++
 board/freescale/p2020ds/config.mk  |  32 ++
 board/freescale/p2020ds/ddr.c      | 130 +++++++
 board/freescale/p2020ds/law.c      |  42 +++
 board/freescale/p2020ds/p2020ds.c  | 634 +++++++++++++++++++++++++++++++
 board/freescale/p2020ds/tlb.c      |  95 +++++
 board/freescale/p2020ds/u-boot.lds | 143 +++++++
 include/configs/P2020DS.h          | 741 +++++++++++++++++++++++++++++++++++++
 10 files changed, 1882 insertions(+)
 create mode 100644 board/freescale/p2020ds/Makefile
 create mode 100644 board/freescale/p2020ds/config.mk
 create mode 100644 board/freescale/p2020ds/ddr.c
 create mode 100644 board/freescale/p2020ds/law.c
 create mode 100644 board/freescale/p2020ds/p2020ds.c
 create mode 100644 board/freescale/p2020ds/tlb.c
 create mode 100644 board/freescale/p2020ds/u-boot.lds
 create mode 100644 include/configs/P2020DS.h

(limited to 'include')

diff --git a/MAKEALL b/MAKEALL
index f48a08e579b..344a8ecfb97 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -382,6 +382,8 @@ LIST_85xx="		\
 	MPC8569MDS	\
 	MPC8572DS	\
 	MPC8572DS_36BIT	\
+	P2020DS		\
+	P2020DS_36BIT	\
 	PM854		\
 	PM856		\
 	sbc8540		\
diff --git a/Makefile b/Makefile
index aa4646f4c16..89808e51ed9 100644
--- a/Makefile
+++ b/Makefile
@@ -2481,6 +2481,15 @@ MPC8572DS_config:       unconfig
 	fi
 	@$(MKCONFIG) -a MPC8572DS ppc mpc85xx mpc8572ds freescale
 
+P2020DS_36BIT_config \
+P2020DS_config:		unconfig
+	@mkdir -p $(obj)include
+	@if [ "$(findstring _36BIT_,$@)" ] ; then \
+		echo "#define CONFIG_PHYS_64BIT" >>$(obj)include/config.h ; \
+		$(XECHO) "... enabling 36-bit physical addressing." ; \
+	fi
+	@$(MKCONFIG) -a P2020DS ppc mpc85xx p2020ds freescale
+
 PM854_config:	unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854
 
diff --git a/board/freescale/p2020ds/Makefile b/board/freescale/p2020ds/Makefile
new file mode 100644
index 00000000000..41032ace426
--- /dev/null
+++ b/board/freescale/p2020ds/Makefile
@@ -0,0 +1,54 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+# (C) Copyright 2001-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p2020ds/config.mk b/board/freescale/p2020ds/config.mk
new file mode 100644
index 00000000000..18bdc86ca73
--- /dev/null
+++ b/board/freescale/p2020ds/config.mk
@@ -0,0 +1,32 @@
+#
+# Copyright 2007-2009 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# p2020ds board
+#
+ifndef TEXT_BASE
+TEXT_BASE = 0xeff80000
+endif
+
+PLATFORM_CPPFLAGS += -DCONFIG_E500=1
+PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1
+PLATFORM_CPPFLAGS += -DCONFIG_P2020=1
diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c
new file mode 100644
index 00000000000..b9c0cb2576b
--- /dev/null
+++ b/board/freescale/p2020ds/ddr.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+static void get_spd(ddr3_spd_eeprom_t *spd, unsigned char i2c_address)
+{
+	i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr3_spd_eeprom_t));
+}
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd,
+		      unsigned int ctrl_num)
+{
+	unsigned int i;
+	unsigned int i2c_address = 0;
+
+	for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
+		if (ctrl_num == 0 && i == 0)
+			i2c_address = SPD_EEPROM_ADDRESS1;
+		get_spd(&(ctrl_dimms_spd[i]), i2c_address);
+	}
+}
+
+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+} board_specific_parameters_t;
+
+/* ranges for parameters:
+ *  wr_data_delay = 0-6
+ *  clk adjust = 0-8
+ *  cpo 2-0x1E (30)
+ */
+
+
+/* XXX: these values need to be checked for all interleaving modes.  */
+/* XXX: No reliable dual-rank 800 MHz setting has been found.  It may
+ *      seem reliable, but errors will appear when memory intensive
+ *      program is run. */
+/* XXX: Single rank at 800 MHz is OK.  */
+const board_specific_parameters_t board_specific_parameters[][20] = {
+	{
+	/* 	memory controller 0 			*/
+	/*	  lo|  hi|  num|  clk| cpo|wrdata|2T	*/
+	/*	 mhz| mhz|ranks|adjst|    | delay|	*/
+		{  0, 333,    2,    6,   7,    3,  0},
+		{334, 400,    2,    6,   9,    3,  0},
+		{401, 549,    2,    6,  11,    3,  0},
+		{550, 680,    2,    1,  10,    5,  0},
+		{681, 850,    2,    1,  12,    5,  1},
+		{  0, 333,    1,    6,   7,    3,  0},
+		{334, 400,    1,    6,   9,    3,  0},
+		{401, 549,    1,    6,  11,    3,  0},
+		{550, 680,    1,    1,  10,    5,  0},
+		{681, 850,    1,    1,  12,    5,  0}
+	},
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const board_specific_parameters_t *pbsp =
+				&(board_specific_parameters[ctrl_num][0]);
+	u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
+				sizeof(board_specific_parameters[0][0]);
+	u32 i;
+	ulong ddr_freq;
+
+	/* set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in
+	 * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If
+	 * there are two dimms in the controller, set odt_rd_cfg to 3 and
+	 * odt_wr_cfg to 3 for the even CS, 0 for the odd CS.
+	 */
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (i&1) {	/* odd CS */
+			popts->cs_local_opts[i].odt_rd_cfg = 0;
+			popts->cs_local_opts[i].odt_wr_cfg = 0;
+		} else {	/* even CS */
+			if (CONFIG_DIMM_SLOTS_PER_CTLR == 1) {
+				popts->cs_local_opts[i].odt_rd_cfg = 0;
+				popts->cs_local_opts[i].odt_wr_cfg = 4;
+			} else if (CONFIG_DIMM_SLOTS_PER_CTLR == 2) {
+				popts->cs_local_opts[i].odt_rd_cfg = 3;
+				popts->cs_local_opts[i].odt_wr_cfg = 3;
+			}
+		}
+	}
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	for (i = 0; i < num_params; i++) {
+		if (ddr_freq >= pbsp->datarate_mhz_low &&
+		    ddr_freq <= pbsp->datarate_mhz_high &&
+		    pdimm->n_ranks == pbsp->n_ranks) {
+			popts->clk_adjust = pbsp->clk_adjust;
+			popts->cpo_override = pbsp->cpo;
+			popts->write_data_delay = pbsp->write_data_delay;
+			popts->twoT_en = pbsp->force_2T;
+		}
+		pbsp++;
+	}
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+}
diff --git a/board/freescale/p2020ds/law.c b/board/freescale/p2020ds/law.c
new file mode 100644
index 00000000000..da297c5ab81
--- /dev/null
+++ b/board/freescale/p2020ds/law.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
new file mode 100644
index 00000000000..6b72d61426f
--- /dev/null
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -0,0 +1,634 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/io.h>
+#include <miiphy.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <tsec.h>
+#include <asm/fsl_law.h>
+#include <asm/mp.h>
+
+#include "../common/pixis.h"
+#include "../common/sgmii_riser.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+phys_size_t fixed_sdram(void);
+
+int checkboard(void)
+{
+	puts("Board: P2020DS ");
+#ifdef CONFIG_PHYS_64BIT
+	puts("(36-bit addrmap) ");
+#endif
+	printf("Sys ID: 0x%02x, "
+		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
+		in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
+		in8(PIXIS_BASE + PIXIS_PVER));
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size = 0;
+
+	puts("Initializing....");
+
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram();
+
+	if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
+			 dram_size,
+			 LAW_TRGT_IF_DDR) < 0) {
+		printf("ERROR setting Local Access Windows for DDR\n");
+		return 0;
+	};
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
+
+#if !defined(CONFIG_SPD_EEPROM)
+/*
+ * Fixed sdram init -- doesn't use serial presence detect.
+ */
+
+phys_size_t fixed_sdram(void)
+{
+	volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	uint d_init;
+
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
+	ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
+	ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
+	ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
+	ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
+	ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
+
+	if (!strcmp("performance", getenv("perf_mode"))) {
+		/* Performance Mode Values */
+
+		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
+		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
+		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
+
+		asm("sync;isync");
+
+		udelay(500);
+
+		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
+	} else {
+		/* Stable Mode Values */
+
+		ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+		ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+		ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+		ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+		ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+
+		/* ECC will be assumed in stable mode */
+		ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+		ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+		ddr->err_sbe = CONFIG_SYS_DDR_SBE;
+
+		asm("sync;isync");
+
+		udelay(500);
+
+		ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
+	}
+
+#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	d_init = 1;
+	debug("DDR - 1st controller: memory initializing\n");
+	/*
+	 * Poll until memory is initialized.
+	 * 512 Meg at 400 might hit this 200 times or so.
+	 */
+	while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
+		udelay(1000);
+	debug("DDR: memory initialized\n\n");
+	asm("sync; isync");
+	udelay(500);
+#endif
+
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+}
+
+#endif
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif
+
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif
+
+#ifdef CONFIG_PCIE3
+static struct pci_controller pcie3_hose;
+#endif
+
+int first_free_busno = 0;
+
+#ifdef CONFIG_PCI
+void pci_init_board(void)
+{
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint devdisr = gur->devdisr;
+	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
+
+	volatile ccsr_fsl_pci_t *pci;
+	struct pci_controller *hose;
+	int pcie_ep, pcie_configured;
+	struct pci_region *r;
+/*		u32 temp32; */
+
+	debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
+			devdisr, io_sel, host_agent);
+
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		printf("    eTSEC2 is in sgmii mode.\n");
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+		printf("    eTSEC3 is in sgmii mode.\n");
+
+#ifdef CONFIG_PCIE2
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
+	hose = &pcie2_hose;
+	pcie_ep = (host_agent == 2) || (host_agent == 4) ||
+		  (host_agent == 6) || (host_agent == 0);
+	pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
+	r = hose->regions;
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+		printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
+				pcie_ep ? "End Point" : "Root Complex",
+				(uint)pci);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE2_MEM_BUS,
+				CONFIG_SYS_PCIE2_MEM_PHYS,
+				CONFIG_SYS_PCIE2_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE2_IO_BUS,
+				CONFIG_SYS_PCIE2_IO_PHYS,
+				CONFIG_SYS_PCIE2_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				  (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+		first_free_busno = hose->last_busno+1;
+		printf("    PCIE2 on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+
+		/*
+		 * The workaround doesn't work on p2020 because the location
+		 * we try and read isn't valid on p2020, fix this later
+		 */
+#if 0
+		/*
+		 * Activate ULI1575 legacy chip by performing a fake
+		 * memory access.  Needed to make ULI RTC work.
+		 * Device 1d has the first on-board memory BAR.
+		 */
+
+		pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
+				PCI_BASE_ADDRESS_1, &temp32);
+		if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
+			void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
+							temp32, 4, 0);
+			debug(" uli1575 read to %p\n", p);
+			in_be32(p);
+		}
+#endif
+	} else {
+		printf("    PCIE2: disabled\n");
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE3
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
+	hose = &pcie3_hose;
+	pcie_ep = (host_agent == 0) || (host_agent == 3) ||
+		(host_agent == 5) || (host_agent == 6);
+	pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
+	r = hose->regions;
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
+		printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
+				pcie_ep ? "End Point" : "Root Complex",
+				(uint)pci);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE3_MEM_BUS,
+				CONFIG_SYS_PCIE3_MEM_PHYS,
+				CONFIG_SYS_PCIE3_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE3_IO_BUS,
+				CONFIG_SYS_PCIE3_IO_PHYS,
+				CONFIG_SYS_PCIE3_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+		hose->first_busno = first_free_busno;
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				  (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno = hose->last_busno+1;
+		printf("    PCIE3 on bus %02x - %02x\n",
+				hose->first_busno, hose->last_busno);
+
+	} else {
+		printf("    PCIE3: disabled\n");
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
+#endif
+
+#ifdef CONFIG_PCIE1
+	pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
+	hose = &pcie1_hose;
+	pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
+	pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
+	r = hose->regions;
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+		printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
+				pcie_ep ? "End Point" : "Root Complex",
+				(uint)pci);
+		if (pci->pme_msg_det) {
+			pci->pme_msg_det = 0xffffffff;
+			debug(" with errors.  Clearing.  Now 0x%08x",
+				pci->pme_msg_det);
+		}
+		printf("\n");
+
+		/* inbound */
+		r += fsl_pci_setup_inbound_windows(r);
+
+		/* outbound memory */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_MEM_BUS,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
+				PCI_REGION_MEM);
+
+		/* outbound io */
+		pci_set_region(r++,
+				CONFIG_SYS_PCIE1_IO_BUS,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
+				PCI_REGION_IO);
+
+		hose->region_count = r - hose->regions;
+		hose->first_busno = first_free_busno;
+
+		pci_setup_indirect(hose, (int)&pci->cfg_addr,
+				  (int)&pci->cfg_data);
+
+		fsl_pci_init(hose);
+
+		first_free_busno = hose->last_busno+1;
+		printf("    PCIE1 on bus %02x - %02x\n",
+			hose->first_busno, hose->last_busno);
+
+	} else {
+		printf("    PCIE1: disabled\n");
+	}
+#else
+	gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
+#endif
+}
+#endif
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = 2;
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	return 0;
+}
+
+#ifdef CONFIG_GET_CLK_FROM_ICS307
+/* decode S[0-2] to Output Divider (OD) */
+static unsigned char ics307_S_to_OD[] = {
+	10, 2, 8, 4, 5, 7, 3, 6
+};
+
+/* Calculate frequency being generated by ICS307-02 clock chip based upon
+ * the control bytes being programmed into it. */
+/* XXX: This function should probably go into a common library */
+static unsigned long
+ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
+{
+	const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
+	unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
+	unsigned long RDW = cw2 & 0x7F;
+	unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
+	unsigned long freq;
+
+	/* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
+
+	/* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
+	 * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
+	 * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
+	 *
+	 * R6:R0 = Reference Divider Word (RDW)
+	 * V8:V0 = VCO Divider Word (VDW)
+	 * S2:S0 = Output Divider Select (OD)
+	 * F1:F0 = Function of CLK2 Output
+	 * TTL = duty cycle
+	 * C1:C0 = internal load capacitance for cyrstal
+	 */
+
+	/* Adding 1 to get a "nicely" rounded number, but this needs
+	 * more tweaking to get a "properly" rounded number. */
+
+	freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
+
+	debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
+			freq);
+	return freq;
+}
+
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	return gd->bus_clk;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
+unsigned long
+calculate_board_sys_clk(ulong dummy)
+{
+	ulong val;
+	val = ics307_clk_freq(
+	    in8(PIXIS_BASE + PIXIS_VSYSCLK0),
+	    in8(PIXIS_BASE + PIXIS_VSYSCLK1),
+	    in8(PIXIS_BASE + PIXIS_VSYSCLK2));
+	debug("sysclk val = %lu\n", val);
+	return val;
+}
+
+unsigned long
+calculate_board_ddr_clk(ulong dummy)
+{
+	ulong val;
+	val = ics307_clk_freq(
+	    in8(PIXIS_BASE + PIXIS_VDDRCLK0),
+	    in8(PIXIS_BASE + PIXIS_VDDRCLK1),
+	    in8(PIXIS_BASE + PIXIS_VDDRCLK2));
+	debug("ddrclk val = %lu\n", val);
+	return val;
+}
+#else
+unsigned long get_board_sys_clk(ulong dummy)
+{
+	u8 i;
+	ulong val = 0;
+
+	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i &= 0x07;
+
+	switch (i) {
+		case 0:
+			val = 33333333;
+			break;
+		case 1:
+			val = 40000000;
+			break;
+		case 2:
+			val = 50000000;
+			break;
+		case 3:
+			val = 66666666;
+			break;
+		case 4:
+			val = 83333333;
+			break;
+		case 5:
+			val = 100000000;
+			break;
+		case 6:
+			val = 133333333;
+			break;
+		case 7:
+			val = 166666666;
+			break;
+	}
+
+	return val;
+}
+
+unsigned long get_board_ddr_clk(ulong dummy)
+{
+	u8 i;
+	ulong val = 0;
+
+	i = in8(PIXIS_BASE + PIXIS_SPD);
+	i &= 0x38;
+	i >>= 3;
+
+	switch (i) {
+		case 0:
+			val = 33333333;
+			break;
+		case 1:
+			val = 40000000;
+			break;
+		case 2:
+			val = 50000000;
+			break;
+		case 3:
+			val = 66666666;
+			break;
+		case 4:
+			val = 83333333;
+			break;
+		case 5:
+			val = 100000000;
+			break;
+		case 6:
+			val = 133333333;
+			break;
+		case 7:
+			val = 166666666;
+			break;
+	}
+	return val;
+}
+#endif
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[4];
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_init(tsec_info, num);
+#endif
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCIE3
+	ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
+#endif
+#ifdef CONFIG_PCIE2
+	ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
+#endif
+#ifdef CONFIG_PCIE1
+	ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
+#endif
+#ifdef CONFIG_FSL_SGMII_RISER
+	fsl_sgmii_riser_fdt_fixup(blob);
+#endif
+}
+#endif
+
+#ifdef CONFIG_MP
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p2020ds/tlb.c b/board/freescale/p2020ds/tlb.c
new file mode 100644
index 00000000000..b2e562aeb10
--- /dev/null
+++ b/board/freescale/p2020ds/tlb.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc.
+ *
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+	/* W**G* - Flash/promjet, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_1G, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
+		      CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 7, BOOKE_PAGESZ_1M, 1),
+
+	SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_4K, 1),
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/board/freescale/p2020ds/u-boot.lds b/board/freescale/p2020ds/u-boot.lds
new file mode 100644
index 00000000000..d6e22a7210e
--- /dev/null
+++ b/board/freescale/p2020ds/u-boot.lds
@@ -0,0 +1,143 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_ARCH(powerpc)
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+PHDRS
+{
+  text PT_LOAD;
+  bss PT_LOAD;
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  . = + SIZEOF_HEADERS;
+  .interp : { *(.interp) }
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .rel.text      : { *(.rel.text)		}
+  .rela.text     : { *(.rela.text)	}
+  .rel.data      : { *(.rel.data)		}
+  .rela.data     : { *(.rela.data)	}
+  .rel.rodata    : { *(.rel.rodata)	}
+  .rela.rodata   : { *(.rela.rodata)	}
+  .rel.got       : { *(.rel.got)		}
+  .rela.got      : { *(.rela.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rela.ctors    : { *(.rela.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rela.dtors    : { *(.rela.dtors)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rela.bss      : { *(.rela.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .rela.plt      : { *(.rela.plt)		}
+  .init          : { *(.init)	}
+  .plt : { *(.plt) }
+  .text      :
+  {
+    *(.text)
+    *(.fixup)
+    *(.got1)
+   } :text
+    _etext = .;
+    PROVIDE (etext = .);
+    .rodata    :
+   {
+    *(.eh_frame)
+    *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+  } :text
+  .fini      : { *(.fini)    } =0
+  .ctors     : { *(.ctors)   }
+  .dtors     : { *(.dtors)   }
+
+  /* Read-write section, merged into data segment: */
+  . = (. + 0x00FF) & 0xFFFFFF00;
+  _erotext = .;
+  PROVIDE (erotext = .);
+  .reloc   :
+  {
+    *(.got)
+    _GOT2_TABLE_ = .;
+    *(.got2)
+    _FIXUP_TABLE_ = .;
+    *(.fixup)
+  }
+  __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
+  __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
+
+  .data    :
+  {
+    *(.data)
+    *(.data1)
+    *(.sdata)
+    *(.sdata2)
+    *(.dynamic)
+    CONSTRUCTORS
+  }
+  _edata  =  .;
+  PROVIDE (edata = .);
+
+  . = .;
+  __u_boot_cmd_start = .;
+  .u_boot_cmd : { *(.u_boot_cmd) }
+  __u_boot_cmd_end = .;
+
+  . = .;
+  __start___ex_table = .;
+  __ex_table : { *(__ex_table) }
+  __stop___ex_table = .;
+
+  . = ALIGN(256);
+  __init_begin = .;
+  .text.init : { *(.text.init) }
+  .data.init : { *(.data.init) }
+  . = ALIGN(256);
+  __init_end = .;
+
+  .bootpg ADDR(.text) + 0x7f000 :
+  {
+    cpu/mpc85xx/start.o	(.bootpg)
+  } :text = 0xffff
+
+  .resetvec ADDR(.text) + 0x7fffc :
+  {
+    *(.resetvec)
+  } :text = 0xffff
+
+  . = ADDR(.text) + 0x80000;
+
+  __bss_start = .;
+  .bss (NOLOAD)       :
+  {
+   *(.sbss) *(.scommon)
+   *(.dynbss)
+   *(.bss)
+   *(COMMON)
+  } :bss
+
+  . = ALIGN(4);
+  _end = . ;
+  PROVIDE (end = .);
+}
diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h
new file mode 100644
index 00000000000..a39ff26a7a2
--- /dev/null
+++ b/include/configs/P2020DS.h
@@ -0,0 +1,741 @@
+/*
+ * Copyright 2007-2009 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * p2020ds board configuration file
+ *
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE		1	/* BOOKE */
+#define CONFIG_E500		1	/* BOOKE e500 family */
+#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41/48 */
+#define CONFIG_P2020		1
+#define CONFIG_P2020DS		1
+#define CONFIG_MP		1	/* support multiple processors */
+#define CONFIG_NUM_CPUS		2	/* Number of CPUs in the system */
+
+#define CONFIG_FSL_ELBC		1	/* Has Enhanced localbus controller */
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		1	/* PCIE controler 1 (slot 1) */
+#define CONFIG_PCIE2		1	/* PCIE controler 2 (slot 2) */
+#define CONFIG_PCIE3		1	/* PCIE controler 3 (ULI bridge) */
+#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
+
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
+
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * When initializing flash, if we cannot find the manufacturer ID,
+ * assume this is the AMD flash associated with the CDS board.
+ * This allows booting from a promjet.
+ */
+#define CONFIG_ASSUME_AMD_FLASH
+
+#ifndef __ASSEMBLY__
+extern unsigned long calculate_board_sys_clk(unsigned long dummy);
+extern unsigned long calculate_board_ddr_clk(unsigned long dummy);
+/* extern unsigned long get_board_sys_clk(unsigned long dummy); */
+/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */
+#endif
+#define CONFIG_SYS_CLK_FREQ	calculate_board_sys_clk(0) /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */
+#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */
+#define CONFIG_GET_CLK_FROM_ICS307	  /* decode sysclk and ddrclk freq
+					     from ICS307 instead of switches */
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE			/* toggle L2 cache */
+#define CONFIG_BTB			/* toggle branch predition */
+
+#define CONFIG_ENABLE_36BIT_PHYS	1
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP			1
+#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
+#endif
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x7fffffff
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull	/* physical addr of CCSRBAR */
+#else
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
+#endif
+#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR */
+
+#define CONFIG_SYS_PCIE3_ADDR		(CONFIG_SYS_CCSRBAR+0x8000)
+#define CONFIG_SYS_PCIE2_ADDR		(CONFIG_SYS_CCSRBAR+0x9000)
+#define CONFIG_SYS_PCIE1_ADDR		(CONFIG_SYS_CCSRBAR+0xa000)
+
+/* DDR Setup */
+#define CONFIG_SYS_DDR_TLB_START 9
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_FSL_DDR3		1
+#undef CONFIG_FSL_DDR_INTERACTIVE
+
+// #define	CONFIG_DDR_ECC /* ECC will be enabled based on perf_mode environment variable */
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define CONFIG_SYS_SPD_BUS_NUM		0	/* SPD EEPROM located on I2C bus 0 */
+#define SPD_EEPROM_ADDRESS1	0x51	/* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+//#define CONFIG_SYS_SDRAM_SIZE		512		/* DDR is 512MB */
+#define CONFIG_SYS_SDRAM_SIZE		1024		/* DDR is 1GB */
+
+/* Default settings for "stable" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS		0x0000003F
+#define CONFIG_SYS_DDR_CS1_BNDS		0x00000000
+#define CONFIG_SYS_DDR_CS0_CONFIG	0x80014202
+#define CONFIG_SYS_DDR_CS1_CONFIG	0x00000000
+#define CONFIG_SYS_DDR_TIMING_3		0x00020000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330804
+#define CONFIG_SYS_DDR_TIMING_1		0x6f6b4846
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa890d4
+#define CONFIG_SYS_DDR_MODE_1		0x00421422
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_MODE_CTRL	0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x61800100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x02000000
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x8655A608
+#define CONFIG_SYS_DDR_CONTROL		0xE7000000 /* Type = DDR3: ECC enabled, No Interleaving */
+#define CONFIG_SYS_DDR_CONTROL2		0x24400011
+#define CONFIG_SYS_DDR_CDR1		0x00040000
+#define CONFIG_SYS_DDR_CDR2		0x00000000
+
+#define CONFIG_SYS_DDR_ERR_INT_EN	0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS		0x00000000
+#define CONFIG_SYS_DDR_SBE		0x00010000
+
+/* Settings that differ for "performance" mode */
+#define CONFIG_SYS_DDR_CS0_BNDS_PERF		0x0000007F /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_BNDS_PERF		0x00000000 /* Interleaving Enabled */
+#define CONFIG_SYS_DDR_CS1_CONFIG_PERF	0x80014202
+#define CONFIG_SYS_DDR_TIMING_1_PERF		0x5d5b4543
+#define CONFIG_SYS_DDR_TIMING_2_PERF		0x0fa890ce
+#define CONFIG_SYS_DDR_CONTROL_PERF		0xC7004000 /* Type = DDR3: ECC disabled, cs0-cs1 interleaving */
+
+/*
+ * The following set of values were tested for DDR2
+ * with a DDR3 to DDR2 interposer
+ *
+#define CONFIG_SYS_DDR_TIMING_3		0x00000000
+#define CONFIG_SYS_DDR_TIMING_0		0x00260802
+#define CONFIG_SYS_DDR_TIMING_1		0x3935d322
+#define CONFIG_SYS_DDR_TIMING_2		0x14904cc8
+#define CONFIG_SYS_DDR_MODE_1		0x00480432
+#define CONFIG_SYS_DDR_MODE_2		0x00000000
+#define CONFIG_SYS_DDR_INTERVAL		0x06180100
+#define CONFIG_SYS_DDR_DATA_INIT	0xdeadbeef
+#define CONFIG_SYS_DDR_CLK_CTRL		0x03800000
+#define CONFIG_SYS_DDR_OCD_CTRL		0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS	0x00000000
+#define CONFIG_SYS_DDR_CONTROL		0xC3008000
+#define CONFIG_SYS_DDR_CONTROL2		0x04400010
+ *
+ */
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
+ * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
+ * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
+ * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
+ *
+ * Localbus cacheable (TBD)
+ * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
+ *
+ * Localbus non-cacheable
+ * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
+ * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
+ * 0xffa0_0000	0xffaf_ffff	NAND			1M non-cacheable
+ * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
+ * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
+ * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
+ */
+
+/*
+ * Local Bus Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE		0xe0000000	/* start of FLASH 128M */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_FLASH_BR_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
+#define CONFIG_FLASH_OR_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xf8000ff7
+
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024		/* sectors per device */
+#undef	CONFIG_SYS_FLASH_CHECKSUM
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
+
+#define CONFIG_BOARD_EARLY_INIT_R	/* call board_early_init_r function */
+
+#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
+#define PIXIS_BASE	0xffdf0000	/* PIXIS registers */
+#ifdef CONFIG_PHYS_64BIT
+#define PIXIS_BASE_PHYS	0xfffdf0000ull
+#else
+#define PIXIS_BASE_PHYS	PIXIS_BASE
+#endif
+
+#define CONFIG_SYS_BR3_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM		0xffffeff7	/* 32KB but only 4k mapped */
+
+#define PIXIS_ID		0x0	/* Board ID at offset 0 */
+#define PIXIS_VER		0x1	/* Board version at offset 1 */
+#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
+#define PIXIS_CSR		0x3	/* PIXIS General control/status register */
+#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
+#define PIXIS_PWR		0x5	/* PIXIS Power status register */
+#define PIXIS_AUX		0x6	/* Auxiliary 1 register */
+#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
+#define PIXIS_AUX2		0x8	/* Auxiliary 2 register */
+#define PIXIS_VCTL		0x10	/* VELA Control Register */
+#define PIXIS_VSTAT		0x11	/* VELA Status Register */
+#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
+#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
+#define PIXIS_VCORE0		0x14	/* VELA VCORE0 Register */
+#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
+#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
+#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
+#define PIXIS_VSPEED2		0x19	/* VELA VSpeed 2 */
+#define PIXIS_VSYSCLK0		0x19	/* VELA SYSCLK0 Register */
+#define PIXIS_VSYSCLK1		0x1A	/* VELA SYSCLK1 Register */
+#define PIXIS_VSYSCLK2		0x1B	/* VELA SYSCLK2 Register */
+#define PIXIS_VDDRCLK0		0x1C	/* VELA DDRCLK0 Register */
+#define PIXIS_VDDRCLK1		0x1D	/* VELA DDRCLK1 Register */
+#define PIXIS_VDDRCLK2		0x1E	/* VELA DDRCLK2 Register */
+
+#define PIXIS_VWATCH		0x24	/* Watchdog Register */
+#define PIXIS_LED		0x25	/* LED Register */
+
+/* old pixis referenced names */
+#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
+#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	0xc0
+#define PIXIS_VSPEED2_TSEC1SER	0x8
+#define PIXIS_VSPEED2_TSEC2SER	0x4
+#define PIXIS_VSPEED2_TSEC3SER	0x2
+#define PIXIS_VSPEED2_TSEC4SER	0x1
+#define PIXIS_VCFGEN1_TSEC1SER	0x20
+#define PIXIS_VCFGEN1_TSEC2SER	0x20
+#define PIXIS_VCFGEN1_TSEC3SER	0x20
+#define PIXIS_VCFGEN1_TSEC4SER	0x20
+#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER \
+					| PIXIS_VSPEED2_TSEC2SER \
+					| PIXIS_VSPEED2_TSEC3SER \
+					| PIXIS_VSPEED2_TSEC4SER)
+#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER \
+					| PIXIS_VCFGEN1_TSEC2SER \
+					| PIXIS_VCFGEN1_TSEC3SER \
+					| PIXIS_VCFGEN1_TSEC4SER)
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000	/* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_END	0x00004000	/* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
+
+#define CONFIG_SYS_NAND_BASE		0xffa00000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	0xfffa00000ull
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE,\
+				CONFIG_SYS_NAND_BASE + 0x40000, \
+				CONFIG_SYS_NAND_BASE + 0x80000,\
+				CONFIG_SYS_NAND_BASE + 0xC0000}
+#define CONFIG_SYS_MAX_NAND_DEVICE	4
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND			1
+#define CONFIG_NAND_FSL_ELBC		1
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+/* NAND flash config */
+#define CONFIG_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_NAND_OR_PRELIM  (0xFFFC0000		/* length 256K */ \
+				| OR_FCM_PGS		/* Large Page*/ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+
+#define CONFIG_SYS_BR0_PRELIM  CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM  CONFIG_FLASH_OR_PRELIM  /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM  CONFIG_NAND_BR_PRELIM  /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM  CONFIG_NAND_OR_PRELIM  /* NAND Options */
+
+#define CONFIG_SYS_BR4_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR4_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+#define CONFIG_SYS_BR5_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR5_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+
+#define CONFIG_SYS_BR6_PRELIM  (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V)			/* valid */
+#define CONFIG_SYS_OR6_PRELIM  CONFIG_NAND_OR_PRELIM	/* NAND Options */
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef	CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+/*
+ * Pass open firmware flat tree
+ */
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+#define CONFIG_SYS_64BIT_VSPRINTF	1
+#define CONFIG_SYS_64BIT_STRTOUL	1
+
+/* new uImage format support */
+#define CONFIG_FIT		1
+#define CONFIG_FIT_VERBOSE	1 /* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0,0x29}}/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_I2C2_OFFSET		0x3100
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 3, Slot 1, tgtid 3, Base address b000 */
+#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
+#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
+#else
+#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
+#endif
+#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 2, direct to uli, tgtid 2, Base address 9000 */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
+#else
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#endif
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
+
+/* controller 1, Slot 2, tgtid 1, Base address a000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+#if defined(CONFIG_PCI)
+
+/*PCIE video card used*/
+#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE1_IO_VIRT
+
+/* video */
+#define CONFIG_VIDEO
+
+#if defined(CONFIG_VIDEO)
+#define CONFIG_BIOSEMU
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_ATI_RADEON_FB
+#define CONFIG_VIDEO_LOGO
+/*#define CONFIG_CONSOLE_CURSOR*/
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
+#endif
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#undef CONFIG_EEPRO100
+#undef CONFIG_TULIP
+#define CONFIG_RTL8139
+
+#ifdef CONFIG_RTL8139
+/* This macro is used by RTL8139 but not defined in PPC architecture */
+#define KSEG1ADDR(x)		(x)
+#define _IO_BASE	0x00000000
+#endif
+
+#ifndef CONFIG_PCI_PNP
+	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCIE3_IO_BUS
+	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
+#endif
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SCSI_AHCI
+
+#ifdef CONFIG_SCSI_AHCI
+#define CONFIG_SATA_ULI5288
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
+#define CONFIG_SYS_SCSI_MAX_LUN	1
+#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_SYS_SCSI_MAXDEVICE	CONFIG_SYS_SCSI_MAX_DEVICE
+#endif /* SCSI */
+
+#endif	/* CONFIG_PCI */
+
+
+#if defined(CONFIG_TSEC_ENET)
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI	1
+#endif
+
+#define CONFIG_MII		1	/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1	1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2	1
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3	1
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define CONFIG_PIXIS_SGMII_CMD
+#define CONFIG_FSL_SGMII_RISER	1
+#define SGMII_RISER_PHY_OFFSET	0x1b
+
+#ifdef CONFIG_FSL_SGMII_RISER
+#define CONFIG_SYS_TBIPA_VALUE		0x10 /* avoid conflict with eTSEC4 paddr */
+#endif
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC2_PHY_ADDR		1
+#define TSEC3_PHY_ADDR		2
+
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
+#endif	/* CONFIG_TSEC_ENET */
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR		0xfff80000
+#else
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_SCSI
+#define CONFIG_CMD_EXT2
+#endif
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+
+/* The mac addresses for all ethernet interface */
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_ETHADDR	00:E0:0C:02:00:FD
+#define CONFIG_HAS_ETH1
+#define CONFIG_ETH1ADDR	00:E0:0C:02:01:FD
+#define CONFIG_HAS_ETH2
+#define CONFIG_ETH2ADDR	00:E0:0C:02:02:FD
+#define CONFIG_HAS_ETH3
+#define CONFIG_ETH3ADDR	00:E0:0C:02:03:FD
+#endif
+
+#define CONFIG_IPADDR		192.168.1.254
+
+#define CONFIG_HOSTNAME		unknown
+#define CONFIG_ROOTPATH		/opt/nfsroot
+#define CONFIG_BOOTFILE		uImage
+#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
+
+#define CONFIG_SERVERIP		192.168.1.1
+#define CONFIG_GATEWAYIP	192.168.1.1
+#define CONFIG_NETMASK		255.255.255.0
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY 10	/* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */
+
+#define CONFIG_BAUDRATE	115200
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "perf_mode=stable\0"			\
+ "memctl_intlv_ctl=2\0"						\
+ "netdev=eth0\0"						\
+ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+ "tftpflash=tftpboot $loadaddr $uboot; "			\
+	"protect off " MK_STR(TEXT_BASE) " +$filesize; "	\
+	"erase " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; "	\
+	"protect on " MK_STR(TEXT_BASE) " +$filesize; "		\
+	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0"	\
+ "consoledev=ttyS0\0"				\
+ "ramdiskaddr=2000000\0"			\
+ "ramdiskfile=p2020ds/ramdisk.uboot\0"		\
+ "fdtaddr=c00000\0"				\
+ "fdtfile=p2020ds/p2020ds.dtb\0"		\
+ "bdev=sda3\0"
+
+#define CONFIG_HDBOOT				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"			\
+ "tftp $fdtaddr $fdtfile;"			\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND		\
+ "setenv bootargs root=/dev/nfs rw "	\
+ "nfsroot=$serverip:$rootpath "		\
+ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND		\
+ "setenv bootargs root=/dev/ram rw "	\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "tftp $ramdiskaddr $ramdiskfile;"	\
+ "tftp $loadaddr $bootfile;"		\
+ "tftp $fdtaddr $fdtfile;"		\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_HDBOOT
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 71b358cc26792889bbac35054d8e89d59b3fabc4 Mon Sep 17 00:00:00 2001
From: Kumar Gala <galak@kernel.crashing.org>
Date: Wed, 20 May 2009 01:11:33 -0500
Subject: 85xx: Added MPC8535/E identifiers

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c           | 2 ++
 include/asm-ppc/processor.h | 2 ++
 2 files changed, 4 insertions(+)

(limited to 'include')

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index ef976a43fe8..1c3eddfd37d 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -40,6 +40,8 @@ DECLARE_GLOBAL_DATA_PTR;
 struct cpu_type cpu_type_list [] = {
 	CPU_TYPE_ENTRY(8533, 8533),
 	CPU_TYPE_ENTRY(8533, 8533_E),
+	CPU_TYPE_ENTRY(8535, 8535),
+	CPU_TYPE_ENTRY(8535, 8535_E),
 	CPU_TYPE_ENTRY(8536, 8536),
 	CPU_TYPE_ENTRY(8536, 8536_E),
 	CPU_TYPE_ENTRY(8540, 8540),
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 8f73c69e76f..e7db1c6abf5 100644
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -934,6 +934,8 @@
 
 #define SVR_8533	0x803400
 #define SVR_8533_E	0x803C00
+#define SVR_8535	0x803701
+#define SVR_8535_E	0x803F01
 #define SVR_8536	0x803700
 #define SVR_8536_E	0x803F00
 #define SVR_8540	0x803000
-- 
cgit v1.3.1


From b3d7f20f43a0f8d11c65e2f92153b5512b11580c Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 12:30:29 -0400
Subject: 85xx: Add QE clk support

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <Timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c            |  4 ++++
 cpu/mpc85xx/speed.c          | 15 ++++++++++++++-
 include/asm-ppc/immap_85xx.h |  2 ++
 include/e500.h               |  1 +
 4 files changed, 21 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 1c3eddfd37d..8f94bada041 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -186,6 +186,10 @@ int checkcpu (void)
 	printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
 #endif
 
+#ifdef CONFIG_QE
+	printf("       QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE));
+#endif
+
 	puts("L1:    D-cache 32 kB enabled\n       I-cache 32 kB enabled\n");
 
 	return 0;
diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index b0f47e042e9..286b6b28ef2 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2007-2009 Freescale Semiconductor Inc.
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (X.Xiao@motorola.com)
  *
@@ -40,6 +40,9 @@ void get_sys_info (sys_info_t * sysInfo)
 	uint plat_ratio,e500_ratio,half_freqSystemBus;
 	uint lcrr_div;
 	int i;
+#ifdef CONFIG_QE
+	u32 qe_ratio;
+#endif
 
 	plat_ratio = (gur->porpllsr) & 0x0000003e;
 	plat_ratio >>= 1;
@@ -65,6 +68,12 @@ void get_sys_info (sys_info_t * sysInfo)
 	}
 #endif
 
+#ifdef CONFIG_QE
+	qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)
+			>> MPC85xx_PORPLLSR_QE_RATIO_SHIFT;
+	sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
+#endif
+
 #if defined(CONFIG_SYS_LBC_LCRR)
 	/* We will program LCRR to this value later */
 	lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -112,6 +121,10 @@ int get_clocks (void)
 	gd->mem_clk = sys_info.freqDDRBus;
 	gd->lbc_clk = sys_info.freqLocalBus;
 
+#ifdef CONFIG_QE
+	gd->qe_clk = sys_info.freqQE;
+	gd->brg_clk = gd->qe_clk / 2;
+#endif
 	/*
 	 * The base clock for I2C depends on the actual SOC.  Unfortunately,
 	 * there is no pattern that can be used to determine the frequency, so
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 06b4dc31f47..0f9f493d1f3 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1596,6 +1596,8 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
 #endif
+#define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
+#define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA		0x00070000
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
diff --git a/include/e500.h b/include/e500.h
index 4c5eeb74e14..84b580de1f4 100644
--- a/include/e500.h
+++ b/include/e500.h
@@ -18,6 +18,7 @@ typedef struct
   unsigned long freqSystemBus;
   unsigned long freqDDRBus;
   unsigned long freqLocalBus;
+  unsigned long freqQE;
 } MPC85xx_SYS_INFO;
 
 #endif  /* _ASMLANGUAGE */
-- 
cgit v1.3.1


From 7211fbfa18f3061858696150ee6e9e093d9eceae Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Thu, 21 May 2009 15:34:14 -0400
Subject: drivers/qe: Change QE RISC ALLOCATION to support 4 RISCs

Also define the QE_RISC_ALLOCATION_RISCs to MACROs instead of using enum, and
define MAX_QE_RISC for QE based silicons.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 drivers/qe/qe.c            |  3 ---
 drivers/qe/qe.h            | 17 +++++++++++------
 drivers/qe/uec.c           | 32 +++++++++++++++++++++++++++++++-
 drivers/qe/uec.h           |  4 ++--
 include/asm-ppc/immap_qe.h |  8 ++++++++
 5 files changed, 52 insertions(+), 12 deletions(-)

(limited to 'include')

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 918bfa748e0..f5096228d08 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -258,9 +258,6 @@ int qe_set_mii_clk_src(int ucc_num)
 	return 0;
 }
 
-/* The maximum number of RISCs we support */
-#define MAX_QE_RISC     2
-
 /* Firmware information stored here for qe_get_firmware_info() */
 static struct qe_firmware_info qe_firmware_info;
 
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index d78edba23e9..2128f5697e9 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  * based on source code of Shlomi Gridish
@@ -46,11 +46,16 @@ typedef struct qe_snum {
 
 /* QE RISC allocation
 */
-typedef enum qe_risc_allocation {
-	QE_RISC_ALLOCATION_RISC1		= 1,  /* RISC 1 */
-	QE_RISC_ALLOCATION_RISC2		= 2,  /* RISC 2 */
-	QE_RISC_ALLOCATION_RISC1_AND_RISC2	= 3   /* RISC 1 or RISC 2 */
-} qe_risc_allocation_e;
+#define	QE_RISC_ALLOCATION_RISC1	0x1  /* RISC 1 */
+#define	QE_RISC_ALLOCATION_RISC2	0x2  /* RISC 2 */
+#define	QE_RISC_ALLOCATION_RISC3	0x4  /* RISC 3 */
+#define	QE_RISC_ALLOCATION_RISC4	0x8  /* RISC 4 */
+#define	QE_RISC_ALLOCATION_RISC1_AND_RISC2 	(QE_RISC_ALLOCATION_RISC1 | \
+						 QE_RISC_ALLOCATION_RISC2)
+#define	QE_RISC_ALLOCATION_FOUR_RISCS	(QE_RISC_ALLOCATION_RISC1 | \
+					 QE_RISC_ALLOCATION_RISC2 | \
+					 QE_RISC_ALLOCATION_RISC3 | \
+					 QE_RISC_ALLOCATION_RISC4)
 
 /* QE CECR commands for UCC fast.
 */
diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c
index e67c0bab644..d02c8c98e85 100644
--- a/drivers/qe/uec.c
+++ b/drivers/qe/uec.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  *
@@ -46,8 +46,13 @@ static uec_info_t eth1_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC1_PHY_ADDR,
@@ -69,8 +74,13 @@ static uec_info_t eth2_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC2_PHY_ADDR,
@@ -92,8 +102,13 @@ static uec_info_t eth3_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC3_PHY_ADDR,
@@ -115,8 +130,13 @@ static uec_info_t eth4_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC4_PHY_ADDR,
@@ -138,8 +158,13 @@ static uec_info_t eth5_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC5_PHY_ADDR,
@@ -161,8 +186,13 @@ static uec_info_t eth6_uec_info = {
 	.num_threads_tx		= UEC_NUM_OF_THREADS_4,
 	.num_threads_rx		= UEC_NUM_OF_THREADS_4,
 #endif
+#if (MAX_QE_RISC == 4)
+	.risc_tx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+	.risc_rx			= QE_RISC_ALLOCATION_FOUR_RISCS,
+#else
 	.risc_tx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
 	.risc_rx			= QE_RISC_ALLOCATION_RISC1_AND_RISC2,
+#endif
 	.tx_bd_ring_len		= 16,
 	.rx_bd_ring_len		= 16,
 	.phy_address		= CONFIG_SYS_UEC6_PHY_ADDR,
diff --git a/drivers/qe/uec.h b/drivers/qe/uec.h
index 414982cdec9..4fd10962c92 100644
--- a/drivers/qe/uec.h
+++ b/drivers/qe/uec.h
@@ -654,8 +654,8 @@ typedef struct uec_info {
 	ucc_fast_info_t			uf_info;
 	uec_num_of_threads_e		num_threads_tx;
 	uec_num_of_threads_e		num_threads_rx;
-	qe_risc_allocation_e		risc_tx;
-	qe_risc_allocation_e		risc_rx;
+	unsigned int			risc_tx;
+	unsigned int			risc_rx;
 	u16				rx_bd_ring_len;
 	u16				tx_bd_ring_len;
 	u8				phy_address;
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 44c0c0aa12a..41e4583210f 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -607,4 +607,12 @@ extern qe_map_t *qe_immr;
 #define QE_MURAM_SIZE		0x4000UL
 #endif
 
+#if defined(CONFIG_MPC8323)
+#define MAX_QE_RISC     1
+#elif defined(CONFIG_MPC8569)
+#define MAX_QE_RISC     4
+#else
+#define MAX_QE_RISC	2
+#endif
+
 #endif				/* __IMMAP_QE_H__ */
-- 
cgit v1.3.1


From 4e7b25e4fe777f525e426cbd58c3a3976c564f2e Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 12:30:35 -0400
Subject: drivers/qe: Add more SNUM number for QE

Some QE chips like 8569 need more SNUM numbers for supporting 4 UECs in RGMII-
1000 mode.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Acked-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 drivers/qe/qe.c            | 15 ++++++++++++---
 drivers/qe/qe.h            |  1 -
 include/asm-ppc/immap_qe.h |  5 ++++-
 3 files changed, 16 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index f5096228d08..8882c4f6277 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2006 Freescale Semiconductor, Inc.
+ * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
  *
  * Dave Liu <daveliu@freescale.com>
  * based on source code of Shlomi Gridish
@@ -108,14 +108,23 @@ static void qe_sdma_init(void)
 	out_be32(&p->sdmr, QE_SDMR_GLB_1_MSK | (0x3 << QE_SDMR_CEN_SHIFT));
 }
 
-static u8 thread_snum[QE_NUM_OF_SNUM] = {
+/* This table is a list of the serial numbers of the Threads, taken from the
+ * "SNUM Table" chart in the QE Reference Manual. The order is not important,
+ * we just need to know what the SNUMs are for the threads.
+ */
+static u8 thread_snum[] = {
 	0x04, 0x05, 0x0c, 0x0d,
 	0x14, 0x15, 0x1c, 0x1d,
 	0x24, 0x25, 0x2c, 0x2d,
 	0x34, 0x35, 0x88, 0x89,
 	0x98, 0x99, 0xa8, 0xa9,
 	0xb8, 0xb9, 0xc8, 0xc9,
-	0xd8, 0xd9, 0xe8, 0xe9
+	0xd8, 0xd9, 0xe8, 0xe9,
+	0x08, 0x09, 0x18, 0x19,
+	0x28, 0x29, 0x38, 0x39,
+	0x48, 0x49, 0x58, 0x59,
+	0x68, 0x69, 0x78, 0x79,
+	0x80, 0x81
 };
 
 static void qe_snums_init(void)
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index 2128f5697e9..faad43c2f9c 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -25,7 +25,6 @@
 
 #include "common.h"
 
-#define QE_NUM_OF_SNUM	28
 #define QE_NUM_OF_BRGS	16
 #define UCC_MAX_NUM	8
 
diff --git a/include/asm-ppc/immap_qe.h b/include/asm-ppc/immap_qe.h
index 41e4583210f..531cfc891d7 100644
--- a/include/asm-ppc/immap_qe.h
+++ b/include/asm-ppc/immap_qe.h
@@ -3,7 +3,7 @@
  * The Internal Memory Map for devices with QE on them. This
  * is the superset of all QE devices (8360, etc.).
  *
- * Copyright (c) 2006 Freescale Semiconductor, Inc.
+ * Copyright (c) 2006-2009 Freescale Semiconductor, Inc.
  * Author: Shlomi Gridih <gridish@freescale.com>
  *
  * This program is free software; you can redistribute  it and/or modify it
@@ -609,10 +609,13 @@ extern qe_map_t *qe_immr;
 
 #if defined(CONFIG_MPC8323)
 #define MAX_QE_RISC     1
+#define QE_NUM_OF_SNUM	28
 #elif defined(CONFIG_MPC8569)
 #define MAX_QE_RISC     4
+#define QE_NUM_OF_SNUM	46
 #else
 #define MAX_QE_RISC	2
+#define QE_NUM_OF_SNUM	28
 #endif
 
 #endif				/* __IMMAP_QE_H__ */
-- 
cgit v1.3.1


From 750098d33bc362ac4263863e92da158cf011063f Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 12:30:36 -0400
Subject: 85xx: Add UEC3 and UEC4 support for MPC8569MDS

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8569mds/bcsr.c       |  4 ++++
 board/freescale/mpc8569mds/mpc8569mds.c | 30 ++++++++++++++++++++++++++++++
 include/configs/MPC8569MDS.h            | 23 +++++++++++++++++++++++
 3 files changed, 57 insertions(+)

(limited to 'include')

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index f4625972608..17c8478a628 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -41,6 +41,10 @@ void enable_8569mds_qe_mdio()
 			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
 			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
 }
 
 void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 7e6cfb73733..387ecad2cf9 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -77,6 +77,36 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{2,  3, 2, 0, 1}, /* ENET2_GRXCLK              */
 	{2,  2, 1, 0, 2}, /* ENET2_GTXCLK              */
 
+	/* UCC_3_RGMII */
+	{2, 11, 2, 0, 1}, /* CLK12 */
+	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
+	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
+	{0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2      */
+	{1,  0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3      */
+	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
+	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
+	{1,  5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2      */
+	{1,  6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3      */
+	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
+	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
+	{2,  9, 2, 0, 2}, /* ENET3_GRXCLK              */
+	{2, 25, 1, 0, 2}, /* ENET3_GTXCLK              */
+
+	/* UCC_4_RGMII */
+	{2, 16, 2, 0, 3}, /* CLK17 */
+	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
+	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
+	{1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2      */
+	{1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3      */
+	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
+	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
+	{1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2      */
+	{1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3      */
+	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
+	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
+	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
+	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
+
 	/* UART1 is muxed with QE PortF bit [9-12].*/
 	{5, 12, 2, 0, 3}, /* UART1_SIN */
 	{5, 9,  1, 0, 3}, /* UART1_SOUT */
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 77946ceae44..259cd572c9a 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -312,6 +312,29 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
 #endif
 
+#define CONFIG_UEC_ETH3         /* GETH3 */
+#define CONFIG_HAS_ETH2
+
+#ifdef CONFIG_UEC_ETH3
+#define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
+#define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
+#define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR       2
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
+
+#define CONFIG_UEC_ETH4         /* GETH4 */
+#define CONFIG_HAS_ETH3
+
+#ifdef CONFIG_UEC_ETH4
+#define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
+#define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
+#define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR       3
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
+#endif
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)
-- 
cgit v1.3.1


From f82107f637f167a77803c0933f9b24741a91c711 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 12:30:37 -0400
Subject: 85xx: Add RMII support for MPC8569MDS

This patch supports UCC working at RMII mode on PIB board, fixup fdt blob to
support rmii in kernel. It also changes the name of enable_mpc8569mds_qe_mdio to
enalbe_mpc8569mds_qe_uec which is  more accurate.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 board/freescale/mpc8569mds/bcsr.c       | 15 +++++-
 board/freescale/mpc8569mds/bcsr.h       |  2 +-
 board/freescale/mpc8569mds/mpc8569mds.c | 96 ++++++++++++++++++++++++++++++++-
 include/configs/MPC8569MDS.h            | 38 +++++++++++--
 4 files changed, 144 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/board/freescale/mpc8569mds/bcsr.c b/board/freescale/mpc8569mds/bcsr.c
index 17c8478a628..a936edb76e4 100644
--- a/board/freescale/mpc8569mds/bcsr.c
+++ b/board/freescale/mpc8569mds/bcsr.c
@@ -35,8 +35,9 @@ void disable_8569mds_flash_write()
 	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 17), BCSR17_FLASH_nWP);
 }
 
-void enable_8569mds_qe_mdio()
+void enable_8569mds_qe_uec()
 {
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
 			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
@@ -45,6 +46,18 @@ void enable_8569mds_qe_mdio()
 			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
 	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
 			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+	/* Set UCC1-4 working at RMII mode */
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 7),
+			BCSR7_UCC1_GETH_EN | BCSR7_UCC1_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 8),
+			BCSR8_UCC2_GETH_EN | BCSR8_UCC2_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9),
+			BCSR9_UCC3_GETH_EN | BCSR9_UCC3_RGMII_EN);
+	clrbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 10),
+			BCSR10_UCC4_GETH_EN | BCSR10_UCC4_RGMII_EN);
+	setbits_8((u8 *)(CONFIG_SYS_BCSR_BASE + 9), BCSR9_UCC3_RMII_EN);
+#endif
 }
 
 void disable_8569mds_brd_eeprom_write_protect()
diff --git a/board/freescale/mpc8569mds/bcsr.h b/board/freescale/mpc8569mds/bcsr.h
index 8efe9bd4bf0..e5d63c71f53 100644
--- a/board/freescale/mpc8569mds/bcsr.h
+++ b/board/freescale/mpc8569mds/bcsr.h
@@ -76,7 +76,7 @@
 
 void enable_8569mds_flash_write(void);
 void disable_8569mds_flash_write(void);
-void enable_8569mds_qe_mdio(void);
+void enable_8569mds_qe_uec(void);
 void disable_8569mds_brd_eeprom_write_protect(void);
 
 #endif	/* __BCSR_H_ */
diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index 387ecad2cf9..1e7526a1aeb 100644
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -47,6 +47,7 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	/* QE_MUX_MDIO */
 	{2,  30, 3, 0, 2}, /* QE_MUX_MDIO              */
 
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 	/* UCC_1_RGMII */
 	{2, 11, 2, 0, 1}, /* CLK12 */
 	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
@@ -107,6 +108,44 @@ const qe_iop_conf_t qe_iop_conf_tab[] = {
 	{2, 17, 2, 0, 2}, /* ENET4_GRXCLK              */
 	{2, 24, 1, 0, 2}, /* ENET4_GTXCLK              */
 
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+	/* UCC_1_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0,  0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0      */
+	{0,  1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1      */
+	{0,  6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0      */
+	{0,  7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1      */
+	{0,  4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B    */
+	{0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B    */
+
+	/* UCC_2_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0      */
+	{0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1      */
+	{0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0      */
+	{0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1      */
+	{0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B    */
+	{0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B    */
+
+	/* UCC_3_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0      */
+	{0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1      */
+	{1,  3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0      */
+	{1,  4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1      */
+	{1,  1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B    */
+	{1,  9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B    */
+
+	/* UCC_4_RMII */
+	{2, 15, 2, 0, 1}, /* CLK16 */
+	{1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0      */
+	{1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1      */
+	{1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0      */
+	{1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1      */
+	{1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B    */
+	{1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B    */
+#endif
+
 	/* UART1 is muxed with QE PortF bit [9-12].*/
 	{5, 12, 2, 0, 3}, /* UART1_SIN */
 	{5, 9,  1, 0, 3}, /* UART1_SOUT */
@@ -128,7 +167,7 @@ int board_early_init_f (void)
 	enable_8569mds_flash_write();
 
 #ifdef CONFIG_QE
-	enable_8569mds_qe_mdio();
+	enable_8569mds_qe_uec();
 #endif
 
 #if CONFIG_SYS_I2C2_OFFSET
@@ -350,6 +389,61 @@ pci_init_board(void)
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_SYS_UCC_RMII_MODE)
+	int nodeoff, off, err;
+	unsigned int val;
+	const u32 *ph;
+	const u32 *index;
+
+	/* fixup device tree for supporting rmii mode */
+	nodeoff = -1;
+	while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
+				"ucc_geth")) >= 0) {
+		err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
+						"clk16");
+		if (err < 0) {
+			printf("WARNING: could not set tx-clock-name %s.\n",
+				fdt_strerror(err));
+			break;
+		}
+
+		err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
+					"rmii");
+		if (err < 0) {
+			printf("WARNING: could not set phy-connection-type "
+				"%s.\n", fdt_strerror(err));
+			break;
+		}
+
+		index = fdt_getprop(blob, nodeoff, "cell-index", 0);
+		if (index == NULL) {
+			printf("WARNING: could not get cell-index of ucc\n");
+			break;
+		}
+
+		ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
+		if (ph == NULL) {
+			printf("WARNING: could not get phy-handle of ucc\n");
+			break;
+		}
+
+		off = fdt_node_offset_by_phandle(blob, *ph);
+		if (off < 0) {
+			printf("WARNING: could not get phy node	%s.\n",
+				fdt_strerror(err));
+			break;
+		}
+
+		val = 0x7 + *index; /* RMII phy address starts from 0x8 */
+
+		err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
+		if (err < 0) {
+			printf("WARNING: could not set reg for phy-handle "
+				"%s.\n", fdt_strerror(err));
+			break;
+		}
+	}
+#endif
 	ft_cpu_setup(blob, bd);
 
 #ifdef CONFIG_PCIE1
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index 259cd572c9a..c97ea2fdcc0 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -282,6 +282,8 @@ extern unsigned long get_clock_freq(void);
 /*
  * QE UEC ethernet configuration
  */
+#define CONFIG_SYS_UCC_RGMII_MODE	/* Set UCC work at RGMII by default */
+#undef CONFIG_SYS_UCC_RMII_MODE		/* Set UCC work at RMII mode */
 
 #define CONFIG_MIIM_ADDRESS	(CONFIG_SYS_CCSRBAR + 0x82120)
 #define CONFIG_UEC_ETH
@@ -294,11 +296,18 @@ extern unsigned long get_clock_freq(void);
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM        0       /* UCC1 */
 #define CONFIG_SYS_UEC1_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 #define CONFIG_SYS_UEC1_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC1_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC1_PHY_ADDR       7
 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC1_TX_CLK         QE_CLK16	/* CLK16 for RMII */
+#define CONFIG_SYS_UEC1_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC1_PHY_ADDR       8	/* 0x8 for RMII */
+#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH1 */
 
 #define CONFIG_UEC_ETH2         /* GETH2 */
 #define CONFIG_HAS_ETH1
@@ -306,11 +315,18 @@ extern unsigned long get_clock_freq(void);
 #ifdef CONFIG_UEC_ETH2
 #define CONFIG_SYS_UEC2_UCC_NUM        1       /* UCC2 */
 #define CONFIG_SYS_UEC2_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 #define CONFIG_SYS_UEC2_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC2_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC2_PHY_ADDR       1
 #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC2_TX_CLK         QE_CLK16	/* CLK 16 for RMII */
+#define CONFIG_SYS_UEC2_ETH_TYPE       FAST_ETH
+#define CONFIG_SYS_UEC2_PHY_ADDR       0x9	/* 0x9 for RMII */
+#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH2 */
 
 #define CONFIG_UEC_ETH3         /* GETH3 */
 #define CONFIG_HAS_ETH2
@@ -318,11 +334,18 @@ extern unsigned long get_clock_freq(void);
 #ifdef CONFIG_UEC_ETH3
 #define CONFIG_SYS_UEC3_UCC_NUM        2       /* UCC3 */
 #define CONFIG_SYS_UEC3_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 #define CONFIG_SYS_UEC3_TX_CLK         QE_CLK12
 #define CONFIG_SYS_UEC3_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC3_PHY_ADDR       2
 #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC3_TX_CLK		QE_CLK16 /* CLK_16 for RMII */
+#define CONFIG_SYS_UEC3_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC3_PHY_ADDR	0xA     /* 0xA for RMII */
+#define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH3 */
 
 #define CONFIG_UEC_ETH4         /* GETH4 */
 #define CONFIG_HAS_ETH3
@@ -330,11 +353,18 @@ extern unsigned long get_clock_freq(void);
 #ifdef CONFIG_UEC_ETH4
 #define CONFIG_SYS_UEC4_UCC_NUM        3       /* UCC4 */
 #define CONFIG_SYS_UEC4_RX_CLK         QE_CLK_NONE
+#if defined(CONFIG_SYS_UCC_RGMII_MODE)
 #define CONFIG_SYS_UEC4_TX_CLK         QE_CLK17
 #define CONFIG_SYS_UEC4_ETH_TYPE       GIGA_ETH
 #define CONFIG_SYS_UEC4_PHY_ADDR       3
 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID
-#endif
+#elif defined(CONFIG_SYS_UCC_RMII_MODE)
+#define CONFIG_SYS_UEC4_TX_CLK		QE_CLK16 /* CLK16 for RMII */
+#define CONFIG_SYS_UEC4_ETH_TYPE	FAST_ETH
+#define CONFIG_SYS_UEC4_PHY_ADDR	0xB     /* 0xB for RMII */
+#define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
+#endif /* CONFIG_SYS_UCC_RGMII_MODE */
+#endif /* CONFIG_UEC_ETH4 */
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)
-- 
cgit v1.3.1


From 3bd8e532b5de20647aeaff94a1cbf33fb8b897b9 Mon Sep 17 00:00:00 2001
From: Haiying Wang <Haiying.Wang@freescale.com>
Date: Wed, 20 May 2009 12:30:41 -0400
Subject: 85xx: Add UEC6 and UEC8 at SGMII mode for MPC8569MDS

On MPC8569MDS board, UCC6 and UCC8 can be configured to work at SGMII mode via
UEM on PB board. Since MPC8569 supports up to 4 Gigabit Ethernet ports, we
disable UEC6 and UEC8 by default.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/configs/MPC8569MDS.h | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'include')

diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h
index c97ea2fdcc0..27044f7bb13 100644
--- a/include/configs/MPC8569MDS.h
+++ b/include/configs/MPC8569MDS.h
@@ -365,6 +365,31 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII
 #endif /* CONFIG_SYS_UCC_RGMII_MODE */
 #endif /* CONFIG_UEC_ETH4 */
+
+#undef CONFIG_UEC_ETH6         /* GETH6 */
+#define CONFIG_HAS_ETH5
+
+#ifdef CONFIG_UEC_ETH6
+#define CONFIG_SYS_UEC6_UCC_NUM        5       /* UCC6 */
+#define CONFIG_SYS_UEC6_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC6_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC6_PHY_ADDR       4
+#define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH6 */
+
+#undef CONFIG_UEC_ETH8         /* GETH8 */
+#define CONFIG_HAS_ETH7
+
+#ifdef CONFIG_UEC_ETH8
+#define CONFIG_SYS_UEC8_UCC_NUM        7       /* UCC8 */
+#define CONFIG_SYS_UEC8_RX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_TX_CLK         QE_CLK_NONE
+#define CONFIG_SYS_UEC8_ETH_TYPE       GIGA_ETH
+#define CONFIG_SYS_UEC8_PHY_ADDR       6
+#define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII
+#endif /* CONFIG_UEC_ETH8 */
+
 #endif /* CONFIG_QE */
 
 #if defined(CONFIG_PCI)
-- 
cgit v1.3.1


From b1f12650d332eadac1306a772cab6096abee6ddd Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Thu, 21 May 2009 12:09:59 -0500
Subject: fsl: Create common fsl_dma.h for 85xx and 86xx cpus

Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to
reduce a large amount of code duplication

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c            | 31 ++++++++++--------
 cpu/mpc86xx/cpu.c            | 27 +++++++++-------
 include/asm-ppc/fsl_dma.h    | 51 +++++++++++++++++++++++++++++
 include/asm-ppc/immap_85xx.h | 76 ++------------------------------------------
 include/asm-ppc/immap_86xx.h | 76 ++------------------------------------------
 5 files changed, 89 insertions(+), 172 deletions(-)
 create mode 100644 include/asm-ppc/fsl_dma.h

(limited to 'include')

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 9ad118842be..331fcc09a4c 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -266,26 +266,28 @@ reset_85xx_watchdog(void)
 
 #if defined(CONFIG_DDR_ECC)
 void dma_init(void) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr0 = 0x02c40000;
-	dma->datr0 = 0x02c40000;
-	dma->sr0 = 0xfffffff; /* clear any errors */
+	dma->satr = 0x02c40000;
+	dma->datr = 0x02c40000;
+	dma->sr = 0xfffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
 
 uint dma_check(void) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
-	volatile uint status = dma->sr0;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
+	volatile uint status = dma->sr;
 
 	/* While the channel is busy, spin */
 	while((status & 4) == 4) {
-		status = dma->sr0;
+		status = dma->sr;
 	}
 
 	/* clear MR0[CS] channel start bit */
-	dma->mr0 &= 0x00000001;
+	dma->mr &= 0x00000001;
 	asm("sync;isync;msync");
 
 	if (status != 0) {
@@ -295,14 +297,15 @@ uint dma_check(void) {
 }
 
 int dma_xfer(void *dest, uint count, void *src) {
-	volatile ccsr_dma_t *dma = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->dar0 = (uint) dest;
-	dma->sar0 = (uint) src;
-	dma->bcr0 = count;
-	dma->mr0 = 0xf000004;
+	dma->dar = (uint) dest;
+	dma->sar = (uint) src;
+	dma->bcr = count;
+	dma->mr = 0xf000004;
 	asm("sync;isync;msync");
-	dma->mr0 = 0xf000005;
+	dma->mr = 0xf000005;
 	asm("sync;isync;msync");
 	return dma_check();
 }
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index 653a137396a..f35323ac676 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -183,10 +183,11 @@ void
 dma_init(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr0 = 0x00040000;
-	dma->datr0 = 0x00040000;
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
 	asm("sync; isync");
 }
 
@@ -194,12 +195,13 @@ uint
 dma_check(void)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
-	volatile uint status = dma->sr0;
+	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
+	volatile uint status = dma->sr;
 
 	/* While the channel is busy, spin */
 	while ((status & 4) == 4) {
-		status = dma->sr0;
+		status = dma->sr;
 	}
 
 	if (status != 0) {
@@ -212,14 +214,15 @@ int
 dma_xfer(void *dest, uint count, void *src)
 {
 	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->dar0 = (uint) dest;
-	dma->sar0 = (uint) src;
-	dma->bcr0 = count;
-	dma->mr0 = 0xf000004;
+	dma->dar = (uint) dest;
+	dma->sar = (uint) src;
+	dma->bcr = count;
+	dma->mr = 0xf000004;
 	asm("sync;isync");
-	dma->mr0 = 0xf000005;
+	dma->mr = 0xf000005;
 	asm("sync;isync");
 	return dma_check();
 }
diff --git a/include/asm-ppc/fsl_dma.h b/include/asm-ppc/fsl_dma.h
new file mode 100644
index 00000000000..aab8720977e
--- /dev/null
+++ b/include/asm-ppc/fsl_dma.h
@@ -0,0 +1,51 @@
+/*
+ * Freescale DMA Controller
+ *
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ *
+ * This software may be used and distributed according to the
+ * terms of the GNU Public License, Version 2, incorporated
+ * herein by reference.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_FSL_DMA_H_
+#define _ASM_FSL_DMA_H_
+
+#include <asm/types.h>
+
+typedef struct fsl_dma {
+	uint	mr;		/* DMA mode register */
+	uint	sr;		/* DMA status register */
+	char	res0[4];
+	uint	clndar;		/* DMA current link descriptor address register */
+	uint	satr;		/* DMA source attributes register */
+	uint	sar;		/* DMA source address register */
+	uint	datr;		/* DMA destination attributes register */
+	uint	dar;		/* DMA destination address register */
+	uint	bcr;		/* DMA byte count register */
+	char	res1[4];
+	uint	nlndar;		/* DMA next link descriptor address register */
+	char	res2[8];
+	uint	clabdar;	/* DMA current List - alternate base descriptor address Register */
+	char	res3[4];
+	uint	nlsdar;		/* DMA next list descriptor address register */
+	uint	ssr;		/* DMA source stride register */
+	uint	dsr;		/* DMA destination stride register */
+	char	res4[56];
+} fsl_dma_t;
+
+#endif	/* _ASM_DMA_H_ */
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 0f9f493d1f3..e4f5ee2bc9e 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -12,6 +12,7 @@
 #define __IMMAP_85xx__
 
 #include <asm/types.h>
+#include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <asm/fsl_lbc.h>
 
@@ -406,80 +407,9 @@ typedef struct ccsr_l2cache {
  */
 typedef struct ccsr_dma {
 	char	res1[256];
-	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
-	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
-	char	res2[4];
-	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
-	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
-	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
-	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
-	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
-	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
-	char	res3[4];
-	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
-	char	res4[8];
-	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
-	char	res5[4];
-	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
-	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
-	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
-	char	res6[56];
-	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
-	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
-	char	res7[4];
-	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
-	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
-	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
-	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
-	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
-	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
-	char	res8[4];
-	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
-	char	res9[8];
-	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
-	char	res10[4];
-	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
-	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
-	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
-	char	res11[56];
-	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
-	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
-	char	res12[4];
-	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
-	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
-	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
-	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
-	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
-	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
-	char	res13[4];
-	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
-	char	res14[8];
-	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
-	char	res15[4];
-	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
-	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
-	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
-	char	res16[56];
-	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
-	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
-	char	res17[4];
-	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
-	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
-	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
-	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
-	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
-	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
-	char	res18[4];
-	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
-	char	res19[8];
-	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
-	char	res20[4];
-	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
-	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
-	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
-	char	res21[56];
+	struct fsl_dma dma[4];
 	uint	dgsr;		/* 0x21300 - DMA General Status Register */
-	char	res22[11516];
+	char	res2[11516];
 } ccsr_dma_t;
 
 /*
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 470385ffd2f..689c720452b 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -11,6 +11,7 @@
 #define __IMMAP_86xx__
 
 #include <asm/types.h>
+#include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 
 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
@@ -386,80 +387,9 @@ typedef struct ccsr_ht {
 /* DMA Registers(0x2_1000-0x2_2000) */
 typedef struct ccsr_dma {
 	char	res1[256];
-	uint	mr0;		/* 0x21100 - DMA 0 Mode Register */
-	uint	sr0;		/* 0x21104 - DMA 0 Status Register */
-	char	res2[4];
-	uint	clndar0;	/* 0x2110c - DMA 0 Current Link Descriptor Address Register */
-	uint	satr0;		/* 0x21110 - DMA 0 Source Attributes Register */
-	uint	sar0;		/* 0x21114 - DMA 0 Source Address Register */
-	uint	datr0;		/* 0x21118 - DMA 0 Destination Attributes Register */
-	uint	dar0;		/* 0x2111c - DMA 0 Destination Address Register */
-	uint	bcr0;		/* 0x21120 - DMA 0 Byte Count Register */
-	char	res3[4];
-	uint	nlndar0;	/* 0x21128 - DMA 0 Next Link Descriptor Address Register */
-	char	res4[8];
-	uint	clabdar0;	/* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */
-	char	res5[4];
-	uint	nlsdar0;	/* 0x2113c - DMA 0 Next List Descriptor Address Register */
-	uint	ssr0;		/* 0x21140 - DMA 0 Source Stride Register */
-	uint	dsr0;		/* 0x21144 - DMA 0 Destination Stride Register */
-	char	res6[56];
-	uint	mr1;		/* 0x21180 - DMA 1 Mode Register */
-	uint	sr1;		/* 0x21184 - DMA 1 Status Register */
-	char	res7[4];
-	uint	clndar1;	/* 0x2118c - DMA 1 Current Link Descriptor Address Register */
-	uint	satr1;		/* 0x21190 - DMA 1 Source Attributes Register */
-	uint	sar1;		/* 0x21194 - DMA 1 Source Address Register */
-	uint	datr1;		/* 0x21198 - DMA 1 Destination Attributes Register */
-	uint	dar1;		/* 0x2119c - DMA 1 Destination Address Register */
-	uint	bcr1;		/* 0x211a0 - DMA 1 Byte Count Register */
-	char	res8[4];
-	uint	nlndar1;	/* 0x211a8 - DMA 1 Next Link Descriptor Address Register */
-	char	res9[8];
-	uint	clabdar1;	/* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */
-	char	res10[4];
-	uint	nlsdar1;	/* 0x211bc - DMA 1 Next List Descriptor Address Register */
-	uint	ssr1;		/* 0x211c0 - DMA 1 Source Stride Register */
-	uint	dsr1;		/* 0x211c4 - DMA 1 Destination Stride Register */
-	char	res11[56];
-	uint	mr2;		/* 0x21200 - DMA 2 Mode Register */
-	uint	sr2;		/* 0x21204 - DMA 2 Status Register */
-	char	res12[4];
-	uint	clndar2;	/* 0x2120c - DMA 2 Current Link Descriptor Address Register */
-	uint	satr2;		/* 0x21210 - DMA 2 Source Attributes Register */
-	uint	sar2;		/* 0x21214 - DMA 2 Source Address Register */
-	uint	datr2;		/* 0x21218 - DMA 2 Destination Attributes Register */
-	uint	dar2;		/* 0x2121c - DMA 2 Destination Address Register */
-	uint	bcr2;		/* 0x21220 - DMA 2 Byte Count Register */
-	char	res13[4];
-	uint	nlndar2;	/* 0x21228 - DMA 2 Next Link Descriptor Address Register */
-	char	res14[8];
-	uint	clabdar2;	/* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */
-	char	res15[4];
-	uint	nlsdar2;	/* 0x2123c - DMA 2 Next List Descriptor Address Register */
-	uint	ssr2;		/* 0x21240 - DMA 2 Source Stride Register */
-	uint	dsr2;		/* 0x21244 - DMA 2 Destination Stride Register */
-	char	res16[56];
-	uint	mr3;		/* 0x21280 - DMA 3 Mode Register */
-	uint	sr3;		/* 0x21284 - DMA 3 Status Register */
-	char	res17[4];
-	uint	clndar3;	/* 0x2128c - DMA 3 Current Link Descriptor Address Register */
-	uint	satr3;		/* 0x21290 - DMA 3 Source Attributes Register */
-	uint	sar3;		/* 0x21294 - DMA 3 Source Address Register */
-	uint	datr3;		/* 0x21298 - DMA 3 Destination Attributes Register */
-	uint	dar3;		/* 0x2129c - DMA 3 Destination Address Register */
-	uint	bcr3;		/* 0x212a0 - DMA 3 Byte Count Register */
-	char	res18[4];
-	uint	nlndar3;	/* 0x212a8 - DMA 3 Next Link Descriptor Address Register */
-	char	res19[8];
-	uint	clabdar3;	/* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */
-	char	res20[4];
-	uint	nlsdar3;	/* 0x212bc - DMA 3 Next List Descriptor Address Register */
-	uint	ssr3;		/* 0x212c0 - DMA 3 Source Stride Register */
-	uint	dsr3;		/* 0x212c4 - DMA 3 Destination Stride Register */
-	char	res21[56];
+	struct fsl_dma dma[4];
 	uint	dgsr;		/* 0x21300 - DMA General Status Register */
-	char	res22[3324];
+	char	res2[3324];
 } ccsr_dma_t;
 
 /* tsec1-4: 24000-28000 */
-- 
cgit v1.3.1


From 2f21ce4d546d31289ac49a680f78bcc9a792c6ec Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Thu, 21 May 2009 12:10:00 -0500
Subject: fsl/85xx, 86xx: Sync up DMA code

The following changes were made to sync up the DMA code between the 85xx
and 86xx architectures which will make it easier to break out common
8xxx DMA code:

85xx:
- Don't set STRANSINT and SPCIORDER fields in SATR register.  These bits
  only have an affect when the SBPATMU bit is set.
- Write 0xffffffff instead of 0xfffffff to clear errors in the DMA
  status register.  We may as well clear all 32 bits of the register...

86xx:
- Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers
- Add clearing of errors in the DMA status register when initializing
  the controller
- Clear the channel start bit in the DMA mode register after a transfer

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 cpu/mpc85xx/cpu.c            |  8 ++++----
 cpu/mpc86xx/cpu.c            | 14 ++++++++------
 include/asm-ppc/immap_86xx.h |  2 ++
 3 files changed, 14 insertions(+), 10 deletions(-)

(limited to 'include')

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c
index 331fcc09a4c..d88c5646208 100644
--- a/cpu/mpc85xx/cpu.c
+++ b/cpu/mpc85xx/cpu.c
@@ -269,9 +269,9 @@ void dma_init(void) {
 	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
-	dma->satr = 0x02c40000;
-	dma->datr = 0x02c40000;
-	dma->sr = 0xfffffff; /* clear any errors */
+	dma->satr = 0x00040000;
+	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync; msync");
 	return;
 }
@@ -286,7 +286,7 @@ uint dma_check(void) {
 		status = dma->sr;
 	}
 
-	/* clear MR0[CS] channel start bit */
+	/* clear MR[CS] channel start bit */
 	dma->mr &= 0x00000001;
 	asm("sync;isync;msync");
 
diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c
index f35323ac676..d47cc5ef3a9 100644
--- a/cpu/mpc86xx/cpu.c
+++ b/cpu/mpc86xx/cpu.c
@@ -182,20 +182,19 @@ watchdog_reset(void)
 void
 dma_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
 	dma->satr = 0x00040000;
 	dma->datr = 0x00040000;
+	dma->sr = 0xffffffff; /* clear any errors */
 	asm("sync; isync");
 }
 
 uint
 dma_check(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 	volatile uint status = dma->sr;
 
@@ -204,6 +203,10 @@ dma_check(void)
 		status = dma->sr;
 	}
 
+	/* clear MR[CS] channel start bit */
+	dma->mr &= 0x00000001;
+	asm("sync;isync");
+
 	if (status != 0) {
 		printf("DMA Error: status = %x\n", status);
 	}
@@ -213,8 +216,7 @@ dma_check(void)
 int
 dma_xfer(void *dest, uint count, void *src)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ccsr_dma_t *dma_base = &immap->im_dma;
+	volatile ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
 	volatile fsl_dma_t *dma = &dma_base->dma[0];
 
 	dma->dar = (uint) dest;
diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h
index 689c720452b..a8398348b1e 100644
--- a/include/asm-ppc/immap_86xx.h
+++ b/include/asm-ppc/immap_86xx.h
@@ -1295,5 +1295,7 @@ extern immap_t  *immr;
 #define CONFIG_SYS_MPC86xx_DDR_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
 #define CONFIG_SYS_MPC86xx_DDR2_OFFSET	(0x6000)
 #define CONFIG_SYS_MPC86xx_DDR2_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC86xx_DMA_OFFSET	(0x21000)
+#define CONFIG_SYS_MPC86xx_DMA_ADDR	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
 
 #endif /*__IMMAP_86xx__*/
-- 
cgit v1.3.1


From 6442b71b522face775c1c31bd43121db3b4bf7d6 Mon Sep 17 00:00:00 2001
From: Peter Tyser <ptyser@xes-inc.com>
Date: Fri, 22 May 2009 10:26:32 -0500
Subject: 85xx: Add PORBMSR and PORDEVSR shift defines

Add defines similar to those already used for the the 86xx architecture.
This will ease sharing of PCI code between the 85xx and 86xx
architectures.

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
---
 include/asm-ppc/immap_85xx.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'include')

diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index e4f5ee2bc9e..db2bdf0afa6 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1530,6 +1530,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
 	uint	porbmsr;	/* 0xe0004 - POR boot mode status register */
 #define MPC85xx_PORBMSR_HA		0x00070000
+#define MPC85xx_PORBMSR_HA_SHIFT	16
 	uint	porimpscr;	/* 0xe0008 - POR I/O impedance status and control register */
 	uint	pordevsr;	/* 0xe000c - POR I/O device status regsiter */
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
@@ -1539,6 +1540,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL   0x38000000
 #define MPC85xx_PORDEVSR_PCI1		0x00800000
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
-- 
cgit v1.3.1