From 5cbbabc2b74f544f5b41c9e32c3f3ca42d6fe5dd Mon Sep 17 00:00:00 2001
From: Hoan Hoang <hnhoan@i-syst.com>
Date: Mon, 10 May 2010 15:38:55 -0400
Subject: Blackfin: ibf-dsp561: enable AX88180 net driver

Signed-off-by: Hoan Hoang <hnhoan@i-syst.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/ibf-dsp561.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'include')

diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 2eef5efa78f..5601416fafe 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -57,6 +57,18 @@
 #define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
 
 
+/*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_HOSTNAME		ibf-dsp561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
 /*
  * Flash Settings
  */
-- 
cgit v1.3.1


From c5530555f82f6fbaf51656e9ba10e295d3c5f195 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 2 Jun 2010 04:34:49 -0400
Subject: Blackfin: unify custom gpio commands

Now that we have a unified gpio layer, the misc partial gpio commands
can be unified and made complete (support all possible gpios).

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 arch/blackfin/cpu/Makefile        |   1 +
 arch/blackfin/cpu/cmd_gpio.c      | 120 +++++++++++++++++++++++
 board/bf537-stamp/Makefile        |   2 +-
 board/bf537-stamp/cmd_bf537led.c  | 201 --------------------------------------
 board/cm-bf527/Makefile           |   2 +-
 board/cm-bf527/gpio.c             |  74 --------------
 board/cm-bf537e/Makefile          |   2 +-
 board/cm-bf537e/flash.c           |  34 -------
 board/cm-bf537u/Makefile          |   2 +-
 board/cm-bf537u/flash.c           |  34 -------
 board/tcm-bf537/Makefile          |   2 +-
 board/tcm-bf537/flash.c           |  37 -------
 include/configs/bf537-stamp.h     |   2 -
 include/configs/bfin_adi_common.h |   1 +
 14 files changed, 127 insertions(+), 387 deletions(-)
 create mode 100644 arch/blackfin/cpu/cmd_gpio.c
 delete mode 100644 board/bf537-stamp/cmd_bf537led.c
 delete mode 100644 board/cm-bf527/gpio.c
 delete mode 100644 board/cm-bf537e/flash.c
 delete mode 100644 board/cm-bf537u/flash.c
 delete mode 100644 board/tcm-bf537/flash.c

(limited to 'include')

diff --git a/arch/blackfin/cpu/Makefile b/arch/blackfin/cpu/Makefile
index 91797c798f5..b7f991dea04 100644
--- a/arch/blackfin/cpu/Makefile
+++ b/arch/blackfin/cpu/Makefile
@@ -18,6 +18,7 @@ CEXTRA   := initcode.o
 SEXTRA   := start.o
 SOBJS    := interrupt.o cache.o
 COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o
+COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o
 COBJS-y  += cpu.o
 COBJS-y  += gpio.o
 COBJS-y  += interrupts.o
diff --git a/arch/blackfin/cpu/cmd_gpio.c b/arch/blackfin/cpu/cmd_gpio.c
new file mode 100644
index 00000000000..9e505b66171
--- /dev/null
+++ b/arch/blackfin/cpu/cmd_gpio.c
@@ -0,0 +1,120 @@
+/*
+ * Control GPIO pins on the fly
+ *
+ * Copyright (c) 2008-2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+
+enum {
+	GPIO_INPUT,
+	GPIO_SET,
+	GPIO_CLEAR,
+	GPIO_TOGGLE,
+};
+
+int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc == 2 && !strcmp(argv[1], "status")) {
+		bfin_gpio_labels();
+		return 0;
+	}
+
+	if (argc != 3) {
+ show_usage:
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	/* parse the behavior */
+	ulong sub_cmd;
+	switch (argv[1][0]) {
+		case 'i': sub_cmd = GPIO_INPUT;  break;
+		case 's': sub_cmd = GPIO_SET;    break;
+		case 'c': sub_cmd = GPIO_CLEAR;  break;
+		case 't': sub_cmd = GPIO_TOGGLE; break;
+		default:  goto show_usage;
+	}
+
+	/* parse the pin with format: [p][port]<#> */
+	const char *str_pin = argv[2];
+
+	/* grab the [p]<port> portion */
+	ulong port_base;
+	if (*str_pin == 'p') ++str_pin;
+	switch (*str_pin) {
+#ifdef GPIO_PA0
+		case 'a': port_base = GPIO_PA0; break;
+#endif
+#ifdef GPIO_PB0
+		case 'b': port_base = GPIO_PB0; break;
+#endif
+#ifdef GPIO_PC0
+		case 'c': port_base = GPIO_PC0; break;
+#endif
+#ifdef GPIO_PD0
+		case 'd': port_base = GPIO_PD0; break;
+#endif
+#ifdef GPIO_PE0
+		case 'e': port_base = GPIO_PE0; break;
+#endif
+#ifdef GPIO_PF0
+		case 'f': port_base = GPIO_PF0; break;
+#endif
+#ifdef GPIO_PG0
+		case 'g': port_base = GPIO_PG0; break;
+#endif
+#ifdef GPIO_PH0
+		case 'h': port_base = GPIO_PH0; break;
+#endif
+#ifdef GPIO_PI0
+		case 'i': port_base = GPIO_PI0; break;
+#endif
+#ifdef GPIO_PJ
+		case 'j': port_base = GPIO_PJ0; break;
+#endif
+		default:  goto show_usage;
+	}
+
+	/* grab the <#> portion */
+	ulong pin = simple_strtoul(str_pin + 1, NULL, 10);
+	if (pin > 15)
+		goto show_usage;
+
+	/* grab the pin before we tweak it */
+	ulong gpio = port_base + pin;
+	gpio_request(gpio, "cmd_gpio");
+
+	/* finally, let's do it: set direction and exec command */
+	if (sub_cmd == GPIO_INPUT) {
+		gpio_direction_input(gpio);
+		printf("gpio: pin %lu on port %c set to input\n", pin, *str_pin);
+		return 0;
+	}
+
+	ulong value;
+	switch (sub_cmd) {
+		case GPIO_SET:    value = 1; break;
+		case GPIO_CLEAR:  value = 0; break;
+		case GPIO_TOGGLE: value = !gpio_get_value(gpio); break;
+		default:          goto show_usage;
+	}
+	gpio_direction_output(gpio, value);
+	printf("gpio: pin %lu on port %c (gpio %lu) value is %lu\n",
+		pin, *str_pin, gpio, value);
+
+	gpio_free(gpio);
+
+	return 0;
+}
+
+U_BOOT_CMD(gpio, 3, 0, do_gpio,
+	"set/clear/toggle gpio output pins",
+	"<set|clear|toggle> <port><pin>\n"
+	"    - set/clear/toggle the specified pin (e.g. PF10)");
diff --git a/board/bf537-stamp/Makefile b/board/bf537-stamp/Makefile
index 0e15062ba8d..4f8985b2acd 100644
--- a/board/bf537-stamp/Makefile
+++ b/board/bf537-stamp/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o cmd_bf537led.o
+COBJS-y	:= $(BOARD).o
 COBJS-$(CONFIG_BFIN_IDE)   += ide-cf.o
 COBJS-$(CONFIG_POST)       += post.o post-memory.o
 
diff --git a/board/bf537-stamp/cmd_bf537led.c b/board/bf537-stamp/cmd_bf537led.c
deleted file mode 100644
index 7d8f3eadffd..00000000000
--- a/board/bf537-stamp/cmd_bf537led.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * U-boot - cmd_bf537led.c
- *
- * Copyright (C) 2006 Aaron Gage, Ocean Optics Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/string.h>
-#ifdef CONFIG_BF537_STAMP_LEDCMD
-
-/* Define the command usage in a reusable way */
-#define USAGE_LONG \
-	"led <number> <action>\n" \
-	"    <number>  - Index (0-5) of LED to change, or \"all\"\n" \
-	"    <action>  - Must be one of:\n" \
-	"		on off toggle"
-
-/* Number of LEDs supported by the board */
-#define NUMBER_LEDS     6
-/* The BF537 stamp has 6 LEDs.  This mask indicates that all should be lit. */
-#define LED_ALL_MASK    0x003F
-
-void show_cmd_usage(void);
-void set_led_state(int index, int state);
-void configure_GPIO_to_output(int index);
-
-/* Map of LEDs according to their GPIO ports.  This can be rearranged or
- * otherwise changed to account for different GPIO configurations.
- */
-int led_ports[] = { PF6, PF7, PF8, PF9, PF10, PF11 };
-
-#define ACTION_TOGGLE   -1
-#define ACTION_OFF      0
-#define ACTION_ON       1
-
-#define LED_STATE_OFF   0
-#define LED_STATE_ON    1
-
-/* This is a trivial atoi implementation since we don't have one available */
-int atoi(char *string)
-{
-	int length;
-	int retval = 0;
-	int i;
-	int sign = 1;
-
-	length = strlen(string);
-	for (i = 0; i < length; i++) {
-		if (0 == i && string[0] == '-') {
-			sign = -1;
-			continue;
-		}
-		if (string[i] > '9' || string[i] < '0') {
-			break;
-		}
-		retval *= 10;
-		retval += string[i] - '0';
-	}
-	retval *= sign;
-	return retval;
-}
-
-int do_bf537led(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
-	int led_mask = 0;
-	int led_current_state = 0;
-	int action = ACTION_OFF;
-	int temp;
-
-	if (3 != argc) {
-		/* Not enough arguments, so just show usage information */
-		show_cmd_usage();
-		return 1;
-	}
-
-	if (strcmp(argv[1], "all") == 0) {
-		led_mask = LED_ALL_MASK;
-	} else {
-		temp = atoi(argv[1]);
-		if (temp < 0 || temp >= NUMBER_LEDS) {
-			printf("Invalid LED number [%s]\n", argv[1]);
-			show_cmd_usage();
-			return 2;
-		}
-		led_mask |= (1 << temp);
-	}
-
-	if (strcmp(argv[2], "off") == 0) {
-		action = ACTION_OFF;
-	} else if (strcmp(argv[2], "on") == 0) {
-		action = ACTION_ON;
-	} else if (strcmp(argv[2], "toggle") == 0) {
-		action = ACTION_TOGGLE;
-	} else {
-		printf("Invalid action [%s]\n", argv[2]);
-		show_cmd_usage();
-		return 3;
-	}
-
-	for (temp = 0; temp < NUMBER_LEDS; temp++) {
-		if ((led_mask & (1 << temp)) > 0) {
-			/*
-			 * It is possible that the user has wired one of PF6-PF11 to
-			 * something other than an LED, so this will only change a pin
-			 * to output if the user has indicated a state change.  This may
-			 * happen a lot, but this way is safer than just setting all pins
-			 * to output.
-			 */
-			configure_GPIO_to_output(temp);
-
-			led_current_state =
-			    ((*pPORTFIO & led_ports[temp]) >
-			     0) ? LED_STATE_ON : LED_STATE_OFF;
-	/*
-		printf("LED state for index %d (%x) is %d\n", temp, led_ports[temp],
-			led_current_state);
-		printf("*pPORTFIO is %x\n", *pPORTFIO);
-	*/
-			if (ACTION_ON == action
-			    || (ACTION_TOGGLE == action
-				&& 0 == led_current_state)) {
-				printf("Turning LED %d on\n", temp);
-				set_led_state(temp, LED_STATE_ON);
-			} else {
-				printf("Turning LED %d off\n", temp);
-				set_led_state(temp, LED_STATE_OFF);
-			}
-		}
-	}
-
-	return 0;
-}
-
-/*
- * The GPIO pins that go to the LEDs on the BF537 stamp must be configured
- * as output.  This function simply configures them that way.  This could
- * be done to all of the GPIO lines at once, but if a user is using a
- * custom board, this will try to be nice and only change the GPIO lines
- * that the user specifically names.
- */
-void configure_GPIO_to_output(int index)
-{
-	int port;
-
-	port = led_ports[index];
-
-	/* Clear the Port F Function Enable Register */
-	*pPORTF_FER &= ~port;
-	/* Set the Port F I/O direction register */
-	*pPORTFIO_DIR |= port;
-	/* Clear the Port F I/O Input Enable Register */
-	*pPORTFIO_INEN &= ~port;
-}
-
-/* Enforce the given state on the GPIO line for the indicated LED */
-void set_led_state(int index, int state)
-{
-	int port;
-
-	port = led_ports[index];
-
-	if (LED_STATE_OFF == state) {
-		/* Clear the bit to turn off the LED */
-		*pPORTFIO &= ~port;
-	} else {
-		/* Set the bit to turn on the LED */
-		*pPORTFIO |= port;
-	}
-}
-
-/* Display usage information */
-void show_cmd_usage()
-{
-	printf("Usage:\n%s\n", USAGE_LONG);
-}
-
-/* Register information for u-boot to find this command */
-U_BOOT_CMD(led, 3, 1, do_bf537led,
-	   "Control BF537 stamp LEDs", USAGE_LONG);
-
-#endif
diff --git a/board/cm-bf527/Makefile b/board/cm-bf527/Makefile
index c2cd244cf29..bad018aa34d 100644
--- a/board/cm-bf527/Makefile
+++ b/board/cm-bf527/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o gpio.o gpio_cfi_flash.o
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf527/gpio.c b/board/cm-bf527/gpio.c
deleted file mode 100644
index 7e0babe8911..00000000000
--- a/board/cm-bf527/gpio.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Control GPIO pins on the fly
- *
- * Copyright (c) 2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-
-#include <asm/blackfin.h>
-
-int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (argc != 3) {
- show_usage:
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	}
-
-	/* parse the behavior */
-	ulong port_cmd = 0;
-	switch (argv[1][0]) {
-		case 'i': break;
-		case 's': port_cmd = (PORTFIO_SET - PORTFIO); break;
-		case 'c': port_cmd = (PORTFIO_CLEAR - PORTFIO); break;
-		case 't': port_cmd = (PORTFIO_TOGGLE - PORTFIO); break;
-		default:  goto show_usage;
-	}
-
-	/* parse the pin with format: [p]<fgh><#> */
-	const char *str_pin = argv[2];
-
-	/* grab the [p]<fgh> portion */
-	ulong port_base;
-	if (*str_pin == 'p') ++str_pin;
-	switch (*str_pin) {
-		case 'f': port_base = PORTFIO; break;
-		case 'g': port_base = PORTGIO; break;
-		case 'h': port_base = PORTHIO; break;
-		default:  goto show_usage;
-	}
-
-	/* grab the <#> portion */
-	ulong pin = simple_strtoul(str_pin+1, NULL, 10);
-	ulong pin_mask = (1 << pin);
-	if (pin > 15)
-		goto show_usage;
-
-	/* finally, let's do it: set direction and exec command */
-	switch (*str_pin) {
-		case 'f': bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~pin_mask); break;
-		case 'g': bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~pin_mask); break;
-		case 'h': bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~pin_mask); break;
-	}
-
-	ulong port_dir = port_base + (PORTFIO_DIR - PORTFIO);
-	if (argv[1][0] == 'i')
-		bfin_write16(port_dir, bfin_read16(port_dir) & ~pin_mask);
-	else {
-		bfin_write16(port_dir, bfin_read16(port_dir) | pin_mask);
-		bfin_write16(port_base + port_cmd, pin_mask);
-	}
-
-	printf("gpio: pin %li on port %c has been %c\n", pin, *str_pin, argv[1][0]);
-
-	return 0;
-}
-
-U_BOOT_CMD(gpio, 3, 0, do_gpio,
-	"gpio    - set/clear/toggle gpio output pins\n",
-	"<s|c|t> <port><pin>\n"
-	"    - set/clear/toggle the specified pin\n");
diff --git a/board/cm-bf537e/Makefile b/board/cm-bf537e/Makefile
index 3812ba1e721..bad018aa34d 100644
--- a/board/cm-bf537e/Makefile
+++ b/board/cm-bf537e/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf537e/flash.c b/board/cm-bf537e/flash.c
deleted file mode 100644
index a4c1ec06cba..00000000000
--- a/board/cm-bf537e/flash.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc > 1) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTFIO();
-		printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
-	"set/clear PF4 GPIO flash bank switch\n",
-	"<pf4> - set PF4 GPIO pin state\n");
diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
index 3812ba1e721..bad018aa34d 100644
--- a/board/cm-bf537u/Makefile
+++ b/board/cm-bf537u/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c
deleted file mode 100644
index 52abe790ab1..00000000000
--- a/board/cm-bf537u/flash.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc > 1) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTHIO();
-		printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(ph, 3, 0, do_ph,
-	"set/clear PH0 GPIO flash bank switch\n",
-	"<ph0> - set PH0 GPIO pin state\n");
diff --git a/board/tcm-bf537/Makefile b/board/tcm-bf537/Makefile
index 3812ba1e721..bad018aa34d 100644
--- a/board/tcm-bf537/Makefile
+++ b/board/tcm-bf537/Makefile
@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS-y	:= $(BOARD).o flash.o gpio_cfi_flash.o
+COBJS-y	:= $(BOARD).o gpio_cfi_flash.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/tcm-bf537/flash.c b/board/tcm-bf537/flash.c
deleted file mode 100644
index 14055c61770..00000000000
--- a/board/tcm-bf537/flash.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc == 3) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		dflg = simple_strtoul(argv[2], NULL, 16);
-		faddr |= (dflg << 22);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTFIO();
-		printf("Port F data %04x (PF4:%i PF5:%i)\n", data,
-			!!(data & PF4), !!(data & PF5));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
-	"set/clear PF4/PF5 GPIO flash bank switch\n",
-	"<pf4> <pf5> - set PF4/PF5 GPIO pin state\n");
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 92ceb3815b6..cba4ac05481 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -268,8 +268,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 
-/* #define CONFIG_BF537_STAMP_LEDCMD	1 */
-
 /* Define if want to do post memory test */
 #undef CONFIG_POST
 #ifdef CONFIG_POST
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 1896cf53d57..fa1e69486fd 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -83,6 +83,7 @@
 # define CONFIG_CMD_CPLBINFO
 # define CONFIG_CMD_ELF
 # define CONFIG_ELF_SIMPLE_LOAD
+# define CONFIG_CMD_GPIO
 # define CONFIG_CMD_KGDB
 # define CONFIG_CMD_REGINFO
 # define CONFIG_CMD_STRINGS
-- 
cgit v1.3.1


From ca86ba11da0f3e2971de58dfd171d1cd617b39d6 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 2 Jun 2010 05:08:58 -0400
Subject: Blackfin: back out status_led.h stubs

When boards define CONFIG_BOARD_SPECIFIC_LED, the common led definitions
are OK for Blackfin boards.  So switch the few boards using these over to
the common code.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf526-ezbrd.h | 6 ------
 include/configs/bf533-stamp.h | 6 ------
 include/status_led.h          | 3 ---
 3 files changed, 15 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 711fa27b446..52aeb5cdfe8 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -161,12 +161,6 @@
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
 /* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
 #define STATUS_LED_BIT 1
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 80c48847e42..d5e82cae1b8 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -231,12 +231,6 @@
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
 /* use LED1 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
 #define STATUS_LED_BIT 1
diff --git a/include/status_led.h b/include/status_led.h
index 9dbf01fca8e..f2135954aab 100644
--- a/include/status_led.h
+++ b/include/status_led.h
@@ -346,9 +346,6 @@ void status_led_set  (int led, int state);
 #elif defined(CONFIG_NIOS2)
 /* XXX empty just to avoid the error */
 /************************************************************************/
-#elif defined(CONFIG_BLACKFIN)
-/* XXX empty just to avoid the error */
-/************************************************************************/
 #elif defined(CONFIG_V38B)
 
 # define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */
-- 
cgit v1.3.1


From a84774f56a97c5a2b0521b85ac9eb8b1c7fb15b3 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 2 Jun 2010 05:12:11 -0400
Subject: Blackfin: switch to common GPIO LED driver

Now that we have a unified gpio layer, the different status led
implementations can be switched to the common gpio led driver.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 board/bf526-ezbrd/Makefile      |  1 -
 board/bf526-ezbrd/status-led.c  | 56 -----------------------------------------
 board/bf533-stamp/bf533-stamp.c | 37 ---------------------------
 include/configs/bf526-ezbrd.h   |  6 +++--
 include/configs/bf533-stamp.h   | 10 +++++---
 5 files changed, 10 insertions(+), 100 deletions(-)
 delete mode 100644 board/bf526-ezbrd/status-led.c

(limited to 'include')

diff --git a/board/bf526-ezbrd/Makefile b/board/bf526-ezbrd/Makefile
index a9ff760073b..f2bd2c247d4 100644
--- a/board/bf526-ezbrd/Makefile
+++ b/board/bf526-ezbrd/Makefile
@@ -30,7 +30,6 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(BOARD).a
 
 COBJS-y	:= $(BOARD).o
-COBJS-$(CONFIG_STATUS_LED) += status-led.o
 
 SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS-y))
diff --git a/board/bf526-ezbrd/status-led.c b/board/bf526-ezbrd/status-led.c
deleted file mode 100644
index 6327022ccf1..00000000000
--- a/board/bf526-ezbrd/status-led.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * U-boot - status leds
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <command.h>
-#include <status_led.h>
-
-static void set_led_f(int pf, int state)
-{
-	switch (state) {
-		case STATUS_LED_OFF:      bfin_write_PORTFIO_CLEAR(pf);  break;
-		case STATUS_LED_BLINKING: bfin_write_PORTFIO_TOGGLE(pf); break;
-		case STATUS_LED_ON:       bfin_write_PORTFIO_SET(pf);    break;
-	}
-}
-static void set_led_g(int pf, int state)
-{
-	switch (state) {
-		case STATUS_LED_OFF:      bfin_write_PORTGIO_CLEAR(pf);  break;
-		case STATUS_LED_BLINKING: bfin_write_PORTGIO_TOGGLE(pf); break;
-		case STATUS_LED_ON:       bfin_write_PORTGIO_SET(pf);    break;
-	}
-}
-
-static void set_leds(led_id_t mask, int state)
-{
-	if (mask & 0x1) set_led_f(PF8, state);
-	if (mask & 0x2) set_led_g(PG11, state);
-	if (mask & 0x4) set_led_g(PG12, state);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~(PF8));
-	bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~(PG11 | PG12));
-	bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() & ~(PF8));
-	bfin_write_PORTGIO_INEN(bfin_read_PORTGIO_INEN() & ~(PG11 | PG12));
-	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | (PF8));
-	bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | (PG11 | PG12));
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	set_leds(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	set_leds(mask, STATUS_LED_BLINKING);
-}
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 4abad08cd9d..fd10eae2f12 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -134,43 +134,6 @@ void show_boot_progress(int status)
 }
 #endif
 
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-
-static void set_led(int pf, int state)
-{
-	switch (state) {
-		case STATUS_LED_OFF:      bfin_write_FIO_FLAG_S(pf); break;
-		case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break;
-		case STATUS_LED_ON:       bfin_write_FIO_FLAG_C(pf); break;
-	}
-}
-
-static void set_leds(led_id_t mask, int state)
-{
-	if (mask & 0x1) set_led(PF2, state);
-	if (mask & 0x2) set_led(PF3, state);
-	if (mask & 0x4) set_led(PF4, state);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
-	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	set_leds(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	set_leds(mask, STATUS_LED_BLINKING);
-}
-
-#endif
-
 #ifdef CONFIG_SMC91111
 int board_eth_init(bd_t *bis)
 {
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index 52aeb5cdfe8..ecda21689d8 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -160,17 +160,19 @@
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
 #define CONFIG_BOARD_SPECIFIC_LED
 /* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF8
 #define STATUS_LED_STATE STATUS_LED_ON
 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
 /* use LED1 to indicate crash */
 #define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PG11
 #define STATUS_LED_STATE1 STATUS_LED_ON
 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PG12 */
 #endif
 
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index d5e82cae1b8..2ec9c422aa4 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -230,17 +230,19 @@
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-/* use LED1 to indicate booting/alive */
+/* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF2
 #define STATUS_LED_STATE STATUS_LED_ON
 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
-/* use LED2 to indicate crash */
+/* use LED1 to indicate crash */
 #define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PF3
 #define STATUS_LED_STATE1 STATUS_LED_ON
 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PF4 */
 #endif
 
 /* define to enable splash screen support */
-- 
cgit v1.3.1


From 67ceefa79b86d9d72b7487005a6a8a61cd6a1d66 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 5 Jul 2010 04:55:05 -0400
Subject: Blackfin: convert plat-nand code to GPIO framework

Use the new GPIO framework code in both the Blackfin arch and the
nand_plat driver to simplify things greatly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf537-pnav.h    |  9 +--------
 include/configs/bf537-stamp.h   |  9 +--------
 include/configs/bf561-acvilon.h |  8 +-------
 include/configs/ip04.h          | 10 +---------
 4 files changed, 4 insertions(+), 32 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index cf40d06b886..73ad95efe2b 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -132,7 +132,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF12
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \
@@ -141,13 +140,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTHIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \
-		bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF12
 
 
 /*
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 92ceb3815b6..64e86d64ff2 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -157,7 +157,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF3
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \
@@ -166,13 +165,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTFIO() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
-		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
 
 
 /*
diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0be170c3ee8..ed8d9443b3d 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -145,7 +145,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 3))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \
@@ -154,12 +153,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO0_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_FIO0_DIR(bfin_read_FIO0_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_FIO0_INEN(bfin_read_FIO0_INEN() | BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index 425a745408e..c024d78c18a 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -116,7 +116,6 @@
 
 #define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
 #define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
-#define BFIN_NAND_READY     PF10
 #define BFIN_NAND_WRITE(addr, cmd) \
 	do { \
 		bfin_write8(addr, cmd); \
@@ -125,14 +124,7 @@
 
 #define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
 #define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
-#define NAND_PLAT_DEV_READY(chip)      (bfin_read_FIO_FLAG_D() & BFIN_NAND_READY)
-#define NAND_PLAT_INIT() \
-	do { \
-		bfin_write_FIO_DIR(bfin_read_FIO_DIR() & ~BFIN_NAND_READY); \
-		bfin_write_FIO_INEN(bfin_read_FIO_INEN() | BFIN_NAND_READY); \
-		bfin_write_FIO_EDGE(bfin_read_FIO_EDGE() & ~BFIN_NAND_READY); \
-		bfin_write_FIO_POLAR(bfin_read_FIO_POLAR() & ~BFIN_NAND_READY); \
-	} while (0)
+#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF10
 
 
 /*
-- 
cgit v1.3.1


From 7c619ddceebc6bf85ee05c705f02691f581bc282 Mon Sep 17 00:00:00 2001
From: Ilya Yanok <yanok@emcraft.com>
Date: Mon, 28 Jun 2010 16:44:33 +0400
Subject: mpc8308: support for Freescale MPC8308 cpu

This patch adds basic support for Freescale MPC8308 CPU. Serial ports,
NOR flash and integrated Ethernet controllers are supported.
PCI Express is also supported. eSDHC, NAND and USB may work but aren't
tested (using ULPI PHY requires additional patch).

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 arch/powerpc/cpu/mpc83xx/cpu.c         |  1 +
 arch/powerpc/cpu/mpc83xx/speed.c       | 23 +++++++++++++++--------
 arch/powerpc/include/asm/global_data.h |  6 ++++--
 arch/powerpc/include/asm/immap_83xx.h  | 15 +++++++++++++--
 arch/powerpc/include/asm/mpc8xxx_spi.h |  3 ++-
 include/mpc83xx.h                      | 27 +++++++++++++++++++--------
 6 files changed, 54 insertions(+), 21 deletions(-)

(limited to 'include')

diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index b664c641a16..42387b49e02 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -55,6 +55,7 @@ int checkcpu(void)
 		char name[15];
 		u32 partid;
 	} cpu_type_list [] = {
+		CPU_TYPE_ENTRY(8308),
 		CPU_TYPE_ENTRY(8311),
 		CPU_TYPE_ENTRY(8313),
 		CPU_TYPE_ENTRY(8314),
diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c
index b5076a9af87..d04b1925999 100644
--- a/arch/powerpc/cpu/mpc83xx/speed.c
+++ b/arch/powerpc/cpu/mpc83xx/speed.c
@@ -100,7 +100,8 @@ int get_clocks(void)
 	u32 lcrr;
 
 	u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -132,7 +133,8 @@ int get_clocks(void)
 	u32 qe_clk;
 	u32 brg_clk;
 #endif
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
@@ -164,7 +166,8 @@ int get_clocks(void)
 
 	sccr = im->clk.sccr;
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 	case 0:
 		tsec1_clk = 0;
@@ -202,7 +205,8 @@ int get_clocks(void)
 	}
 #endif
 
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 	case 0:
 		tsec2_clk = 0;
@@ -319,7 +323,7 @@ int get_clocks(void)
 	i2c1_clk = csb_clk;
 #elif defined(CONFIG_MPC832x)
 	i2c1_clk = enc_clk;
-#elif defined(CONFIG_MPC831x)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x)
 	i2c1_clk = enc_clk;
 #elif defined(CONFIG_FSL_ESDHC)
 	i2c1_clk = sdhc_clk;
@@ -328,7 +332,8 @@ int get_clocks(void)
 	i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 #endif
 
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 	case 0:
 		pciexp1_clk = 0;
@@ -444,7 +449,8 @@ int get_clocks(void)
 #endif
 
 	gd->csb_clk = csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	gd->tsec1_clk = tsec1_clk;
 	gd->tsec2_clk = tsec2_clk;
 	gd->usbdr_clk = usbdr_clk;
@@ -525,7 +531,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 #if defined(CONFIG_FSL_ESDHC)
 	printf("  SDHC:                %-4s MHz\n", strmhz(buf, gd->sdhc_clk));
 #endif
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	printf("  TSEC1:               %-4s MHz\n", strmhz(buf, gd->tsec1_clk));
 	printf("  TSEC2:               %-4s MHz\n", strmhz(buf, gd->tsec2_clk));
 	printf("  USB DR:              %-4s MHz\n", strmhz(buf, gd->usbdr_clk));
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index d3dd44e96d7..c854ce94886 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -60,7 +60,8 @@ typedef	struct	global_data {
 #if defined(CONFIG_MPC83xx)
 	/* There are other clocks in the MPC83XX */
 	u32 csb_clk;
-#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
 	u32 tsec1_clk;
 	u32 tsec2_clk;
 	u32 usbdr_clk;
@@ -76,7 +77,8 @@ typedef	struct	global_data {
 	u32 lbiu_clk;
 	u32 lclk_clk;
 	u32 pci_clk;
-#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC831x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 	u32 pciexp1_clk;
 	u32 pciexp2_clk;
 #endif
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 6b42a73f3f6..3a9cdc4f8df 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -73,7 +73,11 @@ typedef struct sysconf83xx {
 	u32 obir;		/* Output Buffer Impedance Register */
 	u8 res8[0xC];
 	u32 pecr1;		/* PCI Express control register 1 */
+#ifdef CONFIG_MPC8308
+	u32 sdhccr;		/* eSDHC Control Registers for MPC8308 */
+#else
 	u32 pecr2;		/* PCI Express control register 2 */
+#endif
 	u8 res9[0xB8];
 } sysconf83xx_t;
 
@@ -589,7 +593,14 @@ typedef struct sdhc83xx {
  * SerDes
  */
 typedef struct serdes83xx {
-	u8 fixme[0x100];
+	u32 srdscr0;
+	u32 srdscr1;
+	u32 srdscr2;
+	u32 srdscr3;
+	u32 srdscr4;
+	u8 res0[0xc];
+	u32 srdsrstctl;
+	u8 res1[0xdc];
 } serdes83xx_t;
 
 /*
@@ -691,7 +702,7 @@ typedef struct immap {
 	u8			res7[0xC0000];
 } immap_t;
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 typedef struct immap {
 	sysconf83xx_t		sysconf;	/* System configuration */
 	wdt83xx_t		wdt;		/* Watch Dog Timer (WDT) Registers */
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 41737d3c694..b0082affd38 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -27,9 +27,10 @@
 
 #include <asm/types.h>
 
-#if defined(CONFIG_MPC834x) || \
+#if defined(CONFIG_MPC8308) || \
 	defined(CONFIG_MPC8313) || \
 	defined(CONFIG_MPC8315) || \
+	defined(CONFIG_MPC834x) || \
 	defined(CONFIG_MPC837x)
 
 typedef struct spi8xxx {
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 5214911d1c9..ba6cdf1b289 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2004-2007, 2010 Freescale Semiconductor, Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -65,6 +65,7 @@
 #define PARTID_NO_E(spridr)		((spridr & 0xFFFE0000) >> 16)
 #define SPR_FAMILY(spridr)		((spridr & 0xFFF00000) >> 20)
 
+#define SPR_8308			0x8100
 #define SPR_831X_FAMILY			0x80B
 #define SPR_8311			0x80B2
 #define SPR_8313			0x80B0
@@ -115,8 +116,9 @@
 #define SPCR_TSEC2EP			0x00000003	/* TSEC2 emergency priority */
 #define SPCR_TSEC2EP_SHIFT		(31-31)
 
-#elif defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
-/* SPCR bits - MPC831x and MPC837x specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
+/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
 #define SPCR_TSECDP			0x00003000	/* TSEC data priority */
 #define SPCR_TSECDP_SHIFT		(31-19)
 #define SPCR_TSECBDP			0x00000C00	/* TSEC buffer descriptor priority */
@@ -473,7 +475,7 @@
 #define HRCWL_CE_TO_PLL_1X30		0x0000001E
 #define HRCWL_CE_TO_PLL_1X31		0x0000001F
 
-#elif defined(CONFIG_MPC8315)
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
 #define HRCWL_SVCOD			0x30000000
 #define HRCWL_SVCOD_SHIFT		28
 #define HRCWL_SVCOD_DIV_2		0x00000000
@@ -541,7 +543,8 @@
 #define HRCWH_ROM_LOC_LOCAL_16BIT	0x00600000
 #define HRCWH_ROM_LOC_LOCAL_32BIT	0x00700000
 
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 #define HRCWH_ROM_LOC_NAND_SP_8BIT	0x00100000
 #define HRCWH_ROM_LOC_NAND_SP_16BIT	0x00200000
 #define HRCWH_ROM_LOC_NAND_LP_8BIT	0x00500000
@@ -592,7 +595,8 @@
 
 /* RSR - Reset Status Register
  */
-#if defined(CONFIG_MPC831x) || defined(CONFIG_MPC837x)
+#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
+	defined(CONFIG_MPC837x)
 #define RSR_RSTSRC			0xF0000000	/* Reset source */
 #define RSR_RSTSRC_SHIFT		28
 #else
@@ -734,8 +738,8 @@
 #define SCCR_USBDRCM_2			0x00200000
 #define SCCR_USBDRCM_3			0x00300000
 
-#elif defined(CONFIG_MPC8315)
-/* SCCR bits - MPC8315 specific */
+#elif defined(CONFIG_MPC8308) || defined(CONFIG_MPC8315)
+/* SCCR bits - MPC8315/MPC8308 specific */
 #define SCCR_TSEC1CM			0xc0000000
 #define SCCR_TSEC1CM_SHIFT		30
 #define SCCR_TSEC1CM_0			0x00000000
@@ -750,6 +754,13 @@
 #define SCCR_TSEC2CM_2			0x20000000
 #define SCCR_TSEC2CM_3			0x30000000
 
+#define SCCR_SDHCCM			0x0c000000
+#define SCCR_SDHCCM_SHIFT		26
+#define SCCR_SDHCCM_0			0x00000000
+#define SCCR_SDHCCM_1			0x04000000
+#define SCCR_SDHCCM_2			0x08000000
+#define SCCR_SDHCCM_3			0x0c000000
+
 #define SCCR_USBDRCM			0x00c00000
 #define SCCR_USBDRCM_SHIFT		22
 #define SCCR_USBDRCM_0			0x00000000
-- 
cgit v1.3.1


From 5fb17030d5634d9951da48af69be08146eb71bf9 Mon Sep 17 00:00:00 2001
From: Ilya Yanok <yanok@emcraft.com>
Date: Wed, 7 Jul 2010 20:16:13 +0400
Subject: MPC8308RDB: minimal support for devboard from Freescale

This patch provides support for MPC8308RDB development board from
Freescale with a minimal set of features:
 Dual UART is supported
 NOR flash is supported
 Both TSEC Ethernet controllers are supported
 PCI Express initialization is supported

The following features are enabled in configuration but not fully tested:
 I2C (used to get the board revision)
 I2C-connected RTC
 VSC7385 switch

There is one (hopefully) minor issue: on soft reset the board sometimes
resets twice. I've not managed to find the fix for this problem yet.
As a workaround instruction cache can be disabled.

Signed-off-by: Ilya Yanok <yanok@emcraft.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 MAINTAINERS                             |   4 +
 MAKEALL                                 |   1 +
 board/freescale/mpc8308rdb/Makefile     |  52 +++
 board/freescale/mpc8308rdb/config.mk    |   1 +
 board/freescale/mpc8308rdb/mpc8308rdb.c | 160 +++++++++
 board/freescale/mpc8308rdb/sdram.c      | 126 +++++++
 boards.cfg                              |   1 +
 include/configs/MPC8308RDB.h            | 560 ++++++++++++++++++++++++++++++++
 8 files changed, 905 insertions(+)
 create mode 100644 board/freescale/mpc8308rdb/Makefile
 create mode 100644 board/freescale/mpc8308rdb/config.mk
 create mode 100644 board/freescale/mpc8308rdb/mpc8308rdb.c
 create mode 100644 board/freescale/mpc8308rdb/sdram.c
 create mode 100644 include/configs/MPC8308RDB.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 94850702ea7..d9158cec5a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,10 @@ Stephen Williams <steve@icarus.com>
 
 	JSE		PPC405GPr
 
+Ilya Yanok <yanok@emcraft.com>
+
+	MPC8308RDB	MPC8308
+
 Roy Zang <tie-fei.zang@freescale.com>
 
 	mpc7448hpc2	MPC7448
diff --git a/MAKEALL b/MAKEALL
index 463739069d3..e7651dc462b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -360,6 +360,7 @@ LIST_8260="		\
 LIST_83xx="		\
 	caddy2		\
 	kmeter1		\
+	MPC8308RDB	\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_NAND_66	\
 	MPC8315ERDB	\
diff --git a/board/freescale/mpc8308rdb/Makefile b/board/freescale/mpc8308rdb/Makefile
new file mode 100644
index 00000000000..e9bfa2bc0db
--- /dev/null
+++ b/board/freescale/mpc8308rdb/Makefile
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010
+# Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o sdram.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/mpc8308rdb/config.mk b/board/freescale/mpc8308rdb/config.mk
new file mode 100644
index 00000000000..f76826495ef
--- /dev/null
+++ b/board/freescale/mpc8308rdb/config.mk
@@ -0,0 +1 @@
+TEXT_BASE = 0xFE000000
diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c
new file mode 100644
index 00000000000..a864189571a
--- /dev/null
+++ b/board/freescale/mpc8308rdb/mpc8308rdb.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <i2c.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <vsc7385.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_mpc83xx_serdes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		gd->flags |= GD_FLG_SILENT;
+
+	return 0;
+}
+
+static u8 read_board_info(void)
+{
+	u8 val8;
+	i2c_set_bus_num(0);
+
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+		return val8;
+	else
+		return 0;
+}
+
+int checkboard(void)
+{
+	static const char * const rev_str[] = {
+		"1.0",
+		"<reserved>",
+		"<reserved>",
+		"<reserved>",
+		"<unknown>",
+	};
+	u8 info;
+	int i;
+
+	info = read_board_info();
+	i = (!info) ? 4 : info & 0x03;
+
+	printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
+
+	return 0;
+}
+
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+void pci_init_board(void)
+{
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+	sysconf83xx_t *sysconf = &immr->sysconf;
+	clk83xx_t *clk = (clk83xx_t *)&immr->clk;
+	law83xx_t *pcie_law = sysconf->pcielaw;
+	struct pci_region *pcie_reg[] = { pcie_regions_0 };
+
+	fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
+					FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
+
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM ,
+				    SCCR_PCIEXP1CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(1, pcie_reg, 0);
+}
+/*
+ * Miscellaneous late-boot configurations
+ *
+ * If a VSC7385 microcode image is present, then upload it.
+*/
+int misc_init_r(void)
+{
+#ifdef CONFIG_VSC7385_IMAGE
+	if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
+		CONFIG_VSC7385_IMAGE_SIZE)) {
+		puts("Failure uploading VSC7385 microcode.\n");
+		return 1;
+	}
+#endif
+
+	return 0;
+}
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+	fdt_fixup_dr_usb(blob, bd);
+}
+#endif
+
+int board_eth_init(bd_t *bis)
+{
+	int rv, num_if = 0;
+
+	/* Initialize TSECs first */
+	if ((rv = cpu_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize TSECs.\n");
+
+	if ((rv = pci_eth_init(bis)) >= 0)
+		num_if += rv;
+	else
+		printf("ERROR: failed to initialize PCI Ethernet.\n");
+
+	return num_if;
+}
diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c
new file mode 100644
index 00000000000..939c1b85b86
--- /dev/null
+++ b/board/freescale/mpc8308rdb/sdram.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ * Authors: Nick.Spence@freescale.com
+ *          Wilson.Lo@freescale.com
+ *          scottwood@freescale.com
+ *
+ * This files is  mostly identical to the original from
+ * board\freescale\mpc8315erdb\sdram.c
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+#include <asm/processor.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void resume_from_sleep(void)
+{
+	u32 magic = *(u32 *)0;
+
+	typedef void (*func_t)(void);
+	func_t resume = *(func_t *)4;
+
+	if (magic == 0xf5153ae5)
+		resume();
+
+	gd->flags &= ~GD_FLG_SILENT;
+	puts("\nResume from sleep failed: bad magic word\n");
+}
+
+/* Fixed sdram init -- doesn't use serial presence detect.
+ *
+ * This is useful for faster booting in configs where the RAM is unlikely
+ * to be changed, or for things like NAND booting where space is tight.
+ */
+static long fixed_sdram(void)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+			CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000);
+	out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) {
+		out_be32(&im->ddr.sdram_cfg,
+			CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI);
+	} else {
+		out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
+	}
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+	sync();
+
+	return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize);
+}
+
+phys_size_t initdram(int board_type)
+{
+	immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
+	u32 msize;
+
+	if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM */
+	msize = fixed_sdram();
+
+	if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF)
+		resume_from_sleep();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
diff --git a/boards.cfg b/boards.cfg
index da31c3647e9..c23696f1399 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -331,6 +331,7 @@ ppmc8260	powerpc	mpc8260
 RPXsuper	powerpc	mpc8260		rpxsuper
 rsdproto	powerpc	mpc8260
 MPC8266ADS	powerpc	mpc8260		mpc8266ads	freescale
+MPC8308RDB	powerpc	mpc83xx		mpc8308rdb	freescale
 MPC8323ERDB	powerpc	mpc83xx		mpc8323erdb	freescale
 MPC8349EMDS	powerpc	mpc83xx		mpc8349emds	freescale
 MPC837XERDB	powerpc	mpc83xx		mpc837xerdb	freescale
diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h
new file mode 100644
index 00000000000..6cd5da79502
--- /dev/null
+++ b/include/configs/MPC8308RDB.h
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
+ *
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1 /* E300 family */
+#define CONFIG_MPC83xx		1 /* MPC83xx family */
+#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
+#define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */
+
+#define CONFIG_MISC_INIT_R
+
+/*
+ * On-board devices
+ *
+ * TSEC1 is SoC TSEC
+ * TSEC2 is VSC switch
+ */
+#define CONFIG_TSEC1
+#define CONFIG_VSC7385_ENET
+
+/*
+ * System Clock Setup
+ */
+#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+/*
+ * Hardware Reset Configuration Word
+ * if CLKIN is 66.66MHz, then
+ * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
+ * We choose the A type silicon as default, so the core is 400Mhz.
+ */
+#define CONFIG_SYS_HRCW_LOW (\
+	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
+	HRCWL_DDR_TO_SCB_CLK_2X1 |\
+	HRCWL_SVCOD_DIV_2 |\
+	HRCWL_CSB_TO_CLKIN_4X1 |\
+	HRCWL_CORE_TO_CSB_3X1)
+/*
+ * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
+ * in 8308's HRCWH according to the manual, but original Freescale's
+ * code has them and I've expirienced some problems using the board
+ * with BDI3000 attached when I've tried to set these bits to zero
+ * (UART doesn't work after the 'reset run' command).
+ */
+#define CONFIG_SYS_HRCW_HIGH (\
+	HRCWH_PCI_HOST |\
+	HRCWH_PCI1_ARBITER_ENABLE |\
+	HRCWH_CORE_ENABLE |\
+	HRCWH_FROM_0X00000100 |\
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT |\
+	HRCWH_RL_EXT_LEGACY |\
+	HRCWH_TSEC1M_IN_RGMII |\
+	HRCWH_TSEC2M_IN_RGMII |\
+	HRCWH_BIG_ENDIAN)
+
+/*
+ * System IO Config
+ */
+#define CONFIG_SYS_SICRH	0x01b7d103
+#define CONFIG_SYS_SICRL	0x00000040 /* 3.3V, no delay */
+
+#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+
+/*
+ * IMMR new address
+ */
+#define CONFIG_SYS_IMMR		0xE0000000
+
+/*
+ * SERDES
+ */
+#define CONFIG_FSL_SERDES
+#define CONFIG_FSL_SERDES1	0xe3000
+
+/*
+ * Arbiter Setup
+ */
+#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
+#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
+#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
+				| DDRCDR_PZ_LOZ \
+				| DDRCDR_NZ_LOZ \
+				| DDRCDR_ODT \
+				| DDRCDR_Q_DRN)
+				/* 0x7b880001 */
+/*
+ * Manually set up DDR parameters
+ * consist of two chips HY5PS12621BFP-C4 from HYNIX
+ */
+
+#define CONFIG_SYS_DDR_SIZE		128 /* MB */
+
+#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
+#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
+				| 0x00010000  /* ODT_WR to CSn */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
+				/* 0x80010102 */
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
+				| (0 << TIMING_CFG0_WRT_SHIFT) \
+				| (0 << TIMING_CFG0_RRT_SHIFT) \
+				| (0 << TIMING_CFG0_WWT_SHIFT) \
+				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
+				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
+				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
+				/* 0x00220802 */
+#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
+				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
+				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
+				| (6 << TIMING_CFG1_REFREC_SHIFT) \
+				| (2 << TIMING_CFG1_WRREC_SHIFT) \
+				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
+				| (2 << TIMING_CFG1_WRTORD_SHIFT))
+				/* 0x27256222 */
+#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
+				| (4 << TIMING_CFG2_CPO_SHIFT) \
+				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
+				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
+				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
+				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
+				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
+				/* 0x121048c5 */
+#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
+				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
+				/* 0x03600100 */
+#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE)
+				/* 0x43080000 */
+
+#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
+#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
+				| (0x0232 << SDRAM_MODE_SD_SHIFT))
+				/* ODT 150ohm CL=3, AL=1 on SDRAM */
+#define CONFIG_SYS_DDR_MODE2		0x00000000
+
+/*
+ * Memory test
+ */
+#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
+#define CONFIG_SYS_MEMTEST_END		0x07f00000
+
+/*
+ * The reserved memory
+ */
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
+
+#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */
+
+/*
+ * Initial RAM Base Address Setup
+ */
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+
+/*
+ * Local Bus Configuration & Clock Setup
+ */
+#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
+#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
+#define CONFIG_SYS_LBC_LBCR		0x00040000
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+
+#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
+#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
+#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */
+
+/* Window base at flash base */
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000016 /* 8MB window size */
+
+#define CONFIG_SYS_BR0_PRELIM	(\
+		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
+		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
+		BR_V)			/* valid */
+#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
+				| OR_UPM_XAM \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV2 \
+				| OR_GPCM_XACS \
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
+/* 127 64KB sectors and 8 8KB top sectors per device */
+#define CONFIG_SYS_MAX_FLASH_SECT	135
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
+
+/*
+ * NAND Flash on the Local Bus
+ */
+#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
+#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_NAND_BASE \
+				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
+				| BR_PS_8		/* Port Size = 8 bit */ \
+				| BR_MS_FCM		/* MSEL = FCM */ \
+				| BR_V )		/* valid */
+#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR )
+				/* 0xFFFF8396 */
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#ifdef CONFIG_VSC7385_ENET
+#define CONFIG_TSEC2
+#define CONFIG_SYS_VSC7385_BASE		0xF0000000
+#define CONFIG_SYS_BR2_PRELIM		0xf0000801 /* VSC7385 Base address */
+#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff /* VSC7385, 128K bytes*/
+/* Access window base at VSC7385 base */
+#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
+/* Access window size 128K */
+#define CONFIG_SYS_LBLAWAR2_PRELIM	0x80000010
+/* The flash address and size of the VSC7385 firmware image */
+#define CONFIG_VSC7385_IMAGE		0xFE7FE000
+#define CONFIG_VSC7385_IMAGE_SIZE	8192
+#endif
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#undef CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* Pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/* I2C */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_FSL_I2C
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0x51}} /* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+
+/*
+ * Board info - revision and where boot from
+ */
+#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39
+
+/*
+ * Config on-board RTC
+ */
+#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
+#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */
+
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+/*
+ * Fake PCIE2 definitions: there is no PCIE2 on this board but the code
+ * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this
+ */
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xD0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x01000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD1000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
+
+#define CONFIG_PCI
+#define CONFIG_PCIE
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
+
+/*
+ * TSEC
+ */
+#define CONFIG_NET_MULTI
+#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
+#define CONFIG_SYS_TSEC2_OFFSET	0x25000
+#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
+
+/*
+ * TSEC ethernet configuration
+ */
+#define CONFIG_MII		1 /* MII PHY management */
+#define CONFIG_TSEC1_NAME	"eTSEC0"
+#define CONFIG_TSEC2_NAME	"eTSEC1"
+#define TSEC1_PHY_ADDR		2
+#define TSEC2_PHY_ADDR		1
+#define TSEC1_PHYIDX		0
+#define TSEC2_PHYIDX		0
+#define TSEC1_FLAGS		TSEC_GIGABIT
+#define TSEC2_FLAGS		TSEC_GIGABIT
+
+/* Options are: eTSEC[0-1] */
+#define CONFIG_ETHPRIME		"eTSEC0"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
+				 CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_PING
+
+#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
+#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
+
+#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Core HID Setup
+ */
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE | \
+				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
+#define CONFIG_SYS_HID2		HID2_HBE
+
+/*
+ * MMU Setup
+ */
+
+/* DDR: cache cacheable */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+
+/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
+					BATU_VP)
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+
+/* FLASH: icache cacheable, but dcache-inhibit and guarded */
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
+					BATL_CACHEINHIBIT | \
+					BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+
+/* Stack in dcache: cacheable, no memory coherence */
+#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
+#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
+					BATU_VS | BATU_VP)
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02 /* Software reboot */
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_ENV_OVERWRITE
+
+#if defined(CONFIG_TSEC_ENET)
+#define CONFIG_HAS_ETH0
+#define CONFIG_HAS_ETH1
+#endif
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */
+
+#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
+
+#define xstr(s)	str(s)
+#define str(s)	#s
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=${serverip}:${rootpath}\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs ${bootargs} "				\
+		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
+		":${hostname}:${netdev}:off panic=1\0"			\
+	"addtty=setenv bootargs ${bootargs}"				\
+		" console=${consoledev},${baudrate}\0"			\
+	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
+	"addmisc=setenv bootargs ${bootargs}\0"				\
+	"kernel_addr=FE080000\0"					\
+	"fdt_addr=FE280000\0"						\
+	"ramdisk_addr=FE290000\0"					\
+	"u-boot=mpc8308rdb/u-boot.bin\0"				\
+	"kernel_addr_r=1000000\0"					\
+	"fdt_addr_r=C00000\0"						\
+	"hostname=mpc8308rdb\0"						\
+	"bootfile=mpc8308rdb/uImage\0"					\
+	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
+	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
+	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty addmtd addmisc;"		\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"bootcmd=run flash_self\0"					\
+	"load=tftp ${loadaddr} ${u-boot}\0"				\
+	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
+		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};cp.b ${fileaddr} "			\
+		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+	"upd=run load update\0"						\
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 4e43b2e861b981560b19c037c801b56c87575351 Mon Sep 17 00:00:00 2001
From: Heiko Schocher <hs@denx.de>
Date: Wed, 7 Jul 2010 12:26:34 +0200
Subject: 83xx: add support for ve8313 board

This patch add support for the ve8313 board based on
Freescale MPC8313 CPU.

- serial console on UART 1
- 128 MB DDR RAM
- 32 MB NOR Flash
- 16 MB NAND Flash
- Ethernet MII Mode over on TSEC0
- micrel ksz804 phy
- Hardware WDT MAX824

changes since v1
- Environment size = sector size
- use red. environment
- add comments from Kim Phillips
  - add MAKEALL, MAINTAINERS entry
  - Codingstyle issues fixed
  - inserted original Copyrights
  - PCI subsys vendor ID changed from 0x1057 (Motorola)
    to 0x1957 (Freescale)

changes since v2
- add comments from Wolfgang Denk
  - fix Codingstyle and some comments
  - reworked WDT reset (just toggling the WD_TRIG pin)
  - Environment size now 16KiB
  - fixed RAMBOOT version
  - fixed CONFIG_SYS_LOAD_ADDR
  - renamed CONFIG_TSEC1_NAME to TSEC1

Signed-off-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
---
 MAINTAINERS              |   1 +
 MAKEALL                  |   1 +
 board/ve8313/Makefile    |  50 +++++
 board/ve8313/config.mk   |   7 +
 board/ve8313/ve8313.c    | 215 ++++++++++++++++++++
 boards.cfg               |   1 +
 include/configs/ve8313.h | 511 +++++++++++++++++++++++++++++++++++++++++++++++
 7 files changed, 786 insertions(+)
 create mode 100644 board/ve8313/Makefile
 create mode 100644 board/ve8313/config.mk
 create mode 100644 board/ve8313/ve8313.c
 create mode 100644 include/configs/ve8313.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index d9158cec5a6..67d1d133fa2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -428,6 +428,7 @@ Heiko Schocher <hs@denx.de>
 	sc3		PPC405GP
 	suen3		ARM926EJS (Kirkwood SoC)
 	uc101		MPC5200
+	ve8313		MPC8313
 
 Peter De Schrijver <p2@mind.be>
 
diff --git a/MAKEALL b/MAKEALL
index e7651dc462b..ac41a517c0b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -381,6 +381,7 @@ LIST_83xx="		\
 	sbc8349		\
 	SIMPC8313_LP	\
 	TQM834x		\
+	ve8313		\
 	vme8349		\
 "
 
diff --git a/board/ve8313/Makefile b/board/ve8313/Makefile
new file mode 100644
index 00000000000..c95f90eaab8
--- /dev/null
+++ b/board/ve8313/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/ve8313/config.mk b/board/ve8313/config.mk
new file mode 100644
index 00000000000..02dd33e905e
--- /dev/null
+++ b/board/ve8313/config.mk
@@ -0,0 +1,7 @@
+ifndef NAND_SPL
+sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp
+endif
+
+ifndef TEXT_BASE
+TEXT_BASE = 0xfe000000
+endif
diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c
new file mode 100644
index 00000000000..8ba1b193a4b
--- /dev/null
+++ b/board/ve8313/ve8313.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
+ *
+ * Author: Scott Wood <scottwood@freescale.com>
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <libfdt.h>
+#include <pci.h>
+#include <mpc83xx.h>
+#include <ns16550.h>
+#include <nand.h>
+
+#include <asm/bitops.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void disable_addr_trans (void);
+extern void enable_addr_trans (void);
+
+int checkboard(void)
+{
+	puts("Board: ve8313\n");
+	return 0;
+}
+
+static long fixed_sdram(void)
+{
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
+
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize_log2 = __ilog2(msize);
+
+	out_be32(&im->sysconf.ddrlaw[0].bar,
+		(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
+	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
+	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
+
+	/*
+	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
+	 * or the DDR2 controller may fail to initialize correctly.
+	 */
+	__udelay(50000);
+
+	out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
+	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CONFIG);
+
+	/* Currently we use only one CS, so disable the other bank. */
+	out_be32(&im->ddr.cs_config[1], 0);
+
+	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
+	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+
+	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
+
+	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
+	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
+	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
+
+	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
+	sync();
+
+	/* enable DDR controller */
+	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
+
+	/* now check the real size */
+	disable_addr_trans ();
+	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
+	enable_addr_trans ();
+#endif
+
+	return msize;
+}
+
+phys_size_t initdram(int board_type)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile fsl_lbus_t *lbc = &im->lbus;
+	u32 msize;
+
+	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
+		return -1;
+
+	/* DDR SDRAM - Main SODIMM */
+	msize = fixed_sdram();
+
+	/* Local Bus setup lbcr and mrtpr */
+	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
+	sync();
+
+	/* return total bus SDRAM size(bytes)  -- DDR */
+	return msize;
+}
+
+#define VE8313_WDT_EN	0x00020000
+#define VE8313_WDT_TRIG	0x00040000
+
+int board_early_init_f (void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+
+#if defined(CONFIG_HW_WATCHDOG)
+	/* enable WDT */
+	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#else
+	/* disable WDT */
+	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
+#endif
+	/* set WDT pins as output */
+	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
+
+	return 0;
+}
+
+#if defined(CONFIG_HW_WATCHDOG)
+void hw_watchdog_reset(void)
+{
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
+	unsigned long reg;
+
+	reg = in_be32(&gpio->dat);
+	if (reg & VE8313_WDT_TRIG)
+		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+	else
+		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
+}
+#endif
+
+
+#if defined(CONFIG_PCI)
+static struct pci_region pci_regions[] = {
+	{
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
+		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
+		flags: PCI_REGION_MEM
+	},
+	{
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
+		flags: PCI_REGION_IO
+	}
+};
+
+void pci_init_board(void)
+{
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
+	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	struct pci_region *reg[] = { pci_regions };
+	int warmboot;
+
+	/* Enable all 3 PCI_CLK_OUTPUTs. */
+	setbits_be32(&clk->occr, 0xe0000000);
+
+	/*
+	 * Configure PCI Local Access Windows
+	 */
+	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
+	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
+
+	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
+
+	mpc83xx_pci_init(1, reg, warmboot);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
+}
+#endif
diff --git a/boards.cfg b/boards.cfg
index c23696f1399..db8ed2d990e 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -132,6 +132,7 @@ ZPC1900		powerpc	mpc8260		zpc1900
 mgcoge		powerpc	mpc8260		-		keymile
 SCM		powerpc	mpc8260		-		siemens
 TQM8272		powerpc	mpc8260		tqm8272		tqc
+ve8313		powerpc	mpc83xx		ve8313
 kmeter1		powerpc	mpc83xx		kmeter1		keymile
 MVBLM7		powerpc	mpc83xx		mvblm7		matrix_vision
 TQM834x		powerpc	mpc83xx		tqm834x		tqc
diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h
new file mode 100644
index 00000000000..1589913a5e6
--- /dev/null
+++ b/include/configs/ve8313.h
@@ -0,0 +1,511 @@
+/*
+ * Copyright (C) Freescale Semiconductor, Inc. 2006.
+ *
+ * (C) Copyright 2010
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+/*
+ * ve8313 board configuration file
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_E300		1
+#define CONFIG_MPC83xx		1
+#define CONFIG_MPC831x		1
+#define CONFIG_MPC8313		1
+#define CONFIG_VE8313		1
+
+#define CONFIG_PCI		1
+
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+/*
+ * On-board devices
+ *
+ */
+#define CONFIG_83XX_CLKIN	32000000	/* in Hz */
+
+#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
+
+#define CONFIG_SYS_IMMR		0xE0000000
+
+#define CONFIG_SYS_MEMTEST_START	0x00001000
+#define CONFIG_SYS_MEMTEST_END		0x07000000
+
+#define CONFIG_SYS_ACR_PIPE_DEP		3	/* Arbiter pipeline depth */
+#define CONFIG_SYS_ACR_RPTCNT		3	/* Arbiter repeat count */
+
+/*
+ * Device configurations
+ */
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_SYS_DDR_BASE		0x00000000	/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+
+/*
+ * Manually set up DDR parameters, as this board does not
+ * have the SPD connected to I2C.
+ */
+#define CONFIG_SYS_DDR_SIZE		128		/* MB */
+#define CONFIG_SYS_DDR_CONFIG		( CSCONFIG_EN \
+				| CSCONFIG_AP \
+				| 0x00040000 /* TODO */ \
+				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
+				/* 0x80840102 */
+
+#define CONFIG_SYS_DDR_TIMING_3	0x00000000
+#define CONFIG_SYS_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
+				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
+				| ( 3 << TIMING_CFG0_RRT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_WWT_SHIFT ) \
+				| ( 7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
+				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
+				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
+				/* 0x0e720802 */
+#define CONFIG_SYS_DDR_TIMING_1	( ( 2 << TIMING_CFG1_PRETOACT_SHIFT ) \
+				| ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTORW_SHIFT ) \
+				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
+				| ( 6 << TIMING_CFG1_REFREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRREC_SHIFT ) \
+				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
+				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
+				/* 0x26256222 */
+#define CONFIG_SYS_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
+				| ( 5 << TIMING_CFG2_CPO_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
+				| ( 1 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
+				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
+				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
+				| ( 7 << TIMING_CFG2_FOUR_ACT_SHIFT) )
+				/* 0x029028c7 */
+#define CONFIG_SYS_DDR_INTERVAL	( ( 0x320 << SDRAM_INTERVAL_REFINT_SHIFT ) \
+				| ( 0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
+				/* 0x03202000 */
+#define CONFIG_SYS_SDRAM_CFG		( SDRAM_CFG_SREN \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
+				| SDRAM_CFG_32_BE )
+				/* 0x43080000 */
+#define CONFIG_SYS_SDRAM_CFG2		0x00401000
+#define CONFIG_SYS_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
+				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
+				/* 0x44400232 */
+#define CONFIG_SYS_DDR_MODE_2		0x8000C000
+
+#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
+				/*0x02000000*/
+#define CONFIG_SYS_DDRCDR_VALUE	( DDRCDR_EN \
+				| DDRCDR_PZ_NOMZ \
+				| DDRCDR_NZ_NOMZ \
+				| DDRCDR_M_ODR )
+				/* 0x73000002 */
+
+/*
+ * FLASH on the Local Bus
+ */
+#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
+#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
+#define CONFIG_SYS_FLASH_BASE		0xFE000000
+#define CONFIG_SYS_FLASH_SIZE		32	/* size in MB */
+#define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* buffer up multiple bytes */
+
+#define CONFIG_SYS_NOR_BR_PRELIM	(CONFIG_SYS_FLASH_BASE | \
+				(2 << BR_PS_SHIFT) |	/* 16 bit */ \
+				BR_V)			/* valid */
+#define CONFIG_SYS_NOR_OR_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
+				| OR_GPCM_CSNT \
+				| OR_GPCM_ACS_DIV4 \
+				| OR_GPCM_SCY_5 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EAD)
+				/* 0xfe000c55 */
+
+#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32 MB window size */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	256		/* sectors per dev */
+
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor */
+
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFD000000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_END		0x1000	/* End of used area in RAM*/
+
+#define CONFIG_SYS_GBL_DATA_SIZE	0x100	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
+					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
+#define CONFIG_SYS_MONITOR_LEN		(384 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)
+
+/*
+ * Local Bus LCRR and LBCR regs
+ */
+#define CONFIG_SYS_LCRR_EADC	LCRR_EADC_3
+#define CONFIG_SYS_LCRR_CLKDIV	LCRR_CLKDIV_2
+
+#define CONFIG_SYS_LBC_LBCR	0x00040000
+
+#define CONFIG_SYS_LBC_MRTPR	0x20000000
+
+/*
+ * NAND settings
+ */
+#define CONFIG_SYS_NAND_BASE		0x61000000
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND 1
+#define CONFIG_NAND_FSL_ELBC 1
+#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
+
+#define CONFIG_SYS_NAND_BR_PRELIM	( CONFIG_SYS_NAND_BASE \
+				| BR_PS_8		\
+				| BR_DECC_CHK_GEN	\
+				| BR_MS_FCM		\
+				| BR_V )	/* valid */
+				/* 0x61000c21 */
+#define CONFIG_SYS_NAND_OR_PRELIM	(0xffff8000 \
+				| OR_FCM_BCTLD \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_2 \
+				| OR_FCM_RST \
+				| OR_FCM_TRLX)
+				/* 0xffff90ac */
+
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
+
+#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */
+
+#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
+#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
+
+/* CS2 NvRAM */
+#define CONFIG_SYS_BR2_PRELIM	(0x60000000	\
+				| BR_PS_8	\
+				| BR_V)
+				/* 0x60000801 */
+#define CONFIG_SYS_OR2_PRELIM	(0xfffe0000	\
+				| OR_GPCM_CSNT	\
+				| OR_GPCM_XACS	\
+				| OR_GPCM_SCY_3 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+				/* 0xfffe0937 */
+/* local bus read write buffer mapping SRAM@0x64000000 */
+#define CONFIG_SYS_BR3_PRELIM	(0x62000000	\
+				| BR_PS_16	\
+				| BR_V)
+				/* 0x62001001 */
+
+#define CONFIG_SYS_OR3_PRELIM	(0xfe000000	\
+				| OR_GPCM_CSNT	\
+				| OR_GPCM_XACS	\
+				| OR_GPCM_SCY_15 \
+				| OR_GPCM_TRLX \
+				| OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+				/* 0xfe0009f7 */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
+
+/*
+ * Serial Port
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#if defined(CONFIG_PCI)
+/*
+ * General PCI
+ * Addresses are mapped 1-1.
+ */
+#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
+#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
+#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
+#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
+#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
+#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCI1_IO_PHYS	0xE2000000
+#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
+
+#define CONFIG_PCI_PNP		/* do pci plug-and-play */
+#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
+#endif
+
+/*
+ * TSEC
+ */
+#define CONFIG_TSEC_ENET		/* TSEC ethernet support */
+
+#define CONFIG_NET_MULTI
+
+#define CONFIG_TSEC1
+#ifdef CONFIG_TSEC1
+#define CONFIG_HAS_ETH0
+#define CONFIG_TSEC1_NAME	"TSEC1"
+#define CONFIG_SYS_TSEC1_OFFSET	0x24000
+#define TSEC1_PHY_ADDR		0x01
+#define TSEC1_FLAGS		0
+#define TSEC1_PHYIDX		0
+#endif
+
+/* Options are: TSEC[0-1] */
+#define CONFIG_ETHPRIME			"TSEC1"
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + \
+					CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K(one sector) for env */
+#define CONFIG_ENV_SIZE		0x4000
+/* Address and size of Redundant Environment Sector */
+#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+					CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMDLINE_EDITING 1
+#define CONFIG_AUTO_COMPLETE	/* add autocompletion support   */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory */
+#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of cmd args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE /* Boot arg Buffer size */
+#define CONFIG_SYS_HZ		1000		/* 1ms ticks */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/
+
+/* 0x64050000 */
+#define CONFIG_SYS_HRCW_LOW (\
+	0x20000000 /* reserved, must be set */ |\
+	HRCWL_DDRCM |\
+	HRCWL_CSB_TO_CLKIN_4X1 | \
+	HRCWL_CORE_TO_CSB_2_5X1)
+
+/* 0xa0600004 */
+#define CONFIG_SYS_HRCW_HIGH (HRCWH_PCI_HOST | \
+	HRCWH_PCI_ARBITER_ENABLE | \
+	HRCWH_CORE_ENABLE | \
+	HRCWH_FROM_0X00000100 | \
+	HRCWH_BOOTSEQ_DISABLE |\
+	HRCWH_SW_WATCHDOG_DISABLE |\
+	HRCWH_ROM_LOC_LOCAL_16BIT | \
+	HRCWH_TSEC1M_IN_MII | \
+	HRCWH_BIG_ENDIAN | \
+	HRCWH_LALE_EARLY)
+
+/* System IO Config */
+#define CONFIG_SYS_SICRH	(0x01000000 | \
+				SICRH_ETSEC2_B | \
+				SICRH_ETSEC2_C | \
+				SICRH_ETSEC2_D | \
+				SICRH_ETSEC2_E | \
+				SICRH_ETSEC2_F | \
+				SICRH_ETSEC2_G | \
+				SICRH_TSOBI1 | \
+				SICRH_TSOBI2)
+				/* 0x010fff03 */
+#define CONFIG_SYS_SICRL	(SICRL_LBC | \
+				SICRL_SPI_A | \
+				SICRL_SPI_B | \
+				SICRL_SPI_C | \
+				SICRL_SPI_D | \
+				SICRL_ETSEC2_A)
+				/* 0x33fc0003) */
+
+#define CONFIG_SYS_HID0_INIT	0x000000000
+#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
+				 HID0_ENABLE_INSTRUCTION_CACHE)
+
+#define CONFIG_SYS_HID2 HID2_HBE
+
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
+/* DDR @ 0x00000000 */
+#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
+				 BATU_VS | BATU_VP)
+
+#if defined(CONFIG_PCI)
+/* PCI @ 0x80000000 */
+#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10)
+#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \
+				BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \
+				BATU_VS | BATU_VP)
+#else
+#define CONFIG_SYS_IBAT1L	(0)
+#define CONFIG_SYS_IBAT1U	(0)
+#define CONFIG_SYS_IBAT2L	(0)
+#define CONFIG_SYS_IBAT2U	(0)
+#endif
+
+/* PCI2 not supported on 8313 */
+#define CONFIG_SYS_IBAT3L	(0)
+#define CONFIG_SYS_IBAT3U	(0)
+#define CONFIG_SYS_IBAT4L	(0)
+#define CONFIG_SYS_IBAT4U	(0)
+
+/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
+				BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \
+				BATU_VP)
+
+/* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
+#define CONFIG_SYS_IBAT6L	(0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+/*  FPGA, SRAM, NAND @ 0x60000000 */
+#define CONFIG_SYS_IBAT7L	(0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE)
+#define CONFIG_SYS_IBAT7U	(0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+
+#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
+#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
+#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
+#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
+#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
+#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
+#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
+#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
+#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02	/* Software reboot */
+
+#define CONFIG_NETDEV		eth0
+
+#define CONFIG_HOSTNAME		ve8313
+#define CONFIG_UBOOTPATH	ve8313/u-boot.bin
+
+#define CONFIG_BOOTDELAY	6	/* -1 disables auto-boot */
+#define CONFIG_BAUDRATE		115200
+
+#define XMK_STR(x)	#x
+#define MK_STR(x)	XMK_STR(x)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"netdev=" MK_STR(CONFIG_NETDEV) "\0"				\
+	"ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0"			\
+	"u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
+	"u-boot_addr_r=100000\0"					\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+	"erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+	"cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+	" ${filesize};" \
+	"protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
+
+#undef MK_STR
+#undef XMK_STR
+
+#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From 5b1b1883ffcb75de71a0b4e66b279c88ae1e15fc Mon Sep 17 00:00:00 2001
From: Vipin KUMAR <vipin.kumar@st.com>
Date: Tue, 29 Jun 2010 10:53:34 +0530
Subject: SPEAr : Network driver support added

Designware network driver support added.
This is a Synopsys ethernet controller

Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 doc/README.designware_eth |  25 +++
 drivers/net/Makefile      |   1 +
 drivers/net/designware.c  | 531 ++++++++++++++++++++++++++++++++++++++++++++++
 drivers/net/designware.h  | 264 +++++++++++++++++++++++
 include/netdev.h          |   1 +
 5 files changed, 822 insertions(+)
 create mode 100644 doc/README.designware_eth
 create mode 100644 drivers/net/designware.c
 create mode 100644 drivers/net/designware.h

(limited to 'include')

diff --git a/doc/README.designware_eth b/doc/README.designware_eth
new file mode 100644
index 00000000000..25ec6bd9699
--- /dev/null
+++ b/doc/README.designware_eth
@@ -0,0 +1,25 @@
+This driver supports Designware Ethernet Controller provided by Synopsis.
+
+The driver is enabled by CONFIG_DESIGNWARE_ETH.
+
+The driver has been developed and tested on SPEAr platforms. By default, the
+MDIO interface works at 100/Full. #defining the below options in board
+configuration file changes this behavior.
+
+Call an subroutine from respective board/.../board.c
+designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
+
+The various options suported by the driver are
+1. CONFIG_DW_ALTDESCRIPTOR
+	Define this to use the Alternate/Enhanced Descriptor configurations.
+1. CONFIG_DW_AUTONEG
+	Define this to autonegotiate with the host before proceeding with mac
+	level configuration. This obviates the definitions of CONFIG_DW_SPEED10M
+	and CONFIG_DW_DUPLEXHALF.
+2. CONFIG_DW_SPEED10M
+	Define this to change the default behavior from 100Mbps to 10Mbps.
+3. CONFIG_DW_DUPLEXHALF
+	Define this to change the default behavior from Full Duplex to Half.
+4. CONFIG_DW_SEARCH_PHY
+	Define this to search the phy address. This would overwrite the value
+	passed as 3rd arg from designware_initialize routine.
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index b75c02f8c23..7a320fda023 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -34,6 +34,7 @@ COBJS-$(CONFIG_BCM570x) += bcm570x.o bcm570x_autoneg.o 5701rls.o
 COBJS-$(CONFIG_BFIN_MAC) += bfin_mac.o
 COBJS-$(CONFIG_CS8900) += cs8900.o
 COBJS-$(CONFIG_TULIP) += dc2114x.o
+COBJS-$(CONFIG_DESIGNWARE_ETH) += designware.o
 COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o
 COBJS-$(CONFIG_DNET) += dnet.o
 COBJS-$(CONFIG_E1000) += e1000.o
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
new file mode 100644
index 00000000000..d0d98277ea4
--- /dev/null
+++ b/drivers/net/designware.c
@@ -0,0 +1,531 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Designware ethernet IP driver for u-boot
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/io.h>
+#include "designware.h"
+
+static void tx_descs_init(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+	struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
+	char *txbuffs = &priv->txbuffs[0];
+	struct dmamacdescr *desc_p;
+	u32 idx;
+
+	for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
+		desc_p = &desc_table_p[idx];
+		desc_p->dmamac_addr = &txbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = &desc_table_p[idx + 1];
+
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+		desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
+				DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | \
+				DESC_TXSTS_TXCHECKINSCTRL | \
+				DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
+
+		desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
+		desc_p->dmamac_cntl = 0;
+		desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
+#else
+		desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
+		desc_p->txrx_status = 0;
+#endif
+	}
+
+	/* Correcting the last pointer of the chain */
+	desc_p->dmamac_next = &desc_table_p[0];
+
+	writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
+}
+
+static void rx_descs_init(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+	struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
+	char *rxbuffs = &priv->rxbuffs[0];
+	struct dmamacdescr *desc_p;
+	u32 idx;
+
+	for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
+		desc_p = &desc_table_p[idx];
+		desc_p->dmamac_addr = &rxbuffs[idx * CONFIG_ETH_BUFSIZE];
+		desc_p->dmamac_next = &desc_table_p[idx + 1];
+
+		desc_p->dmamac_cntl =
+			(MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | \
+				      DESC_RXCTRL_RXCHAIN;
+
+		desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
+	}
+
+	/* Correcting the last pointer of the chain */
+	desc_p->dmamac_next = &desc_table_p[0];
+
+	writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
+}
+
+static void descs_init(struct eth_device *dev)
+{
+	tx_descs_init(dev);
+	rx_descs_init(dev);
+}
+
+static int mac_reset(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+
+	int timeout = CONFIG_MACRESET_TIMEOUT;
+
+	writel(DMAMAC_SRST, &dma_p->busmode);
+	writel(MII_PORTSELECT, &mac_p->conf);
+
+	do {
+		if (!(readl(&dma_p->busmode) & DMAMAC_SRST))
+			return 0;
+		udelay(1000);
+	} while (timeout--);
+
+	return -1;
+}
+
+static int dw_write_hwaddr(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	u32 macid_lo, macid_hi;
+	u8 *mac_id = &dev->enetaddr[0];
+
+	macid_lo = mac_id[0] + (mac_id[1] << 8) + \
+		   (mac_id[2] << 16) + (mac_id[3] << 24);
+	macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+	writel(macid_hi, &mac_p->macaddr0hi);
+	writel(macid_lo, &mac_p->macaddr0lo);
+
+	return 0;
+}
+
+static int dw_eth_init(struct eth_device *dev, bd_t *bis)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+	u32 conf;
+
+	/* Reset ethernet hardware */
+	if (mac_reset(dev) < 0)
+		return -1;
+
+	writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
+			&dma_p->busmode);
+
+	writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
+	writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+
+	conf = FRAMEBURSTENABLE | DISABLERXOWN;
+
+	if (priv->speed != SPEED_1000M)
+		conf |= MII_PORTSELECT;
+
+	if (priv->duplex == FULL_DUPLEX)
+		conf |= FULLDPLXMODE;
+
+	writel(conf, &mac_p->conf);
+
+	descs_init(dev);
+
+	/*
+	 * Start/Enable xfer at dma as well as mac level
+	 */
+	writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode);
+	writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode);
+
+	writel(readl(&mac_p->conf) | RXENABLE, &mac_p->conf);
+	writel(readl(&mac_p->conf) | TXENABLE, &mac_p->conf);
+
+	return 0;
+}
+
+static int dw_eth_send(struct eth_device *dev, volatile void *packet,
+		int length)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_dma_regs *dma_p = priv->dma_regs_p;
+	u32 desc_num = priv->tx_currdescnum;
+	struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
+
+	/* Check if the descriptor is owned by CPU */
+	if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
+		printf("CPU not owner of tx frame\n");
+		return -1;
+	}
+
+	memcpy((void *)desc_p->dmamac_addr, (void *)packet, length);
+
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+	desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
+	desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & \
+			       DESC_TXCTRL_SIZE1MASK;
+
+	desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
+	desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
+#else
+	desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & \
+			       DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | \
+			       DESC_TXCTRL_TXFIRST;
+
+	desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
+#endif
+
+	/* Test the wrap-around condition. */
+	if (++desc_num >= CONFIG_TX_DESCR_NUM)
+		desc_num = 0;
+
+	priv->tx_currdescnum = desc_num;
+
+	/* Start the transmission */
+	writel(POLL_DATA, &dma_p->txpolldemand);
+
+	return 0;
+}
+
+static int dw_eth_recv(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	u32 desc_num = priv->rx_currdescnum;
+	struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
+
+	u32 status = desc_p->txrx_status;
+	int length = 0;
+
+	/* Check  if the owner is the CPU */
+	if (!(status & DESC_RXSTS_OWNBYDMA)) {
+
+		length = (status & DESC_RXSTS_FRMLENMSK) >> \
+			 DESC_RXSTS_FRMLENSHFT;
+
+		NetReceive(desc_p->dmamac_addr, length);
+
+		/*
+		 * Make the current descriptor valid again and go to
+		 * the next one
+		 */
+		desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
+
+		/* Test the wrap-around condition. */
+		if (++desc_num >= CONFIG_RX_DESCR_NUM)
+			desc_num = 0;
+	}
+
+	priv->rx_currdescnum = desc_num;
+
+	return length;
+}
+
+static void dw_eth_halt(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+
+	mac_reset(dev);
+	priv->tx_currdescnum = priv->rx_currdescnum = 0;
+}
+
+static int eth_mdio_read(struct eth_device *dev, u8 addr, u8 reg, u16 *val)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	u32 miiaddr;
+	int timeout = CONFIG_MDIO_TIMEOUT;
+
+	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
+		  ((reg << MIIREGSHIFT) & MII_REGMSK);
+
+	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+	do {
+		if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
+			*val = readl(&mac_p->miidata);
+			return 0;
+		}
+		udelay(1000);
+	} while (timeout--);
+
+	return -1;
+}
+
+static int eth_mdio_write(struct eth_device *dev, u8 addr, u8 reg, u16 val)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	struct eth_mac_regs *mac_p = priv->mac_regs_p;
+	u32 miiaddr;
+	int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+	u16 value;
+
+	writel(val, &mac_p->miidata);
+	miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | \
+		  ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
+
+	writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
+
+	do {
+		if (!(readl(&mac_p->miiaddr) & MII_BUSY))
+			ret = 0;
+		udelay(1000);
+	} while (timeout--);
+
+	/* Needed as a fix for ST-Phy */
+	eth_mdio_read(dev, addr, reg, &value);
+
+	return ret;
+}
+
+#if defined(CONFIG_DW_SEARCH_PHY)
+static int find_phy(struct eth_device *dev)
+{
+	int phy_addr = 0;
+	u16 ctrl, oldctrl;
+
+	do {
+		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+		oldctrl = ctrl & PHY_BMCR_AUTON;
+
+		ctrl ^= PHY_BMCR_AUTON;
+		eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+		ctrl &= PHY_BMCR_AUTON;
+
+		if (ctrl == oldctrl) {
+			phy_addr++;
+		} else {
+			ctrl ^= PHY_BMCR_AUTON;
+			eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+
+			return phy_addr;
+		}
+	} while (phy_addr < 32);
+
+	return -1;
+}
+#endif
+
+static int dw_reset_phy(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	u16 ctrl;
+	int timeout = CONFIG_PHYRESET_TIMEOUT;
+	u32 phy_addr = priv->address;
+
+	eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
+	do {
+		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
+		if (!(ctrl & PHY_BMCR_RESET))
+			break;
+		udelay(1000);
+	} while (timeout--);
+
+	if (timeout < 0)
+		return -1;
+
+#ifdef CONFIG_PHY_RESET_DELAY
+	udelay(CONFIG_PHY_RESET_DELAY);
+#endif
+	return 0;
+}
+
+static int configure_phy(struct eth_device *dev)
+{
+	struct dw_eth_dev *priv = dev->priv;
+	int phy_addr;
+	u16 bmcr, ctrl;
+#if defined(CONFIG_DW_AUTONEG)
+	u16 bmsr;
+	u32 timeout;
+	u16 anlpar, btsr;
+#endif
+
+#if defined(CONFIG_DW_SEARCH_PHY)
+	phy_addr = find_phy(dev);
+	if (phy_addr > 0)
+		priv->address = phy_addr;
+	else
+		return -1;
+#endif
+	if (dw_reset_phy(dev) < 0)
+		return -1;
+
+#if defined(CONFIG_DW_AUTONEG)
+	bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
+	       PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
+#else
+	bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
+
+#if defined(CONFIG_DW_SPEED10M)
+	bmcr &= ~PHY_BMCR_100MB;
+#endif
+#if defined(CONFIG_DW_DUPLEXHALF)
+	bmcr &= ~PHY_BMCR_DPLX;
+#endif
+#endif
+	if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
+		return -1;
+
+	/* Read the phy status register and populate priv structure */
+#if defined(CONFIG_DW_AUTONEG)
+	timeout = CONFIG_AUTONEG_TIMEOUT;
+	do {
+		eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
+		if (bmsr & PHY_BMSR_AUTN_COMP)
+			break;
+		udelay(1000);
+	} while (timeout--);
+
+	eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
+	eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
+
+	if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
+		priv->speed = SPEED_1000M;
+		if (btsr & PHY_1000BTSR_1000FD)
+			priv->duplex = FULL_DUPLEX;
+		else
+			priv->duplex = HALF_DUPLEX;
+	} else {
+		if (anlpar & PHY_ANLPAR_100)
+			priv->speed = SPEED_100M;
+		else
+			priv->speed = SPEED_10M;
+
+		if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+			priv->duplex = FULL_DUPLEX;
+		else
+			priv->duplex = HALF_DUPLEX;
+	}
+#else
+	if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
+		return -1;
+
+	if (ctrl & PHY_BMCR_DPLX)
+		priv->duplex = FULL_DUPLEX;
+	else
+		priv->duplex = HALF_DUPLEX;
+
+	if (ctrl & PHY_BMCR_1000_MBPS)
+		priv->speed = SPEED_1000M;
+	else if (ctrl & PHY_BMCR_100_MBPS)
+		priv->speed = SPEED_100M;
+	else
+		priv->speed = SPEED_10M;
+#endif
+	return 0;
+}
+
+#if defined(CONFIG_MII)
+static int dw_mii_read(char *devname, u8 addr, u8 reg, u16 *val)
+{
+	struct eth_device *dev;
+
+	dev = eth_get_dev_by_name(devname);
+	if (dev)
+		eth_mdio_read(dev, addr, reg, val);
+
+	return 0;
+}
+
+static int dw_mii_write(char *devname, u8 addr, u8 reg, u16 val)
+{
+	struct eth_device *dev;
+
+	dev = eth_get_dev_by_name(devname);
+	if (dev)
+		eth_mdio_write(dev, addr, reg, val);
+
+	return 0;
+}
+#endif
+
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr)
+{
+	struct eth_device *dev;
+	struct dw_eth_dev *priv;
+
+	dev = (struct eth_device *) malloc(sizeof(struct eth_device));
+	if (!dev)
+		return -ENOMEM;
+
+	/*
+	 * Since the priv structure contains the descriptors which need a strict
+	 * buswidth alignment, memalign is used to allocate memory
+	 */
+	priv = (struct dw_eth_dev *) memalign(16, sizeof(struct dw_eth_dev));
+	if (!priv) {
+		free(dev);
+		return -ENOMEM;
+	}
+
+	memset(dev, 0, sizeof(struct eth_device));
+	memset(priv, 0, sizeof(struct dw_eth_dev));
+
+	sprintf(dev->name, "mii%d", id);
+	dev->iobase = (int)base_addr;
+	dev->priv = priv;
+
+	eth_getenv_enetaddr_by_index(id, &dev->enetaddr[0]);
+
+	priv->dev = dev;
+	priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
+	priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
+			DW_DMA_BASE_OFFSET);
+	priv->address = phy_addr;
+
+	if (mac_reset(dev) < 0)
+		return -1;
+
+	if (configure_phy(dev) < 0) {
+		printf("Phy could not be configured\n");
+		return -1;
+	}
+
+	dev->init = dw_eth_init;
+	dev->send = dw_eth_send;
+	dev->recv = dw_eth_recv;
+	dev->halt = dw_eth_halt;
+	dev->write_hwaddr = dw_write_hwaddr;
+
+	eth_register(dev);
+
+#if defined(CONFIG_MII)
+	miiphy_register(dev->name, dw_mii_read, dw_mii_write);
+#endif
+	return 1;
+}
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
new file mode 100644
index 00000000000..e5828a6a581
--- /dev/null
+++ b/drivers/net/designware.h
@@ -0,0 +1,264 @@
+/*
+ * (C) Copyright 2010
+ * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DW_ETH_H
+#define _DW_ETH_H
+
+#define CONFIG_TX_DESCR_NUM	16
+#define CONFIG_RX_DESCR_NUM	16
+#define CONFIG_ETH_BUFSIZE	2048
+#define TX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
+#define RX_TOTAL_BUFSIZE	(CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
+
+#define CONFIG_MACRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CONFIG_MDIO_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CONFIG_PHYRESET_TIMEOUT	(3 * CONFIG_SYS_HZ)
+#define CONFIG_AUTONEG_TIMEOUT	(5 * CONFIG_SYS_HZ)
+
+struct eth_mac_regs {
+	u32 conf;		/* 0x00 */
+	u32 framefilt;		/* 0x04 */
+	u32 hashtablehigh;	/* 0x08 */
+	u32 hashtablelow;	/* 0x0c */
+	u32 miiaddr;		/* 0x10 */
+	u32 miidata;		/* 0x14 */
+	u32 flowcontrol;	/* 0x18 */
+	u32 vlantag;		/* 0x1c */
+	u32 version;		/* 0x20 */
+	u8 reserved_1[20];
+	u32 intreg;		/* 0x38 */
+	u32 intmask;		/* 0x3c */
+	u32 macaddr0hi;		/* 0x40 */
+	u32 macaddr0lo;		/* 0x44 */
+};
+
+/* MAC configuration register definitions */
+#define FRAMEBURSTENABLE	(1 << 21)
+#define MII_PORTSELECT		(1 << 15)
+#define FES_100			(1 << 14)
+#define DISABLERXOWN		(1 << 13)
+#define FULLDPLXMODE		(1 << 11)
+#define RXENABLE		(1 << 2)
+#define TXENABLE		(1 << 3)
+
+/* MII address register definitions */
+#define MII_BUSY		(1 << 0)
+#define MII_WRITE		(1 << 1)
+#define MII_CLKRANGE_60_100M	(0)
+#define MII_CLKRANGE_100_150M	(0x4)
+#define MII_CLKRANGE_20_35M	(0x8)
+#define MII_CLKRANGE_35_60M	(0xC)
+#define MII_CLKRANGE_150_250M	(0x10)
+#define MII_CLKRANGE_250_300M	(0x14)
+
+#define MIIADDRSHIFT		(11)
+#define MIIREGSHIFT		(6)
+#define MII_REGMSK		(0x1F << 6)
+#define MII_ADDRMSK		(0x1F << 11)
+
+
+struct eth_dma_regs {
+	u32 busmode;		/* 0x00 */
+	u32 txpolldemand;	/* 0x04 */
+	u32 rxpolldemand;	/* 0x08 */
+	u32 rxdesclistaddr;	/* 0x0c */
+	u32 txdesclistaddr;	/* 0x10 */
+	u32 status;		/* 0x14 */
+	u32 opmode;		/* 0x18 */
+	u32 intenable;		/* 0x1c */
+	u8 reserved[40];
+	u32 currhosttxdesc;	/* 0x48 */
+	u32 currhostrxdesc;	/* 0x4c */
+	u32 currhosttxbuffaddr;	/* 0x50 */
+	u32 currhostrxbuffaddr;	/* 0x54 */
+};
+
+#define DW_DMA_BASE_OFFSET	(0x1000)
+
+/* Bus mode register definitions */
+#define FIXEDBURST		(1 << 16)
+#define PRIORXTX_41		(3 << 14)
+#define PRIORXTX_31		(2 << 14)
+#define PRIORXTX_21		(1 << 14)
+#define PRIORXTX_11		(0 << 14)
+#define BURST_1			(1 << 8)
+#define BURST_2			(2 << 8)
+#define BURST_4			(4 << 8)
+#define BURST_8			(8 << 8)
+#define BURST_16		(16 << 8)
+#define BURST_32		(32 << 8)
+#define RXHIGHPRIO		(1 << 1)
+#define DMAMAC_SRST		(1 << 0)
+
+/* Poll demand definitions */
+#define POLL_DATA		(0xFFFFFFFF)
+
+/* Operation mode definitions */
+#define STOREFORWARD		(1 << 21)
+#define FLUSHTXFIFO		(1 << 20)
+#define TXSTART			(1 << 13)
+#define TXSECONDFRAME		(1 << 2)
+#define RXSTART			(1 << 1)
+
+/* Descriptior related definitions */
+#define MAC_MAX_FRAME_SZ	(2048)
+
+struct dmamacdescr {
+	u32 txrx_status;
+	u32 dmamac_cntl;
+	void *dmamac_addr;
+	struct dmamacdescr *dmamac_next;
+};
+
+/*
+ * txrx_status definitions
+ */
+
+/* tx status bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_TXSTS_OWNBYDMA		(1 << 31)
+#define DESC_TXSTS_TXINT		(1 << 30)
+#define DESC_TXSTS_TXLAST		(1 << 29)
+#define DESC_TXSTS_TXFIRST		(1 << 28)
+#define DESC_TXSTS_TXCRCDIS		(1 << 27)
+
+#define DESC_TXSTS_TXPADDIS		(1 << 26)
+#define DESC_TXSTS_TXCHECKINSCTRL	(3 << 22)
+#define DESC_TXSTS_TXRINGEND		(1 << 21)
+#define DESC_TXSTS_TXCHAIN		(1 << 20)
+#define DESC_TXSTS_MSK			(0x1FFFF << 0)
+
+#else
+
+#define DESC_TXSTS_OWNBYDMA		(1 << 31)
+#define DESC_TXSTS_MSK			(0x1FFFF << 0)
+
+#endif
+
+/* rx status bits definitions */
+#define DESC_RXSTS_OWNBYDMA		(1 << 31)
+#define DESC_RXSTS_DAFILTERFAIL		(1 << 30)
+#define DESC_RXSTS_FRMLENMSK		(0x3FFF << 16)
+#define DESC_RXSTS_FRMLENSHFT		(16)
+
+#define DESC_RXSTS_ERROR		(1 << 15)
+#define DESC_RXSTS_RXTRUNCATED		(1 << 14)
+#define DESC_RXSTS_SAFILTERFAIL		(1 << 13)
+#define DESC_RXSTS_RXIPC_GIANTFRAME	(1 << 12)
+#define DESC_RXSTS_RXDAMAGED		(1 << 11)
+#define DESC_RXSTS_RXVLANTAG		(1 << 10)
+#define DESC_RXSTS_RXFIRST		(1 << 9)
+#define DESC_RXSTS_RXLAST		(1 << 8)
+#define DESC_RXSTS_RXIPC_GIANT		(1 << 7)
+#define DESC_RXSTS_RXCOLLISION		(1 << 6)
+#define DESC_RXSTS_RXFRAMEETHER		(1 << 5)
+#define DESC_RXSTS_RXWATCHDOG		(1 << 4)
+#define DESC_RXSTS_RXMIIERROR		(1 << 3)
+#define DESC_RXSTS_RXDRIBBLING		(1 << 2)
+#define DESC_RXSTS_RXCRC		(1 << 1)
+
+/*
+ * dmamac_cntl definitions
+ */
+
+/* tx control bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_TXCTRL_SIZE1MASK		(0x1FFF << 0)
+#define DESC_TXCTRL_SIZE1SHFT		(0)
+#define DESC_TXCTRL_SIZE2MASK		(0x1FFF << 16)
+#define DESC_TXCTRL_SIZE2SHFT		(16)
+
+#else
+
+#define DESC_TXCTRL_TXINT		(1 << 31)
+#define DESC_TXCTRL_TXLAST		(1 << 30)
+#define DESC_TXCTRL_TXFIRST		(1 << 29)
+#define DESC_TXCTRL_TXCHECKINSCTRL	(3 << 27)
+#define DESC_TXCTRL_TXCRCDIS		(1 << 26)
+#define DESC_TXCTRL_TXRINGEND		(1 << 25)
+#define DESC_TXCTRL_TXCHAIN		(1 << 24)
+
+#define DESC_TXCTRL_SIZE1MASK		(0x7FF << 0)
+#define DESC_TXCTRL_SIZE1SHFT		(0)
+#define DESC_TXCTRL_SIZE2MASK		(0x7FF << 11)
+#define DESC_TXCTRL_SIZE2SHFT		(11)
+
+#endif
+
+/* rx control bits definitions */
+#if defined(CONFIG_DW_ALTDESCRIPTOR)
+
+#define DESC_RXCTRL_RXINTDIS		(1 << 31)
+#define DESC_RXCTRL_RXRINGEND		(1 << 15)
+#define DESC_RXCTRL_RXCHAIN		(1 << 14)
+
+#define DESC_RXCTRL_SIZE1MASK		(0x1FFF << 0)
+#define DESC_RXCTRL_SIZE1SHFT		(0)
+#define DESC_RXCTRL_SIZE2MASK		(0x1FFF << 16)
+#define DESC_RXCTRL_SIZE2SHFT		(16)
+
+#else
+
+#define DESC_RXCTRL_RXINTDIS		(1 << 31)
+#define DESC_RXCTRL_RXRINGEND		(1 << 25)
+#define DESC_RXCTRL_RXCHAIN		(1 << 24)
+
+#define DESC_RXCTRL_SIZE1MASK		(0x7FF << 0)
+#define DESC_RXCTRL_SIZE1SHFT		(0)
+#define DESC_RXCTRL_SIZE2MASK		(0x7FF << 11)
+#define DESC_RXCTRL_SIZE2SHFT		(11)
+
+#endif
+
+struct dw_eth_dev {
+	u32 address;
+	u32 speed;
+	u32 duplex;
+	u32 tx_currdescnum;
+	u32 rx_currdescnum;
+	u32 padding;
+
+	struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
+	struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+
+	char txbuffs[TX_TOTAL_BUFSIZE];
+	char rxbuffs[RX_TOTAL_BUFSIZE];
+
+	struct eth_mac_regs *mac_regs_p;
+	struct eth_dma_regs *dma_regs_p;
+
+	struct eth_device *dev;
+} __attribute__ ((aligned(8)));
+
+/* Speed specific definitions */
+#define SPEED_10M		1
+#define SPEED_100M		2
+#define SPEED_1000M		3
+
+/* Duplex mode specific definitions */
+#define HALF_DUPLEX		1
+#define FULL_DUPLEX		2
+
+#endif
diff --git a/include/netdev.h b/include/netdev.h
index 882642a2c44..3abc944e4c3 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -49,6 +49,7 @@ int bfin_EMAC_initialize(bd_t *bis);
 int cs8900_initialize(u8 dev_num, int base_addr);
 int dc21x4x_initialize(bd_t *bis);
 int davinci_emac_initialize(void);
+int designware_initialize(u32 id, ulong base_addr, u32 phy_addr);
 int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int e1000_initialize(bd_t *bis);
 int eepro100_initialize(bd_t *bis);
-- 
cgit v1.3.1


From 36de21106058d2e8d6bb7a2bd3de6a427b5c5533 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 10 May 2010 16:08:54 -0400
Subject: AX88180: add missing init prototype

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 include/netdev.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/netdev.h b/include/netdev.h
index 3abc944e4c3..eb04b638767 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -43,6 +43,7 @@ int cpu_eth_init(bd_t *bis);
 /* Driver initialization prototypes */
 int altera_tse_initialize(u8 dev_num, int mac_base,
 			  int sgdma_rx_base, int sgdma_tx_base);
+int ax88180_initialize(bd_t *bis);
 int au1x00_enet_initialize(bd_t*);
 int at91emac_register(bd_t *bis, unsigned long iobase);
 int bfin_EMAC_initialize(bd_t *bis);
-- 
cgit v1.3.1


From 836cd453583627cbef784bd4d7963109d5914bde Mon Sep 17 00:00:00 2001
From: Eric Bénard <eric@eukrea.com>
Date: Mon, 21 Jun 2010 09:40:43 +0200
Subject: cpuat91: unbreak ethernet
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* the following problems are met :
config was set to use the new driver as a default but
- RMII was not enabled for the new driver
- the new driver didn't compile with RMII enabled
- the new driver initialize a PHY at address O when the PHY of
this board is at 1 thus we get "AT91 EMAC RMII: No PHY present"

* to fix these problems, this patch :
- enable RMII for the new driver
- fix the wrong define used in the at91_emac.c
- allow the config file to set a default phy address (and use
0 as a default as in the actual at91_emac.c driver)

Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 drivers/net/at91_emac.c   | 32 ++++++++++++++++++++++----------
 include/configs/cpuat91.h |  9 +++------
 2 files changed, 25 insertions(+), 16 deletions(-)

(limited to 'include')

diff --git a/drivers/net/at91_emac.c b/drivers/net/at91_emac.c
index fa72e2cabdf..245da121b94 100644
--- a/drivers/net/at91_emac.c
+++ b/drivers/net/at91_emac.c
@@ -53,6 +53,10 @@
 	Please decrease the CONFIG_SYS_RX_ETH_BUFFER value
 #endif
 
+#ifndef CONFIG_DRIVER_AT91EMAC_PHYADDR
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR	0
+#endif
+
 /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
 #if (AT91C_MASTER_CLOCK > 80000000)
 	#define HCLK_DIV	AT91_EMAC_CFG_MCLK_64
@@ -198,12 +202,15 @@ static int at91emac_phy_reset(struct eth_device *netdev)
 	emac = (at91_emac_t *) netdev->iobase;
 
 	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
-	at91emac_write(emac, 0, MII_ADVERTISE, adv);
+	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+		MII_ADVERTISE, adv);
 	VERBOSEP("%s: Starting autonegotiation...\n", netdev->name);
-	at91emac_write(emac, 0, MII_BMCR, (BMCR_ANENABLE | BMCR_ANRESTART));
+	at91emac_write(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMCR,
+		(BMCR_ANENABLE | BMCR_ANRESTART));
 
 	for (i = 0; i < 100000 / 100; i++) {
-		at91emac_read(emac, 0, MII_BMSR, &status);
+		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+			MII_BMSR, &status);
 		if (status & BMSR_ANEGCOMPLETE)
 			break;
 		udelay(100);
@@ -229,13 +236,15 @@ static int at91emac_phy_init(struct eth_device *netdev)
 	emac = (at91_emac_t *) netdev->iobase;
 
 	/* Check if the PHY is up to snuff... */
-	at91emac_read(emac, 0, MII_PHYSID1, &phy_id);
+	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+		MII_PHYSID1, &phy_id);
 	if (phy_id == 0xffff) {
 		printf("%s: No PHY present\n", netdev->name);
 		return 1;
 	}
 
-	at91emac_read(emac, 0, MII_BMSR, &status);
+	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+		MII_BMSR, &status);
 
 	if (!(status & BMSR_LSTATUS)) {
 		/* Try to re-negotiate if we don't have link already. */
@@ -243,7 +252,8 @@ static int at91emac_phy_init(struct eth_device *netdev)
 			return 2;
 
 		for (i = 0; i < 100000 / 100; i++) {
-			at91emac_read(emac, 0, MII_BMSR, &status);
+			at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+				MII_BMSR, &status);
 			if (status & BMSR_LSTATUS)
 				break;
 			udelay(100);
@@ -253,8 +263,10 @@ static int at91emac_phy_init(struct eth_device *netdev)
 		VERBOSEP("%s: link down\n", netdev->name);
 		return 3;
 	} else {
-		at91emac_read(emac, 0, MII_ADVERTISE, &adv);
-		at91emac_read(emac, 0, MII_LPA, &lpa);
+		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+			MII_ADVERTISE, &adv);
+		at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR,
+			MII_LPA, &lpa);
 		media = mii_nway_result(lpa & adv);
 		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
 			 ? 1 : 0);
@@ -271,7 +283,7 @@ int at91emac_UpdateLinkSpeed(at91_emac_t *emac)
 {
 	unsigned short stat1;
 
-	at91emac_read(emac, 0, MII_BMSR, &stat1);
+	at91emac_read(emac, CONFIG_DRIVER_AT91EMAC_PHYADDR, MII_BMSR, &stat1);
 
 	if (!(stat1 & BMSR_LSTATUS))	/* link status up? */
 		return 1;
@@ -364,7 +376,7 @@ static int at91emac_init(struct eth_device *netdev, bd_t *bd)
 	value = AT91_EMAC_CFG_CAF |	AT91_EMAC_CFG_NBC |
 		HCLK_DIV;
 #ifdef CONFIG_RMII
-	value |= AT91C_EMAC_RMII;
+	value |= AT91_EMAC_CFG_RMII;
 #endif
 	writel(value, &emac->cfg);
 
diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h
index b4fda767310..049298cfa36 100644
--- a/include/configs/cpuat91.h
+++ b/include/configs/cpuat91.h
@@ -131,15 +131,12 @@
 	(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 512 * 1024)
 
 #define CONFIG_NET_MULTI		1
-#ifdef CONFIG_NET_MULTI
 #define CONFIG_DRIVER_AT91EMAC		1
 #define CONFIG_SYS_RX_ETH_BUFFER	8
-#else
-#define CONFIG_DRIVER_ETHER		1
-#endif
+#define CONFIG_RMII			1
+#define CONFIG_MII			1
+#define CONFIG_DRIVER_AT91EMAC_PHYADDR	1
 #define CONFIG_NET_RETRY_COUNT			20
-#define CONFIG_AT91C_USE_RMII			1
-#define CONFIG_PHY_ADDRESS			(1 << 5)
 #define CONFIG_KS8721_PHY			1
 
 #define CONFIG_SYS_FLASH_CFI			1
-- 
cgit v1.3.1


From a3c09f66b2b84e98333c317ffb24a95f88ee5a10 Mon Sep 17 00:00:00 2001
From: Thomas Chou <thomas@wytron.com.tw>
Date: Wed, 16 Jun 2010 14:39:30 +0800
Subject: nios2: remove EP1C20, EP1S10, EP1S40 boards

The example configuration files of nios2-generic board can generated
binary to run on the EP1C20, EP1S10, and EP1S40 boards. So the three
boards can be removed.

With nios2-generic approach, the fpga parameter header file can
be generated from hardware designs using tools. Porting u-boot for
nios2 boards is simplified. Vendors can supply their fpga parameter
file or patches to add a new nios2-generic board instance. There is
no need to include other boards support for nios2 in the u-boot
mainline.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Signed-off-by: Scott McNutt <smcnutt@psyent.com>
---
 MAINTAINERS                   |   3 -
 MAKEALL                       |   3 -
 board/altera/ep1c20/Makefile  |  55 -----------
 board/altera/ep1c20/config.mk |  31 ------
 board/altera/ep1c20/ep1c20.c  |  52 ----------
 board/altera/ep1s10/Makefile  |  55 -----------
 board/altera/ep1s10/config.mk |  31 ------
 board/altera/ep1s10/ep1s10.c  |  52 ----------
 board/altera/ep1s40/Makefile  |  55 -----------
 board/altera/ep1s40/config.mk |  31 ------
 board/altera/ep1s40/ep1s40.c  |  47 ----------
 boards.cfg                    |   3 -
 include/configs/EP1C20.h      | 214 ------------------------------------------
 include/configs/EP1S10.h      | 207 ----------------------------------------
 include/configs/EP1S40.h      | 207 ----------------------------------------
 15 files changed, 1046 deletions(-)
 delete mode 100644 board/altera/ep1c20/Makefile
 delete mode 100644 board/altera/ep1c20/config.mk
 delete mode 100644 board/altera/ep1c20/ep1c20.c
 delete mode 100644 board/altera/ep1s10/Makefile
 delete mode 100644 board/altera/ep1s10/config.mk
 delete mode 100644 board/altera/ep1s10/ep1s10.c
 delete mode 100644 board/altera/ep1s40/Makefile
 delete mode 100644 board/altera/ep1s40/config.mk
 delete mode 100644 board/altera/ep1s40/ep1s40.c
 delete mode 100644 include/configs/EP1C20.h
 delete mode 100644 include/configs/EP1S10.h
 delete mode 100644 include/configs/EP1S40.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 94850702ea7..ff3a912ba3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -869,9 +869,6 @@ Scott McNutt <smcnutt@psyent.com>
 
 	PCI5441		Nios-II
 	PK1C20		Nios-II
-	EP1C20		Nios-II
-	EP1S10		Nios-II
-	EP1S40		Nios-II
 	nios2-generic	Nios-II
 
 #########################################################################
diff --git a/MAKEALL b/MAKEALL
index 463739069d3..1c2f54ab2e7 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,9 +824,6 @@ LIST_x86="		\
 #########################################################################
 
 LIST_nios2="		\
-	EP1C20		\
-	EP1S10		\
-	EP1S40		\
 	PCI5441		\
 	PK1C20		\
 	nios2-generic	\
diff --git a/board/altera/ep1c20/Makefile b/board/altera/ep1c20/Makefile
deleted file mode 100644
index acad2aad85d..00000000000
--- a/board/altera/ep1c20/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).a
-
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS	:= $(BOARD).o $(COMOBJS)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/altera/ep1c20/config.mk b/board/altera/ep1c20/config.mk
deleted file mode 100644
index dab27408300..00000000000
--- a/board/altera/ep1c20/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c
deleted file mode 100644
index 82900f71707..00000000000
--- a/board/altera/ep1c20/ep1c20.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f (void)
-{
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("BOARD : Altera EP-1C20\n");
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/altera/ep1s10/Makefile b/board/altera/ep1s10/Makefile
deleted file mode 100644
index acad2aad85d..00000000000
--- a/board/altera/ep1s10/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).a
-
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS	:= $(BOARD).o $(COMOBJS)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/altera/ep1s10/config.mk b/board/altera/ep1s10/config.mk
deleted file mode 100644
index dab27408300..00000000000
--- a/board/altera/ep1s10/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c
deleted file mode 100644
index cf886da64ac..00000000000
--- a/board/altera/ep1s10/ep1s10.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int board_early_init_f (void)
-{
-	return 0;
-}
-
-int checkboard (void)
-{
-	puts ("BOARD : Altera EP-1S10\n");
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/board/altera/ep1s40/Makefile b/board/altera/ep1s40/Makefile
deleted file mode 100644
index acad2aad85d..00000000000
--- a/board/altera/ep1s40/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-ifneq ($(OBJTREE),$(SRCTREE))
-$(shell mkdir -p $(obj)../common)
-endif
-
-LIB	= $(obj)lib$(BOARD).a
-
-COMOBJS := ../common/AMDLV065D.o ../common/epled.o
-
-COBJS	:= $(BOARD).o $(COMOBJS)
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/altera/ep1s40/config.mk b/board/altera/ep1s40/config.mk
deleted file mode 100644
index dab27408300..00000000000
--- a/board/altera/ep1s40/config.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-#
-# (C) Copyright 2005, Psyent Corporation <www.psyent.com>
-# Scott McNutt <smcnutt@psyent.com>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-TEXT_BASE = 0x01fc0000
-
-PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
-PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
-
-ifeq ($(debug),1)
-PLATFORM_CPPFLAGS += -DDEBUG
-endif
diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c
deleted file mode 100644
index 6395de7293b..00000000000
--- a/board/altera/ep1s40/ep1s40.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
-	puts ("BOARD : Altera EP-1S40\n");
-	return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
-	return (0);
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-	int rc = 0;
-#ifdef CONFIG_SMC91111
-	rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
-#endif
-	return rc;
-}
-#endif
diff --git a/boards.cfg b/boards.cfg
index da31c3647e9..e23c60b8b13 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -75,9 +75,6 @@ M5272C3		m68k	mcf52x2		m5272c3		freescale
 EP2500		m68k	mcf52x2		ep2500		Mercury
 purple		mips	mips
 tb0229		mips	mips
-EP1C20		nios2	nios2		ep1c20		altera
-EP1S10		nios2	nios2		ep1s10		altera
-EP1S40		nios2	nios2		ep1s40		altera
 PCI5441		nios2	nios2		pci5441		psyent
 PK1C20		nios2	nios2		pk1c20		psyent
 P3G4		powerpc	74xx_7xx	evb64260
diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h
deleted file mode 100644
index 3920d35264a..00000000000
--- a/include/configs/EP1C20.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1C20		1		/* EP1C20 board		*/
-#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
-
-#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* enable early board-spec. init*/
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB (only 1M mapped)*/
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- *	-Monitor at top.
- *	-The heap is placed below the monitor.
- *	-Global data is placed below the heap.
- *	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 128k		*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned char	/* flash word size	*/
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
- * reset address, no? This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART		1	/* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
-#else
-#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for
- * epcs device access is enabled. The base address is the epcs
- * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
- * The register base is currently at offset 0x600 from the memory base.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_NIOS_EPCSBASE	0x02100200	/* EPCS register base	*/
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num	*/
-#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
-#define CONFIG_SYS_NIOS_TMRCNT \
-		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- leds are, after all,
- * board-specific, no?
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
-#define CONFIG_STATUS_LED			/* Enable status driver */
-
-#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
-#define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.2.21
-#define CONFIG_SERVERIP		192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-
-#undef CONFIG_CMD_BOOTD
-#undef CONFIG_CMD_CONSOLE
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_ITEST
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SETGETDCR
-#undef CONFIG_CMD_SOURCE
-#undef CONFIG_CMD_XIMG
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
-#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
-#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h
deleted file mode 100644
index bfbf8c11197..00000000000
--- a/include/configs/EP1S10.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1S10		1		/* EP1S10 board		*/
-#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
-
-#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB			*/
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- *	-Monitor at top.
- *	-The heap is placed below the monitor.
- *	-Global data is placed below the heap.
- *	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
-
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
- * of flash memory. This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART		1	/* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
-#else
-#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- None for stratix.
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_NIOS_EPCSBASE
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec)*/
-#define CONFIG_SYS_NIOS_TMRCNT \
-		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- since leds are board-specific.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
-#define CONFIG_STATUS_LED			/* Enable status driver */
-
-#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
-#define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.2.21
-#define CONFIG_SERVERIP		192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVES
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
-#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
-#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#endif	/* __CONFIG_H */
diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h
deleted file mode 100644
index 4d905fee385..00000000000
--- a/include/configs/EP1S40.h
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
- * Scott McNutt <smcnutt@psyent.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*------------------------------------------------------------------------
- * BOARD/CPU
- *----------------------------------------------------------------------*/
-#define CONFIG_EP1S40		1		/* EP1S40 board		*/
-#define CONFIG_SYS_CLK_FREQ	50000000	/* 50 MHz core clk	*/
-
-#define CONFIG_SYS_RESET_ADDR		0x00000000	/* Hard-reset address	*/
-#define CONFIG_SYS_EXCEPTION_ADDR	0x01000020	/* Exception entry point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE	0x021208b8	/* System id address	*/
-
-/*------------------------------------------------------------------------
- * CACHE -- the following will support II/s and II/f. The II/s does not
- * have dcache, so the cache instructions will behave as NOPs.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_ICACHE_SIZE		4096		/* 4 KByte total	*/
-#define CONFIG_SYS_ICACHELINE_SIZE	32		/* 32 bytes/line	*/
-#define CONFIG_SYS_DCACHE_SIZE		2048		/* 2 KByte (II/f)	*/
-#define CONFIG_SYS_DCACHELINE_SIZE	4		/* 4 bytes/line (II/f)	*/
-
-/*------------------------------------------------------------------------
- * MEMORY BASE ADDRESSES
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE		0x00000000	/* FLASH base addr	*/
-#define CONFIG_SYS_FLASH_SIZE		0x00800000	/* 8 MByte		*/
-#define CONFIG_SYS_SDRAM_BASE		0x01000000	/* SDRAM base addr	*/
-#define CONFIG_SYS_SDRAM_SIZE		0x01000000	/* 16 MByte		*/
-#define CONFIG_SYS_SRAM_BASE		0x02000000	/* SRAM base addr	*/
-#define CONFIG_SYS_SRAM_SIZE		0x00100000	/* 1 MB			*/
-
-/*------------------------------------------------------------------------
- * MEMORY ORGANIZATION
- *	-Monitor at top.
- *	-The heap is placed below the monitor.
- *	-Global data is placed below the heap.
- *	-The stack is placed below global data (&grows down).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256k		*/
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* Global data size rsvd*/
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 256*1024) /* 256k heap */
-
-#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE		(CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP		CONFIG_SYS_GBL_DATA_OFFSET
-
-/*------------------------------------------------------------------------
- * FLASH (AM29LV065D)
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* Max # sects per bank */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* Max # of flash banks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	8000		/* Erase timeout (msec) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	100		/* Write timeout (msec) */
-
-/*------------------------------------------------------------------------
- * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
- * CONFIG_SYS_FLASH_BASE, since we assume that u-boot is stored at the bottom
- * of flash memory. This will keep the environment in user region
- * of flash. NOTE: the monitor length must be multiple of sector size
- * (which is common practice).
- *----------------------------------------------------------------------*/
-#define CONFIG_ENV_IS_IN_FLASH	1		/* Environment in flash */
-#define CONFIG_ENV_SIZE		(64 * 1024)	/* 64 KByte (1 sector)	*/
-#define CONFIG_ENV_OVERWRITE			/* Serial change Ok	*/
-#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-
-/*------------------------------------------------------------------------
- * CONSOLE
- *----------------------------------------------------------------------*/
-#define CONFIG_ALTERA_UART		1	/* Use altera uart */
-#if defined(CONFIG_ALTERA_JTAG_UART)
-#define CONFIG_SYS_NIOS_CONSOLE	0x021208b0	/* JTAG UART base addr	*/
-#else
-#define CONFIG_SYS_NIOS_CONSOLE	0x02120840	/* UART base addr	*/
-#endif
-
-#define CONFIG_SYS_NIOS_FIXEDBAUD	1		/* Baudrate is fixed	*/
-#define CONFIG_BAUDRATE		115200		/* Initial baudrate	*/
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200}	/* It's fixed ;-)	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1		/* Suppress console info*/
-
-/*------------------------------------------------------------------------
- * EPCS Device -- None for stratix.
- *----------------------------------------------------------------------*/
-#undef CONFIG_SYS_NIOS_EPCSBASE
-
-/*------------------------------------------------------------------------
- * DEBUG
- *----------------------------------------------------------------------*/
-#undef CONFIG_ROM_STUBS				/* Stubs not in ROM	*/
-
-/*------------------------------------------------------------------------
- * TIMEBASE --
- *
- * The high res timer defaults to 1 msec. Since it includes the period
- * registers, the interrupt frequency can be reduced using TMRCNT.
- * If the default period is acceptable, TMRCNT can be left undefined.
- * TMRMS represents the desired mecs per tick (msecs per interrupt).
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_HZ			1000	/* Always 1000 */
-#define CONFIG_SYS_NIOS_TMRBASE	0x02120820	/* Tick timer base addr */
-#define CONFIG_SYS_NIOS_TMRIRQ		3	/* Timer IRQ num */
-#define CONFIG_SYS_NIOS_TMRMS		10	/* Desired period (msec) */
-#define CONFIG_SYS_NIOS_TMRCNT \
-		(CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000))
-
-/*------------------------------------------------------------------------
- * STATUS LED -- Provides a simple blinking led. For Nios2 each board
- * must implement its own led routines -- since leds are board-specific.
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR		0x02120870	/* LED PIO base addr	*/
-#define CONFIG_STATUS_LED			/* Enable status driver */
-
-#define STATUS_LED_BIT		1		/* Bit-0 on PIO		*/
-#define STATUS_LED_STATE	1		/* Blinking		*/
-#define STATUS_LED_PERIOD	(500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec	*/
-
-/*------------------------------------------------------------------------
- * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
- * and really doesn't need any additional clutter. So I choose the lazy
- * way out to avoid changes there -- define the base address to ensure
- * cache bypass so there's no need to monkey with inx/outx macros.
- *----------------------------------------------------------------------*/
-#define CONFIG_SMC91111_BASE	0x82110300	/* Base addr (bypass)	*/
-#define CONFIG_NET_MULTI
-#define CONFIG_SMC91111			/* Using SMC91c111	*/
-#undef	CONFIG_SMC91111_EXT_PHY			/* Internal PHY		*/
-#define CONFIG_SMC_USE_32_BIT			/* 32-bit interface	*/
-
-#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
-#define CONFIG_NETMASK		255.255.255.0
-#define CONFIG_IPADDR		192.168.2.21
-#define CONFIG_SERVERIP		192.168.2.16
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#define CONFIG_CMD_BDI
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-#define CONFIG_CMD_IMI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_LOADS
-#define CONFIG_CMD_LOADB
-#define CONFIG_CMD_MEMORY
-#define CONFIG_CMD_MISC
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_RUN
-#define CONFIG_CMD_SAVES
-
-
-/*------------------------------------------------------------------------
- * MISC
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP				/* Provide extended help*/
-#define CONFIG_SYS_PROMPT		"==> "		/* Command prompt	*/
-#define CONFIG_SYS_CBSIZE		256		/* Console I/O buf size */
-#define CONFIG_SYS_MAXARGS		16		/* Max command args	*/
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot arg buf size	*/
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */
-#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE	/* Default load address */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE	/* Start addr for test	*/
-#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_INIT_SP - 0x00020000
-
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-
-#endif	/* __CONFIG_H */
-- 
cgit v1.3.1


From c9f7351b5bb70d292f6b0baaf0e21366e0b0b163 Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Mon, 5 Jul 2010 13:27:07 -0400
Subject: NAND: environment offset in OOB (CONFIG_ENV_OFFSET_OOB)

This is a re-submission of the patch by Harald Welte
<laforge@openmoko.org> with minor modifications for rebase and changes
as suggested by Scott Wood <scottwood@freescale.com> [1] [2].

This patch enables the environment partition to have a run-time dynamic
location (offset) in the NAND flash.  The reason for this is simply that
all NAND flashes have factory-default bad blocks, and a fixed compile
time offset would mean that sometimes the environment partition would
live inside factory bad blocks. Since the number of factory default
blocks can be quite high (easily 1.3MBytes in current standard
components), it is not economic to keep that many spare blocks inside
the environment partition.

With this patch and CONFIG_ENV_OFFSET_OOB enabled, the location of the
environment partition is stored in the out-of-band (OOB) data of the
first block in flash. Since the first block is where most systems boot
from, the vendors guarantee that the first block is not a factory
default block.

This patch introduces the 'nand env.oob' command, which can be called
from the u-boot command line. 'nand env.oob get' reads the address of
the environment partition from the OOB data, 'nand env.oob set
{offset,partition-name}' allows the setting of the marker by specifying
a numeric offset or a partition name.

[1] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/43916
[2] http://article.gmane.org/gmane.comp.boot-loaders.u-boot/79195

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Acked-by: Harald Welte <laforge@gnumonks.org>
---
 common/cmd_nand.c     | 107 +++++++++++++++++++++++++++++++++++++++++++++++++-
 common/env_nand.c     |  46 ++++++++++++++++++++++
 include/environment.h |  21 +++++++---
 include/nand.h        |   9 +++++
 4 files changed, 176 insertions(+), 7 deletions(-)

(limited to 'include')

diff --git a/common/cmd_nand.c b/common/cmd_nand.c
index ea80555ef89..a4c67c170f8 100644
--- a/common/cmd_nand.c
+++ b/common/cmd_nand.c
@@ -4,6 +4,10 @@
  * (c) 1999 Machine Vision Holdings, Inc.
  * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
  *
+ * Ported 'dynenv' to 'nand env.oob' command
+ * (C) 2010 Nanometrics, Inc.
+ * 'dynenv' -- Dynamic environment offset in NAND OOB
+ * (C) Copyright 2006-2007 OpenMoko, Inc.
  * Added 16-bit nand support
  * (C) 2004 Texas Instruments
  */
@@ -193,6 +197,90 @@ static void do_nand_status(nand_info_t *nand)
 }
 #endif
 
+#ifdef CONFIG_ENV_OFFSET_OOB
+unsigned long nand_env_oob_offset;
+
+int do_nand_env_oob(cmd_tbl_t *cmdtp, nand_info_t *nand,
+				 int argc, char * const argv[])
+{
+	int ret;
+	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+
+	char *cmd = argv[1];
+
+	if (!strcmp(cmd, "get")) {
+		ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+		if (!ret)
+			printf("0x%08lx\n", nand_env_oob_offset);
+		else
+			return 1;
+	} else if (!strcmp(cmd, "set")) {
+		ulong addr;
+		size_t dummy_size;
+		struct mtd_oob_ops ops;
+
+		if (argc < 3)
+			goto usage;
+
+		if (arg_off_size(argc-2, argv + 2, nand, &addr,
+						  &dummy_size) < 0) {
+			printf("Offset or partition name expected\n");
+			return 1;
+		}
+
+		if (nand->oobavail < ENV_OFFSET_SIZE) {
+			printf("Insufficient available OOB bytes: %d OOB bytes"
+			    " available but %d required for env.oob support\n",
+								nand->oobavail,
+							      ENV_OFFSET_SIZE);
+			return 1;
+		}
+
+		if ((addr & (nand->erasesize - 1)) != 0) {
+			printf("Environment offset must be block-aligned\n");
+			return 1;
+		}
+
+		ops.datbuf = NULL;
+		ops.mode = MTD_OOB_AUTO;
+		ops.ooboffs = 0;
+		ops.ooblen = ENV_OFFSET_SIZE;
+		ops.oobbuf = (void *) oob_buf;
+
+		oob_buf[0] = ENV_OOB_MARKER;
+		oob_buf[1] = addr / nand->erasesize;
+
+		ret = nand->write_oob(nand, ENV_OFFSET_SIZE, &ops);
+		if (!ret) {
+			ret = get_nand_env_oob(nand, &nand_env_oob_offset);
+			if (ret) {
+				printf("Error reading env offset in OOB\n");
+				return ret;
+			}
+
+			if (addr != nand_env_oob_offset) {
+				printf("Verification of env offset in OOB "
+				       "failed: 0x%08lx expected but got "
+				       "0x%08lx\n", addr, nand_env_oob_offset);
+				return 1;
+			}
+		} else {
+			printf("Error writing OOB block 0\n");
+			return ret;
+		}
+	} else {
+		goto usage;
+	}
+
+	return ret;
+
+usage:
+	cmd_usage(cmdtp);
+	return 1;
+}
+
+#endif
+
 static void nand_print_info(int idx)
 {
 	nand_info_t *nand = &nand_info[idx];
@@ -272,9 +360,19 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 	    strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 &&
 	    strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 &&
 	    strcmp(cmd, "biterr") != 0 &&
-	    strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 )
+	    strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0
+#ifdef CONFIG_ENV_OFFSET_OOB
+	    && strcmp(cmd, "env.oob") != 0
+#endif
+	    )
 		goto usage;
 
+#ifdef CONFIG_ENV_OFFSET_OOB
+	/* this command operates only on the first nand device */
+	if (strcmp(cmd, "env.oob") == 0)
+	      return do_nand_env_oob(cmdtp, &nand_info[0], argc - 1, argv + 1);
+#endif
+
 	/* the following commands operate on the current device */
 	if (nand_curr_device < 0 || nand_curr_device >= CONFIG_SYS_MAX_NAND_DEVICE ||
 	    !nand_info[nand_curr_device].name) {
@@ -502,6 +600,13 @@ U_BOOT_CMD(nand, CONFIG_SYS_MAXARGS, 1, do_nand,
 	"    bring nand to lock state or display locked pages\n"
 	"nand unlock [offset] [size] - unlock section"
 #endif
+#ifdef CONFIG_ENV_OFFSET_OOB
+	"\n"
+	"nand env.oob - environment offset in OOB of block 0 of"
+	"    first device.\n"
+	"nand env.oob set off|partition - set enviromnent offset\n"
+	"nand env.oob get - get environment offset"
+#endif
 );
 
 static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand,
diff --git a/common/env_nand.c b/common/env_nand.c
index 50bc111a3bf..47d9848acb2 100644
--- a/common/env_nand.c
+++ b/common/env_nand.c
@@ -38,6 +38,7 @@
 #include <linux/stddef.h>
 #include <malloc.h>
 #include <nand.h>
+#include <asm/errno.h>
 
 #if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND)
 #define CMD_SAVEENV
@@ -284,6 +285,40 @@ int readenv (size_t offset, u_char * buf)
 	return 0;
 }
 
+#ifdef CONFIG_ENV_OFFSET_OOB
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result)
+{
+	struct mtd_oob_ops ops;
+	uint32_t oob_buf[ENV_OFFSET_SIZE/sizeof(uint32_t)];
+	int ret;
+
+	ops.datbuf = NULL;
+	ops.mode = MTD_OOB_AUTO;
+	ops.ooboffs = 0;
+	ops.ooblen = ENV_OFFSET_SIZE;
+	ops.oobbuf = (void *) oob_buf;
+
+	ret = nand->read_oob(nand, ENV_OFFSET_SIZE, &ops);
+
+	if (!ret) {
+		if (oob_buf[0] == ENV_OOB_MARKER) {
+			*result = oob_buf[1] * nand->erasesize;
+		} else if (oob_buf[0] == ENV_OOB_MARKER_OLD) {
+			*result = oob_buf[1];
+		} else {
+			printf("No dynamic environment marker in OOB block 0"
+									"\n");
+			ret = -ENOENT;
+			goto fail;
+		}
+	} else {
+		printf("error reading OOB block 0\n");
+	}
+fail:
+	return ret;
+}
+#endif
+
 #ifdef CONFIG_ENV_OFFSET_REDUND
 void env_relocate_spec (void)
 {
@@ -353,6 +388,17 @@ void env_relocate_spec (void)
 #if !defined(ENV_IS_EMBEDDED)
 	int ret;
 
+#if defined(CONFIG_ENV_OFFSET_OOB)
+	ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset);
+	/* If unable to read environment offset from NAND OOB then fall through
+	 * to the normal environment reading code below
+	 */
+	if (!ret)
+		printf("Found Environment offset in OOB..\n");
+	else
+		return use_default();
+#endif
+
 	ret = readenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr);
 	if (ret)
 		return use_default();
diff --git a/include/environment.h b/include/environment.h
index 203f731967e..fbccf6ab0c4 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -74,15 +74,24 @@
 #endif	/* CONFIG_ENV_IS_IN_FLASH */
 
 #if defined(CONFIG_ENV_IS_IN_NAND)
-# ifndef CONFIG_ENV_OFFSET
-#  error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
-# endif
+# if defined(CONFIG_ENV_OFFSET_OOB)
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   error "CONFIG_ENV_OFFSET_REDUND is not supported when CONFIG_ENV_OFFSET_OOB"
+#   error "is set"
+#  endif
+extern unsigned long nand_env_oob_offset;
+#  define CONFIG_ENV_OFFSET nand_env_oob_offset
+# else
+#  ifndef CONFIG_ENV_OFFSET
+#   error "Need to define CONFIG_ENV_OFFSET when using CONFIG_ENV_IS_IN_NAND"
+#  endif
+#  ifdef CONFIG_ENV_OFFSET_REDUND
+#   define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#  endif
+# endif /* CONFIG_ENV_OFFSET_OOB */
 # ifndef CONFIG_ENV_SIZE
 #  error "Need to define CONFIG_ENV_SIZE when using CONFIG_ENV_IS_IN_NAND"
 # endif
-# ifdef CONFIG_ENV_OFFSET_REDUND
-#  define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-# endif
 #endif /* CONFIG_ENV_IS_IN_NAND */
 
 #if defined(CONFIG_ENV_IS_IN_MG_DISK)
diff --git a/include/nand.h b/include/nand.h
index 2a81597a65d..8bdf4191a6d 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -130,3 +130,12 @@ void board_nand_select_device(struct nand_chip *nand, int chip);
 __attribute__((noreturn)) void nand_boot(void);
 
 #endif
+
+#ifdef CONFIG_ENV_OFFSET_OOB
+#define ENV_OOB_MARKER 0x30425645 /*"EVB0" in little-endian -- offset is stored
+				    as block number*/
+#define ENV_OOB_MARKER_OLD 0x30564e45 /*"ENV0" in little-endian -- offset is
+					stored as byte number */
+#define ENV_OFFSET_SIZE 8
+int get_nand_env_oob(nand_info_t *nand, unsigned long *result);
+#endif
-- 
cgit v1.3.1


From d44265ad783f1896685db04faec148e32e918cda Mon Sep 17 00:00:00 2001
From: Albert Aribaud <albert.aribaud@free.fr>
Date: Mon, 12 Jul 2010 22:24:28 +0200
Subject: mvgbe: support SoCs other than kirkwood

Rename all references to kirkwood in mvgbe symbols
throughout the whole codebase.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 arch/arm/cpu/arm926ejs/kirkwood/cpu.c         |   4 +-
 arch/arm/include/asm/arch-kirkwood/kirkwood.h |   3 +
 drivers/net/Makefile                          |   2 +-
 drivers/net/mvgbe.c                           | 346 ++++++++++---------
 drivers/net/mvgbe.h                           | 474 +++++++++++++-------------
 include/configs/guruplug.h                    |   4 +-
 include/configs/km_arm.h                      |   4 +-
 include/configs/mv88f6281gtw_ge.h             |   4 +-
 include/configs/openrd_base.h                 |   4 +-
 include/configs/rd6281a.h                     |   4 +-
 include/configs/sheevaplug.h                  |   4 +-
 include/netdev.h                              |   2 +-
 12 files changed, 439 insertions(+), 416 deletions(-)

(limited to 'include')

diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index 6fc39025809..c63e8641f21 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -378,10 +378,10 @@ int arch_misc_init(void)
 }
 #endif /* CONFIG_ARCH_MISC_INIT */
 
-#ifdef CONFIG_KIRKWOOD_EGIGA
+#ifdef CONFIG_MVGBE
 int cpu_eth_init(bd_t *bis)
 {
-	kirkwood_egiga_initialize(bis);
+	mvgbe_initialize(bis);
 	return 0;
 }
 #endif
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 2470efbd8c9..5c2586be43f 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -60,6 +60,9 @@
 #define KW_EGIGA0_BASE			(KW_REGISTER(0x72000))
 #define KW_EGIGA1_BASE			(KW_REGISTER(0x76000))
 
+#define MVGBE0_BASE			KW_EGIGA0_BASE
+#define MVGBE1_BASE			KW_EGIGA1_BASE
+
 #if defined (CONFIG_KW88F6281)
 #include <asm/arch/kw88f6281.h>
 #elif defined (CONFIG_KW88F6192)
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0894822c4c5..218eeff86e6 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -53,7 +53,7 @@ COBJS-$(CONFIG_MACB) += macb.o
 COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
 COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
 COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o
-COBJS-$(CONFIG_KIRKWOOD_EGIGA) += mvgbe.o
+COBJS-$(CONFIG_MVGBE) += mvgbe.o
 COBJS-$(CONFIG_NATSEMI) += natsemi.o
 COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o
 COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 1efca1e9e9b..e44352c6765 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -35,13 +35,17 @@
 #include <asm/errno.h>
 #include <asm/types.h>
 #include <asm/byteorder.h>
+
+#if defined(CONFIG_KIRKWOOD)
 #include <asm/arch/kirkwood.h>
+#endif
+
 #include "mvgbe.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define KIRKWOOD_PHY_ADR_REQUEST 0xee
-#define KWGBE_SMI_REG (((struct kwgbe_registers *)KW_EGIGA0_BASE)->smi)
+#define MV_PHY_ADR_REQUEST 0xee
+#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
 
 /*
  * smi_reg_read - miiphy_read callback function.
@@ -51,16 +55,16 @@ DECLARE_GLOBAL_DATA_PTR;
 static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
 	u32 smi_reg;
 	u32 timeout;
 
 	/* Phyadr read request */
-	if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
-			reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
+	if (phy_adr == MV_PHY_ADR_REQUEST &&
+			reg_ofs == MV_PHY_ADR_REQUEST) {
 		/* */
-		*data = (u16) (KWGBEREG_RD(regs->phyadr) & PHYADR_MASK);
+		*data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
 		return 0;
 	}
 	/* check parameters */
@@ -75,42 +79,43 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
 		return -EFAULT;
 	}
 
-	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	timeout = MVGBE_PHY_SMI_TIMEOUT;
 	/* wait till the SMI is not busy */
 	do {
 		/* read smi register */
-		smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+		smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 		if (timeout-- == 0) {
 			printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
 			return -EFAULT;
 		}
-	} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+	} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
 
 	/* fill the phy address and regiser offset and read opcode */
-	smi_reg = (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-		| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS)
-		| KWGBE_PHY_SMI_OPCODE_READ;
+	smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
+		| MVGBE_PHY_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+	MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
 
 	/*wait till read value is ready */
-	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	timeout = MVGBE_PHY_SMI_TIMEOUT;
 
 	do {
 		/* read smi register */
-		smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+		smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 		if (timeout-- == 0) {
 			printf("Err..(%s) SMI read ready timeout\n",
 				__FUNCTION__);
 			return -EFAULT;
 		}
-	} while (!(smi_reg & KWGBE_PHY_SMI_READ_VALID_MASK));
+	} while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
 
 	/* Wait for the data to update in the SMI register */
-	for (timeout = 0; timeout < KWGBE_PHY_SMI_TIMEOUT; timeout++) ;
+	for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
+		;
 
-	*data = (u16) (KWGBEREG_RD(KWGBE_SMI_REG) & KWGBE_PHY_SMI_DATA_MASK);
+	*data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
 
 	debug("%s:(adr %d, off %d) value= %04x\n", __FUNCTION__, phy_adr,
 		reg_ofs, *data);
@@ -127,15 +132,15 @@ static int smi_reg_read(char *devname, u8 phy_adr, u8 reg_ofs, u16 * data)
 static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 {
 	struct eth_device *dev = eth_get_dev_by_name(devname);
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
 	u32 smi_reg;
 	u32 timeout;
 
 	/* Phyadr write request*/
-	if (phy_adr == KIRKWOOD_PHY_ADR_REQUEST &&
-			reg_ofs == KIRKWOOD_PHY_ADR_REQUEST) {
-		KWGBEREG_WR(regs->phyadr, data);
+	if (phy_adr == MV_PHY_ADR_REQUEST &&
+			reg_ofs == MV_PHY_ADR_REQUEST) {
+		MVGBE_REG_WR(regs->phyadr, data);
 		return 0;
 	}
 
@@ -150,24 +155,24 @@ static int smi_reg_write(char *devname, u8 phy_adr, u8 reg_ofs, u16 data)
 	}
 
 	/* wait till the SMI is not busy */
-	timeout = KWGBE_PHY_SMI_TIMEOUT;
+	timeout = MVGBE_PHY_SMI_TIMEOUT;
 	do {
 		/* read smi register */
-		smi_reg = KWGBEREG_RD(KWGBE_SMI_REG);
+		smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
 		if (timeout-- == 0) {
 			printf("Err..(%s) SMI busy timeout\n", __FUNCTION__);
 			return -ETIME;
 		}
-	} while (smi_reg & KWGBE_PHY_SMI_BUSY_MASK);
+	} while (smi_reg & MVGBE_PHY_SMI_BUSY_MASK);
 
 	/* fill the phy addr and reg offset and write opcode and data */
-	smi_reg = (data << KWGBE_PHY_SMI_DATA_OFFS);
-	smi_reg |= (phy_adr << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-		| (reg_ofs << KWGBE_SMI_REG_ADDR_OFFS);
-	smi_reg &= ~KWGBE_PHY_SMI_OPCODE_READ;
+	smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
+	smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+		| (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
+	smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
 
 	/* write the smi register */
-	KWGBEREG_WR(KWGBE_SMI_REG, smi_reg);
+	MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
 
 	return 0;
 }
@@ -204,46 +209,46 @@ static void stop_queue(u32 * qreg)
  * @regs	Register struct pointer.
  * @param	Address decode parameter struct.
  */
-static void set_access_control(struct kwgbe_registers *regs,
-				struct kwgbe_winparam *param)
+static void set_access_control(struct mvgbe_registers *regs,
+				struct mvgbe_winparam *param)
 {
 	u32 access_prot_reg;
 
 	/* Set access control register */
-	access_prot_reg = KWGBEREG_RD(regs->epap);
+	access_prot_reg = MVGBE_REG_RD(regs->epap);
 	/* clear window permission */
 	access_prot_reg &= (~(3 << (param->win * 2)));
 	access_prot_reg |= (param->access_ctrl << (param->win * 2));
-	KWGBEREG_WR(regs->epap, access_prot_reg);
+	MVGBE_REG_WR(regs->epap, access_prot_reg);
 
 	/* Set window Size reg (SR) */
-	KWGBEREG_WR(regs->barsz[param->win].size,
+	MVGBE_REG_WR(regs->barsz[param->win].size,
 			(((param->size / 0x10000) - 1) << 16));
 
 	/* Set window Base address reg (BA) */
-	KWGBEREG_WR(regs->barsz[param->win].bar,
+	MVGBE_REG_WR(regs->barsz[param->win].bar,
 			(param->target | param->attrib | param->base_addr));
 	/* High address remap reg (HARR) */
 	if (param->win < 4)
-		KWGBEREG_WR(regs->ha_remap[param->win], param->high_addr);
+		MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
 
 	/* Base address enable reg (BARER) */
 	if (param->enable == 1)
-		KWGBEREG_BITS_RESET(regs->bare, (1 << param->win));
+		MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
 	else
-		KWGBEREG_BITS_SET(regs->bare, (1 << param->win));
+		MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
 }
 
-static void set_dram_access(struct kwgbe_registers *regs)
+static void set_dram_access(struct mvgbe_registers *regs)
 {
-	struct kwgbe_winparam win_param;
+	struct mvgbe_winparam win_param;
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 		/* Set access parameters for DRAM bank i */
 		win_param.win = i;	/* Use Ethernet window i */
 		/* Window target - DDR */
-		win_param.target = KWGBE_TARGET_DRAM;
+		win_param.target = MVGBE_TARGET_DRAM;
 		/* Enable full access */
 		win_param.access_ctrl = EWIN_ACCESS_FULL;
 		win_param.high_addr = 0;
@@ -286,19 +291,19 @@ static void set_dram_access(struct kwgbe_registers *regs)
  * Go through all the DA filter tables (Unicast, Special Multicast & Other
  * Multicast) and set each entry to 0.
  */
-static void port_init_mac_tables(struct kwgbe_registers *regs)
+static void port_init_mac_tables(struct mvgbe_registers *regs)
 {
 	int table_index;
 
 	/* Clear DA filter unicast table (Ex_dFUT) */
 	for (table_index = 0; table_index < 4; ++table_index)
-		KWGBEREG_WR(regs->dfut[table_index], 0);
+		MVGBE_REG_WR(regs->dfut[table_index], 0);
 
 	for (table_index = 0; table_index < 64; ++table_index) {
 		/* Clear DA filter special multicast table (Ex_dFSMT) */
-		KWGBEREG_WR(regs->dfsmt[table_index], 0);
+		MVGBE_REG_WR(regs->dfsmt[table_index], 0);
 		/* Clear DA filter other multicast table (Ex_dFOMT) */
-		KWGBEREG_WR(regs->dfomt[table_index], 0);
+		MVGBE_REG_WR(regs->dfomt[table_index], 0);
 	}
 }
 
@@ -316,7 +321,7 @@ static void port_init_mac_tables(struct kwgbe_registers *regs)
  *
  * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
  */
-static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
+static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
 			int option)
 {
 	u32 unicast_reg;
@@ -336,16 +341,16 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
 		 * Clear accepts frame bit at specified unicast
 		 * DA table entry
 		 */
-		unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+		unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 		unicast_reg &= (0xFF << (8 * reg_offset));
-		KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+		MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 		break;
 	case ACCEPT_MAC_ADDR:
 		/* Set accepts frame bit at unicast DA filter table entry */
-		unicast_reg = KWGBEREG_RD(regs->dfut[tbl_offset]);
+		unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
 		unicast_reg &= (0xFF << (8 * reg_offset));
 		unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
-		KWGBEREG_WR(regs->dfut[tbl_offset], unicast_reg);
+		MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
 		break;
 	default:
 		return 0;
@@ -356,7 +361,7 @@ static int port_uc_addr(struct kwgbe_registers *regs, u8 uc_nibble,
 /*
  * port_uc_addr_set - This function Set the port Unicast address.
  */
-static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
+static void port_uc_addr_set(struct mvgbe_registers *regs, u8 * p_addr)
 {
 	u32 mac_h;
 	u32 mac_l;
@@ -365,94 +370,95 @@ static void port_uc_addr_set(struct kwgbe_registers *regs, u8 * p_addr)
 	mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
 		(p_addr[3] << 0);
 
-	KWGBEREG_WR(regs->macal, mac_l);
-	KWGBEREG_WR(regs->macah, mac_h);
+	MVGBE_REG_WR(regs->macal, mac_l);
+	MVGBE_REG_WR(regs->macah, mac_h);
 
 	/* Accept frames of this address */
 	port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
 }
 
 /*
- * kwgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
+ * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  */
-static void kwgbe_init_rx_desc_ring(struct kwgbe_device *dkwgbe)
+static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
 {
-	struct kwgbe_rxdesc *p_rx_desc;
+	struct mvgbe_rxdesc *p_rx_desc;
 	int i;
 
 	/* initialize the Rx descriptors ring */
-	p_rx_desc = dkwgbe->p_rxdesc;
+	p_rx_desc = dmvgbe->p_rxdesc;
 	for (i = 0; i < RINGSZ; i++) {
 		p_rx_desc->cmd_sts =
-			KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+			MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 		p_rx_desc->buf_size = PKTSIZE_ALIGN;
 		p_rx_desc->byte_cnt = 0;
-		p_rx_desc->buf_ptr = dkwgbe->p_rxbuf + i * PKTSIZE_ALIGN;
+		p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
 		if (i == (RINGSZ - 1))
-			p_rx_desc->nxtdesc_p = dkwgbe->p_rxdesc;
+			p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
 		else {
-			p_rx_desc->nxtdesc_p = (struct kwgbe_rxdesc *)
-				((u32) p_rx_desc + KW_RXQ_DESC_ALIGNED_SIZE);
+			p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
+				((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
 			p_rx_desc = p_rx_desc->nxtdesc_p;
 		}
 	}
-	dkwgbe->p_rxdesc_curr = dkwgbe->p_rxdesc;
+	dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
 }
 
-static int kwgbe_init(struct eth_device *dev)
+static int mvgbe_init(struct eth_device *dev)
 {
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
 	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
 	int i;
 #endif
 	/* setup RX rings */
-	kwgbe_init_rx_desc_ring(dkwgbe);
+	mvgbe_init_rx_desc_ring(dmvgbe);
 
 	/* Clear the ethernet port interrupts */
-	KWGBEREG_WR(regs->ic, 0);
-	KWGBEREG_WR(regs->ice, 0);
+	MVGBE_REG_WR(regs->ic, 0);
+	MVGBE_REG_WR(regs->ice, 0);
 	/* Unmask RX buffer and TX end interrupt */
-	KWGBEREG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
+	MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
 	/* Unmask phy and link status changes interrupts */
-	KWGBEREG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
+	MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
 
 	set_dram_access(regs);
 	port_init_mac_tables(regs);
-	port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+	port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 
 	/* Assign port configuration and command. */
-	KWGBEREG_WR(regs->pxc, PRT_CFG_VAL);
-	KWGBEREG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
-	KWGBEREG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
+	MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
+	MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
+	MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
 
 	/* Assign port SDMA configuration */
-	KWGBEREG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
-	KWGBEREG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
-	KWGBEREG_WR(regs->tqx[0].tqxtbc, (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
+	MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
+	MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
+	MVGBE_REG_WR(regs->tqx[0].tqxtbc,
+		(QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
 	/* Turn off the port/RXUQ bandwidth limitation */
-	KWGBEREG_WR(regs->pmtu, 0);
+	MVGBE_REG_WR(regs->pmtu, 0);
 
 	/* Set maximum receive buffer to 9700 bytes */
-	KWGBEREG_WR(regs->psc0,	KWGBE_MAX_RX_PACKET_9700BYTE
-			| (KWGBEREG_RD(regs->psc0) & MRU_MASK));
+	MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
+			| (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
 
 	/* Enable port initially */
-	KWGBEREG_BITS_SET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+	MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 
 	/*
 	 * Set ethernet MTU for leaky bucket mechanism to 0 - this will
 	 * disable the leaky bucket mechanism .
 	 */
-	KWGBEREG_WR(regs->pmtu, 0);
+	MVGBE_REG_WR(regs->pmtu, 0);
 
 	/* Assignment of Rx CRDB of given RXUQ */
-	KWGBEREG_WR(regs->rxcdp[RXUQ], (u32) dkwgbe->p_rxdesc_curr);
+	MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
 	/* ensure previous write is done before enabling Rx DMA */
 	isb();
 	/* Enable port Rx. */
-	KWGBEREG_WR(regs->rqc, (1 << RXUQ));
+	MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
 
 #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
 	 && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
@@ -460,8 +466,8 @@ static int kwgbe_init(struct eth_device *dev)
 	for (i = 0; i < 5; i++) {
 		u16 phyadr;
 
-		miiphy_read(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
-				KIRKWOOD_PHY_ADR_REQUEST, &phyadr);
+		miiphy_read(dev->name, MV_PHY_ADR_REQUEST,
+				MV_PHY_ADR_REQUEST, &phyadr);
 		/* Return if we get link up */
 		if (miiphy_link(dev->name, phyadr))
 			return 0;
@@ -474,50 +480,50 @@ static int kwgbe_init(struct eth_device *dev)
 	return 0;
 }
 
-static int kwgbe_halt(struct eth_device *dev)
+static int mvgbe_halt(struct eth_device *dev)
 {
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
 
 	/* Disable all gigE address decoder */
-	KWGBEREG_WR(regs->bare, 0x3f);
+	MVGBE_REG_WR(regs->bare, 0x3f);
 
 	stop_queue(&regs->tqc);
 	stop_queue(&regs->rqc);
 
 	/* Disable port */
-	KWGBEREG_BITS_RESET(regs->psc0, KWGBE_SERIAL_PORT_EN);
+	MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
 	/* Set port is not reset */
-	KWGBEREG_BITS_RESET(regs->psc1, 1 << 4);
+	MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
 #ifdef CONFIG_SYS_MII_MODE
 	/* Set MMI interface up */
-	KWGBEREG_BITS_RESET(regs->psc1, 1 << 3);
+	MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
 #endif
 	/* Disable & mask ethernet port interrupts */
-	KWGBEREG_WR(regs->ic, 0);
-	KWGBEREG_WR(regs->ice, 0);
-	KWGBEREG_WR(regs->pim, 0);
-	KWGBEREG_WR(regs->peim, 0);
+	MVGBE_REG_WR(regs->ic, 0);
+	MVGBE_REG_WR(regs->ice, 0);
+	MVGBE_REG_WR(regs->pim, 0);
+	MVGBE_REG_WR(regs->peim, 0);
 
 	return 0;
 }
 
-static int kwgbe_write_hwaddr(struct eth_device *dev)
+static int mvgbe_write_hwaddr(struct eth_device *dev)
 {
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
 
 	/* Programs net device MAC address after initialization */
-	port_uc_addr_set(regs, dkwgbe->dev.enetaddr);
+	port_uc_addr_set(regs, dmvgbe->dev.enetaddr);
 	return 0;
 }
 
-static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
+static int mvgbe_send(struct eth_device *dev, void *dataptr,
 		      int datasize)
 {
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_registers *regs = dkwgbe->regs;
-	struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_registers *regs = dmvgbe->regs;
+	struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
 	void *p = (void *)dataptr;
 	u32 cmd_sts;
 
@@ -529,35 +535,35 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
 			return -1;
 		}
 
-		memcpy(dkwgbe->p_aligned_txbuf, p, datasize);
-		p = dkwgbe->p_aligned_txbuf;
+		memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
+		p = dmvgbe->p_aligned_txbuf;
 	}
 
-	p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC;
-	p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC;
-	p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA;
-	p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT;
+	p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
+	p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
+	p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
+	p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
 	p_txdesc->buf_ptr = (u8 *) p;
 	p_txdesc->byte_cnt = datasize;
 
 	/* Set this tc desc as zeroth TXUQ */
-	KWGBEREG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
+	MVGBE_REG_WR(regs->tcqdp[TXUQ], (u32) p_txdesc);
 
 	/* ensure tx desc writes above are performed before we start Tx DMA */
 	isb();
 
 	/* Apply send command using zeroth TXUQ */
-	KWGBEREG_WR(regs->tqc, (1 << TXUQ));
+	MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
 
 	/*
 	 * wait for packet xmit completion
 	 */
 	cmd_sts = readl(&p_txdesc->cmd_sts);
-	while (cmd_sts & KWGBE_BUFFER_OWNED_BY_DMA) {
+	while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
 		/* return fail if error is detected */
-		if ((cmd_sts & (KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME)) ==
-				(KWGBE_ERROR_SUMMARY | KWGBE_TX_LAST_FRAME) &&
-				cmd_sts & (KWGBE_UR_ERROR | KWGBE_RL_ERROR)) {
+		if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
+				(MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
+				cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
 			printf("Err..(%s) in xmit packet\n", __FUNCTION__);
 			return -1;
 		}
@@ -566,22 +572,22 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr,
 	return 0;
 }
 
-static int kwgbe_recv(struct eth_device *dev)
+static int mvgbe_recv(struct eth_device *dev)
 {
-	struct kwgbe_device *dkwgbe = to_dkwgbe(dev);
-	struct kwgbe_rxdesc *p_rxdesc_curr = dkwgbe->p_rxdesc_curr;
+	struct mvgbe_device *dmvgbe = to_mvgbe(dev);
+	struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
 	u32 cmd_sts;
 	u32 timeout = 0;
 
 	/* wait untill rx packet available or timeout */
 	do {
-		if (timeout < KWGBE_PHY_SMI_TIMEOUT)
+		if (timeout < MVGBE_PHY_SMI_TIMEOUT)
 			timeout++;
 		else {
 			debug("%s time out...\n", __FUNCTION__);
 			return -1;
 		}
-	} while (readl(&p_rxdesc_curr->cmd_sts) & KWGBE_BUFFER_OWNED_BY_DMA);
+	} while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
 
 	if (p_rxdesc_curr->byte_cnt != 0) {
 		debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
@@ -598,13 +604,13 @@ static int kwgbe_recv(struct eth_device *dev)
 	cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
 
 	if ((cmd_sts &
-		(KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC))
-		!= (KWGBE_RX_FIRST_DESC | KWGBE_RX_LAST_DESC)) {
+		(MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
+		!= (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
 
 		printf("Err..(%s) Dropping packet spread on"
 			" multiple descriptors\n", __FUNCTION__);
 
-	} else if (cmd_sts & KWGBE_ERROR_SUMMARY) {
+	} else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
 
 		printf("Err..(%s) Dropping packet with errors\n",
 			__FUNCTION__);
@@ -622,62 +628,72 @@ static int kwgbe_recv(struct eth_device *dev)
 	 * free these descriptors and point next in the ring
 	 */
 	p_rxdesc_curr->cmd_sts =
-		KWGBE_BUFFER_OWNED_BY_DMA | KWGBE_RX_EN_INTERRUPT;
+		MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
 	p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
 	p_rxdesc_curr->byte_cnt = 0;
 
-	writel((unsigned)p_rxdesc_curr->nxtdesc_p, (u32) &dkwgbe->p_rxdesc_curr);
+	writel((unsigned)p_rxdesc_curr->nxtdesc_p,
+		(u32) &dmvgbe->p_rxdesc_curr);
 
 	return 0;
 }
 
-int kirkwood_egiga_initialize(bd_t * bis)
+int mvgbe_initialize(bd_t *bis)
 {
-	struct kwgbe_device *dkwgbe;
+	struct mvgbe_device *dmvgbe;
 	struct eth_device *dev;
 	int devnum;
 	char *s;
-	u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS;
+	u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
 
-	for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) {
+	for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
 		/*skip if port is configured not to use */
 		if (used_ports[devnum] == 0)
 			continue;
 
-		if (!(dkwgbe = malloc(sizeof(struct kwgbe_device))))
+		dmvgbe = malloc(sizeof(struct mvgbe_device));
+
+		if (!dmvgbe)
 			goto error1;
 
-		memset(dkwgbe, 0, sizeof(struct kwgbe_device));
+		memset(dmvgbe, 0, sizeof(struct mvgbe_device));
 
-		if (!(dkwgbe->p_rxdesc =
-		      (struct kwgbe_rxdesc *)memalign(PKTALIGN,
-						KW_RXQ_DESC_ALIGNED_SIZE
-						* RINGSZ + 1)))
+		dmvgbe->p_rxdesc =
+			(struct mvgbe_rxdesc *)memalign(PKTALIGN,
+			MV_RXQ_DESC_ALIGNED_SIZE*RINGSZ + 1);
+
+		if (!dmvgbe->p_rxdesc)
 			goto error2;
 
-		if (!(dkwgbe->p_rxbuf = (u8 *) memalign(PKTALIGN, RINGSZ
-							* PKTSIZE_ALIGN + 1)))
+		dmvgbe->p_rxbuf = (u8 *) memalign(PKTALIGN,
+			RINGSZ*PKTSIZE_ALIGN + 1);
+
+		if (!dmvgbe->p_rxbuf)
 			goto error3;
 
-		if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN)))
+		dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
+
+		if (!dmvgbe->p_aligned_txbuf)
 			goto error4;
 
-		if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *)
-		      memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) {
-			free(dkwgbe->p_aligned_txbuf);
-		      error4:
-			free(dkwgbe->p_rxbuf);
-		      error3:
-			free(dkwgbe->p_rxdesc);
-		      error2:
-			free(dkwgbe);
-		      error1:
+		dmvgbe->p_txdesc = (struct mvgbe_txdesc *) memalign(
+			PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
+
+		if (!dmvgbe->p_txdesc) {
+			free(dmvgbe->p_aligned_txbuf);
+error4:
+			free(dmvgbe->p_rxbuf);
+error3:
+			free(dmvgbe->p_rxdesc);
+error2:
+			free(dmvgbe);
+error1:
 			printf("Err.. %s Failed to allocate memory\n",
 				__FUNCTION__);
 			return -1;
 		}
 
-		dev = &dkwgbe->dev;
+		dev = &dmvgbe->dev;
 
 		/* must be less than NAMESIZE (16) */
 		sprintf(dev->name, "egiga%d", devnum);
@@ -685,13 +701,15 @@ int kirkwood_egiga_initialize(bd_t * bis)
 		/* Extract the MAC address from the environment */
 		switch (devnum) {
 		case 0:
-			dkwgbe->regs = (void *)KW_EGIGA0_BASE;
+			dmvgbe->regs = (void *)MVGBE0_BASE;
 			s = "ethaddr";
 			break;
+#if defined(MVGBE1_BASE)
 		case 1:
-			dkwgbe->regs = (void *)KW_EGIGA1_BASE;
+			dmvgbe->regs = (void *)MVGBE1_BASE;
 			s = "eth1addr";
 			break;
+#endif
 		default:	/* this should never happen */
 			printf("Err..(%s) Invalid device number %d\n",
 				__FUNCTION__, devnum);
@@ -717,19 +735,19 @@ int kirkwood_egiga_initialize(bd_t * bis)
 			eth_setenv_enetaddr(s, dev->enetaddr);
 		}
 
-		dev->init = (void *)kwgbe_init;
-		dev->halt = (void *)kwgbe_halt;
-		dev->send = (void *)kwgbe_send;
-		dev->recv = (void *)kwgbe_recv;
-		dev->write_hwaddr = (void *)kwgbe_write_hwaddr;
+		dev->init = (void *)mvgbe_init;
+		dev->halt = (void *)mvgbe_halt;
+		dev->send = (void *)mvgbe_send;
+		dev->recv = (void *)mvgbe_recv;
+		dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
 
 		eth_register(dev);
 
 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 		miiphy_register(dev->name, smi_reg_read, smi_reg_write);
 		/* Set phy address of the port */
-		miiphy_write(dev->name, KIRKWOOD_PHY_ADR_REQUEST,
-				KIRKWOOD_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
+		miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
+				MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
 #endif
 	}
 	return 0;
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index 30c773ca5c9..7db5af450e2 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -25,10 +25,10 @@
  * MA 02110-1301 USA
  */
 
-#ifndef __EGIGA_H__
-#define __EGIGA_H__
+#ifndef __MVGBE_H__
+#define __MVGBE_H__
 
-#define MAX_KWGBE_DEVS	2	/*controller has two ports */
+#define MAX_MVGBE_DEVS	2	/*controller has two ports */
 
 /* PHY_BASE_ADR is board specific and can be configured */
 #if defined (CONFIG_PHY_BASE_ADR)
@@ -49,60 +49,60 @@
 #define RXUQ	0 /* Used Rx queue */
 #define TXUQ	0 /* Used Rx queue */
 
-#define to_dkwgbe(_kd) container_of(_kd, struct kwgbe_device, dev)
-#define KWGBEREG_WR(adr, val)		writel(val, &adr)
-#define KWGBEREG_RD(adr)		readl(&adr)
-#define KWGBEREG_BITS_RESET(adr, val)	writel(readl(&adr) & ~(val), &adr)
-#define KWGBEREG_BITS_SET(adr, val)	writel(readl(&adr) | val, &adr)
+#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
+#define MVGBE_REG_WR(adr, val)		writel(val, &adr)
+#define MVGBE_REG_RD(adr)		readl(&adr)
+#define MVGBE_REG_BITS_RESET(adr, val)	writel(readl(&adr) & ~(val), &adr)
+#define MVGBE_REG_BITS_SET(adr, val)	writel(readl(&adr) | val, &adr)
 
 /* Default port configuration value */
 #define PRT_CFG_VAL			( \
-	KWGBE_UCAST_MOD_NRML		| \
-	KWGBE_DFLT_RXQ(RXUQ)		| \
-	KWGBE_DFLT_RX_ARPQ(RXUQ)	| \
-	KWGBE_RX_BC_IF_NOT_IP_OR_ARP	| \
-	KWGBE_RX_BC_IF_IP		| \
-	KWGBE_RX_BC_IF_ARP		| \
-	KWGBE_CPTR_TCP_FRMS_DIS		| \
-	KWGBE_CPTR_UDP_FRMS_DIS		| \
-	KWGBE_DFLT_RX_TCPQ(RXUQ)	| \
-	KWGBE_DFLT_RX_UDPQ(RXUQ)	| \
-	KWGBE_DFLT_RX_BPDUQ(RXUQ))
+	MVGBE_UCAST_MOD_NRML		| \
+	MVGBE_DFLT_RXQ(RXUQ)		| \
+	MVGBE_DFLT_RX_ARPQ(RXUQ)	| \
+	MVGBE_RX_BC_IF_NOT_IP_OR_ARP	| \
+	MVGBE_RX_BC_IF_IP		| \
+	MVGBE_RX_BC_IF_ARP		| \
+	MVGBE_CPTR_TCP_FRMS_DIS		| \
+	MVGBE_CPTR_UDP_FRMS_DIS		| \
+	MVGBE_DFLT_RX_TCPQ(RXUQ)	| \
+	MVGBE_DFLT_RX_UDPQ(RXUQ)	| \
+	MVGBE_DFLT_RX_BPDUQ(RXUQ))
 
 /* Default port extend configuration value */
 #define PORT_CFG_EXTEND_VALUE		\
-	KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL	| \
-	KWGBE_PARTITION_DIS		| \
-	KWGBE_TX_CRC_GENERATION_EN
+	MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	| \
+	MVGBE_PARTITION_DIS		| \
+	MVGBE_TX_CRC_GENERATION_EN
 
-#define GT_KWGBE_IPG_INT_RX(value)	((value & 0x3fff) << 8)
+#define GT_MVGBE_IPG_INT_RX(value)	((value & 0x3fff) << 8)
 
 /* Default sdma control value */
 #define PORT_SDMA_CFG_VALUE		( \
-	KWGBE_RX_BURST_SIZE_16_64BIT	| \
-	KWGBE_BLM_RX_NO_SWAP		| \
-	KWGBE_BLM_TX_NO_SWAP		| \
-	GT_KWGBE_IPG_INT_RX(RXUQ)	| \
-	KWGBE_TX_BURST_SIZE_16_64BIT)
+	MVGBE_RX_BURST_SIZE_16_64BIT	| \
+	MVGBE_BLM_RX_NO_SWAP		| \
+	MVGBE_BLM_TX_NO_SWAP		| \
+	GT_MVGBE_IPG_INT_RX(RXUQ)	| \
+	MVGBE_TX_BURST_SIZE_16_64BIT)
 
 /* Default port serial control value */
 #define PORT_SERIAL_CONTROL_VALUE		( \
-	KWGBE_FORCE_LINK_PASS			| \
-	KWGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
-	KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
-	KWGBE_ADV_NO_FLOW_CTRL			| \
-	KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
-	KWGBE_FORCE_BP_MODE_NO_JAM		| \
+	MVGBE_FORCE_LINK_PASS			| \
+	MVGBE_DIS_AUTO_NEG_FOR_DUPLX		| \
+	MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	| \
+	MVGBE_ADV_NO_FLOW_CTRL			| \
+	MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	| \
+	MVGBE_FORCE_BP_MODE_NO_JAM		| \
 	(1 << 9) /* Reserved bit has to be 1 */	| \
-	KWGBE_DO_NOT_FORCE_LINK_FAIL		| \
-	KWGBE_EN_AUTO_NEG_SPEED_GMII		| \
-	KWGBE_DTE_ADV_0				| \
-	KWGBE_MIIPHY_MAC_MODE			| \
-	KWGBE_AUTO_NEG_NO_CHANGE		| \
-	KWGBE_MAX_RX_PACKET_1552BYTE		| \
-	KWGBE_CLR_EXT_LOOPBACK			| \
-	KWGBE_SET_FULL_DUPLEX_MODE		| \
-	KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
+	MVGBE_DO_NOT_FORCE_LINK_FAIL		| \
+	MVGBE_EN_AUTO_NEG_SPEED_GMII		| \
+	MVGBE_DTE_ADV_0				| \
+	MVGBE_MIIPHY_MAC_MODE			| \
+	MVGBE_AUTO_NEG_NO_CHANGE		| \
+	MVGBE_MAX_RX_PACKET_1552BYTE		| \
+	MVGBE_CLR_EXT_LOOPBACK			| \
+	MVGBE_SET_FULL_DUPLEX_MODE		| \
+	MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
 
 /* Tx WRR confoguration macros */
 #define PORT_MAX_TRAN_UNIT	0x24	/* MTU register (default) 9KByte */
@@ -112,187 +112,189 @@
 #define ACCEPT_MAC_ADDR		0
 #define REJECT_MAC_ADDR		1
 /* Size of a Tx/Rx descriptor used in chain list data structure */
-#define KW_RXQ_DESC_ALIGNED_SIZE	\
-	(((sizeof(struct kwgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
+#define MV_RXQ_DESC_ALIGNED_SIZE	\
+	(((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
 /* Buffer offset from buffer pointer */
 #define RX_BUF_OFFSET		0x2
 
 /* Port serial status reg (PSR) */
-#define KWGBE_INTERFACE_GMII_MII	0
-#define KWGBE_INTERFACE_PCM		1
-#define KWGBE_LINK_IS_DOWN		0
-#define KWGBE_LINK_IS_UP		(1 << 1)
-#define KWGBE_PORT_AT_HALF_DUPLEX	0
-#define KWGBE_PORT_AT_FULL_DUPLEX	(1 << 2)
-#define KWGBE_RX_FLOW_CTRL_DISD		0
-#define KWGBE_RX_FLOW_CTRL_ENBALED	(1 << 3)
-#define KWGBE_GMII_SPEED_100_10		0
-#define KWGBE_GMII_SPEED_1000		(1 << 4)
-#define KWGBE_MII_SPEED_10		0
-#define KWGBE_MII_SPEED_100		(1 << 5)
-#define KWGBE_NO_TX			0
-#define KWGBE_TX_IN_PROGRESS		(1 << 7)
-#define KWGBE_BYPASS_NO_ACTIVE		0
-#define KWGBE_BYPASS_ACTIVE		(1 << 8)
-#define KWGBE_PORT_NOT_AT_PARTN_STT	0
-#define KWGBE_PORT_AT_PARTN_STT		(1 << 9)
-#define KWGBE_PORT_TX_FIFO_NOT_EMPTY	0
-#define KWGBE_PORT_TX_FIFO_EMPTY	(1 << 10)
+#define MVGBE_INTERFACE_GMII_MII	0
+#define MVGBE_INTERFACE_PCM		1
+#define MVGBE_LINK_IS_DOWN		0
+#define MVGBE_LINK_IS_UP		(1 << 1)
+#define MVGBE_PORT_AT_HALF_DUPLEX	0
+#define MVGBE_PORT_AT_FULL_DUPLEX	(1 << 2)
+#define MVGBE_RX_FLOW_CTRL_DISD		0
+#define MVGBE_RX_FLOW_CTRL_ENBALED	(1 << 3)
+#define MVGBE_GMII_SPEED_100_10		0
+#define MVGBE_GMII_SPEED_1000		(1 << 4)
+#define MVGBE_MII_SPEED_10		0
+#define MVGBE_MII_SPEED_100		(1 << 5)
+#define MVGBE_NO_TX			0
+#define MVGBE_TX_IN_PROGRESS		(1 << 7)
+#define MVGBE_BYPASS_NO_ACTIVE		0
+#define MVGBE_BYPASS_ACTIVE		(1 << 8)
+#define MVGBE_PORT_NOT_AT_PARTN_STT	0
+#define MVGBE_PORT_AT_PARTN_STT		(1 << 9)
+#define MVGBE_PORT_TX_FIFO_NOT_EMPTY	0
+#define MVGBE_PORT_TX_FIFO_EMPTY	(1 << 10)
 
 /* These macros describes the Port configuration reg (Px_cR) bits */
-#define KWGBE_UCAST_MOD_NRML		0
-#define KWGBE_UNICAST_PROMISCUOUS_MODE	1
-#define KWGBE_DFLT_RXQ(_x)		(_x << 1)
-#define KWGBE_DFLT_RX_ARPQ(_x)		(_x << 4)
-#define KWGBE_RX_BC_IF_NOT_IP_OR_ARP	0
-#define KWGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
-#define KWGBE_RX_BC_IF_IP		0
-#define KWGBE_REJECT_BC_IF_IP		(1 << 8)
-#define KWGBE_RX_BC_IF_ARP		0
-#define KWGBE_REJECT_BC_IF_ARP		(1 << 9)
-#define KWGBE_TX_AM_NO_UPDATE_ERR_SMRY	(1 << 12)
-#define KWGBE_CPTR_TCP_FRMS_DIS		0
-#define KWGBE_CPTR_TCP_FRMS_EN		(1 << 14)
-#define KWGBE_CPTR_UDP_FRMS_DIS		0
-#define KWGBE_CPTR_UDP_FRMS_EN		(1 << 15)
-#define KWGBE_DFLT_RX_TCPQ(_x)		(_x << 16)
-#define KWGBE_DFLT_RX_UDPQ(_x)		(_x << 19)
-#define KWGBE_DFLT_RX_BPDUQ(_x)		(_x << 22)
-#define KWGBE_DFLT_RX_TCP_CHKSUM_MODE	(1 << 25)
+#define MVGBE_UCAST_MOD_NRML		0
+#define MVGBE_UNICAST_PROMISCUOUS_MODE	1
+#define MVGBE_DFLT_RXQ(_x)		(_x << 1)
+#define MVGBE_DFLT_RX_ARPQ(_x)		(_x << 4)
+#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP	0
+#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
+#define MVGBE_RX_BC_IF_IP		0
+#define MVGBE_REJECT_BC_IF_IP		(1 << 8)
+#define MVGBE_RX_BC_IF_ARP		0
+#define MVGBE_REJECT_BC_IF_ARP		(1 << 9)
+#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY	(1 << 12)
+#define MVGBE_CPTR_TCP_FRMS_DIS		0
+#define MVGBE_CPTR_TCP_FRMS_EN		(1 << 14)
+#define MVGBE_CPTR_UDP_FRMS_DIS		0
+#define MVGBE_CPTR_UDP_FRMS_EN		(1 << 15)
+#define MVGBE_DFLT_RX_TCPQ(_x)		(_x << 16)
+#define MVGBE_DFLT_RX_UDPQ(_x)		(_x << 19)
+#define MVGBE_DFLT_RX_BPDUQ(_x)		(_x << 22)
+#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE	(1 << 25)
 
 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
-#define KWGBE_CLASSIFY_EN			1
-#define KWGBE_SPAN_BPDU_PACKETS_AS_NORMAL	0
-#define KWGBE_SPAN_BPDU_PACKETS_TO_RX_Q7	(1 << 1)
-#define KWGBE_PARTITION_DIS			0
-#define KWGBE_PARTITION_EN			(1 << 2)
-#define KWGBE_TX_CRC_GENERATION_EN		0
-#define KWGBE_TX_CRC_GENERATION_DIS		(1 << 3)
+#define MVGBE_CLASSIFY_EN			1
+#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL	0
+#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7	(1 << 1)
+#define MVGBE_PARTITION_DIS			0
+#define MVGBE_PARTITION_EN			(1 << 2)
+#define MVGBE_TX_CRC_GENERATION_EN		0
+#define MVGBE_TX_CRC_GENERATION_DIS		(1 << 3)
 
 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
-#define KWGBE_RIFB				1
-#define KWGBE_RX_BURST_SIZE_1_64BIT		0
-#define KWGBE_RX_BURST_SIZE_2_64BIT		(1 << 1)
-#define KWGBE_RX_BURST_SIZE_4_64BIT		(1 << 2)
-#define KWGBE_RX_BURST_SIZE_8_64BIT		((1 << 2) | (1 << 1))
-#define KWGBE_RX_BURST_SIZE_16_64BIT		(1 << 3)
-#define KWGBE_BLM_RX_NO_SWAP			(1 << 4)
-#define KWGBE_BLM_RX_BYTE_SWAP			0
-#define KWGBE_BLM_TX_NO_SWAP			(1 << 5)
-#define KWGBE_BLM_TX_BYTE_SWAP			0
-#define KWGBE_DESCRIPTORS_BYTE_SWAP		(1 << 6)
-#define KWGBE_DESCRIPTORS_NO_SWAP		0
-#define KWGBE_TX_BURST_SIZE_1_64BIT		0
-#define KWGBE_TX_BURST_SIZE_2_64BIT		(1 << 22)
-#define KWGBE_TX_BURST_SIZE_4_64BIT		(1 << 23)
-#define KWGBE_TX_BURST_SIZE_8_64BIT		((1 << 23) | (1 << 22))
-#define KWGBE_TX_BURST_SIZE_16_64BIT		(1 << 24)
+#define MVGBE_RIFB				1
+#define MVGBE_RX_BURST_SIZE_1_64BIT		0
+#define MVGBE_RX_BURST_SIZE_2_64BIT		(1 << 1)
+#define MVGBE_RX_BURST_SIZE_4_64BIT		(1 << 2)
+#define MVGBE_RX_BURST_SIZE_8_64BIT		((1 << 2) | (1 << 1))
+#define MVGBE_RX_BURST_SIZE_16_64BIT		(1 << 3)
+#define MVGBE_BLM_RX_NO_SWAP			(1 << 4)
+#define MVGBE_BLM_RX_BYTE_SWAP			0
+#define MVGBE_BLM_TX_NO_SWAP			(1 << 5)
+#define MVGBE_BLM_TX_BYTE_SWAP			0
+#define MVGBE_DESCRIPTORS_BYTE_SWAP		(1 << 6)
+#define MVGBE_DESCRIPTORS_NO_SWAP		0
+#define MVGBE_TX_BURST_SIZE_1_64BIT		0
+#define MVGBE_TX_BURST_SIZE_2_64BIT		(1 << 22)
+#define MVGBE_TX_BURST_SIZE_4_64BIT		(1 << 23)
+#define MVGBE_TX_BURST_SIZE_8_64BIT		((1 << 23) | (1 << 22))
+#define MVGBE_TX_BURST_SIZE_16_64BIT		(1 << 24)
 
 /* These macros describes the Port serial control reg (PSCR) bits */
-#define KWGBE_SERIAL_PORT_DIS			0
-#define KWGBE_SERIAL_PORT_EN			1
-#define KWGBE_FORCE_LINK_PASS			(1 << 1)
-#define KWGBE_DO_NOT_FORCE_LINK_PASS		0
-#define KWGBE_EN_AUTO_NEG_FOR_DUPLX		0
-#define KWGBE_DIS_AUTO_NEG_FOR_DUPLX		(1 << 2)
-#define KWGBE_EN_AUTO_NEG_FOR_FLOW_CTRL		0
-#define KWGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	(1 << 3)
-#define KWGBE_ADV_NO_FLOW_CTRL			0
-#define KWGBE_ADV_SYMMETRIC_FLOW_CTRL		(1 << 4)
-#define KWGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	0
-#define KWGBE_FORCE_FC_MODE_TX_PAUSE_DIS	(1 << 5)
-#define KWGBE_FORCE_BP_MODE_NO_JAM		0
-#define KWGBE_FORCE_BP_MODE_JAM_TX		(1 << 7)
-#define KWGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR	(1 << 8)
-#define KWGBE_FORCE_LINK_FAIL			0
-#define KWGBE_DO_NOT_FORCE_LINK_FAIL		(1 << 10)
-#define KWGBE_DIS_AUTO_NEG_SPEED_GMII		(1 << 13)
-#define KWGBE_EN_AUTO_NEG_SPEED_GMII		0
-#define KWGBE_DTE_ADV_0				0
-#define KWGBE_DTE_ADV_1				(1 << 14)
-#define KWGBE_MIIPHY_MAC_MODE			0
-#define KWGBE_MIIPHY_PHY_MODE			(1 << 15)
-#define KWGBE_AUTO_NEG_NO_CHANGE		0
-#define KWGBE_RESTART_AUTO_NEG			(1 << 16)
-#define KWGBE_MAX_RX_PACKET_1518BYTE		0
-#define KWGBE_MAX_RX_PACKET_1522BYTE		(1 << 17)
-#define KWGBE_MAX_RX_PACKET_1552BYTE		(1 << 18)
-#define KWGBE_MAX_RX_PACKET_9022BYTE		((1 << 18) | (1 << 17))
-#define KWGBE_MAX_RX_PACKET_9192BYTE		(1 << 19)
-#define KWGBE_MAX_RX_PACKET_9700BYTE		((1 << 19) | (1 << 17))
-#define KWGBE_SET_EXT_LOOPBACK			(1 << 20)
-#define KWGBE_CLR_EXT_LOOPBACK			0
-#define KWGBE_SET_FULL_DUPLEX_MODE		(1 << 21)
-#define KWGBE_SET_HALF_DUPLEX_MODE		0
-#define KWGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	(1 << 22)
-#define KWGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
-#define KWGBE_SET_GMII_SPEED_TO_10_100		0
-#define KWGBE_SET_GMII_SPEED_TO_1000		(1 << 23)
-#define KWGBE_SET_MII_SPEED_TO_10		0
-#define KWGBE_SET_MII_SPEED_TO_100		(1 << 24)
+#define MVGBE_SERIAL_PORT_DIS			0
+#define MVGBE_SERIAL_PORT_EN			1
+#define MVGBE_FORCE_LINK_PASS			(1 << 1)
+#define MVGBE_DO_NOT_FORCE_LINK_PASS		0
+#define MVGBE_EN_AUTO_NEG_FOR_DUPLX		0
+#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX		(1 << 2)
+#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL		0
+#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL	(1 << 3)
+#define MVGBE_ADV_NO_FLOW_CTRL			0
+#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL		(1 << 4)
+#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX	0
+#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS	(1 << 5)
+#define MVGBE_FORCE_BP_MODE_NO_JAM		0
+#define MVGBE_FORCE_BP_MODE_JAM_TX		(1 << 7)
+#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR	(1 << 8)
+#define MVGBE_FORCE_LINK_FAIL			0
+#define MVGBE_DO_NOT_FORCE_LINK_FAIL		(1 << 10)
+#define MVGBE_DIS_AUTO_NEG_SPEED_GMII		(1 << 13)
+#define MVGBE_EN_AUTO_NEG_SPEED_GMII		0
+#define MVGBE_DTE_ADV_0				0
+#define MVGBE_DTE_ADV_1				(1 << 14)
+#define MVGBE_MIIPHY_MAC_MODE			0
+#define MVGBE_MIIPHY_PHY_MODE			(1 << 15)
+#define MVGBE_AUTO_NEG_NO_CHANGE		0
+#define MVGBE_RESTART_AUTO_NEG			(1 << 16)
+#define MVGBE_MAX_RX_PACKET_1518BYTE		0
+#define MVGBE_MAX_RX_PACKET_1522BYTE		(1 << 17)
+#define MVGBE_MAX_RX_PACKET_1552BYTE		(1 << 18)
+#define MVGBE_MAX_RX_PACKET_9022BYTE		((1 << 18) | (1 << 17))
+#define MVGBE_MAX_RX_PACKET_9192BYTE		(1 << 19)
+#define MVGBE_MAX_RX_PACKET_9700BYTE		((1 << 19) | (1 << 17))
+#define MVGBE_SET_EXT_LOOPBACK			(1 << 20)
+#define MVGBE_CLR_EXT_LOOPBACK			0
+#define MVGBE_SET_FULL_DUPLEX_MODE		(1 << 21)
+#define MVGBE_SET_HALF_DUPLEX_MODE		0
+#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX	(1 << 22)
+#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
+#define MVGBE_SET_GMII_SPEED_TO_10_100		0
+#define MVGBE_SET_GMII_SPEED_TO_1000		(1 << 23)
+#define MVGBE_SET_MII_SPEED_TO_10		0
+#define MVGBE_SET_MII_SPEED_TO_100		(1 << 24)
 
 /* SMI register fields */
-#define KWGBE_PHY_SMI_TIMEOUT		10000
-#define KWGBE_PHY_SMI_DATA_OFFS		0	/* Data */
-#define KWGBE_PHY_SMI_DATA_MASK		(0xffff << KWGBE_PHY_SMI_DATA_OFFS)
-#define KWGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */
-#define KWGBE_PHY_SMI_DEV_ADDR_MASK	(PHYADR_MASK << KWGBE_PHY_SMI_DEV_ADDR_OFFS)
-#define KWGBE_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr */
-#define KWGBE_SMI_REG_ADDR_MASK		(PHYADR_MASK << KWGBE_SMI_REG_ADDR_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_OFFS	26	/* Write/Read opcode */
-#define KWGBE_PHY_SMI_OPCODE_MASK	(3 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_WRITE	(0 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_OPCODE_READ	(1 << KWGBE_PHY_SMI_OPCODE_OFFS)
-#define KWGBE_PHY_SMI_READ_VALID_MASK	(1 << 27)	/* Read Valid */
-#define KWGBE_PHY_SMI_BUSY_MASK		(1 << 28)	/* Busy */
+#define MVGBE_PHY_SMI_TIMEOUT		10000
+#define MVGBE_PHY_SMI_DATA_OFFS		0	/* Data */
+#define MVGBE_PHY_SMI_DATA_MASK		(0xffff << MVGBE_PHY_SMI_DATA_OFFS)
+#define MVGBE_PHY_SMI_DEV_ADDR_OFFS	16	/* PHY device address */
+#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
+	(PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
+#define MVGBE_SMI_REG_ADDR_OFFS		21	/* PHY device reg addr */
+#define MVGBE_SMI_REG_ADDR_MASK \
+	(PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_OFFS	26	/* Write/Read opcode */
+#define MVGBE_PHY_SMI_OPCODE_MASK	(3 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_WRITE	(0 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_OPCODE_READ	(1 << MVGBE_PHY_SMI_OPCODE_OFFS)
+#define MVGBE_PHY_SMI_READ_VALID_MASK	(1 << 27)	/* Read Valid */
+#define MVGBE_PHY_SMI_BUSY_MASK		(1 << 28)	/* Busy */
 
 /* SDMA command status fields macros */
 /* Tx & Rx descriptors status */
-#define KWGBE_ERROR_SUMMARY		1
+#define MVGBE_ERROR_SUMMARY		1
 /* Tx & Rx descriptors command */
-#define KWGBE_BUFFER_OWNED_BY_DMA	(1 << 31)
+#define MVGBE_BUFFER_OWNED_BY_DMA	(1 << 31)
 /* Tx descriptors status */
-#define KWGBE_LC_ERROR			0
-#define KWGBE_UR_ERROR			(1 << 1)
-#define KWGBE_RL_ERROR			(1 << 2)
-#define KWGBE_LLC_SNAP_FORMAT		(1 << 9)
-#define KWGBE_TX_LAST_FRAME		(1 << 20)
+#define MVGBE_LC_ERROR			0
+#define MVGBE_UR_ERROR			(1 << 1)
+#define MVGBE_RL_ERROR			(1 << 2)
+#define MVGBE_LLC_SNAP_FORMAT		(1 << 9)
+#define MVGBE_TX_LAST_FRAME		(1 << 20)
 
 /* Rx descriptors status */
-#define KWGBE_CRC_ERROR			0
-#define KWGBE_OVERRUN_ERROR		(1 << 1)
-#define KWGBE_MAX_FRAME_LENGTH_ERROR	(1 << 2)
-#define KWGBE_RESOURCE_ERROR		((1 << 2) | (1 << 1))
-#define KWGBE_VLAN_TAGGED		(1 << 19)
-#define KWGBE_BPDU_FRAME		(1 << 20)
-#define KWGBE_TCP_FRAME_OVER_IP_V_4	0
-#define KWGBE_UDP_FRAME_OVER_IP_V_4	(1 << 21)
-#define KWGBE_OTHER_FRAME_TYPE		(1 << 22)
-#define KWGBE_LAYER_2_IS_KWGBE_V_2	(1 << 23)
-#define KWGBE_FRAME_TYPE_IP_V_4		(1 << 24)
-#define KWGBE_FRAME_HEADER_OK		(1 << 25)
-#define KWGBE_RX_LAST_DESC		(1 << 26)
-#define KWGBE_RX_FIRST_DESC		(1 << 27)
-#define KWGBE_UNKNOWN_DESTINATION_ADDR	(1 << 28)
-#define KWGBE_RX_EN_INTERRUPT		(1 << 29)
-#define KWGBE_LAYER_4_CHECKSUM_OK	(1 << 30)
+#define MVGBE_CRC_ERROR			0
+#define MVGBE_OVERRUN_ERROR		(1 << 1)
+#define MVGBE_MAX_FRAME_LENGTH_ERROR	(1 << 2)
+#define MVGBE_RESOURCE_ERROR		((1 << 2) | (1 << 1))
+#define MVGBE_VLAN_TAGGED		(1 << 19)
+#define MVGBE_BPDU_FRAME		(1 << 20)
+#define MVGBE_TCP_FRAME_OVER_IP_V_4	0
+#define MVGBE_UDP_FRAME_OVER_IP_V_4	(1 << 21)
+#define MVGBE_OTHER_FRAME_TYPE		(1 << 22)
+#define MVGBE_LAYER_2_IS_MVGBE_V_2	(1 << 23)
+#define MVGBE_FRAME_TYPE_IP_V_4		(1 << 24)
+#define MVGBE_FRAME_HEADER_OK		(1 << 25)
+#define MVGBE_RX_LAST_DESC		(1 << 26)
+#define MVGBE_RX_FIRST_DESC		(1 << 27)
+#define MVGBE_UNKNOWN_DESTINATION_ADDR	(1 << 28)
+#define MVGBE_RX_EN_INTERRUPT		(1 << 29)
+#define MVGBE_LAYER_4_CHECKSUM_OK	(1 << 30)
 
 /* Rx descriptors byte count */
-#define KWGBE_FRAME_FRAGMENTED		(1 << 2)
+#define MVGBE_FRAME_FRAGMENTED		(1 << 2)
 
 /* Tx descriptors command */
-#define KWGBE_LAYER_4_CHECKSUM_FIRST_DESC	(1 << 10)
-#define KWGBE_FRAME_SET_TO_VLAN			(1 << 15)
-#define KWGBE_TCP_FRAME				0
-#define KWGBE_UDP_FRAME				(1 << 16)
-#define KWGBE_GEN_TCP_UDP_CHECKSUM		(1 << 17)
-#define KWGBE_GEN_IP_V_4_CHECKSUM		(1 << 18)
-#define KWGBE_ZERO_PADDING			(1 << 19)
-#define KWGBE_TX_LAST_DESC			(1 << 20)
-#define KWGBE_TX_FIRST_DESC			(1 << 21)
-#define KWGBE_GEN_CRC				(1 << 22)
-#define KWGBE_TX_EN_INTERRUPT			(1 << 23)
-#define KWGBE_AUTO_MODE				(1 << 30)
+#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC	(1 << 10)
+#define MVGBE_FRAME_SET_TO_VLAN			(1 << 15)
+#define MVGBE_TCP_FRAME				0
+#define MVGBE_UDP_FRAME				(1 << 16)
+#define MVGBE_GEN_TCP_UDP_CHECKSUM		(1 << 17)
+#define MVGBE_GEN_IP_V_4_CHECKSUM		(1 << 18)
+#define MVGBE_ZERO_PADDING			(1 << 19)
+#define MVGBE_TX_LAST_DESC			(1 << 20)
+#define MVGBE_TX_FIRST_DESC			(1 << 21)
+#define MVGBE_GEN_CRC				(1 << 22)
+#define MVGBE_TX_EN_INTERRUPT			(1 << 23)
+#define MVGBE_AUTO_MODE				(1 << 30)
 
 /* Address decode parameters */
 /* Ethernet Base Address Register bits */
@@ -341,24 +343,24 @@
 #define EWIN_ACCESS_FULL	((1 << 1) | 1)
 
 /* structures represents Controller registers */
-struct kwgbe_barsz {
+struct mvgbe_barsz {
 	u32 bar;
 	u32 size;
 };
 
-struct kwgbe_rxcdp {
-	struct kwgbe_rxdesc *rxcdp;
+struct mvgbe_rxcdp {
+	struct mvgbe_rxdesc *rxcdp;
 	u32 rxcdp_pad[3];
 };
 
-struct kwgbe_tqx {
+struct mvgbe_tqx {
 	u32 qxttbc;
 	u32 tqxtbc;
 	u32 tqxac;
 	u32 tqxpad;
 };
 
-struct kwgbe_registers {
+struct mvgbe_registers {
 	u32 phyadr;
 	u32 smi;
 	u32 euda;
@@ -372,7 +374,7 @@ struct kwgbe_registers {
 	u8 pad3[0x0b0 - 0x098 - 4];
 	u32 euc;
 	u8 pad3a[0x200 - 0x0b0 - 4];
-	struct kwgbe_barsz barsz[6];
+	struct mvgbe_barsz barsz[6];
 	u8 pad4[0x280 - 0x22c - 4];
 	u32 ha_remap[4];
 	u32 bare;
@@ -417,14 +419,14 @@ struct kwgbe_registers {
 	u32 pmtu;
 	u32 pmtbs;
 	u8 pad14[0x60c - 0x4ec - 4];
-	struct kwgbe_rxcdp rxcdp[7];
-	struct kwgbe_rxdesc *rxcdp7;
+	struct mvgbe_rxcdp rxcdp[7];
+	struct mvgbe_rxdesc *rxcdp7;
 	u32 rqc;
-	struct kwgbe_txdesc *tcsdp;
+	struct mvgbe_txdesc *tcsdp;
 	u8 pad15[0x6c0 - 0x684 - 4];
-	struct kwgbe_txdesc *tcqdp[8];
+	struct mvgbe_txdesc *tcqdp[8];
 	u8 pad16[0x700 - 0x6dc - 4];
-	struct kwgbe_tqx tqx[8];
+	struct mvgbe_tqx tqx[8];
 	u32 pttbc;
 	u8 pad17[0x7a8 - 0x780 - 4];
 	u32 tqxipg0;
@@ -447,26 +449,26 @@ struct kwgbe_registers {
 };
 
 /* structures/enums needed by driver */
-enum kwgbe_adrwin {
-	KWGBE_WIN0,
-	KWGBE_WIN1,
-	KWGBE_WIN2,
-	KWGBE_WIN3,
-	KWGBE_WIN4,
-	KWGBE_WIN5
+enum mvgbe_adrwin {
+	MVGBE_WIN0,
+	MVGBE_WIN1,
+	MVGBE_WIN2,
+	MVGBE_WIN3,
+	MVGBE_WIN4,
+	MVGBE_WIN5
 };
 
-enum kwgbe_target {
-	KWGBE_TARGET_DRAM,
-	KWGBE_TARGET_DEV,
-	KWGBE_TARGET_CBS,
-	KWGBE_TARGET_PCI0,
-	KWGBE_TARGET_PCI1
+enum mvgbe_target {
+	MVGBE_TARGET_DRAM,
+	MVGBE_TARGET_DEV,
+	MVGBE_TARGET_CBS,
+	MVGBE_TARGET_PCI0,
+	MVGBE_TARGET_PCI1
 };
 
-struct kwgbe_winparam {
-	enum kwgbe_adrwin win;	/* Window number */
-	enum kwgbe_target target;	/* System targets */
+struct mvgbe_winparam {
+	enum mvgbe_adrwin win;	/* Window number */
+	enum mvgbe_target target;	/* System targets */
 	u16 attrib;		/* BAR attrib. See above macros */
 	u32 base_addr;		/* Window base address in u32 form */
 	u32 high_addr;		/* Window high address in u32 form */
@@ -475,31 +477,31 @@ struct kwgbe_winparam {
 	u16 access_ctrl;	/*Access ctrl register. see above macros */
 };
 
-struct kwgbe_rxdesc {
+struct mvgbe_rxdesc {
 	u32 cmd_sts;		/* Descriptor command status */
 	u16 buf_size;		/* Buffer size */
 	u16 byte_cnt;		/* Descriptor buffer byte count */
 	u8 *buf_ptr;		/* Descriptor buffer pointer */
-	struct kwgbe_rxdesc *nxtdesc_p;	/* Next descriptor pointer */
+	struct mvgbe_rxdesc *nxtdesc_p;	/* Next descriptor pointer */
 };
 
-struct kwgbe_txdesc {
+struct mvgbe_txdesc {
 	u32 cmd_sts;		/* Descriptor command status */
 	u16 l4i_chk;		/* CPU provided TCP Checksum */
 	u16 byte_cnt;		/* Descriptor buffer byte count */
 	u8 *buf_ptr;		/* Descriptor buffer ptr */
-	struct kwgbe_txdesc *nxtdesc_p;	/* Next descriptor ptr */
+	struct mvgbe_txdesc *nxtdesc_p;	/* Next descriptor ptr */
 };
 
 /* port device data struct */
-struct kwgbe_device {
+struct mvgbe_device {
 	struct eth_device dev;
-	struct kwgbe_registers *regs;
-	struct kwgbe_txdesc *p_txdesc;
-	struct kwgbe_rxdesc *p_rxdesc;
-	struct kwgbe_rxdesc *p_rxdesc_curr;
+	struct mvgbe_registers *regs;
+	struct mvgbe_txdesc *p_txdesc;
+	struct mvgbe_rxdesc *p_rxdesc;
+	struct mvgbe_rxdesc *p_rxdesc_curr;
 	u8 *p_rxbuf;
 	u8 *p_aligned_txbuf;
 };
 
-#endif /* __EGIGA_H__ */
+#endif /* __MVGBE_H__ */
diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h
index 2fbc6ad7f8c..eb3fa57d67e 100644
--- a/include/configs/guruplug.h
+++ b/include/configs/guruplug.h
@@ -172,9 +172,9 @@
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
 #define CONFIG_CMD_MII
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,1}	/* enable both ports */
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv88e1121 PHY */
diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h
index a928c2cfbb0..6519c9042c0 100644
--- a/include/configs/km_arm.h
+++ b/include/configs/km_arm.h
@@ -127,9 +127,9 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init 88E1118 PHY */
diff --git a/include/configs/mv88f6281gtw_ge.h b/include/configs/mv88f6281gtw_ge.h
index 96b4d1c6a12..9ef03a68b78 100644
--- a/include/configs/mv88f6281gtw_ge.h
+++ b/include/configs/mv88f6281gtw_ge.h
@@ -172,9 +172,9 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define	CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #endif /* CONFIG_CMD_NET */
 
diff --git a/include/configs/openrd_base.h b/include/configs/openrd_base.h
index d2f45028aec..52fa73def92 100644
--- a/include/configs/openrd_base.h
+++ b/include/configs/openrd_base.h
@@ -183,9 +183,9 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define	CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0x8
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
diff --git a/include/configs/rd6281a.h b/include/configs/rd6281a.h
index 3d8e25cc84d..585730111f1 100644
--- a/include/configs/rd6281a.h
+++ b/include/configs/rd6281a.h
@@ -171,8 +171,8 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,1}	/* enable both ports */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
+#define CONFIG_MVGBE_PORTS	{1, 1}	/* enable both ports */
 #define CONFIG_MV88E61XX_MULTICHIP_ADRMODE
 #define CONFIG_DIS_AUTO_NEG_SPEED_GMII /*Disable Auto speed negociation */
 #define CONFIG_PHY_SPEED	_1000BASET	/*Force PHYspeed to 1GBPs */
diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h
index e9edc449503..c5de86eb034 100644
--- a/include/configs/sheevaplug.h
+++ b/include/configs/sheevaplug.h
@@ -174,9 +174,9 @@
 #define CONFIG_NETCONSOLE	/* include NetConsole support   */
 #define CONFIG_NET_MULTI	/* specify more that one ports available */
 #define	CONFIG_MII		/* expose smi ove miiphy interface */
-#define CONFIG_KIRKWOOD_EGIGA	/* Enable kirkwood Gbe Controller Driver */
+#define CONFIG_MVGBE		/* Enable Marvell Gbe Controller Driver */
 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
-#define CONFIG_KIRKWOOD_EGIGA_PORTS	{1,0}	/* enable port 0 only */
+#define CONFIG_MVGBE_PORTS	{1, 0}	/* enable port 0 only */
 #define CONFIG_PHY_BASE_ADR	0
 #define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
 #define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
diff --git a/include/netdev.h b/include/netdev.h
index eb04b638767..94eedfe29de 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -63,7 +63,6 @@ int ftmac100_initialize(bd_t *bits);
 int greth_initialize(bd_t *bis);
 void gt6426x_eth_initialize(bd_t *bis);
 int inca_switch_initialize(bd_t *bis);
-int kirkwood_egiga_initialize(bd_t *bis);
 int lan91c96_initialize(u8 dev_num, int base_addr);
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
 int mcdmafec_initialize(bd_t *bis);
@@ -72,6 +71,7 @@ int mpc512x_fec_initialize(bd_t *bis);
 int mpc5xxx_fec_initialize(bd_t *bis);
 int mpc8220_fec_initialize(bd_t *bis);
 int mpc82xx_scc_enet_initialize(bd_t *bis);
+int mvgbe_initialize(bd_t *bis);
 int natsemi_initialize(bd_t *bis);
 int npe_initialize(bd_t *bis);
 int ns8382x_initialize(bd_t *bis);
-- 
cgit v1.3.1


From ab9164d0defe766fbbf0bc75c7e1645de63b7923 Mon Sep 17 00:00:00 2001
From: Albert Aribaud <albert.aribaud@free.fr>
Date: Mon, 12 Jul 2010 22:24:30 +0200
Subject: edminiv2: add ethernet support

Add edminiv2 board support for mv_egiga.
Add edminiv2 config to enable mv_egiga.

Signed-off-by: Albert Aribaud <albert.aribaud@free.fr>
Acked-by: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
---
 board/LaCie/edminiv2/edminiv2.c | 36 ++++++++++++++++++++++++++++++++++++
 board/LaCie/edminiv2/edminiv2.h | 41 +++++++++++++++++++++++++++++++++++++++++
 include/configs/edminiv2.h      | 19 +++++++++++++++----
 3 files changed, 92 insertions(+), 4 deletions(-)
 create mode 100644 board/LaCie/edminiv2/edminiv2.h

(limited to 'include')

diff --git a/board/LaCie/edminiv2/edminiv2.c b/board/LaCie/edminiv2/edminiv2.c
index 54c0ffe98a2..bb388edd13a 100644
--- a/board/LaCie/edminiv2/edminiv2.c
+++ b/board/LaCie/edminiv2/edminiv2.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <asm/arch/orion5x.h>
+#include "edminiv2.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -90,3 +91,38 @@ int board_init(void)
 
 	return 0;
 }
+
+#if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R)
+/* Configure and enable MV88E1116 PHY */
+void reset_phy(void)
+{
+	u16 reg;
+	u16 devadr;
+	char *name = "egiga0";
+
+	if (miiphy_set_current_dev(name))
+		return;
+
+	/* command to read PHY dev address */
+	if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
+		printf("Err..%s could not read PHY dev address\n",
+			__func__);
+		return;
+	}
+
+	/*
+	 * Enable RGMII delay on Tx and Rx for CPU port
+	 * Ref: sec 4.7.2 of chip datasheet
+	 */
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
+	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
+	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
+	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
+	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
+
+	/* reset the phy */
+	miiphy_reset(name, devadr);
+
+	printf("88E1116 Initialized on %s\n", name);
+}
+#endif /* CONFIG_RESET_PHY_R */
diff --git a/board/LaCie/edminiv2/edminiv2.h b/board/LaCie/edminiv2/edminiv2.h
new file mode 100644
index 00000000000..88e62b229c3
--- /dev/null
+++ b/board/LaCie/edminiv2/edminiv2.h
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2009
+ * Net Insight <www.netinsight.net>
+ * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
+ *
+ * Based on sheevaplug.h:
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __EDMINIV2_BASE_H
+#define __EDMINIV2_BASE_H
+
+/* PHY related */
+#define MV88E1116_LED_FCTRL_REG		10
+#define MV88E1116_CPRSP_CR3_REG		21
+#define MV88E1116_MAC_CTRL_REG		21
+#define MV88E1116_PGADR_REG		22
+#define MV88E1116_RGMII_TXTM_CTRL	(1 << 4)
+#define MV88E1116_RGMII_RXTM_CTRL	(1 << 5)
+
+#endif /* __EDMINIV2_BASE_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
index c3d95a04c43..055931cda63 100644
--- a/include/configs/edminiv2.h
+++ b/include/configs/edminiv2.h
@@ -131,12 +131,23 @@
  * Commands configuration - using default command set for now
  */
 #include <config_cmd_default.h>
+
 /*
- * Disabling some default commands for staggered bring-up
+ * Network
  */
-#undef CONFIG_CMD_BOOTD	/* no bootd since no net */
-#undef CONFIG_CMD_NET	/* no net since no eth */
-#undef CONFIG_CMD_NFS	/* no NFS since no net */
+
+#ifdef CONFIG_CMD_NET
+#define CONFIG_MVGBE				/* Enable Marvell GbE Driver */
+#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
+#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
+#define CONFIG_PHY_BASE_ADR	0x8
+#define CONFIG_RESET_PHY_R	/* use reset_phy() to init mv8831116 PHY */
+#define CONFIG_NETCONSOLE	/* include NetConsole support   */
+#define CONFIG_NET_MULTI	/* specify more that one ports available */
+#define	CONFIG_MII		/* expose smi ove miiphy interface */
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN	/* detect link using phy */
+#define CONFIG_ENV_OVERWRITE	/* ethaddr can be reprogrammed */
+#endif
 
 /*
  *  Environment variables configurations
-- 
cgit v1.3.1


From 37a4b75d4c30a37bda2bf8ae0c192446425b6f28 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Wed, 2 Jun 2010 06:13:50 -0400
Subject: Blackfin: bfin_spi: support gpios as chip selects

Rather than only support the pins dedicated as chip selects, utilize the
gpio framework to support any gpio pin.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 drivers/spi/bfin_spi.c            | 85 ++++++++++++++++++++++++++-------------
 include/configs/bfin_adi_common.h |  1 +
 2 files changed, 58 insertions(+), 28 deletions(-)

(limited to 'include')

diff --git a/drivers/spi/bfin_spi.c b/drivers/spi/bfin_spi.c
index 4e008a79b6a..e0ad0298d8a 100644
--- a/drivers/spi/bfin_spi.c
+++ b/drivers/spi/bfin_spi.c
@@ -13,6 +13,7 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
 
@@ -34,48 +35,68 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14)
 
 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
 
-__attribute__((weak))
+#define MAX_CTRL_CS 7
+
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
-#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
-	/* The SPI1/SPI2 buses are weird ... only 1 CS */
-	if (bus > 0 && cs != 1)
-		return 0;
-#endif
-	return (cs >= 1 && cs <= 7);
+	if (is_gpio_cs(cs))
+		return gpio_is_valid(gpio_cs(cs));
+	else
+		return (cs >= 1 && cs <= MAX_CTRL_CS);
 }
 
-__attribute__((weak))
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	write_SPI_FLG(bss,
-		(read_SPI_FLG(bss) &
-		~((!bss->flg << 8) << slave->cs)) |
-		(1 << slave->cs));
+
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		write_SPI_FLG(bss,
+			(read_SPI_FLG(bss) &
+			~((!bss->flg << 8) << slave->cs)) |
+			(1 << slave->cs));
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
+
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
-__attribute__((weak))
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	u16 flg;
-
-	/* make sure we force the cs to deassert rather than let the
-	 * pin float back up.  otherwise, exact timings may not be
-	 * met some of the time leading to random behavior (ugh).
-	 */
-	flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
-	write_SPI_FLG(bss, flg);
-	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 
-	flg &= ~(1 << slave->cs);
-	write_SPI_FLG(bss, flg);
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, !bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		u16 flg;
+
+		/* make sure we force the cs to deassert rather than let the
+		 * pin float back up.  otherwise, exact timings may not be
+		 * met some of the time leading to random behavior (ugh).
+		 */
+		flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+		write_SPI_FLG(bss, flg);
+		SSYNC();
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+		flg &= ~(1 << slave->cs);
+		write_SPI_FLG(bss, flg);
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
+
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
 void spi_init()
@@ -188,7 +209,13 @@ int spi_claim_bus(struct spi_slave *slave)
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
-	pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_request(cs, "bfin-spi");
+		gpio_direction_output(cs, !bss->flg);
+		pins[slave->bus][0] = P_DONTCARE;
+	} else
+		pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
 	peripheral_request_list(pins[slave->bus], "bfin-spi");
 
 	write_SPI_CTL(bss, bss->ctl);
@@ -205,6 +232,8 @@ void spi_release_bus(struct spi_slave *slave)
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
 	peripheral_free_list(pins[slave->bus]);
+	if (is_gpio_cs(slave->cs))
+		gpio_free(gpio_cs(slave->cs));
 
 	write_SPI_CTL(bss, 0);
 	SSYNC();
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index fa1e69486fd..82daeb10006 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -254,6 +254,7 @@
 /*
  * Misc Settings
  */
+#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
 #define CONFIG_LZMA
 
 #endif
-- 
cgit v1.3.1


From 0c929426f8239f4cdf8a4f418596261353bfb455 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Fri, 29 May 2009 18:00:16 -0400
Subject: Blackfin: bf518f-ezbrd: handle different PHYs dynamically

The original BF518F-EZBRD's have a Micrel KSZ8893 DSA on them, but newer
ones only have a National PHY (which lack a RX Error interrupt line).  So
in the board eth init code, dynamically detect what is hooked up to the MAC
and handle each accordingly.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 board/bf518f-ezbrd/bf518f-ezbrd.c | 23 +++++++++++++----------
 include/configs/bf518f-ezbrd.h    | 20 ++++++++++++++++++++
 2 files changed, 33 insertions(+), 10 deletions(-)

(limited to 'include')

diff --git a/board/bf518f-ezbrd/bf518f-ezbrd.c b/board/bf518f-ezbrd/bf518f-ezbrd.c
index 85b350f3ec7..c2ab598d70d 100644
--- a/board/bf518f-ezbrd/bf518f-ezbrd.c
+++ b/board/bf518f-ezbrd/bf518f-ezbrd.c
@@ -61,6 +61,7 @@ static void board_init_enetaddr(uchar *mac_addr)
 #define KSZ_WRITE     0x02
 #define KSZ_READ      0x03
 
+#define KSZ_REG_CHID  0x00	/* Register 0: Chip ID0 */
 #define KSZ_REG_STPID 0x01	/* Register 1: Chip ID1 / Start Switch */
 #define KSZ_REG_GC9   0x0b	/* Register 11: Global Control 9 */
 #define KSZ_REG_P3C0  0x30	/* Register 48: Port 3 Control 0 */
@@ -78,15 +79,17 @@ static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
 	return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
 }
 
-static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
 {
-	int ret = 0;
+	int ret;
 	unsigned char din[3];
+	ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+	return ret ? ret : din[2];
+}
 
-	ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
-	ret |= ksz8893m_reg_set(slave, reg, din[2] & mask);
-
-	return ret;
+static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+{
+	return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
 }
 
 static int ksz8893m_reset(struct spi_slave *slave)
@@ -107,16 +110,16 @@ static int ksz8893m_reset(struct spi_slave *slave)
 
 int board_eth_init(bd_t *bis)
 {
-	static bool switch_is_alive = false;
+	static bool switch_is_alive = false, phy_is_ksz = true;
 	int ret;
 
 	if (!switch_is_alive) {
 		struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
 		if (slave) {
 			if (!spi_claim_bus(slave)) {
-				ret = ksz8893m_reset(slave);
-				if (!ret)
-					switch_is_alive = true;
+				phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
+				ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
+				switch_is_alive = (ret == 0);
 				spi_release_bus(slave);
 			}
 			spi_free_slave(slave);
diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 1e821d9084c..7d20b66d50e 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -63,6 +63,26 @@
 #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
 #define ADI_CMDS_NETWORK	1
 #define CONFIG_BFIN_MAC
+#define CONFIG_BFIN_MAC_PINS \
+	{ \
+	P_MII0_ETxD0, \
+	P_MII0_ETxD1, \
+	P_MII0_ETxD2, \
+	P_MII0_ETxD3, \
+	P_MII0_ETxEN, \
+	P_MII0_TxCLK, \
+	P_MII0_PHYINT, \
+	P_MII0_COL, \
+	P_MII0_ERxD0, \
+	P_MII0_ERxD1, \
+	P_MII0_ERxD2, \
+	P_MII0_ERxD3, \
+	P_MII0_ERxDV, \
+	P_MII0_ERxCLK, \
+	P_MII0_CRS, \
+	P_MII0_MDC, \
+	P_MII0_MDIO, \
+	0 }
 #define CONFIG_NETCONSOLE	1
 #define CONFIG_NET_MULTI	1
 #endif
-- 
cgit v1.3.1


From 787e343b91be62375001b80ee8b70f1594fdfc57 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Tue, 8 Jun 2010 16:18:00 -0400
Subject: Blackfin: unify default I2C settings for ADI boards

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Acked-by: Heiko Schocher <hs@denx.de>
---
 include/configs/bf518f-ezbrd.h    |  2 --
 include/configs/bf526-ezbrd.h     |  2 --
 include/configs/bf527-ezkit.h     |  2 --
 include/configs/bf533-ezkit.h     |  2 --
 include/configs/bf533-stamp.h     |  2 --
 include/configs/bf537-pnav.h      |  2 --
 include/configs/bf537-stamp.h     |  2 --
 include/configs/bf538f-ezkit.h    |  2 --
 include/configs/bf548-ezkit.h     |  2 --
 include/configs/bf561-ezkit.h     |  2 --
 include/configs/bfin_adi_common.h | 12 ++++++++++++
 include/configs/cm-bf527.h        |  2 --
 include/configs/cm-bf537e.h       |  2 --
 include/configs/cm-bf537u.h       |  2 --
 include/configs/cm-bf548.h        |  2 --
 include/configs/ibf-dsp561.h      |  2 --
 include/configs/tcm-bf518.h       |  2 --
 include/configs/tcm-bf537.h       |  2 --
 18 files changed, 12 insertions(+), 34 deletions(-)

(limited to 'include')

diff --git a/include/configs/bf518f-ezbrd.h b/include/configs/bf518f-ezbrd.h
index 7d20b66d50e..6eec1c91a7e 100644
--- a/include/configs/bf518f-ezbrd.h
+++ b/include/configs/bf518f-ezbrd.h
@@ -137,8 +137,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf526-ezbrd.h b/include/configs/bf526-ezbrd.h
index ecda21689d8..82396d0ed25 100644
--- a/include/configs/bf526-ezbrd.h
+++ b/include/configs/bf526-ezbrd.h
@@ -134,8 +134,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf527-ezkit.h b/include/configs/bf527-ezkit.h
index 7800c3276ae..07e4ce86e12 100644
--- a/include/configs/bf527-ezkit.h
+++ b/include/configs/bf527-ezkit.h
@@ -138,8 +138,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h
index c80ddcabdf2..37a70592f8b 100644
--- a/include/configs/bf533-ezkit.h
+++ b/include/configs/bf533-ezkit.h
@@ -136,8 +136,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 
diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h
index 2ec9c422aa4..02c8bc3c36e 100644
--- a/include/configs/bf533-stamp.h
+++ b/include/configs/bf533-stamp.h
@@ -180,8 +180,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 
diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h
index cf40d06b886..8daebc88467 100644
--- a/include/configs/bf537-pnav.h
+++ b/include/configs/bf537-pnav.h
@@ -155,8 +155,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 
 
 /*
diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index cba4ac05481..35928627d83 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h
@@ -137,8 +137,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h
index 59e05650ec1..1c14b6bdd37 100644
--- a/include/configs/bf538f-ezkit.h
+++ b/include/configs/bf538f-ezkit.h
@@ -134,8 +134,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf548-ezkit.h b/include/configs/bf548-ezkit.h
index f9c97114ad0..60cca0c07a3 100644
--- a/include/configs/bf548-ezkit.h
+++ b/include/configs/bf548-ezkit.h
@@ -140,8 +140,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h
index 1e3fdef64a3..036bfe412fa 100644
--- a/include/configs/bf561-ezkit.h
+++ b/include/configs/bf561-ezkit.h
@@ -151,8 +151,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 
diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 82daeb10006..57a73098fce 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -251,6 +251,18 @@
 # define CONFIG_NET_RETRY_COUNT 20
 #endif
 
+/*
+ * I2C Settings
+ */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# ifndef CONFIG_SYS_I2C_SPEED
+#  define CONFIG_SYS_I2C_SPEED 50000
+# endif
+# ifndef CONFIG_SYS_I2C_SLAVE
+#  define CONFIG_SYS_I2C_SLAVE 0
+# endif
+#endif
+
 /*
  * Misc Settings
  */
diff --git a/include/configs/cm-bf527.h b/include/configs/cm-bf527.h
index ad1dd129640..e0c6d53b2c7 100644
--- a/include/configs/cm-bf527.h
+++ b/include/configs/cm-bf527.h
@@ -117,8 +117,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/cm-bf537e.h b/include/configs/cm-bf537e.h
index 8d0bc1232f0..742df9c0199 100644
--- a/include/configs/cm-bf537e.h
+++ b/include/configs/cm-bf537e.h
@@ -119,8 +119,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
index bbea3ab0099..9def99f7283 100644
--- a/include/configs/cm-bf537u.h
+++ b/include/configs/cm-bf537u.h
@@ -120,8 +120,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/cm-bf548.h b/include/configs/cm-bf548.h
index 93c4c8ddc1a..63b9399e142 100644
--- a/include/configs/cm-bf548.h
+++ b/include/configs/cm-bf548.h
@@ -107,8 +107,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/ibf-dsp561.h b/include/configs/ibf-dsp561.h
index 5601416fafe..2c0a263da29 100644
--- a/include/configs/ibf-dsp561.h
+++ b/include/configs/ibf-dsp561.h
@@ -138,8 +138,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 #endif
 
 
diff --git a/include/configs/tcm-bf518.h b/include/configs/tcm-bf518.h
index 9c04d8a28e7..52055e80dcb 100644
--- a/include/configs/tcm-bf518.h
+++ b/include/configs/tcm-bf518.h
@@ -106,8 +106,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
diff --git a/include/configs/tcm-bf537.h b/include/configs/tcm-bf537.h
index 409a042d051..24ce8f854a1 100644
--- a/include/configs/tcm-bf537.h
+++ b/include/configs/tcm-bf537.h
@@ -120,8 +120,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*
-- 
cgit v1.3.1


From 8278b870fce8953e72f092b82dcddcc940a38c7b Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Sun, 13 Jun 2010 12:47:52 -0400
Subject: Blackfin: enable IP defrag for ADI boards

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bfin_adi_common.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 57a73098fce..901a32fb725 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h
@@ -248,6 +248,7 @@
 #   define CONFIG_SYS_AUTOLOAD "no"
 #  endif
 # endif
+# define CONFIG_IP_DEFRAG
 # define CONFIG_NET_RETRY_COUNT 20
 #endif
 
-- 
cgit v1.3.1


From 37aac2d30cb013ab1e9d166eba8bbd9e5fe0bb96 Mon Sep 17 00:00:00 2001
From: Michael Hennerich <michael.hennerich@analog.com>
Date: Mon, 31 May 2010 14:11:53 +0000
Subject: Blackfin: bf527-ad7160-eval: new board support

Support the new AD7160 eval board.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 MAINTAINERS                                 |   2 +
 MAKEALL                                     |   1 +
 board/bf527-ad7160-eval/Makefile            |  54 ++++++++++
 board/bf527-ad7160-eval/bf527-ad7160-eval.c |  25 +++++
 board/bf527-ad7160-eval/config.mk           |  33 +++++++
 boards.cfg                                  |   1 +
 include/configs/bf527-ad7160-eval.h         | 148 ++++++++++++++++++++++++++++
 7 files changed, 264 insertions(+)
 create mode 100644 board/bf527-ad7160-eval/Makefile
 create mode 100644 board/bf527-ad7160-eval/bf527-ad7160-eval.c
 create mode 100644 board/bf527-ad7160-eval/config.mk
 create mode 100644 include/configs/bf527-ad7160-eval.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 94850702ea7..7e66e8d4944 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -998,6 +998,8 @@ Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 	BF548-EZKIT	BF548
 	BF561-EZKIT	BF561
 
+	BF527-AD7160-EVAL	BF527
+
 Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
 Blackfin Team <u-boot-devel@blackfin.uclinux.org>
 
diff --git a/MAKEALL b/MAKEALL
index 463739069d3..ebd0ddc7c9a 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -892,6 +892,7 @@ LIST_avr32="		\
 LIST_blackfin="		\
 	bf518f-ezbrd	\
 	bf526-ezbrd	\
+	bf527-ad7160-eval	\
 	bf527-ezkit	\
 	bf527-ezkit-v2	\
 	bf533-ezkit	\
diff --git a/board/bf527-ad7160-eval/Makefile b/board/bf527-ad7160-eval/Makefile
new file mode 100644
index 00000000000..f2bd2c247d4
--- /dev/null
+++ b/board/bf527-ad7160-eval/Makefile
@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/bf527-ad7160-eval/bf527-ad7160-eval.c b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
new file mode 100644
index 00000000000..b06d5ab2e86
--- /dev/null
+++ b/board/bf527-ad7160-eval/bf527-ad7160-eval.c
@@ -0,0 +1,25 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/mach-common/bits/pll.h>
+
+int checkboard(void)
+{
+	printf("Board: ADI BF527 AD7160-EVAL board\n");
+	printf("       Support: http://blackfin.uclinux.org/\n");
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	/* CLKIN Buffer Output Enable */
+	*pVR_CTL |= CLKBUFOE;
+	return 0;
+}
diff --git a/board/bf527-ad7160-eval/config.mk b/board/bf527-ad7160-eval/config.mk
new file mode 100644
index 00000000000..f85bef5e2a7
--- /dev/null
+++ b/board/bf527-ad7160-eval/config.mk
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
diff --git a/boards.cfg b/boards.cfg
index da31c3647e9..18008b5869c 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -282,6 +282,7 @@ favr-32-ezkit	avr32	at32ap		-		earthlcd	at32ap700x
 hammerhead	avr32	at32ap		-		miromico	at32ap700x
 bf518f-ezbrd	blackfin	blackfin
 bf526-ezbrd	blackfin	blackfin
+bf527-ad7160-eval blackfin	blackfin
 bf527-ezkit	blackfin	blackfin
 bf533-ezkit	blackfin	blackfin
 bf533-stamp	blackfin	blackfin
diff --git a/include/configs/bf527-ad7160-eval.h b/include/configs/bf527-ad7160-eval.h
new file mode 100644
index 00000000000..eb3a2b7dc11
--- /dev/null
+++ b/include/configs/bf527-ad7160-eval.h
@@ -0,0 +1,148 @@
+/*
+ * U-boot - Configuration file for BF527 AD7160-EVAL board
+ */
+
+#ifndef __CONFIG_BF527_AD7160_EVAL_H__
+#define __CONFIG_BF527_AD7160_EVAL_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf527-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_SPI_MASTER
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			24000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			25
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	10
+#define CONFIG_MEM_SIZE		64
+
+#define CONFIG_EBIU_SDRRC_VAL	0x03F6
+#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)
+
+#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(640 * 1024)
+
+
+/*
+ * NAND Settings
+ * (can't be used same time as ethernet)
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+# define CONFIG_BFIN_NFC
+# define CONFIG_BFIN_NFC_BOOTROM_ECC
+#endif
+#ifdef CONFIG_BFIN_NFC
+#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
+#define CONFIG_DRIVER_NAND_BFIN
+#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS		1
+#endif
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	259
+
+
+/*
+ * SPI Settings
+ */
+#define CONFIG_BFIN_SPI
+#define CONFIG_ENV_SPI_MAX_HZ	30000000
+#define CONFIG_SF_DEFAULT_SPEED	30000000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+
+
+/*
+ * Env Storage Settings
+ */
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_OFFSET	0x10000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x10000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	0x40000
+#define CONFIG_ENV_SIZE		0x20000
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x2000
+#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+
+
+/*
+ * SPI_MMC Settings
+ */
+#define CONFIG_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_SPI_MMC
+#define CONFIG_SPI_MMC_DEFAULT_CS (7 + GPIO_PH3)
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_MISC_INIT_R
+#define CONFIG_UART_CONSOLE	0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#endif
-- 
cgit v1.3.1


From d013d1a2ec77ffd0752f098212069985024c8661 Mon Sep 17 00:00:00 2001
From: Mike Frysinger <vapier@gentoo.org>
Date: Mon, 5 Jul 2010 05:15:59 -0400
Subject: Blackfin: bf561-acvilon: drop unused env redund define

The SPI env code didn't support redundant environments until recently, but
this code was written before that.  Since it has never been tested (and
currently causes a build failure), simply punt it.  If the functionality
is actually desired, it can be re-added once it has been tested.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
---
 include/configs/bf561-acvilon.h | 1 -
 1 file changed, 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/bf561-acvilon.h b/include/configs/bf561-acvilon.h
index 0be170c3ee8..44854c79a27 100644
--- a/include/configs/bf561-acvilon.h
+++ b/include/configs/bf561-acvilon.h
@@ -131,7 +131,6 @@
 #define CONFIG_ENV_SECT_SIZE		(1056 * 8)
 #define CONFIG_ENV_OFFSET			((16 + 256) * 1056)
 #define CONFIG_ENV_SIZE				(8 * 1056)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 
 
 /*
-- 
cgit v1.3.1