From d972192520af6db45b502130b5b1e2dfb21b89a1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 26 Oct 2023 14:31:16 -0400 Subject: env: Move env_set() out of cmd/nvedit.c and in to env/common.c Inside of env/common.c we already have our helper env_set_xxx functions, and even have a comment that explains why env_set() itself wasn't moved. We now handle that move. This requires that we rename the previous _do_env_set() to env_do_env_set() and note it as an internal env function. Add comments about this function to explain why we do this when we add the prototype. Add a new function, env_inc_id() to allow for the counter to be updated by both commands and callers, and document this as well by the prototype. Signed-off-by: Tom Rini --- include/env.h | 8 ++++++++ include/env_internal.h | 12 ++++++++++++ 2 files changed, 20 insertions(+) (limited to 'include') diff --git a/include/env.h b/include/env.h index 430c4fa94a4..9778e3e4f2c 100644 --- a/include/env.h +++ b/include/env.h @@ -72,6 +72,14 @@ enum env_redund_flags { */ int env_get_id(void); +/** + * env_inc_id() - Increase the sequence number for the environment + * + * Increment the value that is used by env_get_id() to inform callers + * if the environment has changed since they last checked. + */ +void env_inc_id(void); + /** * env_init() - Set up the pre-relocation environment * diff --git a/include/env_internal.h b/include/env_internal.h index 6a694946468..ae7816d38e5 100644 --- a/include/env_internal.h +++ b/include/env_internal.h @@ -193,6 +193,18 @@ struct env_driver { extern struct hsearch_data env_htab; +/** + * env_do_env_set() - Perform the actual setting of an environment variable + * + * Due to the number of places we may need to set an environmental variable + * from we have an exposed internal function that performs the real work and + * then call this from both the command line function as well as other + * locations. + * + * Return: 0 on success or 1 on failure + */ +int env_do_env_set(int flag, int argc, char *const argv[], int env_flag); + /** * env_ext4_get_intf() - Provide the interface for env in EXT4 * -- cgit v1.3.1 From d563bb5d167dbb8630ececbb35e9cdbef0ddb4be Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Thu, 26 Oct 2023 14:31:36 -0400 Subject: clk_k210.c: Clean up how we handle nop Now that sandbox has and defines nop() there we should include that in our driver for clarity and then remove our local nop() from . Reviewed-by: Sean Anderson Signed-off-by: Tom Rini --- drivers/clk/clk_k210.c | 1 + include/k210/pll.h | 3 --- 2 files changed, 1 insertion(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/clk/clk_k210.c b/drivers/clk/clk_k210.c index c534cc07e09..b9469b93853 100644 --- a/drivers/clk/clk_k210.c +++ b/drivers/clk/clk_k210.c @@ -16,6 +16,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/include/k210/pll.h b/include/k210/pll.h index fd16a89cb20..175c47f6f23 100644 --- a/include/k210/pll.h +++ b/include/k210/pll.h @@ -16,9 +16,6 @@ struct k210_pll_config { #ifdef CONFIG_UNIT_TEST TEST_STATIC int k210_pll_calc_config(u32 rate, u32 rate_in, struct k210_pll_config *best); -#ifndef nop -#define nop() -#endif #endif #endif /* K210_PLL_H */ -- cgit v1.3.1 From 2a7ea650374c5da7e07dbd8a2d05bfc2eef292e5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:05 -0400 Subject: m68k: Remove CONFIG_FSLDMAFEC There are no platforms which enable this feature, so remove it. Signed-off-by: Tom Rini --- arch/m68k/include/asm/fsl_mcdmafec.h | 151 --- arch/m68k/include/asm/immap.h | 15 - arch/m68k/lib/fec.c | 4 +- drivers/dma/Kconfig | 1 - drivers/dma/MCD_dmaApi.c | 1010 -------------- drivers/dma/MCD_tasks.c | 2413 ---------------------------------- drivers/dma/MCD_tasksInit.c | 225 ---- drivers/dma/Makefile | 1 - drivers/net/Kconfig | 8 - drivers/net/Makefile | 1 - drivers/net/fsl_mcdmafec.c | 592 --------- include/MCD_dma.h | 369 ------ include/MCD_progCheck.h | 10 - include/MCD_tasksInit.h | 43 - 14 files changed, 2 insertions(+), 4841 deletions(-) delete mode 100644 arch/m68k/include/asm/fsl_mcdmafec.h delete mode 100644 drivers/dma/MCD_dmaApi.c delete mode 100644 drivers/dma/MCD_tasks.c delete mode 100644 drivers/dma/MCD_tasksInit.c delete mode 100644 drivers/net/fsl_mcdmafec.c delete mode 100644 include/MCD_dma.h delete mode 100644 include/MCD_progCheck.h delete mode 100644 include/MCD_tasksInit.h (limited to 'include') diff --git a/arch/m68k/include/asm/fsl_mcdmafec.h b/arch/m68k/include/asm/fsl_mcdmafec.h deleted file mode 100644 index de6c548fafd..00000000000 --- a/arch/m68k/include/asm/fsl_mcdmafec.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * fsl_mcdmafec.h -- Multi-channel DMA Fast Ethernet Controller definitions - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef fsl_mcdmafec_h -#define fsl_mcdmafec_h - -/* Re-use of the definitions */ -#include - -typedef struct fecdma { - u32 rsvd0; /* 0x000 */ - u32 eir; /* 0x004 */ - u32 eimr; /* 0x008 */ - u32 rsvd1[6]; /* 0x00C - 0x023 */ - u32 ecr; /* 0x024 */ - u32 rsvd2[6]; /* 0x028 - 0x03F */ - u32 mmfr; /* 0x040 */ - u32 mscr; /* 0x044 */ - u32 rsvd3[7]; /* 0x048 - 0x063 */ - u32 mibc; /* 0x064 */ - u32 rsvd4[7]; /* 0x068 - 0x083 */ - u32 rcr; /* 0x084 */ - u32 rhr; /* 0x088 */ - u32 rsvd5[14]; /* 0x08C - 0x0C3 */ - u32 tcr; /* 0x0C4 */ - u32 rsvd6[7]; /* 0x0C8 - 0x0E3 */ - u32 palr; /* 0x0E4 */ - u32 paur; /* 0x0E8 */ - u32 opd; /* 0x0EC */ - u32 rsvd7[10]; /* 0x0F0 - 0x117 */ - u32 iaur; /* 0x118 */ - u32 ialr; /* 0x11C */ - u32 gaur; /* 0x120 */ - u32 galr; /* 0x124 */ - u32 rsvd8[7]; /* 0x128 - 0x143 */ - u32 tfwr; /* 0x144 */ - u32 rsvd9[14]; /* 0x148 - 0x17F */ - u32 fmc; /* 0x180 */ - u32 rfdr; /* 0x184 */ - u32 rfsr; /* 0x188 */ - u32 rfcr; /* 0x18C */ - u32 rlrfp; /* 0x190 */ - u32 rlwfp; /* 0x194 */ - u32 rfar; /* 0x198 */ - u32 rfrp; /* 0x19C */ - u32 rfwp; /* 0x1A0 */ - u32 tfdr; /* 0x1A4 */ - u32 tfsr; /* 0x1A8 */ - u32 tfcr; /* 0x1AC */ - u32 tlrfp; /* 0x1B0 */ - u32 tlwfp; /* 0x1B4 */ - u32 tfar; /* 0x1B8 */ - u32 tfrp; /* 0x1BC */ - u32 tfwp; /* 0x1C0 */ - u32 frst; /* 0x1C4 */ - u32 ctcwr; /* 0x1C8 */ -} fecdma_t; - -struct fec_info_dma { - int index; - u32 iobase; - u32 pinmux; - u32 miibase; - int phy_addr; - int dup_spd; - char *phy_name; - int phyname_init; - cbd_t *rxbd; /* Rx BD */ - cbd_t *txbd; /* Tx BD */ - uint rx_idx; - uint tx_idx; - char *txbuf; - int initialized; - struct fec_info_dma *next; - u16 rx_task; /* DMA receive Task Number */ - u16 tx_task; /* DMA Transmit Task Number */ - u16 rx_pri; /* DMA Receive Priority */ - u16 tx_pri; /* DMA Transmit Priority */ - u16 rx_init; /* DMA Receive Initiator */ - u16 tx_init; /* DMA Transmit Initiator */ - u16 used_tbd_idx; /* next transmit BD to clean */ - u16 clean_tbd_num; /* the number of available transmit BDs */ - int to_loop; - struct mii_dev *bus; -}; - -/* Bit definitions and macros for IEVENT */ -#define FEC_EIR_TXERR (0x00040000) -#define FEC_EIR_RXERR (0x00020000) -#undef FEC_EIR_CLEAR_ALL -#define FEC_EIR_CLEAR_ALL (0xFFFE0000) - -/* Bit definitions and macros for R_HASH */ -#define FEC_RHASH_FCE_DC (0x80000000) -#define FEC_RHASH_MULTCAST (0x40000000) -#define FEC_RHASH_HASH(x) (((x)&0x0000003F)<<24) - -/* Bit definitions and macros for FEC_TFWR */ -#undef FEC_TFWR_X_WMRK -#undef FEC_TFWR_X_WMRK_64 -#undef FEC_TFWR_X_WMRK_128 -#undef FEC_TFWR_X_WMRK_192 - -#define FEC_TFWR_X_WMRK(x) ((x)&0x0F) -#define FEC_TFWR_X_WMRK_64 (0x00) -#define FEC_TFWR_X_WMRK_128 (0x01) -#define FEC_TFWR_X_WMRK_192 (0x02) -#define FEC_TFWR_X_WMRK_256 (0x03) -#define FEC_TFWR_X_WMRK_320 (0x04) -#define FEC_TFWR_X_WMRK_384 (0x05) -#define FEC_TFWR_X_WMRK_448 (0x06) -#define FEC_TFWR_X_WMRK_512 (0x07) -#define FEC_TFWR_X_WMRK_576 (0x08) -#define FEC_TFWR_X_WMRK_640 (0x09) -#define FEC_TFWR_X_WMRK_704 (0x0A) -#define FEC_TFWR_X_WMRK_768 (0x0B) -#define FEC_TFWR_X_WMRK_832 (0x0C) -#define FEC_TFWR_X_WMRK_896 (0x0D) -#define FEC_TFWR_X_WMRK_960 (0x0E) -#define FEC_TFWR_X_WMRK_1024 (0x0F) - -/* FIFO definitions */ -/* Bit definitions and macros for FSTAT */ -#define FIFO_STAT_IP (0x80000000) -#define FIFO_STAT_FRAME(x) (((x)&0x0000000F)<<24) -#define FIFO_STAT_FAE (0x00800000) -#define FIFO_STAT_RXW (0x00400000) -#define FIFO_STAT_UF (0x00200000) -#define FIFO_STAT_OF (0x00100000) -#define FIFO_STAT_FR (0x00080000) -#define FIFO_STAT_FULL (0x00040000) -#define FIFO_STAT_ALARM (0x00020000) -#define FIFO_STAT_EMPTY (0x00010000) - -/* Bit definitions and macros for FCTRL */ -#define FIFO_CTRL_WCTL (0x40000000) -#define FIFO_CTRL_WFR (0x20000000) -#define FIFO_CTRL_FRAME (0x08000000) -#define FIFO_CTRL_GR(x) (((x)&0x00000007)<<24) -#define FIFO_CTRL_IPMASK (0x00800000) -#define FIFO_CTRL_FAEMASK (0x00400000) -#define FIFO_CTRL_RXWMASK (0x00200000) -#define FIFO_CTRL_UFMASK (0x00100000) -#define FIFO_CTRL_OFMASK (0x00080000) - -#endif /* fsl_mcdmafec_h */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index 411b00899c2..b118a917542 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -314,21 +314,6 @@ #include #include -#ifdef CONFIG_FSLDMAFEC -#define FEC0_RX_TASK 0 -#define FEC0_TX_TASK 1 -#define FEC0_RX_PRIORITY 6 -#define FEC0_TX_PRIORITY 7 -#define FEC0_RX_INIT 16 -#define FEC0_TX_INIT 17 -#define FEC1_RX_TASK 2 -#define FEC1_TX_TASK 3 -#define FEC1_RX_PRIORITY 6 -#define FEC1_TX_PRIORITY 7 -#define FEC1_RX_INIT 30 -#define FEC1_TX_INIT 31 -#endif - #define CFG_SYS_UART_BASE (MMAP_UART0 + (CFG_SYS_UART_PORT * 0x100)) #ifdef CONFIG_SLTTMR diff --git a/arch/m68k/lib/fec.c b/arch/m68k/lib/fec.c index d6f238e4b34..ac36aec0ed7 100644 --- a/arch/m68k/lib/fec.c +++ b/arch/m68k/lib/fec.c @@ -10,7 +10,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_MCFFEC) || defined(CONFIG_FSLDMAFEC) +#if defined(CONFIG_MCFFEC) static int fec_get_node(int fec_idx) { char fec_alias[5] = {"fec"}; @@ -77,4 +77,4 @@ int fec_get_mii_base(int fec_idx, u32 *mii_base) return fec_get_fdt_prop(fec_idx, "mii-base", mii_base); } -#endif //CONFIG_MCFFEC || CONFIG_FSLDMAFEC +#endif //CONFIG_MCFFEC diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 0af54604211..3c64e894646 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -87,7 +87,6 @@ endif config DMA_LEGACY bool "Legacy DMA support" - default y if FSLDMAFEC help Enable legacy DMA support. This does not use driver model and should be migrated to the new API. diff --git a/drivers/dma/MCD_dmaApi.c b/drivers/dma/MCD_dmaApi.c deleted file mode 100644 index af0e1345220..00000000000 --- a/drivers/dma/MCD_dmaApi.c +++ /dev/null @@ -1,1010 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -/*Main C file for multi-channel DMA API. */ - -#include - -#include -#include -#include - -/********************************************************************/ -/* This is an API-internal pointer to the DMA's registers */ -dmaRegs *MCD_dmaBar; - -/* - * These are the real and model task tables as generated by the - * build process - */ -extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS]; -extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS]; - -/* - * However, this (usually) gets relocated to on-chip SRAM, at which - * point we access them as these tables - */ -volatile TaskTableEntry *MCD_taskTable; -TaskTableEntry *MCD_modelTaskTable; - -/* - * MCD_chStatus[] is an array of status indicators for remembering - * whether a DMA has ever been attempted on each channel, pausing - * status, etc. - */ -static int MCD_chStatus[NCHANNELS] = { - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, - MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA -}; - -/* Prototypes for local functions */ -static void MCD_memcpy(int *dest, int *src, u32 size); -static void MCD_resmActions(int channel); - -/* - * Buffer descriptors used for storage of progress info for single Dmas - * Also used as storage for the DMA for CRCs for single DMAs - * Otherwise, the DMA does not parse these buffer descriptors - */ -#ifdef MCD_INCLUDE_EU -extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#else -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif -MCD_bufDesc *MCD_relocBuffDesc; - -/* Defines for the debug control register's functions */ -#define DBG_CTL_COMP1_TASK (0x00002000) -#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_BREAK | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \ - DBG_CTL_INT_BREAK | \ - DBG_CTL_COMP1_TASK) -#define DBG_KILL_ALL_STAT (0xFFFFFFFF) - -/* Offset to context save area where progress info is stored */ -#define CSAVE_OFFSET 10 - -/* Defines for Byte Swapping */ -#define MCD_BYTE_SWAP_KILLER 0xFFF8888F -#define MCD_NO_BYTE_SWAP_ATALL 0x00040000 - -/* Execution Unit Identifiers */ -#define MAC 0 /* legacy - not used */ -#define LUAC 1 /* legacy - not used */ -#define CRC 2 /* legacy - not used */ -#define LURC 3 /* Logic Unit with CRC */ - -/* Task Identifiers */ -#define TASK_CHAINNOEU 0 -#define TASK_SINGLENOEU 1 -#ifdef MCD_INCLUDE_EU -#define TASK_CHAINEU 2 -#define TASK_SINGLEEU 3 -#define TASK_FECRX 4 -#define TASK_FECTX 5 -#else -#define TASK_CHAINEU 0 -#define TASK_SINGLEEU 1 -#define TASK_FECRX 2 -#define TASK_FECTX 3 -#endif - -/* - * Structure to remember which variant is on which channel - * TBD- need this? - */ -typedef struct MCD_remVariants_struct MCD_remVariant; -struct MCD_remVariants_struct { - int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */ - int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */ - s16 remDestIncr[NCHANNELS]; /* DestIncr */ - s16 remSrcIncr[NCHANNELS]; /* srcIncr */ - u32 remXferSize[NCHANNELS]; /* xferSize */ -}; - -/* Structure to remember the startDma parameters for each channel */ -MCD_remVariant MCD_remVariants; -/********************************************************************/ -/* Function: MCD_initDma - * Purpose: Initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task - * structures, and setting up some global settings - * Arguments: - * dmaBarAddr - pointer to the multichannel DMA registers - * taskTableDest - location to move DMA task code and structs to - * flags - operational parameters - * Return Value: - * MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned - * MCD_OK otherwise - */ -extern u32 MCD_funcDescTab0[]; - -int MCD_initDma(dmaRegs * dmaBarAddr, void *taskTableDest, u32 flags) -{ - int i; - TaskTableEntry *entryPtr; - - /* setup the local pointer to register set */ - MCD_dmaBar = dmaBarAddr; - - /* do we need to move/create a task table */ - if ((flags & MCD_RELOC_TASKS) != 0) { - int fixedSize; - u32 *fixedPtr; - /*int *tablePtr = taskTableDest;TBD */ - int varTabsOffset, funcDescTabsOffset, contextSavesOffset; - int taskDescTabsOffset; - int taskTableSize, varTabsSize, funcDescTabsSize, - contextSavesSize; - int taskDescTabSize; - - int i; - - /* check if physical address is aligned on 512 byte boundary */ - if (((u32) taskTableDest & 0x000001ff) != 0) - return (MCD_TABLE_UNALIGNED); - - /* set up local pointer to task Table */ - MCD_taskTable = taskTableDest; - - /* - * Create a task table: - * - compute aligned base offsets for variable tables and - * function descriptor tables, then - * - loop through the task table and setup the pointers - * - copy over model task table with the the actual task - * descriptor tables - */ - - taskTableSize = NCHANNELS * sizeof(TaskTableEntry); - /* align variable tables to size */ - varTabsOffset = taskTableSize + (u32) taskTableDest; - if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0) - varTabsOffset = - (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE); - /* align function descriptor tables */ - varTabsSize = NCHANNELS * VAR_TAB_SIZE; - funcDescTabsOffset = varTabsOffset + varTabsSize; - - if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0) - funcDescTabsOffset = - (funcDescTabsOffset + - FUNCDESC_TAB_SIZE) & (~FUNCDESC_TAB_SIZE); - - funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE; - contextSavesOffset = funcDescTabsOffset + funcDescTabsSize; - contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE); - fixedSize = - taskTableSize + varTabsSize + funcDescTabsSize + - contextSavesSize; - - /* zero the thing out */ - fixedPtr = (u32 *) taskTableDest; - for (i = 0; i < (fixedSize / 4); i++) - fixedPtr[i] = 0; - - entryPtr = (TaskTableEntry *) MCD_taskTable; - /* set up fixed pointers */ - for (i = 0; i < NCHANNELS; i++) { - /* update ptr to local value */ - entryPtr[i].varTab = (u32) varTabsOffset; - entryPtr[i].FDTandFlags = - (u32) funcDescTabsOffset | MCD_TT_FLAGS_DEF; - entryPtr[i].contextSaveSpace = (u32) contextSavesOffset; - varTabsOffset += VAR_TAB_SIZE; -#ifdef MCD_INCLUDE_EU - /* if not there is only one, just point to the - same one */ - funcDescTabsOffset += FUNCDESC_TAB_SIZE; -#endif - contextSavesOffset += CONTEXT_SAVE_SIZE; - } - /* copy over the function descriptor table */ - for (i = 0; i < FUNCDESC_TAB_NUM; i++) { - MCD_memcpy((void *)(entryPtr[i]. - FDTandFlags & ~MCD_TT_FLAGS_MASK), - (void *)MCD_funcDescTab0, FUNCDESC_TAB_SIZE); - } - - /* copy model task table to where the context saves stuff - leaves off */ - MCD_modelTaskTable = (TaskTableEntry *) contextSavesOffset; - - MCD_memcpy((void *)MCD_modelTaskTable, - (void *)MCD_modelTaskTableSrc, - NUMOFVARIANTS * sizeof(TaskTableEntry)); - - /* point to local version of model task table */ - entryPtr = MCD_modelTaskTable; - taskDescTabsOffset = (u32) MCD_modelTaskTable + - (NUMOFVARIANTS * sizeof(TaskTableEntry)); - - /* copy actual task code and update TDT ptrs in local - model task table */ - for (i = 0; i < NUMOFVARIANTS; i++) { - taskDescTabSize = - entryPtr[i].TDTend - entryPtr[i].TDTstart + 4; - MCD_memcpy((void *)taskDescTabsOffset, - (void *)entryPtr[i].TDTstart, - taskDescTabSize); - entryPtr[i].TDTstart = (u32) taskDescTabsOffset; - taskDescTabsOffset += taskDescTabSize; - entryPtr[i].TDTend = (u32) taskDescTabsOffset - 4; - } -#ifdef MCD_INCLUDE_EU - /* Tack single DMA BDs onto end of code so API controls - where they are since DMA might write to them */ - MCD_relocBuffDesc = - (MCD_bufDesc *) (entryPtr[NUMOFVARIANTS - 1].TDTend + 4); -#else - /* DMA does not touch them so they can be wherever and we - don't need to waste SRAM on them */ - MCD_relocBuffDesc = MCD_singleBufDescs; -#endif - } else { - /* point the would-be relocated task tables and the - buffer descriptors to the ones the linker generated */ - - if (((u32) MCD_realTaskTableSrc & 0x000001ff) != 0) - return (MCD_TABLE_UNALIGNED); - - /* need to add code to make sure that every thing else is - aligned properly TBD. this is problematic if we init - more than once or after running tasks, need to add - variable to see if we have aleady init'd */ - entryPtr = MCD_realTaskTableSrc; - for (i = 0; i < NCHANNELS; i++) { - if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) || - ((entryPtr[i]. - FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0)) - return (MCD_TABLE_UNALIGNED); - } - - MCD_taskTable = MCD_realTaskTableSrc; - MCD_modelTaskTable = MCD_modelTaskTableSrc; - MCD_relocBuffDesc = MCD_singleBufDescs; - } - - /* Make all channels as totally inactive, and remember them as such: */ - - MCD_dmaBar->taskbar = (u32) MCD_taskTable; - for (i = 0; i < NCHANNELS; i++) { - MCD_dmaBar->taskControl[i] = 0x0; - MCD_chStatus[i] = MCD_NO_DMA; - } - - /* Set up pausing mechanism to inactive state: */ - /* no particular values yet for either comparator registers */ - MCD_dmaBar->debugComp1 = 0; - MCD_dmaBar->debugComp2 = 0; - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT; - - /* enable or disable commbus prefetch, really need an ifdef or - something to keep from trying to set this in the 8220 */ - if ((flags & MCD_COMM_PREFETCH_EN) != 0) - MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH; - else - MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH; - - return (MCD_OK); -} - -/*********************** End of MCD_initDma() ***********************/ - -/********************************************************************/ -/* Function: MCD_dmaStatus - * Purpose: Returns the status of the DMA on the requested channel - * Arguments: channel - channel number - * Returns: Predefined status indicators - */ -int MCD_dmaStatus(int channel) -{ - u16 tcrValue; - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - tcrValue = MCD_dmaBar->taskControl[channel]; - if ((tcrValue & TASK_CTL_EN) == 0) { /* nothing running */ - /* if last reported with task enabled */ - if (MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) - MCD_chStatus[channel] = MCD_DONE; - } else { /* something is running */ - - /* There are three possibilities: paused, running or idle. */ - if (MCD_chStatus[channel] == MCD_RUNNING - || MCD_chStatus[channel] == MCD_IDLE) { - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; - /* This register is selected to know which initiator is - actually asserted. */ - if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; - /* do not change the status if it is already paused. */ - } - } - return MCD_chStatus[channel]; -} - -/******************** End of MCD_dmaStatus() ************************/ - -/********************************************************************/ -/* Function: MCD_startDma - * Ppurpose: Starts a particular kind of DMA - * Arguments: - * srcAddr - the channel on which to run the DMA - * srcIncr - the address to move data from, or buffer-descriptor address - * destAddr - the amount to increment the source address per transfer - * destIncr - the address to move data to - * dmaSize - the amount to increment the destination address per transfer - * xferSize - the number bytes in of each data movement (1, 2, or 4) - * initiator - what device initiates the DMA - * priority - priority of the DMA - * flags - flags describing the DMA - * funcDesc - description of byte swapping, bit swapping, and CRC actions - * srcAddrVirt - virtual buffer descriptor address TBD - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ - -int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, - s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, - int priority, u32 flags, u32 funcDesc -#ifdef MCD_NEED_ADDR_TRANS - s8 * srcAddrVirt -#endif - ) -{ - int srcRsdIncr, destRsdIncr; - int *cSave; - short xferSizeIncr; - int tcrCount = 0; -#ifdef MCD_INCLUDE_EU - u32 *realFuncArray; -#endif - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - /* tbd - need to determine the proper response to a bad funcDesc when - not including EU functions, for now, assign a benign funcDesc, but - maybe should return an error */ -#ifndef MCD_INCLUDE_EU - funcDesc = MCD_FUNC_NOEU1; -#endif - -#ifdef MCD_DEBUG - printf("startDma:Setting up params\n"); -#endif - /* Set us up for task-wise priority. We don't technically need to do - this on every start, but since the register involved is in the same - longword as other registers that users are in control of, setting - it more than once is probably preferable. That since the - documentation doesn't seem to be completely consistent about the - nature of the PTD control register. */ - MCD_dmaBar->ptdControl |= (u16) 0x8000; - - /* Not sure what we need to keep here rtm TBD */ -#if 1 - /* Calculate additional parameters to the regular DMA calls. */ - srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0); - destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0); - - xferSizeIncr = (xferSize & 0xffff) | 0x20000000; - - /* Remember for each channel which variant is running. */ - MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr; - MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr; - MCD_remVariants.remDestIncr[channel] = destIncr; - MCD_remVariants.remSrcIncr[channel] = srcIncr; - MCD_remVariants.remXferSize[channel] = xferSize; -#endif - - cSave = - (int *)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + - CURRBD; - -#ifdef MCD_INCLUDE_EU - /* may move this to EU specific calls */ - realFuncArray = - (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00); - /* Modify the LURC's normal and byte-residue-loop functions according - to parameter. */ - realFuncArray[(LURC * 16)] = xferSize == 4 ? - funcDesc : xferSize == 2 ? - funcDesc & 0xfffff00f : funcDesc & 0xffff000f; - realFuncArray[(LURC * 16 + 1)] = - (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL; -#endif - /* Write the initiator field in the TCR, and also set the - initiator-hold bit. Note that,due to a hardware quirk, this could - collide with an MDE access to the initiator-register file, so we - have to verify that the write reads back correctly. */ - - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM; - - while (((MCD_dmaBar->taskControl[channel] & 0x1fff) != - ((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) - && (tcrCount < 1000)) { - tcrCount++; - /*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020; */ - MCD_dmaBar->taskControl[channel] = - (initiator << 8) | TASK_CTL_HIPRITSKEN | - TASK_CTL_HLDINITNUM; - } - - MCD_dmaBar->priority[channel] = (u8) priority & PRIORITY_PRI_MASK; - /* should be albe to handle this stuff with only one write to ts reg - - tbd */ - if (channel < 8 && channel >= 0) { - MCD_dmaBar->taskSize0 &= ~(0xf << (7 - channel) * 4); - MCD_dmaBar->taskSize0 |= - (xferSize & 3) << (((7 - channel) * 4) + 2); - MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel) * 4); - } else { - MCD_dmaBar->taskSize1 &= ~(0xf << (15 - channel) * 4); - MCD_dmaBar->taskSize1 |= - (xferSize & 3) << (((15 - channel) * 4) + 2); - MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel) * 4); - } - - /* setup task table flags/options which mostly control the line - buffers */ - MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK; - MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags); - - if (flags & MCD_FECTX_DMA) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_FECTX].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_FECTX].TDTend; - MCD_startDmaENetXmit((char *)srcAddr, (char *)srcAddr, - (char *)destAddr, MCD_taskTable, - channel); - } else if (flags & MCD_FECRX_DMA) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_FECRX].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_FECRX].TDTend; - MCD_startDmaENetRcv((char *)srcAddr, (char *)srcAddr, - (char *)destAddr, MCD_taskTable, - channel); - } else if (flags & MCD_SINGLE_DMA) { - /* this buffer descriptor is used for storing off initial - parameters for later progress query calculation and for the - DMA to write the resulting checksum. The DMA does not use - this to determine how to operate, that info is passed with - the init routine */ - MCD_relocBuffDesc[channel].srcAddr = srcAddr; - MCD_relocBuffDesc[channel].destAddr = destAddr; - - /* definitely not its final value */ - MCD_relocBuffDesc[channel].lastDestAddr = destAddr; - - MCD_relocBuffDesc[channel].dmaSize = dmaSize; - MCD_relocBuffDesc[channel].flags = 0; /* not used */ - MCD_relocBuffDesc[channel].csumResult = 0; /* not used */ - MCD_relocBuffDesc[channel].next = 0; /* not used */ - - /* Initialize the progress-querying stuff to show no - progress: */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET] = -(u32) & (MCD_relocBuffDesc[channel]); - /* tbd - need to keep the user from trying to call the EU - routine when MCD_INCLUDE_EU is not defined */ - if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_SINGLENOEU].TDTend; - MCD_startDmaSingleNoEu((char *)srcAddr, srcIncr, - (char *)destAddr, destIncr, - (int)dmaSize, xferSizeIncr, - flags, (int *) - &(MCD_relocBuffDesc[channel]), - cSave, MCD_taskTable, channel); - } else { - /* TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_SINGLEEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_SINGLEEU].TDTend; - MCD_startDmaSingleEu((char *)srcAddr, srcIncr, - (char *)destAddr, destIncr, - (int)dmaSize, xferSizeIncr, - flags, (int *) - &(MCD_relocBuffDesc[channel]), - cSave, MCD_taskTable, channel); - } - } else { /* chained DMAS */ - /* Initialize the progress-querying stuff to show no - progress: */ -#if 1 - /* (!defined(MCD_NEED_ADDR_TRANS)) */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddr)->srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddr)->destAddr; -#else - /* if using address translation, need the virtual addr of the - first buffdesc */ - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddrVirt)->srcAddr; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET] - = (int)((MCD_bufDesc *) srcAddrVirt)->destAddr; -#endif - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0; - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr; - - if (funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2) { - /*TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_CHAINNOEU].TDTend; - MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, - destIncr, xferSize, - xferSizeIncr, cSave, - MCD_taskTable, channel); - } else { - /*TDTStart and TDTEnd */ - MCD_taskTable[channel].TDTstart = - MCD_modelTaskTable[TASK_CHAINEU].TDTstart; - MCD_taskTable[channel].TDTend = - MCD_modelTaskTable[TASK_CHAINEU].TDTend; - MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, - xferSize, xferSizeIncr, cSave, - MCD_taskTable, channel); - } - } - MCD_chStatus[channel] = MCD_IDLE; - return (MCD_OK); -} - -/************************ End of MCD_startDma() *********************/ - -/********************************************************************/ -/* Function: MCD_XferProgrQuery - * Purpose: Returns progress of DMA on requested channel - * Arguments: channel - channel to retrieve progress for - * progRep - pointer to user supplied MCD_XferProg struct - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * MCD_XferProgrQuery() upon completing or after aborting a DMA, or - * while the DMA is in progress, this function returns the first - * DMA-destination address not (or not yet) used in the DMA. When - * encountering a non-ready buffer descriptor, the information for - * the last completed descriptor is returned. - * - * MCD_XferProgQuery() has to avoid the possibility of getting - * partially-updated information in the event that we should happen - * to query DMA progress just as the DMA is updating it. It does that - * by taking advantage of the fact context is not saved frequently for - * the most part. We therefore read it at least twice until we get the - * same information twice in a row. - * - * Because a small, but not insignificant, amount of time is required - * to write out the progress-query information, especially upon - * completion of the DMA, it would be wise to guarantee some time lag - * between successive readings of the progress-query information. - */ - -/* How many iterations of the loop below to execute to stabilize values */ -#define STABTIME 0 - -int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep) -{ - MCD_XferProg prevRep; - int again; /* true if we are to try again to ge - consistent results */ - int i; /* used as a time-waste counter */ - int destDiffBytes; /* Total no of bytes that we think actually - got xfered. */ - int numIterations; /* number of iterations */ - int bytesNotXfered; /* bytes that did not get xfered. */ - s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr; - int subModVal, addModVal; /* Mode values to added and subtracted - from the final destAddr */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - /* Read a trial value for the progress-reporting values */ - prevRep.lastSrcAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - prevRep.lastDestAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - prevRep.dmaSize = - ((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + - CSAVE_OFFSET]; - prevRep.currBufDesc = - (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* Repeatedly reread those values until they match previous values: */ - do { - /* Waste a little bit of time to ensure stability: */ - for (i = 0; i < STABTIME; i++) { - /* make sure this loop does something so that it - doesn't get optimized out */ - i += i >> 2; - } - /* Check them again: */ - progRep->lastSrcAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[SRCPTR + CSAVE_OFFSET]; - progRep->lastDestAddr = - (s8 *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DESTPTR + CSAVE_OFFSET]; - progRep->dmaSize = - ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[DCOUNT + CSAVE_OFFSET]; - progRep->currBufDesc = - (MCD_bufDesc *) ((volatile int *)MCD_taskTable[channel]. - contextSaveSpace)[CURRBD + CSAVE_OFFSET]; - /* See if they match: */ - if (prevRep.lastSrcAddr != progRep->lastSrcAddr - || prevRep.lastDestAddr != progRep->lastDestAddr - || prevRep.dmaSize != progRep->dmaSize - || prevRep.currBufDesc != progRep->currBufDesc) { - /* If they don't match, remember previous values and - try again: */ - prevRep.lastSrcAddr = progRep->lastSrcAddr; - prevRep.lastDestAddr = progRep->lastDestAddr; - prevRep.dmaSize = progRep->dmaSize; - prevRep.currBufDesc = progRep->currBufDesc; - again = MCD_TRUE; - } else - again = MCD_FALSE; - } while (again == MCD_TRUE); - - /* Update the dCount, srcAddr and destAddr */ - /* To calculate dmaCount, we consider destination address. C - overs M1,P1,Z for destination */ - switch (MCD_remVariants.remDestRsdIncr[channel]) { - case MINUS1: - subModVal = - ((int)progRep-> - lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - - 1); - addModVal = - ((int)progRep->currBufDesc-> - destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - LWAlignedInitDestAddr = - (progRep->currBufDesc->destAddr) - addModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal; - destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr; - bytesNotXfered = - (destDiffBytes / MCD_remVariants.remDestIncr[channel]) * - (MCD_remVariants.remDestIncr[channel] - + MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = - destDiffBytes - bytesNotXfered + addModVal - subModVal; - break; - case ZERO: - progRep->lastDestAddr = progRep->currBufDesc->destAddr; - break; - case PLUS1: - /* This value has to be subtracted from the final - calculated dCount. */ - subModVal = - ((int)progRep->currBufDesc-> - destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1); - /* These bytes are already in lastDestAddr. */ - addModVal = - ((int)progRep-> - lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - - 1); - LWAlignedInitDestAddr = - (progRep->currBufDesc->destAddr) - subModVal; - LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal; - destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr); - numIterations = - (LWAlignedCurrDestAddr - - LWAlignedInitDestAddr) / - MCD_remVariants.remDestIncr[channel]; - bytesNotXfered = - numIterations * (MCD_remVariants.remDestIncr[channel] - - MCD_remVariants.remXferSize[channel]); - progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal; - break; - default: - break; - } - - /* This covers M1,P1,Z for source */ - switch (MCD_remVariants.remSrcRsdIncr[channel]) { - case MINUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - (MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize / MCD_remVariants.remXferSize[channel])); - break; - case ZERO: - progRep->lastSrcAddr = progRep->currBufDesc->srcAddr; - break; - case PLUS1: - progRep->lastSrcAddr = - progRep->currBufDesc->srcAddr + - (MCD_remVariants.remSrcIncr[channel] * - (progRep->dmaSize / MCD_remVariants.remXferSize[channel])); - break; - default: - break; - } - - return (MCD_OK); -} - -/******************* End of MCD_XferProgrQuery() ********************/ - -/********************************************************************/ -/* MCD_resmActions() does the majority of the actions of a DMA resume. - * It is called from MCD_killDma() and MCD_resumeDma(). It has to be - * a separate function because the kill function has to negate the task - * enable before resuming it, but the resume function has to do nothing - * if there is no DMA on that channel (i.e., if the enable bit is 0). - */ -static void MCD_resmActions(int channel) -{ - MCD_dmaBar->debugControl = DBG_CTL_DISABLE; - MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus; - /* This register is selected to know which initiator is - actually asserted. */ - MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; - - if ((MCD_dmaBar->ptdDebug >> channel) & 0x1) - MCD_chStatus[channel] = MCD_RUNNING; - else - MCD_chStatus[channel] = MCD_IDLE; -} - -/********************* End of MCD_resmActions() *********************/ - -/********************************************************************/ -/* Function: MCD_killDma - * Purpose: Halt the DMA on the requested channel, without any - * intention of resuming the DMA. - * Arguments: channel - requested channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * A DMA may be killed from any state, including paused state, and it - * always goes to the MCD_HALTED state even if it is killed while in - * the MCD_NO_DMA or MCD_IDLE states. - */ -int MCD_killDma(int channel) -{ - /* MCD_XferProg progRep; */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] = 0x0; - MCD_resumeDma(channel); - /* - * This must be after the write to the TCR so that the task doesn't - * start up again momentarily, and before the status assignment so - * as to override whatever MCD_resumeDma() may do to the channel - * status. - */ - MCD_chStatus[channel] = MCD_HALTED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - return (MCD_OK); -} - -/************************ End of MCD_killDma() **********************/ - -/********************************************************************/ -/* Function: MCD_continDma - * Purpose: Continue a DMA which as stopped due to encountering an - * unready buffer descriptor. - * Arguments: channel - channel to continue the DMA on - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - * - * Notes: - * This routine does not check to see if there is a task which can - * be continued. Also this routine should not be used with single DMAs. - */ -int MCD_continDma(int channel) -{ - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN; - MCD_chStatus[channel] = MCD_RUNNING; - - return (MCD_OK); -} - -/********************** End of MCD_continDma() **********************/ - -/********************************************************************* - * MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit - * to freeze a task and resume it. We freeze a task by breakpointing - * on the stated task. That is, not any specific place in the task, - * but any time that task executes. In particular, when that task - * executes, we want to freeze that task and only that task. - * - * The bits of the debug control register influence interrupts vs. - * breakpoints as follows: - * - Bits 14 and 0 enable or disable debug functions. If enabled, you - * will get the interrupt but you may or may not get a breakpoint. - * - Bits 2 and 1 decide whether you also get a breakpoint in addition - * to an interrupt. - * - * The debug unit can do these actions in response to either internally - * detected breakpoint conditions from the comparators, or in response - * to the external breakpoint pin, or both. - * - Bits 14 and 1 perform the above-described functions for - * internally-generated conditions, i.e., the debug comparators. - * - Bits 0 and 2 perform the above-described functions for external - * conditions, i.e., the breakpoint external pin. - * - * Note that, although you "always" get the interrupt when you turn - * the debug functions, the interrupt can nevertheless, if desired, be - * masked by the corresponding bit in the PTD's IMR. Note also that - * this means that bits 14 and 0 must enable debug functions before - * bits 1 and 2, respectively, have any effect. - * - * NOTE: It's extremely important to not pause more than one DMA channel - * at a time. - ********************************************************************/ - -/********************************************************************/ -/* Function: MCD_pauseDma - * Purpose: Pauses the DMA on a given channel (if any DMA is running - * on that channel). - * Arguments: channel - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_pauseDma(int channel) -{ - /* MCD_XferProg progRep; */ - - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) { - MCD_dmaBar->debugComp1 = channel; - MCD_dmaBar->debugControl = - DBG_CTL_ENABLE | (1 << (channel + 16)); - MCD_chStatus[channel] = MCD_PAUSED; - - /* - * Update the current buffer descriptor's lastDestAddr field - * - * MCD_XferProgrQuery (channel, &progRep); - * progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr; - */ - } - return (MCD_OK); -} - -/************************* End of MCD_pauseDma() ********************/ - -/********************************************************************/ -/* Function: MCD_resumeDma - * Purpose: Resumes the DMA on a given channel (if any DMA is - * running on that channel). - * Arguments: channel - channel on which to resume DMA - * Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK - */ -int MCD_resumeDma(int channel) -{ - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN) - MCD_resmActions(channel); - - return (MCD_OK); -} - -/************************ End of MCD_resumeDma() ********************/ - -/********************************************************************/ -/* Function: MCD_csumQuery - * Purpose: Provide the checksum after performing a non-chained DMA - * Arguments: channel - channel to report on - * csum - pointer to where to write the checksum/CRC - * Returns: MCD_ERROR if the channel is invalid, else MCD_OK - * - * Notes: - * - */ -int MCD_csumQuery(int channel, u32 * csum) -{ -#ifdef MCD_INCLUDE_EU - if ((channel < 0) || (channel >= NCHANNELS)) - return (MCD_CHANNEL_INVALID); - - *csum = MCD_relocBuffDesc[channel].csumResult; - return (MCD_OK); -#else - return (MCD_ERROR); -#endif -} - -/*********************** End of MCD_resumeDma() *********************/ - -/********************************************************************/ -/* Function: MCD_getCodeSize - * Purpose: Provide the size requirements of the microcoded tasks - * Returns: Size in bytes - */ -int MCD_getCodeSize(void) -{ -#ifdef MCD_INCLUDE_EU - return (0x2b5c); -#else - return (0x173c); -#endif -} - -/********************** End of MCD_getCodeSize() ********************/ - -/********************************************************************/ -/* Function: MCD_getVersion - * Purpose: Provide the version string and number - * Arguments: longVersion - user supplied pointer to a pointer to a char - * which points to the version string - * Returns: Version number and version string (by reference) - */ -char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)"; -#define MCD_REV_MAJOR 0x00 -#define MCD_REV_MINOR 0x03 - -int MCD_getVersion(char **longVersion) -{ - *longVersion = MCD_versionString; - return ((MCD_REV_MAJOR << 8) | MCD_REV_MINOR); -} - -/********************** End of MCD_getVersion() *********************/ - -/********************************************************************/ -/* Private version of memcpy() - * Note that everything this is used for is longword-aligned. - */ -static void MCD_memcpy(int *dest, int *src, u32 size) -{ - u32 i; - - for (i = 0; i < size; i += sizeof(int), dest++, src++) - *dest = *src; -} diff --git a/drivers/dma/MCD_tasks.c b/drivers/dma/MCD_tasks.c deleted file mode 100644 index 453d95413da..00000000000 --- a/drivers/dma/MCD_tasks.c +++ /dev/null @@ -1,2413 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -/* Contains task code and structures for Multi-channel DMA */ - -#include - -#include - -u32 MCD_varTab0[]; -u32 MCD_varTab1[]; -u32 MCD_varTab2[]; -u32 MCD_varTab3[]; -u32 MCD_varTab4[]; -u32 MCD_varTab5[]; -u32 MCD_varTab6[]; -u32 MCD_varTab7[]; -u32 MCD_varTab8[]; -u32 MCD_varTab9[]; -u32 MCD_varTab10[]; -u32 MCD_varTab11[]; -u32 MCD_varTab12[]; -u32 MCD_varTab13[]; -u32 MCD_varTab14[]; -u32 MCD_varTab15[]; - -u32 MCD_funcDescTab0[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[]; -u32 MCD_funcDescTab2[]; -u32 MCD_funcDescTab3[]; -u32 MCD_funcDescTab4[]; -u32 MCD_funcDescTab5[]; -u32 MCD_funcDescTab6[]; -u32 MCD_funcDescTab7[]; -u32 MCD_funcDescTab8[]; -u32 MCD_funcDescTab9[]; -u32 MCD_funcDescTab10[]; -u32 MCD_funcDescTab11[]; -u32 MCD_funcDescTab12[]; -u32 MCD_funcDescTab13[]; -u32 MCD_funcDescTab14[]; -u32 MCD_funcDescTab15[]; -#endif - -u32 MCD_contextSave0[]; -u32 MCD_contextSave1[]; -u32 MCD_contextSave2[]; -u32 MCD_contextSave3[]; -u32 MCD_contextSave4[]; -u32 MCD_contextSave5[]; -u32 MCD_contextSave6[]; -u32 MCD_contextSave7[]; -u32 MCD_contextSave8[]; -u32 MCD_contextSave9[]; -u32 MCD_contextSave10[]; -u32 MCD_contextSave11[]; -u32 MCD_contextSave12[]; -u32 MCD_contextSave13[]; -u32 MCD_contextSave14[]; -u32 MCD_contextSave15[]; - -u32 MCD_realTaskTableSrc[] = { - 0x00000000, - 0x00000000, - (u32) MCD_varTab0, /* Task 0 Variable Table */ - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ - 0x00000000, - 0x00000000, - (u32) MCD_contextSave0, /* Task 0 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab1, /* Task 1 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab1, /* Task 1 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave1, /* Task 1 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab2, /* Task 2 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab2, /* Task 2 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave2, /* Task 2 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab3, /* Task 3 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab3, /* Task 3 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave3, /* Task 3 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab4, /* Task 4 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab4, /* Task 4 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave4, /* Task 4 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab5, /* Task 5 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab5, /* Task 5 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave5, /* Task 5 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab6, /* Task 6 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab6, /* Task 6 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave6, /* Task 6 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab7, /* Task 7 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab7, /* Task 7 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave7, /* Task 7 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab8, /* Task 8 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab8, /* Task 8 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave8, /* Task 8 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab9, /* Task 9 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab9, /* Task 9 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave9, /* Task 9 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab10, /* Task 10 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab10, /* Task 10 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave10, /* Task 10 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab11, /* Task 11 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab11, /* Task 11 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave11, /* Task 11 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab12, /* Task 12 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab12, /* Task 12 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave12, /* Task 12 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab13, /* Task 13 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab13, /* Task 13 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave13, /* Task 13 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab14, /* Task 14 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab14, /* Task 14 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave14, /* Task 14 context save space */ - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_varTab15, /* Task 15 Variable Table */ -#ifdef MCD_INCLUDE_EU - (u32) MCD_funcDescTab15, /* Task 15 Fn Desc. Table & Flags */ -#else - (u32) MCD_funcDescTab0, /* Task 0 Fn Desc. Table & Flags */ -#endif - 0x00000000, - 0x00000000, - (u32) MCD_contextSave15, /* Task 15 context save space */ - 0x00000000, -}; - -u32 MCD_varTab0[] = { /* Task 0 Variable Table */ - 0x00000000, /* var[0] */ - 0x00000000, /* var[1] */ - 0x00000000, /* var[2] */ - 0x00000000, /* var[3] */ - 0x00000000, /* var[4] */ - 0x00000000, /* var[5] */ - 0x00000000, /* var[6] */ - 0x00000000, /* var[7] */ - 0x00000000, /* var[8] */ - 0x00000000, /* var[9] */ - 0x00000000, /* var[10] */ - 0x00000000, /* var[11] */ - 0x00000000, /* var[12] */ - 0x00000000, /* var[13] */ - 0x00000000, /* var[14] */ - 0x00000000, /* var[15] */ - 0x00000000, /* var[16] */ - 0x00000000, /* var[17] */ - 0x00000000, /* var[18] */ - 0x00000000, /* var[19] */ - 0x00000000, /* var[20] */ - 0x00000000, /* var[21] */ - 0x00000000, /* var[22] */ - 0x00000000, /* var[23] */ - 0xe0000000, /* inc[0] */ - 0x20000000, /* inc[1] */ - 0x2000ffff, /* inc[2] */ - 0x00000000, /* inc[3] */ - 0x00000000, /* inc[4] */ - 0x00000000, /* inc[5] */ - 0x00000000, /* inc[6] */ - 0x00000000, /* inc[7] */ -}; - -u32 MCD_varTab1[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab2[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab3[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab4[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab5[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab6[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab7[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab8[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab9[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab10[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab11[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab12[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab13[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab14[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_varTab15[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xe0000000, - 0x20000000, - 0x2000ffff, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_funcDescTab0[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -#ifdef MCD_INCLUDE_EU -u32 MCD_funcDescTab1[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab2[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab3[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab4[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab5[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab6[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab7[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab8[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab9[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab10[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab11[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab12[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab13[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab14[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; - -u32 MCD_funcDescTab15[] = { - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0xa0045670, - 0xa0000000, - 0xa0000000, - 0x20000000, - 0x21800000, - 0x21e00000, - 0x20400000, - 0x20500000, - 0x205a0000, - 0x20a00000, - 0x202fa000, - 0x202f9000, - 0x202ea000, - 0x202da000, - 0x202e2000, - 0x202f2000, -}; -#endif /*MCD_INCLUDE_EU */ - -u32 MCD_contextSave0[128]; /* Task 0 context save space */ -u32 MCD_contextSave1[128]; /* Task 1 context save space */ -u32 MCD_contextSave2[128]; /* Task 2 context save space */ -u32 MCD_contextSave3[128]; /* Task 3 context save space */ -u32 MCD_contextSave4[128]; /* Task 4 context save space */ -u32 MCD_contextSave5[128]; /* Task 5 context save space */ -u32 MCD_contextSave6[128]; /* Task 6 context save space */ -u32 MCD_contextSave7[128]; /* Task 7 context save space */ -u32 MCD_contextSave8[128]; /* Task 8 context save space */ -u32 MCD_contextSave9[128]; /* Task 9 context save space */ -u32 MCD_contextSave10[128]; /* Task 10 context save space */ -u32 MCD_contextSave11[128]; /* Task 11 context save space */ -u32 MCD_contextSave12[128]; /* Task 12 context save space */ -u32 MCD_contextSave13[128]; /* Task 13 context save space */ -u32 MCD_contextSave14[128]; /* Task 14 context save space */ -u32 MCD_contextSave15[128]; /* Task 15 context save space */ - -u32 MCD_ChainNoEu_TDT[]; -u32 MCD_SingleNoEu_TDT[]; -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[]; -u32 MCD_SingleEu_TDT[]; -#endif -u32 MCD_ENetRcv_TDT[]; -u32 MCD_ENetXmit_TDT[]; - -u32 MCD_modelTaskTableSrc[] = { - (u32) MCD_ChainNoEu_TDT, - (u32) & ((u8 *) MCD_ChainNoEu_TDT)[0x0000016c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_SingleNoEu_TDT, - (u32) & ((u8 *) MCD_SingleNoEu_TDT)[0x000000d4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#ifdef MCD_INCLUDE_EU - (u32) MCD_ChainEu_TDT, - (u32) & ((u8 *) MCD_ChainEu_TDT)[0x000001b4], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_SingleEu_TDT, - (u32) & ((u8 *) MCD_SingleEu_TDT)[0x00000124], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -#endif - (u32) MCD_ENetRcv_TDT, - (u32) & ((u8 *) MCD_ENetRcv_TDT)[0x0000009c], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - (u32) MCD_ENetXmit_TDT, - (u32) & ((u8 *) MCD_ENetXmit_TDT)[0x000000d0], - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, - 0x00000000, -}; - -u32 MCD_ChainNoEu_TDT[] = { - 0x80004000, - 0x8118801b, - 0xb8c60018, - 0x10002b10, - 0x7000000d, - 0x018cf89f, - 0x6000000a, - 0x080cf89f, - 0x000001f8, - 0x98180364, - 0x8118801b, - 0xf8c6001a, - 0xb8c6601b, - 0x10002710, - 0x00000f18, - 0xb8c6001d, - 0x10001310, - 0x60000007, - 0x014cf88b, - 0x98c6001c, - 0x00000710, - 0x98c70018, - 0x10001f10, - 0x0000c818, - 0x000001f8, - 0xc1476018, - 0xc003231d, - 0x811a601b, - 0xc1862102, - 0x849be009, - 0x03fed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x1000cb20, - 0x70000006, - 0x088cf88f, - 0x1000cb28, - 0x70000006, - 0x088cf88f, - 0x1000cb30, - 0x70000006, - 0x088cf88f, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0xc1476018, - 0xc003241d, - 0x811a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc1862102, - 0x849be009, - 0x0bfed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x1000cb20, - 0x70000006, - 0x088cf88f, - 0x1000cb28, - 0x70000006, - 0x088cf88f, - 0x1000cb30, - 0x70000006, - 0x088cf88f, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0x8118801b, - 0xd8c60018, - 0x98c6601c, - 0x6000000b, - 0x0c8cfc9f, - 0x000001f8, - 0xa146001e, - 0x10000b08, - 0x10002050, - 0xb8c60018, - 0x10002b10, - 0x7000000a, - 0x080cf89f, - 0x6000000d, - 0x018cf89f, - 0x000001f8, - 0x8618801b, - 0x7000000e, - 0x084cf21f, - 0xd8990336, - 0x8019801b, - 0x040001f8, - 0x000001f8, - 0x000001f8, -}; - -u32 MCD_SingleNoEu_TDT[] = { - 0x8198001b, - 0x7000000d, - 0x080cf81f, - 0x8198801b, - 0x6000000e, - 0x084cf85f, - 0x000001f8, - 0x8298001b, - 0x7000000d, - 0x010cf81f, - 0x6000000e, - 0x018cf81f, - 0xc202601b, - 0xc002221c, - 0x809a601b, - 0xc10420c2, - 0x839be009, - 0x03fed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x70000006, - 0x088cf889, - 0x1000cb28, - 0x70000006, - 0x088cf889, - 0x1000cb30, - 0x70000006, - 0x088cf889, - 0x0000cb38, - 0x000001f8, - 0xc202601b, - 0xc002229c, - 0x809a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc10420c2, - 0x839be009, - 0x0bfed7b8, - 0xda9b001b, - 0x9b9be01b, - 0x70000006, - 0x088cf889, - 0x1000cb28, - 0x70000006, - 0x088cf889, - 0x1000cb30, - 0x70000006, - 0x088cf889, - 0x0000cb38, - 0x000001f8, - 0xc318022d, - 0x8018801b, - 0x040001f8, -}; - -#ifdef MCD_INCLUDE_EU -u32 MCD_ChainEu_TDT[] = { - 0x80004000, - 0x8198801b, - 0xb8c68018, - 0x10002f10, - 0x7000000d, - 0x01ccf89f, - 0x6000000a, - 0x080cf89f, - 0x000001f8, - 0x981803a4, - 0x8198801b, - 0xf8c6801a, - 0xb8c6e01b, - 0x10002b10, - 0x00001318, - 0xb8c6801d, - 0x10001710, - 0x60000007, - 0x018cf88c, - 0x98c6801c, - 0x00000b10, - 0x98c78018, - 0x10002310, - 0x0000c820, - 0x000001f8, - 0x8698801b, - 0x7000000f, - 0x084cf2df, - 0xd899042d, - 0x8019801b, - 0x60000003, - 0x2cd7c7df, - 0xd8990364, - 0x8019801b, - 0x60000003, - 0x2c17c7df, - 0x000001f8, - 0xc1c7e018, - 0xc003a35e, - 0x819a601b, - 0xc206a142, - 0x851be009, - 0x63fe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf81f, - 0x1000cb20, - 0x70000006, - 0x088cf891, - 0x1000cb28, - 0x70000006, - 0x088cf891, - 0x1000cb30, - 0x70000006, - 0x088cf891, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0xc1c7e018, - 0xc003a49e, - 0x819a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc206a142, - 0x851be009, - 0x6bfe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf81f, - 0x1000cb20, - 0x70000006, - 0x088cf891, - 0x1000cb28, - 0x70000006, - 0x088cf891, - 0x1000cb30, - 0x70000006, - 0x088cf891, - 0x1000cb38, - 0x0000c728, - 0x000001f8, - 0x8198801b, - 0xd8c68018, - 0x98c6e01c, - 0x6000000b, - 0x0c8cfc9f, - 0x0000cc08, - 0xa1c6801e, - 0x10000f08, - 0x10002458, - 0xb8c68018, - 0x10002f10, - 0x7000000a, - 0x080cf89f, - 0x6000000d, - 0x01ccf89f, - 0x000001f8, - 0x8698801b, - 0x7000000e, - 0x084cf25f, - 0xd899037f, - 0x8019801b, - 0x040001f8, - 0x000001f8, - 0x000001f8, -}; - -u32 MCD_SingleEu_TDT[] = { - 0x8218001b, - 0x7000000d, - 0x080cf81f, - 0x8218801b, - 0x6000000e, - 0x084cf85f, - 0x000001f8, - 0x8318001b, - 0x7000000d, - 0x014cf81f, - 0x6000000e, - 0x01ccf81f, - 0x8498001b, - 0x7000000f, - 0x080cf19f, - 0xd81882a4, - 0x8019001b, - 0x60000003, - 0x2c97c7df, - 0xd818826d, - 0x8019001b, - 0x60000003, - 0x2c17c7df, - 0x000001f8, - 0xc282e01b, - 0xc002a25e, - 0x811a601b, - 0xc184a102, - 0x841be009, - 0x63fe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf99f, - 0x70000006, - 0x088cf88b, - 0x1000cb28, - 0x70000006, - 0x088cf88b, - 0x1000cb30, - 0x70000006, - 0x088cf88b, - 0x0000cb38, - 0x000001f8, - 0xc282e01b, - 0xc002a31e, - 0x811a601b, - 0xda9b001b, - 0x9b9be01b, - 0x0000d3a0, - 0xc184a102, - 0x841be009, - 0x6bfe0000, - 0x0d4cfddf, - 0xda9b001b, - 0x9b9be01b, - 0x70000002, - 0x004cf99f, - 0x70000006, - 0x088cf88b, - 0x1000cb28, - 0x70000006, - 0x088cf88b, - 0x1000cb30, - 0x70000006, - 0x088cf88b, - 0x0000cb38, - 0x000001f8, - 0x8144801c, - 0x0000c008, - 0xc398027f, - 0x8018801b, - 0x040001f8, -}; -#endif -u32 MCD_ENetRcv_TDT[] = { - 0x80004000, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0x98180209, - 0x81c40004, - 0x7000000e, - 0x010cf05f, - 0x7000000c, - 0x01ccf05f, - 0x70000004, - 0x014cf049, - 0x70000004, - 0x004cf04a, - 0x00000b88, - 0xc4030150, - 0x8119e012, - 0x03e0cf90, - 0x81188000, - 0x000ac788, - 0xc4030000, - 0x8199e000, - 0x70000004, - 0x084cfc8b, - 0x60000005, - 0x0cccf841, - 0x81c60000, - 0xc399021b, - 0x80198000, - 0x00008400, - 0x00000f08, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0xc2188209, - 0x80190000, - 0x040001f8, - 0x000001f8, -}; - -u32 MCD_ENetXmit_TDT[] = { - 0x80004000, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0x98180309, - 0x80004003, - 0x81c60004, - 0x7000000e, - 0x014cf05f, - 0x7000000c, - 0x028cf05f, - 0x7000000d, - 0x018cf05f, - 0x70000004, - 0x01ccf04d, - 0x10000b90, - 0x60000004, - 0x020cf0a1, - 0xc3188312, - 0x83c70000, - 0x00001f10, - 0xc583a3c3, - 0x81042325, - 0x03e0c798, - 0xd8990000, - 0x9999e000, - 0x000acf98, - 0xd8992306, - 0x9999e03f, - 0x03eac798, - 0xd8990000, - 0x9999e000, - 0x000acf98, - 0xd8990000, - 0x99832302, - 0x0beac798, - 0x81988000, - 0x6000000b, - 0x0c4cfc5f, - 0x81c80000, - 0xc5190312, - 0x80198000, - 0x00008400, - 0x00000f08, - 0x81988000, - 0x10000788, - 0x6000000a, - 0x080cf05f, - 0xc2988309, - 0x80190000, - 0x040001f8, - 0x000001f8, -}; - -#ifdef MCD_INCLUDE_EU -MCD_bufDesc MCD_singleBufDescs[NCHANNELS]; -#endif diff --git a/drivers/dma/MCD_tasksInit.c b/drivers/dma/MCD_tasksInit.c deleted file mode 100644 index 079cd0af3c0..00000000000 --- a/drivers/dma/MCD_tasksInit.c +++ /dev/null @@ -1,225 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#include - -/* Functions for initializing variable tables of different types of tasks. */ - -/* - * Do not edit! - */ - -#include - -extern dmaRegs *MCD_dmaBar; - -/* Task 0 */ - -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 11, (u32) xferSize); /* var[11] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 3, (u32) 0x00000000); /* var[3] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x80000000); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0x00000010); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x08000000); /* var[16] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000001); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x40000000); /* inc[6] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 1 */ - -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 7, (u32) srcAddr); /* var[7] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 2, (u32) destAddr); /* var[2] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 3, (u32) dmaSize); /* var[3] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 5, (u32) flags); /* var[5] */ - MCD_SET_VAR(taskChan, 1, (u32) currBD); /* var[1] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000004); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x08000000); /* var[10] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000001); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x40000000); /* inc[5] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 2 */ - -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 12, (u32) xferSize); /* var[12] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x00000000); /* var[11] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x00000000); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0x80000000); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000010); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x00000001); /* var[16] */ - MCD_SET_VAR(taskChan, 17, (u32) 0x00000004); /* var[17] */ - MCD_SET_VAR(taskChan, 18, (u32) 0x08000000); /* var[18] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0x80000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0xc0000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 3 */ - -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 8, (u32) srcAddr); /* var[8] */ - MCD_SET_VAR(taskChan, 25, (u32) (0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */ - MCD_SET_VAR(taskChan, 3, (u32) destAddr); /* var[3] */ - MCD_SET_VAR(taskChan, 24, (u32) (0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */ - MCD_SET_VAR(taskChan, 4, (u32) dmaSize); /* var[4] */ - MCD_SET_VAR(taskChan, 26, (u32) (0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */ - MCD_SET_VAR(taskChan, 6, (u32) flags); /* var[6] */ - MCD_SET_VAR(taskChan, 2, (u32) currBD); /* var[2] */ - MCD_SET_VAR(taskChan, 0, (u32) cSave); /* var[0] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000001); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x00000004); /* var[11] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x08000000); /* var[12] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x00000000); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0xc0000000); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x80000001); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0x40000000); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 4 */ - -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */ - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 6, (u32) rcvFifoPtr); /* var[6] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x0000ffff); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x30000000); /* var[10] */ - MCD_SET_VAR(taskChan, 11, (u32) 0x0fffffff); /* var[11] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000008); /* var[12] */ - MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */ - MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */ - MCD_SET_VAR(taskChan, 26, (u32) 0x20000004); /* inc[2] */ - MCD_SET_VAR(taskChan, 27, (u32) 0x40000000); /* inc[3] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} - -/* Task 5 */ - -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, - volatile TaskTableEntry * taskTable, int channel) -{ - volatile TaskTableEntry *taskChan = taskTable + channel; - - MCD_SET_VAR(taskChan, 0, (u32) bDBase); /* var[0] */ - MCD_SET_VAR(taskChan, 3, (u32) currBD); /* var[3] */ - MCD_SET_VAR(taskChan, 11, (u32) xmitFifoPtr); /* var[11] */ - MCD_SET_VAR(taskChan, 1, (u32) 0x00000000); /* var[1] */ - MCD_SET_VAR(taskChan, 2, (u32) 0x00000000); /* var[2] */ - MCD_SET_VAR(taskChan, 4, (u32) 0x00000000); /* var[4] */ - MCD_SET_VAR(taskChan, 5, (u32) 0x00000000); /* var[5] */ - MCD_SET_VAR(taskChan, 6, (u32) 0x00000000); /* var[6] */ - MCD_SET_VAR(taskChan, 7, (u32) 0x00000000); /* var[7] */ - MCD_SET_VAR(taskChan, 8, (u32) 0x00000000); /* var[8] */ - MCD_SET_VAR(taskChan, 9, (u32) 0x00000000); /* var[9] */ - MCD_SET_VAR(taskChan, 10, (u32) 0x00000000); /* var[10] */ - MCD_SET_VAR(taskChan, 12, (u32) 0x00000000); /* var[12] */ - MCD_SET_VAR(taskChan, 13, (u32) 0x0000ffff); /* var[13] */ - MCD_SET_VAR(taskChan, 14, (u32) 0xffffffff); /* var[14] */ - MCD_SET_VAR(taskChan, 15, (u32) 0x00000004); /* var[15] */ - MCD_SET_VAR(taskChan, 16, (u32) 0x00000008); /* var[16] */ - MCD_SET_VAR(taskChan, 24, (u32) 0x00000000); /* inc[0] */ - MCD_SET_VAR(taskChan, 25, (u32) 0x60000000); /* inc[1] */ - MCD_SET_VAR(taskChan, 26, (u32) 0x40000000); /* inc[2] */ - MCD_SET_VAR(taskChan, 27, (u32) 0xc000fffc); /* inc[3] */ - MCD_SET_VAR(taskChan, 28, (u32) 0xe0000004); /* inc[4] */ - MCD_SET_VAR(taskChan, 29, (u32) 0x80000000); /* inc[5] */ - MCD_SET_VAR(taskChan, 30, (u32) 0x4000ffff); /* inc[6] */ - MCD_SET_VAR(taskChan, 31, (u32) 0xe0000001); /* inc[7] */ - - /* Set the task's Enable bit in its Task Control Register */ - MCD_dmaBar->taskControl[channel] |= (u16) 0x8000; -} diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index a75572fe5de..48811eaaeb3 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_DMA) += dma-uclass.o -obj-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o obj-$(CONFIG_APBH_DMA) += apbh_dma.o obj-$(CONFIG_BCM6348_IUDMA) += bcm6348-iudma.o obj-$(CONFIG_FSL_DMA) += fsl_dma.o diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index ebab4d9f2e5..23ad2c29d0a 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -471,14 +471,6 @@ config SYS_UNIFY_CACHE depends on MCFFEC bool "Invalidate icache during ethernet operations" -config FSLDMAFEC - bool "ColdFire DMA Ethernet Support" - select PHYLIB - select SYS_DISCOVER_PHY - help - This driver supports the network interface units in the - ColdFire family. - config KS8851_MLL bool "Microchip KS8851-MLL controller driver" help diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 1ce6fea323c..f9aed1646c9 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -37,7 +37,6 @@ obj-$(CONFIG_ETH_SANDBOX_RAW) += sandbox-raw.o obj-$(CONFIG_FEC_MXC) += fec_mxc.o obj-$(CONFIG_FMAN_ENET) += fm/ obj-$(CONFIG_FMAN_ENET) += fsl_mdio.o -obj-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o obj-$(CONFIG_FSL_ENETC) += fsl_enetc.o fsl_enetc_mdio.o obj-$(CONFIG_FSL_LS_MDIO) += fsl_ls_mdio.o obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c deleted file mode 100644 index cc61a107403..00000000000 --- a/drivers/net/fsl_mcdmafec.c +++ /dev/null @@ -1,592 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * Conversion to DM - * (C) 2019 Angelo Dureghello - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "MCD_dma.h" - -#undef ET_DEBUG -#undef MII_DEBUG - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 -#define PKT_MAXBUF_SIZE 1518 -#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) - -/* RxBD bits definitions */ -#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ - BD_ENET_RX_OV | BD_ENET_RX_TR) - -DECLARE_GLOBAL_DATA_PTR; - -static void init_eth_info(struct fec_info_dma *info) -{ - /* setup Receive and Transmit buffer descriptor */ -#ifdef CFG_SYS_FEC_BUF_USE_SRAM - static u32 tmp; - - if (info->index == 0) - tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; - else - info->rxbd = (cbd_t *)DBUF_LENGTH; - - info->rxbd = (cbd_t *)((u32)info->rxbd + tmp); - tmp = (u32)info->rxbd; - info->txbd = - (cbd_t *)((u32)info->txbd + tmp + - (PKTBUFSRX * sizeof(cbd_t))); - tmp = (u32)info->txbd; - info->txbuf = - (char *)((u32)info->txbuf + tmp + - (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - tmp = (u32)info->txbuf; -#else - info->rxbd = - (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (PKTBUFSRX * sizeof(cbd_t))); - info->txbd = - (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE, - (CFG_SYS_TX_ETH_BUFFER * sizeof(cbd_t))); - info->txbuf = - (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH); -#endif - -#ifdef ET_DEBUG - printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd); -#endif - info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32); -} - -static void fec_halt(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - int counter = 0xffff; - - /* issue graceful stop command to the FEC transmitter if necessary */ - fecp->tcr |= FEC_TCR_GTS; - - /* wait for graceful stop to register */ - while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) - ; - - /* Disable DMA tasks */ - MCD_killDma(info->tx_task); - MCD_killDma(info->rx_task); - - /* Disable the Ethernet Controller */ - fecp->ecr &= ~FEC_ECR_ETHER_EN; - - /* Clear FIFO status registers */ - fecp->rfsr &= FIFO_ERRSTAT; - fecp->tfsr &= FIFO_ERRSTAT; - - fecp->frst = 0x01000000; - - /* Issue a reset command to the FEC chip */ - fecp->ecr |= FEC_ECR_RESET; - - /* wait at least 20 clock cycles */ - mdelay(10); - -#ifdef ET_DEBUG - printf("Ethernet task stopped\n"); -#endif -} - -#ifdef ET_DEBUG -static void dbg_fec_regs(struct eth_device *dev) -{ - struct fec_info_dma *info = dev->priv; - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - - printf("=====\n"); - printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); - printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); - printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); - printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); - printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); - printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); - printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); - printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); - printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); - printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); - printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); - printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); - printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); - printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); - printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); - printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); - printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); - printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); - printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); - printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); - printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); - printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); - printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); - printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); - printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); - printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); - printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); - printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); - printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); - printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); - printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); - printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); - printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); - printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); - printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); -} -#endif - -static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd) -{ - struct bd_info *bd = gd->bd; - - if ((dup_spd >> 16) == FULL) { - /* Set maximum frame length */ - fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | - FEC_RCR_PROM | 0x100; - fecp->tcr = FEC_TCR_FDEN; - } else { - /* Half duplex mode */ - fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | - FEC_RCR_MII_MODE | FEC_RCR_DRT; - fecp->tcr &= ~FEC_TCR_FDEN; - } - - if ((dup_spd & 0xFFFF) == _100BASET) { -#ifdef MII_DEBUG - printf("100Mbps\n"); -#endif - bd->bi_ethspeed = 100; - } else { -#ifdef MII_DEBUG - printf("10Mbps\n"); -#endif - bd->bi_ethspeed = 10; - } -} - -static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac) -{ - u8 curr_byte; /* byte for which to compute the CRC */ - int byte; /* loop - counter */ - int bit; /* loop - counter */ - u32 crc = 0xffffffff; /* initial value */ - - for (byte = 0; byte < 6; byte++) { - curr_byte = mac[byte]; - for (bit = 0; bit < 8; bit++) { - if ((curr_byte & 0x01) ^ (crc & 0x01)) { - crc >>= 1; - crc = crc ^ 0xedb88320; - } else { - crc >>= 1; - } - curr_byte >>= 1; - } - } - - crc = crc >> 26; - - /* Set individual hash table register */ - if (crc >= 32) { - fecp->ialr = (1 << (crc - 32)); - fecp->iaur = 0; - } else { - fecp->ialr = 0; - fecp->iaur = (1 << crc); - } - - /* Set physical address */ - fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; - fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; - - /* Clear multicast address hash table */ - fecp->gaur = 0; - fecp->galr = 0; -} - -static int fec_init(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - int rval, i; - uchar enetaddr[6]; - -#ifdef ET_DEBUG - printf("fec_init: iobase 0x%08x ...\n", info->iobase); -#endif - - fecpin_setclear(info, 1); - fec_halt(dev); - - mii_init(); - set_fec_duplex_speed(fecp, info->dup_spd); - - /* We use strictly polling mode only */ - fecp->eimr = 0; - - /* Clear any pending interrupt */ - fecp->eir = 0xffffffff; - - /* Set station address */ - if (info->index == 0) - rval = eth_env_get_enetaddr("ethaddr", enetaddr); - else - rval = eth_env_get_enetaddr("eth1addr", enetaddr); - - if (!rval) { - puts("Please set a valid MAC address\n"); - return -EINVAL; - } - - fec_set_hwaddr(fecp, enetaddr); - - /* Set Opcode/Pause Duration Register */ - fecp->opd = 0x00010020; - - /* Setup Buffers and Buffer Descriptors */ - info->rx_idx = 0; - info->tx_idx = 0; - - /* Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: Empty, Wrap */ - for (i = 0; i < PKTBUFSRX; i++) { - info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; - info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i]; - } - info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: Last, Tx CRC */ - for (i = 0; i < CFG_SYS_TX_ETH_BUFFER; i++) { - info->txbd[i].cbd_sc = 0; - info->txbd[i].cbd_datlen = 0; - info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); - } - info->txbd[CFG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; - - info->used_tbd_idx = 0; - info->clean_tbd_num = CFG_SYS_TX_ETH_BUFFER; - - /* Set Rx FIFO alarm and granularity value */ - fecp->rfcr = 0x0c000000; - fecp->rfar = 0x0000030c; - - /* Set Tx FIFO granularity value */ - fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; - fecp->tfar = 0x00000080; - - fecp->tfwr = 0x2; - fecp->ctcwr = 0x03000000; - - /* Enable DMA receive task */ - MCD_startDma(info->rx_task, - (s8 *)info->rxbd, - 0, - (s8 *)&fecp->rfdr, - 4, - 0, - 4, - info->rx_init, - info->rx_pri, - (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) - ); - - /* Enable DMA tx task with no ready buffer descriptors */ - MCD_startDma(info->tx_task, - (s8 *)info->txbd, - 0, - (s8 *)&fecp->tfdr, - 4, - 0, - 4, - info->tx_init, - info->tx_pri, - (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), - (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) - ); - - /* Now enable the transmit and receive processing */ - fecp->ecr |= FEC_ECR_ETHER_EN; - - return 0; -} - -static int mcdmafec_init(struct udevice *dev) -{ - return fec_init(dev); -} - -static int mcdmafec_send(struct udevice *dev, void *packet, int length) -{ - struct fec_info_dma *info = dev_get_priv(dev); - cbd_t *p_tbd, *p_used_tbd; - u16 phy_status; - - miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status); - - /* process all the consumed TBDs */ - while (info->clean_tbd_num < CFG_SYS_TX_ETH_BUFFER) { - p_used_tbd = &info->txbd[info->used_tbd_idx]; - if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) { -#ifdef ET_DEBUG - printf("Cannot clean TBD %d, in use\n", - info->clean_tbd_num); -#endif - return 0; - } - - /* clean this buffer descriptor */ - if (info->used_tbd_idx == (CFG_SYS_TX_ETH_BUFFER - 1)) - p_used_tbd->cbd_sc = BD_ENET_TX_WRAP; - else - p_used_tbd->cbd_sc = 0; - - /* update some indeces for a correct handling of TBD ring */ - info->clean_tbd_num++; - info->used_tbd_idx = (info->used_tbd_idx + 1) - % CFG_SYS_TX_ETH_BUFFER; - } - - /* Check for valid length of data. */ - if (length > 1500 || length <= 0) - return -1; - - /* Check the number of vacant TxBDs. */ - if (info->clean_tbd_num < 1) { - printf("No available TxBDs ...\n"); - return -1; - } - - /* Get the first TxBD to send the mac header */ - p_tbd = &info->txbd[info->tx_idx]; - p_tbd->cbd_datlen = length; - p_tbd->cbd_bufaddr = (u32)packet; - p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; - info->tx_idx = (info->tx_idx + 1) % CFG_SYS_TX_ETH_BUFFER; - - /* Enable DMA transmit task */ - MCD_continDma(info->tx_task); - - info->clean_tbd_num -= 1; - - /* wait until frame is sent . */ - while (p_tbd->cbd_sc & BD_ENET_TX_READY) - udelay(10); - - return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS); -} - -static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp) -{ - struct fec_info_dma *info = dev_get_priv(dev); - volatile fecdma_t *fecp = (fecdma_t *)info->iobase; - - cbd_t *prbd = &info->rxbd[info->rx_idx]; - u32 ievent; - int frame_length, len = 0; - - /* Check if any critical events have happened */ - ievent = fecp->eir; - if (ievent != 0) { - fecp->eir = ievent; - - if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { - printf("fec_recv: error\n"); - fec_halt(dev); - fec_init(dev); - return 0; - } - - if (ievent & FEC_EIR_HBERR) { - /* Heartbeat error */ - fecp->tcr |= FEC_TCR_GTS; - } - - if (ievent & FEC_EIR_GRA) { - /* Graceful stop complete */ - if (fecp->tcr & FEC_TCR_GTS) { - printf("fec_recv: tcr_gts\n"); - fec_halt(dev); - fecp->tcr &= ~FEC_TCR_GTS; - fec_init(dev); - } - } - } - - if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) { - if ((prbd->cbd_sc & BD_ENET_RX_LAST) && - !(prbd->cbd_sc & BD_ENET_RX_ERR) && - ((prbd->cbd_datlen - 4) > 14)) { - /* Get buffer address and size */ - frame_length = prbd->cbd_datlen - 4; - - /* Fill the buffer and pass it to upper layers */ - net_process_received_packet((uchar *)prbd->cbd_bufaddr, - frame_length); - len = frame_length; - } - - /* Reset buffer descriptor as empty */ - if (info->rx_idx == (PKTBUFSRX - 1)) - prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - else - prbd->cbd_sc = BD_ENET_RX_EMPTY; - - prbd->cbd_datlen = PKTSIZE_ALIGN; - - /* Now, we have an empty RxBD, restart the DMA receive task */ - MCD_continDma(info->rx_task); - - /* Increment BD count */ - info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX; - } - - return len; -} - -static void mcdmafec_halt(struct udevice *dev) -{ - fec_halt(dev); -} - -static const struct eth_ops mcdmafec_ops = { - .start = mcdmafec_init, - .send = mcdmafec_send, - .recv = mcdmafec_recv, - .stop = mcdmafec_halt, -}; - -/* - * Boot sequence, called just after mcffec_of_to_plat, - * as DM way, it replaces old mcffec_initialize. - */ -static int mcdmafec_probe(struct udevice *dev) -{ - struct fec_info_dma *info = dev_get_priv(dev); - struct eth_pdata *pdata = dev_get_plat(dev); - int node = dev_of_offset(dev); - int retval; - const u32 *val; - - info->index = dev_seq(dev); - info->iobase = pdata->iobase; - info->miibase = pdata->iobase; - info->phy_addr = -1; - - val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL); - if (val) - info->rx_task = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL); - if (val) - info->tx_task = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL); - if (val) - info->rx_pri = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL); - if (val) - info->tx_pri = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL); - if (val) - info->rx_init = fdt32_to_cpu(*val); - - val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL); - if (val) - info->tx_init = fdt32_to_cpu(*val); - -#ifdef CFG_SYS_FEC_BUF_USE_SRAM - u32 tmp = CFG_SYS_INIT_RAM_ADDR + 0x1000; -#endif - init_eth_info(info); - -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) - info->bus = mdio_alloc(); - if (!info->bus) - return -ENOMEM; - strlcpy(info->bus->name, dev->name, MDIO_NAME_LEN); - info->bus->read = mcffec_miiphy_read; - info->bus->write = mcffec_miiphy_write; - - retval = mdio_register(info->bus); - if (retval < 0) - return retval; -#endif - - return 0; -} - -static int mcdmafec_remove(struct udevice *dev) -{ - struct fec_info_dma *priv = dev_get_priv(dev); - - mdio_unregister(priv->bus); - mdio_free(priv->bus); - - return 0; -} - -/* - * Boot sequence, called 1st - */ -static int mcdmafec_of_to_plat(struct udevice *dev) -{ - struct eth_pdata *pdata = dev_get_plat(dev); - const u32 *val; - - pdata->iobase = dev_read_addr(dev); - /* Default to 10Mbit/s */ - pdata->max_speed = 10; - - val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL); - if (val) - pdata->max_speed = fdt32_to_cpu(*val); - - return 0; -} - -static const struct udevice_id mcdmafec_ids[] = { - { .compatible = "fsl,mcf-dma-fec" }, - { } -}; - -U_BOOT_DRIVER(mcffec) = { - .name = "mcdmafec", - .id = UCLASS_ETH, - .of_match = mcdmafec_ids, - .of_to_plat = mcdmafec_of_to_plat, - .probe = mcdmafec_probe, - .remove = mcdmafec_remove, - .ops = &mcdmafec_ops, - .priv_auto = sizeof(struct fec_info_dma), - .plat_auto = sizeof(struct eth_pdata), -}; diff --git a/include/MCD_dma.h b/include/MCD_dma.h deleted file mode 100644 index 2f16c89044e..00000000000 --- a/include/MCD_dma.h +++ /dev/null @@ -1,369 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#ifndef _MCD_API_H -#define _MCD_API_H - -/* Turn Execution Unit tasks ON (#define) or OFF (#undef) */ -#undef MCD_INCLUDE_EU - -/* Number of DMA channels */ -#define NCHANNELS 16 - -/* Total number of variants */ -#ifdef MCD_INCLUDE_EU -#define NUMOFVARIANTS 6 -#else -#define NUMOFVARIANTS 4 -#endif - -/* Define sizes of the various tables */ -#define TASK_TABLE_SIZE (NCHANNELS*32) -#define VAR_TAB_SIZE (128) -#define CONTEXT_SAVE_SIZE (128) -#define FUNCDESC_TAB_SIZE (256) - -#ifdef MCD_INCLUDE_EU -#define FUNCDESC_TAB_NUM 16 -#else -#define FUNCDESC_TAB_NUM 1 -#endif - -#ifndef DEFINESONLY - -/* Portability typedefs */ -#if 1 -#include "common.h" -#else -#ifndef s32 -typedef int s32; -#endif -#ifndef u32 -typedef unsigned int u32; -#endif -#ifndef s16 -typedef short s16; -#endif -#ifndef u16 -typedef unsigned short u16; -#endif -#ifndef s8 -typedef char s8; -#endif -#ifndef u8 -typedef unsigned char u8; -#endif -#endif - -/* - * These structures represent the internal registers of the - * multi-channel DMA - */ -struct dmaRegs_s { - u32 taskbar; /* task table base address */ - u32 currPtr; - u32 endPtr; - u32 varTablePtr; - u16 dma_rsvd0; - u16 ptdControl; /* ptd control */ - u32 intPending; /* interrupt pending */ - u32 intMask; /* interrupt mask */ - u16 taskControl[16]; /* task control */ - u8 priority[32]; /* priority */ - u32 initiatorMux; /* initiator mux control */ - u32 taskSize0; /* task size control 0. */ - u32 taskSize1; /* task size control 1. */ - u32 dma_rsvd1; /* reserved */ - u32 dma_rsvd2; /* reserved */ - u32 debugComp1; /* debug comparator 1 */ - u32 debugComp2; /* debug comparator 2 */ - u32 debugControl; /* debug control */ - u32 debugStatus; /* debug status */ - u32 ptdDebug; /* priority task decode debug */ - u32 dma_rsvd3[31]; /* reserved */ -}; -typedef volatile struct dmaRegs_s dmaRegs; - -#endif - -/* PTD contrl reg bits */ -#define PTD_CTL_TSK_PRI 0x8000 -#define PTD_CTL_COMM_PREFETCH 0x0001 - -/* Task Control reg bits and field masks */ -#define TASK_CTL_EN 0x8000 -#define TASK_CTL_VALID 0x4000 -#define TASK_CTL_ALWAYS 0x2000 -#define TASK_CTL_INIT_MASK 0x1f00 -#define TASK_CTL_ASTRT 0x0080 -#define TASK_CTL_HIPRITSKEN 0x0040 -#define TASK_CTL_HLDINITNUM 0x0020 -#define TASK_CTL_ASTSKNUM_MASK 0x000f - -/* Priority reg bits and field masks */ -#define PRIORITY_HLD 0x80 -#define PRIORITY_PRI_MASK 0x07 - -/* Debug Control reg bits and field masks */ -#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000 -#define DBG_CTL_AUTO_ARM 0x00008000 -#define DBG_CTL_BREAK 0x00004000 -#define DBG_CTL_COMP1_TYP_MASK 0x00003800 -#define DBG_CTL_COMP2_TYP_MASK 0x00000070 -#define DBG_CTL_EXT_BREAK 0x00000004 -#define DBG_CTL_INT_BREAK 0x00000002 - -/* - * PTD Debug reg selector addresses - * This reg must be written with a value to show the contents of - * one of the desired internal register. - */ -#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */ -#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and - have initiators asserted */ - -/* General return values */ -#define MCD_OK 0 -#define MCD_ERROR -1 -#define MCD_TABLE_UNALIGNED -2 -#define MCD_CHANNEL_INVALID -3 - -/* MCD_initDma input flags */ -#define MCD_RELOC_TASKS 0x00000001 -#define MCD_NO_RELOC_TASKS 0x00000000 -#define MCD_COMM_PREFETCH_EN 0x00000002 /* MCF547x/548x ONLY */ - -/* - * MCD_dmaStatus Status Values for each channel: - * MCD_NO_DMA - No DMA has been requested since reset - * MCD_IDLE - DMA active, but the initiator is currently inactive - * MCD_RUNNING - DMA active, and the initiator is currently active - * MCD_PAUSED - DMA active but it is currently paused - * MCD_HALTED - the most recent DMA has been killed with MCD_killTask() - * MCD_DONE - the most recent DMA has completed - */ -#define MCD_NO_DMA 1 -#define MCD_IDLE 2 -#define MCD_RUNNING 3 -#define MCD_PAUSED 4 -#define MCD_HALTED 5 -#define MCD_DONE 6 - -/* MCD_startDma parameter defines */ - -/* Constants for the funcDesc parameter */ -/* - * MCD_NO_BYTE_SWAP - to disable byte swapping - * MCD_BYTE_REVERSE - to reverse the bytes of each u32 of the DMAed data - * MCD_U16_REVERSE - to reverse the 16-bit halves of each 32-bit data - * value being DMAed - * MCD_U16_BYTE_REVERSE - to reverse the byte halves of each 16-bit half of - * each 32-bit data value DMAed - * MCD_NO_BIT_REV - do not reverse the bits of each byte DMAed - * MCD_BIT_REV - reverse the bits of each byte DMAed - * MCD_CRC16 - to perform CRC-16 on DMAed data - * MCD_CRCCCITT - to perform CRC-CCITT on DMAed data - * MCD_CRC32 - to perform CRC-32 on DMAed data - * MCD_CSUMINET - to perform internet checksums on DMAed data - * MCD_NO_CSUM - to perform no checksumming - */ -#define MCD_NO_BYTE_SWAP 0x00045670 -#define MCD_BYTE_REVERSE 0x00076540 -#define MCD_U16_REVERSE 0x00067450 -#define MCD_U16_BYTE_REVERSE 0x00054760 -#define MCD_NO_BIT_REV 0x00000000 -#define MCD_BIT_REV 0x00088880 -/* CRCing: */ -#define MCD_CRC16 0xc0100000 -#define MCD_CRCCCITT 0xc0200000 -#define MCD_CRC32 0xc0300000 -#define MCD_CSUMINET 0xc0400000 -#define MCD_NO_CSUM 0xa0000000 - -#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | \ - MCD_NO_CSUM) -#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM) - -/* Constants for the flags parameter */ -#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */ -#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */ -#define MCD_TT_FLAGS_SP 0x00000004 /* MCF547x/548x ONLY */ -#define MCD_TT_FLAGS_MASK 0x000000ff -#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW) - -#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */ -#define MCD_CHAIN_DMA /* TBD */ -#define MCD_EU_DMA /* TBD */ -#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */ -#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */ - -/* these flags are valid for MCD_startDma and the chained buffer descriptors */ -/* - * MCD_BUF_READY - indicates that this buf is now under the DMA's ctrl - * MCD_WRAP - to tell the FEC Dmas to wrap to the first BD - * MCD_INTERRUPT - to generate an interrupt after completion of the DMA - * MCD_END_FRAME - tell the DMA to end the frame when transferring - * last byte of data in buffer - * MCD_CRC_RESTART - to empty out the accumulated checksum prior to - * performing the DMA - */ -#define MCD_BUF_READY 0x80000000 -#define MCD_WRAP 0x20000000 -#define MCD_INTERRUPT 0x10000000 -#define MCD_END_FRAME 0x08000000 -#define MCD_CRC_RESTART 0x40000000 - -/* Defines for the FEC buffer descriptor control/status word*/ -#define MCD_FEC_BUF_READY 0x8000 -#define MCD_FEC_WRAP 0x2000 -#define MCD_FEC_INTERRUPT 0x1000 -#define MCD_FEC_END_FRAME 0x0800 - -/* Defines for general intuitiveness */ - -#define MCD_TRUE 1 -#define MCD_FALSE 0 - -/* Three different cases for destination and source. */ -#define MINUS1 -1 -#define ZERO 0 -#define PLUS1 1 - -#ifndef DEFINESONLY - -/* Task Table Entry struct*/ -typedef struct { - u32 TDTstart; /* task descriptor table start */ - u32 TDTend; /* task descriptor table end */ - u32 varTab; /* variable table start */ - u32 FDTandFlags; /* function descriptor table start & flags */ - volatile u32 descAddrAndStatus; - volatile u32 modifiedVarTab; - u32 contextSaveSpace; /* context save space start */ - u32 literalBases; -} TaskTableEntry; - -/* Chained buffer descriptor: - * flags - flags describing the DMA - * csumResult - checksum performed since last checksum reset - * srcAddr - the address to move data from - * destAddr - the address to move data to - * lastDestAddr - the last address written to - * dmaSize - the no of bytes to xfer independent of the xfer sz - * next - next buffer descriptor in chain - * info - private info about this descriptor; DMA does not affect it - */ -typedef volatile struct MCD_bufDesc_struct MCD_bufDesc; -struct MCD_bufDesc_struct { - u32 flags; - u32 csumResult; - s8 *srcAddr; - s8 *destAddr; - s8 *lastDestAddr; - u32 dmaSize; - MCD_bufDesc *next; - u32 info; -}; - -/* Progress Query struct: - * lastSrcAddr - the most-recent or last, post-increment source address - * lastDestAddr - the most-recent or last, post-increment destination address - * dmaSize - the amount of data transferred for the current buffer - * currBufDesc - pointer to the current buffer descriptor being DMAed - */ - -typedef volatile struct MCD_XferProg_struct { - s8 *lastSrcAddr; - s8 *lastDestAddr; - u32 dmaSize; - MCD_bufDesc *currBufDesc; -} MCD_XferProg; - -/* FEC buffer descriptor */ -typedef volatile struct MCD_bufDescFec_struct { - u16 statCtrl; - u16 length; - u32 dataPointer; -} MCD_bufDescFec; - -/*************************************************************************/ -/* API function Prototypes - see MCD_dmaApi.c for further notes */ - -/* MCD_startDma starts a particular kind of DMA: - * srcAddr - the channel on which to run the DMA - * srcIncr - the address to move data from, or buffer-descriptor address - * destAddr - the amount to increment the source address per transfer - * destIncr - the address to move data to - * dmaSize - the amount to increment the destination address per transfer - * xferSize - the number bytes in of each data movement (1, 2, or 4) - * initiator - what device initiates the DMA - * priority - priority of the DMA - * flags - flags describing the DMA - * funcDesc - description of byte swapping, bit swapping, and CRC actions - */ -int MCD_startDma(int channel, s8 * srcAddr, s16 srcIncr, s8 * destAddr, - s16 destIncr, u32 dmaSize, u32 xferSize, u32 initiator, - int priority, u32 flags, u32 funcDesc); - -/* - * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA - * registers, relocating and creating the appropriate task structures, and - * setting up some global settings - */ -int MCD_initDma(dmaRegs * sDmaBarAddr, void *taskTableDest, u32 flags); - -/* MCD_dmaStatus() returns the status of the DMA on the requested channel. */ -int MCD_dmaStatus(int channel); - -/* MCD_XferProgrQuery() returns progress of DMA on requested channel */ -int MCD_XferProgrQuery(int channel, MCD_XferProg * progRep); - -/* - * MCD_killDma() halts the DMA on the requested channel, without any - * intention of resuming the DMA. - */ -int MCD_killDma(int channel); - -/* - * MCD_continDma() continues a DMA which as stopped due to encountering an - * unready buffer descriptor. - */ -int MCD_continDma(int channel); - -/* - * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is - * running on that channel). - */ -int MCD_pauseDma(int channel); - -/* - * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is - * running on that channel). - */ -int MCD_resumeDma(int channel); - -/* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA */ -int MCD_csumQuery(int channel, u32 * csum); - -/* - * MCD_getCodeSize provides the packed size required by the microcoded task - * and structures. - */ -int MCD_getCodeSize(void); - -/* - * MCD_getVersion provides a pointer to a version string and returns a - * version number. - */ -int MCD_getVersion(char **longVersion); - -/* macro for setting a location in the variable table */ -#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value -/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function, - so I'm avoiding surrounding it with "do {} while(0)" */ - -#endif /* DEFINESONLY */ - -#endif /* _MCD_API_H */ diff --git a/include/MCD_progCheck.h b/include/MCD_progCheck.h deleted file mode 100644 index 1ec8fbfbd28..00000000000 --- a/include/MCD_progCheck.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - - /* This file is autogenerated. Do not change */ -#define CURRBD 4 -#define DCOUNT 6 -#define DESTPTR 5 -#define SRCPTR 7 diff --git a/include/MCD_tasksInit.h b/include/MCD_tasksInit.h deleted file mode 100644 index 9f582beb51a..00000000000 --- a/include/MCD_tasksInit.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - */ - -#ifndef MCD_TSK_INIT_H -#define MCD_TSK_INIT_H 1 - -/* - * Do not edit! - */ - -/* Task 0 */ -void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 1 */ -void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 2 */ -void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, - int xferSize, short xferSizeIncr, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 3 */ -void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, - short destIncr, int dmaSize, short xferSizeIncr, - int flags, int *currBD, int *cSave, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 4 */ -void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, - volatile TaskTableEntry * taskTable, int channel); - -/* Task 5 */ -void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, - volatile TaskTableEntry * taskTable, int channel); - -#endif /* MCD_TSK_INIT_H */ -- cgit v1.3.1 From dcda1f27f55e4ddd2d86dac76d57febe15ff8713 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:07 -0400 Subject: display_options.h: Correct includes First, a header should never include itself so remove that. Second, this header needs to be included as the function prototypes use types that we get via that header. Signed-off-by: Tom Rini --- include/display_options.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/display_options.h b/include/display_options.h index 85dacbc7590..66e59607737 100644 --- a/include/display_options.h +++ b/include/display_options.h @@ -9,6 +9,8 @@ #ifndef __DISPLAY_OPTIONS_H #define __DISPLAY_OPTIONS_H +#include + /** * print_size() - Print a size with a suffix * @@ -19,7 +21,6 @@ * @size: Size to print * @suffix String to print after the size */ -#include void print_size(uint64_t size, const char *suffix); /** -- cgit v1.3.1 From 5faf66a2d10cbc813e65005100d778577a16fa04 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:08 -0400 Subject: fsl_qe: Drop common.h In both include/fsl_qe.h and then also remove common.h from the files which had included fsl_qe.h Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/cpu_init.c | 1 - arch/powerpc/cpu/mpc85xx/cpu_init.c | 1 - board/freescale/common/arm_sleep.c | 1 - board/freescale/common/mpc85xx_sleep.c | 1 - board/freescale/ls1021aqds/ls1021aqds.c | 1 - board/freescale/ls1021atsn/ls1021atsn.c | 1 - board/freescale/ls1021atwr/ls1021atwr.c | 1 - board/freescale/ls1043ardb/ls1043ardb.c | 1 - board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 1 - drivers/net/fm/fm.c | 1 - drivers/net/qe/uccf.c | 1 - drivers/qe/fdt.c | 1 - drivers/qe/qe.c | 1 - include/fsl_qe.h | 1 - 14 files changed, 14 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index f5cb000de6b..8e6d3d28fc6 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -3,7 +3,6 @@ * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 96183ac2c84..b770d294e61 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -9,7 +9,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 46ffd817b44..228f07502f7 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index d3323b9ec1e..770fa0d62be 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -3,7 +3,6 @@ * Copyright 2014 Freescale Semiconductor, Inc. */ -#include #include #include #include diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index a618ce11a58..930ef6be385 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -4,7 +4,6 @@ * Copyright 2019, 2021 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index d0e4e796c60..b7e043b2e62 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -1,7 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright 2016-2019, 2021 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 27b9d79e5f0..78006afce86 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -4,7 +4,6 @@ * Copyright 2019, 2021-2022 NXP */ -#include #include #include #include diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 18869d8c1df..cf84ff9e638 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -4,7 +4,6 @@ * Copyright 2021-2022 NXP */ -#include #include #include #include diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index 21c21aac221..01786d938de 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -3,7 +3,6 @@ * Copyright 2020 Hitachi Power Grids. All rights reserved. */ -#include #include #include #include diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index 7dfa8219094..a8caa0f0927 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -3,7 +3,6 @@ * Copyright 2009-2011 Freescale Semiconductor, Inc. * Dave Liu */ -#include #include #include #include diff --git a/drivers/net/qe/uccf.c b/drivers/net/qe/uccf.c index 306f1ea1db6..00848a1a37d 100644 --- a/drivers/net/qe/uccf.c +++ b/drivers/net/qe/uccf.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include #include #include #include diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c index 6195c7c4442..fa9e4065560 100644 --- a/drivers/qe/fdt.c +++ b/drivers/qe/fdt.c @@ -6,7 +6,6 @@ * Wolfgang Denk, DENX Software Engineering, wd@denx.de. */ -#include #include #include #include diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 2825dc6f9aa..736dd8558b6 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -6,7 +6,6 @@ * based on source code of Shlomi Gridish */ -#include #include #include #include diff --git a/include/fsl_qe.h b/include/fsl_qe.h index 48accb8d891..309ca7ea6af 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -9,7 +9,6 @@ #ifndef __QE_H__ #define __QE_H__ -#include "common.h" #ifdef CONFIG_U_QE #include #endif -- cgit v1.3.1 From dd1365c2e93563e589892fded756a18a39bd8815 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:11 -0400 Subject: powerpc: mpc83xx: Rework includes slightly In order to not rely on common.h providing a number of common includes, cleanup what we include directly in order to be able to drop common.h later. Signed-off-by: Tom Rini --- arch/powerpc/cpu/mpc83xx/cpu_init.c | 2 ++ arch/powerpc/cpu/mpc83xx/start.S | 1 + include/mpc83xx.h | 2 -- 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 8e6d3d28fc6..340f9a0da56 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -18,6 +18,8 @@ #ifdef CONFIG_QE #include #endif +#include +#include #include "lblaw/lblaw.h" #include "elbc/elbc.h" diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S index d72d3147f63..ceb54867894 100644 --- a/arch/powerpc/cpu/mpc83xx/start.S +++ b/arch/powerpc/cpu/mpc83xx/start.S @@ -20,6 +20,7 @@ #include #include +#include #include #include "hrcw/hrcw.h" diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 5926c8090a4..aa8803413cd 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -6,8 +6,6 @@ #ifndef __MPC83XX_H__ #define __MPC83XX_H__ -#include -#include #if defined(CONFIG_E300) #include #endif -- cgit v1.3.1 From 678be88bbe5c808bc5c00e86a133ce5dec101517 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:18 -0400 Subject: fsl-mc: Add prototype for bd_info As the functions fsl_mc_ldpaa_init/fsl_mc_ldpaa_exit take a bd_info as an argument, add a struct bd_info to this header file rather than add to the overall chain. Signed-off-by: Tom Rini --- include/fsl-mc/fsl_mc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index 258738dfc8c..de2bba93ecf 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -10,6 +10,8 @@ #include #include +struct bd_info; + #define MC_CCSR_BASE_ADDR \ ((struct mc_ccsr_registers __iomem *)0x8340000) -- cgit v1.3.1 From c675222d04d9c260014f4f38cbc025bec5319cf1 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:19 -0400 Subject: include/linux/mii.h: Add As this file uses u8/u16 we need to bring in here. Signed-off-by: Tom Rini --- include/linux/mii.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/linux/mii.h b/include/linux/mii.h index 49e29ac314a..70689bc53d7 100644 --- a/include/linux/mii.h +++ b/include/linux/mii.h @@ -9,6 +9,8 @@ #ifndef __LINUX_MII_H__ #define __LINUX_MII_H__ +#include + /* Generic MII registers. */ #define MII_BMCR 0x00 /* Basic mode control register */ #define MII_BMSR 0x01 /* Basic mode status register */ -- cgit v1.3.1 From 7f38e9c9a49418fffa233c1a42959ff928415ec4 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 1 Nov 2023 12:28:20 -0400 Subject: include: Drop from include lists At this point, we don't need to have be included because of properties in the header itself, it only includes other common header files. We've also audited the code enough at this point that we can drop from being included in headers and rely on code to have the correct inclusions themselves, or at least . Signed-off-by: Tom Rini --- include/bootcount.h | 1 - include/dfu.h | 1 - include/efi_loader.h | 1 - include/efi_selftest.h | 1 - include/fm_eth.h | 1 - include/fs.h | 1 - include/fsl-mc/fsl_mc.h | 1 - include/fsl_errata.h | 1 - include/fsl_ifc.h | 1 - include/fsl_sec.h | 1 - include/fsl_sec_mon.h | 1 - include/fsl_sfp.h | 1 - include/iotrace.h | 1 - include/key_matrix.h | 1 - include/libata.h | 1 - include/linux/mtd/spinand.h | 1 - include/linux/usb/composite.h | 1 - include/miiphy.h | 1 - include/mv88e6352.h | 1 - include/net/ncsi.h | 1 - include/palmas.h | 1 - include/post.h | 1 - include/spi.h | 1 - include/tegra-kbc.h | 1 - include/twl4030.h | 1 - include/twl6030.h | 1 - include/ubi_uboot.h | 1 - include/usbdevice.h | 1 - 28 files changed, 28 deletions(-) (limited to 'include') diff --git a/include/bootcount.h b/include/bootcount.h index bfa5d464276..bc06e17c9fb 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -6,7 +6,6 @@ #ifndef _BOOTCOUNT_H__ #define _BOOTCOUNT_H__ -#include #include #include #include diff --git a/include/dfu.h b/include/dfu.h index 07922224ef1..68b5ca46ce5 100644 --- a/include/dfu.h +++ b/include/dfu.h @@ -10,7 +10,6 @@ #ifndef __DFU_ENTITY_H_ #define __DFU_ENTITY_H_ -#include #include #include #include diff --git a/include/efi_loader.h b/include/efi_loader.h index e24410505f4..247be060e1c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -8,7 +8,6 @@ #ifndef _EFI_LOADER_H #define _EFI_LOADER_H 1 -#include #include #include #include diff --git a/include/efi_selftest.h b/include/efi_selftest.h index 7c69c3f3761..5bcebb36828 100644 --- a/include/efi_selftest.h +++ b/include/efi_selftest.h @@ -8,7 +8,6 @@ #ifndef _EFI_SELFTEST_H #define _EFI_SELFTEST_H -#include #include #include #include diff --git a/include/fm_eth.h b/include/fm_eth.h index 8b133e703b4..f30110817c7 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -7,7 +7,6 @@ #ifndef __FM_ETH_H__ #define __FM_ETH_H__ -#include #include #include diff --git a/include/fs.h b/include/fs.h index e341a0ed01b..ef540e7c23d 100644 --- a/include/fs.h +++ b/include/fs.h @@ -5,7 +5,6 @@ #ifndef _FS_H #define _FS_H -#include #include struct cmd_tbl; diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index de2bba93ecf..71907bc73c5 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -7,7 +7,6 @@ #ifndef __FSL_MC_H__ #define __FSL_MC_H__ -#include #include struct bd_info; diff --git a/include/fsl_errata.h b/include/fsl_errata.h index 88f4268658a..44547645df8 100644 --- a/include/fsl_errata.h +++ b/include/fsl_errata.h @@ -6,7 +6,6 @@ #ifndef _FSL_ERRATA_H #define _FSL_ERRATA_H -#include #if defined(CONFIG_PPC) #include #elif defined(CONFIG_ARCH_LS1021A) diff --git a/include/fsl_ifc.h b/include/fsl_ifc.h index de1e70a6d0b..f9a0a7017d4 100644 --- a/include/fsl_ifc.h +++ b/include/fsl_ifc.h @@ -9,7 +9,6 @@ #ifdef CONFIG_FSL_IFC #include -#include #include #ifdef CONFIG_ARM #include diff --git a/include/fsl_sec.h b/include/fsl_sec.h index 9dad1d1ec47..8c5e59c5b1c 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -9,7 +9,6 @@ #ifndef __FSL_SEC_H #define __FSL_SEC_H -#include #include #ifdef CONFIG_SYS_FSL_SEC_LE diff --git a/include/fsl_sec_mon.h b/include/fsl_sec_mon.h index 3092a0ea62a..248d5b6d421 100644 --- a/include/fsl_sec_mon.h +++ b/include/fsl_sec_mon.h @@ -8,7 +8,6 @@ #ifndef __FSL_SEC_MON_H #define __FSL_SEC_MON_H -#include #include #ifdef CONFIG_SYS_FSL_SEC_MON_LE diff --git a/include/fsl_sfp.h b/include/fsl_sfp.h index e7674c1bff2..0dec69a7235 100644 --- a/include/fsl_sfp.h +++ b/include/fsl_sfp.h @@ -6,7 +6,6 @@ #ifndef _FSL_SFP_SNVS_ #define _FSL_SFP_SNVS_ -#include #include #include diff --git a/include/iotrace.h b/include/iotrace.h index 7ff2e8332b0..d5610426cc8 100644 --- a/include/iotrace.h +++ b/include/iotrace.h @@ -6,7 +6,6 @@ #ifndef __IOTRACE_H #define __IOTRACE_H -//#include #include /* Support up to the machine word length for now */ diff --git a/include/key_matrix.h b/include/key_matrix.h index e7420b9d795..17f5d12cdd9 100644 --- a/include/key_matrix.h +++ b/include/key_matrix.h @@ -8,7 +8,6 @@ #ifndef _KEY_MATRIX_H #define _KEY_MATRIX_H -#include /* Information about a matrix keyboard */ struct key_matrix { diff --git a/include/libata.h b/include/libata.h index b03b29960df..a55e9315a73 100644 --- a/include/libata.h +++ b/include/libata.h @@ -10,7 +10,6 @@ #ifndef __LIBATA_H__ #define __LIBATA_H__ -#include enum { /* various global constants */ diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h index e8d6feb9705..6d68514e07a 100644 --- a/include/linux/mtd/spinand.h +++ b/include/linux/mtd/spinand.h @@ -17,7 +17,6 @@ #include #include #else -#include #include #include #include diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h index 935e5c0cbb1..bb1eb93bd20 100644 --- a/include/linux/usb/composite.h +++ b/include/linux/usb/composite.h @@ -21,7 +21,6 @@ * the composite model the host can use both functions at the same time. */ -#include #include #include #include diff --git a/include/miiphy.h b/include/miiphy.h index c66a1845b58..5abffd8fb6b 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -14,7 +14,6 @@ #ifndef _miiphy_h_ #define _miiphy_h_ -#include #include #include #include diff --git a/include/mv88e6352.h b/include/mv88e6352.h index 2e810c8183e..152a0774fc0 100644 --- a/include/mv88e6352.h +++ b/include/mv88e6352.h @@ -7,7 +7,6 @@ #ifndef __MV886352_H #define __MV886352_H -#include /* PHY registers */ #define PHY(itf) (itf) diff --git a/include/net/ncsi.h b/include/net/ncsi.h index 2800c842b72..7aec457562d 100644 --- a/include/net/ncsi.h +++ b/include/net/ncsi.h @@ -5,7 +5,6 @@ * Copyright (C) 2019, IBM Corporation. */ -#include #include bool ncsi_active(void); diff --git a/include/palmas.h b/include/palmas.h index e259a4d04ba..c13b67a84d9 100644 --- a/include/palmas.h +++ b/include/palmas.h @@ -6,7 +6,6 @@ #ifndef PALMAS_H #define PALMAS_H -#include #include /* I2C chip addresses, TW6035/37 */ diff --git a/include/post.h b/include/post.h index 6e88d550722..da851e37fa2 100644 --- a/include/post.h +++ b/include/post.h @@ -11,7 +11,6 @@ #define _POST_H #ifndef __ASSEMBLY__ -#include #include #if defined(CONFIG_POST) diff --git a/include/spi.h b/include/spi.h index 1bc18e65525..7e38cc2a2ad 100644 --- a/include/spi.h +++ b/include/spi.h @@ -9,7 +9,6 @@ #ifndef _SPI_H_ #define _SPI_H_ -#include #include /* SPI mode flags */ diff --git a/include/tegra-kbc.h b/include/tegra-kbc.h index f331c79c9d5..1208b75ee78 100644 --- a/include/tegra-kbc.h +++ b/include/tegra-kbc.h @@ -7,7 +7,6 @@ #ifndef __include_tegra_kbc_h__ #define __include_tegra_kbc_h__ -#include #define KEY_IS_MODIFIER(key) ((key) >= KEY_FIRST_MODIFIER) diff --git a/include/twl4030.h b/include/twl4030.h index 0a6d85a7c1c..ee80bb1f6b9 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -11,7 +11,6 @@ #ifndef TWL4030_H #define TWL4030_H -#include #include /* I2C chip addresses */ diff --git a/include/twl6030.h b/include/twl6030.h index 05d476f8048..e3a1058091a 100644 --- a/include/twl6030.h +++ b/include/twl6030.h @@ -7,7 +7,6 @@ #ifndef TWL6030_H #define TWL6030_H -#include #include /* I2C chip addresses */ diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index 6da348eb628..d7a8851094b 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -14,7 +14,6 @@ #ifndef __UBOOT_UBI_H #define __UBOOT_UBI_H -#include #include #include #include diff --git a/include/usbdevice.h b/include/usbdevice.h index 80c5af0cbcd..e59f5587eea 100644 --- a/include/usbdevice.h +++ b/include/usbdevice.h @@ -17,7 +17,6 @@ #ifndef __USBDCORE_H__ #define __USBDCORE_H__ -#include #include "usbdescriptors.h" -- cgit v1.3.1 From b630f8b3aefc2d11cdc73314743a6fb16deaf4c5 Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Fri, 27 Oct 2023 20:59:51 -0400 Subject: scsi: Forceably finish migration to DM_SCSI The migration deadline for moving to DM_SCSI was v2023.04. A further reminder was sent out in August 2023 to the remaining platforms that had not migrated already, and that a few more over the line (or configs deleted). With this commit we: - Rename CONFIG_DM_SCSI to CONFIG_SCSI. - Remove all of the non-DM SCSI code. This includes removing other legacy symbols and code and removes some legacy non-DM AHCI code. - Some platforms that had previously been DM_SCSI=y && SCSI=n are now fully migrated to DM_SCSI as a few corner cases in the code assumed DM_SCSI=y meant SCSI=y. Signed-off-by: Tom Rini --- Makefile | 1 - api/api_storage.c | 7 -- arch/Kconfig | 2 +- arch/arm/Kconfig | 4 +- arch/arm/mach-imx/mx6/Kconfig | 2 +- arch/arm/mach-mvebu/cpu.c | 9 -- arch/arm/mach-omap2/Makefile | 7 -- arch/arm/mach-omap2/boot-common.c | 7 -- arch/arm/mach-omap2/omap5/hw_data.c | 12 -- arch/arm/mach-omap2/pipe3-phy.c | 231 ------------------------------------ arch/arm/mach-omap2/pipe3-phy.h | 35 ------ arch/arm/mach-omap2/sata.c | 72 ----------- board/emulation/qemu-riscv/Kconfig | 1 - board/highbank/highbank.c | 13 -- cmd/scsi.c | 3 - common/board_r.c | 15 --- configs/apalis_imx6_defconfig | 3 +- configs/dh_imx6_defconfig | 3 +- configs/edison_defconfig | 1 + configs/efi-x86_app32_defconfig | 1 + configs/efi-x86_app64_defconfig | 1 + configs/galileo_defconfig | 1 + configs/mvebu_ac5_rd_defconfig | 3 +- configs/novena_defconfig | 1 + configs/udoo_defconfig | 3 +- configs/wandboard_defconfig | 3 +- configs/x240_defconfig | 3 +- drivers/ata/Kconfig | 18 +-- drivers/ata/Makefile | 1 - drivers/ata/ahci.c | 172 +-------------------------- drivers/ata/sata.c | 58 --------- drivers/ata/sata_sandbox.c | 33 ------ drivers/scsi/Kconfig | 43 +------ drivers/scsi/Makefile | 17 +-- drivers/scsi/scsi.c | 151 ----------------------- drivers/ufs/Kconfig | 2 +- include/ahci.h | 3 - include/configs/ls1021aiot.h | 7 -- include/configs/ls1028ardb.h | 5 - include/configs/ls1043ardb.h | 7 -- include/sata.h | 16 --- include/scsi.h | 9 -- 42 files changed, 34 insertions(+), 952 deletions(-) delete mode 100644 arch/arm/mach-omap2/pipe3-phy.c delete mode 100644 arch/arm/mach-omap2/pipe3-phy.h delete mode 100644 arch/arm/mach-omap2/sata.c delete mode 100644 drivers/ata/sata_sandbox.c (limited to 'include') diff --git a/Makefile b/Makefile index bedcef4b9a4..b2e9cd3cb21 100644 --- a/Makefile +++ b/Makefile @@ -1153,7 +1153,6 @@ endif @# is enable to tell 'deprecated' that one of these symbols exists $(call deprecated,CONFIG_TIMER,Timer drivers,v2023.01,$(if $(strip $(CFG_SYS_TIMER_RATE)$(CFG_SYS_TIMER_COUNTER)),x)) $(call deprecated,CONFIG_DM_SERIAL,Serial drivers,v2023.04,$(CONFIG_SERIAL)) - $(call deprecated,CONFIG_DM_SCSI,SCSI drivers,v2023.04,$(CONFIG_SCSI)) @# Check that this build does not override OF_HAS_PRIOR_STAGE by @# disabling OF_BOARD. $(call cmd,ofcheck,$(KCONFIG_CONFIG)) diff --git a/api/api_storage.c b/api/api_storage.c index 997e8727a96..78becbe39fb 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -67,13 +67,6 @@ void dev_stor_init(void) specs[ENUM_SATA].type = DEV_TYP_STOR | DT_STOR_SATA; specs[ENUM_SATA].name = "sata"; #endif -#if defined(CONFIG_SCSI) - specs[ENUM_SCSI].max_dev = SCSI_MAX_DEVICE; - specs[ENUM_SCSI].enum_started = 0; - specs[ENUM_SCSI].enum_ended = 0; - specs[ENUM_SCSI].type = DEV_TYP_STOR | DT_STOR_SCSI; - specs[ENUM_SCSI].name = "scsi"; -#endif #if defined(CONFIG_CMD_USB) && defined(CONFIG_USB_STORAGE) specs[ENUM_USB].max_dev = USB_MAX_STOR_DEV; specs[ENUM_USB].enum_started = 0; diff --git a/arch/Kconfig b/arch/Kconfig index 1cdcd1fdb8b..2e0528d819c 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -251,7 +251,7 @@ config X86 imply DM_KEYBOARD imply DM_MMC imply DM_RTC - imply DM_SCSI + imply SCSI imply DM_SERIAL imply DM_SPI imply DM_SPI_FLASH diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c984..6009b7d46dc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1133,7 +1133,6 @@ config ARCH_SUNXI select DM_SPI_FLASH if SPI select DM_KEYBOARD select DM_MMC if MMC - select DM_SCSI if SCSI select DM_SERIAL select OF_BOARD_SETUP select OF_CONTROL @@ -1838,7 +1837,7 @@ config TARGET_SL28 select PCI select DM_RNG select DM_RTC - select DM_SCSI + select SCSI select DM_SERIAL select DM_SPI select GPIO_EXTRA_HEADER @@ -2053,7 +2052,6 @@ config TARGET_POMELO select PCI select DM_PCI select SCSI - select DM_SCSI select DM_SERIAL imply CMD_PCI help diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7529b311f80..50a9c3e4203 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -246,7 +246,7 @@ config TARGET_KOSAGI_NOVENA select DM_GPIO select DM_MMC select PCI - select DM_SCSI + select SCSI select VIDEO select OF_CONTROL select SUPPORT_SPL diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c index 6deffb81836..8e0de935385 100644 --- a/arch/arm/mach-mvebu/cpu.c +++ b/arch/arm/mach-mvebu/cpu.c @@ -589,15 +589,6 @@ int board_ahci_enable(void) return 0; } -#ifdef CONFIG_SCSI_AHCI_PLAT -void scsi_init(void) -{ - printf("MVEBU SATA INIT\n"); - board_ahci_enable(); - ahci_init((void __iomem *)MVEBU_SATA0_BASE); -} -#endif - #ifdef CONFIG_USB_XHCI_MVEBU #define USB3_MAX_WINDOWS 4 #define USB3_WIN_CTRL(w) (0x0 + ((w) * 8)) diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index bb01eab80e6..8c10c694dff 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -27,13 +27,6 @@ obj-y += vc.o obj-y += abb.o endif -ifneq ($(CONFIG_OMAP54XX),) -ifeq ($(CONFIG_DM_SCSI),) -obj-y += pipe3-phy.o -obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o -endif -endif - ifeq ($(CONFIG_$(SPL_TPL_)SYS_DCACHE_OFF),) obj-y += omap-cache.o endif diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index a2dd5f6df01..5e4d29910c9 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -309,13 +309,6 @@ void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) } #endif -#ifdef CONFIG_SCSI_AHCI_PLAT -void arch_preboot_os(void) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); -} -#endif - #ifdef CONFIG_TI_SECURE_DEVICE void board_fit_image_post_process(const void *fit, int node, void **p_image, size_t *p_size) diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index e6bee48dfcb..b39132222ee 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -485,9 +485,6 @@ void enable_basic_clocks(void) (*prcm)->cm_l4per_gpio6_clkctrl, (*prcm)->cm_l4per_gpio7_clkctrl, (*prcm)->cm_l4per_gpio8_clkctrl, -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_ocp2scp3_clkctrl, -#endif 0 }; @@ -506,9 +503,6 @@ void enable_basic_clocks(void) #ifdef CONFIG_TI_QSPI (*prcm)->cm_l4per_qspi_clkctrl, -#endif -#ifdef CONFIG_SCSI_AHCI_PLAT - (*prcm)->cm_l3init_sata_clkctrl, #endif 0 }; @@ -542,12 +536,6 @@ void enable_basic_clocks(void) setbits_le32((*prcm)->cm_l4per_qspi_clkctrl, (1<<24)); #endif -#ifdef CONFIG_SCSI_AHCI_PLAT - /* Enable optional functional clock for SATA */ - setbits_le32((*prcm)->cm_l3init_sata_clkctrl, - SATA_CLKCTRL_OPTFCLKEN_MASK); -#endif - /* Enable SCRM OPT clocks for PER and CORE dpll */ setbits_le32((*prcm)->cm_wkupaon_scrm_clkctrl, OPTFCLKEN_SCRM_PER_MASK); diff --git a/arch/arm/mach-omap2/pipe3-phy.c b/arch/arm/mach-omap2/pipe3-phy.c deleted file mode 100644 index 3dfb184c430..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.c +++ /dev/null @@ -1,231 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "pipe3-phy.h" - -/* PLLCTRL Registers */ -#define PLL_STATUS 0x00000004 -#define PLL_GO 0x00000008 -#define PLL_CONFIGURATION1 0x0000000C -#define PLL_CONFIGURATION2 0x00000010 -#define PLL_CONFIGURATION3 0x00000014 -#define PLL_CONFIGURATION4 0x00000020 - -#define PLL_REGM_MASK 0x001FFE00 -#define PLL_REGM_SHIFT 9 -#define PLL_REGM_F_MASK 0x0003FFFF -#define PLL_REGM_F_SHIFT 0 -#define PLL_REGN_MASK 0x000001FE -#define PLL_REGN_SHIFT 1 -#define PLL_SELFREQDCO_MASK 0x0000000E -#define PLL_SELFREQDCO_SHIFT 1 -#define PLL_SD_MASK 0x0003FC00 -#define PLL_SD_SHIFT 10 -#define SET_PLL_GO 0x1 -#define PLL_TICOPWDN BIT(16) -#define PLL_LDOPWDN BIT(15) -#define PLL_LOCK 0x2 -#define PLL_IDLE 0x1 - -/* PHY POWER CONTROL Register */ -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK 0x003FC000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT 0xE - -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK 0xFFC00000 -#define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT 0x16 - -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON 0x3 -#define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF 0x0 - - -#define PLL_IDLE_TIME 100 /* in milliseconds */ -#define PLL_LOCK_TIME 100 /* in milliseconds */ - -static inline u32 omap_pipe3_readl(void __iomem *addr, unsigned offset) -{ - return __raw_readl(addr + offset); -} - -static inline void omap_pipe3_writel(void __iomem *addr, unsigned offset, - u32 data) -{ - __raw_writel(data, addr + offset); -} - -static struct pipe3_dpll_params *omap_pipe3_get_dpll_params(struct omap_pipe3 - *pipe3) -{ - u32 rate; - struct pipe3_dpll_map *dpll_map = pipe3->dpll_map; - - rate = get_sys_clk_freq(); - - for (; dpll_map->rate; dpll_map++) { - if (rate == dpll_map->rate) - return &dpll_map->params; - } - - printf("%s: No DPLL configuration for %u Hz SYS CLK\n", - __func__, rate); - return NULL; -} - - -static int omap_pipe3_wait_lock(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_LOCK_TIME; - - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (val & PLL_LOCK) - break; - } while (--timeout); - - if (!(val & PLL_LOCK)) { - printf("%s: DPLL failed to lock\n", __func__); - return -EBUSY; - } - - return 0; -} - -static int omap_pipe3_dpll_program(struct omap_pipe3 *phy) -{ - u32 val; - struct pipe3_dpll_params *dpll_params; - - dpll_params = omap_pipe3_get_dpll_params(phy); - if (!dpll_params) { - printf("%s: Invalid DPLL parameters\n", __func__); - return -EINVAL; - } - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGN_MASK; - val |= dpll_params->n << PLL_REGN_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val &= ~PLL_SELFREQDCO_MASK; - val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION1); - val &= ~PLL_REGM_MASK; - val |= dpll_params->m << PLL_REGM_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION1, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION4); - val &= ~PLL_REGM_F_MASK; - val |= dpll_params->mf << PLL_REGM_F_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION4, val); - - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION3); - val &= ~PLL_SD_MASK; - val |= dpll_params->sd << PLL_SD_SHIFT; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION3, val); - - omap_pipe3_writel(phy->pll_ctrl_base, PLL_GO, SET_PLL_GO); - - return omap_pipe3_wait_lock(phy); -} - -static void omap_control_phy_power(struct omap_pipe3 *phy, int on) -{ - u32 val, rate; - - val = readl(phy->power_reg); - - rate = get_sys_clk_freq(); - rate = rate/1000000; - - if (on) { - val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK | - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK); - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - val |= rate << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT; - } else { - val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK; - val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF << - OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT; - } - - writel(val, phy->power_reg); -} - -int phy_pipe3_power_on(struct omap_pipe3 *phy) -{ - int ret; - u32 val; - - /* Program the DPLL only if not locked */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if (!(val & PLL_LOCK)) { - ret = omap_pipe3_dpll_program(phy); - if (ret) - return ret; - } else { - /* else just bring it out of IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - if (val & PLL_IDLE) { - val &= ~PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, - PLL_CONFIGURATION2, val); - ret = omap_pipe3_wait_lock(phy); - if (ret) - return ret; - } - } - - /* Power up the PHY */ - omap_control_phy_power(phy, 1); - - return 0; -} - -int phy_pipe3_power_off(struct omap_pipe3 *phy) -{ - u32 val; - int timeout = PLL_IDLE_TIME; - - /* Power down the PHY */ - omap_control_phy_power(phy, 0); - - /* Put DPLL in IDLE mode */ - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_CONFIGURATION2); - val |= PLL_IDLE; - omap_pipe3_writel(phy->pll_ctrl_base, PLL_CONFIGURATION2, val); - - /* wait for LDO and Oscillator to power down */ - do { - mdelay(1); - val = omap_pipe3_readl(phy->pll_ctrl_base, PLL_STATUS); - if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN)) - break; - } while (--timeout); - - if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) { - printf("%s: Failed to power down DPLL: PLL_STATUS 0x%x\n", - __func__, val); - return -EBUSY; - } - - return 0; -} diff --git a/arch/arm/mach-omap2/pipe3-phy.h b/arch/arm/mach-omap2/pipe3-phy.h deleted file mode 100644 index 182bdcd4c81..00000000000 --- a/arch/arm/mach-omap2/pipe3-phy.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * TI PIPE3 PHY - * - * (C) Copyright 2013 - * Texas Instruments, - */ - -#ifndef __OMAP_PIPE3_PHY_H -#define __OMAP_PIPE3_PHY_H - -struct pipe3_dpll_params { - u16 m; - u8 n; - u8 freq:3; - u8 sd; - u32 mf; -}; - -struct pipe3_dpll_map { - unsigned long rate; - struct pipe3_dpll_params params; -}; - -struct omap_pipe3 { - void __iomem *pll_ctrl_base; - void __iomem *power_reg; - struct pipe3_dpll_map *dpll_map; -}; - - -int phy_pipe3_power_on(struct omap_pipe3 *phy); -int phy_pipe3_power_off(struct omap_pipe3 *pipe3); - -#endif /* __OMAP_PIPE3_PHY_H */ diff --git a/arch/arm/mach-omap2/sata.c b/arch/arm/mach-omap2/sata.c deleted file mode 100644 index 53c39ce1fb6..00000000000 --- a/arch/arm/mach-omap2/sata.c +++ /dev/null @@ -1,72 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * TI SATA platform driver - * - * (C) Copyright 2013 - * Texas Instruments, - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "pipe3-phy.h" - -static struct pipe3_dpll_map dpll_map_sata[] = { - {12000000, {1000, 7, 4, 6, 0} }, /* 12 MHz */ - {16800000, {714, 7, 4, 6, 0} }, /* 16.8 MHz */ - {19200000, {625, 7, 4, 6, 0} }, /* 19.2 MHz */ - {20000000, {600, 7, 4, 6, 0} }, /* 20 MHz */ - {26000000, {461, 7, 4, 6, 0} }, /* 26 MHz */ - {38400000, {312, 7, 4, 6, 0} }, /* 38.4 MHz */ - { }, /* Terminator */ -}; - -struct omap_pipe3 sata_phy = { - .pll_ctrl_base = (void __iomem *)TI_SATA_PLLCTRL_BASE, - /* .power_reg is updated at runtime */ - .dpll_map = dpll_map_sata, -}; - -int init_sata(int dev) -{ - int ret; - u32 val; - - sata_phy.power_reg = (void __iomem *)(*ctrl)->control_phy_power_sata; - - /* Power up the PHY */ - phy_pipe3_power_on(&sata_phy); - - /* Enable SATA module, No Idle, No Standby */ - val = TI_SATA_IDLE_NO | TI_SATA_STANDBY_NO; - writel(val, TI_SATA_WRAPPER_BASE + TI_SATA_SYSCONFIG); - - ret = ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return ret; -} - -int reset_sata(int dev) -{ - return 0; -} - -/* On OMAP platforms SATA provides the SCSI subsystem */ -void scsi_init(void) -{ - init_sata(0); - scsi_scan(1); -} - -int scsi_bus_reset(struct udevice *dev) -{ - ahci_reset((void __iomem *)DWC_AHSATA_BASE); - ahci_init((void __iomem *)DWC_AHSATA_BASE); - - return 0; -} diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index d56b4b5bc1e..108e9fdb00a 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -59,7 +59,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy imply PCIE_ECAM_GENERIC imply DM_RNG imply SCSI - imply DM_SCSI imply SYS_NS16550 imply SIFIVE_SERIAL imply HTIF_CONSOLE if 64BIT diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index b5fa5101e88..7f67d1e4530 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -52,19 +52,6 @@ int board_init(void) return 0; } -#ifdef CONFIG_SCSI_AHCI_PLAT -void scsi_init(void) -{ - u32 reg = readl(HB_SREG_A9_PWRDOM_STAT); - - cphy_disable_overrides(); - if (reg & PWRDOM_STAT_SATA) { - ahci_init((void __iomem *)HB_AHCI_BASE); - scsi_scan(true); - } -} -#endif - #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { diff --git a/cmd/scsi.c b/cmd/scsi.c index 4549995ba73..c501d7f456d 100644 --- a/cmd/scsi.c +++ b/cmd/scsi.c @@ -34,9 +34,6 @@ static int do_scsi(struct cmd_tbl *cmdtp, int flag, int argc, if (argc == 2) { if (strncmp(argv[1], "res", 3) == 0) { printf("\nReset SCSI\n"); -#ifndef CONFIG_DM_SCSI - scsi_bus_reset(NULL); -#endif ret = scsi_scan(true); if (ret) return CMD_RET_FAILURE; diff --git a/common/board_r.c b/common/board_r.c index a7967849dc0..da0b80f24ff 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -472,17 +472,6 @@ static int initr_status_led(void) } #endif -#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) -static int initr_scsi(void) -{ - puts("SCSI: "); - scsi_init(); - puts("\n"); - - return 0; -} -#endif - #ifdef CONFIG_CMD_NET static int initr_net(void) { @@ -732,10 +721,6 @@ static init_fnc_t init_sequence_r[] = { #ifdef CONFIG_BOARD_LATE_INIT board_late_init, #endif -#if defined(CONFIG_SCSI) && !defined(CONFIG_DM_SCSI) - INIT_FUNC_WATCHDOG_RESET - initr_scsi, -#endif #ifdef CONFIG_BITBANGMII bb_miiphy_init, #endif diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index aa9cf77960b..cf2af5797f3 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_I2C=y # CONFIG_CMD_LOADB is not set # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_SDP=y CONFIG_CMD_USB_MASS_STORAGE=y @@ -105,7 +106,7 @@ CONFIG_DM_PMIC_PFUZE100=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PFUZE100=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 5a83b6a08a2..154131e62e0 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -52,6 +52,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_USB_MASS_STORAGE=y CONFIG_CMD_WDT=y @@ -99,7 +100,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index f134680e412..db2e35f388b 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_DFU=y CONFIG_CMD_GPT=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_TIMER=y CONFIG_CMD_HASH=y CONFIG_CMD_EXT4=y diff --git a/configs/efi-x86_app32_defconfig b/configs/efi-x86_app32_defconfig index dfc315774a5..682ba5b8957 100644 --- a/configs/efi-x86_app32_defconfig +++ b/configs/efi-x86_app32_defconfig @@ -20,6 +20,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set # CONFIG_CMD_NET is not set CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y diff --git a/configs/efi-x86_app64_defconfig b/configs/efi-x86_app64_defconfig index e0cfe3ee243..d6b6c3d8299 100644 --- a/configs/efi-x86_app64_defconfig +++ b/configs/efi-x86_app64_defconfig @@ -21,6 +21,7 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTZ=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set # CONFIG_CMD_NET is not set CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y diff --git a/configs/galileo_defconfig b/configs/galileo_defconfig index 3eb1917454d..35f7fb77e63 100644 --- a/configs/galileo_defconfig +++ b/configs/galileo_defconfig @@ -23,6 +23,7 @@ CONFIG_CMD_CPU=y CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/mvebu_ac5_rd_defconfig b/configs/mvebu_ac5_rd_defconfig index e8fa22b648b..0a9adcc0399 100644 --- a/configs/mvebu_ac5_rd_defconfig +++ b/configs/mvebu_ac5_rd_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -72,7 +73,7 @@ CONFIG_PINCTRL_ARMADA_8K=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_SYS_NS16550=y CONFIG_MVEBU_A3700_SPI=y CONFIG_DM_THERMAL=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 278e3fd8adb..23899911882 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -48,6 +48,7 @@ CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index e128a62cd00..f89b163ddf5 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -34,6 +34,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_MMC=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y @@ -54,7 +55,7 @@ CONFIG_FEC_MXC=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 7c1727f8b12..c9ec962201b 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -45,6 +45,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_SATA=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_USB=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y @@ -71,7 +72,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_PMIC_PFUZE100=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_DM_THERMAL=y diff --git a/configs/x240_defconfig b/configs/x240_defconfig index 4b1a761a908..152413de0e5 100644 --- a/configs/x240_defconfig +++ b/configs/x240_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y +# CONFIG_CMD_SCSI is not set CONFIG_CMD_SPI=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set @@ -68,7 +69,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RTC=y CONFIG_RTC_MAX313XX=y -CONFIG_DM_SCSI=y +CONFIG_SCSI=y CONFIG_SYS_NS16550=y CONFIG_MVEBU_A3700_SPI=y CONFIG_DM_THERMAL=y diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 049f7efd10b..9bc5283c268 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -20,14 +20,6 @@ config SATA See also CMD_SATA which provides command-line support. -config SYS_SATA_MAX_PORTS - int "Maximum supported SATA ports" - depends on SCSI_AHCI && !DM_SCSI - default 1 - help - Sets the maximum number of ports to scan when looking for devices. - Ports from 0 to (this value - 1) are scanned. - config LIBATA bool help @@ -44,7 +36,7 @@ menu "SATA/SCSI device support" config AHCI_PCI bool "Support for PCI-based AHCI controller" depends on PCI - depends on DM_SCSI + depends on SCSI depends on SCSI_AHCI help Enables support for the PCI-based AHCI controller. @@ -55,13 +47,13 @@ config SPL_AHCI_PCI bool "Support for PCI-based AHCI controller for SPL" depends on SPL depends on SPL_PCI - depends on SPL_SATA && DM_SCSI + depends on SPL_SATA && SCSI config DWC_AHCI bool "Enable Synopsys DWC AHCI driver support" select SCSI_AHCI select PHY - depends on DM_SCSI + depends on SCSI help Enable this driver to support Sata devices through Synopsys DWC AHCI module. @@ -91,7 +83,7 @@ config AHCI_MVEBU bool "Marvell EBU AHCI SATA support" depends on ARCH_MVEBU || ARCH_OCTEON select SCSI_AHCI - select DM_SCSI + select SCSI help This option enables support for the Marvell EBU SoC's onboard AHCI SATA. @@ -112,7 +104,7 @@ if SATA config SATA_CEVA bool "Ceva Sata controller" depends on AHCI - depends on DM_SCSI + depends on SCSI help This option enables Ceva Sata controller hard IP available on Xilinx ZynqMP. Support up to 2 external devices. Compliant with SATA 3.1 and diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 0b6f91098a3..af6f0bf2780 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -14,7 +14,6 @@ obj-$(CONFIG_SATA) += sata.o sata_bootdev.o obj-$(CONFIG_SATA_CEVA) += sata_ceva.o obj-$(CONFIG_SATA_MV) += sata_mv.o obj-$(CONFIG_SATA_SIL) += sata_sil.o -obj-$(CONFIG_SANDBOX) += sata_sandbox.o obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o obj-$(CONFIG_SUNXI_AHCI) += ahci_sunxi.o obj-$(CONFIG_MTK_AHCI) += mtk_ahci.o diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c index cb2c648a91f..04ddc339464 100644 --- a/drivers/ata/ahci.c +++ b/drivers/ata/ahci.c @@ -33,10 +33,6 @@ static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port); -#ifndef CONFIG_DM_SCSI -struct ahci_uc_priv *probe_ent = NULL; -#endif - #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) /* @@ -169,11 +165,6 @@ int ahci_reset(void __iomem *base) static int ahci_host_init(struct ahci_uc_priv *uc_priv) { -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - struct udevice *dev = uc_priv->dev; - struct pci_child_plat *pplat = dev_get_parent_plat(dev); - u16 tmp16; -#endif void __iomem *mmio = uc_priv->mmio_base; u32 tmp, cap_save, cmd; int i, j, ret; @@ -194,14 +185,6 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) writel(cap_save, mmio + HOST_CAP); writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - if (pplat->vendor == PCI_VENDOR_ID_INTEL) { - u16 tmp16; - - dm_pci_read_config16(dev, 0x92, &tmp16); - dm_pci_write_config16(dev, 0x92, tmp16 | 0xf); - } -#endif uc_priv->cap = readl(mmio + HOST_CAP); uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL); port_map = uc_priv->port_map; @@ -210,11 +193,6 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) debug("cap 0x%x port_map 0x%x n_ports %d\n", uc_priv->cap, uc_priv->port_map, uc_priv->n_ports); -#if !defined(CONFIG_DM_SCSI) - if (uc_priv->n_ports > CONFIG_SYS_SATA_MAX_PORTS) - uc_priv->n_ports = CONFIG_SYS_SATA_MAX_PORTS; -#endif - for (i = 0; i < uc_priv->n_ports; i++) { if (!(port_map & (1 << i))) continue; @@ -313,23 +291,12 @@ static int ahci_host_init(struct ahci_uc_priv *uc_priv) writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); tmp = readl(mmio + HOST_CTL); debug("HOST_CTL 0x%x\n", tmp); -#if !defined(CONFIG_DM_SCSI) -#ifndef CONFIG_SCSI_AHCI_PLAT - dm_pci_read_config16(dev, PCI_COMMAND, &tmp16); - tmp |= PCI_COMMAND_MASTER; - dm_pci_write_config16(dev, PCI_COMMAND, tmp16); -#endif -#endif return 0; } static void ahci_print_info(struct ahci_uc_priv *uc_priv) { -#if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI) - struct udevice *dev = uc_priv->dev; - u16 cc; -#endif void __iomem *mmio = uc_priv->mmio_base; u32 vers, cap, cap2, impl, speed; const char *speed_s; @@ -350,19 +317,7 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) else speed_s = "?"; -#if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI) scc_s = "SATA"; -#else - dm_pci_read_config16(dev, 0x0a, &cc); - if (cc == 0x0101) - scc_s = "IDE"; - else if (cc == 0x0106) - scc_s = "SATA"; - else if (cc == 0x0104) - scc_s = "RAID"; - else - scc_s = "unknown"; -#endif printf("AHCI %02x%02x.%02x%02x " "%u slots %u ports %s Gbps 0x%x impl %s mode\n", (vers >> 24) & 0xff, @@ -397,12 +352,8 @@ static void ahci_print_info(struct ahci_uc_priv *uc_priv) cap2 & (1 << 0) ? "boh " : ""); } -#if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT) static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) { -#if !defined(CONFIG_DM_SCSI) - u16 vendor; -#endif int rc; uc_priv->dev = dev; @@ -415,21 +366,8 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) uc_priv->pio_mask = 0x1f; uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ -#if !defined(CONFIG_DM_SCSI) - uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5, 0, 0, - PCI_REGION_TYPE, PCI_REGION_MEM); - - /* Take from kernel: - * JMicron-specific fixup: - * make sure we're in AHCI mode - */ - dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor); - if (vendor == 0x197b) - dm_pci_write_config8(dev, 0x41, 0xa1); -#else struct scsi_plat *plat = dev_get_uclass_plat(dev); uc_priv->mmio_base = (void *)plat->base; -#endif debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base); /* initialize adapter */ @@ -444,7 +382,6 @@ static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev) err_out: return rc; } -#endif #define MAX_DATA_BYTE_COUNT (4*1024*1024) @@ -893,12 +830,7 @@ static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv, static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) { - struct ahci_uc_priv *uc_priv; -#ifdef CONFIG_DM_SCSI - uc_priv = dev_get_uclass_priv(dev->parent); -#else - uc_priv = probe_ent; -#endif + struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev->parent); int ret; switch (pccb->cmd[0]) { @@ -953,41 +885,12 @@ static int ahci_start_ports(struct ahci_uc_priv *uc_priv) return 0; } -#ifndef CONFIG_DM_SCSI -void scsi_low_level_init(int busdevfunc) -{ - struct ahci_uc_priv *uc_priv; - -#ifndef CONFIG_SCSI_AHCI_PLAT - probe_ent = calloc(1, sizeof(struct ahci_uc_priv)); - if (!probe_ent) { - printf("%s: No memory for uc_priv\n", __func__); - return; - } - uc_priv = probe_ent; - struct udevice *dev; - int ret; - - ret = dm_pci_bus_find_bdf(busdevfunc, &dev); - if (ret) - return; - ahci_init_one(uc_priv, dev); -#else - uc_priv = probe_ent; -#endif - - ahci_start_ports(uc_priv); -} -#endif - -#ifndef CONFIG_SCSI_AHCI_PLAT int ahci_init_one_dm(struct udevice *dev) { struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); return ahci_init_one(uc_priv, dev); } -#endif int ahci_start_ports_dm(struct udevice *dev) { @@ -996,65 +899,6 @@ int ahci_start_ports_dm(struct udevice *dev) return ahci_start_ports(uc_priv); } -#ifdef CONFIG_SCSI_AHCI_PLAT -static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base) -{ - int rc; - - uc_priv->host_flags = ATA_FLAG_SATA - | ATA_FLAG_NO_LEGACY - | ATA_FLAG_MMIO - | ATA_FLAG_PIO_DMA - | ATA_FLAG_NO_ATAPI; - uc_priv->pio_mask = 0x1f; - uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ - - uc_priv->mmio_base = base; - - /* initialize adapter */ - rc = ahci_host_init(uc_priv); - if (rc) - goto err_out; - - ahci_print_info(uc_priv); - - rc = ahci_start_ports(uc_priv); - -err_out: - return rc; -} - -#ifndef CONFIG_DM_SCSI -int ahci_init(void __iomem *base) -{ - struct ahci_uc_priv *uc_priv; - - probe_ent = malloc(sizeof(struct ahci_uc_priv)); - if (!probe_ent) { - printf("%s: No memory for uc_priv\n", __func__); - return -ENOMEM; - } - - uc_priv = probe_ent; - memset(uc_priv, 0, sizeof(struct ahci_uc_priv)); - - return ahci_init_common(uc_priv, base); -} -#endif - -int ahci_init_dm(struct udevice *dev, void __iomem *base) -{ - struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev); - - return ahci_init_common(uc_priv, base); -} - -void __weak scsi_init(void) -{ -} - -#endif /* CONFIG_SCSI_AHCI_PLAT */ - /* * In the general case of generic rotating media it makes sense to have a * flush capability. It probably even makes sense in the case of SSDs because @@ -1098,7 +942,6 @@ static int ahci_scsi_bus_reset(struct udevice *dev) return 0; } -#ifdef CONFIG_DM_SCSI int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp) { struct udevice *dev; @@ -1190,16 +1033,3 @@ U_BOOT_DRIVER(ahci_scsi) = { .id = UCLASS_SCSI, .ops = &scsi_ops, }; -#else -int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb) -{ - return ahci_scsi_exec(dev, pccb); -} - -__weak int scsi_bus_reset(struct udevice *dev) -{ - return ahci_scsi_bus_reset(dev); - - return 0; -} -#endif diff --git a/drivers/ata/sata.c b/drivers/ata/sata.c index dcb5fcf476b..be1ee01b296 100644 --- a/drivers/ata/sata.c +++ b/drivers/ata/sata.c @@ -18,10 +18,6 @@ #include #include -#ifndef CONFIG_AHCI -struct blk_desc sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE]; -#endif - int sata_reset(struct udevice *dev) { struct ahci_ops *ops = ahci_get_ops(dev); @@ -88,15 +84,6 @@ int sata_rescan(bool verbose) return ret; } -#ifndef CONFIG_AHCI -#ifdef CONFIG_PARTITIONS -struct blk_desc *sata_get_dev(int dev) -{ - return (dev < CONFIG_SYS_SATA_MAX_DEVICE) ? &sata_dev_desc[dev] : NULL; -} -#endif -#endif - static unsigned long sata_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst) { @@ -109,51 +96,6 @@ static unsigned long sata_bwrite(struct udevice *dev, lbaint_t start, return -ENOSYS; } -#ifndef CONFIG_AHCI -int __sata_initialize(void) -{ - int rc, ret = -1; - int i; - - for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) { - memset(&sata_dev_desc[i], 0, sizeof(struct blk_desc)); - sata_dev_desc[i].uclass_id = UCLASS_AHCI; - sata_dev_desc[i].devnum = i; - sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN; - sata_dev_desc[i].type = DEV_TYPE_HARDDISK; - sata_dev_desc[i].lba = 0; - sata_dev_desc[i].blksz = 512; - sata_dev_desc[i].log2blksz = LOG2(sata_dev_desc[i].blksz); - rc = init_sata(i); - if (!rc) { - rc = scan_sata(i); - if (!rc && sata_dev_desc[i].lba > 0 && - sata_dev_desc[i].blksz > 0) { - part_init(&sata_dev_desc[i]); - ret = i; - } - } - } - - return ret; -} -int sata_initialize(void) __attribute__((weak, alias("__sata_initialize"))); - -__weak int __sata_stop(void) -{ - int i, err = 0; - - for (i = 0; i < CONFIG_SYS_SATA_MAX_DEVICE; i++) - err |= reset_sata(i); - - if (err) - printf("Could not reset some SATA devices\n"); - - return err; -} -int sata_stop(void) __attribute__((weak, alias("__sata_stop"))); -#endif - static const struct blk_ops sata_blk_ops = { .read = sata_bread, .write = sata_bwrite, diff --git a/drivers/ata/sata_sandbox.c b/drivers/ata/sata_sandbox.c deleted file mode 100644 index e64cc4a5c10..00000000000 --- a/drivers/ata/sata_sandbox.c +++ /dev/null @@ -1,33 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2015 Google, Inc - * Written by Simon Glass - */ - -#include -#include - -int init_sata(int dev) -{ - return 0; -} - -int reset_sata(int dev) -{ - return 0; -} - -int scan_sata(int dev) -{ - return 0; -} - -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer) -{ - return 0; -} - -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer) -{ - return 0; -} diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig index a8014129d33..7e21c4ae2bb 100644 --- a/drivers/scsi/Kconfig +++ b/drivers/scsi/Kconfig @@ -1,46 +1,9 @@ config SCSI - bool "Support SCSI controllers" + bool "Support SCSI controllers with driver model" help This enables support for SCSI (Small Computer System Interface), a parallel interface widely used with storage peripherals such as hard drives and optical drives. The SCSI standards define physical interfaces as well as protocols for controlling devices and - tranferring data. - -config DM_SCSI - bool "Support SCSI controllers with driver model" - help - This option enables the SCSI (Small Computer System Interface) uclass - which supports SCSI and SATA HDDs. For every device configuration - (IDs/LUNs) a block device is created with RAW read/write and - filesystem support. - -if SCSI && !DM_SCSI - -config SCSI_AHCI_PLAT - bool "Platform-specific init of AHCI" - help - This enables a way for boards to set up an AHCI device manually, by - called ahci_init() and providing an ahci_reset() mechanism. - - This is deprecated. An AHCI driver should be provided instead. - -config SYS_SCSI_MAX_SCSI_ID - int "Maximum supported SCSI ID" - default 1 - help - Sets the maximum number of SCSI IDs to scan when looking for devices. - IDs from 0 to (this value - 1) are scanned. - - This is deprecated and is not needed when BLK is enabled. - -config SYS_SCSI_MAX_LUN - int "Maximum support SCSI LUN" - default 1 - help - Sets the maximum number of SCSI Logical Unit Numbers (LUNs) to scan on - devices. LUNs from 0 to (this value - 1) are scanned. - - This is deprecated and is not needed when CONFIG_DM_SCSI is enabled. - -endif + tranferring data. For every device configuration (IDs/LUNs) a block + device is created with RAW read/write and filesystem support. diff --git a/drivers/scsi/Makefile b/drivers/scsi/Makefile index d8d6de59090..628be4c89fb 100644 --- a/drivers/scsi/Makefile +++ b/drivers/scsi/Makefile @@ -4,25 +4,16 @@ # Wolfgang Denk, DENX Software Engineering, wd@denx.de. ifndef CONFIG_SPL_BUILD -obj-$(CONFIG_DM_SCSI) += scsi-uclass.o -obj-$(CONFIG_SCSI) += scsi.o - +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o ifdef CONFIG_SCSI -ifdef CONFIG_DM_SCSI obj-$(CONFIG_$(SPL_TPL_)BOOTSTD) += scsi_bootdev.o +obj-$(CONFIG_SANDBOX) += sandbox_scsi.o +obj-$(CONFIG_SANDBOX) += scsi_emul.o endif endif -endif - ifdef CONFIG_SPL_BUILD ifdef CONFIG_SPL_SATA -obj-$(CONFIG_DM_SCSI) += scsi-uclass.o -obj-$(CONFIG_SCSI) += scsi.o +obj-$(CONFIG_SCSI) += scsi.o scsi-uclass.o endif endif - -ifdef CONFIG_SCSI -obj-$(CONFIG_SANDBOX) += sandbox_scsi.o -obj-$(CONFIG_SANDBOX) += scsi_emul.o -endif diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c index 779a34bd2f1..363047d0f72 100644 --- a/drivers/scsi/scsi.c +++ b/drivers/scsi/scsi.c @@ -21,38 +21,10 @@ #include #include -#if !defined(CONFIG_DM_SCSI) -# ifdef CFG_SCSI_DEV_LIST -# define SCSI_DEV_LIST CFG_SCSI_DEV_LIST -# else -# ifdef CONFIG_SATA_ULI5288 - -# define SCSI_VEND_ID 0x10b9 -# define SCSI_DEV_ID 0x5288 - -# elif !defined(CONFIG_SCSI_AHCI_PLAT) -# error no scsi device defined -# endif -# define SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -# endif -#endif - -#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \ - !defined(CONFIG_DM_SCSI) -const struct pci_device_id scsi_device_list[] = { SCSI_DEV_LIST }; -#endif static struct scsi_cmd tempccb; /* temporary scsi command buffer */ DEFINE_CACHE_ALIGN_BUFFER(u8, tempbuff, 512); /* temporary data buffer */ -#if !defined(CONFIG_DM_SCSI) -static int scsi_max_devs; /* number of highest available scsi device */ - -static int scsi_curr_dev; /* current device */ - -static struct blk_desc scsi_dev_desc[SCSI_MAX_DEVICE]; -#endif - /* almost the maximum amount of the scsi_ext command.. */ #define SCSI_MAX_BLK 0xFFFF #define SCSI_LBA48_READ 0xFFFFFFF @@ -107,7 +79,6 @@ static void scsi_setup_inquiry(struct scsi_cmd *pccb) pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */ } -#ifdef CONFIG_BLK static void scsi_setup_read_ext(struct scsi_cmd *pccb, lbaint_t start, unsigned short blocks) { @@ -286,59 +257,6 @@ static int scsi_buffer_aligned(struct udevice *dev, struct bounce_buffer *state) return 1; } #endif /* CONFIG_BOUNCE_BUFFER */ -#endif - -#if defined(CONFIG_PCI) && !defined(CONFIG_SCSI_AHCI_PLAT) && \ - !defined(CONFIG_DM_SCSI) -void scsi_init(void) -{ - int busdevfunc = -1; - int i; - /* - * Find a device from the list, this driver will support a single - * controller. - */ - for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { - /* get PCI Device ID */ - struct udevice *dev; - int ret; - - ret = dm_pci_find_device(scsi_device_list[i].vendor, - scsi_device_list[i].device, 0, &dev); - if (!ret) { - busdevfunc = dm_pci_get_bdf(dev); - break; - } - if (busdevfunc != -1) - break; - } - - if (busdevfunc == -1) { - printf("Error: SCSI Controller(s) "); - for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) { - printf("%04X:%04X ", - scsi_device_list[i].vendor, - scsi_device_list[i].device); - } - printf("not found\n"); - return; - } -#ifdef DEBUG - else { - printf("SCSI Controller (%04X,%04X) found (%d:%d:%d)\n", - scsi_device_list[i].vendor, - scsi_device_list[i].device, - (busdevfunc >> 16) & 0xFF, - (busdevfunc >> 11) & 0x1F, - (busdevfunc >> 8) & 0x7); - } -#endif - bootstage_start(BOOTSTAGE_ID_ACCUM_SCSI, "ahci"); - scsi_low_level_init(busdevfunc); - scsi_scan(true); - bootstage_accum(BOOTSTAGE_ID_ACCUM_SCSI); -} -#endif /* copy src to dest, skipping leading and trailing blanks * and null terminate the string @@ -464,25 +382,6 @@ static void scsi_init_dev_desc_priv(struct blk_desc *dev_desc) #endif /* CONFIG_BOUNCE_BUFFER */ } -#if !defined(CONFIG_DM_SCSI) -/** - * scsi_init_dev_desc - initialize all SCSI specific blk_desc properties - * - * @dev_desc: Block device description pointer - * @devnum: Device number - */ -static void scsi_init_dev_desc(struct blk_desc *dev_desc, int devnum) -{ - dev_desc->lba = 0; - dev_desc->blksz = 0; - dev_desc->uclass_id = UCLASS_SCSI; - dev_desc->devnum = devnum; - dev_desc->part_type = PART_TYPE_UNKNOWN; - - scsi_init_dev_desc_priv(dev_desc); -} -#endif - /** * scsi_detect_dev - Detect scsi device * @@ -570,7 +469,6 @@ removable: * (re)-scan the scsi bus and reports scsi device info * to the user if mode = 1 */ -#if defined(CONFIG_DM_SCSI) static int do_scsi_scan_one(struct udevice *dev, int id, int lun, bool verbose) { int ret; @@ -691,48 +589,7 @@ int scsi_scan(bool verbose) return 0; } -#else -int scsi_scan(bool verbose) -{ - unsigned char i, lun; - int ret; - - if (verbose) - printf("scanning bus for devices...\n"); - for (i = 0; i < SCSI_MAX_DEVICE; i++) - scsi_init_dev_desc(&scsi_dev_desc[i], i); - - scsi_max_devs = 0; - for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { - for (lun = 0; lun < CONFIG_SYS_SCSI_MAX_LUN; lun++) { - struct blk_desc *bdesc = &scsi_dev_desc[scsi_max_devs]; - - ret = scsi_detect_dev(NULL, i, lun, bdesc); - if (ret) - continue; - part_init(bdesc); - - if (verbose) { - printf(" Device %d: ", bdesc->devnum); - dev_print(bdesc); - } - scsi_max_devs++; - } /* next LUN */ - } - if (scsi_max_devs > 0) - scsi_curr_dev = 0; - else - scsi_curr_dev = -1; - - printf("Found %d device(s).\n", scsi_max_devs); -#ifndef CONFIG_SPL_BUILD - env_set_ulong("scsidevs", scsi_max_devs); -#endif - return 0; -} -#endif -#ifdef CONFIG_BLK static const struct blk_ops scsi_blk_ops = { .read = scsi_read, .write = scsi_write, @@ -746,11 +603,3 @@ U_BOOT_DRIVER(scsi_blk) = { .id = UCLASS_BLK, .ops = &scsi_blk_ops, }; -#else -U_BOOT_LEGACY_BLK(scsi) = { - .uclass_idname = "scsi", - .uclass_id = UCLASS_SCSI, - .max_devs = SCSI_MAX_DEVICE, - .desc = scsi_dev_desc, -}; -#endif diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 0e0cc58e3d6..ee021c7d549 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -2,7 +2,7 @@ menu "UFS Host Controller Support" config UFS bool "Support UFS controllers" - depends on DM_SCSI + depends on SCSI select CHARSET help This selects support for Universal Flash Subsystem (UFS). diff --git a/include/ahci.h b/include/ahci.h index d7f951c3883..d4f0f3ce0e7 100644 --- a/include/ahci.h +++ b/include/ahci.h @@ -223,9 +223,6 @@ int sata_dm_port_status(struct udevice *dev, int port); */ int sata_scan(struct udevice *dev); -int ahci_init(void __iomem *base); -int ahci_reset(void __iomem *base); - /** * ahci_init_one_dm() - set up a single AHCI port * diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 83ab94ec444..971a393817a 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -57,13 +57,6 @@ * MMC */ -/* SATA */ -#ifndef PCI_DEVICE_ID_FREESCALE_AHCI -#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 -#endif -#define CFG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ - PCI_DEVICE_ID_FREESCALE_AHCI} - /* SPI */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index ee4f885c534..0f591e3c4ab 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -49,11 +49,6 @@ CSOR_NOR_TRHZ_80) #endif -/* SATA */ -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} - /* Initial environment variables */ #ifndef SPL_NO_ENV #undef CFG_EXTRA_ENV_SETTINGS diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 60362b6a4d0..ef8fdc1912b 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -199,13 +199,6 @@ #endif #endif -/* SATA */ -#ifndef SPL_NO_SATA -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CFG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#endif - #include #endif /* __LS1043ARDB_H__ */ diff --git a/include/sata.h b/include/sata.h index 6111cf65d9d..8414e77e42b 100644 --- a/include/sata.h +++ b/include/sata.h @@ -2,22 +2,6 @@ #define __SATA_H__ #include -#if !defined(CONFIG_DM_SCSI) && !defined(CONFIG_AHCI) -int init_sata(int dev); -int reset_sata(int dev); -int scan_sata(int dev); -ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer); -ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer); - -int sata_initialize(void); -int __sata_initialize(void); -int sata_stop(void); -int __sata_stop(void); -int sata_port_status(int dev, int port); - -extern struct blk_desc sata_dev_desc[]; -#endif - int sata_probe(int devnum); int sata_remove(int devnum); diff --git a/include/scsi.h b/include/scsi.h index ee9d622680d..cf756aa62e1 100644 --- a/include/scsi.h +++ b/include/scsi.h @@ -10,10 +10,6 @@ #include #include -/* Fix this to the maximum */ -#define SCSI_MAX_DEVICE \ - (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) - struct udevice; /** @@ -355,11 +351,6 @@ int scsi_scan(bool verbose); */ int scsi_scan_dev(struct udevice *dev, bool verbose); -#ifndef CONFIG_DM_SCSI -void scsi_low_level_init(int busdevfunc); -void scsi_init(void); -#endif - #define SCSI_IDENTIFY 0xC0 /* not used */ /* Hardware errors */ -- cgit v1.3.1 From 970d1673b016ae013839d7bcd69a17601b450304 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 27 Oct 2023 16:43:03 +0200 Subject: ARM: dts: stm32: Add STM32MP257F Evaluation board support Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ... Sync device tree with kernel v6.6-rc1. Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 ++++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 ++++++++++ arch/arm/dts/stm32mp251.dtsi | 285 ++++++++++++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 +++ arch/arm/dts/stm32mp255.dtsi | 9 + arch/arm/dts/stm32mp257.dtsi | 9 + arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 ++ arch/arm/dts/stm32mp257f-ev1.dts | 55 ++++++ arch/arm/dts/stm32mp25xc.dtsi | 8 + arch/arm/dts/stm32mp25xf.dtsi | 8 + arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 ++++++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 +++++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 +++++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 + 15 files changed, 788 insertions(+) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 55aceb51cdb..e0a0d430dab 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1352,6 +1352,9 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcor-drc-compact.dtb \ stm32mp15xx-dhcor-testbench.dtb +dtb-$(CONFIG_STM32MP25X) += \ + stm32mp257f-ev1.dtb + dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ k3-am654-r5-base-board.dtb \ diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi new file mode 100644 index 00000000000..d34a1d5e79c --- /dev/null +++ b/arch/arm/dts/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = ; /* USART2_TX */ + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi new file mode 100644 index 00000000000..f4f26add2a4 --- /dev/null +++ b/arch/arm/dts/stm32mp25-u-boot.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2023 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi new file mode 100644 index 00000000000..cf2f28dc158 --- /dev/null +++ b/arch/arm/dts/stm32mp251.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = , + , + , + ; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = ; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi new file mode 100644 index 00000000000..af48e82efe8 --- /dev/null +++ b/arch/arm/dts/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi new file mode 100644 index 00000000000..e6fa596211f --- /dev/null +++ b/arch/arm/dts/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi new file mode 100644 index 00000000000..5c5000d3d9d --- /dev/null +++ b/arch/arm/dts/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi new file mode 100644 index 00000000000..a35a9b90388 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + */ + +#include "stm32mp25-u-boot.dtsi" + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts new file mode 100644 index 00000000000..a88494eed34 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 00000000000..abdbc7aebc7 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 00000000000..2e0d4d349d1 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 00000000000..2406e972554 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&pinctrl { + st,package = ; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4..28ad0235086 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800 #endif /* _DT_BINDINGS_STM32_PINFUNC_H */ -- cgit v1.3.1 From 01a701994b0590b6452516a7c67353359d053c94 Mon Sep 17 00:00:00 2001 From: Patrice Chotard Date: Fri, 27 Oct 2023 16:43:04 +0200 Subject: stm32mp2: initial support Add initial support for STM32MP2 SoCs family. SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html Migrate all MP1 related code into stm32mp1/ directory Create stm32mp2 directory dedicated for STM32MP2 SoCs. Common code to MP1, MP13 and MP25 is kept into arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu(). Signed-off-by: Patrice Chotard Reviewed-by: Patrick Delaunay --- arch/arm/Kconfig | 2 +- arch/arm/mach-stm32mp/Kconfig | 26 +- arch/arm/mach-stm32mp/Kconfig.25x | 43 ++ arch/arm/mach-stm32mp/Makefile | 15 +- arch/arm/mach-stm32mp/cpu.c | 431 ------------- arch/arm/mach-stm32mp/fdt.c | 514 ---------------- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 +++-- arch/arm/mach-stm32mp/include/mach/sys_proto.h | 26 + arch/arm/mach-stm32mp/psci.c | 808 ------------------------- arch/arm/mach-stm32mp/pwr_regulator.c | 279 --------- arch/arm/mach-stm32mp/spl.c | 252 -------- arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 + arch/arm/mach-stm32mp/stm32mp1/cpu.c | 431 +++++++++++++ arch/arm/mach-stm32mp/stm32mp1/fdt.c | 514 ++++++++++++++++ arch/arm/mach-stm32mp/stm32mp1/psci.c | 808 +++++++++++++++++++++++++ arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c | 279 +++++++++ arch/arm/mach-stm32mp/stm32mp1/spl.c | 252 ++++++++ arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c | 138 +++++ arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c | 344 +++++++++++ arch/arm/mach-stm32mp/stm32mp1/tzc400.c | 136 +++++ arch/arm/mach-stm32mp/stm32mp13x.c | 138 ----- arch/arm/mach-stm32mp/stm32mp15x.c | 344 ----------- arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 + arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 +++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 ++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 + arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 ++++++ arch/arm/mach-stm32mp/syscon.c | 4 +- arch/arm/mach-stm32mp/tzc400.c | 136 ----- board/st/stm32mp2/Kconfig | 13 + board/st/stm32mp2/MAINTAINERS | 9 + board/st/stm32mp2/Makefile | 6 + board/st/stm32mp2/stm32mp2.c | 52 ++ configs/stm32mp25_defconfig | 52 ++ include/configs/stm32mp25_common.h | 24 + 35 files changed, 3659 insertions(+), 2973 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x delete mode 100644 arch/arm/mach-stm32mp/cpu.c delete mode 100644 arch/arm/mach-stm32mp/fdt.c delete mode 100644 arch/arm/mach-stm32mp/psci.c delete mode 100644 arch/arm/mach-stm32mp/pwr_regulator.c delete mode 100644 arch/arm/mach-stm32mp/spl.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp1/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/psci.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/spl.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c create mode 100644 arch/arm/mach-stm32mp/stm32mp1/tzc400.c delete mode 100644 arch/arm/mach-stm32mp/stm32mp13x.c delete mode 100644 arch/arm/mach-stm32mp/stm32mp15x.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c delete mode 100644 arch/arm/mach-stm32mp/tzc400.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6009b7d46dc..a6f00187e9c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1944,7 +1944,7 @@ config ARCH_STM32MP select REGMAP select SYSCON select SYSRESET - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if !ARM64 imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index db47baba6d1..5fc92d07fe6 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -76,6 +76,30 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 + +config STM32MP25X + bool "Support STMicroelectronics STM32MP25x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice config NR_DRAM_BANKS @@ -128,6 +152,6 @@ config CMD_STM32KEY source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" - +source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x new file mode 100644 index 00000000000..2c0f691f8b5 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.25x @@ -0,0 +1,43 @@ +if STM32MP25X + +choice + prompt "STM32MP25x board select" + optional + +config TARGET_ST_STM32MP25X + bool "STMicroelectronics STM32MP25x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP25x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0x87000000 + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a19b2797c8b..00dc25bb275 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -3,24 +3,17 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved # -obj-y += cpu.o obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o -obj-$(CONFIG_STM32MP13x) += stm32mp13x.o -obj-$(CONFIG_STM32MP15x) += stm32mp15x.o +obj-$(CONFIG_STM32MP15x) += stm32mp1/ +obj-$(CONFIG_STM32MP13x) += stm32mp1/ +obj-$(CONFIG_STM32MP25X) += stm32mp2/ obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -obj-y += tzc400.o -else +ifndef CONFIG_SPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif - -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o -obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/cpu.c deleted file mode 100644 index e07abbe21c1..00000000000 --- a/arch/arm/mach-stm32mp/cpu.c +++ /dev/null @@ -1,431 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * early TLB into the .data section so that it not get cleared - * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) - */ -u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); - -struct lmb lmb; - -u32 get_bootmode(void) -{ - /* read bootmode from TAMP backup register */ - return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> - TAMP_BOOT_MODE_SHIFT; -} - -/* - * weak function overidde: set the DDR/SYSRAM executable before to enable the - * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) - */ -void dram_bank_mmu_setup(int bank) -{ - struct bd_info *bd = gd->bd; - int i; - phys_addr_t start; - phys_size_t size; - bool use_lmb = false; - enum dcache_option option; - - if (IS_ENABLED(CONFIG_SPL_BUILD)) { -/* STM32_SYSRAM_BASE exist only when SPL is supported */ -#ifdef CONFIG_SPL - start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); - size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); -#endif - } else if (gd->flags & GD_FLG_RELOC) { - /* bd->bi_dram is available only after relocation */ - start = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; - use_lmb = true; - } else { - /* mark cacheable and executable the beggining of the DDR */ - start = STM32_DDR_BASE; - size = CONFIG_DDR_CACHEABLE_SIZE; - } - - for (i = start >> MMU_SECTION_SHIFT; - i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); - i++) { - option = DCACHE_DEFAULT_OPTION; - if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) - option = 0; /* INVALID ENTRY in TLB */ - set_section_dcache(i, option); - } -} -/* - * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage - * MMU/TLB is updated in enable_caches() for U-Boot after relocation - * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 - */ -static void early_enable_caches(void) -{ - /* I-cache is already enabled in start.S: cpu_init_cp15 */ - - if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - return; - - if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { - gd->arch.tlb_size = PGTABLE_SIZE; - gd->arch.tlb_addr = (unsigned long)&early_tlb; - } - - /* enable MMU (default configuration) */ - dcache_enable(); -} - -/* - * Early system init - */ -int arch_cpu_init(void) -{ - early_enable_caches(); - - /* early armv7 timer init: needed for polling */ - timer_init(); - - return 0; -} - -/* weak function for SOC specific initialization */ -__weak void stm32mp_cpu_init(void) -{ -} - -int mach_cpu_init(void) -{ - u32 boot_mode; - - stm32mp_cpu_init(); - - boot_mode = get_bootmode(); - - if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && - (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) - gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; - else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) - debug_uart_init(); - - return 0; -} - -void enable_caches(void) -{ - /* parse device tree when data cache is still activated */ - lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); - - /* I-cache is already enabled in start.S: icache_enable() not needed */ - - /* deactivate the data cache, early enabled in arch_cpu_init() */ - dcache_disable(); - /* - * update MMU after relocation and enable the data cache - * warning: the TLB location udpated in board_f.c::reserve_mmu - */ - dcache_enable(); -} - -/* used when CONFIG_DISPLAY_CPUINFO is activated */ -int print_cpuinfo(void) -{ - char name[SOC_NAME_SIZE]; - - get_soc_name(name); - printf("CPU: %s\n", name); - - return 0; -} - -static void setup_boot_mode(void) -{ - const u32 serial_addr[] = { - STM32_USART1_BASE, - STM32_USART2_BASE, - STM32_USART3_BASE, - STM32_UART4_BASE, - STM32_UART5_BASE, - STM32_USART6_BASE, - STM32_UART7_BASE, - STM32_UART8_BASE - }; - const u32 sdmmc_addr[] = { - STM32_SDMMC1_BASE, - STM32_SDMMC2_BASE, - STM32_SDMMC3_BASE - }; - char cmd[60]; - u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); - u32 boot_mode = - (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; - unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; - u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); - struct udevice *dev; - - log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", - __func__, boot_ctx, boot_mode, instance, forced_mode); - switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { - case BOOT_SERIAL_UART: - if (instance >= ARRAY_SIZE(serial_addr)) - break; - /* serial : search associated node in devicetree */ - sprintf(cmd, "serial@%x", serial_addr[instance]); - if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { - /* restore console on error */ - if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) - gd->flags &= ~(GD_FLG_SILENT | - GD_FLG_DISABLE_CONSOLE); - log_err("uart%d = %s not found in device tree!\n", - instance + 1, cmd); - break; - } - sprintf(cmd, "%d", dev_seq(dev)); - env_set("boot_device", "serial"); - env_set("boot_instance", cmd); - - /* restore console on uart when not used */ - if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { - gd->flags &= ~(GD_FLG_SILENT | - GD_FLG_DISABLE_CONSOLE); - log_info("serial boot with console enabled!\n"); - } - break; - case BOOT_SERIAL_USB: - env_set("boot_device", "usb"); - env_set("boot_instance", "0"); - break; - case BOOT_FLASH_SD: - case BOOT_FLASH_EMMC: - if (instance >= ARRAY_SIZE(sdmmc_addr)) - break; - /* search associated sdmmc node in devicetree */ - sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); - if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { - printf("mmc%d = %s not found in device tree!\n", - instance, cmd); - break; - } - sprintf(cmd, "%d", dev_seq(dev)); - env_set("boot_device", "mmc"); - env_set("boot_instance", cmd); - break; - case BOOT_FLASH_NAND: - env_set("boot_device", "nand"); - env_set("boot_instance", "0"); - break; - case BOOT_FLASH_SPINAND: - env_set("boot_device", "spi-nand"); - env_set("boot_instance", "0"); - break; - case BOOT_FLASH_NOR: - env_set("boot_device", "nor"); - env_set("boot_instance", "0"); - break; - default: - env_set("boot_device", "invalid"); - env_set("boot_instance", ""); - log_err("unexpected boot mode = %x\n", boot_mode); - break; - } - - switch (forced_mode) { - case BOOT_FASTBOOT: - log_info("Enter fastboot!\n"); - env_set("preboot", "env set preboot; fastboot 0"); - break; - case BOOT_STM32PROG: - env_set("boot_device", "usb"); - env_set("boot_instance", "0"); - break; - case BOOT_UMS_MMC0: - case BOOT_UMS_MMC1: - case BOOT_UMS_MMC2: - log_info("Enter UMS!\n"); - instance = forced_mode - BOOT_UMS_MMC0; - sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); - env_set("preboot", cmd); - break; - case BOOT_RECOVERY: - env_set("preboot", "env set preboot; run altbootcmd"); - break; - case BOOT_NORMAL: - break; - default: - log_debug("unexpected forced boot mode = %x\n", forced_mode); - break; - } - - /* clear TAMP for next reboot */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); -} - -/* - * If there is no MAC address in the environment, then it will be initialized - * (silently) from the value in the OTP. - */ -__weak int setup_mac_address(void) -{ - int ret; - int i; - u32 otp[3]; - uchar enetaddr[6]; - struct udevice *dev; - int nb_eth, nb_otp, index; - - if (!IS_ENABLED(CONFIG_NET)) - return 0; - - nb_eth = get_eth_nb(); - - /* 6 bytes for each MAC addr and 4 bytes for each OTP */ - nb_otp = DIV_ROUND_UP(6 * nb_eth, 4); - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(stm32mp_bsec), - &dev); - if (ret) - return ret; - - ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); - if (ret < 0) - return ret; - - for (index = 0; index < nb_eth; index++) { - /* MAC already in environment */ - if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) - continue; - - for (i = 0; i < 6; i++) - enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index]; - - if (!is_valid_ethaddr(enetaddr)) { - log_err("invalid MAC address %d in OTP %pM\n", - index, enetaddr); - return -EINVAL; - } - log_debug("OTP MAC address %d = %pM\n", index, enetaddr); - ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); - if (ret) { - log_err("Failed to set mac address %pM from OTP: %d\n", - enetaddr, ret); - return ret; - } - } - - return 0; -} - -static int setup_serial_number(void) -{ - char serial_string[25]; - u32 otp[3] = {0, 0, 0 }; - struct udevice *dev; - int ret; - - if (env_get("serial#")) - return 0; - - ret = uclass_get_device_by_driver(UCLASS_MISC, - DM_DRIVER_GET(stm32mp_bsec), - &dev); - if (ret) - return ret; - - ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), - otp, sizeof(otp)); - if (ret < 0) - return ret; - - sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); - env_set("serial#", serial_string); - - return 0; -} - -__weak void stm32mp_misc_init(void) -{ -} - -int arch_misc_init(void) -{ - setup_boot_mode(); - setup_mac_address(); - setup_serial_number(); - stm32mp_misc_init(); - - return 0; -} - -/* - * Without forcing the ".data" section, this would get saved in ".bss". BSS - * will be cleared soon after, so it's not suitable. - */ -static uintptr_t rom_api_table __section(".data"); -static uintptr_t nt_fw_dtb __section(".data"); - -/* - * The ROM gives us the API location in r0 when starting. This is only available - * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save - * the FDT address provided by TF-A in r2 at boot time. This function is called - * from start.S - */ -void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, - unsigned long r3) -{ - if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY)) - rom_api_table = r0; - - if (IS_ENABLED(CONFIG_TFABOOT)) - nt_fw_dtb = r2; - - save_boot_params_ret(); -} - -uintptr_t get_stm32mp_rom_api_table(void) -{ - return rom_api_table; -} - -uintptr_t get_stm32mp_bl2_dtb(void) -{ - return nt_fw_dtb; -} - -#ifdef CONFIG_SPL_BUILD -void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) -{ - typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); - uintptr_t romapi = get_stm32mp_rom_api_table(); - - image_entry_stm32_t image_entry = - (image_entry_stm32_t)spl_image->entry_point; - - printf("image entry point: 0x%lx\n", spl_image->entry_point); - image_entry(romapi); -} -#endif diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/fdt.c deleted file mode 100644 index de5c5a55ea0..00000000000 --- a/arch/arm/mach-stm32mp/fdt.c +++ /dev/null @@ -1,514 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include -#include -#include -#include -#include -#include -#include - -#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) -#define ETZPC_DECPROT_NB 6 - -#define DECPROT_MASK 0x03 -#define NB_PROT_PER_REG 0x10 -#define DECPROT_NB_BITS 2 - -#define DECPROT_SECURED 0x00 -#define DECPROT_WRITE_SECURE 0x01 -#define DECPROT_MCU_ISOLATION 0x02 -#define DECPROT_NON_SECURED 0x03 - -#define ETZPC_RESERVED 0xffffffff - -#define STM32MP13_FDCAN_BASE 0x4400F000 -#define STM32MP13_ADC1_BASE 0x48003000 -#define STM32MP13_TSC_BASE 0x5000B000 -#define STM32MP13_CRYP_BASE 0x54002000 -#define STM32MP13_ETH2_BASE 0x5800E000 -#define STM32MP13_DCMIPP_BASE 0x5A000000 -#define STM32MP13_LTDC_BASE 0x5A010000 - -#define STM32MP15_FDCAN_BASE 0x4400e000 -#define STM32MP15_CRYP2_BASE 0x4c005000 -#define STM32MP15_CRYP1_BASE 0x54001000 -#define STM32MP15_GPU_BASE 0x59000000 -#define STM32MP15_DSI_BASE 0x5a000000 - -static const u32 stm32mp13_ip_addr[] = { - 0x50025000, /* 0 VREFBUF APB3 */ - 0x50021000, /* 1 LPTIM2 APB3 */ - 0x50022000, /* 2 LPTIM3 APB3 */ - STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ - STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ - 0x5A006000, /* 5 USBPHYCTRL APB4 */ - 0x5A003000, /* 6 DDRCTRLPHY APB4 */ - ETZPC_RESERVED, /* 7 Reserved*/ - ETZPC_RESERVED, /* 8 Reserved*/ - ETZPC_RESERVED, /* 9 Reserved*/ - 0x5C006000, /* 10 TZC APB5 */ - 0x58001000, /* 11 MCE APB5 */ - 0x5C000000, /* 12 IWDG1 APB5 */ - 0x5C008000, /* 13 STGENC APB5 */ - ETZPC_RESERVED, /* 14 Reserved*/ - ETZPC_RESERVED, /* 15 Reserved*/ - 0x4C000000, /* 16 USART1 APB6 */ - 0x4C001000, /* 17 USART2 APB6 */ - 0x4C002000, /* 18 SPI4 APB6 */ - 0x4C003000, /* 19 SPI5 APB6 */ - 0x4C004000, /* 20 I2C3 APB6 */ - 0x4C005000, /* 21 I2C4 APB6 */ - 0x4C006000, /* 22 I2C5 APB6 */ - 0x4C007000, /* 23 TIM12 APB6 */ - 0x4C008000, /* 24 TIM13 APB6 */ - 0x4C009000, /* 25 TIM14 APB6 */ - 0x4C00A000, /* 26 TIM15 APB6 */ - 0x4C00B000, /* 27 TIM16 APB6 */ - 0x4C00C000, /* 28 TIM17 APB6 */ - ETZPC_RESERVED, /* 29 Reserved*/ - ETZPC_RESERVED, /* 30 Reserved*/ - ETZPC_RESERVED, /* 31 Reserved*/ - STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ - 0x48004000, /* 33 ADC2 AHB2 */ - 0x49000000, /* 34 OTG AHB2 */ - ETZPC_RESERVED, /* 35 Reserved*/ - ETZPC_RESERVED, /* 36 Reserved*/ - STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ - ETZPC_RESERVED, /* 38 Reserved*/ - ETZPC_RESERVED, /* 39 Reserved*/ - 0x54004000, /* 40 RNG AHB5 */ - 0x54003000, /* 41 HASH AHB5 */ - STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ - 0x54005000, /* 43 SAES AHB5 */ - 0x54006000, /* 44 PKA AHB5 */ - 0x54000000, /* 45 BKPSRAM AHB5 */ - ETZPC_RESERVED, /* 46 Reserved*/ - ETZPC_RESERVED, /* 47 Reserved*/ - 0x5800A000, /* 48 ETH1 AHB6 */ - STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ - 0x58005000, /* 50 SDMMC1 AHB6 */ - 0x58007000, /* 51 SDMMC2 AHB6 */ - ETZPC_RESERVED, /* 52 Reserved*/ - ETZPC_RESERVED, /* 53 Reserved*/ - 0x58002000, /* 54 FMC AHB6 */ - 0x58003000, /* 55 QSPI AHB6 */ - ETZPC_RESERVED, /* 56 Reserved*/ - ETZPC_RESERVED, /* 57 Reserved*/ - ETZPC_RESERVED, /* 58 Reserved*/ - ETZPC_RESERVED, /* 59 Reserved*/ - 0x30000000, /* 60 SRAM1 MLAHB */ - 0x30004000, /* 61 SRAM2 MLAHB */ - 0x30006000, /* 62 SRAM3 MLAHB */ - ETZPC_RESERVED, /* 63 Reserved*/ - ETZPC_RESERVED, /* 64 Reserved*/ - ETZPC_RESERVED, /* 65 Reserved*/ - ETZPC_RESERVED, /* 66 Reserved*/ - ETZPC_RESERVED, /* 67 Reserved*/ - ETZPC_RESERVED, /* 68 Reserved*/ - ETZPC_RESERVED, /* 69 Reserved*/ - ETZPC_RESERVED, /* 70 Reserved*/ - ETZPC_RESERVED, /* 71 Reserved*/ - ETZPC_RESERVED, /* 72 Reserved*/ - ETZPC_RESERVED, /* 73 Reserved*/ - ETZPC_RESERVED, /* 74 Reserved*/ - ETZPC_RESERVED, /* 75 Reserved*/ - ETZPC_RESERVED, /* 76 Reserved*/ - ETZPC_RESERVED, /* 77 Reserved*/ - ETZPC_RESERVED, /* 78 Reserved*/ - ETZPC_RESERVED, /* 79 Reserved*/ - ETZPC_RESERVED, /* 80 Reserved*/ - ETZPC_RESERVED, /* 81 Reserved*/ - ETZPC_RESERVED, /* 82 Reserved*/ - ETZPC_RESERVED, /* 83 Reserved*/ - ETZPC_RESERVED, /* 84 Reserved*/ - ETZPC_RESERVED, /* 85 Reserved*/ - ETZPC_RESERVED, /* 86 Reserved*/ - ETZPC_RESERVED, /* 87 Reserved*/ - ETZPC_RESERVED, /* 88 Reserved*/ - ETZPC_RESERVED, /* 89 Reserved*/ - ETZPC_RESERVED, /* 90 Reserved*/ - ETZPC_RESERVED, /* 91 Reserved*/ - ETZPC_RESERVED, /* 92 Reserved*/ - ETZPC_RESERVED, /* 93 Reserved*/ - ETZPC_RESERVED, /* 94 Reserved*/ - ETZPC_RESERVED, /* 95 Reserved*/ -}; - -static const u32 stm32mp15_ip_addr[] = { - 0x5c008000, /* 00 stgenc */ - 0x54000000, /* 01 bkpsram */ - 0x5c003000, /* 02 iwdg1 */ - 0x5c000000, /* 03 usart1 */ - 0x5c001000, /* 04 spi6 */ - 0x5c002000, /* 05 i2c4 */ - ETZPC_RESERVED, /* 06 reserved */ - 0x54003000, /* 07 rng1 */ - 0x54002000, /* 08 hash1 */ - STM32MP15_CRYP1_BASE, /* 09 cryp1 */ - 0x5a003000, /* 0A ddrctrl */ - 0x5a004000, /* 0B ddrphyc */ - 0x5c009000, /* 0C i2c6 */ - ETZPC_RESERVED, /* 0D reserved */ - ETZPC_RESERVED, /* 0E reserved */ - ETZPC_RESERVED, /* 0F reserved */ - 0x40000000, /* 10 tim2 */ - 0x40001000, /* 11 tim3 */ - 0x40002000, /* 12 tim4 */ - 0x40003000, /* 13 tim5 */ - 0x40004000, /* 14 tim6 */ - 0x40005000, /* 15 tim7 */ - 0x40006000, /* 16 tim12 */ - 0x40007000, /* 17 tim13 */ - 0x40008000, /* 18 tim14 */ - 0x40009000, /* 19 lptim1 */ - 0x4000a000, /* 1A wwdg1 */ - 0x4000b000, /* 1B spi2 */ - 0x4000c000, /* 1C spi3 */ - 0x4000d000, /* 1D spdifrx */ - 0x4000e000, /* 1E usart2 */ - 0x4000f000, /* 1F usart3 */ - 0x40010000, /* 20 uart4 */ - 0x40011000, /* 21 uart5 */ - 0x40012000, /* 22 i2c1 */ - 0x40013000, /* 23 i2c2 */ - 0x40014000, /* 24 i2c3 */ - 0x40015000, /* 25 i2c5 */ - 0x40016000, /* 26 cec */ - 0x40017000, /* 27 dac */ - 0x40018000, /* 28 uart7 */ - 0x40019000, /* 29 uart8 */ - ETZPC_RESERVED, /* 2A reserved */ - ETZPC_RESERVED, /* 2B reserved */ - 0x4001c000, /* 2C mdios */ - ETZPC_RESERVED, /* 2D reserved */ - ETZPC_RESERVED, /* 2E reserved */ - ETZPC_RESERVED, /* 2F reserved */ - 0x44000000, /* 30 tim1 */ - 0x44001000, /* 31 tim8 */ - ETZPC_RESERVED, /* 32 reserved */ - 0x44003000, /* 33 usart6 */ - 0x44004000, /* 34 spi1 */ - 0x44005000, /* 35 spi4 */ - 0x44006000, /* 36 tim15 */ - 0x44007000, /* 37 tim16 */ - 0x44008000, /* 38 tim17 */ - 0x44009000, /* 39 spi5 */ - 0x4400a000, /* 3A sai1 */ - 0x4400b000, /* 3B sai2 */ - 0x4400c000, /* 3C sai3 */ - 0x4400d000, /* 3D dfsdm */ - STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ - ETZPC_RESERVED, /* 3F reserved */ - 0x50021000, /* 40 lptim2 */ - 0x50022000, /* 41 lptim3 */ - 0x50023000, /* 42 lptim4 */ - 0x50024000, /* 43 lptim5 */ - 0x50027000, /* 44 sai4 */ - 0x50025000, /* 45 vrefbuf */ - 0x4c006000, /* 46 dcmi */ - 0x4c004000, /* 47 crc2 */ - 0x48003000, /* 48 adc */ - 0x4c002000, /* 49 hash2 */ - 0x4c003000, /* 4A rng2 */ - STM32MP15_CRYP2_BASE, /* 4B cryp2 */ - ETZPC_RESERVED, /* 4C reserved */ - ETZPC_RESERVED, /* 4D reserved */ - ETZPC_RESERVED, /* 4E reserved */ - ETZPC_RESERVED, /* 4F reserved */ - ETZPC_RESERVED, /* 50 sram1 */ - ETZPC_RESERVED, /* 51 sram2 */ - ETZPC_RESERVED, /* 52 sram3 */ - ETZPC_RESERVED, /* 53 sram4 */ - ETZPC_RESERVED, /* 54 retram */ - 0x49000000, /* 55 otg */ - 0x48004000, /* 56 sdmmc3 */ - 0x48005000, /* 57 dlybsd3 */ - 0x48000000, /* 58 dma1 */ - 0x48001000, /* 59 dma2 */ - 0x48002000, /* 5A dmamux */ - 0x58002000, /* 5B fmc */ - 0x58003000, /* 5C qspi */ - 0x58004000, /* 5D dlybq */ - 0x5800a000, /* 5E eth */ - ETZPC_RESERVED, /* 5F reserved */ -}; - -/* fdt helper */ -static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) -{ - int node; - fdt_addr_t regs; - - for (node = fdt_first_subnode(fdt, offset); - node >= 0; - node = fdt_next_subnode(fdt, node)) { - regs = fdtdec_get_addr(fdt, node, "reg"); - if (addr == regs) { - if (fdtdec_get_is_enabled(fdt, node)) { - fdt_status_disabled(fdt, node); - - return true; - } - return false; - } - } - - return false; -} - -static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) -{ - const u32 *array; - int array_size, i; - int offset, shift; - u32 addr, status, decprot[ETZPC_DECPROT_NB]; - - if (IS_ENABLED(CONFIG_STM32MP13x)) { - array = stm32mp13_ip_addr; - array_size = ARRAY_SIZE(stm32mp13_ip_addr); - } - - if (IS_ENABLED(CONFIG_STM32MP15x)) { - array = stm32mp15_ip_addr; - array_size = ARRAY_SIZE(stm32mp15_ip_addr); - } - - for (i = 0; i < ETZPC_DECPROT_NB; i++) - decprot[i] = readl(ETZPC_DECPROT(i)); - - for (i = 0; i < array_size; i++) { - offset = i / NB_PROT_PER_REG; - shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; - status = (decprot[offset] >> shift) & DECPROT_MASK; - addr = array[i]; - - log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); - - if (addr == ETZPC_RESERVED || - status == DECPROT_NON_SECURED) - continue; - - if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) - log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n", - addr, i, status); - } - - return 0; -} - -/* deactivate all the cpu except core 0 */ -static void stm32_fdt_fixup_cpu(void *blob, char *name) -{ - int off; - u32 reg; - - off = fdt_path_offset(blob, "/cpus"); - if (off < 0) { - log_warning("%s: couldn't find /cpus node\n", __func__); - return; - } - - off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); - while (off != -FDT_ERR_NOTFOUND) { - reg = fdtdec_get_addr(blob, off, "reg"); - if (reg != 0) { - fdt_del_node(blob, off); - log_notice("FDT: cpu %d node remove for %s\n", - reg, name); - /* after delete we can't trust the offsets anymore */ - off = -1; - } - off = fdt_node_offset_by_prop_value(blob, off, - "device_type", "cpu", 4); - } -} - -static void stm32_fdt_disable(void *fdt, int offset, u32 addr, - const char *string, const char *name) -{ - if (fdt_disable_subnode_by_address(fdt, offset, addr)) - log_notice("FDT: %s@%08x node disabled for %s\n", - string, addr, name); -} - -static void stm32_fdt_disable_optee(void *blob) -{ - int off, node; - - /* Delete "optee" firmware node */ - off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); - if (off >= 0 && fdtdec_get_is_enabled(blob, off)) - fdt_del_node(blob, off); - - /* Delete "optee@..." reserved-memory node */ - off = fdt_path_offset(blob, "/reserved-memory/"); - if (off < 0) - return; - for (node = fdt_first_subnode(blob, off); - node >= 0; - node = fdt_next_subnode(blob, node)) { - if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) - continue; - - if (fdt_del_node(blob, node)) - printf("Failed to remove optee reserved-memory node\n"); - } -} - -static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) -{ - switch (cpu) { - case CPU_STM32MP131Fxx: - case CPU_STM32MP131Dxx: - case CPU_STM32MP131Cxx: - case CPU_STM32MP131Axx: - stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); - stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); - fallthrough; - case CPU_STM32MP133Fxx: - case CPU_STM32MP133Dxx: - case CPU_STM32MP133Cxx: - case CPU_STM32MP133Axx: - stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); - stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", - name); - stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); - break; - default: - break; - } - - switch (cpu) { - case CPU_STM32MP135Dxx: - case CPU_STM32MP135Axx: - case CPU_STM32MP133Dxx: - case CPU_STM32MP133Axx: - case CPU_STM32MP131Dxx: - case CPU_STM32MP131Axx: - stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); - break; - default: - break; - } -} - -static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) -{ - u32 pkg; - - switch (cpu) { - case CPU_STM32MP151Fxx: - case CPU_STM32MP151Dxx: - case CPU_STM32MP151Cxx: - case CPU_STM32MP151Axx: - stm32_fdt_fixup_cpu(blob, name); - /* after cpu delete we can't trust the soc offsets anymore */ - soc = fdt_path_offset(blob, "/soc"); - stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); - fallthrough; - case CPU_STM32MP153Fxx: - case CPU_STM32MP153Dxx: - case CPU_STM32MP153Cxx: - case CPU_STM32MP153Axx: - stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); - stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); - break; - default: - break; - } - switch (cpu) { - case CPU_STM32MP157Dxx: - case CPU_STM32MP157Axx: - case CPU_STM32MP153Dxx: - case CPU_STM32MP153Axx: - case CPU_STM32MP151Dxx: - case CPU_STM32MP151Axx: - stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", - name); - stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", - name); - break; - default: - break; - } - switch (get_cpu_package()) { - case STM32MP15_PKG_AA_LBGA448: - pkg = STM32MP_PKG_AA; - break; - case STM32MP15_PKG_AB_LBGA354: - pkg = STM32MP_PKG_AB; - break; - case STM32MP15_PKG_AC_TFBGA361: - pkg = STM32MP_PKG_AC; - break; - case STM32MP15_PKG_AD_TFBGA257: - pkg = STM32MP_PKG_AD; - break; - default: - pkg = 0; - break; - } - if (pkg) { - do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl", - "st,package", pkg, false); - do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", - "st,package", pkg, false); - } -} - -/* - * This function is called right before the kernel is booted. "blob" is the - * device tree that will be passed to the kernel. - */ -int ft_system_setup(void *blob, struct bd_info *bd) -{ - int ret = 0; - int soc; - u32 cpu; - char name[SOC_NAME_SIZE]; - - soc = fdt_path_offset(blob, "/soc"); - /* when absent, nothing to do */ - if (soc == -FDT_ERR_NOTFOUND) - return 0; - if (soc < 0) - return soc; - - if (CONFIG_IS_ENABLED(STM32_ETZPC)) { - ret = stm32_fdt_fixup_etzpc(blob, soc); - if (ret) - return ret; - } - - /* MPUs Part Numbers and name*/ - cpu = get_cpu_type(); - get_soc_name(name); - - if (IS_ENABLED(CONFIG_STM32MP13x)) - stm32mp13_fdt_fixup(blob, soc, cpu, name); - - if (IS_ENABLED(CONFIG_STM32MP15x)) { - stm32mp15_fdt_fixup(blob, soc, cpu, name); - - /* - * TEMP: remove OP-TEE nodes in kernel device tree - * copied from U-Boot device tree by optee_copy_fdt_nodes - * when OP-TEE is not detected (probe failed) - * these OP-TEE nodes are present in -u-boot.dtsi - * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility - * when FIP is not used by TF-A - */ - if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE) && - !tee_find_device(NULL, NULL, NULL, NULL)) - stm32_fdt_disable_optee(blob); - } - - return ret; -} diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1cdc5e3b186..ce9d795651b 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -8,12 +8,66 @@ #ifndef __ASSEMBLY__ #include + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#define TAMP_BOOT_DEBUG_ON BIT(16) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + #endif /* * Peripheral memory map * only address used before device tree parsing */ + +#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x) #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 @@ -58,12 +112,6 @@ #define STM32_DDR_SIZE SZ_1G #ifndef __ASSEMBLY__ -/* enumerated used to identify the SYSCON driver instance */ -enum { - STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_SYSCFG, -}; - /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT * - boot device = bit 8:4 @@ -74,40 +122,6 @@ enum { #define BOOT_INSTANCE_MASK 0x0F #define BOOT_INSTANCE_SHIFT 0 -enum boot_device { - BOOT_FLASH_SD = 0x10, - BOOT_FLASH_SD_1 = 0x11, - BOOT_FLASH_SD_2 = 0x12, - BOOT_FLASH_SD_3 = 0x13, - - BOOT_FLASH_EMMC = 0x20, - BOOT_FLASH_EMMC_1 = 0x21, - BOOT_FLASH_EMMC_2 = 0x22, - BOOT_FLASH_EMMC_3 = 0x23, - - BOOT_FLASH_NAND = 0x30, - BOOT_FLASH_NAND_FMC = 0x31, - - BOOT_FLASH_NOR = 0x40, - BOOT_FLASH_NOR_QSPI = 0x41, - - BOOT_SERIAL_UART = 0x50, - BOOT_SERIAL_UART_1 = 0x51, - BOOT_SERIAL_UART_2 = 0x52, - BOOT_SERIAL_UART_3 = 0x53, - BOOT_SERIAL_UART_4 = 0x54, - BOOT_SERIAL_UART_5 = 0x55, - BOOT_SERIAL_UART_6 = 0x56, - BOOT_SERIAL_UART_7 = 0x57, - BOOT_SERIAL_UART_8 = 0x58, - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, - - BOOT_FLASH_SPINAND = 0x70, - BOOT_FLASH_SPINAND_1 = 0x71, -}; - /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x) @@ -123,7 +137,6 @@ enum boot_device { #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0) #define TAMP_FWU_BOOT_IDX_OFFSET 0 - #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -137,21 +150,23 @@ enum boot_device { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif -#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) -#define TAMP_BOOT_MODE_SHIFT 8 -#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) -#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */ -enum forced_boot_mode { - BOOT_NORMAL = 0x00, - BOOT_FASTBOOT = 0x01, - BOOT_RECOVERY = 0x02, - BOOT_STM32PROG = 0x03, - BOOT_UMS_MMC0 = 0x10, - BOOT_UMS_MMC1 = 0x11, - BOOT_UMS_MMC2 = 0x12, -}; +#if CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */ /* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -175,6 +190,20 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 246 +#endif + +#ifndef __ASSEMBLY__ +#include + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/ -#endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 83fb32a45fc..7b2df09a33c 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,11 +30,30 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9 +/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void); #define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505 /* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -59,6 +78,13 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0 +/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c deleted file mode 100644 index 8cdeb0ab3f2..00000000000 --- a/arch/arm/mach-stm32mp/psci.c +++ /dev/null @@ -1,808 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* PWR */ -#define PWR_CR3 0x0c -#define PWR_MPUCR 0x10 - -#define PWR_CR3_DDRSREN BIT(10) -#define PWR_CR3_DDRRETEN BIT(12) - -#define PWR_MPUCR_PDDS BIT(0) -#define PWR_MPUCR_CSTDBYDIS BIT(3) -#define PWR_MPUCR_CSSF BIT(9) - -/* RCC */ -#define RCC_MSSCKSELR 0x48 -#define RCC_DDRITFCR 0xd8 - -#define RCC_DDRITFCR_DDRC1EN BIT(0) -#define RCC_DDRITFCR_DDRC1LPEN BIT(1) -#define RCC_DDRITFCR_DDRC2EN BIT(2) -#define RCC_DDRITFCR_DDRC2LPEN BIT(3) -#define RCC_DDRITFCR_DDRPHYCEN BIT(4) -#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) -#define RCC_DDRITFCR_DDRCAPBEN BIT(6) -#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) -#define RCC_DDRITFCR_AXIDCGEN BIT(8) -#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) -#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) -#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) -#define RCC_DDRITFCR_GSKPCTRL BIT(24) - -#define RCC_MP_SREQSETR 0x104 -#define RCC_MP_SREQCLRR 0x108 - -#define RCC_MP_CIER 0x414 -#define RCC_MP_CIFR 0x418 -#define RCC_MP_CIFR_WKUPF BIT(20) - -#define RCC_MCUDIVR 0x830 -#define RCC_PLL3CR 0x880 -#define RCC_PLL4CR 0x894 - -/* SYSCFG */ -#define SYSCFG_CMPCR 0x20 -#define SYSCFG_CMPCR_SW_CTRL BIT(2) -#define SYSCFG_CMPENSETR 0x24 -#define SYSCFG_CMPENCLRR 0x28 -#define SYSCFG_CMPENR_MPUEN BIT(0) - -/* DDR Controller registers offsets */ -#define DDRCTRL_STAT 0x004 -#define DDRCTRL_PWRCTL 0x030 -#define DDRCTRL_PWRTMG 0x034 -#define DDRCTRL_HWLPCTL 0x038 -#define DDRCTRL_DFIMISC 0x1b0 -#define DDRCTRL_SWCTL 0x320 -#define DDRCTRL_SWSTAT 0x324 -#define DDRCTRL_PSTAT 0x3fc -#define DDRCTRL_PCTRL_0 0x490 -#define DDRCTRL_PCTRL_1 0x540 - -/* DDR Controller Register fields */ -#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) -#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1 -#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3 -#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) -#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4) -#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4) - -#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) -#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) -#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) - -#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) -#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) - -#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) - -#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) - -#define DDRCTRL_SWCTL_SW_DONE BIT(0) - -#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) - -#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0) -#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1) -#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16) -#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17) - -#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) - -/* DDR PHY registers offsets */ -#define DDRPHYC_PIR 0x004 -#define DDRPHYC_PGSR 0x00c -#define DDRPHYC_ACDLLCR 0x014 -#define DDRPHYC_ACIOCR 0x024 -#define DDRPHYC_DXCCR 0x028 -#define DDRPHYC_DSGCR 0x02c -#define DDRPHYC_ZQ0CR0 0x180 -#define DDRPHYC_DX0DLLCR 0x1cc -#define DDRPHYC_DX1DLLCR 0x20c -#define DDRPHYC_DX2DLLCR 0x24c -#define DDRPHYC_DX3DLLCR 0x28c - -/* DDR PHY Register fields */ -#define DDRPHYC_PIR_INIT BIT(0) -#define DDRPHYC_PIR_DLLSRST BIT(1) -#define DDRPHYC_PIR_DLLLOCK BIT(2) -#define DDRPHYC_PIR_ITMSRST BIT(4) - -#define DDRPHYC_PGSR_IDONE BIT(0) - -#define DDRPHYC_ACDLLCR_DLLSRST BIT(30) -#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) - -#define DDRPHYC_ACIOCR_ACOE BIT(1) -#define DDRPHYC_ACIOCR_ACPDD BIT(3) -#define DDRPHYC_ACIOCR_ACPDR BIT(4) -#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8) -#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8) -#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11) -#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11) -#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18) -#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18) - -#define DDRPHYC_DXCCR_DXPDD BIT(2) -#define DDRPHYC_DXCCR_DXPDR BIT(3) - -#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16) -#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16) -#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20) -#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20) -#define DDRPHYC_DSGCR_NL2PD BIT(24) -#define DDRPHYC_DSGCR_CKOE BIT(28) - -#define DDRPHYC_ZQ0CRN_ZQPD BIT(31) - -#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) - -#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0 -#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1 - -#define MPIDR_AFF0 GENMASK(7, 0) - -#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404) -#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) -#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) -#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) - -/* IWDG */ -#define IWDG_KR 0x00 -#define IWDG_KR_RELOAD_KEY 0xaaaa -#define IWDG_EWCR 0x14 -#define IWDG_EWCR_EWIC BIT(14) - -#define STM32MP1_PSCI_NR_CPUS 2 -#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS -#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" -#endif - -u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = { - PSCI_AFFINITY_LEVEL_ON, - PSCI_AFFINITY_LEVEL_OFF}; - -static u32 __secure_data cntfrq; - -static u32 __secure cp15_read_cntfrq(void) -{ - u32 frq; - - asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); - - return frq; -} - -static void __secure cp15_write_cntfrq(u32 frq) -{ - asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq)); -} - -static inline void psci_set_state(int cpu, u8 state) -{ - psci_state[cpu] = state; - dsb(); - isb(); -} - -static u32 __secure stm32mp_get_gicd_base_address(void) -{ - u32 periphbase; - - /* get the GIC base address from the CBAR register */ - asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); - - return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; -} - -static void __secure stm32mp_raise_sgi0(int cpu) -{ - u32 gic_dist_addr; - - gic_dist_addr = stm32mp_get_gicd_base_address(); - - /* ask cpu with SGI0 */ - writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR); -} - -void __secure psci_arch_cpu_entry(void) -{ - u32 cpu = psci_get_cpu_id(); - - psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); - - /* write the saved cntfrq */ - cp15_write_cntfrq(cntfrq); - - /* reset magic in TAMP register */ - writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); -} - -s32 __secure psci_features(u32 function_id, u32 psci_fid) -{ - switch (psci_fid) { - case ARM_PSCI_0_2_FN_PSCI_VERSION: - case ARM_PSCI_0_2_FN_CPU_OFF: - case ARM_PSCI_0_2_FN_CPU_ON: - case ARM_PSCI_0_2_FN_AFFINITY_INFO: - case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: - case ARM_PSCI_0_2_FN_SYSTEM_OFF: - case ARM_PSCI_0_2_FN_SYSTEM_RESET: - case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND: - return 0x0; - } - return ARM_PSCI_RET_NI; -} - -u32 __secure psci_version(void) -{ - return ARM_PSCI_VER_1_0; -} - -s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity, - u32 lowest_affinity_level) -{ - u32 cpu = target_affinity & MPIDR_AFF0; - - if (lowest_affinity_level > 0) - return ARM_PSCI_RET_INVAL; - - if (target_affinity & ~MPIDR_AFF0) - return ARM_PSCI_RET_INVAL; - - if (cpu >= STM32MP1_PSCI_NR_CPUS) - return ARM_PSCI_RET_INVAL; - - return psci_state[cpu]; -} - -u32 __secure psci_migrate_info_type(void) -{ - /* - * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf - * return 2 = Trusted OS is either not present or does not require - * migration, system of this type does not require the caller - * to use the MIGRATE function. - * MIGRATE function calls return NOT_SUPPORTED. - */ - return 2; -} - -s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, - u32 context_id) -{ - u32 cpu = target_cpu & MPIDR_AFF0; - - if (target_cpu & ~MPIDR_AFF0) - return ARM_PSCI_RET_INVAL; - - if (cpu >= STM32MP1_PSCI_NR_CPUS) - return ARM_PSCI_RET_INVAL; - - if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) - return ARM_PSCI_RET_ALREADY_ON; - - /* read and save cntfrq of current cpu to write on target cpu */ - cntfrq = cp15_read_cntfrq(); - - /* reset magic in TAMP register */ - if (readl(TAMP_BACKUP_MAGIC_NUMBER)) - writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); - /* - * ROM code need a first SGI0 after core reset - * core is ready when magic is set to 0 in ROM code - */ - while (readl(TAMP_BACKUP_MAGIC_NUMBER)) - stm32mp_raise_sgi0(cpu); - - /* store target PC and context id*/ - psci_save(cpu, pc, context_id); - - /* write entrypoint in backup RAM register */ - writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS); - psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); - - /* write magic number in backup register */ - if (cpu == 0x01) - writel(BOOT_API_A7_CORE1_MAGIC_NUMBER, - TAMP_BACKUP_MAGIC_NUMBER); - else - writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, - TAMP_BACKUP_MAGIC_NUMBER); - - /* Generate an IT to start the core */ - stm32mp_raise_sgi0(cpu); - - return ARM_PSCI_RET_SUCCESS; -} - -s32 __secure psci_cpu_off(void) -{ - u32 cpu; - - cpu = psci_get_cpu_id(); - - psci_cpu_off_common(); - psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); - - /* reset core: wfi is managed by BootRom */ - if (cpu == 0x01) - writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR); - else - writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR); - - /* just waiting reset */ - while (1) - wfi(); -} - -void __secure psci_system_reset(void) -{ - /* System reset */ - writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR); - /* just waiting reset */ - while (1) - wfi(); -} - -void __secure psci_system_off(void) -{ - /* System Off is not managed, waiting user power off - * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF - */ - while (1) - wfi(); -} - -static void __secure secure_udelay(unsigned int delay) -{ - u32 freq = cp15_read_cntfrq() / 1000000; - u64 start, end; - - delay *= freq; - - asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); - for (;;) { - asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); - if ((end - start) > delay) - break; - } -} - -static int __secure secure_waitbits(u32 reg, u32 mask, u32 val) -{ - u32 freq = cp15_read_cntfrq() / 1000000; - u32 delay = 500 * freq; /* 500 us */ - u64 start, end; - u32 tmp; - - asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); - for (;;) { - tmp = readl(reg); - tmp &= mask; - if ((tmp & val) == val) - return 0; - asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); - if ((end - start) > delay) - return -ETIMEDOUT; - } -} - -static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl) -{ - setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, - RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN | - RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN | - RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN | - RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN | - RCC_DDRITFCR_DDRPHYCEN); - - clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, - RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK); - - /* Disable HW LP interface of uMCTL2 */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL, - DDRCTRL_HWLPCTL_HW_LP_EN); - - /* Configure Automatic LP modes of uMCTL2 */ - clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG, - DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, - DDRCTRL_PWRTMG_SELFREF_TO_X32_0); - - /* Save PWRCTL register to restart ASR after suspend (if applicable) */ - *saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL); - - /* - * Disable Clock disable with LP modes - * (used in RUN mode for LPDDR2 with specific timing). - */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, - DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); - - /* Disable automatic Self-Refresh mode */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, - DDRCTRL_PWRCTL_SELFREF_EN); -} - -static void __secure ddr_sr_mode_restore(u32 saved_pwrctl) -{ - saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | - DDRCTRL_PWRCTL_SELFREF_EN; - - /* Restore ASR mode in case it was enabled before suspend. */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl); -} - -static int __secure ddr_sw_self_refresh_in(void) -{ - int ret; - - clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); - - /* Blocks AXI ports from taking anymore transactions */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, - DDRCTRL_PCTRL_N_PORT_EN); - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, - DDRCTRL_PCTRL_N_PORT_EN); - - /* - * Waits unit all AXI ports are idle - * Poll PSTAT.rd_port_busy_n = 0 - * Poll PSTAT.wr_port_busy_n = 0 - */ - ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT, - DDRCTRL_PSTAT_RD_PORT_BUSY_0 | - DDRCTRL_PSTAT_RD_PORT_BUSY_1 | - DDRCTRL_PSTAT_WR_PORT_BUSY_0 | - DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0); - if (ret) - goto pstat_failed; - - /* SW Self-Refresh entry */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); - - /* - * Wait operating mode change in self-refresh mode - * with STAT.operating_mode[1:0]==11. - * Ensure transition to self-refresh was due to software - * by checking also that STAT.selfref_type[1:0]=2. - */ - ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, - DDRCTRL_STAT_OPERATING_MODE_MASK | - DDRCTRL_STAT_SELFREF_TYPE_MASK, - DDRCTRL_STAT_OPERATING_MODE_SR | - DDRCTRL_STAT_SELFREF_TYPE_SR); - if (ret) - goto selfref_sw_failed; - - /* IOs powering down (PUBL registers) */ - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR); - - clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, - DDRPHYC_ACIOCR_CKPDD_MASK, - DDRPHYC_ACIOCR_CKPDD_0); - - clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, - DDRPHYC_ACIOCR_CKPDR_MASK, - DDRPHYC_ACIOCR_CKPDR_0); - - clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, - DDRPHYC_ACIOCR_CSPDD_MASK, - DDRPHYC_ACIOCR_CSPDD_0); - - /* Disable command/address output driver */ - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); - - clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, - DDRPHYC_DSGCR_ODTPDD_MASK, - DDRPHYC_DSGCR_ODTPDD_0); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); - - clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, - DDRPHYC_DSGCR_CKEPDD_MASK, - DDRPHYC_DSGCR_CKEPDD_0); - - /* Disable PZQ cell (PUBL register) */ - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); - - /* Set latch */ - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); - - /* Additional delay to avoid early latch */ - secure_udelay(10); - - /* Activate sw retention in PWRCTRL */ - setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); - - /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ - setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); - - /* Disable all DLLs: GLITCH window */ - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - /* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */ - clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); - - /* Deactivate all DDR clocks */ - clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, - RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | - RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN); - - return 0; - -selfref_sw_failed: - /* This bit should be cleared to restore DDR in its previous state */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, - DDRCTRL_PWRCTL_SELFREF_SW); - -pstat_failed: - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, - DDRCTRL_PCTRL_N_PORT_EN); - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, - DDRCTRL_PCTRL_N_PORT_EN); - - return -EINVAL; -}; - -static void __secure ddr_sw_self_refresh_exit(void) -{ - int ret; - - /* Enable all clocks */ - setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, - RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | - RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN | - RCC_DDRITFCR_DDRCAPBEN); - - /* Handshake */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); - - /* Mask dfi_init_complete_en */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, - DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - - /* Ack */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); - ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, - DDRCTRL_SWSTAT_SW_DONE_ACK, - DDRCTRL_SWSTAT_SW_DONE_ACK); - if (ret) - hang(); - - /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ - setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); - - /* Enable all DLLs: GLITCH window */ - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, - DDRPHYC_ACDLLCR_DLLDIS); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); - - /* Additional delay to avoid early DLL clock switch */ - secure_udelay(50); - - /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ - clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); - - secure_udelay(10); - - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); - - /* PHY partial init: (DLL lock and ITM reset) */ - writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | - DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT, - STM32_DDRPHYC_BASE + DDRPHYC_PIR); - - /* Need to wait at least 10 clock cycles before accessing PGSR */ - secure_udelay(1); - - /* Pool end of init */ - ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR, - DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE); - if (ret) - hang(); - - /* Handshake */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); - - /* Unmask dfi_init_complete_en to uMCTL2 */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); - - /* Ack */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); - ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, - DDRCTRL_SWSTAT_SW_DONE_ACK, - DDRCTRL_SWSTAT_SW_DONE_ACK); - if (ret) - hang(); - - /* Deactivate sw retention in PWR */ - clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); - - /* Enable PZQ cell (PUBL register) */ - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); - - /* Enable pad drivers */ - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); - - /* Enable command/address output driver */ - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); - - /* Release latch */ - setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); - - clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK); - - /* Remove selfrefresh */ - clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); - - /* Wait operating_mode == normal */ - ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, - DDRCTRL_STAT_OPERATING_MODE_MASK, - DDRCTRL_STAT_OPERATING_MODE_NORMAL); - if (ret) - hang(); - - /* AXI ports are no longer blocked from taking transactions */ - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN); - setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN); - - setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); -} - -void __secure psci_system_suspend(u32 __always_unused function_id, - u32 ep, u32 context_id) -{ - u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; - u32 gicd_addr = stm32mp_get_gicd_base_address(); - bool iwdg1_wake = false; - bool iwdg2_wake = false; - bool other_wake = false; - u32 saved_pwrctl, reg; - u32 gic_enabled[8]; - u32 irqs; - int i; - - /* Cache enable mask of all 256 SPI */ - for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) - gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i); - - /* Disable IO compensation */ - - /* Place current APSRC/ANSRC into RAPSRC/RANSRC */ - reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR); - reg >>= 8; - reg &= 0xff << 16; - reg |= SYSCFG_CMPCR_SW_CTRL; - writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR); - writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR); - - writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR); - setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); - - setbits_le32(STM32_PWR_BASE + PWR_MPUCR, - PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); - - saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); - saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); - saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); - saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); - - psci_v7_flush_dcache_all(); - ddr_sr_mode_ssr(&saved_pwrctl); - ddr_sw_self_refresh_in(); - setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN); - writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); - - /* Ping the IWDG before entering suspend */ - iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */ - iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */ - - for (;;) { - /* Ping IWDG1 and ACK pretimer IRQ */ - if (iwdg1_wake) { - writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); - writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); - } - - /* Ping IWDG2 and ACK pretimer IRQ */ - if (iwdg2_wake) { - writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); - writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); - } - - iwdg1_wake = false; - iwdg2_wake = false; - - /* Zzz, enter stop mode */ - asm volatile( - "isb\n" - "dsb\n" - "wfi\n"); - - /* Determine the wake up source */ - for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) { - irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i); - irqs &= gic_enabled[i]; - if (!irqs) - continue; - - /* Test whether IWDG pretimeout triggered the wake up. */ - if (i == 4) { /* SPI Num 128..159 */ - iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */ - iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */ - irqs &= ~(BIT(22) | BIT(23)); - } - - /* Test whether there is any other wake up trigger. */ - if (irqs) { - other_wake = true; - break; - } - } - - /* Other wake up triggers pending, let OS deal with all of it. */ - if (other_wake) - break; - } - - writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); - ddr_sw_self_refresh_exit(); - ddr_sr_mode_restore(saved_pwrctl); - - writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); - writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); - writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); - writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); - - writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); - clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); -} diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/pwr_regulator.c deleted file mode 100644 index 846637ab162..00000000000 --- a/arch/arm/mach-stm32mp/pwr_regulator.c +++ /dev/null @@ -1,279 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY UCLASS_REGULATOR - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define STM32MP_PWR_CR3 0xc -#define STM32MP_PWR_CR3_USB33DEN BIT(24) -#define STM32MP_PWR_CR3_USB33RDY BIT(26) -#define STM32MP_PWR_CR3_REG18DEN BIT(28) -#define STM32MP_PWR_CR3_REG18RDY BIT(29) -#define STM32MP_PWR_CR3_REG11DEN BIT(30) -#define STM32MP_PWR_CR3_REG11RDY BIT(31) - -struct stm32mp_pwr_reg_info { - u32 enable; - u32 ready; - char *name; -}; - -struct stm32mp_pwr_priv { - fdt_addr_t base; -}; - -static int stm32mp_pwr_write(struct udevice *dev, uint reg, - const uint8_t *buff, int len) -{ - struct stm32mp_pwr_priv *priv = dev_get_priv(dev); - u32 val = *(u32 *)buff; - - if (len != 4) - return -EINVAL; - - writel(val, priv->base + STM32MP_PWR_CR3); - - return 0; -} - -static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, - int len) -{ - struct stm32mp_pwr_priv *priv = dev_get_priv(dev); - - if (len != 4) - return -EINVAL; - - *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3); - - return 0; -} - -static int stm32mp_pwr_of_to_plat(struct udevice *dev) -{ - struct stm32mp_pwr_priv *priv = dev_get_priv(dev); - - priv->base = dev_read_addr(dev); - if (priv->base == FDT_ADDR_T_NONE) - return -EINVAL; - - return 0; -} - -static const struct pmic_child_info pwr_children_info[] = { - { .prefix = "reg", .driver = "stm32mp_pwr_regulator"}, - { .prefix = "usb", .driver = "stm32mp_pwr_regulator"}, - { }, -}; - -static int stm32mp_pwr_bind(struct udevice *dev) -{ - int children; - - children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info); - if (!children) - dev_dbg(dev, "no child found\n"); - - return 0; -} - -static struct dm_pmic_ops stm32mp_pwr_ops = { - .read = stm32mp_pwr_read, - .write = stm32mp_pwr_write, -}; - -static const struct udevice_id stm32mp_pwr_ids[] = { - { .compatible = "st,stm32mp1,pwr-reg" }, - { } -}; - -U_BOOT_DRIVER(stm32mp_pwr_pmic) = { - .name = "stm32mp_pwr_pmic", - .id = UCLASS_PMIC, - .of_match = stm32mp_pwr_ids, - .bind = stm32mp_pwr_bind, - .ops = &stm32mp_pwr_ops, - .of_to_plat = stm32mp_pwr_of_to_plat, - .priv_auto = sizeof(struct stm32mp_pwr_priv), -}; - -static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { - .enable = STM32MP_PWR_CR3_REG11DEN, - .ready = STM32MP_PWR_CR3_REG11RDY, - .name = "reg11" -}; - -static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = { - .enable = STM32MP_PWR_CR3_REG18DEN, - .ready = STM32MP_PWR_CR3_REG18RDY, - .name = "reg18" -}; - -static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = { - .enable = STM32MP_PWR_CR3_USB33DEN, - .ready = STM32MP_PWR_CR3_USB33RDY, - .name = "usb33" -}; - -static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { - &stm32mp_pwr_reg11, - &stm32mp_pwr_reg18, - &stm32mp_pwr_usb33, - NULL -}; - -static int stm32mp_pwr_regulator_probe(struct udevice *dev) -{ - const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; - struct dm_regulator_uclass_plat *uc_pdata; - - uc_pdata = dev_get_uclass_plat(dev); - - while (*p) { - int rc; - - rc = dev_read_stringlist_search(dev, "regulator-name", - (*p)->name); - if (rc >= 0) { - dev_dbg(dev, "found regulator %s\n", (*p)->name); - break; - } else if (rc != -ENODATA) { - return rc; - } - p++; - } - if (!*p) { - int i = 0; - const char *s; - - dev_dbg(dev, "regulator "); - while (dev_read_string_index(dev, "regulator-name", - i++, &s) >= 0) - dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s); - dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is"); - return -EINVAL; - } - - uc_pdata->type = REGULATOR_TYPE_FIXED; - dev_set_priv(dev, (void *)*p); - - return 0; -} - -static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) -{ - struct dm_regulator_uclass_plat *uc_pdata; - - uc_pdata = dev_get_uclass_plat(dev); - if (!uc_pdata) - return -ENXIO; - - if (uc_pdata->min_uV != uV) { - dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name); - return -EINVAL; - } - - return 0; -} - -static int stm32mp_pwr_regulator_get_value(struct udevice *dev) -{ - struct dm_regulator_uclass_plat *uc_pdata; - - uc_pdata = dev_get_uclass_plat(dev); - if (!uc_pdata) - return -ENXIO; - - if (uc_pdata->min_uV != uc_pdata->max_uV) { - dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name); - return -EINVAL; - } - - return uc_pdata->min_uV; -} - -static int stm32mp_pwr_regulator_get_enable(struct udevice *dev) -{ - const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); - int rc; - u32 reg; - - rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); - if (rc) - return rc; - - dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off"); - - return (reg & p->enable) != 0; -} - -static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable) -{ - const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); - int rc; - u32 reg; - u32 time_start; - - dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name); - - rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); - if (rc) - return rc; - - /* if regulator is already in the wanted state, nothing to do */ - if (!!(reg & p->enable) == enable) - return 0; - - reg &= ~p->enable; - if (enable) - reg |= p->enable; - - rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg)); - if (rc) - return rc; - - if (!enable) - return 0; - - /* waiting ready for enable */ - time_start = get_timer(0); - while (1) { - rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); - if (rc) - return rc; - if (reg & p->ready) - break; - if (get_timer(time_start) > CONFIG_SYS_HZ) { - dev_dbg(dev, "%s: timeout\n", p->name); - return -ETIMEDOUT; - } - } - return 0; -} - -static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = { - .set_value = stm32mp_pwr_regulator_set_value, - .get_value = stm32mp_pwr_regulator_get_value, - .get_enable = stm32mp_pwr_regulator_get_enable, - .set_enable = stm32mp_pwr_regulator_set_enable, -}; - -U_BOOT_DRIVER(stm32mp_pwr_regulator) = { - .name = "stm32mp_pwr_regulator", - .id = UCLASS_REGULATOR, - .ops = &stm32mp_pwr_regulator_ops, - .probe = stm32mp_pwr_regulator_probe, -}; diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/spl.c deleted file mode 100644 index 6c79259b2c8..00000000000 --- a/arch/arm/mach-stm32mp/spl.c +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -u32 spl_boot_device(void) -{ - u32 boot_mode; - - boot_mode = get_bootmode(); - - switch (boot_mode) { - case BOOT_FLASH_SD_1: - case BOOT_FLASH_EMMC_1: - return BOOT_DEVICE_MMC1; - case BOOT_FLASH_SD_2: - case BOOT_FLASH_EMMC_2: - return BOOT_DEVICE_MMC2; - case BOOT_SERIAL_UART_1: - case BOOT_SERIAL_UART_2: - case BOOT_SERIAL_UART_3: - case BOOT_SERIAL_UART_4: - case BOOT_SERIAL_UART_5: - case BOOT_SERIAL_UART_6: - case BOOT_SERIAL_UART_7: - case BOOT_SERIAL_UART_8: - return BOOT_DEVICE_UART; - case BOOT_SERIAL_USB_OTG: - return BOOT_DEVICE_DFU; - case BOOT_FLASH_NAND_FMC: - return BOOT_DEVICE_NAND; - case BOOT_FLASH_NOR_QSPI: - return BOOT_DEVICE_SPI; - case BOOT_FLASH_SPINAND_1: - return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */ - } - - return BOOT_DEVICE_MMC1; -} - -u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) -{ - return MMCSD_MODE_RAW; -} - -#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION -int spl_mmc_boot_partition(const u32 boot_device) -{ - switch (boot_device) { - case BOOT_DEVICE_MMC1: - return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION; - case BOOT_DEVICE_MMC2: - return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2; - default: - return -EINVAL; - } -} -#endif - -#ifdef CONFIG_SPL_DISPLAY_PRINT -void spl_display_print(void) -{ - DECLARE_GLOBAL_DATA_PTR; - const char *model; - - /* same code than show_board_info() but not compiled for SPL - * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c - */ - model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); - if (model) - log_info("Model: %s\n", model); -} -#endif - -__weak int board_early_init_f(void) -{ - return 0; -} - -uint32_t stm32mp_get_dram_size(void) -{ - struct ram_info ram; - struct udevice *dev; - int ret; - - if (uclass_get_device(UCLASS_RAM, 0, &dev)) - return 0; - - ret = ram_get_info(dev, &ram); - if (ret) - return 0; - - return ram.size; -} - -static int optee_get_reserved_memory(uint32_t *start, uint32_t *size) -{ - fdt_addr_t fdt_mem_size; - fdt_addr_t fdt_start; - ofnode node; - - node = ofnode_path("/reserved-memory/optee"); - if (!ofnode_valid(node)) - return 0; - - fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); - *start = fdt_start; - *size = fdt_mem_size; - return (fdt_start < 0) ? fdt_start : 0; -} - -#define CFG_SHMEM_SIZE 0x200000 -#define STM32_TZC_NSID_ALL 0xffff -#define STM32_TZC_FILTER_ALL 3 - -void stm32_init_tzc_for_optee(void) -{ - const uint32_t dram_size = stm32mp_get_dram_size(); - const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); - uint32_t optee_base, optee_size, tee_shmem_base; - const uintptr_t tzc = STM32_TZC_BASE; - int ret; - - if (dram_size == 0) - panic("Cannot determine DRAM size from devicetree\n"); - - ret = optee_get_reserved_memory(&optee_base, &optee_size); - if (ret < 0 || optee_size <= CFG_SHMEM_SIZE) - panic("Invalid OPTEE reserved memory in devicetree\n"); - - tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE; - - const struct tzc_region optee_config[] = { - { - .base = STM32_DDR_BASE, - .top = optee_base - 1, - .sec_mode = TZC_ATTR_SEC_NONE, - .nsec_id = STM32_TZC_NSID_ALL, - .filters_mask = STM32_TZC_FILTER_ALL, - }, { - .base = optee_base, - .top = tee_shmem_base - 1, - .sec_mode = TZC_ATTR_SEC_RW, - .nsec_id = 0, - .filters_mask = STM32_TZC_FILTER_ALL, - }, { - .base = tee_shmem_base, - .top = dram_top, - .sec_mode = TZC_ATTR_SEC_NONE, - .nsec_id = STM32_TZC_NSID_ALL, - .filters_mask = STM32_TZC_FILTER_ALL, - }, { - .top = 0, - } - }; - - flush_dcache_all(); - - tzc_configure(tzc, optee_config); - tzc_dump_config(tzc); - - dcache_disable(); -} - -void spl_board_prepare_for_optee(void *fdt) -{ - stm32_init_tzc_for_optee(); -} - -void board_init_f(ulong dummy) -{ - struct udevice *dev; - int ret; - - arch_cpu_init(); - mach_cpu_init(); - - ret = spl_early_init(); - if (ret) { - log_debug("spl_early_init() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_CLK, 0, &dev); - if (ret) { - log_debug("Clock init failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_RESET, 0, &dev); - if (ret) { - log_debug("Reset init failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); - if (ret) { - log_debug("%s: Cannot find pinctrl device\n", __func__); - hang(); - } - - /* enable console uart printing */ - preloader_console_init(); - - ret = board_early_init_f(); - if (ret) { - log_debug("board_early_init_f() failed: %d\n", ret); - hang(); - } - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - log_err("DRAM init failed: %d\n", ret); - hang(); - } - - /* - * activate cache on DDR only when DDR is fully initialized - * to avoid speculative access and issue in get_ram_size() - */ - if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) - mmu_set_region_dcache_behaviour(STM32_DDR_BASE, - CONFIG_DDR_CACHEABLE_SIZE, - DCACHE_DEFAULT_OPTION); -} - -void spl_board_prepare_for_boot(void) -{ - dcache_disable(); -} - -void spl_board_prepare_for_linux(void) -{ - dcache_disable(); -} diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile new file mode 100644 index 00000000000..94c7724127e --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o + +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + +obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += tzc400.o +else +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c new file mode 100644 index 00000000000..e07abbe21c1 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB allignment (see TTBR0_BASE_ADDR_MASK) + */ +u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000); + +struct lmb lmb; + +u32 get_bootmode(void) +{ + /* read bootmode from TAMP backup register */ + return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >> + TAMP_BOOT_MODE_SHIFT; +} + +/* + * weak function overidde: set the DDR/SYSRAM executable before to enable the + * MMU and configure DACR, for early early_enable_caches (SPL or pre-reloc) + */ +void dram_bank_mmu_setup(int bank) +{ + struct bd_info *bd = gd->bd; + int i; + phys_addr_t start; + phys_size_t size; + bool use_lmb = false; + enum dcache_option option; + + if (IS_ENABLED(CONFIG_SPL_BUILD)) { +/* STM32_SYSRAM_BASE exist only when SPL is supported */ +#ifdef CONFIG_SPL + start = ALIGN_DOWN(STM32_SYSRAM_BASE, MMU_SECTION_SIZE); + size = ALIGN(STM32_SYSRAM_SIZE, MMU_SECTION_SIZE); +#endif + } else if (gd->flags & GD_FLG_RELOC) { + /* bd->bi_dram is available only after relocation */ + start = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + use_lmb = true; + } else { + /* mark cacheable and executable the beggining of the DDR */ + start = STM32_DDR_BASE; + size = CONFIG_DDR_CACHEABLE_SIZE; + } + + for (i = start >> MMU_SECTION_SHIFT; + i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT); + i++) { + option = DCACHE_DEFAULT_OPTION; + if (use_lmb && lmb_is_reserved_flags(&lmb, i << MMU_SECTION_SHIFT, LMB_NOMAP)) + option = 0; /* INVALID ENTRY in TLB */ + set_section_dcache(i, option); + } +} +/* + * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + * or is deactivated in U-Boot entry function start.S::cpu_init_cp15 + */ +static void early_enable_caches(void) +{ + /* I-cache is already enabled in start.S: cpu_init_cp15 */ + + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = PGTABLE_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + early_enable_caches(); + + /* early armv7 timer init: needed for polling */ + timer_init(); + + return 0; +} + +/* weak function for SOC specific initialization */ +__weak void stm32mp_cpu_init(void) +{ +} + +int mach_cpu_init(void) +{ + u32 boot_mode; + + stm32mp_cpu_init(); + + boot_mode = get_bootmode(); + + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && + (boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART) + gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; + else if (IS_ENABLED(CONFIG_DEBUG_UART) && IS_ENABLED(CONFIG_SPL_BUILD)) + debug_uart_init(); + + return 0; +} + +void enable_caches(void) +{ + /* parse device tree when data cache is still activated */ + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + + /* I-cache is already enabled in start.S: icache_enable() not needed */ + + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * update MMU after relocation and enable the data cache + * warning: the TLB location udpated in board_f.c::reserve_mmu + */ + dcache_enable(); +} + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +static void setup_boot_mode(void) +{ + const u32 serial_addr[] = { + STM32_USART1_BASE, + STM32_USART2_BASE, + STM32_USART3_BASE, + STM32_UART4_BASE, + STM32_UART5_BASE, + STM32_USART6_BASE, + STM32_UART7_BASE, + STM32_UART8_BASE + }; + const u32 sdmmc_addr[] = { + STM32_SDMMC1_BASE, + STM32_SDMMC2_BASE, + STM32_SDMMC3_BASE + }; + char cmd[60]; + u32 boot_ctx = readl(TAMP_BOOT_CONTEXT); + u32 boot_mode = + (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT; + unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; + u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK); + struct udevice *dev; + + log_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n", + __func__, boot_ctx, boot_mode, instance, forced_mode); + switch (boot_mode & TAMP_BOOT_DEVICE_MASK) { + case BOOT_SERIAL_UART: + if (instance >= ARRAY_SIZE(serial_addr)) + break; + /* serial : search associated node in devicetree */ + sprintf(cmd, "serial@%x", serial_addr[instance]); + if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev)) { + /* restore console on error */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL)) + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_err("uart%d = %s not found in device tree!\n", + instance + 1, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "serial"); + env_set("boot_instance", cmd); + + /* restore console on uart when not used */ + if (IS_ENABLED(CONFIG_CMD_STM32PROG_SERIAL) && gd->cur_serial_dev != dev) { + gd->flags &= ~(GD_FLG_SILENT | + GD_FLG_DISABLE_CONSOLE); + log_info("serial boot with console enabled!\n"); + } + break; + case BOOT_SERIAL_USB: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SD: + case BOOT_FLASH_EMMC: + if (instance >= ARRAY_SIZE(sdmmc_addr)) + break; + /* search associated sdmmc node in devicetree */ + sprintf(cmd, "mmc@%x", sdmmc_addr[instance]); + if (uclass_get_device_by_name(UCLASS_MMC, cmd, &dev)) { + printf("mmc%d = %s not found in device tree!\n", + instance, cmd); + break; + } + sprintf(cmd, "%d", dev_seq(dev)); + env_set("boot_device", "mmc"); + env_set("boot_instance", cmd); + break; + case BOOT_FLASH_NAND: + env_set("boot_device", "nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_SPINAND: + env_set("boot_device", "spi-nand"); + env_set("boot_instance", "0"); + break; + case BOOT_FLASH_NOR: + env_set("boot_device", "nor"); + env_set("boot_instance", "0"); + break; + default: + env_set("boot_device", "invalid"); + env_set("boot_instance", ""); + log_err("unexpected boot mode = %x\n", boot_mode); + break; + } + + switch (forced_mode) { + case BOOT_FASTBOOT: + log_info("Enter fastboot!\n"); + env_set("preboot", "env set preboot; fastboot 0"); + break; + case BOOT_STM32PROG: + env_set("boot_device", "usb"); + env_set("boot_instance", "0"); + break; + case BOOT_UMS_MMC0: + case BOOT_UMS_MMC1: + case BOOT_UMS_MMC2: + log_info("Enter UMS!\n"); + instance = forced_mode - BOOT_UMS_MMC0; + sprintf(cmd, "env set preboot; ums 0 mmc %d", instance); + env_set("preboot", cmd); + break; + case BOOT_RECOVERY: + env_set("preboot", "env set preboot; run altbootcmd"); + break; + case BOOT_NORMAL: + break; + default: + log_debug("unexpected forced boot mode = %x\n", forced_mode); + break; + } + + /* clear TAMP for next reboot */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL); +} + +/* + * If there is no MAC address in the environment, then it will be initialized + * (silently) from the value in the OTP. + */ +__weak int setup_mac_address(void) +{ + int ret; + int i; + u32 otp[3]; + uchar enetaddr[6]; + struct udevice *dev; + int nb_eth, nb_otp, index; + + if (!IS_ENABLED(CONFIG_NET)) + return 0; + + nb_eth = get_eth_nb(); + + /* 6 bytes for each MAC addr and 4 bytes for each OTP */ + nb_otp = DIV_ROUND_UP(6 * nb_eth, 4); + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC), otp, 4 * nb_otp); + if (ret < 0) + return ret; + + for (index = 0; index < nb_eth; index++) { + /* MAC already in environment */ + if (eth_env_get_enetaddr_by_index("eth", index, enetaddr)) + continue; + + for (i = 0; i < 6; i++) + enetaddr[i] = ((uint8_t *)&otp)[i + 6 * index]; + + if (!is_valid_ethaddr(enetaddr)) { + log_err("invalid MAC address %d in OTP %pM\n", + index, enetaddr); + return -EINVAL; + } + log_debug("OTP MAC address %d = %pM\n", index, enetaddr); + ret = eth_env_set_enetaddr_by_index("eth", index, enetaddr); + if (ret) { + log_err("Failed to set mac address %pM from OTP: %d\n", + enetaddr, ret); + return ret; + } + } + + return 0; +} + +static int setup_serial_number(void) +{ + char serial_string[25]; + u32 otp[3] = {0, 0, 0 }; + struct udevice *dev; + int ret; + + if (env_get("serial#")) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(stm32mp_bsec), + &dev); + if (ret) + return ret; + + ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL), + otp, sizeof(otp)); + if (ret < 0) + return ret; + + sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]); + env_set("serial#", serial_string); + + return 0; +} + +__weak void stm32mp_misc_init(void) +{ +} + +int arch_misc_init(void) +{ + setup_boot_mode(); + setup_mac_address(); + setup_serial_number(); + stm32mp_misc_init(); + + return 0; +} + +/* + * Without forcing the ".data" section, this would get saved in ".bss". BSS + * will be cleared soon after, so it's not suitable. + */ +static uintptr_t rom_api_table __section(".data"); +static uintptr_t nt_fw_dtb __section(".data"); + +/* + * The ROM gives us the API location in r0 when starting. This is only available + * during SPL, as there isn't (yet) a mechanism to pass this on to u-boot. Save + * the FDT address provided by TF-A in r2 at boot time. This function is called + * from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + if (IS_ENABLED(CONFIG_STM32_ECDSA_VERIFY)) + rom_api_table = r0; + + if (IS_ENABLED(CONFIG_TFABOOT)) + nt_fw_dtb = r2; + + save_boot_params_ret(); +} + +uintptr_t get_stm32mp_rom_api_table(void) +{ + return rom_api_table; +} + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +#ifdef CONFIG_SPL_BUILD +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + typedef void __noreturn (*image_entry_stm32_t)(u32 romapi); + uintptr_t romapi = get_stm32mp_rom_api_table(); + + image_entry_stm32_t image_entry = + (image_entry_stm32_t)spl_image->entry_point; + + printf("image entry point: 0x%lx\n", spl_image->entry_point); + image_entry(romapi); +} +#endif diff --git a/arch/arm/mach-stm32mp/stm32mp1/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c new file mode 100644 index 00000000000..de5c5a55ea0 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/fdt.c @@ -0,0 +1,514 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2019-2020, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include + +#define ETZPC_DECPROT(n) (STM32_ETZPC_BASE + 0x10 + 4 * (n)) +#define ETZPC_DECPROT_NB 6 + +#define DECPROT_MASK 0x03 +#define NB_PROT_PER_REG 0x10 +#define DECPROT_NB_BITS 2 + +#define DECPROT_SECURED 0x00 +#define DECPROT_WRITE_SECURE 0x01 +#define DECPROT_MCU_ISOLATION 0x02 +#define DECPROT_NON_SECURED 0x03 + +#define ETZPC_RESERVED 0xffffffff + +#define STM32MP13_FDCAN_BASE 0x4400F000 +#define STM32MP13_ADC1_BASE 0x48003000 +#define STM32MP13_TSC_BASE 0x5000B000 +#define STM32MP13_CRYP_BASE 0x54002000 +#define STM32MP13_ETH2_BASE 0x5800E000 +#define STM32MP13_DCMIPP_BASE 0x5A000000 +#define STM32MP13_LTDC_BASE 0x5A010000 + +#define STM32MP15_FDCAN_BASE 0x4400e000 +#define STM32MP15_CRYP2_BASE 0x4c005000 +#define STM32MP15_CRYP1_BASE 0x54001000 +#define STM32MP15_GPU_BASE 0x59000000 +#define STM32MP15_DSI_BASE 0x5a000000 + +static const u32 stm32mp13_ip_addr[] = { + 0x50025000, /* 0 VREFBUF APB3 */ + 0x50021000, /* 1 LPTIM2 APB3 */ + 0x50022000, /* 2 LPTIM3 APB3 */ + STM32MP13_LTDC_BASE, /* 3 LTDC APB4 */ + STM32MP13_DCMIPP_BASE, /* 4 DCMIPP APB4 */ + 0x5A006000, /* 5 USBPHYCTRL APB4 */ + 0x5A003000, /* 6 DDRCTRLPHY APB4 */ + ETZPC_RESERVED, /* 7 Reserved*/ + ETZPC_RESERVED, /* 8 Reserved*/ + ETZPC_RESERVED, /* 9 Reserved*/ + 0x5C006000, /* 10 TZC APB5 */ + 0x58001000, /* 11 MCE APB5 */ + 0x5C000000, /* 12 IWDG1 APB5 */ + 0x5C008000, /* 13 STGENC APB5 */ + ETZPC_RESERVED, /* 14 Reserved*/ + ETZPC_RESERVED, /* 15 Reserved*/ + 0x4C000000, /* 16 USART1 APB6 */ + 0x4C001000, /* 17 USART2 APB6 */ + 0x4C002000, /* 18 SPI4 APB6 */ + 0x4C003000, /* 19 SPI5 APB6 */ + 0x4C004000, /* 20 I2C3 APB6 */ + 0x4C005000, /* 21 I2C4 APB6 */ + 0x4C006000, /* 22 I2C5 APB6 */ + 0x4C007000, /* 23 TIM12 APB6 */ + 0x4C008000, /* 24 TIM13 APB6 */ + 0x4C009000, /* 25 TIM14 APB6 */ + 0x4C00A000, /* 26 TIM15 APB6 */ + 0x4C00B000, /* 27 TIM16 APB6 */ + 0x4C00C000, /* 28 TIM17 APB6 */ + ETZPC_RESERVED, /* 29 Reserved*/ + ETZPC_RESERVED, /* 30 Reserved*/ + ETZPC_RESERVED, /* 31 Reserved*/ + STM32MP13_ADC1_BASE, /* 32 ADC1 AHB2 */ + 0x48004000, /* 33 ADC2 AHB2 */ + 0x49000000, /* 34 OTG AHB2 */ + ETZPC_RESERVED, /* 35 Reserved*/ + ETZPC_RESERVED, /* 36 Reserved*/ + STM32MP13_TSC_BASE, /* 37 TSC AHB4 */ + ETZPC_RESERVED, /* 38 Reserved*/ + ETZPC_RESERVED, /* 39 Reserved*/ + 0x54004000, /* 40 RNG AHB5 */ + 0x54003000, /* 41 HASH AHB5 */ + STM32MP13_CRYP_BASE, /* 42 CRYPT AHB5 */ + 0x54005000, /* 43 SAES AHB5 */ + 0x54006000, /* 44 PKA AHB5 */ + 0x54000000, /* 45 BKPSRAM AHB5 */ + ETZPC_RESERVED, /* 46 Reserved*/ + ETZPC_RESERVED, /* 47 Reserved*/ + 0x5800A000, /* 48 ETH1 AHB6 */ + STM32MP13_ETH2_BASE, /* 49 ETH2 AHB6 */ + 0x58005000, /* 50 SDMMC1 AHB6 */ + 0x58007000, /* 51 SDMMC2 AHB6 */ + ETZPC_RESERVED, /* 52 Reserved*/ + ETZPC_RESERVED, /* 53 Reserved*/ + 0x58002000, /* 54 FMC AHB6 */ + 0x58003000, /* 55 QSPI AHB6 */ + ETZPC_RESERVED, /* 56 Reserved*/ + ETZPC_RESERVED, /* 57 Reserved*/ + ETZPC_RESERVED, /* 58 Reserved*/ + ETZPC_RESERVED, /* 59 Reserved*/ + 0x30000000, /* 60 SRAM1 MLAHB */ + 0x30004000, /* 61 SRAM2 MLAHB */ + 0x30006000, /* 62 SRAM3 MLAHB */ + ETZPC_RESERVED, /* 63 Reserved*/ + ETZPC_RESERVED, /* 64 Reserved*/ + ETZPC_RESERVED, /* 65 Reserved*/ + ETZPC_RESERVED, /* 66 Reserved*/ + ETZPC_RESERVED, /* 67 Reserved*/ + ETZPC_RESERVED, /* 68 Reserved*/ + ETZPC_RESERVED, /* 69 Reserved*/ + ETZPC_RESERVED, /* 70 Reserved*/ + ETZPC_RESERVED, /* 71 Reserved*/ + ETZPC_RESERVED, /* 72 Reserved*/ + ETZPC_RESERVED, /* 73 Reserved*/ + ETZPC_RESERVED, /* 74 Reserved*/ + ETZPC_RESERVED, /* 75 Reserved*/ + ETZPC_RESERVED, /* 76 Reserved*/ + ETZPC_RESERVED, /* 77 Reserved*/ + ETZPC_RESERVED, /* 78 Reserved*/ + ETZPC_RESERVED, /* 79 Reserved*/ + ETZPC_RESERVED, /* 80 Reserved*/ + ETZPC_RESERVED, /* 81 Reserved*/ + ETZPC_RESERVED, /* 82 Reserved*/ + ETZPC_RESERVED, /* 83 Reserved*/ + ETZPC_RESERVED, /* 84 Reserved*/ + ETZPC_RESERVED, /* 85 Reserved*/ + ETZPC_RESERVED, /* 86 Reserved*/ + ETZPC_RESERVED, /* 87 Reserved*/ + ETZPC_RESERVED, /* 88 Reserved*/ + ETZPC_RESERVED, /* 89 Reserved*/ + ETZPC_RESERVED, /* 90 Reserved*/ + ETZPC_RESERVED, /* 91 Reserved*/ + ETZPC_RESERVED, /* 92 Reserved*/ + ETZPC_RESERVED, /* 93 Reserved*/ + ETZPC_RESERVED, /* 94 Reserved*/ + ETZPC_RESERVED, /* 95 Reserved*/ +}; + +static const u32 stm32mp15_ip_addr[] = { + 0x5c008000, /* 00 stgenc */ + 0x54000000, /* 01 bkpsram */ + 0x5c003000, /* 02 iwdg1 */ + 0x5c000000, /* 03 usart1 */ + 0x5c001000, /* 04 spi6 */ + 0x5c002000, /* 05 i2c4 */ + ETZPC_RESERVED, /* 06 reserved */ + 0x54003000, /* 07 rng1 */ + 0x54002000, /* 08 hash1 */ + STM32MP15_CRYP1_BASE, /* 09 cryp1 */ + 0x5a003000, /* 0A ddrctrl */ + 0x5a004000, /* 0B ddrphyc */ + 0x5c009000, /* 0C i2c6 */ + ETZPC_RESERVED, /* 0D reserved */ + ETZPC_RESERVED, /* 0E reserved */ + ETZPC_RESERVED, /* 0F reserved */ + 0x40000000, /* 10 tim2 */ + 0x40001000, /* 11 tim3 */ + 0x40002000, /* 12 tim4 */ + 0x40003000, /* 13 tim5 */ + 0x40004000, /* 14 tim6 */ + 0x40005000, /* 15 tim7 */ + 0x40006000, /* 16 tim12 */ + 0x40007000, /* 17 tim13 */ + 0x40008000, /* 18 tim14 */ + 0x40009000, /* 19 lptim1 */ + 0x4000a000, /* 1A wwdg1 */ + 0x4000b000, /* 1B spi2 */ + 0x4000c000, /* 1C spi3 */ + 0x4000d000, /* 1D spdifrx */ + 0x4000e000, /* 1E usart2 */ + 0x4000f000, /* 1F usart3 */ + 0x40010000, /* 20 uart4 */ + 0x40011000, /* 21 uart5 */ + 0x40012000, /* 22 i2c1 */ + 0x40013000, /* 23 i2c2 */ + 0x40014000, /* 24 i2c3 */ + 0x40015000, /* 25 i2c5 */ + 0x40016000, /* 26 cec */ + 0x40017000, /* 27 dac */ + 0x40018000, /* 28 uart7 */ + 0x40019000, /* 29 uart8 */ + ETZPC_RESERVED, /* 2A reserved */ + ETZPC_RESERVED, /* 2B reserved */ + 0x4001c000, /* 2C mdios */ + ETZPC_RESERVED, /* 2D reserved */ + ETZPC_RESERVED, /* 2E reserved */ + ETZPC_RESERVED, /* 2F reserved */ + 0x44000000, /* 30 tim1 */ + 0x44001000, /* 31 tim8 */ + ETZPC_RESERVED, /* 32 reserved */ + 0x44003000, /* 33 usart6 */ + 0x44004000, /* 34 spi1 */ + 0x44005000, /* 35 spi4 */ + 0x44006000, /* 36 tim15 */ + 0x44007000, /* 37 tim16 */ + 0x44008000, /* 38 tim17 */ + 0x44009000, /* 39 spi5 */ + 0x4400a000, /* 3A sai1 */ + 0x4400b000, /* 3B sai2 */ + 0x4400c000, /* 3C sai3 */ + 0x4400d000, /* 3D dfsdm */ + STM32MP15_FDCAN_BASE, /* 3E tt_fdcan */ + ETZPC_RESERVED, /* 3F reserved */ + 0x50021000, /* 40 lptim2 */ + 0x50022000, /* 41 lptim3 */ + 0x50023000, /* 42 lptim4 */ + 0x50024000, /* 43 lptim5 */ + 0x50027000, /* 44 sai4 */ + 0x50025000, /* 45 vrefbuf */ + 0x4c006000, /* 46 dcmi */ + 0x4c004000, /* 47 crc2 */ + 0x48003000, /* 48 adc */ + 0x4c002000, /* 49 hash2 */ + 0x4c003000, /* 4A rng2 */ + STM32MP15_CRYP2_BASE, /* 4B cryp2 */ + ETZPC_RESERVED, /* 4C reserved */ + ETZPC_RESERVED, /* 4D reserved */ + ETZPC_RESERVED, /* 4E reserved */ + ETZPC_RESERVED, /* 4F reserved */ + ETZPC_RESERVED, /* 50 sram1 */ + ETZPC_RESERVED, /* 51 sram2 */ + ETZPC_RESERVED, /* 52 sram3 */ + ETZPC_RESERVED, /* 53 sram4 */ + ETZPC_RESERVED, /* 54 retram */ + 0x49000000, /* 55 otg */ + 0x48004000, /* 56 sdmmc3 */ + 0x48005000, /* 57 dlybsd3 */ + 0x48000000, /* 58 dma1 */ + 0x48001000, /* 59 dma2 */ + 0x48002000, /* 5A dmamux */ + 0x58002000, /* 5B fmc */ + 0x58003000, /* 5C qspi */ + 0x58004000, /* 5D dlybq */ + 0x5800a000, /* 5E eth */ + ETZPC_RESERVED, /* 5F reserved */ +}; + +/* fdt helper */ +static bool fdt_disable_subnode_by_address(void *fdt, int offset, u32 addr) +{ + int node; + fdt_addr_t regs; + + for (node = fdt_first_subnode(fdt, offset); + node >= 0; + node = fdt_next_subnode(fdt, node)) { + regs = fdtdec_get_addr(fdt, node, "reg"); + if (addr == regs) { + if (fdtdec_get_is_enabled(fdt, node)) { + fdt_status_disabled(fdt, node); + + return true; + } + return false; + } + } + + return false; +} + +static int stm32_fdt_fixup_etzpc(void *fdt, int soc_node) +{ + const u32 *array; + int array_size, i; + int offset, shift; + u32 addr, status, decprot[ETZPC_DECPROT_NB]; + + if (IS_ENABLED(CONFIG_STM32MP13x)) { + array = stm32mp13_ip_addr; + array_size = ARRAY_SIZE(stm32mp13_ip_addr); + } + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + array = stm32mp15_ip_addr; + array_size = ARRAY_SIZE(stm32mp15_ip_addr); + } + + for (i = 0; i < ETZPC_DECPROT_NB; i++) + decprot[i] = readl(ETZPC_DECPROT(i)); + + for (i = 0; i < array_size; i++) { + offset = i / NB_PROT_PER_REG; + shift = (i % NB_PROT_PER_REG) * DECPROT_NB_BITS; + status = (decprot[offset] >> shift) & DECPROT_MASK; + addr = array[i]; + + log_debug("ETZPC: 0x%08x decprot %d=%d\n", addr, i, status); + + if (addr == ETZPC_RESERVED || + status == DECPROT_NON_SECURED) + continue; + + if (fdt_disable_subnode_by_address(fdt, soc_node, addr)) + log_notice("ETZPC: 0x%08x node disabled, decprot %d=%d\n", + addr, i, status); + } + + return 0; +} + +/* deactivate all the cpu except core 0 */ +static void stm32_fdt_fixup_cpu(void *blob, char *name) +{ + int off; + u32 reg; + + off = fdt_path_offset(blob, "/cpus"); + if (off < 0) { + log_warning("%s: couldn't find /cpus node\n", __func__); + return; + } + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + reg = fdtdec_get_addr(blob, off, "reg"); + if (reg != 0) { + fdt_del_node(blob, off); + log_notice("FDT: cpu %d node remove for %s\n", + reg, name); + /* after delete we can't trust the offsets anymore */ + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } +} + +static void stm32_fdt_disable(void *fdt, int offset, u32 addr, + const char *string, const char *name) +{ + if (fdt_disable_subnode_by_address(fdt, offset, addr)) + log_notice("FDT: %s@%08x node disabled for %s\n", + string, addr, name); +} + +static void stm32_fdt_disable_optee(void *blob) +{ + int off, node; + + /* Delete "optee" firmware node */ + off = fdt_node_offset_by_compatible(blob, -1, "linaro,optee-tz"); + if (off >= 0 && fdtdec_get_is_enabled(blob, off)) + fdt_del_node(blob, off); + + /* Delete "optee@..." reserved-memory node */ + off = fdt_path_offset(blob, "/reserved-memory/"); + if (off < 0) + return; + for (node = fdt_first_subnode(blob, off); + node >= 0; + node = fdt_next_subnode(blob, node)) { + if (strncmp(fdt_get_name(blob, node, NULL), "optee@", 6)) + continue; + + if (fdt_del_node(blob, node)) + printf("Failed to remove optee reserved-memory node\n"); + } +} + +static void stm32mp13_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + switch (cpu) { + case CPU_STM32MP131Fxx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Cxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_FDCAN_BASE, "can", name); + stm32_fdt_disable(blob, soc, STM32MP13_ADC1_BASE, "adc", name); + fallthrough; + case CPU_STM32MP133Fxx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Cxx: + case CPU_STM32MP133Axx: + stm32_fdt_disable(blob, soc, STM32MP13_LTDC_BASE, "ltdc", name); + stm32_fdt_disable(blob, soc, STM32MP13_DCMIPP_BASE, "dcmipp", + name); + stm32_fdt_disable(blob, soc, STM32MP13_TSC_BASE, "tsc", name); + break; + default: + break; + } + + switch (cpu) { + case CPU_STM32MP135Dxx: + case CPU_STM32MP135Axx: + case CPU_STM32MP133Dxx: + case CPU_STM32MP133Axx: + case CPU_STM32MP131Dxx: + case CPU_STM32MP131Axx: + stm32_fdt_disable(blob, soc, STM32MP13_CRYP_BASE, "cryp", name); + break; + default: + break; + } +} + +static void stm32mp15_fdt_fixup(void *blob, int soc, u32 cpu, char *name) +{ + u32 pkg; + + switch (cpu) { + case CPU_STM32MP151Fxx: + case CPU_STM32MP151Dxx: + case CPU_STM32MP151Cxx: + case CPU_STM32MP151Axx: + stm32_fdt_fixup_cpu(blob, name); + /* after cpu delete we can't trust the soc offsets anymore */ + soc = fdt_path_offset(blob, "/soc"); + stm32_fdt_disable(blob, soc, STM32MP15_FDCAN_BASE, "can", name); + fallthrough; + case CPU_STM32MP153Fxx: + case CPU_STM32MP153Dxx: + case CPU_STM32MP153Cxx: + case CPU_STM32MP153Axx: + stm32_fdt_disable(blob, soc, STM32MP15_GPU_BASE, "gpu", name); + stm32_fdt_disable(blob, soc, STM32MP15_DSI_BASE, "dsi", name); + break; + default: + break; + } + switch (cpu) { + case CPU_STM32MP157Dxx: + case CPU_STM32MP157Axx: + case CPU_STM32MP153Dxx: + case CPU_STM32MP153Axx: + case CPU_STM32MP151Dxx: + case CPU_STM32MP151Axx: + stm32_fdt_disable(blob, soc, STM32MP15_CRYP1_BASE, "cryp", + name); + stm32_fdt_disable(blob, soc, STM32MP15_CRYP2_BASE, "cryp", + name); + break; + default: + break; + } + switch (get_cpu_package()) { + case STM32MP15_PKG_AA_LBGA448: + pkg = STM32MP_PKG_AA; + break; + case STM32MP15_PKG_AB_LBGA354: + pkg = STM32MP_PKG_AB; + break; + case STM32MP15_PKG_AC_TFBGA361: + pkg = STM32MP_PKG_AC; + break; + case STM32MP15_PKG_AD_TFBGA257: + pkg = STM32MP_PKG_AD; + break; + default: + pkg = 0; + break; + } + if (pkg) { + do_fixup_by_compat_u32(blob, "st,stm32mp157-pinctrl", + "st,package", pkg, false); + do_fixup_by_compat_u32(blob, "st,stm32mp157-z-pinctrl", + "st,package", pkg, false); + } +} + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + int ret = 0; + int soc; + u32 cpu; + char name[SOC_NAME_SIZE]; + + soc = fdt_path_offset(blob, "/soc"); + /* when absent, nothing to do */ + if (soc == -FDT_ERR_NOTFOUND) + return 0; + if (soc < 0) + return soc; + + if (CONFIG_IS_ENABLED(STM32_ETZPC)) { + ret = stm32_fdt_fixup_etzpc(blob, soc); + if (ret) + return ret; + } + + /* MPUs Part Numbers and name*/ + cpu = get_cpu_type(); + get_soc_name(name); + + if (IS_ENABLED(CONFIG_STM32MP13x)) + stm32mp13_fdt_fixup(blob, soc, cpu, name); + + if (IS_ENABLED(CONFIG_STM32MP15x)) { + stm32mp15_fdt_fixup(blob, soc, cpu, name); + + /* + * TEMP: remove OP-TEE nodes in kernel device tree + * copied from U-Boot device tree by optee_copy_fdt_nodes + * when OP-TEE is not detected (probe failed) + * these OP-TEE nodes are present in -u-boot.dtsi + * under CONFIG_STM32MP15x_STM32IMAGE only for compatibility + * when FIP is not used by TF-A + */ + if (IS_ENABLED(CONFIG_STM32MP15x_STM32IMAGE) && + !tee_find_device(NULL, NULL, NULL, NULL)) + stm32_fdt_disable_optee(blob); + } + + return ret; +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c new file mode 100644 index 00000000000..8cdeb0ab3f2 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/psci.c @@ -0,0 +1,808 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* PWR */ +#define PWR_CR3 0x0c +#define PWR_MPUCR 0x10 + +#define PWR_CR3_DDRSREN BIT(10) +#define PWR_CR3_DDRRETEN BIT(12) + +#define PWR_MPUCR_PDDS BIT(0) +#define PWR_MPUCR_CSTDBYDIS BIT(3) +#define PWR_MPUCR_CSSF BIT(9) + +/* RCC */ +#define RCC_MSSCKSELR 0x48 +#define RCC_DDRITFCR 0xd8 + +#define RCC_DDRITFCR_DDRC1EN BIT(0) +#define RCC_DDRITFCR_DDRC1LPEN BIT(1) +#define RCC_DDRITFCR_DDRC2EN BIT(2) +#define RCC_DDRITFCR_DDRC2LPEN BIT(3) +#define RCC_DDRITFCR_DDRPHYCEN BIT(4) +#define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) +#define RCC_DDRITFCR_DDRCAPBEN BIT(6) +#define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) +#define RCC_DDRITFCR_AXIDCGEN BIT(8) +#define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) +#define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) +#define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK(22, 20) +#define RCC_DDRITFCR_GSKPCTRL BIT(24) + +#define RCC_MP_SREQSETR 0x104 +#define RCC_MP_SREQCLRR 0x108 + +#define RCC_MP_CIER 0x414 +#define RCC_MP_CIFR 0x418 +#define RCC_MP_CIFR_WKUPF BIT(20) + +#define RCC_MCUDIVR 0x830 +#define RCC_PLL3CR 0x880 +#define RCC_PLL4CR 0x894 + +/* SYSCFG */ +#define SYSCFG_CMPCR 0x20 +#define SYSCFG_CMPCR_SW_CTRL BIT(2) +#define SYSCFG_CMPENSETR 0x24 +#define SYSCFG_CMPENCLRR 0x28 +#define SYSCFG_CMPENR_MPUEN BIT(0) + +/* DDR Controller registers offsets */ +#define DDRCTRL_STAT 0x004 +#define DDRCTRL_PWRCTL 0x030 +#define DDRCTRL_PWRTMG 0x034 +#define DDRCTRL_HWLPCTL 0x038 +#define DDRCTRL_DFIMISC 0x1b0 +#define DDRCTRL_SWCTL 0x320 +#define DDRCTRL_SWSTAT 0x324 +#define DDRCTRL_PSTAT 0x3fc +#define DDRCTRL_PCTRL_0 0x490 +#define DDRCTRL_PCTRL_1 0x540 + +/* DDR Controller Register fields */ +#define DDRCTRL_STAT_OPERATING_MODE_MASK GENMASK(2, 0) +#define DDRCTRL_STAT_OPERATING_MODE_NORMAL 0x1 +#define DDRCTRL_STAT_OPERATING_MODE_SR 0x3 +#define DDRCTRL_STAT_SELFREF_TYPE_MASK GENMASK(5, 4) +#define DDRCTRL_STAT_SELFREF_TYPE_ASR (0x3 << 4) +#define DDRCTRL_STAT_SELFREF_TYPE_SR (0x2 << 4) + +#define DDRCTRL_PWRCTL_SELFREF_EN BIT(0) +#define DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE BIT(3) +#define DDRCTRL_PWRCTL_SELFREF_SW BIT(5) + +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK GENMASK(23, 16) +#define DDRCTRL_PWRTMG_SELFREF_TO_X32_0 BIT(16) + +#define DDRCTRL_HWLPCTL_HW_LP_EN BIT(0) + +#define DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) + +#define DDRCTRL_SWCTL_SW_DONE BIT(0) + +#define DDRCTRL_SWSTAT_SW_DONE_ACK BIT(0) + +#define DDRCTRL_PSTAT_RD_PORT_BUSY_0 BIT(0) +#define DDRCTRL_PSTAT_RD_PORT_BUSY_1 BIT(1) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_0 BIT(16) +#define DDRCTRL_PSTAT_WR_PORT_BUSY_1 BIT(17) + +#define DDRCTRL_PCTRL_N_PORT_EN BIT(0) + +/* DDR PHY registers offsets */ +#define DDRPHYC_PIR 0x004 +#define DDRPHYC_PGSR 0x00c +#define DDRPHYC_ACDLLCR 0x014 +#define DDRPHYC_ACIOCR 0x024 +#define DDRPHYC_DXCCR 0x028 +#define DDRPHYC_DSGCR 0x02c +#define DDRPHYC_ZQ0CR0 0x180 +#define DDRPHYC_DX0DLLCR 0x1cc +#define DDRPHYC_DX1DLLCR 0x20c +#define DDRPHYC_DX2DLLCR 0x24c +#define DDRPHYC_DX3DLLCR 0x28c + +/* DDR PHY Register fields */ +#define DDRPHYC_PIR_INIT BIT(0) +#define DDRPHYC_PIR_DLLSRST BIT(1) +#define DDRPHYC_PIR_DLLLOCK BIT(2) +#define DDRPHYC_PIR_ITMSRST BIT(4) + +#define DDRPHYC_PGSR_IDONE BIT(0) + +#define DDRPHYC_ACDLLCR_DLLSRST BIT(30) +#define DDRPHYC_ACDLLCR_DLLDIS BIT(31) + +#define DDRPHYC_ACIOCR_ACOE BIT(1) +#define DDRPHYC_ACIOCR_ACPDD BIT(3) +#define DDRPHYC_ACIOCR_ACPDR BIT(4) +#define DDRPHYC_ACIOCR_CKPDD_MASK GENMASK(10, 8) +#define DDRPHYC_ACIOCR_CKPDD_0 BIT(8) +#define DDRPHYC_ACIOCR_CKPDR_MASK GENMASK(13, 11) +#define DDRPHYC_ACIOCR_CKPDR_0 BIT(11) +#define DDRPHYC_ACIOCR_CSPDD_MASK GENMASK(20, 18) +#define DDRPHYC_ACIOCR_CSPDD_0 BIT(18) + +#define DDRPHYC_DXCCR_DXPDD BIT(2) +#define DDRPHYC_DXCCR_DXPDR BIT(3) + +#define DDRPHYC_DSGCR_CKEPDD_MASK GENMASK(19, 16) +#define DDRPHYC_DSGCR_CKEPDD_0 BIT(16) +#define DDRPHYC_DSGCR_ODTPDD_MASK GENMASK(23, 20) +#define DDRPHYC_DSGCR_ODTPDD_0 BIT(20) +#define DDRPHYC_DSGCR_NL2PD BIT(24) +#define DDRPHYC_DSGCR_CKOE BIT(28) + +#define DDRPHYC_ZQ0CRN_ZQPD BIT(31) + +#define DDRPHYC_DXNDLLCR_DLLDIS BIT(31) + +#define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xca7face0 +#define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xca7face1 + +#define MPIDR_AFF0 GENMASK(7, 0) + +#define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404) +#define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) +#define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) +#define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) + +/* IWDG */ +#define IWDG_KR 0x00 +#define IWDG_KR_RELOAD_KEY 0xaaaa +#define IWDG_EWCR 0x14 +#define IWDG_EWCR_EWIC BIT(14) + +#define STM32MP1_PSCI_NR_CPUS 2 +#if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS +#error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" +#endif + +u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = { + PSCI_AFFINITY_LEVEL_ON, + PSCI_AFFINITY_LEVEL_OFF}; + +static u32 __secure_data cntfrq; + +static u32 __secure cp15_read_cntfrq(void) +{ + u32 frq; + + asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq)); + + return frq; +} + +static void __secure cp15_write_cntfrq(u32 frq) +{ + asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq)); +} + +static inline void psci_set_state(int cpu, u8 state) +{ + psci_state[cpu] = state; + dsb(); + isb(); +} + +static u32 __secure stm32mp_get_gicd_base_address(void) +{ + u32 periphbase; + + /* get the GIC base address from the CBAR register */ + asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); + + return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; +} + +static void __secure stm32mp_raise_sgi0(int cpu) +{ + u32 gic_dist_addr; + + gic_dist_addr = stm32mp_get_gicd_base_address(); + + /* ask cpu with SGI0 */ + writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR); +} + +void __secure psci_arch_cpu_entry(void) +{ + u32 cpu = psci_get_cpu_id(); + + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON); + + /* write the saved cntfrq */ + cp15_write_cntfrq(cntfrq); + + /* reset magic in TAMP register */ + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); +} + +s32 __secure psci_features(u32 function_id, u32 psci_fid) +{ + switch (psci_fid) { + case ARM_PSCI_0_2_FN_PSCI_VERSION: + case ARM_PSCI_0_2_FN_CPU_OFF: + case ARM_PSCI_0_2_FN_CPU_ON: + case ARM_PSCI_0_2_FN_AFFINITY_INFO: + case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE: + case ARM_PSCI_0_2_FN_SYSTEM_OFF: + case ARM_PSCI_0_2_FN_SYSTEM_RESET: + case ARM_PSCI_1_0_FN_SYSTEM_SUSPEND: + return 0x0; + } + return ARM_PSCI_RET_NI; +} + +u32 __secure psci_version(void) +{ + return ARM_PSCI_VER_1_0; +} + +s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity, + u32 lowest_affinity_level) +{ + u32 cpu = target_affinity & MPIDR_AFF0; + + if (lowest_affinity_level > 0) + return ARM_PSCI_RET_INVAL; + + if (target_affinity & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= STM32MP1_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + return psci_state[cpu]; +} + +u32 __secure psci_migrate_info_type(void) +{ + /* + * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf + * return 2 = Trusted OS is either not present or does not require + * migration, system of this type does not require the caller + * to use the MIGRATE function. + * MIGRATE function calls return NOT_SUPPORTED. + */ + return 2; +} + +s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc, + u32 context_id) +{ + u32 cpu = target_cpu & MPIDR_AFF0; + + if (target_cpu & ~MPIDR_AFF0) + return ARM_PSCI_RET_INVAL; + + if (cpu >= STM32MP1_PSCI_NR_CPUS) + return ARM_PSCI_RET_INVAL; + + if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON) + return ARM_PSCI_RET_ALREADY_ON; + + /* read and save cntfrq of current cpu to write on target cpu */ + cntfrq = cp15_read_cntfrq(); + + /* reset magic in TAMP register */ + if (readl(TAMP_BACKUP_MAGIC_NUMBER)) + writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER); + /* + * ROM code need a first SGI0 after core reset + * core is ready when magic is set to 0 in ROM code + */ + while (readl(TAMP_BACKUP_MAGIC_NUMBER)) + stm32mp_raise_sgi0(cpu); + + /* store target PC and context id*/ + psci_save(cpu, pc, context_id); + + /* write entrypoint in backup RAM register */ + writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING); + + /* write magic number in backup register */ + if (cpu == 0x01) + writel(BOOT_API_A7_CORE1_MAGIC_NUMBER, + TAMP_BACKUP_MAGIC_NUMBER); + else + writel(BOOT_API_A7_CORE0_MAGIC_NUMBER, + TAMP_BACKUP_MAGIC_NUMBER); + + /* Generate an IT to start the core */ + stm32mp_raise_sgi0(cpu); + + return ARM_PSCI_RET_SUCCESS; +} + +s32 __secure psci_cpu_off(void) +{ + u32 cpu; + + cpu = psci_get_cpu_id(); + + psci_cpu_off_common(); + psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF); + + /* reset core: wfi is managed by BootRom */ + if (cpu == 0x01) + writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR); + else + writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR); + + /* just waiting reset */ + while (1) + wfi(); +} + +void __secure psci_system_reset(void) +{ + /* System reset */ + writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR); + /* just waiting reset */ + while (1) + wfi(); +} + +void __secure psci_system_off(void) +{ + /* System Off is not managed, waiting user power off + * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF + */ + while (1) + wfi(); +} + +static void __secure secure_udelay(unsigned int delay) +{ + u32 freq = cp15_read_cntfrq() / 1000000; + u64 start, end; + + delay *= freq; + + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); + for (;;) { + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); + if ((end - start) > delay) + break; + } +} + +static int __secure secure_waitbits(u32 reg, u32 mask, u32 val) +{ + u32 freq = cp15_read_cntfrq() / 1000000; + u32 delay = 500 * freq; /* 500 us */ + u64 start, end; + u32 tmp; + + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (start)); + for (;;) { + tmp = readl(reg); + tmp &= mask; + if ((tmp & val) == val) + return 0; + asm volatile("mrrc p15, 0, %Q0, %R0, c14" : "=r" (end)); + if ((end - start) > delay) + return -ETIMEDOUT; + } +} + +static void __secure ddr_sr_mode_ssr(u32 *saved_pwrctl) +{ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1LPEN | RCC_DDRITFCR_DDRC1EN | + RCC_DDRITFCR_DDRC2LPEN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRCAPBLPEN | RCC_DDRITFCR_DDRPHYCAPBLPEN | + RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN | + RCC_DDRITFCR_DDRPHYCEN); + + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_AXIDCGEN | RCC_DDRITFCR_DDRCKMOD_MASK); + + /* Disable HW LP interface of uMCTL2 */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_HWLPCTL, + DDRCTRL_HWLPCTL_HW_LP_EN); + + /* Configure Automatic LP modes of uMCTL2 */ + clrsetbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRTMG, + DDRCTRL_PWRTMG_SELFREF_TO_X32_MASK, + DDRCTRL_PWRTMG_SELFREF_TO_X32_0); + + /* Save PWRCTL register to restart ASR after suspend (if applicable) */ + *saved_pwrctl = readl(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL); + + /* + * Disable Clock disable with LP modes + * (used in RUN mode for LPDDR2 with specific timing). + */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE); + + /* Disable automatic Self-Refresh mode */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_SELFREF_EN); +} + +static void __secure ddr_sr_mode_restore(u32 saved_pwrctl) +{ + saved_pwrctl &= DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE | + DDRCTRL_PWRCTL_SELFREF_EN; + + /* Restore ASR mode in case it was enabled before suspend. */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, saved_pwrctl); +} + +static int __secure ddr_sw_self_refresh_in(void) +{ + int ret; + + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); + + /* Blocks AXI ports from taking anymore transactions */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, + DDRCTRL_PCTRL_N_PORT_EN); + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, + DDRCTRL_PCTRL_N_PORT_EN); + + /* + * Waits unit all AXI ports are idle + * Poll PSTAT.rd_port_busy_n = 0 + * Poll PSTAT.wr_port_busy_n = 0 + */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_PSTAT, + DDRCTRL_PSTAT_RD_PORT_BUSY_0 | + DDRCTRL_PSTAT_RD_PORT_BUSY_1 | + DDRCTRL_PSTAT_WR_PORT_BUSY_0 | + DDRCTRL_PSTAT_WR_PORT_BUSY_1, 0); + if (ret) + goto pstat_failed; + + /* SW Self-Refresh entry */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); + + /* + * Wait operating mode change in self-refresh mode + * with STAT.operating_mode[1:0]==11. + * Ensure transition to self-refresh was due to software + * by checking also that STAT.selfref_type[1:0]=2. + */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, + DDRCTRL_STAT_OPERATING_MODE_MASK | + DDRCTRL_STAT_SELFREF_TYPE_MASK, + DDRCTRL_STAT_OPERATING_MODE_SR | + DDRCTRL_STAT_SELFREF_TYPE_SR); + if (ret) + goto selfref_sw_failed; + + /* IOs powering down (PUBL registers) */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDR); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CKPDD_MASK, + DDRPHYC_ACIOCR_CKPDD_0); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CKPDR_MASK, + DDRPHYC_ACIOCR_CKPDR_0); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, + DDRPHYC_ACIOCR_CSPDD_MASK, + DDRPHYC_ACIOCR_CSPDD_0); + + /* Disable command/address output driver */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, + DDRPHYC_DSGCR_ODTPDD_MASK, + DDRPHYC_DSGCR_ODTPDD_0); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); + + clrsetbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, + DDRPHYC_DSGCR_CKEPDD_MASK, + DDRPHYC_DSGCR_CKEPDD_0); + + /* Disable PZQ cell (PUBL register) */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); + + /* Set latch */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); + + /* Additional delay to avoid early latch */ + secure_udelay(10); + + /* Activate sw retention in PWRCTRL */ + setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Disable all DLLs: GLITCH window */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL output clock */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Deactivate all DDR clocks */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRCAPBEN | RCC_DDRITFCR_DDRPHYCAPBEN); + + return 0; + +selfref_sw_failed: + /* This bit should be cleared to restore DDR in its previous state */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, + DDRCTRL_PWRCTL_SELFREF_SW); + +pstat_failed: + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, + DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, + DDRCTRL_PCTRL_N_PORT_EN); + + return -EINVAL; +}; + +static void __secure ddr_sw_self_refresh_exit(void) +{ + int ret; + + /* Enable all clocks */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, + RCC_DDRITFCR_DDRC1EN | RCC_DDRITFCR_DDRC2EN | + RCC_DDRITFCR_DDRPHYCEN | RCC_DDRITFCR_DDRPHYCAPBEN | + RCC_DDRITFCR_DDRCAPBEN); + + /* Handshake */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + + /* Mask dfi_init_complete_en */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, + DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + + /* Ack */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, + DDRCTRL_SWSTAT_SW_DONE_ACK, + DDRCTRL_SWSTAT_SW_DONE_ACK); + if (ret) + hang(); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + /* Enable all DLLs: GLITCH window */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, + DDRPHYC_ACDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX0DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX1DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX2DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DX3DLLCR, DDRPHYC_DXNDLLCR_DLLDIS); + + /* Additional delay to avoid early DLL clock switch */ + secure_udelay(50); + + /* Switch controller clocks (uMCTL2/PUBL) to DLL ref clock */ + clrbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_GSKPCTRL); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); + + secure_udelay(10); + + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACDLLCR, DDRPHYC_ACDLLCR_DLLSRST); + + /* PHY partial init: (DLL lock and ITM reset) */ + writel(DDRPHYC_PIR_DLLSRST | DDRPHYC_PIR_DLLLOCK | + DDRPHYC_PIR_ITMSRST | DDRPHYC_PIR_INIT, + STM32_DDRPHYC_BASE + DDRPHYC_PIR); + + /* Need to wait at least 10 clock cycles before accessing PGSR */ + secure_udelay(1); + + /* Pool end of init */ + ret = secure_waitbits(STM32_DDRPHYC_BASE + DDRPHYC_PGSR, + DDRPHYC_PGSR_IDONE, DDRPHYC_PGSR_IDONE); + if (ret) + hang(); + + /* Handshake */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + + /* Unmask dfi_init_complete_en to uMCTL2 */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_DFIMISC, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); + + /* Ack */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_SWCTL, DDRCTRL_SWCTL_SW_DONE); + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_SWSTAT, + DDRCTRL_SWSTAT_SW_DONE_ACK, + DDRCTRL_SWSTAT_SW_DONE_ACK); + if (ret) + hang(); + + /* Deactivate sw retention in PWR */ + clrbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRRETEN); + + /* Enable PZQ cell (PUBL register) */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ZQ0CR0, DDRPHYC_ZQ0CRN_ZQPD); + + /* Enable pad drivers */ + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACPDD); + + /* Enable command/address output driver */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_ACOE); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CKPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_ACIOCR, DDRPHYC_ACIOCR_CSPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDD); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DXCCR, DDRPHYC_DXCCR_DXPDR); + + /* Release latch */ + setbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKOE); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_ODTPDD_MASK); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_NL2PD); + + clrbits_le32(STM32_DDRPHYC_BASE + DDRPHYC_DSGCR, DDRPHYC_DSGCR_CKEPDD_MASK); + + /* Remove selfrefresh */ + clrbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PWRCTL, DDRCTRL_PWRCTL_SELFREF_SW); + + /* Wait operating_mode == normal */ + ret = secure_waitbits(STM32_DDRCTRL_BASE + DDRCTRL_STAT, + DDRCTRL_STAT_OPERATING_MODE_MASK, + DDRCTRL_STAT_OPERATING_MODE_NORMAL); + if (ret) + hang(); + + /* AXI ports are no longer blocked from taking transactions */ + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_0, DDRCTRL_PCTRL_N_PORT_EN); + setbits_le32(STM32_DDRCTRL_BASE + DDRCTRL_PCTRL_1, DDRCTRL_PCTRL_N_PORT_EN); + + setbits_le32(STM32_RCC_BASE + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); +} + +void __secure psci_system_suspend(u32 __always_unused function_id, + u32 ep, u32 context_id) +{ + u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; + u32 gicd_addr = stm32mp_get_gicd_base_address(); + bool iwdg1_wake = false; + bool iwdg2_wake = false; + bool other_wake = false; + u32 saved_pwrctl, reg; + u32 gic_enabled[8]; + u32 irqs; + int i; + + /* Cache enable mask of all 256 SPI */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) + gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i); + + /* Disable IO compensation */ + + /* Place current APSRC/ANSRC into RAPSRC/RANSRC */ + reg = readl(STM32_SYSCFG_BASE + SYSCFG_CMPCR); + reg >>= 8; + reg &= 0xff << 16; + reg |= SYSCFG_CMPCR_SW_CTRL; + writel(reg, STM32_SYSCFG_BASE + SYSCFG_CMPCR); + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENCLRR); + + writel(RCC_MP_CIFR_WKUPF, STM32_RCC_BASE + RCC_MP_CIFR); + setbits_le32(STM32_RCC_BASE + RCC_MP_CIER, RCC_MP_CIFR_WKUPF); + + setbits_le32(STM32_PWR_BASE + PWR_MPUCR, + PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS); + + saved_mcudivr = readl(STM32_RCC_BASE + RCC_MCUDIVR); + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); + + psci_v7_flush_dcache_all(); + ddr_sr_mode_ssr(&saved_pwrctl); + ddr_sw_self_refresh_in(); + setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN); + writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); + + /* Ping the IWDG before entering suspend */ + iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */ + + for (;;) { + /* Ping IWDG1 and ACK pretimer IRQ */ + if (iwdg1_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (iwdg2_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + iwdg1_wake = false; + iwdg2_wake = false; + + /* Zzz, enter stop mode */ + asm volatile( + "isb\n" + "dsb\n" + "wfi\n"); + + /* Determine the wake up source */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) { + irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i); + irqs &= gic_enabled[i]; + if (!irqs) + continue; + + /* Test whether IWDG pretimeout triggered the wake up. */ + if (i == 4) { /* SPI Num 128..159 */ + iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */ + irqs &= ~(BIT(22) | BIT(23)); + } + + /* Test whether there is any other wake up trigger. */ + if (irqs) { + other_wake = true; + break; + } + } + + /* Other wake up triggers pending, let OS deal with all of it. */ + if (other_wake) + break; + } + + writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); + ddr_sw_self_refresh_exit(); + ddr_sr_mode_restore(saved_pwrctl); + + writel(saved_mcudivr, STM32_RCC_BASE + RCC_MCUDIVR); + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); + + writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); + clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c new file mode 100644 index 00000000000..846637ab162 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY UCLASS_REGULATOR + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define STM32MP_PWR_CR3 0xc +#define STM32MP_PWR_CR3_USB33DEN BIT(24) +#define STM32MP_PWR_CR3_USB33RDY BIT(26) +#define STM32MP_PWR_CR3_REG18DEN BIT(28) +#define STM32MP_PWR_CR3_REG18RDY BIT(29) +#define STM32MP_PWR_CR3_REG11DEN BIT(30) +#define STM32MP_PWR_CR3_REG11RDY BIT(31) + +struct stm32mp_pwr_reg_info { + u32 enable; + u32 ready; + char *name; +}; + +struct stm32mp_pwr_priv { + fdt_addr_t base; +}; + +static int stm32mp_pwr_write(struct udevice *dev, uint reg, + const uint8_t *buff, int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + u32 val = *(u32 *)buff; + + if (len != 4) + return -EINVAL; + + writel(val, priv->base + STM32MP_PWR_CR3); + + return 0; +} + +static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff, + int len) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + + if (len != 4) + return -EINVAL; + + *(u32 *)buff = readl(priv->base + STM32MP_PWR_CR3); + + return 0; +} + +static int stm32mp_pwr_of_to_plat(struct udevice *dev) +{ + struct stm32mp_pwr_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +static const struct pmic_child_info pwr_children_info[] = { + { .prefix = "reg", .driver = "stm32mp_pwr_regulator"}, + { .prefix = "usb", .driver = "stm32mp_pwr_regulator"}, + { }, +}; + +static int stm32mp_pwr_bind(struct udevice *dev) +{ + int children; + + children = pmic_bind_children(dev, dev_ofnode(dev), pwr_children_info); + if (!children) + dev_dbg(dev, "no child found\n"); + + return 0; +} + +static struct dm_pmic_ops stm32mp_pwr_ops = { + .read = stm32mp_pwr_read, + .write = stm32mp_pwr_write, +}; + +static const struct udevice_id stm32mp_pwr_ids[] = { + { .compatible = "st,stm32mp1,pwr-reg" }, + { } +}; + +U_BOOT_DRIVER(stm32mp_pwr_pmic) = { + .name = "stm32mp_pwr_pmic", + .id = UCLASS_PMIC, + .of_match = stm32mp_pwr_ids, + .bind = stm32mp_pwr_bind, + .ops = &stm32mp_pwr_ops, + .of_to_plat = stm32mp_pwr_of_to_plat, + .priv_auto = sizeof(struct stm32mp_pwr_priv), +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = { + .enable = STM32MP_PWR_CR3_REG11DEN, + .ready = STM32MP_PWR_CR3_REG11RDY, + .name = "reg11" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg18 = { + .enable = STM32MP_PWR_CR3_REG18DEN, + .ready = STM32MP_PWR_CR3_REG18RDY, + .name = "reg18" +}; + +static const struct stm32mp_pwr_reg_info stm32mp_pwr_usb33 = { + .enable = STM32MP_PWR_CR3_USB33DEN, + .ready = STM32MP_PWR_CR3_USB33RDY, + .name = "usb33" +}; + +static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = { + &stm32mp_pwr_reg11, + &stm32mp_pwr_reg18, + &stm32mp_pwr_usb33, + NULL +}; + +static int stm32mp_pwr_regulator_probe(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos; + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + + while (*p) { + int rc; + + rc = dev_read_stringlist_search(dev, "regulator-name", + (*p)->name); + if (rc >= 0) { + dev_dbg(dev, "found regulator %s\n", (*p)->name); + break; + } else if (rc != -ENODATA) { + return rc; + } + p++; + } + if (!*p) { + int i = 0; + const char *s; + + dev_dbg(dev, "regulator "); + while (dev_read_string_index(dev, "regulator-name", + i++, &s) >= 0) + dev_dbg(dev, "%s'%s' ", (i > 1) ? ", " : "", s); + dev_dbg(dev, "%s not supported\n", (i > 2) ? "are" : "is"); + return -EINVAL; + } + + uc_pdata->type = REGULATOR_TYPE_FIXED; + dev_set_priv(dev, (void *)*p); + + return 0; +} + +static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uV) { + dev_dbg(dev, "Invalid uV=%d for: %s\n", uV, uc_pdata->name); + return -EINVAL; + } + + return 0; +} + +static int stm32mp_pwr_regulator_get_value(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (!uc_pdata) + return -ENXIO; + + if (uc_pdata->min_uV != uc_pdata->max_uV) { + dev_dbg(dev, "Invalid constraints for: %s\n", uc_pdata->name); + return -EINVAL; + } + + return uc_pdata->min_uV; +} + +static int stm32mp_pwr_regulator_get_enable(struct udevice *dev) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + dev_dbg(dev, "%s id %s\n", p->name, (reg & p->enable) ? "on" : "off"); + + return (reg & p->enable) != 0; +} + +static int stm32mp_pwr_regulator_set_enable(struct udevice *dev, bool enable) +{ + const struct stm32mp_pwr_reg_info *p = dev_get_priv(dev); + int rc; + u32 reg; + u32 time_start; + + dev_dbg(dev, "Turning %s %s\n", enable ? "on" : "off", p->name); + + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + /* if regulator is already in the wanted state, nothing to do */ + if (!!(reg & p->enable) == enable) + return 0; + + reg &= ~p->enable; + if (enable) + reg |= p->enable; + + rc = pmic_write(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + + if (!enable) + return 0; + + /* waiting ready for enable */ + time_start = get_timer(0); + while (1) { + rc = pmic_read(dev->parent, 0, (uint8_t *)®, sizeof(reg)); + if (rc) + return rc; + if (reg & p->ready) + break; + if (get_timer(time_start) > CONFIG_SYS_HZ) { + dev_dbg(dev, "%s: timeout\n", p->name); + return -ETIMEDOUT; + } + } + return 0; +} + +static const struct dm_regulator_ops stm32mp_pwr_regulator_ops = { + .set_value = stm32mp_pwr_regulator_set_value, + .get_value = stm32mp_pwr_regulator_get_value, + .get_enable = stm32mp_pwr_regulator_get_enable, + .set_enable = stm32mp_pwr_regulator_set_enable, +}; + +U_BOOT_DRIVER(stm32mp_pwr_regulator) = { + .name = "stm32mp_pwr_regulator", + .id = UCLASS_REGULATOR, + .ops = &stm32mp_pwr_regulator_ops, + .probe = stm32mp_pwr_regulator_probe, +}; diff --git a/arch/arm/mach-stm32mp/stm32mp1/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c new file mode 100644 index 00000000000..6c79259b2c8 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/spl.c @@ -0,0 +1,252 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +u32 spl_boot_device(void) +{ + u32 boot_mode; + + boot_mode = get_bootmode(); + + switch (boot_mode) { + case BOOT_FLASH_SD_1: + case BOOT_FLASH_EMMC_1: + return BOOT_DEVICE_MMC1; + case BOOT_FLASH_SD_2: + case BOOT_FLASH_EMMC_2: + return BOOT_DEVICE_MMC2; + case BOOT_SERIAL_UART_1: + case BOOT_SERIAL_UART_2: + case BOOT_SERIAL_UART_3: + case BOOT_SERIAL_UART_4: + case BOOT_SERIAL_UART_5: + case BOOT_SERIAL_UART_6: + case BOOT_SERIAL_UART_7: + case BOOT_SERIAL_UART_8: + return BOOT_DEVICE_UART; + case BOOT_SERIAL_USB_OTG: + return BOOT_DEVICE_DFU; + case BOOT_FLASH_NAND_FMC: + return BOOT_DEVICE_NAND; + case BOOT_FLASH_NOR_QSPI: + return BOOT_DEVICE_SPI; + case BOOT_FLASH_SPINAND_1: + return BOOT_DEVICE_NONE; /* SPINAND not supported in SPL */ + } + + return BOOT_DEVICE_MMC1; +} + +u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +#ifdef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION +int spl_mmc_boot_partition(const u32 boot_device) +{ + switch (boot_device) { + case BOOT_DEVICE_MMC1: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION; + case BOOT_DEVICE_MMC2: + return CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2; + default: + return -EINVAL; + } +} +#endif + +#ifdef CONFIG_SPL_DISPLAY_PRINT +void spl_display_print(void) +{ + DECLARE_GLOBAL_DATA_PTR; + const char *model; + + /* same code than show_board_info() but not compiled for SPL + * see CONFIG_DISPLAY_BOARDINFO & common/board_info.c + */ + model = fdt_getprop(gd->fdt_blob, 0, "model", NULL); + if (model) + log_info("Model: %s\n", model); +} +#endif + +__weak int board_early_init_f(void) +{ + return 0; +} + +uint32_t stm32mp_get_dram_size(void) +{ + struct ram_info ram; + struct udevice *dev; + int ret; + + if (uclass_get_device(UCLASS_RAM, 0, &dev)) + return 0; + + ret = ram_get_info(dev, &ram); + if (ret) + return 0; + + return ram.size; +} + +static int optee_get_reserved_memory(uint32_t *start, uint32_t *size) +{ + fdt_addr_t fdt_mem_size; + fdt_addr_t fdt_start; + ofnode node; + + node = ofnode_path("/reserved-memory/optee"); + if (!ofnode_valid(node)) + return 0; + + fdt_start = ofnode_get_addr_size(node, "reg", &fdt_mem_size); + *start = fdt_start; + *size = fdt_mem_size; + return (fdt_start < 0) ? fdt_start : 0; +} + +#define CFG_SHMEM_SIZE 0x200000 +#define STM32_TZC_NSID_ALL 0xffff +#define STM32_TZC_FILTER_ALL 3 + +void stm32_init_tzc_for_optee(void) +{ + const uint32_t dram_size = stm32mp_get_dram_size(); + const uintptr_t dram_top = STM32_DDR_BASE + (dram_size - 1); + uint32_t optee_base, optee_size, tee_shmem_base; + const uintptr_t tzc = STM32_TZC_BASE; + int ret; + + if (dram_size == 0) + panic("Cannot determine DRAM size from devicetree\n"); + + ret = optee_get_reserved_memory(&optee_base, &optee_size); + if (ret < 0 || optee_size <= CFG_SHMEM_SIZE) + panic("Invalid OPTEE reserved memory in devicetree\n"); + + tee_shmem_base = optee_base + optee_size - CFG_SHMEM_SIZE; + + const struct tzc_region optee_config[] = { + { + .base = STM32_DDR_BASE, + .top = optee_base - 1, + .sec_mode = TZC_ATTR_SEC_NONE, + .nsec_id = STM32_TZC_NSID_ALL, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .base = optee_base, + .top = tee_shmem_base - 1, + .sec_mode = TZC_ATTR_SEC_RW, + .nsec_id = 0, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .base = tee_shmem_base, + .top = dram_top, + .sec_mode = TZC_ATTR_SEC_NONE, + .nsec_id = STM32_TZC_NSID_ALL, + .filters_mask = STM32_TZC_FILTER_ALL, + }, { + .top = 0, + } + }; + + flush_dcache_all(); + + tzc_configure(tzc, optee_config); + tzc_dump_config(tzc); + + dcache_disable(); +} + +void spl_board_prepare_for_optee(void *fdt) +{ + stm32_init_tzc_for_optee(); +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + arch_cpu_init(); + mach_cpu_init(); + + ret = spl_early_init(); + if (ret) { + log_debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + log_debug("Clock init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_RESET, 0, &dev); + if (ret) { + log_debug("Reset init failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &dev); + if (ret) { + log_debug("%s: Cannot find pinctrl device\n", __func__); + hang(); + } + + /* enable console uart printing */ + preloader_console_init(); + + ret = board_early_init_f(); + if (ret) { + log_debug("board_early_init_f() failed: %d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + log_err("DRAM init failed: %d\n", ret); + hang(); + } + + /* + * activate cache on DDR only when DDR is fully initialized + * to avoid speculative access and issue in get_ram_size() + */ + if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + mmu_set_region_dcache_behaviour(STM32_DDR_BASE, + CONFIG_DDR_CACHEABLE_SIZE, + DCACHE_DEFAULT_OPTION); +} + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_linux(void) +{ + dcache_disable(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c new file mode 100644 index 00000000000..845d973ad1b --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2022, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include + +/* SYSCFG register */ +#define SYSCFG_IDC_OFFSET 0x380 +#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_IDC_DEV_ID_SHIFT 0 +#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_IDC_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(11, 0) + +static u32 read_idc(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_IDC_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + int nb_eth = 2; + + switch (get_cpu_type()) { + case CPU_STM32MP131Dxx: + fallthrough; + case CPU_STM32MP131Cxx: + fallthrough; + case CPU_STM32MP131Axx: + nb_eth = 1; + break; + default: + nb_eth = 2; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r; + + /* MPUs Part Numbers */ + switch (get_cpu_type()) { + case CPU_STM32MP135Fxx: + cpu_s = "135F"; + break; + case CPU_STM32MP135Dxx: + cpu_s = "135D"; + break; + case CPU_STM32MP135Cxx: + cpu_s = "135C"; + break; + case CPU_STM32MP135Axx: + cpu_s = "135A"; + break; + case CPU_STM32MP133Fxx: + cpu_s = "133F"; + break; + case CPU_STM32MP133Dxx: + cpu_s = "133D"; + break; + case CPU_STM32MP133Cxx: + cpu_s = "133C"; + break; + case CPU_STM32MP133Axx: + cpu_s = "133A"; + break; + case CPU_STM32MP131Fxx: + cpu_s = "131F"; + break; + case CPU_STM32MP131Dxx: + cpu_s = "131D"; + break; + case CPU_STM32MP131Cxx: + cpu_s = "131C"; + break; + case CPU_STM32MP131Axx: + cpu_s = "131A"; + break; + default: + cpu_s = "????"; + break; + } + + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + case CPU_REV1_1: + cpu_r = "Z"; + break; + case CPU_REV1_2: + cpu_r = "Y"; + break; + default: + cpu_r = "?"; + break; + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c new file mode 100644 index 00000000000..afc56b02eea --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2021, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* RCC register */ +#define RCC_TZCR (STM32_RCC_BASE + 0x00) +#define RCC_BDCR (STM32_RCC_BASE + 0x0140) +#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) +#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) +#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) + +#define RCC_BDCR_VSWRST BIT(31) +#define RCC_BDCR_RTCSRC GENMASK(17, 16) + +#define RCC_DBGCFGR_DBGCKEN BIT(8) + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) +#define DBGMCU_APB4FZ1_IWDG2 BIT(2) + +/* Security register */ +#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) +#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) + +#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) +#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) +#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) + +#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) + +#define PWR_CR1 (STM32_PWR_BASE + 0x00) +#define PWR_MCUCR (STM32_PWR_BASE + 0x14) +#define PWR_CR1_DBP BIT(8) +#define PWR_MCUCR_SBF BIT(6) + +/* GPIOZ registers */ +#define GPIOZ_SECCFGR 0x54004030 + +/* DBGMCU register */ +#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) +#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) +#define DBGMCU_IDC_DEV_ID_SHIFT 0 +#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) +#define DBGMCU_IDC_REV_ID_SHIFT 16 + +/* boot interface from Bootrom + * - boot instance = bit 31:16 + * - boot device = bit 15:0 + */ +#define BOOTROM_PARAM_ADDR 0x2FFC0078 +#define BOOTROM_MODE_MASK GENMASK(15, 0) +#define BOOTROM_MODE_SHIFT 0 +#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) +#define BOOTROM_INSTANCE_SHIFT 16 + +/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(7, 0) + +/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines + * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm + * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm + * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm + * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 27 +#define PKG_MASK GENMASK(2, 0) + +static void security_init(void) +{ + /* Disable the backup domain write protection */ + /* the protection is enable at each reset by hardware */ + /* And must be disable by software */ + setbits_le32(PWR_CR1, PWR_CR1_DBP); + + while (!(readl(PWR_CR1) & PWR_CR1_DBP)) + ; + + /* If RTC clock isn't enable so this is a cold boot then we need + * to reset the backup domain + */ + if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { + setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) + ; + clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); + } + + /* allow non secure access in Write/Read for all peripheral */ + writel(GENMASK(25, 0), ETZPC_DECPROT0); + + /* Open SYSRAM for no secure access */ + writel(0x0, ETZPC_TZMA1_SIZE); + + /* enable TZC1 TZC2 clock */ + writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); + + /* Region 0 set to no access by default */ + /* bit 0 / 16 => nsaid0 read/write Enable + * bit 1 / 17 => nsaid1 read/write Enable + * ... + * bit 15 / 31 => nsaid15 read/write Enable + */ + writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); + /* bit 30 / 31 => Secure Global Enable : write/read */ + /* bit 0 / 1 => Region Enable for filter 0/1 */ + writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); + + /* Enable Filter 0 and 1 */ + setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); + + /* RCC trust zone deactivated */ + writel(0x0, RCC_TZCR); + + /* TAMP: deactivate the internal tamper + * Bit 23 ITAMP8E: monotonic counter overflow + * Bit 20 ITAMP5E: RTC calendar overflow + * Bit 19 ITAMP4E: HSE monitoring + * Bit 18 ITAMP3E: LSE monitoring + * Bit 16 ITAMP1E: RTC power domain supply monitoring + */ + writel(0x0, TAMP_CR1); + + /* GPIOZ: deactivate the security */ + writel(BIT(0), RCC_MP_AHB5ENSETR); + writel(0x0, GPIOZ_SECCFGR); +} + +/* + * Debug init + */ +void dbgmcu_init(void) +{ + /* + * Freeze IWDG2 if Cortex-A7 is in debug mode + * done in TF-A for TRUSTED boot and + * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE + */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); + } +} + +void spl_board_init(void) +{ + struct udevice *dev; + int ret; + + dbgmcu_init(); + + /* force probe of BSEC driver to shadow the upper OTP */ + ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); + if (ret) + log_warning("BSEC probe failed: %d\n", ret); +} + +/* get bootmode from ROM code boot context: saved in TAMP register */ +static void update_bootmode(void) +{ + u32 boot_mode; + u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); + u32 bootrom_device, bootrom_instance; + + /* enable TAMP clock = RTCAPBEN */ + writel(BIT(8), RCC_MP_APB5ENSETR); + + /* read bootrom context */ + bootrom_device = + (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; + bootrom_instance = + (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; + boot_mode = + ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | + ((bootrom_instance << BOOT_INSTANCE_SHIFT) & + BOOT_INSTANCE_MASK); + + /* save the boot mode in TAMP backup register */ + clrsetbits_le32(TAMP_BOOT_CONTEXT, + TAMP_BOOT_MODE_MASK, + boot_mode << TAMP_BOOT_MODE_SHIFT); +} + +/* weak function: STM32MP15x mach init for boot without TFA */ +void stm32mp_cpu_init(void) +{ + if (IS_ENABLED(CONFIG_SPL_BUILD)) { + security_init(); + update_bootmode(); + } + + /* reset copro state in SPL, when used, or in U-Boot */ + if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { + /* Reset Coprocessor state unless it wakes up from Standby power mode */ + if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { + writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); + writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); + } + } +} + +static u32 read_idc(void) +{ + /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ + if (bsec_dbgswenable()) { + setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); + + return readl(DBGMCU_IDC); + } + + return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ +} + +u32 get_cpu_dev(void) +{ + return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +static u32 get_cpu_rpn(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +u32 get_cpu_type(void) +{ + return (get_cpu_dev() << 16) | get_cpu_rpn(); +} + +int get_eth_nb(void) +{ + return 1; +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +static const char * const soc_type[] = { + "????", + "151C", "151A", "151F", "151D", + "153C", "153A", "153F", "153D", + "157C", "157A", "157F", "157D" +}; + +static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"}; + +static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, + unsigned int *rev) +{ + u32 cpu_type = get_cpu_type(); + u32 ct = cpu_type & ~(BIT(7) | BIT(0)); + u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); + + /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ + switch (ct) { + case CPU_STM32MP151Cxx: + *type = cm + 1; + break; + case CPU_STM32MP153Cxx: + *type = cm + 5; + break; + case CPU_STM32MP157Cxx: + *type = cm + 9; + break; + default: + *type = 0; + break; + } + + /* Package */ + *pkg = get_cpu_package(); + if (*pkg > STM32MP15_PKG_AA_LBGA448) + *pkg = STM32MP15_PKG_UNKNOWN; + + /* Revision */ + switch (get_cpu_rev()) { + case CPU_REV1: + *rev = 1; + break; + case CPU_REV2: + *rev = 2; + break; + case CPU_REV2_1: + *rev = 3; + break; + case CPU_REV2_2: + *rev = 4; + break; + default: + *rev = 0; + break; + } +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", + soc_type[type], soc_pkg[pkg], soc_rev[rev]); +} + +static void setup_soc_type_pkg_rev(void) +{ + unsigned int type, pkg, rev; + + get_cpu_string_offsets(&type, &pkg, &rev); + + env_set("soc_type", soc_type[type]); + env_set("soc_pkg", soc_pkg[pkg]); + env_set("soc_rev", soc_rev[rev]); +} + +/* weak function called in arch_misc_init */ +void stm32mp_misc_init(void) +{ + setup_soc_type_pkg_rev(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp1/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c new file mode 100644 index 00000000000..cdc4a40edaf --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Simple API for configuring TrustZone memory restrictions for TZC400 + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include + +#define TZC_TIMEOUT_US 100 + +#define TZC_BUILD_CONFIG 0x00 +#define TZC_ACTION 0x04 +#define TZC_ACTION_NONE 0 +#define TZC_ACTION_ERR 1 +#define TZC_ACTION_INT 2 +#define TZC_ACTION_INT_ERR 3 +#define TZC_GATE_KEEPER 0x08 + +#define TZC_REGION0_OFFSET 0x100 +#define TZC_REGION_CFG_SIZE 0x20 +#define TZC_REGION1_OFFSET 0x120 +#define TZC_REGION_BASE 0x00 +#define TZC_REGION_TOP 0x08 +#define TZC_REGION_ATTRIBUTE 0x10 +#define TZC_REGION_ACCESS 0x14 + +static uint32_t tzc_read(uintptr_t tzc, size_t reg) +{ + return readl(tzc + reg); +} + +static void tzc_write(uintptr_t tzc, size_t reg, uint32_t val) +{ + writel(val, tzc + reg); +} + +static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg) +{ + uint16_t active_filters = 0; + + for ( ; cfg->top != 0; cfg++) + active_filters |= cfg->filters_mask; + + return active_filters; +} + +int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg) +{ + uintptr_t region = tzc + TZC_REGION1_OFFSET; + uint32_t nsid, attr_reg, active_filters; + int ret; + + active_filters = tzc_config_get_active_filters(cfg); + if (active_filters == 0) + return -EINVAL; + + ret = tzc_disable_filters(tzc, active_filters); + if (ret < 0) + return ret; + + for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) { + attr_reg = (cfg->sec_mode & 0x03) << 30; + attr_reg |= (cfg->filters_mask & 0x03) << 0; + nsid = cfg->nsec_id & 0xffff; + nsid |= nsid << 16; + + tzc_write(region, TZC_REGION_BASE, cfg->base); + tzc_write(region, TZC_REGION_TOP, cfg->top); + tzc_write(region, TZC_REGION_ACCESS, nsid); + tzc_write(region, TZC_REGION_ATTRIBUTE, attr_reg); + } + + tzc_write(tzc, TZC_ACTION, TZC_ACTION_ERR); + return tzc_enable_filters(tzc, active_filters); +} + +int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask) +{ + uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); + uint32_t filter_status = filters_mask << 16; + + gate &= ~filters_mask; + tzc_write(tzc, TZC_GATE_KEEPER, gate); + + return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, + (gate & filter_status) == 0, TZC_TIMEOUT_US); +} + +int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask) +{ + uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); + uint32_t filter_status = filters_mask << 16; + + gate |= filters_mask; + tzc_write(tzc, TZC_GATE_KEEPER, gate); + + return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, + (gate & filter_status) == filter_status, + TZC_TIMEOUT_US); +} + +static const char *sec_access_str_from_attr(uint32_t attr) +{ + const char *const sec_mode[] = { "none", "RO ", "WO ", "RW " }; + + return sec_mode[(attr >> 30) & 0x03]; +} + +void tzc_dump_config(uintptr_t tzc) +{ + uint32_t build_config, base, top, attr, nsaid; + int num_regions, i; + uintptr_t region; + + build_config = tzc_read(tzc, TZC_BUILD_CONFIG); + num_regions = ((build_config >> 0) & 0x1f) + 1; + + for (i = 0; i < num_regions; i++) { + region = tzc + TZC_REGION0_OFFSET + i * TZC_REGION_CFG_SIZE; + + base = tzc_read(region, TZC_REGION_BASE); + top = tzc_read(region, TZC_REGION_TOP); + attr = tzc_read(region, TZC_REGION_ATTRIBUTE); + nsaid = tzc_read(region, TZC_REGION_ACCESS); + + if (attr == 0 && nsaid == 0) + continue; + + log_info("TZC region %u: %08x->%08x - filters 0x%x\n", + i, base, top, (attr >> 0) & 0xf); + log_info("\t Secure access %s NSAID %08x\n", + sec_access_str_from_attr(attr), nsaid); + } +} diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp13x.c deleted file mode 100644 index 845d973ad1b..00000000000 --- a/arch/arm/mach-stm32mp/stm32mp13x.c +++ /dev/null @@ -1,138 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause -/* - * Copyright (C) 2022, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include -#include -#include -#include -#include - -/* SYSCFG register */ -#define SYSCFG_IDC_OFFSET 0x380 -#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0) -#define SYSCFG_IDC_DEV_ID_SHIFT 0 -#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16) -#define SYSCFG_IDC_REV_ID_SHIFT 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 11 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(11, 0) - -static u32 read_idc(void) -{ - void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); - - return readl(syscfg + SYSCFG_IDC_OFFSET); -} - -u32 get_cpu_dev(void) -{ - return (read_idc() & SYSCFG_IDC_DEV_ID_MASK) >> SYSCFG_IDC_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return (read_idc() & SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT; -} - -/* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -u32 get_cpu_type(void) -{ - return (get_cpu_dev() << 16) | get_cpu_rpn(); -} - -int get_eth_nb(void) -{ - int nb_eth = 2; - - switch (get_cpu_type()) { - case CPU_STM32MP131Dxx: - fallthrough; - case CPU_STM32MP131Cxx: - fallthrough; - case CPU_STM32MP131Axx: - nb_eth = 1; - break; - default: - nb_eth = 2; - break; - } - - return nb_eth; -} - -void get_soc_name(char name[SOC_NAME_SIZE]) -{ - char *cpu_s, *cpu_r; - - /* MPUs Part Numbers */ - switch (get_cpu_type()) { - case CPU_STM32MP135Fxx: - cpu_s = "135F"; - break; - case CPU_STM32MP135Dxx: - cpu_s = "135D"; - break; - case CPU_STM32MP135Cxx: - cpu_s = "135C"; - break; - case CPU_STM32MP135Axx: - cpu_s = "135A"; - break; - case CPU_STM32MP133Fxx: - cpu_s = "133F"; - break; - case CPU_STM32MP133Dxx: - cpu_s = "133D"; - break; - case CPU_STM32MP133Cxx: - cpu_s = "133C"; - break; - case CPU_STM32MP133Axx: - cpu_s = "133A"; - break; - case CPU_STM32MP131Fxx: - cpu_s = "131F"; - break; - case CPU_STM32MP131Dxx: - cpu_s = "131D"; - break; - case CPU_STM32MP131Cxx: - cpu_s = "131C"; - break; - case CPU_STM32MP131Axx: - cpu_s = "131A"; - break; - default: - cpu_s = "????"; - break; - } - - /* REVISION */ - switch (get_cpu_rev()) { - case CPU_REV1: - cpu_r = "A"; - break; - case CPU_REV1_1: - cpu_r = "Z"; - break; - case CPU_REV1_2: - cpu_r = "Y"; - break; - default: - cpu_r = "?"; - break; - } - - snprintf(name, SOC_NAME_SIZE, "STM32MP%s Rev.%s", cpu_s, cpu_r); -} diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c deleted file mode 100644 index afc56b02eea..00000000000 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ /dev/null @@ -1,344 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause -/* - * Copyright (C) 2021, STMicroelectronics - All Rights Reserved - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -/* RCC register */ -#define RCC_TZCR (STM32_RCC_BASE + 0x00) -#define RCC_BDCR (STM32_RCC_BASE + 0x0140) -#define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208) -#define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210) -#define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C) - -#define RCC_BDCR_VSWRST BIT(31) -#define RCC_BDCR_RTCSRC GENMASK(17, 16) - -#define RCC_DBGCFGR_DBGCKEN BIT(8) - -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C) -#define DBGMCU_APB4FZ1_IWDG2 BIT(2) - -/* Security register */ -#define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04) -#define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10) - -#define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008) -#define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110) -#define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114) - -#define TAMP_CR1 (STM32_TAMP_BASE + 0x00) - -#define PWR_CR1 (STM32_PWR_BASE + 0x00) -#define PWR_MCUCR (STM32_PWR_BASE + 0x14) -#define PWR_CR1_DBP BIT(8) -#define PWR_MCUCR_SBF BIT(6) - -/* GPIOZ registers */ -#define GPIOZ_SECCFGR 0x54004030 - -/* DBGMCU register */ -#define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00) -#define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0) -#define DBGMCU_IDC_DEV_ID_SHIFT 0 -#define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16) -#define DBGMCU_IDC_REV_ID_SHIFT 16 - -/* boot interface from Bootrom - * - boot instance = bit 31:16 - * - boot device = bit 15:0 - */ -#define BOOTROM_PARAM_ADDR 0x2FFC0078 -#define BOOTROM_MODE_MASK GENMASK(15, 0) -#define BOOTROM_MODE_SHIFT 0 -#define BOOTROM_INSTANCE_MASK GENMASK(31, 16) -#define BOOTROM_INSTANCE_SHIFT 16 - -/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */ -#define RPN_SHIFT 0 -#define RPN_MASK GENMASK(7, 0) - -/* Package = bit 27:29 of OTP16 => STM32MP15_PKG defines - * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm - * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm - * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm - * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm - * - others: Reserved - */ -#define PKG_SHIFT 27 -#define PKG_MASK GENMASK(2, 0) - -static void security_init(void) -{ - /* Disable the backup domain write protection */ - /* the protection is enable at each reset by hardware */ - /* And must be disable by software */ - setbits_le32(PWR_CR1, PWR_CR1_DBP); - - while (!(readl(PWR_CR1) & PWR_CR1_DBP)) - ; - - /* If RTC clock isn't enable so this is a cold boot then we need - * to reset the backup domain - */ - if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) { - setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST)) - ; - clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST); - } - - /* allow non secure access in Write/Read for all peripheral */ - writel(GENMASK(25, 0), ETZPC_DECPROT0); - - /* Open SYSRAM for no secure access */ - writel(0x0, ETZPC_TZMA1_SIZE); - - /* enable TZC1 TZC2 clock */ - writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR); - - /* Region 0 set to no access by default */ - /* bit 0 / 16 => nsaid0 read/write Enable - * bit 1 / 17 => nsaid1 read/write Enable - * ... - * bit 15 / 31 => nsaid15 read/write Enable - */ - writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0); - /* bit 30 / 31 => Secure Global Enable : write/read */ - /* bit 0 / 1 => Region Enable for filter 0/1 */ - writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0); - - /* Enable Filter 0 and 1 */ - setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1)); - - /* RCC trust zone deactivated */ - writel(0x0, RCC_TZCR); - - /* TAMP: deactivate the internal tamper - * Bit 23 ITAMP8E: monotonic counter overflow - * Bit 20 ITAMP5E: RTC calendar overflow - * Bit 19 ITAMP4E: HSE monitoring - * Bit 18 ITAMP3E: LSE monitoring - * Bit 16 ITAMP1E: RTC power domain supply monitoring - */ - writel(0x0, TAMP_CR1); - - /* GPIOZ: deactivate the security */ - writel(BIT(0), RCC_MP_AHB5ENSETR); - writel(0x0, GPIOZ_SECCFGR); -} - -/* - * Debug init - */ -void dbgmcu_init(void) -{ - /* - * Freeze IWDG2 if Cortex-A7 is in debug mode - * done in TF-A for TRUSTED boot and - * DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE - */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2); - } -} - -void spl_board_init(void) -{ - struct udevice *dev; - int ret; - - dbgmcu_init(); - - /* force probe of BSEC driver to shadow the upper OTP */ - ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(stm32mp_bsec), &dev); - if (ret) - log_warning("BSEC probe failed: %d\n", ret); -} - -/* get bootmode from ROM code boot context: saved in TAMP register */ -static void update_bootmode(void) -{ - u32 boot_mode; - u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR); - u32 bootrom_device, bootrom_instance; - - /* enable TAMP clock = RTCAPBEN */ - writel(BIT(8), RCC_MP_APB5ENSETR); - - /* read bootrom context */ - bootrom_device = - (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT; - bootrom_instance = - (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT; - boot_mode = - ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) | - ((bootrom_instance << BOOT_INSTANCE_SHIFT) & - BOOT_INSTANCE_MASK); - - /* save the boot mode in TAMP backup register */ - clrsetbits_le32(TAMP_BOOT_CONTEXT, - TAMP_BOOT_MODE_MASK, - boot_mode << TAMP_BOOT_MODE_SHIFT); -} - -/* weak function: STM32MP15x mach init for boot without TFA */ -void stm32mp_cpu_init(void) -{ - if (IS_ENABLED(CONFIG_SPL_BUILD)) { - security_init(); - update_bootmode(); - } - - /* reset copro state in SPL, when used, or in U-Boot */ - if (!IS_ENABLED(CONFIG_SPL) || IS_ENABLED(CONFIG_SPL_BUILD)) { - /* Reset Coprocessor state unless it wakes up from Standby power mode */ - if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) { - writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE); - writel(0, TAMP_COPRO_RSC_TBL_ADDRESS); - } - } -} - -static u32 read_idc(void) -{ - /* DBGMCU access is controlled by BSEC_DENABLE.DBGSWENABLE */ - if (bsec_dbgswenable()) { - setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN); - - return readl(DBGMCU_IDC); - } - - return CPU_DEV_STM32MP15; /* STM32MP15x and unknown revision */ -} - -u32 get_cpu_dev(void) -{ - return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT; -} - -u32 get_cpu_rev(void) -{ - return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT; -} - -/* Get Device Part Number (RPN) from OTP */ -static u32 get_cpu_rpn(void) -{ - return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); -} - -u32 get_cpu_type(void) -{ - return (get_cpu_dev() << 16) | get_cpu_rpn(); -} - -int get_eth_nb(void) -{ - return 1; -} - -/* Get Package options from OTP */ -u32 get_cpu_package(void) -{ - return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); -} - -static const char * const soc_type[] = { - "????", - "151C", "151A", "151F", "151D", - "153C", "153A", "153F", "153D", - "157C", "157A", "157F", "157D" -}; - -static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; -static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"}; - -static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, - unsigned int *rev) -{ - u32 cpu_type = get_cpu_type(); - u32 ct = cpu_type & ~(BIT(7) | BIT(0)); - u32 cm = ((cpu_type & BIT(7)) >> 6) | (cpu_type & BIT(0)); - - /* Bits 0 and 7 are the ACDF, 00:C 01:A 10:F 11:D */ - switch (ct) { - case CPU_STM32MP151Cxx: - *type = cm + 1; - break; - case CPU_STM32MP153Cxx: - *type = cm + 5; - break; - case CPU_STM32MP157Cxx: - *type = cm + 9; - break; - default: - *type = 0; - break; - } - - /* Package */ - *pkg = get_cpu_package(); - if (*pkg > STM32MP15_PKG_AA_LBGA448) - *pkg = STM32MP15_PKG_UNKNOWN; - - /* Revision */ - switch (get_cpu_rev()) { - case CPU_REV1: - *rev = 1; - break; - case CPU_REV2: - *rev = 2; - break; - case CPU_REV2_1: - *rev = 3; - break; - case CPU_REV2_2: - *rev = 4; - break; - default: - *rev = 0; - break; - } -} - -void get_soc_name(char name[SOC_NAME_SIZE]) -{ - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", - soc_type[type], soc_pkg[pkg], soc_rev[rev]); -} - -static void setup_soc_type_pkg_rev(void) -{ - unsigned int type, pkg, rev; - - get_cpu_string_offsets(&type, &pkg, &rev); - - env_set("soc_type", soc_type[type]); - env_set("soc_pkg", soc_pkg[pkg]); - env_set("soc_rev", soc_rev[rev]); -} - -/* weak function called in arch_misc_init */ -void stm32mp_misc_init(void) -{ - setup_soc_type_pkg_rev(); -} diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile new file mode 100644 index 00000000000..b579ce5a800 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o +obj-y += arm64-mmu.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c new file mode 100644 index 00000000000..a203eebdc59 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include +#include +#include + +#define MP2_MEM_MAP_MAX 10 + +#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) +#error "invalid CONFIG_TEXT_BASE value" +#endif + +struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = stm32mp2_mem_map; diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c new file mode 100644 index 00000000000..5bfeab17ab7 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ +#define EARLY_TLB_SIZE 0xA000 +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + icache_enable(); + early_enable_caches(); + + return 0; +} + +void enable_caches(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); +} + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} + +/* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static uintptr_t nt_fw_dtb __section(".data"); + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +/* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + nt_fw_dtb = r2; + + save_boot_params_ret(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c new file mode 100644 index 00000000000..ee570863bb7 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c new file mode 100644 index 00000000000..7d2dab2201d --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include +#include +#include + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 +#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a0e8e1dfdc5..a2e351d74a7 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -10,8 +10,8 @@ #include static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp157-syscfg", - .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG}, { } }; diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/tzc400.c deleted file mode 100644 index cdc4a40edaf..00000000000 --- a/arch/arm/mach-stm32mp/tzc400.c +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Simple API for configuring TrustZone memory restrictions for TZC400 - */ - -#define LOG_CATEGORY LOGC_ARCH - -#include -#include - -#define TZC_TIMEOUT_US 100 - -#define TZC_BUILD_CONFIG 0x00 -#define TZC_ACTION 0x04 -#define TZC_ACTION_NONE 0 -#define TZC_ACTION_ERR 1 -#define TZC_ACTION_INT 2 -#define TZC_ACTION_INT_ERR 3 -#define TZC_GATE_KEEPER 0x08 - -#define TZC_REGION0_OFFSET 0x100 -#define TZC_REGION_CFG_SIZE 0x20 -#define TZC_REGION1_OFFSET 0x120 -#define TZC_REGION_BASE 0x00 -#define TZC_REGION_TOP 0x08 -#define TZC_REGION_ATTRIBUTE 0x10 -#define TZC_REGION_ACCESS 0x14 - -static uint32_t tzc_read(uintptr_t tzc, size_t reg) -{ - return readl(tzc + reg); -} - -static void tzc_write(uintptr_t tzc, size_t reg, uint32_t val) -{ - writel(val, tzc + reg); -} - -static uint16_t tzc_config_get_active_filters(const struct tzc_region *cfg) -{ - uint16_t active_filters = 0; - - for ( ; cfg->top != 0; cfg++) - active_filters |= cfg->filters_mask; - - return active_filters; -} - -int tzc_configure(uintptr_t tzc, const struct tzc_region *cfg) -{ - uintptr_t region = tzc + TZC_REGION1_OFFSET; - uint32_t nsid, attr_reg, active_filters; - int ret; - - active_filters = tzc_config_get_active_filters(cfg); - if (active_filters == 0) - return -EINVAL; - - ret = tzc_disable_filters(tzc, active_filters); - if (ret < 0) - return ret; - - for ( ; cfg->top != 0; cfg++, region += TZC_REGION_CFG_SIZE) { - attr_reg = (cfg->sec_mode & 0x03) << 30; - attr_reg |= (cfg->filters_mask & 0x03) << 0; - nsid = cfg->nsec_id & 0xffff; - nsid |= nsid << 16; - - tzc_write(region, TZC_REGION_BASE, cfg->base); - tzc_write(region, TZC_REGION_TOP, cfg->top); - tzc_write(region, TZC_REGION_ACCESS, nsid); - tzc_write(region, TZC_REGION_ATTRIBUTE, attr_reg); - } - - tzc_write(tzc, TZC_ACTION, TZC_ACTION_ERR); - return tzc_enable_filters(tzc, active_filters); -} - -int tzc_disable_filters(uintptr_t tzc, uint16_t filters_mask) -{ - uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); - uint32_t filter_status = filters_mask << 16; - - gate &= ~filters_mask; - tzc_write(tzc, TZC_GATE_KEEPER, gate); - - return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, - (gate & filter_status) == 0, TZC_TIMEOUT_US); -} - -int tzc_enable_filters(uintptr_t tzc, uint16_t filters_mask) -{ - uint32_t gate = tzc_read(tzc, TZC_GATE_KEEPER); - uint32_t filter_status = filters_mask << 16; - - gate |= filters_mask; - tzc_write(tzc, TZC_GATE_KEEPER, gate); - - return readl_poll_timeout(tzc + TZC_GATE_KEEPER, gate, - (gate & filter_status) == filter_status, - TZC_TIMEOUT_US); -} - -static const char *sec_access_str_from_attr(uint32_t attr) -{ - const char *const sec_mode[] = { "none", "RO ", "WO ", "RW " }; - - return sec_mode[(attr >> 30) & 0x03]; -} - -void tzc_dump_config(uintptr_t tzc) -{ - uint32_t build_config, base, top, attr, nsaid; - int num_regions, i; - uintptr_t region; - - build_config = tzc_read(tzc, TZC_BUILD_CONFIG); - num_regions = ((build_config >> 0) & 0x1f) + 1; - - for (i = 0; i < num_regions; i++) { - region = tzc + TZC_REGION0_OFFSET + i * TZC_REGION_CFG_SIZE; - - base = tzc_read(region, TZC_REGION_BASE); - top = tzc_read(region, TZC_REGION_TOP); - attr = tzc_read(region, TZC_REGION_ATTRIBUTE); - nsaid = tzc_read(region, TZC_REGION_ACCESS); - - if (attr == 0 && nsaid == 0) - continue; - - log_info("TZC region %u: %08x->%08x - filters 0x%x\n", - i, base, top, (attr >> 0) & 0xf); - log_info("\t Secure access %s NSAID %08x\n", - sec_access_str_from_attr(attr), nsaid); - } -} diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig new file mode 100644 index 00000000000..89039f068a2 --- /dev/null +++ b/board/st/stm32mp2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_ST_STM32MP25X + +config SYS_BOARD + default "stm32mp2" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp25_common" + +source "board/st/common/Kconfig" +endif diff --git a/board/st/stm32mp2/MAINTAINERS b/board/st/stm32mp2/MAINTAINERS new file mode 100644 index 00000000000..e6bea910f92 --- /dev/null +++ b/board/st/stm32mp2/MAINTAINERS @@ -0,0 +1,9 @@ +STM32MP2 BOARD +M: Patrice Chotard +M: Patrick Delaunay +L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +S: Maintained +F: arch/arm/dts/stm32mp25* +F: board/st/stm32mp2/ +F: configs/stm32mp25_defconfig +F: include/configs/stm32mp25_common.h diff --git a/board/st/stm32mp2/Makefile b/board/st/stm32mp2/Makefile new file mode 100644 index 00000000000..50352fb71b4 --- /dev/null +++ b/board/st/stm32mp2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += stm32mp2.o diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c new file mode 100644 index 00000000000..132c511ce96 --- /dev/null +++ b/board/st/stm32mp2/stm32mp2.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_BOARD + +#include +#include +#include +#include +#include +#include + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* board dependent setup after realloc */ +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + const void *fdt_compat; + int fdt_compat_len; + char dtb_name[256]; + int buf_len; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) { + env_set("board_name", fdt_compat); + } else { + env_set("board_name", fdt_compat + 3); + + buf_len = sizeof(dtb_name); + strlcpy(dtb_name, fdt_compat + 3, buf_len); + buf_len -= strlen(fdt_compat + 3); + strlcat(dtb_name, ".dtb", buf_len); + env_set("fdtfile", dtb_name); + } + } + } + + return 0; +} diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig new file mode 100644 index 00000000000..8423943f091 --- /dev/null +++ b/configs/stm32mp25_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x400000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1" +CONFIG_STM32MP25X=y +CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_TARGET_ST_STM32MP25X=y +CONFIG_SYS_LOAD_ADDR=0x84000000 +CONFIG_SYS_MEMTEST_START=0x84000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_FIT=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_BOOTDELAY=1 +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_NET is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +# CONFIG_MMC is not set +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +# CONFIG_STM32MP1_DDR is not set +CONFIG_DM_RNG=y +CONFIG_SERIAL_RX_BUFFER=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_WDT_ARM_SMC=y +CONFIG_ERRNO_STR=y +# CONFIG_LMB_USE_MAX_REGIONS is not set +CONFIG_LMB_MEMORY_REGIONS=2 +CONFIG_LMB_RESERVED_REGIONS=32 diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h new file mode 100644 index 00000000000..ec980eea856 --- /dev/null +++ b/include/configs/stm32mp25_common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP25x CPU + */ + +#ifndef __CONFIG_STM32MP25_COMMMON_H +#define __CONFIG_STM32MP25_COMMMON_H +#include +#include + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +#endif /* __CONFIG_STM32MP25_COMMMON_H */ -- cgit v1.3.1 From 601b8901e058e524a57c7590020dc68193c2f9aa Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:41 -0400 Subject: nand: Calculate SYS_NAND_BLOCK_PAGES (neé SYS_NAND_PAGE_COUNT) automatically MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Contrary to what the help message says, this is the number of pages per block. Calculate it automatically based on SYS_NAND_BLOCK_SIZE and SYS_NAND_PAGE_SIZE. To better reflect its semantics, rename it to SYS_NAND_BLOCK_PAGES. Signed-off-by: Sean Anderson --- README | 9 ++++----- configs/am335x_baltos_defconfig | 1 - configs/am335x_evm_defconfig | 1 - configs/am335x_guardian_defconfig | 1 - configs/am335x_igep003x_defconfig | 1 - configs/am3517_evm_defconfig | 1 - configs/am43xx_evm_defconfig | 1 - configs/am43xx_evm_rtconly_defconfig | 1 - configs/am43xx_evm_usbhost_boot_defconfig | 1 - configs/am43xx_hs_evm_defconfig | 1 - configs/axm_defconfig | 1 - configs/chiliboard_defconfig | 1 - configs/corvus_defconfig | 1 - configs/da850evm_nand_defconfig | 1 - configs/devkit3250_defconfig | 1 - configs/devkit8000_defconfig | 1 - configs/dra7xx_evm_defconfig | 1 - configs/draco_defconfig | 1 - configs/etamin_defconfig | 1 - configs/gardena-smart-gateway-at91sam_defconfig | 1 - configs/igep00x0_defconfig | 1 - configs/m53menlo_defconfig | 1 - configs/omap35_logic_defconfig | 1 - configs/omap35_logic_somlv_defconfig | 1 - configs/omap3_beagle_defconfig | 1 - configs/omap3_evm_defconfig | 1 - configs/omap3_logic_defconfig | 1 - configs/omap3_logic_somlv_defconfig | 1 - configs/omapl138_lcdk_defconfig | 1 - configs/phycore-am335x-r2-regor_defconfig | 1 - configs/phycore-am335x-r2-wega_defconfig | 1 - configs/pxm2_defconfig | 1 - configs/rastaban_defconfig | 1 - configs/rut_defconfig | 1 - configs/sama5d3_xplained_nandflash_defconfig | 1 - configs/sama5d3xek_nandflash_defconfig | 1 - configs/sama5d4_xplained_nandflash_defconfig | 1 - configs/sama5d4ek_nandflash_defconfig | 1 - configs/smartweb_defconfig | 1 - configs/taurus_defconfig | 1 - configs/thuban_defconfig | 1 - drivers/mtd/nand/raw/Kconfig | 8 -------- drivers/mtd/nand/raw/am335x_spl_bch.c | 3 ++- drivers/mtd/nand/raw/atmel_nand.c | 5 +++-- drivers/mtd/nand/raw/mxc_nand_spl.c | 5 +++-- drivers/mtd/nand/raw/nand_spl_loaders.c | 2 +- drivers/mtd/nand/raw/nand_spl_simple.c | 5 +++-- drivers/mtd/nand/raw/omap_gpmc.c | 3 ++- include/system-constants.h | 4 ++++ 49 files changed, 22 insertions(+), 62 deletions(-) (limited to 'include') diff --git a/README b/README index 60c6b8a19db..00d422737fb 100644 --- a/README +++ b/README @@ -1191,11 +1191,10 @@ The following options need to be configured: Support for a lightweight UBI (fastmap) scanner and loader - CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_COUNT, - CONFIG_SYS_NAND_PAGE_SIZE, CONFIG_SYS_NAND_OOBSIZE, - CONFIG_SYS_NAND_BLOCK_SIZE, CONFIG_SYS_NAND_BAD_BLOCK_POS, - CFG_SYS_NAND_ECCPOS, CFG_SYS_NAND_ECCSIZE, - CFG_SYS_NAND_ECCBYTES + CONFIG_SYS_NAND_5_ADDR_CYCLE, CONFIG_SYS_NAND_PAGE_SIZE, + CONFIG_SYS_NAND_OOBSIZE, CONFIG_SYS_NAND_BLOCK_SIZE, + CONFIG_SYS_NAND_BAD_BLOCK_POS, CFG_SYS_NAND_ECCPOS, + CFG_SYS_NAND_ECCSIZE, CFG_SYS_NAND_ECCBYTES Defines the size and behavior of the NAND that SPL uses to read U-Boot diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 16993ef5386..3891e48e9c7 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -67,7 +67,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index f048e60f7f3..73f221d55bc 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -84,7 +84,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index 01d848ceede..5369e46bc1b 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0x100 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 4dd6366ef67..4c5c82f9bdd 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -85,7 +85,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_MTD_UBI_FASTMAP=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 0a83ac9378c..111929fb912 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -75,7 +75,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 6571afd345e..5f2356bcd32 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -72,7 +72,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index e84aed4d54d..30681e7eeb6 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -62,7 +62,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 0cae3242b04..6c4cc99e5ff 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -75,7 +75,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 370ee967258..49ecb4c9e66 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -68,7 +68,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/axm_defconfig b/configs/axm_defconfig index f9c02144c4a..e1a01b24b88 100644 --- a/configs/axm_defconfig +++ b/configs/axm_defconfig @@ -86,7 +86,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/chiliboard_defconfig b/configs/chiliboard_defconfig index 06642d282d1..0cd649d643a 100644 --- a/configs/chiliboard_defconfig +++ b/configs/chiliboard_defconfig @@ -63,7 +63,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/corvus_defconfig b/configs/corvus_defconfig index ecf61f0d1e6..5eaa6dbb5fc 100644 --- a/configs/corvus_defconfig +++ b/configs/corvus_defconfig @@ -81,7 +81,6 @@ CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 5f6f5d788d0..62b8edde248 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -88,7 +88,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index ec4031da51d..569b156c997 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -73,7 +73,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_LPC32XX_SLC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 # CONFIG_SYS_NAND_5_ADDR_CYCLE is not set diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index ef16da176a9..a7f82442eb0 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -77,7 +77,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 19ca89fa867..c3a3ec2cd42 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -104,7 +104,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/draco_defconfig b/configs/draco_defconfig index ee19920a703..2a82087ab31 100644 --- a/configs/draco_defconfig +++ b/configs/draco_defconfig @@ -100,7 +100,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index c0ce7a33569..4ac0abc56b0 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -104,7 +104,6 @@ CONFIG_SYS_MAX_NAND_DEVICE=3 CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x80 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 439fcc05753..0fb92ff1638 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_NAND_ATMEL=y CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 993bbe29c6b..3b1af07f057 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -78,7 +78,6 @@ CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/m53menlo_defconfig b/configs/m53menlo_defconfig index ef9e15d1520..e1ddc0af5db 100644 --- a/configs/m53menlo_defconfig +++ b/configs/m53menlo_defconfig @@ -90,7 +90,6 @@ CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_MXC=y CONFIG_MXC_NAND_HWECC=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 539b0cfa4f7..3a656072534 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -74,7 +74,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index f14ce3d23db..868e89114b7 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -83,7 +83,6 @@ CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index cabd3659385..7f0b927528d 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -83,7 +83,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_HAM1_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 33ff39ff548..3434783d45b 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -74,7 +74,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 7d3d602c9d9..78bfbbd1a22 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -73,7 +73,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 0141a425e07..aefd8861db3 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -84,7 +84,6 @@ CONFIG_SYS_MAX_FLASH_SECT=256 CONFIG_MTD_RAW_NAND=y CONFIG_NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 47feff21bd4..63554d56016 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -84,7 +84,6 @@ CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_BUSWIDTH_16BIT=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 4bdf8822181..85d53d06357 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -76,7 +76,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 7644fbec273..60607548a25 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -76,7 +76,6 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/pxm2_defconfig b/configs/pxm2_defconfig index 2ea007d0de5..e1d1066815b 100644 --- a/configs/pxm2_defconfig +++ b/configs/pxm2_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/rastaban_defconfig b/configs/rastaban_defconfig index 9f538a2f83d..21495341e26 100644 --- a/configs/rastaban_defconfig +++ b/configs/rastaban_defconfig @@ -100,7 +100,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/rut_defconfig b/configs/rut_defconfig index ccf25667b50..248073be1f2 100644 --- a/configs/rut_defconfig +++ b/configs/rut_defconfig @@ -99,7 +99,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index a1b6122f8eb..a0802f9c5fe 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -86,7 +86,6 @@ CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 6278a6c68a7..d96bb91e65d 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -90,7 +90,6 @@ CONFIG_PMECC_CAP=4 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index d12f749d7f4..68101a12fc2 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -84,7 +84,6 @@ CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 27bfcdf0084..b8062db775d 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -81,7 +81,6 @@ CONFIG_PMECC_CAP=8 CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER=y CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x1000 CONFIG_SYS_NAND_OOBSIZE=0xe0 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/smartweb_defconfig b/configs/smartweb_defconfig index 10cbccb69b0..80d2c0f1cc1 100644 --- a/configs/smartweb_defconfig +++ b/configs/smartweb_defconfig @@ -84,7 +84,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/taurus_defconfig b/configs/taurus_defconfig index cc5755178b7..9be30c8d8a4 100644 --- a/configs/taurus_defconfig +++ b/configs/taurus_defconfig @@ -94,7 +94,6 @@ CONFIG_MTD=y # CONFIG_SYS_NAND_USE_FLASH_BBT is not set CONFIG_NAND_ATMEL=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/configs/thuban_defconfig b/configs/thuban_defconfig index 116700e0df0..1134624f9d2 100644 --- a/configs/thuban_defconfig +++ b/configs/thuban_defconfig @@ -100,7 +100,6 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 CONFIG_SYS_NAND_OOBSIZE=0x40 CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index a13e6f59cbd..6e9351f8380 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -659,14 +659,6 @@ config SYS_NAND_ONFI_DETECTION And fetching device parameters flashed on device, by parsing ONFI parameter page. -config SYS_NAND_PAGE_COUNT - hex "NAND chip page count" - depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \ - SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE || \ - NAND_OMAP_GPMC) - help - Number of pages in the NAND chip. - config SYS_NAND_PAGE_SIZE hex "NAND chip page size" depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \ diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index 6ab3f1f42c5..fb9c623f561 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -32,7 +33,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 6b17e744a69..83320112952 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -1258,7 +1259,7 @@ static struct nand_chip nand_chip; static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; @@ -1359,7 +1360,7 @@ int spl_nand_erase_one(int block, int page) if (nand_chip.select_chip) nand_chip.select_chip(mtd, 0); - page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + page_addr = page + block * SYS_NAND_BLOCK_PAGES; hwctrl(mtd, NAND_CMD_ERASE1, NAND_CTRL_CLE | NAND_CTRL_CHANGE); /* Row address */ hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE | NAND_CTRL_CHANGE); diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index 309e75d01e5..81ceb12103b 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -304,13 +305,13 @@ int nand_spl_load_image(uint32_t from, unsigned int size, void *buf) * Check if we have crossed a block boundary, and if so * check for bad block. */ - if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { + if (!(page % SYS_NAND_BLOCK_PAGES)) { /* * Yes, new block. See if this block is good. If not, * loop until we find a good block. */ while (is_badblock(page)) { - page = page + CONFIG_SYS_NAND_PAGE_COUNT; + page = page + SYS_NAND_BLOCK_PAGES; /* Check i we've reached the end of flash. */ if (page >= maxpages) return -1; diff --git a/drivers/mtd/nand/raw/nand_spl_loaders.c b/drivers/mtd/nand/raw/nand_spl_loaders.c index 156b44d8358..35d6b1d6c0c 100644 --- a/drivers/mtd/nand/raw/nand_spl_loaders.c +++ b/drivers/mtd/nand/raw/nand_spl_loaders.c @@ -12,7 +12,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) while (block <= lastblock) { if (!nand_is_bad_block(block)) { /* Skip bad blocks */ - while (page < CONFIG_SYS_NAND_PAGE_COUNT) { + while (page < SYS_NAND_BLOCK_PAGES) { nand_read_page(block, page, dst); /* * When offs is not aligned to page address the diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index 2f3af9edd4c..bbdb76d6b75 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -27,7 +28,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; while (!this->dev_ready(mtd)) ; @@ -59,7 +60,7 @@ static int nand_command(int block, int page, uint32_t offs, u8 cmd) { struct nand_chip *this = mtd_to_nand(mtd); - int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT; + int page_addr = page + block * SYS_NAND_BLOCK_PAGES; void (*hwctrl)(struct mtd_info *mtd, int cmd, unsigned int ctrl) = this->cmd_ctrl; diff --git a/drivers/mtd/nand/raw/omap_gpmc.c b/drivers/mtd/nand/raw/omap_gpmc.c index 1a5ed0de31a..0e25bd5dc28 100644 --- a/drivers/mtd/nand/raw/omap_gpmc.c +++ b/drivers/mtd/nand/raw/omap_gpmc.c @@ -6,6 +6,7 @@ #include #include +#include #include #include #include @@ -1298,7 +1299,7 @@ static int nand_is_bad_block(int block) static int nand_read_page(int block, int page, uchar *dst) { - int page_addr = block * CONFIG_SYS_NAND_PAGE_COUNT + page; + int page_addr = block * SYS_NAND_BLOCK_PAGES + page; loff_t ofs = page_addr * CONFIG_SYS_NAND_PAGE_SIZE; int ret; size_t len = CONFIG_SYS_NAND_PAGE_SIZE; diff --git a/include/system-constants.h b/include/system-constants.h index 59371568d1e..d688629f119 100644 --- a/include/system-constants.h +++ b/include/system-constants.h @@ -41,4 +41,8 @@ #define SPL_PAYLOAD_ARGS_ADDR 0 #endif +/* Number of pages per block */ +#define SYS_NAND_BLOCK_PAGES \ + (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE) + #endif -- cgit v1.3.1 From 38ef64e6ce3d1f84478c6d2700e4d76f80cfcaf4 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:44 -0400 Subject: spl: nand: Set bl_len to page size Since commit 34793598c83 ("mtd: nand: mxs_nand_spl: Remove the page aligned access") there are no longer any users of nand_get_mtd. However, it is still important to know what the page size is so we can allocate a large-enough buffer. If the image size is not page-aligned, we will go off the end of the buffer and clobber some memory. Introduce a new function nand_page_size which returns the page size. For most drivers it is easy to determine the page size. However, a few need to be modified since they only keep the page size around temporarily. It's possible that this patch could cause a regression on some platforms if the offset is non-aligned and there is invalid address space immediately before the load address. spl_load_legacy_img does not (except when compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or SPL_LOAD_IMX_CONTAINER (none in tree) would be affected. defconfig CONFIG_TEXT_BASE ======================= ================ am335x_evm 0x80800000 am43xx_evm 0x80800000 am43xx_evm_rtconly 0x80800000 am43xx_evm_usbhost_boot 0x80800000 am43xx_hs_evm 0x80800000 dra7xx_evm 0x80800000 gwventana_nand 0x17800000 imx8mn_bsh_smm_s2 0x40200000 All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a little underflow. Signed-off-by: Sean Anderson --- common/spl/spl_nand.c | 11 +++-------- drivers/mtd/nand/raw/am335x_spl_bch.c | 5 +++++ drivers/mtd/nand/raw/atmel_nand.c | 5 +++++ drivers/mtd/nand/raw/denali_spl.c | 5 +++++ drivers/mtd/nand/raw/fsl_ifc_spl.c | 8 ++++++++ drivers/mtd/nand/raw/lpc32xx_nand_mlc.c | 5 +++++ drivers/mtd/nand/raw/mt7621_nand_spl.c | 5 +++++ drivers/mtd/nand/raw/mxc_nand_spl.c | 5 +++++ drivers/mtd/nand/raw/mxs_nand_spl.c | 5 +++++ drivers/mtd/nand/raw/nand.c | 7 +++++++ drivers/mtd/nand/raw/nand_spl_simple.c | 5 +++++ drivers/mtd/nand/raw/sunxi_nand_spl.c | 8 +++++++- include/nand.h | 1 + 13 files changed, 66 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 5b6932bf7e0..57a7a1a73b9 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -72,23 +72,18 @@ static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs, return size; } -struct mtd_info * __weak nand_get_mtd(void) -{ - return NULL; -} - static int spl_nand_load_element(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, int offset, struct legacy_img_hdr *header) { - struct mtd_info *mtd = nand_get_mtd(); - int bl_len = mtd ? mtd->writesize : 1; + int bl_len; int err; err = nand_spl_load_image(offset, sizeof(*header), (void *)header); if (err) return err; + bl_len = nand_page_size(); if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; @@ -118,7 +113,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.dev = NULL; load.priv = NULL; load.filename = NULL; - load.bl_len = 1; + load.bl_len = IS_ENABLED(CONFIG_SPL_LZMA) ? bl_len : 1; load.read = spl_nand_legacy_read; return spl_load_legacy_img(spl_image, bootdev, &load, offset, header); diff --git a/drivers/mtd/nand/raw/am335x_spl_bch.c b/drivers/mtd/nand/raw/am335x_spl_bch.c index fb9c623f561..6831af98b73 100644 --- a/drivers/mtd/nand/raw/am335x_spl_bch.c +++ b/drivers/mtd/nand/raw/am335x_spl_bch.c @@ -218,6 +218,11 @@ void nand_init(void) nand_command(0, 0, 0, NAND_CMD_RESET); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + /* Unselect after operation */ void nand_deselect(void) { diff --git a/drivers/mtd/nand/raw/atmel_nand.c b/drivers/mtd/nand/raw/atmel_nand.c index 83320112952..6d94e7af38e 100644 --- a/drivers/mtd/nand/raw/atmel_nand.c +++ b/drivers/mtd/nand/raw/atmel_nand.c @@ -1452,6 +1452,11 @@ void nand_init(void) nand_chip.select_chip(mtd, 0); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + void nand_deselect(void) { if (nand_chip.select_chip) diff --git a/drivers/mtd/nand/raw/denali_spl.c b/drivers/mtd/nand/raw/denali_spl.c index 690279c9976..165a23312cb 100644 --- a/drivers/mtd/nand/raw/denali_spl.c +++ b/drivers/mtd/nand/raw/denali_spl.c @@ -234,4 +234,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) return 0; } +unsigned int nand_page_size(void) +{ + return page_size; +} + void nand_deselect(void) {} diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index c67065eaf8c..69d26f1f79a 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -106,6 +106,8 @@ static inline int bad_block(uchar *marker, int port_size) return __raw_readw((u16 *)marker) != 0xffff; } +static int saved_page_size; + int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) { struct fsl_ifc_fcm *gregs = (void *)CFG_SYS_IFC_ADDR; @@ -150,6 +152,7 @@ int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst) if (port_size == 8) bad_marker = 5; } + saved_page_size = page_size; ver = ifc_in32(&gregs->ifc_rev); if (ver >= FSL_IFC_V2_0_0) @@ -302,6 +305,11 @@ void nand_init(void) { } +unsigned int nand_page_size(void) +{ + return saved_page_size; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c index ac2e669d46b..f8ae216d56c 100644 --- a/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c +++ b/drivers/mtd/nand/raw/lpc32xx_nand_mlc.c @@ -765,4 +765,9 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) return 0; } +unsigned int nand_page_size(void) +{ + return BYTES_PER_PAGE; +} + #endif /* CONFIG_SPL_BUILD */ diff --git a/drivers/mtd/nand/raw/mt7621_nand_spl.c b/drivers/mtd/nand/raw/mt7621_nand_spl.c index 114fc8b7cea..a2be9ba80e0 100644 --- a/drivers/mtd/nand/raw/mt7621_nand_spl.c +++ b/drivers/mtd/nand/raw/mt7621_nand_spl.c @@ -203,6 +203,11 @@ unsigned long nand_size(void) return SZ_2G; } +unsigned int nand_page_size(void) +{ + return nfc_dev.nand.mtd.writesize; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/mxc_nand_spl.c b/drivers/mtd/nand/raw/mxc_nand_spl.c index 81ceb12103b..a855c9987f8 100644 --- a/drivers/mtd/nand/raw/mxc_nand_spl.c +++ b/drivers/mtd/nand/raw/mxc_nand_spl.c @@ -351,3 +351,8 @@ __used void nand_boot(void) void nand_init(void) {} void nand_deselect(void) {} + +unsigned int nand_page_size(void) +{ + return CONFIG_SYS_NAND_PAGE_SIZE; +} diff --git a/drivers/mtd/nand/raw/mxs_nand_spl.c b/drivers/mtd/nand/raw/mxs_nand_spl.c index 300662994cf..f7d3f02f85a 100644 --- a/drivers/mtd/nand/raw/mxs_nand_spl.c +++ b/drivers/mtd/nand/raw/mxs_nand_spl.c @@ -295,6 +295,11 @@ int nand_default_bbt(struct mtd_info *mtd) return 0; } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + void nand_deselect(void) { } diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index eacd99c4e27..4da41438790 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -174,3 +174,10 @@ void nand_init(void) create_mtd_concat(); } + +unsigned int nand_page_size(void) +{ + struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); + + return mtd ? mtd->writesize : 1; +} diff --git a/drivers/mtd/nand/raw/nand_spl_simple.c b/drivers/mtd/nand/raw/nand_spl_simple.c index bbdb76d6b75..80d6e0e1e4e 100644 --- a/drivers/mtd/nand/raw/nand_spl_simple.c +++ b/drivers/mtd/nand/raw/nand_spl_simple.c @@ -227,6 +227,11 @@ void nand_init(void) nand_chip.select_chip(mtd, 0); } +unsigned int nand_page_size(void) +{ + return nand_to_mtd(&nand_chip)->writesize; +} + /* Unselect after operation */ void nand_deselect(void) { diff --git a/drivers/mtd/nand/raw/sunxi_nand_spl.c b/drivers/mtd/nand/raw/sunxi_nand_spl.c index 6de0b0a3554..c9b8c78ed75 100644 --- a/drivers/mtd/nand/raw/sunxi_nand_spl.c +++ b/drivers/mtd/nand/raw/sunxi_nand_spl.c @@ -524,9 +524,10 @@ static int nand_read_buffer(struct nfc_config *conf, uint32_t offs, return 0; } +static struct nfc_config conf; + int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) { - static struct nfc_config conf = { }; int ret; ret = nand_detect_config(&conf, offs, dest); @@ -536,6 +537,11 @@ int nand_spl_load_image(uint32_t offs, unsigned int size, void *dest) return nand_read_buffer(&conf, offs, size, dest); } +unsigned int nand_page_size(void) +{ + return conf.page_size; +} + void nand_deselect(void) { struct sunxi_ccm_reg *const ccm = diff --git a/include/nand.h b/include/nand.h index 70c1286ccb4..c1d7533aaac 100644 --- a/include/nand.h +++ b/include/nand.h @@ -12,6 +12,7 @@ extern void nand_init(void); unsigned long nand_size(void); +unsigned int nand_page_size(void); #include #include -- cgit v1.3.1 From b35df87ae5c812d09c82e3c329b01275ab5bd41b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:47 -0400 Subject: mtd: Rename SPL_MTD_SUPPORT to SPL_MTD Rename SPL_MTD_SUPPORT to SPL_MTD in order to match MTD. This allows using CONFIG_IS_ENABLED to test for MTD support. Signed-off-by: Sean Anderson --- common/spl/Kconfig | 2 +- configs/am335x_baltos_defconfig | 2 +- configs/am335x_evm_defconfig | 2 +- configs/am335x_evm_spiboot_defconfig | 2 +- configs/am335x_hs_evm_defconfig | 2 +- configs/am335x_hs_evm_uart_defconfig | 2 +- configs/am335x_igep003x_defconfig | 2 +- configs/am335x_sl50_defconfig | 2 +- configs/am3517_evm_defconfig | 2 +- configs/am43xx_evm_defconfig | 2 +- configs/am43xx_evm_rtconly_defconfig | 2 +- configs/am43xx_evm_usbhost_boot_defconfig | 2 +- configs/am43xx_hs_evm_defconfig | 2 +- configs/am62ax_evm_r5_defconfig | 2 +- configs/am65x_evm_a53_defconfig | 2 +- configs/cm_t43_defconfig | 2 +- configs/igep00x0_defconfig | 2 +- configs/imx6ulz_smm_m2_defconfig | 2 +- configs/imx8mn_bsh_smm_s2_defconfig | 2 +- configs/j7200_evm_a72_defconfig | 2 +- configs/j7200_evm_r5_defconfig | 2 +- configs/j721e_evm_a72_defconfig | 2 +- configs/j721e_evm_r5_defconfig | 2 +- configs/j721s2_evm_a72_defconfig | 2 +- configs/j721s2_evm_r5_defconfig | 2 +- configs/omap35_logic_defconfig | 2 +- configs/omap35_logic_somlv_defconfig | 2 +- configs/omap3_beagle_defconfig | 2 +- configs/omap3_evm_defconfig | 2 +- configs/omap3_logic_defconfig | 2 +- configs/omap3_logic_somlv_defconfig | 2 +- configs/phycore-am335x-r2-regor_defconfig | 2 +- configs/phycore-am335x-r2-wega_defconfig | 2 +- configs/socfpga_secu1_defconfig | 2 +- configs/stm32746g-eval_spl_defconfig | 2 +- configs/stm32f746-disco_spl_defconfig | 2 +- configs/stm32f769-disco_spl_defconfig | 2 +- configs/stm32mp15_basic_defconfig | 2 +- configs/stm32mp15_dhcom_basic_defconfig | 2 +- configs/stm32mp15_dhcor_basic_defconfig | 2 +- drivers/mtd/Makefile | 2 +- include/mtd/cfi_flash.h | 2 +- 42 files changed, 42 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 25cd18afda7..00332cf243a 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -857,7 +857,7 @@ config SPL_MPC8XXX_INIT_DDR allows DRAM to be set up before loading U-Boot into that DRAM, where it can run. -config SPL_MTD_SUPPORT +config SPL_MTD bool "Support MTD drivers" help Enable support for MTD (Memory Technology Device) within SPL. MTD diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 3891e48e9c7..0599ae217e6 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index 73f221d55bc..5d38dad35bb 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -26,7 +26,7 @@ CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_ETH=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_MUSB_NEW=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am335x_evm_spiboot_defconfig b/configs/am335x_evm_spiboot_defconfig index 9866246aa51..b5b11fb62c8 100644 --- a/configs/am335x_evm_spiboot_defconfig +++ b/configs/am335x_evm_spiboot_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_SPI_LOAD=y diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig index b961b6c41f0..ea46e58be2d 100644 --- a/configs/am335x_hs_evm_defconfig +++ b/configs/am335x_hs_evm_defconfig @@ -27,7 +27,7 @@ CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig index b5d8eac9f3d..7886557c8da 100644 --- a/configs/am335x_hs_evm_uart_defconfig +++ b/configs/am335x_hs_evm_uart_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FIT_IMAGE_TINY=y # CONFIG_SPL_ENV_SUPPORT is not set # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am335x_igep003x_defconfig b/configs/am335x_igep003x_defconfig index 4c5c82f9bdd..e2c5b70c405 100644 --- a/configs/am335x_igep003x_defconfig +++ b/configs/am335x_igep003x_defconfig @@ -24,7 +24,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am335x_sl50_defconfig b/configs/am335x_sl50_defconfig index 9ba376feda8..fb61dd71c69 100644 --- a/configs/am335x_sl50_defconfig +++ b/configs/am335x_sl50_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 111929fb912..a96936c92d2 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -26,7 +26,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 5f2356bcd32..d5ce2995548 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am43xx_evm_rtconly_defconfig b/configs/am43xx_evm_rtconly_defconfig index 30681e7eeb6..a0a9e8ac584 100644 --- a/configs/am43xx_evm_rtconly_defconfig +++ b/configs/am43xx_evm_rtconly_defconfig @@ -21,7 +21,7 @@ CONFIG_SPL_MAX_SIZE=0x439e0 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 6c4cc99e5ff..cd47806204e 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -20,7 +20,7 @@ CONFIG_SPL_MAX_SIZE=0x37690 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 49ecb4c9e66..d721664ecb1 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -28,7 +28,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_ETH=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/am62ax_evm_r5_defconfig b/configs/am62ax_evm_r5_defconfig index d52de8bf8be..40704151255 100644 --- a/configs/am62ax_evm_r5_defconfig +++ b/configs/am62ax_evm_r5_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 CONFIG_SPL_DMA=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index f4369865bf6..55289b967b7 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -52,7 +52,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y CONFIG_SPL_POWER_DOMAIN=y diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index 73ccefd269a..1a558b030fe 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -37,7 +37,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x480 CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y # CONFIG_SPL_NAND_SUPPORT is not set CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 3b1af07f057..34439cf77be 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -24,7 +24,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index d6edc719004..c471e04d9bd 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -25,7 +25,7 @@ CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_BSS_START_ADDR=0x84100000 CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_DMA=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_DM=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 657eb354c1b..a9c02976f8c 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -43,7 +43,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NAND_IDENT=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index cb4a141675d..01f19570d7e 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -50,7 +50,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index d25dd8134b6..10b7205e49e 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -48,7 +48,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index 99e0e168ebf..1d043f2fdeb 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -50,7 +50,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index e76ab5997fe..55169bb1391 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -53,7 +53,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 876f07816a2..a7adb9282b0 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 4990e271c3f..c0fdd86e1f0 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -55,7 +55,7 @@ CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_NOR_SUPPORT=y CONFIG_SPL_DM_RESET=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 3a656072534..5040af058dd 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -30,7 +30,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index 868e89114b7..1ea35c7cfab 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 7f0b927528d..c8c9ae02f16 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index 3434783d45b..93427f3691c 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -22,7 +22,7 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SPL_FS_EXT4 is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 78bfbbd1a22..729586bfdc1 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -29,7 +29,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index aefd8861db3..f0f326d2f9c 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -31,7 +31,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set # CONFIG_SPL_FS_EXT4 is not set # CONFIG_SPL_I2C is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_SIMPLE=y diff --git a/configs/phycore-am335x-r2-regor_defconfig b/configs/phycore-am335x-r2-regor_defconfig index 85d53d06357..cbfe1cf7985 100644 --- a/configs/phycore-am335x-r2-regor_defconfig +++ b/configs/phycore-am335x-r2-regor_defconfig @@ -28,7 +28,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/phycore-am335x-r2-wega_defconfig b/configs/phycore-am335x-r2-wega_defconfig index 60607548a25..b91b9665cc2 100644 --- a/configs/phycore-am335x-r2-wega_defconfig +++ b/configs/phycore-am335x-r2-wega_defconfig @@ -28,7 +28,7 @@ CONFIG_ARCH_MISC_INIT=y CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_SYS_MALLOC_SIZE=0x800000 CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_DRIVERS=y CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index 157391a71c0..09a7a3453e8 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -43,7 +43,7 @@ CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE is not set -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_NAND_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_BOOTM_LEN=0x4000000 diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index 3864e21a180..f9711bedd7d 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -34,7 +34,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index b2a786121c5..a2b740c9cce 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -34,7 +34,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x80c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index 34622032210..37d22f8d95f 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -33,7 +33,7 @@ CONFIG_SPL_PAD_TO=0x9000 CONFIG_SPL_NO_BSS_LIMIT=y CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_XIP_SUPPORT=y CONFIG_SPL_PAYLOAD_ARGS_ADDR=0x81c0000 CONFIG_SPL_DM_RESET=y diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 6df09352400..be553ad3c36 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -40,7 +40,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index b6cd0a47fa7..3d5df307d40 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -47,7 +47,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_RAM_SUPPORT=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index d1acf9c657e..50a8882a074 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -45,7 +45,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=3 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_I2C=y -CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_MTD=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER=y CONFIG_SPL_RAM_SUPPORT=y diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile index c638980ea2b..c2fc80b10f0 100644 --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile @@ -31,7 +31,7 @@ obj-$(CONFIG_NVMXIP) += nvmxip/ else ifneq ($(mtd-y),) -obj-$(CONFIG_SPL_MTD_SUPPORT) += mtd.o +obj-$(CONFIG_SPL_MTD) += mtd.o endif obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += nand/ obj-$(CONFIG_SPL_ONENAND_SUPPORT) += onenand/ diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 52cd1c4dbc4..f4aecaac75f 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -163,7 +163,7 @@ struct cfi_pri_hdr { #if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) /* map to cfi_flash_num_flash_banks only when supported */ #if IS_ENABLED(CONFIG_FLASH_CFI_DRIVER) && \ - (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD_SUPPORT)) + (!IS_ENABLED(CONFIG_SPL_BUILD) || IS_ENABLED(CONFIG_SPL_MTD)) #define CFI_FLASH_BANKS (cfi_flash_num_flash_banks) /* board code can update this variable before CFI detection */ extern int cfi_flash_num_flash_banks; -- cgit v1.3.1 From b37a9208a2ed36b67303e8169539c1a0c42ea0e1 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:48 -0400 Subject: mtd: Add some fallbacks for add/del_mtd_device This allows using these functions without ifdefs. OneNAND depends on MTD, so this ifdef was redundant in the first place. Signed-off-by: Sean Anderson Reviewed-by: Dario Binacchi --- drivers/mtd/nand/raw/nand.c | 2 -- drivers/mtd/onenand/onenand_uboot.c | 2 -- include/linux/mtd/mtd.h | 12 ++++++++++++ 3 files changed, 12 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 4da41438790..3abd82068fb 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -60,13 +60,11 @@ int nand_register(int devnum, struct mtd_info *mtd) sprintf(dev_name[devnum], "nand%d", devnum); mtd->name = dev_name[devnum]; -#ifdef CONFIG_MTD /* * Add MTD device so that we can reference it later * via the mtdcore infrastructure (e.g. ubi). */ add_mtd_device(mtd); -#endif total_nand_size += mtd->size / 1024; diff --git a/drivers/mtd/onenand/onenand_uboot.c b/drivers/mtd/onenand/onenand_uboot.c index 04791df69bb..ecacabefadc 100644 --- a/drivers/mtd/onenand/onenand_uboot.c +++ b/drivers/mtd/onenand/onenand_uboot.c @@ -44,14 +44,12 @@ void onenand_init(void) puts("Flex-"); puts("OneNAND: "); -#ifdef CONFIG_MTD /* * Add MTD device so that we can reference it later * via the mtdcore infrastructure (e.g. ubi). */ onenand_mtd.name = dev_name; add_mtd_device(&onenand_mtd); -#endif } print_size(onenand_chip.chipsize, "\n"); } diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 09f52698877..7a66c7af749 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -552,8 +552,20 @@ unsigned mtd_mmap_capabilities(struct mtd_info *mtd); #ifdef __UBOOT__ /* drivers/mtd/mtdcore.h */ +#if CONFIG_IS_ENABLED(MTD) int add_mtd_device(struct mtd_info *mtd); int del_mtd_device(struct mtd_info *mtd); +#else +static inline int add_mtd_device(struct mtd_info *mtd) +{ + return -ENOSYS; +} + +static inline int del_mtd_device(struct mtd_info *mtd) +{ + return -ENOSYS; +} +#endif #ifdef CONFIG_MTD_PARTITIONS int add_mtd_partitions(struct mtd_info *, const struct mtd_partition *, int); -- cgit v1.3.1 From c2034821772898b54d745e79fc96586cebaae12c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:49 -0400 Subject: nand: Add function to unregister NAND devices This performs the opposite of nand_register, allowing drivers to unregister nand devices. This is probably unnecessary for most regular drivers, but we expect sandbox drivers to get repeatedly bound/unbound, so this will help avoid dangling pointers. Signed-off-by: Sean Anderson Reviewed-by: Dario Binacchi --- drivers/mtd/nand/raw/nand.c | 17 +++++++++++++++++ include/nand.h | 1 + 2 files changed, 18 insertions(+) (limited to 'include') diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 3abd82068fb..80017b3dddd 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -74,6 +74,23 @@ int nand_register(int devnum, struct mtd_info *mtd) return 0; } +void nand_unregister(struct mtd_info *mtd) +{ + int devnum = nand_mtd_to_devnum(mtd); + + if (devnum < 0) + return; + + if (nand_curr_device == devnum) + nand_curr_device = -1; + + total_nand_size -= mtd->size / 1024; + + del_mtd_device(nand_info[devnum]); + + nand_info[devnum] = NULL; +} + #if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) static void nand_init_chip(int i) { diff --git a/include/nand.h b/include/nand.h index c1d7533aaac..fc584f5ef7a 100644 --- a/include/nand.h +++ b/include/nand.h @@ -22,6 +22,7 @@ int nand_mtd_to_devnum(struct mtd_info *mtd); #if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT) void board_nand_init(void); int nand_register(int devnum, struct mtd_info *mtd); +void nand_unregister(struct mtd_info *mtd); #else struct nand_chip; -- cgit v1.3.1 From 333d43f6a3e2aa1d6249d22211d77802614e37e5 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:50 -0400 Subject: nand: Allow reinitialization NAND devices are destroyed in between unit tests. Provide a function to reinitialize the subsystem at the beginning of each test. Signed-off-by: Sean Anderson Reviewed-by: Dario Binacchi --- drivers/mtd/nand/raw/nand.c | 40 +++++++++++++++++++++++++++++++++------- include/nand.h | 1 + 2 files changed, 34 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c index 80017b3dddd..4c18861aa25 100644 --- a/drivers/mtd/nand/raw/nand.c +++ b/drivers/mtd/nand/raw/nand.c @@ -115,6 +115,8 @@ static void nand_init_chip(int i) #endif #ifdef CONFIG_MTD_CONCAT +struct mtd_info *concat_mtd; + static void create_mtd_concat(void) { struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE]; @@ -129,28 +131,40 @@ static void create_mtd_concat(void) } } if (nand_devices_found > 1) { - struct mtd_info *mtd; char c_mtd_name[16]; /* * We detected multiple devices. Concatenate them together. */ sprintf(c_mtd_name, "nand%d", nand_devices_found); - mtd = mtd_concat_create(nand_info_list, nand_devices_found, - c_mtd_name); + concat_mtd = mtd_concat_create(nand_info_list, + nand_devices_found, c_mtd_name); - if (mtd == NULL) + if (!concat_mtd) return; - nand_register(nand_devices_found, mtd); + nand_register(nand_devices_found, concat_mtd); } return; } + +static void destroy_mtd_concat(void) +{ + if (!concat_mtd) + return; + + mtd_concat_destroy(concat_mtd); + concat_mtd = NULL; +} #else static void create_mtd_concat(void) { } + +static void destroy_mtd_concat(void) +{ +} #endif unsigned long nand_size(void) @@ -158,10 +172,10 @@ unsigned long nand_size(void) return total_nand_size; } +static int initialized; + void nand_init(void) { - static int initialized; - /* * Avoid initializing NAND Flash multiple times, * otherwise it will calculate a wrong total size. @@ -190,6 +204,18 @@ void nand_init(void) create_mtd_concat(); } +void nand_reinit(void) +{ + int i; + + destroy_mtd_concat(); + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + assert(!nand_info[i]); + + initialized = 0; + nand_init(); +} + unsigned int nand_page_size(void) { struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device); diff --git a/include/nand.h b/include/nand.h index fc584f5ef7a..220ffa202ef 100644 --- a/include/nand.h +++ b/include/nand.h @@ -11,6 +11,7 @@ #include extern void nand_init(void); +void nand_reinit(void); unsigned long nand_size(void); unsigned int nand_page_size(void); -- cgit v1.3.1 From 9181cb0507d1dd5627cc3d9cd86d427abe00cc21 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Sat, 4 Nov 2023 16:37:51 -0400 Subject: arch: sandbox: Add function to create temporary files When working with sparse data buffers that may be larger than the address space, it is convenient to work with files instead. Add a function to create temporary files of a certain size. Signed-off-by: Sean Anderson --- arch/sandbox/cpu/os.c | 17 +++++++++++++++++ include/os.h | 13 +++++++++++++ 2 files changed, 30 insertions(+) (limited to 'include') diff --git a/arch/sandbox/cpu/os.c b/arch/sandbox/cpu/os.c index 85d0d6a1703..8847c4cd0a8 100644 --- a/arch/sandbox/cpu/os.c +++ b/arch/sandbox/cpu/os.c @@ -282,6 +282,23 @@ int os_persistent_file(char *buf, int maxsize, const char *fname) return 0; } +int os_mktemp(char *fname, off_t size) +{ + int fd; + + fd = mkostemp(fname, O_CLOEXEC); + if (fd < 0) + return -errno; + + if (unlink(fname) < 0) + return -errno; + + if (ftruncate(fd, size)) + return -errno; + + return fd; +} + /* Restore tty state when we exit */ static struct termios orig_term; static bool term_setup; diff --git a/include/os.h b/include/os.h index fc8a1b15cbf..877404a6c13 100644 --- a/include/os.h +++ b/include/os.h @@ -108,6 +108,19 @@ int os_unlink(const char *pathname); */ int os_persistent_file(char *buf, int maxsize, const char *fname); +/** + * os_mktemp() - Create a temporary file + * @fname: The template to use for the file name. This must end with 6 Xs. It + * will be modified to the opened filename on success. + * @size: The size of the file + * + * Create a temporary file using @fname as a template, unlink it, and truncate + * it to @size. + * + * Return: A file descriptor, or negative errno on error + */ +int os_mktemp(char *fname, off_t size); + /** * os_exit() - access to the OS exit() system call * -- cgit v1.3.1 From 0c6c83e6a2608421d992781bdbd33a12fa31c10d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:38 -0500 Subject: spl: Remove dev from spl_load_info dev and priv serve the same purpose, and are never set at the same time. Remove dev and convert all users to priv. While we're at it, reorder bl_len to be last for better alignment. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_mmc.c | 6 +++--- common/spl/spl_spi.c | 6 +++--- drivers/usb/gadget/f_sdp.c | 6 +++--- include/spl.h | 4 +--- 4 files changed, 10 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 6d9137c32e0..3d7551a7dae 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -65,7 +65,7 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { - struct mmc *mmc = load->dev; + struct mmc *mmc = load->priv; return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); } @@ -105,7 +105,7 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.dev = mmc; + load.priv = mmc; load.filename = NULL; load.bl_len = mmc->read_bl_len; load.read = h_spl_load_read; @@ -114,7 +114,7 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.dev = mmc; + load.priv = mmc; load.filename = NULL; load.bl_len = mmc->read_bl_len; load.read = h_spl_load_read; diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index d83d70f2f33..af7a28e7c25 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -59,7 +59,7 @@ static int spi_load_image_os(struct spl_image_info *spl_image, static ulong spl_spi_fit_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) { - struct spi_flash *flash = load->dev; + struct spi_flash *flash = load->priv; ulong ret; ret = spi_flash_read(flash, sector, count, buf); @@ -151,7 +151,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.dev = flash; + load.priv = flash; load.filename = NULL; load.bl_len = 1; load.read = spl_spi_fit_read; @@ -162,7 +162,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.dev = flash; + load.priv = flash; load.filename = NULL; load.bl_len = 1; load.read = spl_spi_fit_read; diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index ee9384fb37e..1b16b7eb452 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -744,7 +744,7 @@ static ulong sdp_load_read(struct spl_load_info *load, ulong sector, { debug("%s: sector %lx, count %lx, buf %lx\n", __func__, sector, count, (ulong)buf); - memcpy(buf, (void *)(load->dev + sector), count); + memcpy(buf, (void *)(load->priv + sector), count); return count; } @@ -844,7 +844,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.dev = header; + load.priv = header; load.bl_len = 1; load.read = sdp_load_read; spl_load_simple_fit(spl_image, &load, 0, @@ -857,7 +857,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, valid_container_hdr((void *)header)) { struct spl_load_info load; - load.dev = header; + load.priv = header; load.bl_len = 1; load.read = sdp_load_read; spl_load_imx_container(spl_image, &load, 0); diff --git a/include/spl.h b/include/spl.h index 8ff20adc28e..951e136b9ea 100644 --- a/include/spl.h +++ b/include/spl.h @@ -285,16 +285,13 @@ static inline void *spl_image_fdt_addr(struct spl_image_info *info) /** * Information required to load data from a device * - * @dev: Pointer to the device, e.g. struct mmc * * @priv: Private data for the device * @bl_len: Block length for reading in bytes * @filename: Name of the fit image file. * @read: Function to call to read from the device */ struct spl_load_info { - void *dev; void *priv; - int bl_len; const char *filename; /** * read() - Read from device @@ -307,6 +304,7 @@ struct spl_load_info { */ ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, void *buf); + int bl_len; }; /* -- cgit v1.3.1 From 73c40fcb7367f5a431c987f7da0420c058a939fc Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:40 -0500 Subject: spl: Refactor spl_load_info->read to use units of bytes Simplify things a bit for callers of spl_load_info->read by refactoring it to use units of bytes instead of bl_len. This generally simplifies the logic, as MMC is the only loader which actually works in sectors. It will also allow further refactoring to remove the special-case handling of filename. spl_load_legacy_img already works in units of bytes (oops) so it doesn't need to be changed. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- arch/arm/mach-imx/spl_imx_romapi.c | 16 +++--------- common/spl/spl_fit.c | 51 +++++++++++++++++++------------------- common/spl/spl_imx_container.c | 45 ++++++++++++++------------------- common/spl/spl_mmc.c | 24 ++++++++++-------- common/spl/spl_nand.c | 8 +++--- include/spl.h | 18 ++++++++------ test/image/spl_load_os.c | 13 +++++----- 7 files changed, 82 insertions(+), 93 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index 93d48e56aca..d7f6cb4b5ba 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -53,16 +53,10 @@ static int is_boot_from_stream_device(u32 boot) } static ulong spl_romapi_read_seekable(struct spl_load_info *load, - ulong sector, ulong count, + ulong offset, ulong byte, void *buf) { - u32 pagesize = *(u32 *)load->priv; - ulong byte = count * pagesize; - u32 offset; - - offset = sector * pagesize; - - return spl_romapi_raw_seekable_read(offset, byte, buf) / pagesize; + return spl_romapi_raw_seekable_read(offset, byte, buf); } static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, @@ -109,8 +103,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, memset(&load, 0, sizeof(load)); load.bl_len = pagesize; load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - return spl_load_simple_fit(spl_image, &load, offset / pagesize, header); + return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; @@ -118,9 +111,8 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, memset(&load, 0, sizeof(load)); load.bl_len = pagesize; load.read = spl_romapi_read_seekable; - load.priv = &pagesize; - ret = spl_load_imx_container(spl_image, &load, offset / pagesize); + ret = spl_load_imx_container(spl_image, &load, offset); } else { /* TODO */ puts("Can't support legacy image\n"); diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 6084ead0919..ce7ef0efd0d 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -180,7 +180,7 @@ static int get_aligned_image_offset(struct spl_load_info *info, int offset) if (info->filename) return offset & ~(ARCH_DMA_MINALIGN - 1); - return offset / info->bl_len; + return ALIGN_DOWN(offset, info->bl_len); } static int get_aligned_image_overhead(struct spl_load_info *info, int offset) @@ -205,7 +205,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, if (info->filename) return data_size; - return (data_size + info->bl_len - 1) / info->bl_len; + return ALIGN(data_size, info->bl_len); } /** @@ -222,7 +222,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, * * Return: 0 on success or a negative error number. */ -static int load_simple_fit(struct spl_load_info *info, ulong sector, +static int load_simple_fit(struct spl_load_info *info, ulong fit_offset, const struct spl_fit_info *ctx, int node, struct spl_image_info *image_info) { @@ -234,7 +234,6 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector, void *load_ptr; void *src; ulong overhead; - int nr_sectors; uint8_t image_comp = -1, type = -1; const void *data; const void *fit = ctx->fit; @@ -291,11 +290,12 @@ static int load_simple_fit(struct spl_load_info *info, ulong sector, length = len; overhead = get_aligned_image_overhead(info, offset); - nr_sectors = get_aligned_image_size(info, length, offset); + size = get_aligned_image_size(info, length, offset); if (info->read(info, - sector + get_aligned_image_offset(info, offset), - nr_sectors, src_ptr) != nr_sectors) + fit_offset + + get_aligned_image_offset(info, offset), size, + src_ptr) != size) return -EIO; debug("External data: dst=%p, offset=%x, size=%lx\n", @@ -380,7 +380,7 @@ __weak int board_spl_fit_append_fdt_skip(const char *name) } static int spl_fit_append_fdt(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, + struct spl_load_info *info, ulong offset, const struct spl_fit_info *ctx) { struct spl_image_info image_info; @@ -414,7 +414,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, spl_image->fdt_addr = map_sysmem(image_info.load_addr, size); memcpy(spl_image->fdt_addr, gd->fdt_blob, size); } else { - ret = load_simple_fit(info, sector, ctx, node, &image_info); + ret = load_simple_fit(info, offset, ctx, node, &image_info); if (ret < 0) return ret; @@ -465,7 +465,7 @@ static int spl_fit_append_fdt(struct spl_image_info *spl_image, __func__); } image_info.load_addr = (ulong)tmpbuffer; - ret = load_simple_fit(info, sector, ctx, node, + ret = load_simple_fit(info, offset, ctx, node, &image_info); if (ret < 0) break; @@ -642,7 +642,7 @@ static int spl_fit_upload_fpga(struct spl_fit_info *ctx, int node, } static int spl_fit_load_fpga(struct spl_fit_info *ctx, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { int node, ret; @@ -657,7 +657,7 @@ static int spl_fit_load_fpga(struct spl_fit_info *ctx, warn_deprecated("'fpga' property in config node. Use 'loadables'"); /* Load the image and set up the fpga_image structure */ - ret = load_simple_fit(info, sector, ctx, node, &fpga_image); + ret = load_simple_fit(info, offset, ctx, node, &fpga_image); if (ret) { printf("%s: Cannot load the FPGA: %i\n", __func__, ret); return ret; @@ -667,11 +667,10 @@ static int spl_fit_load_fpga(struct spl_fit_info *ctx, } static int spl_simple_fit_read(struct spl_fit_info *ctx, - struct spl_load_info *info, ulong sector, + struct spl_load_info *info, ulong offset, const void *fit_header) { unsigned long count, size; - int sectors; void *buf; /* @@ -690,13 +689,13 @@ static int spl_simple_fit_read(struct spl_fit_info *ctx, * For FIT with data embedded, data is loaded as part of FIT image. * For FIT with external data, data is not loaded in this step. */ - sectors = get_aligned_image_size(info, size, 0); - buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len); + size = get_aligned_image_size(info, size, 0); + buf = board_spl_fit_buffer_addr(size, size, 1); - count = info->read(info, sector, sectors, buf); + count = info->read(info, offset, size, buf); ctx->fit = buf; - debug("fit read sector %lx, sectors=%d, dst=%p, count=%lu, size=0x%lx\n", - sector, sectors, buf, count, size); + debug("fit read offset %lx, size=%lu, dst=%p, count=%lu\n", + offset, size, buf, count); return (count == 0) ? -EIO : 0; } @@ -728,7 +727,7 @@ static int spl_simple_fit_parse(struct spl_fit_info *ctx) } int spl_load_simple_fit(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, void *fit) + struct spl_load_info *info, ulong offset, void *fit) { struct spl_image_info image_info; struct spl_fit_info ctx; @@ -737,7 +736,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, int index = 0; int firmware_node; - ret = spl_simple_fit_read(&ctx, info, sector, fit); + ret = spl_simple_fit_read(&ctx, info, offset, fit); if (ret < 0) return ret; @@ -752,7 +751,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, return ret; if (IS_ENABLED(CONFIG_SPL_FPGA)) - spl_fit_load_fpga(&ctx, info, sector); + spl_fit_load_fpga(&ctx, info, offset); /* * Find the U-Boot image using the following search order: @@ -782,7 +781,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, } /* Load the image and set up the spl_image structure */ - ret = load_simple_fit(info, sector, &ctx, node, spl_image); + ret = load_simple_fit(info, offset, &ctx, node, spl_image); if (ret) return ret; @@ -800,7 +799,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, * We allow this to fail, as the U-Boot image might embed its FDT. */ if (os_takes_devicetree(spl_image->os)) { - ret = spl_fit_append_fdt(spl_image, info, sector, &ctx); + ret = spl_fit_append_fdt(spl_image, info, offset, &ctx); if (ret < 0 && spl_image->os != IH_OS_U_BOOT) return ret; } @@ -823,7 +822,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, continue; image_info.load_addr = 0; - ret = load_simple_fit(info, sector, &ctx, node, &image_info); + ret = load_simple_fit(info, offset, &ctx, node, &image_info); if (ret < 0) { printf("%s: can't load image loadables index %d (ret = %d)\n", __func__, index, ret); @@ -837,7 +836,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, debug("Loadable is %s\n", genimg_get_os_name(os_type)); if (os_takes_devicetree(os_type)) { - spl_fit_append_fdt(&image_info, info, sector, &ctx); + spl_fit_append_fdt(&image_info, info, offset, &ctx); spl_image->fdt_addr = image_info.fdt_addr; } diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index 1cc51782766..ad89a99fb23 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -19,11 +19,10 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, struct spl_load_info *info, struct container_hdr *container, int image_index, - u32 container_sector) + ulong container_offset) { struct boot_img_t *images; - ulong sector; - u32 sectors; + ulong offset, overhead, size; if (image_index > container->num_images) { debug("Invalid image number\n"); @@ -39,16 +38,14 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, return NULL; } - sectors = ALIGN(images[image_index].size, info->bl_len) / - info->bl_len; - sector = images[image_index].offset / info->bl_len + - container_sector; + size = ALIGN(images[image_index].size, info->bl_len); + offset = images[image_index].offset + container_offset; - debug("%s: container: %p sector: %lu sectors: %u\n", __func__, - container, sector, sectors); - if (info->read(info, sector, sectors, - map_sysmem(images[image_index].dst, - images[image_index].size)) != sectors) { + debug("%s: container: %p offset: %lu size: %lu\n", __func__, + container, offset, size); + if (info->read(info, offset, size, + map_sysmem(images[image_index].dst - overhead, + images[image_index].size)) != size) { printf("%s wrong\n", __func__); return NULL; } @@ -62,15 +59,13 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, } static int read_auth_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { struct container_hdr *container = NULL; u16 length; - u32 sectors; int i, size, ret = 0; size = ALIGN(CONTAINER_HDR_ALIGNMENT, info->bl_len); - sectors = size / info->bl_len; /* * It will not override the ATF code, so safe to use it here, @@ -80,9 +75,9 @@ static int read_auth_container(struct spl_image_info *spl_image, if (!container) return -ENOMEM; - debug("%s: container: %p sector: %lu sectors: %u\n", __func__, - container, sector, sectors); - if (info->read(info, sector, sectors, container) != sectors) { + debug("%s: container: %p offset: %lu size: %u\n", __func__, + container, offset, size); + if (info->read(info, offset, size, container) != size) { ret = -EIO; goto end; } @@ -104,17 +99,15 @@ static int read_auth_container(struct spl_image_info *spl_image, if (length > CONTAINER_HDR_ALIGNMENT) { size = ALIGN(length, info->bl_len); - sectors = size / info->bl_len; free(container); container = malloc(size); if (!container) return -ENOMEM; - debug("%s: container: %p sector: %lu sectors: %u\n", - __func__, container, sector, sectors); - if (info->read(info, sector, sectors, container) != - sectors) { + debug("%s: container: %p offset: %lu size: %u\n", + __func__, container, offset, size); + if (info->read(info, offset, size, container) != size) { ret = -EIO; goto end; } @@ -129,7 +122,7 @@ static int read_auth_container(struct spl_image_info *spl_image, for (i = 0; i < container->num_images; i++) { struct boot_img_t *image = read_auth_image(spl_image, info, container, i, - sector); + offset); if (!image) { ret = -EINVAL; @@ -154,7 +147,7 @@ end: } int spl_load_imx_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector) + struct spl_load_info *info, ulong offset) { - return read_auth_container(spl_image, info, sector); + return read_auth_container(spl_image, info, offset); } diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 3d7551a7dae..9f41ea648ce 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -62,12 +62,14 @@ static int mmc_load_legacy(struct spl_image_info *spl_image, return 0; } -static ulong h_spl_load_read(struct spl_load_info *load, ulong sector, - ulong count, void *buf) +static ulong h_spl_load_read(struct spl_load_info *load, ulong off, + ulong size, void *buf) { - struct mmc *mmc = load->priv; + struct blk_desc *bd = load->priv; + lbaint_t sector = off >> bd->log2blksz; + lbaint_t count = size >> bd->log2blksz; - return blk_dread(mmc_get_blk_desc(mmc), sector, count, buf); + return blk_dread(bd, sector, count, buf) << bd->log2blksz; } static __maybe_unused unsigned long spl_mmc_raw_uboot_offset(int part) @@ -105,21 +107,23 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.priv = mmc; + load.priv = bd; load.filename = NULL; - load.bl_len = mmc->read_bl_len; + load.bl_len = bd->blksz; load.read = h_spl_load_read; - ret = spl_load_simple_fit(spl_image, &load, sector, header); + ret = spl_load_simple_fit(spl_image, &load, + sector << bd->log2blksz, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; - load.priv = mmc; + load.priv = bd; load.filename = NULL; - load.bl_len = mmc->read_bl_len; + load.bl_len = bd->blksz; load.read = h_spl_load_read; - ret = spl_load_imx_container(spl_image, &load, sector); + ret = spl_load_imx_container(spl_image, &load, + sector << bd->log2blksz); } else { ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header); } diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9a5a5ffa04a..1fcc89fa660 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -49,14 +49,12 @@ static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs, ulong sector; sector = *(int *)load->priv; - offs *= load->bl_len; - size *= load->bl_len; offs = sector + nand_spl_adjust_offset(sector, offs - sector); err = nand_spl_load_image(offs, size, dst); if (err) return 0; - return size / load->bl_len; + return size; } static ulong spl_nand_legacy_read(struct spl_load_info *load, ulong offs, @@ -95,7 +93,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.filename = NULL; load.bl_len = bl_len; load.read = spl_nand_fit_read; - return spl_load_simple_fit(spl_image, &load, offset / bl_len, header); + return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; @@ -104,7 +102,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, load.filename = NULL; load.bl_len = bl_len; load.read = spl_nand_fit_read; - return spl_load_imx_container(spl_image, &load, offset / bl_len); + return spl_load_imx_container(spl_image, &load, offset); } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) && image_get_magic(header) == IH_MAGIC) { struct spl_load_info load; diff --git a/include/spl.h b/include/spl.h index 951e136b9ea..5a355e0a1e0 100644 --- a/include/spl.h +++ b/include/spl.h @@ -297,10 +297,12 @@ struct spl_load_info { * read() - Read from device * * @load: Information about the load state - * @sector: Sector number to read from (each @load->bl_len bytes) - * @count: Number of sectors to read + * @offset: Offset to read from in bytes. This must be a multiple of + * @load->bl_len. + * @count: Number of bytes to read. This must be a multiple of + * @load->bl_len. * @buf: Buffer to read into - * @return number of sectors read, 0 on error + * @return number of bytes read, 0 on error */ ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, void *buf); @@ -368,7 +370,8 @@ void *spl_load_simple_fit_fix_load(const void *fit); * spl_load_simple_fit() - Loads a fit image from a device. * @spl_image: Image description to set up * @info: Structure containing the information required to load data. - * @sector: Sector number where FIT image is located in the device + * @offset: Offset where FIT image is located in the device. Must be aligned + * to the device's bl_len. * @fdt: Pointer to the copied FIT header. * * Reads the FIT image @sector in the device. Loads u-boot image to @@ -376,7 +379,7 @@ void *spl_load_simple_fit_fix_load(const void *fit); * Returns 0 on success. */ int spl_load_simple_fit(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector, void *fdt); + struct spl_load_info *info, ulong offset, void *fdt); #define SPL_COPY_PAYLOAD_ONLY 1 #define SPL_FIT_FOUND 2 @@ -402,13 +405,14 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, * spl_load_imx_container() - Loads a imx container image from a device. * @spl_image: Image description to set up * @info: Structure containing the information required to load data. - * @sector: Sector number where container image is located in the device + * @sector: Offset where container image is located in the device. Must be + * aligned to the device block size. * * Reads the container image @sector in the device. Loads u-boot image to * specified load address. */ int spl_load_imx_container(struct spl_image_info *spl_image, - struct spl_load_info *info, ulong sector); + struct spl_load_info *info, ulong offset); /* SPL common functions */ void preloader_console_init(void); diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 49edf152d78..794cfad4e70 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -16,14 +16,13 @@ struct text_ctx { int fd; }; -static ulong read_fit_image(struct spl_load_info *load, ulong sector, - ulong count, void *buf) +static ulong read_fit_image(struct spl_load_info *load, ulong offset, + ulong size, void *buf) { struct text_ctx *text_ctx = load->priv; - off_t offset, ret; + off_t ret; ssize_t res; - offset = sector * load->bl_len; ret = os_lseek(text_ctx->fd, offset, OS_SEEK_SET); if (ret != offset) { printf("Failed to seek to %zx, got %zx (errno=%d)\n", offset, @@ -31,14 +30,14 @@ static ulong read_fit_image(struct spl_load_info *load, ulong sector, return 0; } - res = os_read(text_ctx->fd, buf, count * load->bl_len); + res = os_read(text_ctx->fd, buf, size); if (res == -1) { printf("Failed to read %lx bytes, got %ld (errno=%d)\n", - count * load->bl_len, res, errno); + size, res, errno); return 0; } - return count; + return size; } static int spl_test_load(struct unit_test_state *uts) -- cgit v1.3.1 From afdd2d98c29c443f348fd88198e59b78d50f4e2c Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:42 -0500 Subject: spl: Remove filename from spl_load_info For filesystems, filename serves the same purpose as priv. However, spl_load_fit_image also uses it to determine whether to use a DMA-aligned buffer. This is beneficial for FAT, which uses a bounce-buffer if the destination is not DMA-aligned. However, this is unnecessary now that filesystems set bl_len to ARCH_DMA_MINALIGN instead. With this done, we can remove filename entirely. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- arch/arm/mach-sunxi/spl_spi_sunxi.c | 1 - common/spl/spl_blk_fs.c | 7 ++++--- common/spl/spl_fat.c | 4 ++-- common/spl/spl_mmc.c | 2 -- common/spl/spl_nand.c | 3 --- common/spl/spl_semihosting.c | 1 - common/spl/spl_spi.c | 2 -- common/spl/spl_ymodem.c | 1 - include/spl.h | 2 -- test/image/spl_load_os.c | 1 - 10 files changed, 6 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 896aba69c32..5e7fba0c8e4 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -354,7 +354,6 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT image\n"); - load.filename = NULL; load.bl_len = 1; load.read = spi_load_read; ret = spl_load_simple_fit(spl_image, &load, diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index c105c55877a..4975ce4d6ec 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -14,6 +14,7 @@ struct blk_dev { const char *ifname; + const char *filename; char dev_part_str[8]; }; @@ -31,11 +32,11 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, return ret; } - ret = fs_read(load->filename, virt_to_phys(buf), file_offset, size, + ret = fs_read(dev->filename, virt_to_phys(buf), file_offset, size, &actlen); if (ret < 0) { printf("spl: error reading image %s. Err - %d\n", - load->filename, ret); + dev->filename, ret); return ret; } @@ -87,8 +88,8 @@ int spl_blk_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = spl_fit_read; load.bl_len = ARCH_DMA_MINALIGN; - load.filename = (void *)filename; load.priv = &dev; + dev.filename = filename; return spl_load_simple_fit(spl_image, &load, 0, header); } diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index 5b723456478..8a2c4e3af49 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -51,7 +51,7 @@ static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, { loff_t actread; int ret; - char *filename = (char *)load->filename; + char *filename = load->priv; ret = fat_read_file(filename, buf, file_offset, size, &actread); if (ret) @@ -98,7 +98,7 @@ int spl_load_image_fat(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = spl_fit_read; load.bl_len = ARCH_DMA_MINALIGN; - load.filename = (void *)filename; + load.priv = (void *)filename; return spl_load_simple_fit(spl_image, &load, 0, header); } else { diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 9f41ea648ce..8c4ffe743d5 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -108,7 +108,6 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = bd; - load.filename = NULL; load.bl_len = bd->blksz; load.read = h_spl_load_read; ret = spl_load_simple_fit(spl_image, &load, @@ -118,7 +117,6 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = bd; - load.filename = NULL; load.bl_len = bd->blksz; load.read = h_spl_load_read; diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 1fcc89fa660..45d7c5f6cfb 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -90,7 +90,6 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = &offset; - load.filename = NULL; load.bl_len = bl_len; load.read = spl_nand_fit_read; return spl_load_simple_fit(spl_image, &load, offset, header); @@ -99,7 +98,6 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = &offset; - load.filename = NULL; load.bl_len = bl_len; load.read = spl_nand_fit_read; return spl_load_imx_container(spl_image, &load, offset); @@ -108,7 +106,6 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found legacy image\n"); - load.filename = NULL; load.bl_len = IS_ENABLED(CONFIG_SPL_LZMA) ? bl_len : 1; load.read = spl_nand_legacy_read; diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 8f11c29913f..24a3d9fd1c9 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -69,7 +69,6 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = smh_fit_read; load.bl_len = 1; - load.filename = NULL; load.priv = &fd; ret = spl_load_simple_fit(spl_image, &load, 0, header); diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index af7a28e7c25..373caea322a 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -152,7 +152,6 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = flash; - load.filename = NULL; load.bl_len = 1; load.read = spl_spi_fit_read; err = spl_load_simple_fit(spl_image, &load, @@ -163,7 +162,6 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = flash; - load.filename = NULL; load.bl_len = 1; load.read = spl_spi_fit_read; diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 8616cb3e915..3f92b9b0036 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -135,7 +135,6 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = (void *)&info; - load.filename = NULL; load.bl_len = 1; info.buf = buf; info.image_read = BUF_SIZE; diff --git a/include/spl.h b/include/spl.h index 5a355e0a1e0..fec656d3018 100644 --- a/include/spl.h +++ b/include/spl.h @@ -287,12 +287,10 @@ static inline void *spl_image_fdt_addr(struct spl_image_info *info) * * @priv: Private data for the device * @bl_len: Block length for reading in bytes - * @filename: Name of the fit image file. * @read: Function to call to read from the device */ struct spl_load_info { void *priv; - const char *filename; /** * read() - Read from device * diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index 794cfad4e70..f46df907c63 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -57,7 +57,6 @@ static int spl_test_load(struct unit_test_state *uts) ret = sandbox_find_next_phase(fname, sizeof(fname), true); if (ret) ut_assertf(0, "%s not found, error %d\n", fname, ret); - load.filename = fname; header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); -- cgit v1.3.1 From 5271e359a46cc6a60d0048576326e2fa1527f231 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:43 -0500 Subject: spl: Only support bl_len when we have to Aligning addresses and sizes causes overhead which is unnecessary when we are not loading from block devices. Remove bl_len when it is not needed. For example, on iot2050 we save 144 bytes with this patch (once the rest of this series is applied): add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-144 (-144) Function old new delta spl_load_simple_fit 920 904 -16 load_simple_fit 496 444 -52 spl_spi_load_image 384 308 -76 Total: Before=87431, After=87287, chg -0.16% We use panic() instead of BUILD_BUG_ON in spl_set_bl_len because we still need to be able to compile it for things like mmc_load_image_raw_sector, even if that function will not be used. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- arch/arm/mach-imx/spl_imx_romapi.c | 8 ++++---- arch/arm/mach-sunxi/spl_spi_sunxi.c | 2 +- common/spl/Kconfig | 14 +++++++++++++- common/spl/spl_blk_fs.c | 2 +- common/spl/spl_fat.c | 2 +- common/spl/spl_fit.c | 6 +++--- common/spl/spl_imx_container.c | 10 +++++----- common/spl/spl_legacy.c | 4 ++-- common/spl/spl_mmc.c | 4 ++-- common/spl/spl_nand.c | 6 +++--- common/spl/spl_net.c | 2 +- common/spl/spl_nor.c | 8 ++++---- common/spl/spl_ram.c | 2 +- common/spl/spl_semihosting.c | 2 +- common/spl/spl_spi.c | 4 ++-- common/spl/spl_ymodem.c | 2 +- drivers/usb/gadget/f_sdp.c | 4 ++-- include/spl.h | 25 +++++++++++++++++++++++++ test/image/Kconfig | 1 + test/image/spl_load.c | 9 ++++----- test/image/spl_load_os.c | 2 +- 21 files changed, 78 insertions(+), 41 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index d7f6cb4b5ba..9f0968cdf71 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -101,7 +101,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && @@ -109,7 +109,7 @@ static int spl_romapi_load_image_seekable(struct spl_image_info *spl_image, struct spl_load_info load; memset(&load, 0, sizeof(load)); - load.bl_len = pagesize; + spl_set_bl_len(&load, pagesize); load.read = spl_romapi_read_seekable; ret = spl_load_imx_container(spl_image, &load, offset); @@ -334,7 +334,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, ss.pagesize = pagesize; memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_romapi_read_stream; load.priv = &ss; @@ -358,7 +358,7 @@ static int spl_romapi_load_image_stream(struct spl_image_info *spl_image, printf("ROM download failure %d\n", imagesize); memset(&load, 0, sizeof(load)); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_ram_load_read; if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER)) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 5e7fba0c8e4..267cb0b1aba 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -354,7 +354,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT image\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spi_load_read; ret = spl_load_simple_fit(spl_image, &load, load_offset, header); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index e929f1bbae1..0bc57d5fedb 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -280,8 +280,15 @@ config SPL_BOARD_INIT spl_board_init() from board_init_r(). This function should be provided by the board. +config SPL_LOAD_BLOCK + bool + help + Support loading images from block devices. This adds a bl_len member + to struct spl_load_info. + config SPL_BOOTROM_SUPPORT bool "Support returning to the BOOTROM" + select SPL_LOAD_BLOCK if MACH_IMX help Some platforms (e.g. the Rockchip RK3368) provide support in their ROM for loading the next boot-stage after performing basic setup @@ -482,6 +489,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP44XX || OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED + select SPL_LOAD_BLOCK if SPL_MMC help Use sector number for specifying U-Boot location on MMC/SD in raw mode. @@ -518,6 +526,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" + select SPL_LOAD_BLOCK if SPL_MMC help Use a partition for loading U-Boot when using MMC/SD in raw mode. @@ -678,6 +687,7 @@ config SPL_FS_SQUASHFS config SPL_FS_FAT bool "Support FAT filesystems" select FS_FAT + select SPL_LOAD_BLOCK help Enable support for FAT and VFAT filesystems with SPL. This permits U-Boot (or Linux in Falcon mode) to be loaded from a FAT @@ -877,6 +887,7 @@ config SPL_MUSB_NEW config SPL_NAND_SUPPORT bool "Support NAND flash" + select SPL_LOAD_BLOCK help Enable support for NAND (Negative AND) flash in SPL. NAND flash can be used to allow SPL to load U-Boot from supported devices. @@ -1102,6 +1113,7 @@ config SYS_OS_BASE config SPL_FALCON_BOOT_MMCSD bool "Enable Falcon boot from MMC or SD media" depends on SPL_OS_BOOT && SPL_MMC + select SPL_LOAD_BLOCK help Select this if the Falcon mode OS image mode is on MMC or SD media. @@ -1260,9 +1272,9 @@ config SPL_SATA_RAW_U_BOOT_SECTOR config SPL_NVME bool "NVM Express device support" depends on BLK - select HAVE_BLOCK_DEVICE select FS_LOADER select SPL_BLK_FS + select SPL_LOAD_BLOCK help This option enables support for NVM Express devices. It supports basic functions of NVMe (read/write). diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index 4975ce4d6ec..53b8e1b11b4 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -87,7 +87,7 @@ int spl_blk_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = spl_fit_read; - load.bl_len = ARCH_DMA_MINALIGN; + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); load.priv = &dev; dev.filename = filename; diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index 8a2c4e3af49..a0c34eba48f 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -97,7 +97,7 @@ int spl_load_image_fat(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = spl_fit_read; - load.bl_len = ARCH_DMA_MINALIGN; + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); load.priv = (void *)filename; return spl_load_simple_fit(spl_image, &load, 0, header); diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index 0df4e6d1484..872df0c0fe8 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -171,12 +171,12 @@ static int spl_fit_get_image_node(const struct spl_fit_info *ctx, static int get_aligned_image_offset(struct spl_load_info *info, int offset) { - return ALIGN_DOWN(offset, info->bl_len); + return ALIGN_DOWN(offset, spl_get_bl_len(info)); } static int get_aligned_image_overhead(struct spl_load_info *info, int offset) { - return offset & (info->bl_len - 1); + return offset & (spl_get_bl_len(info) - 1); } static int get_aligned_image_size(struct spl_load_info *info, int data_size, @@ -184,7 +184,7 @@ static int get_aligned_image_size(struct spl_load_info *info, int data_size, { data_size = data_size + get_aligned_image_overhead(info, offset); - return ALIGN(data_size, info->bl_len); + return ALIGN(data_size, spl_get_bl_len(info)); } /** diff --git a/common/spl/spl_imx_container.c b/common/spl/spl_imx_container.c index 7cd674f835f..b4ea9241d68 100644 --- a/common/spl/spl_imx_container.c +++ b/common/spl/spl_imx_container.c @@ -32,13 +32,13 @@ static struct boot_img_t *read_auth_image(struct spl_image_info *spl_image, images = (struct boot_img_t *)((u8 *)container + sizeof(struct container_hdr)); - if (!IS_ALIGNED(images[image_index].offset, info->bl_len)) { + if (!IS_ALIGNED(images[image_index].offset, spl_get_bl_len(info))) { printf("%s: image%d offset not aligned to %u\n", - __func__, image_index, info->bl_len); + __func__, image_index, spl_get_bl_len(info)); return NULL; } - size = ALIGN(images[image_index].size, info->bl_len); + size = ALIGN(images[image_index].size, spl_get_bl_len(info)); offset = images[image_index].offset + container_offset; debug("%s: container: %p offset: %lu size: %lu\n", __func__, @@ -66,7 +66,7 @@ static int read_auth_container(struct spl_image_info *spl_image, u16 length; int i, size, ret = 0; - size = ALIGN(CONTAINER_HDR_ALIGNMENT, info->bl_len); + size = ALIGN(CONTAINER_HDR_ALIGNMENT, spl_get_bl_len(info)); /* * It will not override the ATF code, so safe to use it here, @@ -100,7 +100,7 @@ static int read_auth_container(struct spl_image_info *spl_image, debug("Container length %u\n", length); if (length > CONTAINER_HDR_ALIGNMENT) { - size = ALIGN(length, info->bl_len); + size = ALIGN(length, spl_get_bl_len(info)); free(container); container = malloc(size); diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 9189576b774..75d9d822337 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -139,9 +139,9 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, lzma_len = LZMA_LEN; /* dataptr points to compressed payload */ - dataptr = ALIGN_DOWN(sizeof(*hdr), load->bl_len); + dataptr = ALIGN_DOWN(sizeof(*hdr), spl_get_bl_len(load)); overhead = sizeof(*hdr) - dataptr; - size = ALIGN(spl_image->size + overhead, load->bl_len); + size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load)); dataptr += offset; debug("LZMA: Decompressing %08lx to %08lx\n", diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 8c4ffe743d5..91272c03d3f 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -108,7 +108,7 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = bd; - load.bl_len = bd->blksz; + spl_set_bl_len(&load, bd->blksz); load.read = h_spl_load_read; ret = spl_load_simple_fit(spl_image, &load, sector << bd->log2blksz, header); @@ -117,7 +117,7 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = bd; - load.bl_len = bd->blksz; + spl_set_bl_len(&load, bd->blksz); load.read = h_spl_load_read; ret = spl_load_imx_container(spl_image, &load, diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 45d7c5f6cfb..281211b7f24 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -90,7 +90,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = &offset; - load.bl_len = bl_len; + spl_set_bl_len(&load, bl_len); load.read = spl_nand_fit_read; return spl_load_simple_fit(spl_image, &load, offset, header); } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && @@ -98,7 +98,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = &offset; - load.bl_len = bl_len; + spl_set_bl_len(&load, bl_len); load.read = spl_nand_fit_read; return spl_load_imx_container(spl_image, &load, offset); } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) && @@ -106,7 +106,7 @@ static int spl_nand_load_element(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found legacy image\n"); - load.bl_len = IS_ENABLED(CONFIG_SPL_LZMA) ? bl_len : 1; + spl_set_bl_len(&load, IS_ENABLED(CONFIG_SPL_LZMA) ? bl_len : 1); load.read = spl_nand_legacy_read; return spl_load_legacy_img(spl_image, bootdev, &load, offset, header); diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index f01d4df8bc6..47994e28165 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -54,7 +54,7 @@ static int spl_net_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_net_load_read; rv = spl_load_simple_fit(spl_image, &load, 0, header); } else { diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 236b0718283..aad230db4d3 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -49,7 +49,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, int ret; debug("Found FIT\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_nor_load_read; ret = spl_load_simple_fit(spl_image, &load, @@ -97,7 +97,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { debug("Found FIT format U-Boot\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_nor_load_read; return spl_load_simple_fit(spl_image, &load, spl_nor_get_uboot_base(), @@ -106,7 +106,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, #endif if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_nor_load_read; return spl_load_imx_container(spl_image, &load, spl_nor_get_uboot_base()); @@ -114,7 +114,7 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, /* Legacy image handling */ if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) { - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_nor_load_read; return spl_load_legacy_img(spl_image, bootdev, &load, spl_nor_get_uboot_base(), diff --git a/common/spl/spl_ram.c b/common/spl/spl_ram.c index 4158ed1c32d..8aeda237be1 100644 --- a/common/spl/spl_ram.c +++ b/common/spl/spl_ram.c @@ -70,7 +70,7 @@ static int spl_ram_load_image(struct spl_image_info *spl_image, struct spl_load_info load; debug("Found FIT\n"); - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_ram_load_read; ret = spl_load_simple_fit(spl_image, &load, 0, header); } else { diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 24a3d9fd1c9..9b0610b8fc8 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -68,7 +68,7 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.read = smh_fit_read; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.priv = &fd; ret = spl_load_simple_fit(spl_image, &load, 0, header); diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 373caea322a..3e08ac7c1a2 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -152,7 +152,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = flash; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_spi_fit_read; err = spl_load_simple_fit(spl_image, &load, payload_offs, @@ -162,7 +162,7 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = flash; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = spl_spi_fit_read; err = spl_load_imx_container(spl_image, &load, diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 3f92b9b0036..1faaa2c938d 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -135,7 +135,7 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = (void *)&info; - load.bl_len = 1; + spl_set_bl_len(&load, 1); info.buf = buf; info.image_read = BUF_SIZE; load.read = ymodem_read_fit; diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index 1b16b7eb452..ca2760c00d0 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -845,7 +845,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, debug("Found FIT\n"); load.priv = header; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = sdp_load_read; spl_load_simple_fit(spl_image, &load, 0, header); @@ -858,7 +858,7 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, struct spl_load_info load; load.priv = header; - load.bl_len = 1; + spl_set_bl_len(&load, 1); load.read = sdp_load_read; spl_load_imx_container(spl_image, &load, 0); return SDP_EXIT; diff --git a/include/spl.h b/include/spl.h index fec656d3018..03c5c5c66b4 100644 --- a/include/spl.h +++ b/include/spl.h @@ -304,9 +304,34 @@ struct spl_load_info { */ ulong (*read)(struct spl_load_info *load, ulong sector, ulong count, void *buf); +#if IS_ENABLED(CONFIG_SPL_LOAD_BLOCK) int bl_len; }; +static inline int spl_get_bl_len(struct spl_load_info *info) +{ + return info->bl_len; +} + +static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +{ + info->bl_len = bl_len; +} +#else +}; + +static inline int spl_get_bl_len(struct spl_load_info *info) +{ + return 1; +} + +static inline void spl_set_bl_len(struct spl_load_info *info, int bl_len) +{ + if (bl_len != 1) + panic("CONFIG_SPL_LOAD_BLOCK not enabled"); +} +#endif + /* * We need to know the position of U-Boot in memory so we can jump to it. We * allow any U-Boot binary to be used (u-boot.bin, u-boot-nodtb.bin, diff --git a/test/image/Kconfig b/test/image/Kconfig index 6f0bb81f835..45b6e8c52e6 100644 --- a/test/image/Kconfig +++ b/test/image/Kconfig @@ -52,6 +52,7 @@ config SPL_UT_LOAD_SPI config SPL_UT_LOAD_OS bool "Test loading from the host OS" depends on SANDBOX && SPL_LOAD_FIT + select SPL_LOAD_BLOCK default y help Smoke test to ensure that loading U-boot works in sandbox. diff --git a/test/image/spl_load.c b/test/image/spl_load.c index ab4c14d6491..35ceed67756 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -342,12 +342,11 @@ static int spl_test_image(struct unit_test_state *uts, const char *test_name, if (check_image_info(uts, &info_write, &info_read)) return CMD_RET_FAILURE; } else { - struct spl_load_info load = { - .bl_len = 1, - .priv = img, - .read = spl_test_read, - }; + struct spl_load_info load; + spl_set_bl_len(&load, 1); + load.priv = img; + load.read = spl_test_read; if (type == IMX8) ut_assertok(spl_load_imx_container(&info_read, &load, 0)); diff --git a/test/image/spl_load_os.c b/test/image/spl_load_os.c index f46df907c63..26228a8a4a9 100644 --- a/test/image/spl_load_os.c +++ b/test/image/spl_load_os.c @@ -51,7 +51,7 @@ static int spl_test_load(struct unit_test_state *uts) int fd; memset(&load, '\0', sizeof(load)); - load.bl_len = 512; + spl_set_bl_len(&load, 512); load.read = read_fit_image; ret = sandbox_find_next_phase(fname, sizeof(fname), true); -- cgit v1.3.1 From efe92cd2f9eff3699d4a6b5e1c3d261c4b88b342 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:45 -0500 Subject: spl: legacy: Split off LZMA decompression into its own function To allow for easier reuse of this functionality, split it off into its own function. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_legacy.c | 75 ++++++++++++++++++++++++++----------------------- include/spl.h | 13 +++++++++ 2 files changed, 53 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index 75d9d822337..a561939b4f0 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -82,6 +82,43 @@ int spl_parse_legacy_header(struct spl_image_info *spl_image, return 0; } +int spl_load_legacy_lzma(struct spl_image_info *spl_image, + struct spl_load_info *load, ulong offset) +{ + SizeT lzma_len = LZMA_LEN; + void *src; + ulong dataptr, overhead, size; + int ret; + + /* dataptr points to compressed payload */ + dataptr = ALIGN_DOWN(sizeof(struct legacy_img_hdr), + spl_get_bl_len(load)); + overhead = sizeof(struct legacy_img_hdr) - dataptr; + size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load)); + dataptr += offset; + + debug("LZMA: Decompressing %08lx to %08lx\n", + dataptr, spl_image->load_addr); + src = malloc(size); + if (!src) { + printf("Unable to allocate %d bytes for LZMA\n", + spl_image->size); + return -ENOMEM; + } + + load->read(load, dataptr, size, src); + ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr, + spl_image->size), &lzma_len, + src + overhead, spl_image->size); + if (ret) { + printf("LZMA decompression error: %d\n", ret); + return ret; + } + + spl_image->size = lzma_len; + return 0; +} + /* * This function is added explicitly to avoid code size increase, when * no compression method is enabled. The compiler will optimize the @@ -101,8 +138,6 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, struct spl_load_info *load, ulong offset, struct legacy_img_hdr *hdr) { - __maybe_unused SizeT lzma_len; - __maybe_unused void *src; ulong dataptr; int ret; @@ -133,39 +168,9 @@ int spl_load_legacy_img(struct spl_image_info *spl_image, map_sysmem(spl_image->load_addr, spl_image->size)); break; - case IH_COMP_LZMA: { - ulong overhead, size; - - lzma_len = LZMA_LEN; - - /* dataptr points to compressed payload */ - dataptr = ALIGN_DOWN(sizeof(*hdr), spl_get_bl_len(load)); - overhead = sizeof(*hdr) - dataptr; - size = ALIGN(spl_image->size + overhead, spl_get_bl_len(load)); - dataptr += offset; - - debug("LZMA: Decompressing %08lx to %08lx\n", - dataptr, spl_image->load_addr); - src = malloc(size); - if (!src) { - printf("Unable to allocate %d bytes for LZMA\n", - spl_image->size); - return -ENOMEM; - } - - load->read(load, dataptr, size, src); - ret = lzmaBuffToBuffDecompress(map_sysmem(spl_image->load_addr, - spl_image->size), - &lzma_len, src + overhead, - spl_image->size); - if (ret) { - printf("LZMA decompression error: %d\n", ret); - return ret; - } - - spl_image->size = lzma_len; - break; - } + case IH_COMP_LZMA: + return spl_load_legacy_lzma(spl_image, load, offset); + default: debug("Compression method %s is not supported\n", genimg_get_comp_short_name(image_get_comp(hdr))); diff --git a/include/spl.h b/include/spl.h index 03c5c5c66b4..09521889014 100644 --- a/include/spl.h +++ b/include/spl.h @@ -407,6 +407,19 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, #define SPL_COPY_PAYLOAD_ONLY 1 #define SPL_FIT_FOUND 2 +/** + * spl_load_legacy_lzma() - Load an LZMA-compressed legacy image + * @spl_image: Image description (already set up) + * @load: Structure containing the information required to load data. + * @offset: Pointer to image + * + * Load/decompress an LZMA-compressed legacy image from the device. + * + * Return: 0 on success, or a negative error on failure + */ +int spl_load_legacy_lzma(struct spl_image_info *spl_image, + struct spl_load_info *load, ulong offset); + /** * spl_load_legacy_img() - Loads a legacy image from a device. * @spl_image: Image description to set up -- cgit v1.3.1 From 5b3debc61ea6b6ce3e9125331381c55403d82dce Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:46 -0500 Subject: test: spl: Support testing LEGACY_LZMA filesystem images These will soon be supported, so we need to be able to test it. Export the lzma data and generally use the same process in spl_test_mmc_fs as do_spl_test_load. If we end up needing this in third place in the future, it would probably be good to refactor things out. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- include/test/spl.h | 4 ++++ test/image/spl_load.c | 4 +++- test/image/spl_load_fs.c | 23 ++++++++++++++++++----- 3 files changed, 25 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/test/spl.h b/include/test/spl.h index c1f64658502..a2a5f33e328 100644 --- a/include/test/spl.h +++ b/include/test/spl.h @@ -81,6 +81,10 @@ size_t create_image(void *dst, enum spl_test_image type, int check_image_info(struct unit_test_state *uts, struct spl_image_info *info1, struct spl_image_info *info2); +/* Some compressed data and it size */ +extern const char lzma_compressed[]; +extern const size_t lzma_compressed_size; + /** * typedef write_image_t - Callback for writing an image * @uts: Current unit test state diff --git a/test/image/spl_load.c b/test/image/spl_load.c index 35ceed67756..e1036eff28c 100644 --- a/test/image/spl_load.c +++ b/test/image/spl_load.c @@ -374,7 +374,7 @@ SPL_IMG_TEST(spl_test_image, FIT_EXTERNAL, 0); * LZMA is too complex to generate on the fly, so let's use some data I put in * the oven^H^H^H^H compressed earlier */ -static const char lzma_compressed[] = { +const char lzma_compressed[] = { 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x02, 0x05, 0x55, 0x4e, 0x82, 0xbc, 0xc2, 0x42, 0xf6, 0x88, 0x6c, 0x99, 0xd6, 0x82, 0x48, 0xa6, 0x06, 0x67, 0xf8, 0x46, 0x7c, 0xe9, @@ -610,6 +610,8 @@ static const char lzma_compressed[] = { 0x1e, 0xff, 0xff, 0x80, 0x8e, 0x00, 0x00 }; +const size_t lzma_compressed_size = sizeof(lzma_compressed); + int do_spl_test_load(struct unit_test_state *uts, const char *test_name, enum spl_test_image type, struct spl_image_loader *loader, int (*write_image)(struct unit_test_state *, void *, size_t)) diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 297ab08a820..59d0244d44b 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -320,10 +320,11 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; struct blk_desc *dev_desc; size_t fs_size, fs_data, img_size, img_data, - data_size = SPL_TEST_DATA_SIZE; + plain_size = SPL_TEST_DATA_SIZE; struct spl_image_info info_write = { .name = test_name, - .size = data_size, + .size = type == LEGACY_LZMA ? lzma_compressed_size : + plain_size, }, info_read = { }; struct disk_partition part = { .start = 1, @@ -335,7 +336,7 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, .boot_device = loader->boot_device, }; void *fs; - char *data; + char *data, *plain; img_size = create_image(NULL, type, &info_write, &img_data); ut_assert(img_size); @@ -345,7 +346,15 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, ut_assertnonnull(fs); data = fs + fs_data + img_data; - generate_data(data, data_size, test_name); + if (type == LEGACY_LZMA) { + plain = malloc(plain_size); + ut_assertnonnull(plain); + generate_data(plain, plain_size, "lzma"); + memcpy(data, lzma_compressed, lzma_compressed_size); + } else { + plain = data; + generate_data(plain, plain_size, test_name); + } ut_asserteq(img_size, create_image(fs + fs_data, type, &info_write, NULL)); ut_asserteq(fs_size, create_fs(fs, img_size, filename, NULL)); @@ -366,8 +375,12 @@ static int spl_test_mmc_fs(struct unit_test_state *uts, const char *test_name, ut_assertok(loader->load_image(&info_read, &bootdev)); if (check_image_info(uts, &info_write, &info_read)) return CMD_RET_FAILURE; - ut_asserteq_mem(data, phys_to_virt(info_write.load_addr), data_size); + if (type == LEGACY_LZMA) + ut_asserteq(plain_size, info_read.size); + ut_asserteq_mem(plain, phys_to_virt(info_write.load_addr), plain_size); + if (type == LEGACY_LZMA) + free(plain); free(fs); return 0; } -- cgit v1.3.1 From 775074165d97e03277eaf345d8c472e48659f5af Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:47 -0500 Subject: spl: Add generic spl_load function Implementers of SPL_LOAD_IMAGE_METHOD have to correctly determine what type of image is being loaded and then call the appropriate image load function correctly. This is tricky, because some image load functions expect the whole image to already be loaded (CONFIG_SPL_LOAD_FIT_FULL), some will load the image automatically using spl_load_info.read() (CONFIG_SPL_LOAD_FIT/CONFIG_SPL_LOAD_IMX_CONTAINER), and some just parse the header and expect the caller to do the actual loading afterwards (legacy/raw images). Load methods often only support a subset of the above methods, meaning that not all image types can be used with all load methods. Further, the code to invoke these functions is duplicated between different load functions. To address this problem, this commit introduces a "spl_load" function. It aims to handle image detection and correct invocation of each of the parse/load functions. Although this function generally results in a size reduction with several users, it tends to bloat boards with only a single user. This is generally because programmers open-coding the contents of this function can make optimizations based on the specific loader. For example, NOR flash is memory-mapped, so it never bothers calling load->read. The compiler can't really make these optimizations across translation units. LTO solves this, but it is only available on some arches. To address this, perform "pseudo-LTO" by inlining spl_load when there are one or fewer users. At the moment, there are no users, so define SPL_LOAD_USERS to be 0. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl.c | 10 ++++ include/spl_load.h | 135 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 include/spl_load.h (limited to 'include') diff --git a/common/spl/spl.c b/common/spl/spl.c index 7ce38ce46d4..3ce5bfeec8b 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -352,6 +353,15 @@ int spl_parse_image_header(struct spl_image_info *spl_image, return 0; } +#if SPL_LOAD_USERS > 1 +int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, struct spl_load_info *info, + size_t size, size_t offset) +{ + return _spl_load(spl_image, bootdev, info, size, offset); +} +#endif + __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) { typedef void __noreturn (*image_entry_noargs_t)(void); diff --git a/include/spl_load.h b/include/spl_load.h new file mode 100644 index 00000000000..406f8b577b2 --- /dev/null +++ b/include/spl_load.h @@ -0,0 +1,135 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) Sean Anderson + */ +#ifndef _SPL_LOAD_H_ +#define _SPL_LOAD_H_ + +#include +#include +#include +#include + +static inline int _spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, + struct spl_load_info *info, size_t size, + size_t offset) +{ + struct legacy_img_hdr *header = + spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + ulong base_offset, image_offset, overhead; + int read, ret; + + read = info->read(info, offset, ALIGN(sizeof(*header), + spl_get_bl_len(info)), header); + if (read < sizeof(*header)) + return -EIO; + + if (image_get_magic(header) == FDT_MAGIC) { + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + void *buf; + + /* + * In order to support verifying images in the FIT, we + * need to load the whole FIT into memory. Try and + * guess how much we need to load by using the total + * size. This will fail for FITs with external data, + * but there's not much we can do about that. + */ + if (!size) + size = round_up(fdt_totalsize(header), 4); + buf = map_sysmem(CONFIG_SYS_LOAD_ADDR, size); + read = info->read(info, offset, + ALIGN(size, spl_get_bl_len(info)), + buf); + if (read < size) + return -EIO; + + return spl_parse_image_header(spl_image, bootdev, buf); + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT)) + return spl_load_simple_fit(spl_image, info, offset, + header); + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && + valid_container_hdr((void *)header)) + return spl_load_imx_container(spl_image, info, offset); + + if (IS_ENABLED(CONFIG_SPL_LZMA) && + image_get_magic(header) == IH_MAGIC && + image_get_comp(header) == IH_COMP_LZMA) { + spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) + return ret; + + return spl_load_legacy_lzma(spl_image, info, offset); + } + + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) + return ret; + + base_offset = spl_image->offset; + /* Only NOR sets this flag. */ + if (IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) && + spl_image->flags & SPL_COPY_PAYLOAD_ONLY) + base_offset += sizeof(*header); + image_offset = ALIGN_DOWN(base_offset, spl_get_bl_len(info)); + overhead = base_offset - image_offset; + size = ALIGN(spl_image->size + overhead, spl_get_bl_len(info)); + + read = info->read(info, offset + image_offset, size, + map_sysmem(spl_image->load_addr - overhead, size)); + return read < spl_image->size ? -EIO : 0; +} + +/* + * Although spl_load results in size reduction for callers, this is generally + * not enough to counteract the bloat if there is only one caller. The core + * problem is that the compiler can't optimize across translation units. The + * general solution to this is CONFIG_LTO, but that is not available on all + * architectures. Perform a pseudo-LTO just for this function by declaring it + * inline if there is one caller, and extern otherwise. + */ +#define SPL_LOAD_USERS \ + 0 + +#if SPL_LOAD_USERS > 1 +/** + * spl_load() - Parse a header and load the image + * @spl_image: Image data which will be filled in by this function + * @bootdev: The device to load from + * @info: Describes how to load additional information from @bootdev. At the + * minimum, read() and bl_len must be populated. + * @size: The size of the image, in bytes, if it is known in advance. Some boot + * devices (such as filesystems) know how big an image is before parsing + * the header. If 0, then the size will be determined from the header. + * @offset: The offset from the start of @bootdev, in bytes. This should have + * the offset @header was loaded from. It will be added to any offsets + * passed to @info->read(). + * + * This function determines the image type (FIT, legacy, i.MX, raw, etc), calls + * the appropriate parsing function, determines the load address, and the loads + * the image from storage. It is designed to replace ad-hoc image loading which + * may not support all image types (especially when config options are + * involved). + * + * Return: 0 on success, or a negative error on failure + */ +int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, struct spl_load_info *info, + size_t size, size_t offset); +#else +static inline int spl_load(struct spl_image_info *spl_image, + const struct spl_boot_device *bootdev, + struct spl_load_info *info, size_t size, + size_t offset) +{ + return _spl_load(spl_image, bootdev, info, size, offset); +} +#endif + +#endif /* _SPL_LOAD_H_ */ -- cgit v1.3.1 From b8ed72256748119d392c63c6fa8b1f8bb156fd38 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:48 -0500 Subject: spl: Convert ext to use spl_load This converts the ext load method to use spl_load. As a consequence, it also adds support for FIT and IMX images. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_ext.c | 36 ++++++++++++++++++------------------ include/spl_load.h | 1 + test/image/spl_load_fs.c | 9 ++++++--- 3 files changed, 25 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index af836ca15b8..d280b69c387 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -2,25 +2,35 @@ #include #include -#include #include #include +#include #include #include #include #include +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + int ret; + loff_t actlen; + + ret = ext4fs_read(buf, file_offset, size, &actlen); + if (ret) + return ret; + return actlen; +} + int spl_load_image_ext(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition, const char *filename) { s32 err; - struct legacy_img_hdr *header; - loff_t filelen, actlen; + loff_t filelen; struct disk_partition part_info = {}; - - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + struct spl_load_info load; if (part_get_info(block_dev, partition, &part_info)) { printf("spl: no partition table found\n"); @@ -42,20 +52,10 @@ int spl_load_image_ext(struct spl_image_info *spl_image, puts("spl: ext4fs_open failed\n"); goto end; } - err = ext4fs_read((char *)header, 0, sizeof(struct legacy_img_hdr), &actlen); - if (err < 0) { - puts("spl: ext4fs_read failed\n"); - goto end; - } - - err = spl_parse_image_header(spl_image, bootdev, header); - if (err < 0) { - puts("spl: ext: failed to parse image header\n"); - goto end; - } - err = ext4fs_read(map_sysmem(spl_image->load_addr, filelen), 0, filelen, - &actlen); + spl_set_bl_len(&load, 1); + load.read = spl_fit_read; + err = spl_load(spl_image, bootdev, &load, filelen, 0); end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT diff --git a/include/spl_load.h b/include/spl_load.h index 406f8b577b2..65aa6bb4493 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -95,6 +95,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, * inline if there is one caller, and extern otherwise. */ #define SPL_LOAD_USERS \ + IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 59d0244d44b..01559e98c4f 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -422,20 +422,23 @@ static int spl_test_mmc(struct unit_test_state *uts, const char *test_name, spl_mmc_clear_cache(); spl_fat_force_reregister(); - if (type == LEGACY && - spl_test_mmc_fs(uts, test_name, type, create_ext2, false)) + if (spl_test_mmc_fs(uts, test_name, type, create_ext2, false)) return CMD_RET_FAILURE; - if (type != IMX8 && + if (type != IMX8 && type != LEGACY_LZMA && spl_test_mmc_fs(uts, test_name, type, create_fat, false)) return CMD_RET_FAILURE; + if (type == LEGACY_LZMA) + return 0; + return do_spl_test_load(uts, test_name, type, SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_MMC1, spl_mmc_load_image), spl_test_mmc_write_image); } SPL_IMG_TEST(spl_test_mmc, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_mmc, LEGACY_LZMA, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, FIT_EXTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_mmc, FIT_INTERNAL, DM_FLAGS); -- cgit v1.3.1 From 682184e9b9a6f67b108209651ad2ce90aae9ec9d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:49 -0500 Subject: spl: Convert fat to spl_load This converts the fat loader to use spl_load. Some platforms are very tight on space, so we take care to only include the code we really need. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_fat.c | 56 ++++++++++++++++-------------------------------- include/spl_load.h | 1 + test/image/spl_load_fs.c | 3 +-- 3 files changed, 20 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/common/spl/spl_fat.c b/common/spl/spl_fat.c index a0c34eba48f..569f2b32928 100644 --- a/common/spl/spl_fat.c +++ b/common/spl/spl_fat.c @@ -11,8 +11,8 @@ #include #include #include -#include #include +#include #include #include #include @@ -66,58 +66,38 @@ int spl_load_image_fat(struct spl_image_info *spl_image, const char *filename) { int err; - struct legacy_img_hdr *header; + loff_t size; + struct spl_load_info load; err = spl_register_fat_device(block_dev, partition); if (err) goto end; - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); - - err = file_fat_read(filename, header, sizeof(struct legacy_img_hdr)); - if (err <= 0) - goto end; - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) && - image_get_magic(header) == FDT_MAGIC) { - err = file_fat_read(filename, - map_sysmem(CONFIG_SYS_LOAD_ADDR, 0), 0); - if (err <= 0) - goto end; - err = spl_parse_image_header(spl_image, bootdev, - map_sysmem(CONFIG_SYS_LOAD_ADDR, - err)); - if (err == -EAGAIN) - return err; - if (err == 0) - err = 1; - } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = spl_fit_read; - spl_set_bl_len(&load, ARCH_DMA_MINALIGN); - load.priv = (void *)filename; - - return spl_load_simple_fit(spl_image, &load, 0, header); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); + /* + * Avoid pulling in this function for other image types since we are + * very short on space on some boards. + */ + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + err = fat_size(filename, &size); if (err) goto end; - - err = file_fat_read(filename, map_sysmem(spl_image->load_addr, - spl_image->size), 0); + } else { + size = 0; } + load.read = spl_fit_read; + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); + load.priv = (void *)filename; + err = spl_load(spl_image, bootdev, &load, size, 0); + end: #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT - if (err <= 0) + if (err < 0) printf("%s: error reading image %s, err - %d\n", __func__, filename, err); #endif - return (err <= 0); + return err; } #if CONFIG_IS_ENABLED(OS_BOOT) diff --git a/include/spl_load.h b/include/spl_load.h index 65aa6bb4493..5e0460d956d 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -96,6 +96,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, */ #define SPL_LOAD_USERS \ IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ + IS_ENABLED(CONFIG_SPL_FS_FAT) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 01559e98c4f..333df2dfb53 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -425,8 +425,7 @@ static int spl_test_mmc(struct unit_test_state *uts, const char *test_name, if (spl_test_mmc_fs(uts, test_name, type, create_ext2, false)) return CMD_RET_FAILURE; - if (type != IMX8 && type != LEGACY_LZMA && - spl_test_mmc_fs(uts, test_name, type, create_fat, false)) + if (spl_test_mmc_fs(uts, test_name, type, create_fat, false)) return CMD_RET_FAILURE; if (type == LEGACY_LZMA) -- cgit v1.3.1 From 5d3401a448353767c5e67246a79271c9ee6f3f73 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:50 -0500 Subject: spl: Convert mmc to spl_load This converts the mmc loader to spl_load. Legacy images are handled by spl_load (via spl_parse_image_header), so mmc_load_legacy can be omitted. To accurately determine whether mmc_load_image_raw_sector is used (which might not be the case if SYS_MMCSD_FS_BOOT is enabled), we introduce a helper config SYS_MMCSD_RAW_MODE. This ensures we can inline spl_load correctly when a board only boots from filesystems. We still need to check for SPL_MMC, since some boards enable configure raw mode even without MMC support. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/Kconfig | 8 +++++ common/spl/spl_mmc.c | 89 ++++-------------------------------------------- include/spl_load.h | 1 + test/image/spl_load_fs.c | 3 -- 4 files changed, 16 insertions(+), 85 deletions(-) (limited to 'include') diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 0bc57d5fedb..b93526904eb 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -481,6 +481,11 @@ config SPL_DISPLAY_PRINT banner ("U-Boot SPL ..."). This function should be provided by the board. +config SPL_SYS_MMCSD_RAW_MODE + bool + help + Support booting from an MMC without a filesystem. + config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR bool "MMC raw mode: by sector" default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ @@ -490,6 +495,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR OMAP44XX || OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED select SPL_LOAD_BLOCK if SPL_MMC + select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC help Use sector number for specifying U-Boot location on MMC/SD in raw mode. @@ -527,6 +533,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_DATA_PART_OFFSET config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION bool "MMC Raw mode: by partition" select SPL_LOAD_BLOCK if SPL_MMC + select SPL_SYS_MMCSD_RAW_MODE if SPL_MMC help Use a partition for loading U-Boot when using MMC/SD in raw mode. @@ -1114,6 +1121,7 @@ config SPL_FALCON_BOOT_MMCSD bool "Enable Falcon boot from MMC or SD media" depends on SPL_OS_BOOT && SPL_MMC select SPL_LOAD_BLOCK + select SPL_SYS_MMCSD_RAW_MODE help Select this if the Falcon mode OS image mode is on MMC or SD media. diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index 91272c03d3f..3d032bb27ce 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -8,9 +8,9 @@ #include #include #include -#include #include #include +#include #include #include #include @@ -19,49 +19,6 @@ #include #include -static int mmc_load_legacy(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct mmc *mmc, - ulong sector, struct legacy_img_hdr *header) -{ - u32 image_offset_sectors; - u32 image_size_sectors; - unsigned long count; - u32 image_offset; - int ret; - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) - return ret; - - /* convert offset to sectors - round down */ - image_offset_sectors = spl_image->offset / mmc->read_bl_len; - /* calculate remaining offset */ - image_offset = spl_image->offset % mmc->read_bl_len; - - /* convert size to sectors - round up */ - image_size_sectors = (spl_image->size + mmc->read_bl_len - 1) / - mmc->read_bl_len; - - /* Read the header too to avoid extra memcpy */ - count = blk_dread(mmc_get_blk_desc(mmc), - sector + image_offset_sectors, - image_size_sectors, - map_sysmem(spl_image->load_addr, - image_size_sectors * mmc->read_bl_len)); - debug("read %x sectors to %lx\n", image_size_sectors, - spl_image->load_addr); - if (count != image_size_sectors) - return -EIO; - - if (image_offset) - memmove((void *)(ulong)spl_image->load_addr, - (void *)(ulong)spl_image->load_addr + image_offset, - spl_image->size); - - return 0; -} - static ulong h_spl_load_read(struct spl_load_info *load, ulong off, ulong size, void *buf) { @@ -87,46 +44,14 @@ int mmc_load_image_raw_sector(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct mmc *mmc, unsigned long sector) { - unsigned long count; - struct legacy_img_hdr *header; + int ret; struct blk_desc *bd = mmc_get_blk_desc(mmc); - int ret = 0; - - header = spl_get_load_buffer(-sizeof(*header), bd->blksz); - - /* read image header to find the image size & load address */ - count = blk_dread(bd, sector, 1, header); - debug("hdr read sector %lx, count=%lu\n", sector, count); - if (count == 0) { - ret = -EIO; - goto end; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.priv = bd; - spl_set_bl_len(&load, bd->blksz); - load.read = h_spl_load_read; - ret = spl_load_simple_fit(spl_image, &load, - sector << bd->log2blksz, header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.priv = bd; - spl_set_bl_len(&load, bd->blksz); - load.read = h_spl_load_read; - - ret = spl_load_imx_container(spl_image, &load, - sector << bd->log2blksz); - } else { - ret = mmc_load_legacy(spl_image, bootdev, mmc, sector, header); - } + struct spl_load_info load; -end: + load.priv = bd; + spl_set_bl_len(&load, bd->blksz); + load.read = h_spl_load_read; + ret = spl_load(spl_image, bootdev, &load, 0, sector << bd->log2blksz); if (ret) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT puts("mmc_load_image_raw_sector: mmc block read error\n"); diff --git a/include/spl_load.h b/include/spl_load.h index 5e0460d956d..d55a47ae7d7 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -97,6 +97,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, #define SPL_LOAD_USERS \ IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ IS_ENABLED(CONFIG_SPL_FS_FAT) + \ + IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 333df2dfb53..67c19da95e7 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -428,9 +428,6 @@ static int spl_test_mmc(struct unit_test_state *uts, const char *test_name, if (spl_test_mmc_fs(uts, test_name, type, create_fat, false)) return CMD_RET_FAILURE; - if (type == LEGACY_LZMA) - return 0; - return do_spl_test_load(uts, test_name, type, SPL_LOAD_IMAGE_GET(0, BOOT_DEVICE_MMC1, spl_mmc_load_image), -- cgit v1.3.1 From 11f834614e8577bffea04d39e7eb235ee1271b29 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:51 -0500 Subject: spl: Convert nand to spl_load This converts the nand load method to use spl_load. nand_page_size may not be valid until after nand_spl_load_image is called (see e.g. fsl_ifc_spl), so we set bl_len in spl_nand_read. Since spl_load reads the header for us, we can remove that argument from spl_nand_load_element. There are two possible regressions which could result from this commit. First, we ask for a negative address from spl_get_load_buffer. That is, instead of header = spl_get_load_buffer(0, sizeof(*header)); we do header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); this could cause a problem if spl_get_load_buffer does not return valid memory for negative offsets. Second, we now set bl_len for legacy images. This can cause memory up to a bl_len - 1 before the image load address to be written, which might not have been the case before. If this turns out to be a problem, we can add an option for a bounce buffer. We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the test in that case. No boards enable SPL_NAND_SUPPORT and SPL_LOAD_FIT_FULL, so this is not a regression. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_nand.c | 70 +++++++++++----------------------------------- include/spl_load.h | 1 + test/image/spl_load_nand.c | 2 ++ 3 files changed, 19 insertions(+), 54 deletions(-) (limited to 'include') diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 91fa7674f17..3b0a1524238 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -59,6 +60,7 @@ static ulong spl_nand_read(struct spl_load_info *load, ulong offs, ulong size, sector = *(int *)load->priv; offs = sector + nand_spl_adjust_offset(sector, offs - sector); err = nand_spl_load_image(offs, size, dst); + spl_set_bl_len(load, nand_page_size()); if (err) return 0; @@ -66,60 +68,20 @@ static ulong spl_nand_read(struct spl_load_info *load, ulong offs, ulong size, } static int spl_nand_load_element(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - int offset, struct legacy_img_hdr *header) + struct spl_boot_device *bootdev, int offset) { - int bl_len; - int err; + struct spl_load_info load; - err = nand_spl_load_image(offset, sizeof(*header), (void *)header); - if (err) - return err; - - bl_len = nand_page_size(); - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.priv = &offset; - spl_set_bl_len(&load, bl_len); - load.read = spl_nand_read; - return spl_load_simple_fit(spl_image, &load, offset, header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.priv = &offset; - spl_set_bl_len(&load, bl_len); - load.read = spl_nand_read; - return spl_load_imx_container(spl_image, &load, offset); - } else if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT) && - image_get_magic(header) == IH_MAGIC) { - struct spl_load_info load; - - debug("Found legacy image\n"); - load.priv = &offset; - spl_set_bl_len(&load, IS_ENABLED(CONFIG_SPL_LZMA) ? bl_len : 1); - load.read = spl_nand_read; - return spl_load_legacy_img(spl_image, bootdev, &load, offset, header); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); - if (err) - return err; - return nand_spl_load_image(offset, spl_image->size, - map_sysmem(spl_image->load_addr, - spl_image->size)); - } + load.priv = &offset; + spl_set_bl_len(&load, 1); + load.read = spl_nand_read; + return spl_load(spl_image, bootdev, &load, 0, offset); } static int spl_nand_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { int err; - struct legacy_img_hdr *header; - int *src __attribute__((unused)); - int *dst __attribute__((unused)); #ifdef CONFIG_SPL_NAND_SOFTECC debug("spl: nand - using sw ecc\n"); @@ -128,10 +90,12 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, #endif nand_init(); - header = spl_get_load_buffer(0, sizeof(*header)); - #if CONFIG_IS_ENABLED(OS_BOOT) if (!spl_start_uboot()) { + int *src, *dst; + struct legacy_img_hdr *header = + spl_get_load_buffer(0, sizeof(*header)); + /* * load parameter image * load to temp position since nand_spl_load_image reads @@ -174,20 +138,18 @@ static int spl_nand_load_image(struct spl_image_info *spl_image, } #endif #ifdef CONFIG_NAND_ENV_DST - spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET, header); + spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET); #ifdef CONFIG_ENV_OFFSET_REDUND - spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND, header); + spl_nand_load_element(spl_image, bootdev, CONFIG_ENV_OFFSET_REDUND); #endif #endif /* Load u-boot */ - err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page(), - header); + err = spl_nand_load_element(spl_image, bootdev, spl_nand_get_uboot_raw_page()); #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND if (err) err = spl_nand_load_element(spl_image, bootdev, - CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND, - header); + CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND); #endif #endif nand_deselect(); diff --git a/include/spl_load.h b/include/spl_load.h index d55a47ae7d7..38294a21ad0 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -98,6 +98,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ IS_ENABLED(CONFIG_SPL_FS_FAT) + \ IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ + (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_nand.c b/test/image/spl_load_nand.c index 30179de98e7..ec242207948 100644 --- a/test/image/spl_load_nand.c +++ b/test/image/spl_load_nand.c @@ -51,4 +51,6 @@ SPL_IMG_TEST(spl_test_nand, LEGACY, DM_FLAGS); SPL_IMG_TEST(spl_test_nand, LEGACY_LZMA, DM_FLAGS); SPL_IMG_TEST(spl_test_nand, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_nand, FIT_INTERNAL, DM_FLAGS); +#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) SPL_IMG_TEST(spl_test_nand, FIT_EXTERNAL, DM_FLAGS); +#endif -- cgit v1.3.1 From 2e5476b5a7fe7255e58bd6b086c1c6c77350cadd Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:52 -0500 Subject: spl: Convert net to spl_load This converts the net load method to use spl_load. As a result, it also adds support for LOAD_FIT_FULL and IMX images. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_net.c | 29 +++++------------------------ include/spl_load.h | 1 + test/image/spl_load_net.c | 2 ++ 3 files changed, 8 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/common/spl/spl_net.c b/common/spl/spl_net.c index 47994e28165..898f9df705a 100644 --- a/common/spl/spl_net.c +++ b/common/spl/spl_net.c @@ -11,8 +11,8 @@ #include #include #include -#include #include +#include #include #include @@ -29,8 +29,7 @@ static ulong spl_net_load_read(struct spl_load_info *load, ulong sector, static int spl_net_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { - struct legacy_img_hdr *header = map_sysmem(image_load_addr, - sizeof(*header)); + struct spl_load_info load; int rv; env_init(); @@ -49,27 +48,9 @@ static int spl_net_load_image(struct spl_image_info *spl_image, return rv; } - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - spl_set_bl_len(&load, 1); - load.read = spl_net_load_read; - rv = spl_load_simple_fit(spl_image, &load, 0, header); - } else { - debug("Legacy image\n"); - - rv = spl_parse_image_header(spl_image, bootdev, header); - if (rv) - return rv; - - memcpy(map_sysmem(spl_image->load_addr, spl_image->size), - map_sysmem(image_load_addr, spl_image->size), - spl_image->size); - } - - return rv; + spl_set_bl_len(&load, 1); + load.read = spl_net_load_read; + return spl_load(spl_image, bootdev, &load, 0, 0); } #endif diff --git a/include/spl_load.h b/include/spl_load.h index 38294a21ad0..4777f84ac6b 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -99,6 +99,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, IS_ENABLED(CONFIG_SPL_FS_FAT) + \ IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \ + IS_ENABLED(CONFIG_SPL_NET) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_net.c b/test/image/spl_load_net.c index f570cef163f..9d067a7a592 100644 --- a/test/image/spl_load_net.c +++ b/test/image/spl_load_net.c @@ -248,5 +248,7 @@ static int spl_test_net(struct unit_test_state *uts, const char *test_name, return ret; } SPL_IMG_TEST(spl_test_net, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_net, LEGACY_LZMA, DM_FLAGS); +SPL_IMG_TEST(spl_test_net, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_net, FIT_INTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_net, FIT_EXTERNAL, DM_FLAGS); -- cgit v1.3.1 From cbe86576cbe6344f9e9dafe10e28815a0fac801d Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:53 -0500 Subject: spl: Convert nor to spl_load This converts the nor load method to use spl_load. As a result it also adds support for LOAD_FIT_FULL. Since this is the last caller of spl_load_legacy_img, it has been removed. We can't load FITs with external data with SPL_LOAD_FIT_FULL, so disable the test in that case. No boards enable SPL_NOR_SUPPORT and SPL_LOAD_FIT_FULL, so this is not a regression. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_legacy.c | 61 ----------------------------------------------- common/spl/spl_nor.c | 40 ++++++------------------------- include/spl_load.h | 1 + test/image/spl_load_nor.c | 2 ++ 4 files changed, 10 insertions(+), 94 deletions(-) (limited to 'include') diff --git a/common/spl/spl_legacy.c b/common/spl/spl_legacy.c index a561939b4f0..08687ca8f6c 100644 --- a/common/spl/spl_legacy.c +++ b/common/spl/spl_legacy.c @@ -118,64 +118,3 @@ int spl_load_legacy_lzma(struct spl_image_info *spl_image, spl_image->size = lzma_len; return 0; } - -/* - * This function is added explicitly to avoid code size increase, when - * no compression method is enabled. The compiler will optimize the - * following switch/case statement in spl_load_legacy_img() away due to - * Dead Code Elimination. - */ -static inline int spl_image_get_comp(const struct legacy_img_hdr *hdr) -{ - if (IS_ENABLED(CONFIG_SPL_LZMA)) - return image_get_comp(hdr); - - return IH_COMP_NONE; -} - -int spl_load_legacy_img(struct spl_image_info *spl_image, - struct spl_boot_device *bootdev, - struct spl_load_info *load, ulong offset, - struct legacy_img_hdr *hdr) -{ - ulong dataptr; - int ret; - - /* - * If the payload is compressed, the decompressed data should be - * directly write to its load address. - */ - if (spl_image_get_comp(hdr) != IH_COMP_NONE) - spl_image->flags |= SPL_COPY_PAYLOAD_ONLY; - - ret = spl_parse_image_header(spl_image, bootdev, hdr); - if (ret) - return ret; - - /* Read image */ - switch (spl_image_get_comp(hdr)) { - case IH_COMP_NONE: - dataptr = offset; - - /* - * Image header will be skipped only if SPL_COPY_PAYLOAD_ONLY - * is set - */ - if (spl_image->flags & SPL_COPY_PAYLOAD_ONLY) - dataptr += sizeof(*hdr); - - load->read(load, dataptr, spl_image->size, - map_sysmem(spl_image->load_addr, spl_image->size)); - break; - - case IH_COMP_LZMA: - return spl_load_legacy_lzma(spl_image, load, offset); - - default: - debug("Compression method %s is not supported\n", - genimg_get_comp_short_name(image_get_comp(hdr))); - return -EINVAL; - } - - return 0; -} diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index aad230db4d3..70745114efe 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -7,8 +7,8 @@ #include #include #include -#include #include +#include static ulong spl_nor_load_read(struct spl_load_info *load, ulong sector, ulong count, void *buf) @@ -28,8 +28,7 @@ unsigned long __weak spl_nor_get_uboot_base(void) static int spl_nor_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { - struct legacy_img_hdr *header; - __maybe_unused struct spl_load_info load; + struct spl_load_info load; /* * Loading of the payload to SDRAM is done with skipping of @@ -43,7 +42,8 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load Linux from its location in NOR flash to its defined * location in SDRAM */ - header = (void *)CONFIG_SYS_OS_BASE; + const struct legacy_img_hdr *header = + (const struct legacy_img_hdr *)CONFIG_SYS_OS_BASE; #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { int ret; @@ -93,34 +93,8 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, * Load real U-Boot from its location in NOR flash to its * defined location in SDRAM */ - header = map_sysmem(spl_nor_get_uboot_base(), sizeof(*header)); -#ifdef CONFIG_SPL_LOAD_FIT - if (image_get_magic(header) == FDT_MAGIC) { - debug("Found FIT format U-Boot\n"); - spl_set_bl_len(&load, 1); - load.read = spl_nor_load_read; - return spl_load_simple_fit(spl_image, &load, - spl_nor_get_uboot_base(), - (void *)header); - } -#endif - if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - spl_set_bl_len(&load, 1); - load.read = spl_nor_load_read; - return spl_load_imx_container(spl_image, &load, - spl_nor_get_uboot_base()); - } - - /* Legacy image handling */ - if (IS_ENABLED(CONFIG_SPL_LEGACY_IMAGE_FORMAT)) { - spl_set_bl_len(&load, 1); - load.read = spl_nor_load_read; - return spl_load_legacy_img(spl_image, bootdev, &load, - spl_nor_get_uboot_base(), - header); - } - - return -EINVAL; + spl_set_bl_len(&load, 1); + load.read = spl_nor_load_read; + return spl_load(spl_image, bootdev, &load, 0, spl_nor_get_uboot_base()); } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/include/spl_load.h b/include/spl_load.h index 4777f84ac6b..b48f80324bb 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -100,6 +100,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \ IS_ENABLED(CONFIG_SPL_NET) + \ + IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_nor.c b/test/image/spl_load_nor.c index a62bb60d253..de5686343b9 100644 --- a/test/image/spl_load_nor.c +++ b/test/image/spl_load_nor.c @@ -36,4 +36,6 @@ SPL_IMG_TEST(spl_test_nor, LEGACY, 0); SPL_IMG_TEST(spl_test_nor, LEGACY_LZMA, 0); SPL_IMG_TEST(spl_test_nor, IMX8, 0); SPL_IMG_TEST(spl_test_nor, FIT_INTERNAL, 0); +#if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) SPL_IMG_TEST(spl_test_nor, FIT_EXTERNAL, 0); +#endif -- cgit v1.3.1 From 6029a0e1affa19b83004083af3130e153af028fa Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:54 -0500 Subject: spl: Convert NVMe to spl_load This converts the blk load method (used exclusively by NVMe) to use spl_load. As a consequence, it also adds support for LOAD_FIT_FULL and IMX images. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_blk_fs.c | 66 ++++++++---------------------------------------- include/spl_load.h | 1 + test/image/spl_load_fs.c | 2 ++ 3 files changed, 14 insertions(+), 55 deletions(-) (limited to 'include') diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c index 53b8e1b11b4..ac267ab979b 100644 --- a/common/spl/spl_blk_fs.c +++ b/common/spl/spl_blk_fs.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -48,11 +49,11 @@ int spl_blk_load_image(struct spl_image_info *spl_image, enum uclass_id uclass_id, int devnum, int partnum) { const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; - struct legacy_img_hdr *header; struct blk_desc *blk_desc; - loff_t actlen, filesize; + loff_t filesize; struct blk_dev dev; - int ret = -ENODEV; + struct spl_load_info load; + int ret; blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum); if (!blk_desc) { @@ -61,8 +62,8 @@ int spl_blk_load_image(struct spl_image_info *spl_image, } blk_show_device(uclass_id, devnum); - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + dev.filename = filename; dev.ifname = blk_get_uclass_name(uclass_id); snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%x:%x", devnum, partnum); @@ -70,63 +71,18 @@ int spl_blk_load_image(struct spl_image_info *spl_image, if (ret) { printf("spl: unable to set blk_dev %s %s. Err - %d\n", dev.ifname, dev.dev_part_str, ret); - goto out; - } - - ret = fs_read(filename, virt_to_phys(header), 0, - sizeof(struct legacy_img_hdr), &actlen); - if (ret) { - printf("spl: unable to read file %s. Err - %d\n", filename, - ret); - goto out; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = spl_fit_read; - spl_set_bl_len(&load, ARCH_DMA_MINALIGN); - load.priv = &dev; - dev.filename = filename; - - return spl_load_simple_fit(spl_image, &load, 0, header); - } - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) { - printf("spl: unable to parse image header. Err - %d\n", - ret); - goto out; - } - - ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); - if (ret) { - printf("spl: unable to set blk_dev %s %s. Err - %d\n", - dev.ifname, dev.dev_part_str, ret); - goto out; + return ret; } ret = fs_size(filename, &filesize); if (ret) { printf("spl: unable to get file size: %s. Err - %d\n", filename, ret); - goto out; - } - - ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); - if (ret) { - printf("spl: unable to set blk_dev %s %s. Err - %d\n", - dev.ifname, dev.dev_part_str, ret); - goto out; + return ret; } - ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize, - &actlen); - if (ret) - printf("spl: unable to read file %s. Err - %d\n", - filename, ret); -out: - return ret; + load.read = spl_fit_read; + spl_set_bl_len(&load, ARCH_DMA_MINALIGN); + load.priv = &dev; + return spl_load(spl_image, bootdev, &load, filesize, 0); } diff --git a/include/spl_load.h b/include/spl_load.h index b48f80324bb..2618109cee0 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -95,6 +95,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, * inline if there is one caller, and extern otherwise. */ #define SPL_LOAD_USERS \ + IS_ENABLED(CONFIG_SPL_BLK_FS) + \ IS_ENABLED(CONFIG_SPL_FS_EXT4) + \ IS_ENABLED(CONFIG_SPL_FS_FAT) + \ IS_ENABLED(CONFIG_SPL_SYS_MMCSD_RAW_MODE) + \ diff --git a/test/image/spl_load_fs.c b/test/image/spl_load_fs.c index 67c19da95e7..5f1de5486f4 100644 --- a/test/image/spl_load_fs.c +++ b/test/image/spl_load_fs.c @@ -395,6 +395,8 @@ static int spl_test_blk(struct unit_test_state *uts, const char *test_name, return spl_test_mmc_fs(uts, test_name, type, create_ext2, true); } SPL_IMG_TEST(spl_test_blk, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_blk, LEGACY_LZMA, DM_FLAGS); +SPL_IMG_TEST(spl_test_blk, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_blk, FIT_EXTERNAL, DM_FLAGS); SPL_IMG_TEST(spl_test_blk, FIT_INTERNAL, DM_FLAGS); -- cgit v1.3.1 From 9b9c6aaaf22e59bc903b640a26961cdba451140f Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:55 -0500 Subject: spl: Convert semihosting to spl_load This converts the semihosting load method to use spl_load. As a result, it also adds support for LOAD_FIT_FULL and IMX images. Signed-off-by: Sean Anderson --- common/spl/spl_semihosting.c | 52 +++++--------------------------------------- include/spl_load.h | 1 + 2 files changed, 7 insertions(+), 46 deletions(-) (limited to 'include') diff --git a/common/spl/spl_semihosting.c b/common/spl/spl_semihosting.c index 9b0610b8fc8..941fa911040 100644 --- a/common/spl/spl_semihosting.c +++ b/common/spl/spl_semihosting.c @@ -8,18 +8,7 @@ #include #include #include - -static int smh_read_full(long fd, void *memp, size_t len) -{ - long read; - - read = smh_read(fd, memp, len); - if (read < 0) - return read; - if (read != len) - return -EIO; - return 0; -} +#include static ulong smh_fit_read(struct spl_load_info *load, ulong file_offset, ulong size, void *buf) @@ -40,8 +29,7 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, const char *filename = CONFIG_SPL_FS_LOAD_PAYLOAD_NAME; int ret; long fd, len; - struct legacy_img_hdr *header = - spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + struct spl_load_info load; fd = smh_open(filename, MODE_READ | MODE_BINARY); if (fd < 0) { @@ -56,38 +44,10 @@ static int spl_smh_load_image(struct spl_image_info *spl_image, } len = ret; - ret = smh_read_full(fd, header, sizeof(struct legacy_img_hdr)); - if (ret) { - log_debug("could not read image header: %d\n", ret); - goto out; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.read = smh_fit_read; - spl_set_bl_len(&load, 1); - load.priv = &fd; - - ret = spl_load_simple_fit(spl_image, &load, 0, header); - goto out; - } - - ret = spl_parse_image_header(spl_image, bootdev, header); - if (ret) { - log_debug("failed to parse image header: %d\n", ret); - goto out; - } - - ret = smh_seek(fd, 0); - if (ret) { - log_debug("could not seek to start of image: %d\n", ret); - goto out; - } - - ret = smh_read_full(fd, (void *)spl_image->load_addr, len); + load.read = smh_fit_read; + spl_set_bl_len(&load, 1); + load.priv = &fd; + ret = spl_load(spl_image, bootdev, &load, len, 0); if (ret) log_debug("could not read %s: %d\n", filename, ret); out: diff --git a/include/spl_load.h b/include/spl_load.h index 2618109cee0..2a20e866cd8 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -102,6 +102,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, (IS_ENABLED(CONFIG_SPL_NAND_SUPPORT) && !IS_ENABLED(CONFIG_SPL_UBI)) + \ IS_ENABLED(CONFIG_SPL_NET) + \ IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \ + IS_ENABLED(CONFIG_SPL_SEMIHOSTING) + \ 0 #if SPL_LOAD_USERS > 1 -- cgit v1.3.1 From a04d5f60a581ad5feac309ef014e47d41ccc8d48 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 11:48:56 -0500 Subject: spl: Convert spi to spl_load This converts the spi load method to use spl_load. The address used for LOAD_FIT_FULL may be different, but there are no in-tree users of that config. Since payload_offs is only used without OS_BOOT, we defer its initialization. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass --- common/spl/spl_spi.c | 80 ++++++++--------------------------------------- include/spl_load.h | 1 + test/image/spl_load_spi.c | 1 + 3 files changed, 15 insertions(+), 67 deletions(-) (limited to 'include') diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index 3e08ac7c1a2..f49e534b749 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -12,11 +12,11 @@ #include #include #include -#include #include #include #include #include +#include #include #include #include @@ -95,9 +95,9 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, int err = 0; unsigned int payload_offs; struct spi_flash *flash; - struct legacy_img_hdr *header; unsigned int sf_bus = spl_spi_boot_bus(); unsigned int sf_cs = spl_spi_boot_cs(); + struct spl_load_info load; /* * Load U-Boot image from SPI flash into RAM @@ -112,77 +112,23 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, return -ENODEV; } - payload_offs = spl_spi_get_uboot_offs(flash); - - header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); +#if CONFIG_IS_ENABLED(OS_BOOT) + if (!spl_start_uboot() && !spi_load_image_os(spl_image, bootdev, flash, header)) + return 0; +#endif + payload_offs = spl_spi_get_uboot_offs(flash); if (CONFIG_IS_ENABLED(OF_REAL)) { payload_offs = ofnode_conf_read_int("u-boot,spl-payload-offset", payload_offs); } -#if CONFIG_IS_ENABLED(OS_BOOT) - if (spl_start_uboot() || spi_load_image_os(spl_image, bootdev, flash, header)) -#endif - { - /* Load u-boot, mkimage header is 64 bytes. */ - err = spi_flash_read(flash, payload_offs, sizeof(*header), - (void *)header); - if (err) { - debug("%s: Failed to read from SPI flash (err=%d)\n", - __func__, err); - return err; - } - - if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) && - image_get_magic(header) == FDT_MAGIC) { - u32 size = roundup(fdt_totalsize(header), 4); - - err = spi_flash_read(flash, payload_offs, - size, - map_sysmem(CONFIG_SYS_LOAD_ADDR, - size)); - if (err) - return err; - err = spl_parse_image_header(spl_image, bootdev, - phys_to_virt(CONFIG_SYS_LOAD_ADDR)); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && - image_get_magic(header) == FDT_MAGIC) { - struct spl_load_info load; - - debug("Found FIT\n"); - load.priv = flash; - spl_set_bl_len(&load, 1); - load.read = spl_spi_fit_read; - err = spl_load_simple_fit(spl_image, &load, - payload_offs, - header); - } else if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && - valid_container_hdr((void *)header)) { - struct spl_load_info load; - - load.priv = flash; - spl_set_bl_len(&load, 1); - load.read = spl_spi_fit_read; - - err = spl_load_imx_container(spl_image, &load, - payload_offs); - } else { - err = spl_parse_image_header(spl_image, bootdev, header); - if (err) - return err; - err = spi_flash_read(flash, payload_offs + spl_image->offset, - spl_image->size, - map_sysmem(spl_image->load_addr, - spl_image->size)); - } - if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) { - err = spi_nor_remove(flash); - if (err) - return err; - } - } - + load.priv = flash; + spl_set_bl_len(&load, 1); + load.read = spl_spi_fit_read; + err = spl_load(spl_image, bootdev, &load, 0, payload_offs); + if (IS_ENABLED(CONFIG_SPI_FLASH_SOFT_RESET)) + err = spi_nor_remove(flash); return err; } /* Use priorty 1 so that boards can override this */ diff --git a/include/spl_load.h b/include/spl_load.h index 2a20e866cd8..1c2b296c0a2 100644 --- a/include/spl_load.h +++ b/include/spl_load.h @@ -103,6 +103,7 @@ static inline int _spl_load(struct spl_image_info *spl_image, IS_ENABLED(CONFIG_SPL_NET) + \ IS_ENABLED(CONFIG_SPL_NOR_SUPPORT) + \ IS_ENABLED(CONFIG_SPL_SEMIHOSTING) + \ + IS_ENABLED(CONFIG_SPL_SPI_LOAD) + \ 0 #if SPL_LOAD_USERS > 1 diff --git a/test/image/spl_load_spi.c b/test/image/spl_load_spi.c index 8f9b6e0139b..54a95465e23 100644 --- a/test/image/spl_load_spi.c +++ b/test/image/spl_load_spi.c @@ -34,6 +34,7 @@ static int spl_test_spi(struct unit_test_state *uts, const char *test_name, spl_test_spi_write_image); } SPL_IMG_TEST(spl_test_spi, LEGACY, DM_FLAGS); +SPL_IMG_TEST(spl_test_spi, LEGACY_LZMA, DM_FLAGS); SPL_IMG_TEST(spl_test_spi, IMX8, DM_FLAGS); SPL_IMG_TEST(spl_test_spi, FIT_INTERNAL, DM_FLAGS); #if !IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL) -- cgit v1.3.1 From 7667bdeb0e6f63b4df9a253c85ea08d1625d6e63 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Wed, 8 Nov 2023 12:51:09 -0500 Subject: fs: ext4: Remove unused parameter from ext4_mount The part_length parameter is not used. Remove it. Signed-off-by: Sean Anderson --- common/spl/spl_ext.c | 4 ++-- env/ext4.c | 4 ++-- fs/ext4/ext4_common.c | 2 +- fs/ext4/ext4fs.c | 2 +- include/ext4fs.h | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/common/spl/spl_ext.c b/common/spl/spl_ext.c index af836ca15b8..2f960956c44 100644 --- a/common/spl/spl_ext.c +++ b/common/spl/spl_ext.c @@ -29,7 +29,7 @@ int spl_load_image_ext(struct spl_image_info *spl_image, ext4fs_set_blk_dev(block_dev, &part_info); - err = ext4fs_mount(part_info.size); + err = ext4fs_mount(); if (!err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: ext4fs mount err - %d\n", __func__, err); @@ -84,7 +84,7 @@ int spl_load_image_ext_os(struct spl_image_info *spl_image, ext4fs_set_blk_dev(block_dev, &part_info); - err = ext4fs_mount(part_info.size); + err = ext4fs_mount(); if (!err) { #ifdef CONFIG_SPL_LIBCOMMON_SUPPORT printf("%s: ext4fs mount err - %d\n", __func__, err); diff --git a/env/ext4.c b/env/ext4.c index 47e05a48919..da26705b8da 100644 --- a/env/ext4.c +++ b/env/ext4.c @@ -77,7 +77,7 @@ static int env_ext4_save_buffer(env_t *env_new) dev = dev_desc->devnum; ext4fs_set_blk_dev(dev_desc, &info); - if (!ext4fs_mount(info.size)) { + if (!ext4fs_mount()) { printf("\n** Unable to use %s %s for saveenv **\n", ifname, dev_and_part); return 1; @@ -160,7 +160,7 @@ static int env_ext4_load(void) dev = dev_desc->devnum; ext4fs_set_blk_dev(dev_desc, &info); - if (!ext4fs_mount(info.size)) { + if (!ext4fs_mount()) { printf("\n** Unable to use %s %s for loading the env **\n", ifname, dev_and_part); goto err_env_relocate; diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c index f50de7c089e..ea9b92298ba 100644 --- a/fs/ext4/ext4_common.c +++ b/fs/ext4/ext4_common.c @@ -2368,7 +2368,7 @@ fail: return -1; } -int ext4fs_mount(unsigned part_length) +int ext4fs_mount(void) { struct ext2_data *data; int status; diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c index 4c89152ce4a..3b12ec54fa2 100644 --- a/fs/ext4/ext4fs.c +++ b/fs/ext4/ext4fs.c @@ -233,7 +233,7 @@ int ext4fs_probe(struct blk_desc *fs_dev_desc, { ext4fs_set_blk_dev(fs_dev_desc, fs_partition); - if (!ext4fs_mount(fs_partition->size)) { + if (!ext4fs_mount()) { ext4fs_close(); return -1; } diff --git a/include/ext4fs.h b/include/ext4fs.h index dd66d27f776..d96edfd0576 100644 --- a/include/ext4fs.h +++ b/include/ext4fs.h @@ -147,7 +147,7 @@ int ext4fs_create_link(const char *target, const char *fname); struct ext_filesystem *get_fs(void); int ext4fs_open(const char *filename, loff_t *len); int ext4fs_read(char *buf, loff_t offset, loff_t len, loff_t *actread); -int ext4fs_mount(unsigned part_length); +int ext4fs_mount(void); void ext4fs_close(void); void ext4fs_reinit_global(void); int ext4fs_ls(const char *dirname); -- cgit v1.3.1 From d7ce04c7f4cbae9608287ebd810a411944efff9a Mon Sep 17 00:00:00 2001 From: Igor Prusov Date: Thu, 9 Nov 2023 20:10:02 +0300 Subject: linux/time.h: Add Linux time conversion defines Currently there are no defines for time conversion in time.h, which leads to drivers declaring those locally or not using defines at all, so add them from Linux. Signed-off-by: Igor Prusov Reviewed-by: Simon Glass --- include/linux/time.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/linux/time.h b/include/linux/time.h index 14ff5b6f481..14a144d9c9c 100644 --- a/include/linux/time.h +++ b/include/linux/time.h @@ -11,6 +11,15 @@ #define _REENT_ONLY +#define MSEC_PER_SEC 1000L +#define USEC_PER_MSEC 1000L +#define NSEC_PER_USEC 1000L +#define NSEC_PER_MSEC 1000000L +#define USEC_PER_SEC 1000000L +#define NSEC_PER_SEC 1000000000L +#define PSEC_PER_SEC 1000000000000LL +#define FSEC_PER_SEC 1000000000000000LL + #define SECSPERMIN 60L #define MINSPERHOUR 60L #define HOURSPERDAY 24L -- cgit v1.3.1 From 66a3618b9afc564ca073446a50cd6a139b741f51 Mon Sep 17 00:00:00 2001 From: Igor Opaniuk Date: Thu, 9 Nov 2023 23:34:35 +0100 Subject: poplar: provide more space for kernel image Adjust mem layout, providing more space for linux kernel image. This fixes the problem: ERROR: FDT image overlaps OS image (OS=0x30000000..0x32580000) Signed-off-by: Igor Opaniuk Reviewed-by: Sam Protsenko --- include/configs/poplar.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/poplar.h b/include/configs/poplar.h index 6e8adf91877..629b335f5d1 100644 --- a/include/configs/poplar.h +++ b/include/configs/poplar.h @@ -37,11 +37,11 @@ "env_mmc_blknum=0xf80\0" \ "env_mmc_nblks=0x80\0" \ "kernel_addr_r=0x30000000\0" \ - "pxefile_addr_r=0x32000000\0" \ - "scriptaddr=0x32000000\0" \ - "fdt_addr_r=0x32200000\0" \ + "pxefile_addr_r=0x33000000\0" \ + "scriptaddr=0x33000000\0" \ + "fdt_addr_r=0x33200000\0" \ "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \ - "ramdisk_addr_r=0x32400000\0" \ + "ramdisk_addr_r=0x33400000\0" \ BOOTENV #endif /* _POPLAR_H_ */ -- cgit v1.3.1 From a654369b4923781059032b7c7ba68f4c5195d93f Mon Sep 17 00:00:00 2001 From: Dmitrii Merkurev Date: Fri, 10 Nov 2023 05:59:54 +0000 Subject: cmd: bcb: support various block device interfaces for BCB command Currently BCB command-line, C APIs and implementation only support MMC interface. Extend it to allow various block device interfaces. Signed-off-by: Dmitrii Merkurev Cc: Eugeniu Rosca Cc: Ying-Chun Liu (PaulLiu) Cc: Simon Glass Cc: Mattijs Korpershoek Cc: Sean Anderson Cc: Cody Schuffelen Tested-by: Mattijs Korpershoek # on vim3 Reviewed-by: Mattijs Korpershoek --- cmd/Kconfig | 1 - cmd/bcb.c | 70 +++++++++++++++++++++++++++----------------- doc/android/bcb.rst | 34 +++++++++++---------- drivers/fastboot/fb_common.c | 2 +- include/bcb.h | 5 ++-- 5 files changed, 65 insertions(+), 47 deletions(-) (limited to 'include') diff --git a/cmd/Kconfig b/cmd/Kconfig index 629a90afb7b..6f636155e5b 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -960,7 +960,6 @@ config CMD_ADC config CMD_BCB bool "bcb" - depends on MMC depends on PARTITIONS help Read/modify/write the fields of Bootloader Control Block, usually diff --git a/cmd/bcb.c b/cmd/bcb.c index 02d0c70d87e..6594ac64396 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -25,6 +25,7 @@ enum bcb_cmd { BCB_CMD_STORE, }; +static enum uclass_id bcb_uclass_id = UCLASS_INVALID; static int bcb_dev = -1; static int bcb_part = -1; static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } }; @@ -53,6 +54,9 @@ static int bcb_is_misused(int argc, char *const argv[]) switch (cmd) { case BCB_CMD_LOAD: + if (argc != 3 && argc != 4) + goto err; + break; case BCB_CMD_FIELD_SET: if (argc != 3) goto err; @@ -115,7 +119,7 @@ static int bcb_field_get(char *name, char **fieldp, int *sizep) return 0; } -static int __bcb_load(int devnum, const char *partp) +static int __bcb_load(const char *iface, int devnum, const char *partp) { struct blk_desc *desc; struct disk_partition info; @@ -123,14 +127,14 @@ static int __bcb_load(int devnum, const char *partp) char *endp; int part, ret; - desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, devnum); + desc = blk_get_dev(iface, devnum); if (!desc) { ret = -ENODEV; goto err_read_fail; } /* - * always select the USER mmc hwpart in case another + * always select the first hwpart in case another * blk operation selected a different hwpart */ ret = blk_dselect_hwpart(desc, 0); @@ -161,18 +165,20 @@ static int __bcb_load(int devnum, const char *partp) goto err_read_fail; } + bcb_uclass_id = desc->uclass_id; bcb_dev = desc->devnum; bcb_part = part; - debug("%s: Loaded from mmc %d:%d\n", __func__, bcb_dev, bcb_part); + debug("%s: Loaded from %s %d:%d\n", __func__, iface, bcb_dev, bcb_part); return CMD_RET_SUCCESS; err_read_fail: - printf("Error: mmc %d:%s read failed (%d)\n", devnum, partp, ret); + printf("Error: %s %d:%s read failed (%d)\n", iface, devnum, partp, ret); goto err; err_too_small: - printf("Error: mmc %d:%s too small!", devnum, partp); + printf("Error: %s %d:%s too small!", iface, devnum, partp); goto err; err: + bcb_uclass_id = UCLASS_INVALID; bcb_dev = -1; bcb_part = -1; @@ -182,15 +188,23 @@ err: static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + int devnum; char *endp; - int devnum = simple_strtoul(argv[1], &endp, 0); + char *iface = "mmc"; + + if (argc == 4) { + iface = argv[1]; + argc--; + argv++; + } + devnum = simple_strtoul(argv[1], &endp, 0); if (*endp != '\0') { printf("Error: Device id '%s' not a number\n", argv[1]); return CMD_RET_FAILURE; } - return __bcb_load(devnum, argv[2]); + return __bcb_load(iface, devnum, argv[2]); } static int __bcb_set(char *fieldp, const char *valp) @@ -298,7 +312,7 @@ static int __bcb_store(void) u64 cnt; int ret; - desc = blk_get_devnum_by_uclass_id(UCLASS_MMC, bcb_dev); + desc = blk_get_devnum_by_uclass_id(bcb_uclass_id, bcb_dev); if (!desc) { ret = -ENODEV; goto err; @@ -317,7 +331,7 @@ static int __bcb_store(void) return CMD_RET_SUCCESS; err: - printf("Error: mmc %d:%d write failed (%d)\n", bcb_dev, bcb_part, ret); + printf("Error: %d %d:%d write failed (%d)\n", bcb_uclass_id, bcb_dev, bcb_part, ret); return CMD_RET_FAILURE; } @@ -328,11 +342,11 @@ static int do_bcb_store(struct cmd_tbl *cmdtp, int flag, int argc, return __bcb_store(); } -int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp) +int bcb_write_reboot_reason(const char *iface, int devnum, char *partp, const char *reasonp) { int ret; - ret = __bcb_load(devnum, partp); + ret = __bcb_load(iface, devnum, partp); if (ret != CMD_RET_SUCCESS) return ret; @@ -385,21 +399,23 @@ static int do_bcb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) U_BOOT_CMD( bcb, CONFIG_SYS_MAXARGS, 1, do_bcb, "Load/set/clear/test/dump/store Android BCB fields", - "load - load BCB from mmc :\n" - "bcb set - set BCB to \n" - "bcb clear [] - clear BCB or all fields\n" - "bcb test - test BCB against \n" - "bcb dump - dump BCB \n" - "bcb store - store BCB back to mmc\n" + "load - load BCB from :\n" + "load - load BCB from mmc :\n" + "bcb set - set BCB to \n" + "bcb clear [] - clear BCB or all fields\n" + "bcb test - test BCB against \n" + "bcb dump - dump BCB \n" + "bcb store - store BCB back to \n" "\n" "Legend:\n" - " - MMC device index containing the BCB partition\n" - " - MMC partition index or name containing the BCB\n" - " - one of {command,status,recovery,stage,reserved}\n" - " - the binary operator used in 'bcb test':\n" - " '=' returns true if matches the string stored in \n" - " '~' returns true if matches a subset of 's string\n" - " - string/text provided as input to bcb {set,test}\n" - " NOTE: any ':' character in will be replaced by line feed\n" - " during 'bcb set' and used as separator by upper layers\n" + " - storage device interface (virtio, mmc, etc)\n" + " - storage device index containing the BCB partition\n" + " - partition index or name containing the BCB\n" + " - one of {command,status,recovery,stage,reserved}\n" + " - the binary operator used in 'bcb test':\n" + " '=' returns true if matches the string stored in \n" + " '~' returns true if matches a subset of 's string\n" + " - string/text provided as input to bcb {set,test}\n" + " NOTE: any ':' character in will be replaced by line feed\n" + " during 'bcb set' and used as separator by upper layers\n" ); diff --git a/doc/android/bcb.rst b/doc/android/bcb.rst index 88616083005..2226517d39f 100644 --- a/doc/android/bcb.rst +++ b/doc/android/bcb.rst @@ -41,23 +41,25 @@ requirements enumerated above. Below is the command's help message:: bcb - Load/set/clear/test/dump/store Android BCB fields Usage: - bcb load - load BCB from mmc : - bcb set - set BCB to - bcb clear [] - clear BCB or all fields - bcb test - test BCB against - bcb dump - dump BCB - bcb store - store BCB back to mmc + bcb load - load BCB from : + load - load BCB from mmc : + bcb set - set BCB to + bcb clear [] - clear BCB or all fields + bcb test - test BCB against + bcb dump - dump BCB + bcb store - store BCB back to Legend: - - MMC device index containing the BCB partition - - MMC partition index or name containing the BCB - - one of {command,status,recovery,stage,reserved} - - the binary operator used in 'bcb test': - '=' returns true if matches the string stored in - '~' returns true if matches a subset of 's string - - string/text provided as input to bcb {set,test} - NOTE: any ':' character in will be replaced by line feed - during 'bcb set' and used as separator by upper layers + - storage device interface (virtio, mmc, etc) + - storage device index containing the BCB partition + - partition index or name containing the BCB + - one of {command,status,recovery,stage,reserved} + - the binary operator used in 'bcb test': + '=' returns true if matches the string stored in + '~' returns true if matches a subset of 's string + - string/text provided as input to bcb {set,test} + NOTE: any ':' character in will be replaced by line feed + during 'bcb set' and used as separator by upper layers 'bcb'. Example of getting reboot reason @@ -91,7 +93,7 @@ The following Kconfig options must be enabled:: CONFIG_PARTITIONS=y CONFIG_MMC=y - CONFIG_BCB=y + CONFIG_CMD_BCB=y .. [1] https://android.googlesource.com/platform/bootable/recovery .. [2] https://source.android.com/devices/bootloader diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 4e9d9b719c6..2a6608b28c2 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -105,7 +105,7 @@ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) return -EINVAL; - return bcb_write_reboot_reason(mmc_dev, "misc", boot_cmds[reason]); + return bcb_write_reboot_reason("mmc", mmc_dev, "misc", boot_cmds[reason]); } /** diff --git a/include/bcb.h b/include/bcb.h index 5edb17aa47d..a6326523c47 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -9,10 +9,11 @@ #define __BCB_H__ #if IS_ENABLED(CONFIG_CMD_BCB) -int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp); +int bcb_write_reboot_reason(const char *iface, int devnum, char *partp, const char *reasonp); #else #include -static inline int bcb_write_reboot_reason(int devnum, char *partp, const char *reasonp) +static inline int bcb_write_reboot_reason(const char *iface, int devnum, + char *partp, const char *reasonp) { return -EOPNOTSUPP; } -- cgit v1.3.1 From dfeb4f0d79351dc0256b45c7a9f26c752c4e0e09 Mon Sep 17 00:00:00 2001 From: Dmitrii Merkurev Date: Fri, 10 Nov 2023 05:59:55 +0000 Subject: cmd: bcb: extend BCB C API to allow read/write the fields Currently BCB C API only allows to modify 'command' BCB field. Extend it so that we can also read and modify all the available BCB fields (command, status, recovery, stage). Co-developed-by: Cody Schuffelen Signed-off-by: Cody Schuffelen Signed-off-by: Dmitrii Merkurev Cc: Eugeniu Rosca Cc: Ying-Chun Liu (PaulLiu) Cc: Simon Glass Cc: Mattijs Korpershoek Cc: Sean Anderson Cc: Cody Schuffelen Tested-by: Mattijs Korpershoek # on vim3 Reviewed-by: Mattijs Korpershoek --- cmd/bcb.c | 161 ++++++++++++++++++++++++++++--------------- drivers/fastboot/fb_common.c | 14 +++- include/bcb.h | 60 +++++++++++++++- 3 files changed, 177 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/cmd/bcb.c b/cmd/bcb.c index 6594ac64396..f3b92564d10 100644 --- a/cmd/bcb.c +++ b/cmd/bcb.c @@ -25,10 +25,18 @@ enum bcb_cmd { BCB_CMD_STORE, }; -static enum uclass_id bcb_uclass_id = UCLASS_INVALID; -static int bcb_dev = -1; -static int bcb_part = -1; +static const char * const fields[] = { + "command", + "status", + "recovery", + "stage" +}; + static struct bootloader_message bcb __aligned(ARCH_DMA_MINALIGN) = { { 0 } }; +static struct disk_partition partition_data; + +static struct blk_desc *block; +static struct disk_partition *partition = &partition_data; static int bcb_cmd_get(char *cmd) { @@ -82,7 +90,7 @@ static int bcb_is_misused(int argc, char *const argv[]) return -1; } - if (cmd != BCB_CMD_LOAD && (bcb_dev < 0 || bcb_part < 0)) { + if (cmd != BCB_CMD_LOAD && !block) { printf("Error: Please, load BCB first!\n"); return -1; } @@ -94,7 +102,7 @@ err: return -1; } -static int bcb_field_get(char *name, char **fieldp, int *sizep) +static int bcb_field_get(const char *name, char **fieldp, int *sizep) { if (!strcmp(name, "command")) { *fieldp = bcb.command; @@ -119,16 +127,21 @@ static int bcb_field_get(char *name, char **fieldp, int *sizep) return 0; } -static int __bcb_load(const char *iface, int devnum, const char *partp) +static void __bcb_reset(void) +{ + block = NULL; + partition = &partition_data; + memset(&partition_data, 0, sizeof(struct disk_partition)); + memset(&bcb, 0, sizeof(struct bootloader_message)); +} + +static int __bcb_initialize(const char *iface, int devnum, const char *partp) { - struct blk_desc *desc; - struct disk_partition info; - u64 cnt; char *endp; int part, ret; - desc = blk_get_dev(iface, devnum); - if (!desc) { + block = blk_get_dev(iface, devnum); + if (!block) { ret = -ENODEV; goto err_read_fail; } @@ -137,7 +150,7 @@ static int __bcb_load(const char *iface, int devnum, const char *partp) * always select the first hwpart in case another * blk operation selected a different hwpart */ - ret = blk_dselect_hwpart(desc, 0); + ret = blk_dselect_hwpart(block, 0); if (IS_ERR_VALUE(ret)) { ret = -ENODEV; goto err_read_fail; @@ -145,49 +158,60 @@ static int __bcb_load(const char *iface, int devnum, const char *partp) part = simple_strtoul(partp, &endp, 0); if (*endp == '\0') { - ret = part_get_info(desc, part, &info); + ret = part_get_info(block, part, partition); if (ret) goto err_read_fail; } else { - part = part_get_info_by_name(desc, partp, &info); + part = part_get_info_by_name(block, partp, partition); if (part < 0) { ret = part; goto err_read_fail; } } - cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); - if (cnt > info.size) + return CMD_RET_SUCCESS; + +err_read_fail: + printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); + __bcb_reset(); + return CMD_RET_FAILURE; +} + +static int __bcb_load(void) +{ + u64 cnt; + int ret; + + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz); + if (cnt > partition->size) goto err_too_small; - if (blk_dread(desc, info.start, cnt, &bcb) != cnt) { + if (blk_dread(block, partition->start, cnt, &bcb) != cnt) { ret = -EIO; goto err_read_fail; } - bcb_uclass_id = desc->uclass_id; - bcb_dev = desc->devnum; - bcb_part = part; - debug("%s: Loaded from %s %d:%d\n", __func__, iface, bcb_dev, bcb_part); + debug("%s: Loaded from %d %d:%s\n", __func__, block->uclass_id, + block->devnum, partition->name); return CMD_RET_SUCCESS; err_read_fail: - printf("Error: %s %d:%s read failed (%d)\n", iface, devnum, partp, ret); + printf("Error: %d %d:%s read failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); goto err; err_too_small: - printf("Error: %s %d:%s too small!", iface, devnum, partp); - goto err; + printf("Error: %d %d:%s too small!", block->uclass_id, + block->devnum, partition->name); err: - bcb_uclass_id = UCLASS_INVALID; - bcb_dev = -1; - bcb_part = -1; - + __bcb_reset(); return CMD_RET_FAILURE; } static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { + int ret; int devnum; char *endp; char *iface = "mmc"; @@ -204,10 +228,14 @@ static int do_bcb_load(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - return __bcb_load(iface, devnum, argv[2]); + ret = __bcb_initialize(iface, devnum, argv[2]); + if (ret != CMD_RET_SUCCESS) + return ret; + + return __bcb_load(); } -static int __bcb_set(char *fieldp, const char *valp) +static int __bcb_set(const char *fieldp, const char *valp) { int size, len; char *field, *str, *found, *tmp; @@ -307,31 +335,20 @@ static int do_bcb_dump(struct cmd_tbl *cmdtp, int flag, int argc, static int __bcb_store(void) { - struct blk_desc *desc; - struct disk_partition info; u64 cnt; int ret; - desc = blk_get_devnum_by_uclass_id(bcb_uclass_id, bcb_dev); - if (!desc) { - ret = -ENODEV; - goto err; - } + cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), partition->blksz); - ret = part_get_info(desc, bcb_part, &info); - if (ret) - goto err; - - cnt = DIV_ROUND_UP(sizeof(struct bootloader_message), info.blksz); - - if (blk_dwrite(desc, info.start, cnt, &bcb) != cnt) { + if (blk_dwrite(block, partition->start, cnt, &bcb) != cnt) { ret = -EIO; goto err; } return CMD_RET_SUCCESS; err: - printf("Error: %d %d:%d write failed (%d)\n", bcb_uclass_id, bcb_dev, bcb_part, ret); + printf("Error: %d %d:%s write failed (%d)\n", block->uclass_id, + block->devnum, partition->name, ret); return CMD_RET_FAILURE; } @@ -342,23 +359,59 @@ static int do_bcb_store(struct cmd_tbl *cmdtp, int flag, int argc, return __bcb_store(); } -int bcb_write_reboot_reason(const char *iface, int devnum, char *partp, const char *reasonp) +int bcb_find_partition_and_load(const char *iface, int devnum, char *partp) { int ret; - ret = __bcb_load(iface, devnum, partp); - if (ret != CMD_RET_SUCCESS) - return ret; + __bcb_reset(); - ret = __bcb_set("command", reasonp); + ret = __bcb_initialize(iface, devnum, partp); if (ret != CMD_RET_SUCCESS) return ret; - ret = __bcb_store(); - if (ret != CMD_RET_SUCCESS) - return ret; + return __bcb_load(); +} - return 0; +int bcb_load(struct blk_desc *block_description, struct disk_partition *disk_partition) +{ + __bcb_reset(); + + block = block_description; + partition = disk_partition; + + return __bcb_load(); +} + +int bcb_set(enum bcb_field field, const char *value) +{ + if (field > BCB_FIELD_STAGE) + return CMD_RET_FAILURE; + return __bcb_set(fields[field], value); +} + +int bcb_get(enum bcb_field field, char *value_out, size_t value_size) +{ + int size; + char *field_value; + + if (field > BCB_FIELD_STAGE) + return CMD_RET_FAILURE; + if (bcb_field_get(fields[field], &field_value, &size)) + return CMD_RET_FAILURE; + + strlcpy(value_out, field_value, value_size); + + return CMD_RET_SUCCESS; +} + +int bcb_store(void) +{ + return __bcb_store(); +} + +void bcb_reset(void) +{ + __bcb_reset(); } static struct cmd_tbl cmd_bcb_sub[] = { diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 2a6608b28c2..3576b067729 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -91,6 +91,7 @@ void fastboot_okay(const char *reason, char *response) */ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) { + int ret; static const char * const boot_cmds[] = { [FASTBOOT_REBOOT_REASON_BOOTLOADER] = "bootonce-bootloader", [FASTBOOT_REBOOT_REASON_FASTBOOTD] = "boot-fastboot", @@ -105,7 +106,18 @@ int __weak fastboot_set_reboot_flag(enum fastboot_reboot_reason reason) if (reason >= FASTBOOT_REBOOT_REASONS_COUNT) return -EINVAL; - return bcb_write_reboot_reason("mmc", mmc_dev, "misc", boot_cmds[reason]); + ret = bcb_find_partition_and_load("mmc", mmc_dev, "misc"); + if (ret) + goto out; + + ret = bcb_set(BCB_FIELD_COMMAND, boot_cmds[reason]); + if (ret) + goto out; + + ret = bcb_store(); +out: + bcb_reset(); + return ret; } /** diff --git a/include/bcb.h b/include/bcb.h index a6326523c47..1941d8c28b4 100644 --- a/include/bcb.h +++ b/include/bcb.h @@ -8,15 +8,69 @@ #ifndef __BCB_H__ #define __BCB_H__ +#include + +enum bcb_field { + BCB_FIELD_COMMAND, + BCB_FIELD_STATUS, + BCB_FIELD_RECOVERY, + BCB_FIELD_STAGE +}; + #if IS_ENABLED(CONFIG_CMD_BCB) -int bcb_write_reboot_reason(const char *iface, int devnum, char *partp, const char *reasonp); + +int bcb_find_partition_and_load(const char *iface, + int devnum, char *partp); +int bcb_load(struct blk_desc *block_description, + struct disk_partition *disk_partition); +int bcb_set(enum bcb_field field, const char *value); + +/** + * bcb_get() - get the field value. + * @field: field to get + * @value_out: buffer to copy bcb field value to + * @value_size: buffer size to avoid overflow in case + * value_out is smaller then the field value + */ +int bcb_get(enum bcb_field field, char *value_out, size_t value_size); + +int bcb_store(void); +void bcb_reset(void); + #else + #include -static inline int bcb_write_reboot_reason(const char *iface, int devnum, - char *partp, const char *reasonp) + +static inline int bcb_load(struct blk_desc *block_description, + struct disk_partition *disk_partition) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_find_partition_and_load(const char *iface, + int devnum, char *partp) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_set(enum bcb_field field, const char *value) +{ + return -EOPNOTSUPP; +} + +static inline int bcb_get(enum bcb_field field, char *value_out) { return -EOPNOTSUPP; } + +static inline int bcb_store(void) +{ + return -EOPNOTSUPP; +} + +static inline void bcb_reset(void) +{ +} #endif #endif /* __BCB_H__ */ -- cgit v1.3.1 From 8cf18da1a971dbfe121c1fc1836bb4af942d06dc Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Fri, 10 Nov 2023 13:25:35 +0900 Subject: net: wget: add wget with dns utility function Current wget takes the target uri in this format: ":" e.g.) 192.168.1.1:/bar The http server ip address must be resolved before calling wget. This commit adds the utility function runs wget with dhs. User can call wget with the uri like "http://foo/bar". Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas Reviewed-by: Ramon Fried Reviewed-by: Simon Glass Signed-off-by: Ilias Apalodimas --- include/net.h | 9 +++++++++ net/wget.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) (limited to 'include') diff --git a/include/net.h b/include/net.h index e63a946002d..61f9018769a 100644 --- a/include/net.h +++ b/include/net.h @@ -930,4 +930,13 @@ void eth_set_enable_bootdevs(bool enable); static inline void eth_set_enable_bootdevs(bool enable) {} #endif +/** + * wget_with_dns() - runs dns host IP address resulution before wget + * + * @dst_addr: destination address to download the file + * @uri: uri string of target file of wget + * Return: downloaded file size, negative if failed + */ +int wget_with_dns(ulong dst_addr, char *uri); + #endif /* __NET_H__ */ diff --git a/net/wget.c b/net/wget.c index 6f97eb1d125..2087146b377 100644 --- a/net/wget.c +++ b/net/wget.c @@ -15,6 +15,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -512,3 +513,56 @@ void wget_start(void) wget_send(TCP_SYN, 0, 0, 0); } + +#if (IS_ENABLED(CONFIG_CMD_DNS)) +int wget_with_dns(ulong dst_addr, char *uri) +{ + int ret; + char *s, *host_name, *file_name, *str_copy; + + /* + * Download file using wget. + * + * U-Boot wget takes the target uri in this format. + * ":" e.g.) 192.168.1.1:/sample/test.iso + * Need to resolve the http server ip address before starting wget. + */ + str_copy = strdup(uri); + if (!str_copy) + return -ENOMEM; + + s = str_copy + strlen("http://"); + host_name = strsep(&s, "/"); + if (!s) { + log_err("Error: invalied uri, no file path\n"); + ret = -EINVAL; + goto out; + } + file_name = s; + + /* TODO: If the given uri has ip address for the http server, skip dns */ + net_dns_resolve = host_name; + net_dns_env_var = "httpserverip"; + if (net_loop(DNS) < 0) { + log_err("Error: dns lookup of %s failed, check setup\n", net_dns_resolve); + ret = -EINVAL; + goto out; + } + s = env_get("httpserverip"); + if (!s) { + ret = -EINVAL; + goto out; + } + + strlcpy(net_boot_file_name, s, sizeof(net_boot_file_name)); + strlcat(net_boot_file_name, ":/", sizeof(net_boot_file_name)); /* append '/' which is removed by strsep() */ + strlcat(net_boot_file_name, file_name, sizeof(net_boot_file_name)); + image_load_addr = dst_addr; + ret = net_loop(WGET); + +out: + free(str_copy); + + return ret; +} +#endif -- cgit v1.3.1 From d822255d653421bdcda9d6f443929a5b67ca4454 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Fri, 10 Nov 2023 13:25:36 +0900 Subject: blk: blkmap: add ramdisk creation utility function User needs to call several functions to create the ramdisk with blkmap. This adds the utility function to create blkmap device and mount the ramdisk. Signed-off-by: Masahisa Kojima Reviewed-by: Simon Glass Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- drivers/block/Makefile | 3 ++- drivers/block/blkmap.c | 15 ------------ drivers/block/blkmap_helper.c | 53 +++++++++++++++++++++++++++++++++++++++++++ include/blkmap.h | 29 +++++++++++++++++++++++ 4 files changed, 84 insertions(+), 16 deletions(-) create mode 100644 drivers/block/blkmap_helper.c (limited to 'include') diff --git a/drivers/block/Makefile b/drivers/block/Makefile index fdcba5c8318..fe6a1fcf486 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -15,7 +15,8 @@ obj-$(CONFIG_RKMTD) += rkmtd.o endif obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o obj-$(CONFIG_$(SPL_TPL_)BLOCK_CACHE) += blkcache.o -obj-$(CONFIG_BLKMAP) += blkmap.o +obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap.o +obj-$(CONFIG_$(SPL_TPL_)BLKMAP) += blkmap_helper.o obj-$(CONFIG_EFI_MEDIA) += efi-media-uclass.o obj-$(CONFIG_EFI_MEDIA_SANDBOX) += sb_efi_media.o diff --git a/drivers/block/blkmap.c b/drivers/block/blkmap.c index 149a4cac3ea..21201409ed4 100644 --- a/drivers/block/blkmap.c +++ b/drivers/block/blkmap.c @@ -66,21 +66,6 @@ struct blkmap_slice { void (*destroy)(struct blkmap *bm, struct blkmap_slice *bms); }; -/** - * struct blkmap - Block map - * - * Data associated with a blkmap. - * - * @label: Human readable name of this blkmap - * @blk: Underlying block device - * @slices: List of slices associated with this blkmap - */ -struct blkmap { - char *label; - struct udevice *blk; - struct list_head slices; -}; - static bool blkmap_slice_contains(struct blkmap_slice *bms, lbaint_t blknr) { return (blknr >= bms->blknr) && (blknr < (bms->blknr + bms->blkcnt)); diff --git a/drivers/block/blkmap_helper.c b/drivers/block/blkmap_helper.c new file mode 100644 index 00000000000..bfba14110d2 --- /dev/null +++ b/drivers/block/blkmap_helper.c @@ -0,0 +1,53 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * blkmap helper function + * + * Copyright (c) 2023, Linaro Limited + */ + +#include +#include +#include +#include + +int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size, + struct udevice **devp) +{ + int ret; + lbaint_t blknum; + struct blkmap *bm; + struct blk_desc *desc; + struct udevice *bm_dev; + + ret = blkmap_create(label, &bm_dev); + if (ret) { + log_err("failed to create blkmap\n"); + return ret; + } + + bm = dev_get_plat(bm_dev); + desc = dev_get_uclass_plat(bm->blk); + blknum = image_size >> desc->log2blksz; + ret = blkmap_map_pmem(bm_dev, 0, blknum, image_addr); + if (ret) { + log_err("Unable to map %#llx at block %d : %d\n", + (unsigned long long)image_addr, 0, ret); + goto err; + } + log_info("Block %d+0x" LBAF " mapped to %#llx\n", 0, blknum, + (unsigned long long)image_addr); + + ret = device_probe(bm->blk); + if (ret) + goto err; + + if (devp) + *devp = bm_dev; + + return 0; + +err: + blkmap_destroy(bm_dev); + + return ret; +} diff --git a/include/blkmap.h b/include/blkmap.h index af54583c7dd..30dc84a7da8 100644 --- a/include/blkmap.h +++ b/include/blkmap.h @@ -7,6 +7,23 @@ #ifndef _BLKMAP_H #define _BLKMAP_H +#include + +/** + * struct blkmap - Block map + * + * Data associated with a blkmap. + * + * @label: Human readable name of this blkmap + * @blk: Underlying block device + * @slices: List of slices associated with this blkmap + */ +struct blkmap { + char *label; + struct udevice *blk; + struct list_head slices; +}; + /** * blkmap_map_linear() - Map region of other block device * @@ -74,4 +91,16 @@ int blkmap_create(const char *label, struct udevice **devp); */ int blkmap_destroy(struct udevice *dev); +/** + * blkmap_create_ramdisk() - Create new ramdisk with blkmap + * + * @label: Label of the new blkmap + * @image_addr: Target memory start address of this mapping + * @image_size: Target memory size of this mapping + * @devp: Updated with the address of the created blkmap device + * Returns: 0 on success, negative error code on failure + */ +int blkmap_create_ramdisk(const char *label, ulong image_addr, ulong image_size, + struct udevice **devp); + #endif /* _BLKMAP_H */ -- cgit v1.3.1 From e23c8e81ebc97bbe9d4037b1324994446c2bc6c4 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Fri, 10 Nov 2023 13:25:38 +0900 Subject: efi_loader: add missing const classifier for event service const classifier is missing in EventGroup parameter of CreateEventEx(). Fix it to remove the compiler warning. NotifyContext parameter of CreateEventEx() is also defined with const in UEFI specification, but NotifyContext parameter of CreateEvent() is defined without const. Since current implementation calls the common efi_create_event() function from both CreateEventEx() and CreateEvent() services, NotifyContext parameter leaves as is. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/efi_api.h | 2 +- include/efi_loader.h | 2 +- lib/efi_loader/efi_boottime.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/efi_api.h b/include/efi_api.h index 8f5ef5f680f..c2d69644679 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -192,7 +192,7 @@ struct efi_boot_services { struct efi_event *event, void *context), void *notify_context, - efi_guid_t *event_group, + const efi_guid_t *event_group, struct efi_event **event); }; diff --git a/include/efi_loader.h b/include/efi_loader.h index 247be060e1c..1fd7b0b73c9 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -684,7 +684,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, efi_guid_t *group, + void *notify_context, const efi_guid_t *group, struct efi_event **event); /* Call this to set a timer */ efi_status_t efi_set_timer(struct efi_event *event, enum efi_timer_delay type, diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index 0b7579cb5af..f9b10a9763b 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -712,7 +712,7 @@ efi_status_t efi_create_event(uint32_t type, efi_uintn_t notify_tpl, void (EFIAPI *notify_function) ( struct efi_event *event, void *context), - void *notify_context, efi_guid_t *group, + void *notify_context, const efi_guid_t *group, struct efi_event **event) { struct efi_event *evt; @@ -790,7 +790,7 @@ efi_status_t EFIAPI efi_create_event_ex(uint32_t type, efi_uintn_t notify_tpl, struct efi_event *event, void *context), void *notify_context, - efi_guid_t *event_group, + const efi_guid_t *event_group, struct efi_event **event) { efi_status_t ret; -- cgit v1.3.1 From e0d1a1ea68c47b29d93bfc375d984fe0aee21093 Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Fri, 10 Nov 2023 13:25:39 +0900 Subject: efi_loader: add return to efibootmgr event group When the image loaded by efibootmgr returns, efibootmgr needs to clean the resources. Adding the event of returning to efibootmgr is useful to simplify the implementation. Signed-off-by: Masahisa Kojima Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- cmd/bootefi.c | 12 ++++++++++++ include/efi_api.h | 3 +++ include/efi_loader.h | 2 ++ lib/efi_loader/efi_boottime.c | 3 +++ 4 files changed, 20 insertions(+) (limited to 'include') diff --git a/cmd/bootefi.c b/cmd/bootefi.c index 20e5c94a33a..4d74969ad62 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -356,6 +356,7 @@ static efi_status_t do_bootefi_exec(efi_handle_t handle, void *load_options) efi_status_t ret; efi_uintn_t exit_data_size = 0; u16 *exit_data = NULL; + struct efi_event *evt; /* On ARM switch from EL3 or secure mode to EL2 or non-secure mode */ switch_to_non_secure_mode(); @@ -394,6 +395,17 @@ out: log_err("Failed to remove loadfile2 for initrd\n"); } + /* Notify EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR event group. */ + list_for_each_entry(evt, &efi_events, link) { + if (evt->group && + !guidcmp(evt->group, + &efi_guid_event_group_return_to_efibootmgr)) { + efi_signal_event(evt); + EFI_CALL(systab.boottime->close_event(evt)); + break; + } + } + /* Control is returned to U-Boot, disable EFI watchdog */ efi_set_watchdog(0); diff --git a/include/efi_api.h b/include/efi_api.h index c2d69644679..0e92cb8a7f6 100644 --- a/include/efi_api.h +++ b/include/efi_api.h @@ -404,6 +404,9 @@ struct efi_runtime_services { #define EFI_EVENT_GROUP_RESET_SYSTEM \ EFI_GUID(0x62da6a56, 0x13fb, 0x485a, 0xa8, 0xda, \ 0xa3, 0xdd, 0x79, 0x12, 0xcb, 0x6b) +#define EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR \ + EFI_GUID(0xb4a40fe6, 0x9149, 0x4f29, 0x94, 0x47, \ + 0x49, 0x38, 0x7a, 0x7f, 0xab, 0x87) /* EFI Configuration Table and GUID definitions */ #define NULL_GUID \ diff --git a/include/efi_loader.h b/include/efi_loader.h index 1fd7b0b73c9..664dae28f88 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -289,6 +289,8 @@ extern const efi_guid_t efi_guid_event_group_memory_map_change; extern const efi_guid_t efi_guid_event_group_ready_to_boot; /* event group ResetSystem() invoked (before ExitBootServices) */ extern const efi_guid_t efi_guid_event_group_reset_system; +/* event group return to efibootmgr */ +extern const efi_guid_t efi_guid_event_group_return_to_efibootmgr; /* GUID of the device tree table */ extern const efi_guid_t efi_guid_fdt; extern const efi_guid_t efi_guid_loaded_image; diff --git a/lib/efi_loader/efi_boottime.c b/lib/efi_loader/efi_boottime.c index f9b10a9763b..3767fa2db42 100644 --- a/lib/efi_loader/efi_boottime.c +++ b/lib/efi_loader/efi_boottime.c @@ -90,6 +90,9 @@ const efi_guid_t efi_guid_event_group_ready_to_boot = /* event group ResetSystem() invoked (before ExitBootServices) */ const efi_guid_t efi_guid_event_group_reset_system = EFI_EVENT_GROUP_RESET_SYSTEM; +/* event group return to efibootmgr */ +const efi_guid_t efi_guid_event_group_return_to_efibootmgr = + EFI_EVENT_GROUP_RETURN_TO_EFIBOOTMGR; /* GUIDs of the Load File and Load File2 protocols */ const efi_guid_t efi_guid_load_file_protocol = EFI_LOAD_FILE_PROTOCOL_GUID; const efi_guid_t efi_guid_load_file2_protocol = EFI_LOAD_FILE2_PROTOCOL_GUID; -- cgit v1.3.1 From f01c961ee34c0124ce53020970ba11b0ab316d9e Mon Sep 17 00:00:00 2001 From: Masahisa Kojima Date: Fri, 10 Nov 2023 13:25:41 +0900 Subject: cmd: efidebug: add uri device path This adds the URI device path option for 'boot add' subcommand. User can add the URI load option for downloading ISO image file or EFI application through network. Currently HTTP is only supported. Signed-off-by: Masahisa Kojima Signed-off-by: Ilias Apalodimas --- cmd/efidebug.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/net.h | 8 ++++++ net/wget.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 157 insertions(+) (limited to 'include') diff --git a/cmd/efidebug.c b/cmd/efidebug.c index 201531ac19f..78ef16f4cb5 100644 --- a/cmd/efidebug.c +++ b/cmd/efidebug.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -707,6 +708,65 @@ out: return initrd_dp; } +/** + * efi_boot_add_uri() - set URI load option + * + * @argc: Number of arguments + * @argv: Argument array + * @var_name16: variable name buffer + * @var_name16_size: variable name buffer size + * @lo: pointer to the load option + * @file_path: buffer to set the generated device path pointer + * @fp_size: file_path size + * Return: CMD_RET_SUCCESS on success, + * CMD_RET_USAGE or CMD_RET_RET_FAILURE on failure + */ +static int efi_boot_add_uri(int argc, char *const argv[], u16 *var_name16, + size_t var_name16_size, struct efi_load_option *lo, + struct efi_device_path **file_path, + efi_uintn_t *fp_size) +{ + int id; + char *pos; + char *endp; + u16 *label; + efi_uintn_t uridp_len; + struct efi_device_path_uri *uridp; + + if (argc < 3 || lo->label) + return CMD_RET_USAGE; + + id = (int)hextoul(argv[1], &endp); + if (*endp != '\0' || id > 0xffff) + return CMD_RET_USAGE; + + label = efi_convert_string(argv[2]); + if (!label) + return CMD_RET_FAILURE; + + if (!wget_validate_uri(argv[3])) { + printf("ERROR: invalid URI\n"); + return CMD_RET_FAILURE; + } + + efi_create_indexed_name(var_name16, var_name16_size, "Boot", id); + lo->label = label; + + uridp_len = sizeof(struct efi_device_path) + strlen(argv[3]) + 1; + uridp = efi_alloc(uridp_len + sizeof(END)); + uridp->dp.type = DEVICE_PATH_TYPE_MESSAGING_DEVICE; + uridp->dp.sub_type = DEVICE_PATH_SUB_TYPE_MSG_URI; + uridp->dp.length = uridp_len; + strcpy(uridp->uri, argv[3]); + pos = (char *)uridp + uridp_len; + memcpy(pos, &END, sizeof(END)); + + *file_path = &uridp->dp; + *fp_size += uridp_len + sizeof(END); + + return CMD_RET_SUCCESS; +} + /** * do_efi_boot_add() - set UEFI load option * @@ -829,6 +889,21 @@ static int do_efi_boot_add(struct cmd_tbl *cmdtp, int flag, argc -= 1; argv += 1; break; + case 'u': + if (IS_ENABLED(CONFIG_EFI_HTTP_BOOT)) { + r = efi_boot_add_uri(argc, argv, var_name16, + sizeof(var_name16), &lo, + &file_path, &fp_size); + if (r != CMD_RET_SUCCESS) + goto out; + fp_free = file_path; + argc -= 3; + argv += 3; + } else{ + r = CMD_RET_USAGE; + goto out; + } + break; default: r = CMD_RET_USAGE; goto out; @@ -1491,6 +1566,9 @@ U_BOOT_LONGHELP(efidebug, " -b|-B