From e8d9ad18f068f65537bc04779d6110a1058bfb1e Mon Sep 17 00:00:00 2001 From: Kory Maincent Date: Mon, 19 Jan 2026 17:07:41 +0100 Subject: fwu: Pass bank state enum to fwu_state_machine_updates() Change fwu_state_machine_updates() to accept an enum fwu_bank_states parameter instead of a boolean. This makes the function interface more explicit and prepares for adding FWU_BANK_INVALID support to handle boot failures on the active bank. Convert the FWU_BANK_* defines to an enum and update all call sites accordingly. Signed-off-by: Kory Maincent Reviewed-by: Ilias Apalodimas Signed-off-by: Ilias Apalodimas --- include/fwu.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/fwu.h b/include/fwu.h index e7bd1d492af..9cee8fb085c 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -80,9 +80,11 @@ struct fwu_mdata_ops { #define FWU_IMAGE_ACCEPTED 0x1 -#define FWU_BANK_INVALID (uint8_t)0xFF -#define FWU_BANK_VALID (uint8_t)0xFE -#define FWU_BANK_ACCEPTED (uint8_t)0xFC +enum fwu_bank_states { + FWU_BANK_INVALID = 0xFF, + FWU_BANK_VALID = 0xFE, + FWU_BANK_ACCEPTED = 0xFC, +}; enum { PRIMARY_PART = 1, @@ -396,24 +398,24 @@ int fwu_get_mdata_size(uint32_t *mdata_size); /** * fwu_state_machine_updates() - Update FWU state of the platform - * @trial_state: Is platform transitioning into Trial State + * @state: FWU bank state * @update_index: Bank number to which images have been updated * - * On successful completion of updates, transition the platform to - * either Trial State or Regular State. + * FWU_BANK_VALID transition the platform to Trial state + * FWU_BANK_ACCEPTED accept the FWU bank state + * FWU_BANK_INVALID invalid the FWU bank state * * To transition the platform to Trial State, start the * TrialStateCtr counter, followed by setting the value of bank_state * field of the metadata to Valid state(applicable only in version 2 * of metadata). * - * In case, the platform is to transition directly to Regular State, - * update the bank_state field of the metadata to Accepted - * state(applicable only in version 2 of metadata). + * Saving the bank_state field of the metadata is only applicable in + * version 2 of metadata. * * Return: 0 if OK, -ve on error */ -int fwu_state_machine_updates(bool trial_state, uint32_t update_index); +int fwu_state_machine_updates(enum fwu_bank_states state, uint32_t update_index); /** * fwu_init() - FWU specific initialisations -- cgit v1.3.1 From 7105f8f2958b23823388ac4963caffeed5fe607c Mon Sep 17 00:00:00 2001 From: Pranav Sanwal Date: Thu, 29 Jan 2026 17:30:20 +0530 Subject: fdtdec: Add declaration for get_next_memory_node() helper Add get_next_memory_node() function declaration to fdtdec.h to support iterating through multiple memory nodes in device tree. This function is used to enumerate memory banks when the system has non-contiguous or multiple memory regions defined with device_type = "memory". The function implementation already exists in lib/fdtdec.c (lines 1298-1305) but was missing the public declaration in the header file. This patch adds the declaration and includes dm/ofnode_decl.h for the ofnode type definition. This is needed for platforms that require early memory enumeration before standard fdtdec_setup_memory_banksize() is called, particularly for dynamic MMU page table size calculation based on actual DRAM configuration. Signed-off-by: Pranav Sanwal Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260129120021.1328653-2-pranav.sanwal@amd.com --- include/fdtdec.h | 24 ++++++++++++++++++++++++ lib/fdtdec.c | 7 ++++++- 2 files changed, 30 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index d9fcd037ed2..4e09f9d718c 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -16,6 +16,7 @@ #include #include +#include /* * Support for 64bit fdt addresses. @@ -198,6 +199,29 @@ struct fdtdec_phandle_args { uint32_t args[MAX_PHANDLE_ARGS]; }; +/** + * fdtdec_get_next_memory_node() - Get the next enabled memory node from device tree + * + * @mem: Current memory node to start search from, or ofnode_null() to get first node + * + * This function iterates through device tree nodes with device_type = "memory" + * property, automatically skipping disabled nodes (status != "okay"). + * + * It is used to enumerate multiple memory regions when the system has + * non-contiguous or multiple memory banks defined in the device tree. + * The function continues searching from the given node onwards, looking + * for the next node with the "memory" device_type property and checking + * its status property. + * + * Can be called multiple times to iterate through all memory nodes. + * Pass ofnode_null() on first call, then pass the returned node + * on subsequent calls until an invalid node is returned. + * + * Return: Next valid, enabled memory ofnode, or invalid ofnode if no more + * memory nodes exist + */ +ofnode fdtdec_get_next_memory_node(ofnode mem); + /** * fdtdec_parse_phandle_with_args() - Find a node pointed by phandle in a list * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index c38738b48c7..3779076377f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1083,7 +1083,7 @@ int fdtdec_setup_mem_size_base(void) return 0; } -ofnode get_next_memory_node(ofnode mem) +static ofnode get_next_memory_node(ofnode mem) { do { mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); @@ -1092,6 +1092,11 @@ ofnode get_next_memory_node(ofnode mem) return mem; } +ofnode fdtdec_get_next_memory_node(ofnode mem) +{ + return get_next_memory_node(mem); +} + int fdtdec_setup_memory_banksize(void) { int bank, ret, reg = 0; -- cgit v1.3.1 From df1875ea31df7762d3e4417438f5ff7563e15502 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Thu, 29 Jan 2026 13:40:11 -0500 Subject: pinctrl: zynqmp: Add SPL support Although the pinctrl pm requests are implemented in the PMU firmware, PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in EL3), ATF is not yet running, so we need to implement this API ourselves. Do the bare minimum, allowing SPL to enumerate functions, but don't bother with groups. Groups take up a lot of space, and can be emulated with pins. For example, a node like display-port { mux { groups = "dpaux0_1"; function = "dpaux0"; }; }; can be replaced by display-port { mux { pins = "MIO34", "MIO35", "MIO36", "MIO37"; function = "dpaux0"; }; }; While this isn't backwards-compatible with existing devicetrees, it's more than enough for SPL where we may only need to mux one or two pins. Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl is enabled in U-Boot but isn't necessary for SPL. The only config this would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so SPL_PINCTRL_ZYNQMP is not selected. Signed-off-by: Sean Anderson Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/20260129184011.3932790-1-sean.anderson@linux.dev --- drivers/firmware/firmware-zynqmp.c | 101 +++++++++++++++++++++++++++++++++++++ drivers/pinctrl/Kconfig | 8 +++ drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/pinctrl-zynqmp.c | 8 +-- include/zynqmp_firmware.h | 5 ++ 5 files changed, 117 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index f8a9945c1da..fb583580ebe 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -427,6 +427,104 @@ U_BOOT_DRIVER(zynqmp_power) = { }; #endif +static const char *const pinctrl_functions[] = { + "can0", + "can1", + "ethernet0", + "ethernet1", + "ethernet2", + "ethernet3", + "gemtsu0", + "gpio0", + "i2c0", + "i2c1", + "mdio0", + "mdio1", + "mdio2", + "mdio3", + "qspi0", + "qspi_fbclk", + "qspi_ss", + "spi0", + "spi1", + "spi0_ss", + "spi1_ss", + "sdio0", + "sdio0_pc", + "sdio0_cd", + "sdio0_wp", + "sdio1", + "sdio1_pc", + "sdio1_cd", + "sdio1_wp", + "nand0", + "nand0_ce", + "nand0_rb", + "nand0_dqs", + "ttc0_clk", + "ttc0_wav", + "ttc1_clk", + "ttc1_wav", + "ttc2_clk", + "ttc2_wav", + "ttc3_clk", + "ttc3_wav", + "uart0", + "uart1", + "usb0", + "usb1", + "swdt0_clk", + "swdt0_rst", + "swdt1_clk", + "swdt1_rst", + "pmu0", + "pcie0", + "csu0", + "dpaux0", + "pjtag0", + "trace0", + "trace0_clk", + "testscan0", +}; + +/* + * PM_QUERY_DATA is implemented by ATF and not the PMU firmware, so we have to + * emulate it in SPL. Just implement functions/pins since the groups take up a + * lot of rodata and are mostly superfluous. + */ +static int zynqmp_pm_query_data(enum pm_query_id qid, u32 arg1, u32 arg2, + u32 *ret_payload) +{ + switch (qid) { + case PM_QID_PINCTRL_GET_NUM_PINS: + ret_payload[1] = 78; /* NUM_PINS */ + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTIONS: + ret_payload[1] = ARRAY_SIZE(pinctrl_functions); + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS: + ret_payload[1] = 0; + ret_payload[0] = 0; + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_NAME: + assert(arg1 < ARRAY_SIZE(pinctrl_functions)); + memset(ret_payload, 0, MAX_FUNC_NAME_LEN); + strcpy((char *)ret_payload, pinctrl_functions[arg1]); + return 0; + case PM_QID_PINCTRL_GET_FUNCTION_GROUPS: + case PM_QID_PINCTRL_GET_PIN_GROUPS: + memset(ret_payload + 1, 0xff, + sizeof(s16) * NUM_GROUPS_PER_RESP); + ret_payload[0] = 0; + return 0; + default: + ret_payload[0] = 1; + return 1; + } +} + smc_call_handler_t __data smc_call_handler; static int smc_call_legacy(u32 api_id, u32 arg0, u32 arg1, u32 arg2, @@ -493,6 +591,9 @@ int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, __func__, current_el(), api_id, arg0, arg1, arg2, arg3, arg4, arg5); if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { + if (CONFIG_IS_ENABLED(PINCTRL_ZYNQMP) && + api_id == PM_QUERY_DATA) + return zynqmp_pm_query_data(arg0, arg1, arg2, ret_payload); #if defined(CONFIG_ZYNQMP_IPI) /* * Use fixed payload and arg size as the EL2 call. The firmware diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index ea90713ec6c..73dd5ff4a79 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -386,6 +386,14 @@ config PINCTRL_ZYNQMP Generic Pinctrl framework and is compatible with the Linux driver, i.e. it uses the same device tree configuration. +config SPL_PINCTRL_ZYNQMP + bool "Xilinx ZynqMP pin control driver in SPL" + depends on SPL_DM && SPL_PINCTRL_GENERIC && ARCH_ZYNQMP + default PINCTRL_ZYNQMP + help + Support pin multiplexing control in SPL on Xilinx ZynqMP. Only "pins" + can be muxed; "groups" are not supported. + endif source "drivers/pinctrl/broadcom/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 33ff7b95ef2..4fb6cef3113 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -36,5 +36,5 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o obj-y += broadcom/ -obj-$(CONFIG_PINCTRL_ZYNQMP) += pinctrl-zynqmp.o +obj-$(CONFIG_$(PHASE_)PINCTRL_ZYNQMP) += pinctrl-zynqmp.o obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c index 7c11ac4c8b8..0b936684f8a 100644 --- a/drivers/pinctrl/pinctrl-zynqmp.c +++ b/drivers/pinctrl/pinctrl-zynqmp.c @@ -19,15 +19,11 @@ #include #include -#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN 12 -#define PINCTRL_GET_PIN_GROUPS_RESP_LEN 12 -#define NUM_GROUPS_PER_RESP 6 -#define NA_GROUP -1 -#define RESERVED_GROUP -2 +#define PINCTRL_GET_FUNC_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) +#define PINCTRL_GET_PIN_GROUPS_RESP_LEN (sizeof(s16) * NUM_GROUPS_PER_RESP) #define MAX_GROUP_PIN 50 #define MAX_PIN_GROUPS 50 #define MAX_GROUP_NAME_LEN 32 -#define MAX_FUNC_NAME_LEN 16 #define DRIVE_STRENGTH_2MA 2 #define DRIVE_STRENGTH_4MA 4 diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 05df49f292a..f5e72625e53 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -185,6 +185,11 @@ enum pm_query_id { PM_QID_CLOCK_GET_MAX_DIVISOR = 13, }; +#define NUM_GROUPS_PER_RESP 6 +#define NA_GROUP -1 +#define RESERVED_GROUP -2 +#define MAX_FUNC_NAME_LEN 16 + enum pm_pinctrl_config_param { PM_PINCTRL_CONFIG_SLEW_RATE = 0, PM_PINCTRL_CONFIG_BIAS_STATUS = 1, -- cgit v1.3.1 From 59fa20f729789d12e7815fede6f5b3fb280dcdc9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Oct 2025 23:43:42 +0100 Subject: spi: Squash spi_slave_of_to_plat() into spi_child_post_bind() The spi_slave_of_to_plat() is called from one place, spi_child_post_bind(). Squash it into the later and remove the public declaration, make this function local static. No functional change. Signed-off-by: Marek Vasut --- drivers/spi/spi-uclass.c | 145 ++++++++++++++++++++++------------------------- include/spi.h | 11 ---- 2 files changed, 69 insertions(+), 87 deletions(-) (limited to 'include') diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 49b584c648d..a7a06312435 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -180,11 +180,79 @@ int spi_write_then_read(struct spi_slave *slave, const u8 *opcode, static int spi_child_post_bind(struct udevice *dev) { struct dm_spi_slave_plat *plat = dev_get_parent_plat(dev); + int __maybe_unused ret; + int mode = 0; + int value; if (!dev_has_ofnode(dev)) return 0; - return spi_slave_of_to_plat(dev, plat); +#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) + ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); + + if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { + dev_read_u32(dev, "reg", &plat->cs[0]); + } else { + dev_err(dev, "has no valid 'reg' property (%d)\n", ret); + return ret; + } +#else + plat->cs[0] = dev_read_u32_default(dev, "reg", -1); +#endif + + plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", + SPI_DEFAULT_SPEED_HZ); + if (dev_read_bool(dev, "spi-cpol")) + mode |= SPI_CPOL; + if (dev_read_bool(dev, "spi-cpha")) + mode |= SPI_CPHA; + if (dev_read_bool(dev, "spi-cs-high")) + mode |= SPI_CS_HIGH; + if (dev_read_bool(dev, "spi-3wire")) + mode |= SPI_3WIRE; + if (dev_read_bool(dev, "spi-half-duplex")) + mode |= SPI_PREAMBLE; + + /* Device DUAL/QUAD mode */ + value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_TX_DUAL; + break; + case 4: + mode |= SPI_TX_QUAD; + break; + case 8: + mode |= SPI_TX_OCTAL; + break; + default: + warn_non_xpl("spi-tx-bus-width %d not supported\n", value); + break; + } + + value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); + switch (value) { + case 1: + break; + case 2: + mode |= SPI_RX_DUAL; + break; + case 4: + mode |= SPI_RX_QUAD; + break; + case 8: + mode |= SPI_RX_OCTAL; + break; + default: + warn_non_xpl("spi-rx-bus-width %d not supported\n", value); + break; + } + + plat->mode = mode; + + return 0; } #endif @@ -511,81 +579,6 @@ void spi_free_slave(struct spi_slave *slave) device_remove(slave->dev, DM_REMOVE_NORMAL); } -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat) -{ - int mode = 0; - int value; - -#if CONFIG_IS_ENABLED(SPI_STACKED_PARALLEL) - int ret; - - ret = dev_read_u32_array(dev, "reg", plat->cs, SPI_CS_CNT_MAX); - - if (ret == -EOVERFLOW || ret == -FDT_ERR_BADLAYOUT) { - dev_read_u32(dev, "reg", &plat->cs[0]); - } else { - dev_err(dev, "has no valid 'reg' property (%d)\n", ret); - return ret; - } -#else - plat->cs[0] = dev_read_u32_default(dev, "reg", -1); -#endif - - plat->max_hz = dev_read_u32_default(dev, "spi-max-frequency", - SPI_DEFAULT_SPEED_HZ); - if (dev_read_bool(dev, "spi-cpol")) - mode |= SPI_CPOL; - if (dev_read_bool(dev, "spi-cpha")) - mode |= SPI_CPHA; - if (dev_read_bool(dev, "spi-cs-high")) - mode |= SPI_CS_HIGH; - if (dev_read_bool(dev, "spi-3wire")) - mode |= SPI_3WIRE; - if (dev_read_bool(dev, "spi-half-duplex")) - mode |= SPI_PREAMBLE; - - /* Device DUAL/QUAD mode */ - value = dev_read_u32_default(dev, "spi-tx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_TX_DUAL; - break; - case 4: - mode |= SPI_TX_QUAD; - break; - case 8: - mode |= SPI_TX_OCTAL; - break; - default: - warn_non_xpl("spi-tx-bus-width %d not supported\n", value); - break; - } - - value = dev_read_u32_default(dev, "spi-rx-bus-width", 1); - switch (value) { - case 1: - break; - case 2: - mode |= SPI_RX_DUAL; - break; - case 4: - mode |= SPI_RX_QUAD; - break; - case 8: - mode |= SPI_RX_OCTAL; - break; - default: - warn_non_xpl("spi-rx-bus-width %d not supported\n", value); - break; - } - - plat->mode = mode; - - return 0; -} - UCLASS_DRIVER(spi) = { .id = UCLASS_SPI, .name = "spi", diff --git a/include/spi.h b/include/spi.h index 2783200d663..95e7d5b1556 100644 --- a/include/spi.h +++ b/include/spi.h @@ -657,17 +657,6 @@ int spi_chip_select(struct udevice *slave); */ int spi_find_chip_select(struct udevice *bus, int cs, struct udevice **devp); -/** - * spi_slave_of_to_plat() - decode standard SPI platform data - * - * This decodes the speed and mode for a slave from a device tree node - * - * @blob: Device tree blob - * @node: Node offset to read from - * @plat: Place to put the decoded information - */ -int spi_slave_of_to_plat(struct udevice *dev, struct dm_spi_slave_plat *plat); - /** * spi_cs_info() - Check information on a chip select * -- cgit v1.3.1 From 97b17ecae8161bbe259d22fb50b39e549971e22a Mon Sep 17 00:00:00 2001 From: Brian Sune Date: Wed, 28 Jan 2026 22:18:15 +0800 Subject: Add CoreCourse socfpga Board - AC501 CoreCourse Altera GEN5 Cyclone V board do support different size and formfactor. Now introducing AC501 C5 to mainstream u-boot This is a UBGA-484 based board with basic feature. More info on [1] [1] https://corecourse.cn/forum.php?mod=viewthread&tid=27704&highlight=AC501 Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi | 44 ++ arch/arm/dts/socfpga_cyclone5_ac501soc.dts | 72 +++ arch/arm/mach-socfpga/Kconfig | 7 + board/corecourse/ac501soc/MAINTAINERS | 6 + board/corecourse/ac501soc/qts/iocsr_config.h | 664 +++++++++++++++++++++ board/corecourse/ac501soc/qts/pinmux_config.h | 222 +++++++ board/corecourse/ac501soc/qts/pll_config.h | 86 +++ board/corecourse/ac501soc/qts/sdram_config.h | 349 +++++++++++ configs/socfpga_ac501soc_defconfig | 85 +++ include/configs/socfpga_ac501soc.h | 13 + 11 files changed, 1549 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_ac501soc.dts create mode 100644 board/corecourse/ac501soc/MAINTAINERS create mode 100644 board/corecourse/ac501soc/qts/iocsr_config.h create mode 100644 board/corecourse/ac501soc/qts/pinmux_config.h create mode 100644 board/corecourse/ac501soc/qts/pll_config.h create mode 100644 board/corecourse/ac501soc/qts/sdram_config.h create mode 100644 configs/socfpga_ac501soc_defconfig create mode 100644 include/configs/socfpga_ac501soc.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 82ad3035308..1ade51e2dea 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -469,6 +469,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_socrates.dtb \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ + socfpga_cyclone5_ac501soc.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac501soc.dts b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts new file mode 100644 index 00000000000..6b02fa63c7c --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac501soc.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC501SoC"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index f2e959b5662..1a0fcd64296 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -239,6 +239,10 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_CORECOURSE_AC501SOC + bool "CoreCourse AC501SoC (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + endchoice config SYS_BOARD @@ -263,6 +267,7 @@ config SYS_BOARD default "sr1500" if TARGET_SOCFPGA_SR1500 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK @@ -284,6 +289,7 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC config SYS_SOC default "socfpga" @@ -310,5 +316,6 @@ config SYS_CONFIG_NAME default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA + default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC endif diff --git a/board/corecourse/ac501soc/MAINTAINERS b/board/corecourse/ac501soc/MAINTAINERS new file mode 100644 index 00000000000..1feac0c0584 --- /dev/null +++ b/board/corecourse/ac501soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune +S: Maintained +F: board/corecourse/ac501soc/ +F: include/configs/socfpga_ac501soc.h +F: configs/socfpga_ac501soc_defconfig diff --git a/board/corecourse/ac501soc/qts/iocsr_config.h b/board/corecourse/ac501soc/qts/iocsr_config.h new file mode 100644 index 00000000000..cce43c54377 --- /dev/null +++ b/board/corecourse/ac501soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x000C0300, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x80008000, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x00000000, + 0x00000010, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x300C0300, + 0x00000000, + 0x0FF00000, + 0x00000000, + 0x0C0300C0, + 0x00008000, + 0x18060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x00000030, + 0x00000000, + 0x0300C030, + 0x00002000, + 0x10018060, + 0x00000000, + 0x06000000, + 0x00010018, + 0x01806018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000800C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C420D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x41034030, + 0x02081A00, + 0x80A280D0, + 0x34030C06, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x00410340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0xC0680A28, + 0x49034030, + 0x12481A02, + 0x80A280D0, + 0x34030C06, + 0x01A00040, + 0x280D0002, + 0x30C0680A, + 0x02490340, + 0xD012481A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x05140680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A028A, + 0x0000D000, + 0x00000680, + 0xD559647A, + 0x1EF228A3, + 0x48F4D145, + 0x000352D3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0xFE120800, + 0x00000001, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x59647A05, + 0xF228A3D5, + 0xF4D1451E, + 0x03429248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00034AD3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0xF8482000, + 0x00000007, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x00FF090C, + 0x00000000, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0x69A47A05, + 0xF228A3D9, + 0xF4D1451E, + 0x0352D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD969A47A, + 0x1EF228A3, + 0x48F4D145, + 0x00035292, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x0000FF00, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0xC0000004, + 0x0000003F, + 0x0000FF00, + 0x03FC0000, + 0xF0000000, + 0x0000000F, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0xE0000002, + 0x0000001F, + 0x00007F80, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0xF0000001, + 0x0000000F, + 0x00003FC0, + 0x00FF0000, + 0xFC000000, + 0x00000003, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x0001FE00, + 0x07F80000, + 0xE0000000, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pinmux_config.h b/board/corecourse/ac501soc/qts/pinmux_config.h new file mode 100644 index 00000000000..462cde84565 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 1, /* GENERALIO3 */ + 1, /* GENERALIO4 */ + 1, /* GENERALIO5 */ + 1, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 3, /* GENERALIO9 */ + 3, /* GENERALIO10 */ + 3, /* GENERALIO11 */ + 3, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 1, /* GENERALIO15 */ + 1, /* GENERALIO16 */ + 1, /* GENERALIO17 */ + 1, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 0, /* MIXED1IO15 */ + 0, /* MIXED1IO16 */ + 0, /* MIXED1IO17 */ + 0, /* MIXED1IO18 */ + 0, /* MIXED1IO19 */ + 0, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 0, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 0, /* UART1USEFPGA */ + 0, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 0, /* I2C3USEFPGA */ + 0, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/pll_config.h b/board/corecourse/ac501soc/qts/pll_config.h new file mode 100644 index 00000000000..88e0b2a3776 --- /dev/null +++ b/board/corecourse/ac501soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac501soc/qts/sdram_config.h b/board/corecourse/ac501soc/qts/sdram_config.h new file mode 100644 index 00000000000..43cf307847e --- /dev/null +++ b/board/corecourse/ac501soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 401 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 12 +#define CALIB_VFIFO_OFFSET 10 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 312 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 31 +#define IO_DQS_EN_DELAY_OFFSET 0 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 99 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 99 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080471, + 0x10080570, + 0x10090006, + 0x100a0218, + 0x100b0000, + 0x10380400, + 0x10080469, + 0x100804e8, + 0x100a0006, + 0x10090218, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/configs/socfpga_ac501soc_defconfig b/configs/socfpga_ac501soc_defconfig new file mode 100644 index 00000000000..3d584a6a8a9 --- /dev/null +++ b/configs/socfpga_ac501soc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_ac501soc" +CONFIG_DM_RESET=y +CONFIG_SPL_STACK=0x0 +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_TARGET_SOCFPGA_CORECOURSE_AC501SOC=y +CONFIG_SPL_FS_FAT=y +# CONFIG_SPL_SPI is not set +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_ac501soc.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="corecourse" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_TOOLS_MKEFICAPSULE is not set +CONFIG_CMD_C5_PL330_DMA=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/include/configs/socfpga_ac501soc.h b/include/configs/socfpga_ac501soc.h new file mode 100644 index 00000000000..703520e7cb8 --- /dev/null +++ b/include/configs/socfpga_ac501soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC501SOC_H__ +#define __CONFIG_CORESOURCE_AC501SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC501SOC_H__ */ -- cgit v1.3.1 From 3d1dc5b79fe80b16eae2738e7f753752befa5881 Mon Sep 17 00:00:00 2001 From: Brian Sune Date: Wed, 28 Jan 2026 22:18:16 +0800 Subject: Add CoreCourse socfpga Board - AC550 CoreCourse Altera GEN5 Cyclone V board do support different size and formfactor. Now introducing AC550 C5 to mainstream u-boot This is a more complex and unified board with feature. More info on [1] [1] https://corecourse.cn/forum.php?mod=viewthread&tid=29788&extra=page%3D1 Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi | 44 ++ arch/arm/dts/socfpga_cyclone5_ac550soc.dts | 118 ++++ arch/arm/mach-socfpga/Kconfig | 7 + board/corecourse/ac550soc/MAINTAINERS | 6 + board/corecourse/ac550soc/qts/iocsr_config.h | 664 +++++++++++++++++++++ board/corecourse/ac550soc/qts/pinmux_config.h | 222 +++++++ board/corecourse/ac550soc/qts/pll_config.h | 86 +++ board/corecourse/ac550soc/qts/sdram_config.h | 349 +++++++++++ configs/socfpga_ac550soc_defconfig | 85 +++ include/configs/socfpga_ac550soc.h | 13 + 11 files changed, 1595 insertions(+) create mode 100644 arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_cyclone5_ac550soc.dts create mode 100644 board/corecourse/ac550soc/MAINTAINERS create mode 100644 board/corecourse/ac550soc/qts/iocsr_config.h create mode 100644 board/corecourse/ac550soc/qts/pinmux_config.h create mode 100644 board/corecourse/ac550soc/qts/pll_config.h create mode 100644 board/corecourse/ac550soc/qts/sdram_config.h create mode 100644 configs/socfpga_ac550soc_defconfig create mode 100644 include/configs/socfpga_ac550soc.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1ade51e2dea..264b13b6f5d 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -470,6 +470,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_sr1500.dtb \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_cyclone5_ac501soc.dtb \ + socfpga_cyclone5_ac550soc.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi new file mode 100644 index 00000000000..8d2caf69dd1 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc-u-boot.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright Altera Corporation (C) 2015 + * Copyright (c) 2018 Simon Goldschmidt + */ + +#include "socfpga-common-u-boot.dtsi" + +/{ + aliases { + udc0 = &usb1; + }; +}; + +&watchdog0 { + status = "disabled"; +}; + +&mmc { + bootph-all; +}; + +&uart0 { + clock-frequency = <100000000>; + bootph-all; +}; + +&uart1 { + clock-frequency = <100000000>; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&portc { + bank-name = "portc"; +}; diff --git a/arch/arm/dts/socfpga_cyclone5_ac550soc.dts b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts new file mode 100644 index 00000000000..cc841e85560 --- /dev/null +++ b/arch/arm/dts/socfpga_cyclone5_ac550soc.dts @@ -0,0 +1,118 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2025, Brian Sune + * + * based on socfpga_cyclone5_socdk.dts + */ + +#include "socfpga_cyclone5.dtsi" + +/ { + model = "CoreCourse AC550SoC,AC802-CVA6"; + compatible = "altr,socfpga-cyclone5", "altr,socfpga"; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gmac1; + udc0 = &usb1; + }; + + memory@0 { + name = "memory"; + device_type = "memory"; + reg = <0x0 0x40000000>; /* 1GB */ + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 6 1>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&porta 9 1>; + }; + }; + + buttons { + compatible = "gpio-keys"; + hps0 { + label = "HPS GPIO0"; + gpios = <&porta 0 0>; + }; + }; + + regulator_3_3v: 3-3-v-regulator { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&i2c0 { + status = "okay"; + clock-frequency = <100000>; +}; + +&i2c3 { + status = "okay"; + clock-frequency = <100000>; + + i2c-sda-falling-time-ns = <5000>; + i2c-scl-falling-time-ns = <5000>; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + rtc@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + #clock-cells = <0>; + }; +}; + +&gmac1 { + status = "okay"; + phy-mode = "rgmii"; + + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + txen-skew-ps = <0>; + txc-skew-ps = <1860>; + rxdv-skew-ps = <420>; + rxc-skew-ps = <1680>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&mmc0 { + vmmc-supply = <®ulator_3_3v>; + vqmmc-supply = <®ulator_3_3v>; + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1a0fcd64296..69af0b48348 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -243,6 +243,10 @@ config TARGET_SOCFPGA_CORECOURSE_AC501SOC bool "CoreCourse AC501SoC (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 +config TARGET_SOCFPGA_CORECOURSE_AC550SOC + bool "CoreCourse AC550SoC (Cyclone V)" + select TARGET_SOCFPGA_CYCLONE5 + endchoice config SYS_BOARD @@ -268,6 +272,7 @@ config SYS_BOARD default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_VENDOR default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK @@ -290,6 +295,7 @@ config SYS_VENDOR default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "corecourse" if TARGET_SOCFPGA_CORECOURSE_AC550SOC config SYS_SOC default "socfpga" @@ -317,5 +323,6 @@ config SYS_CONFIG_NAME default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA default "socfpga_ac501soc" if TARGET_SOCFPGA_CORECOURSE_AC501SOC + default "socfpga_ac550soc" if TARGET_SOCFPGA_CORECOURSE_AC550SOC endif diff --git a/board/corecourse/ac550soc/MAINTAINERS b/board/corecourse/ac550soc/MAINTAINERS new file mode 100644 index 00000000000..c46d8c70702 --- /dev/null +++ b/board/corecourse/ac550soc/MAINTAINERS @@ -0,0 +1,6 @@ +SOCFPGA BOARD +M: Brian Sune +S: Maintained +F: board/corecourse/ac550soc/ +F: include/configs/socfpga_ac550soc.h +F: configs/socfpga_ac550soc_defconfig diff --git a/board/corecourse/ac550soc/qts/iocsr_config.h b/board/corecourse/ac550soc/qts/iocsr_config.h new file mode 100644 index 00000000000..710ab602de6 --- /dev/null +++ b/board/corecourse/ac550soc/qts/iocsr_config.h @@ -0,0 +1,664 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA IOCSR configuration + */ + +#ifndef __SOCFPGA_IOCSR_CONFIG_H__ +#define __SOCFPGA_IOCSR_CONFIG_H__ + +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 + +const unsigned long iocsr_scan_chain0_table[] = { + 0x00000000, + 0x00000000, + 0x0FF00000, + 0xC0000000, + 0x0000003F, + 0x00008000, + 0x00060180, + 0x18060000, + 0x18000000, + 0x00018060, + 0x00000000, + 0x00004000, + 0x000300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00000018, + 0x00006018, + 0x00001000, +}; + +const unsigned long iocsr_scan_chain1_table[] = { + 0x00100000, + 0x300C0000, + 0x300000C0, + 0x000000C0, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x00000000, + 0x00000080, + 0x00020000, + 0x00004000, + 0x000300C0, + 0x10000000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x06018060, + 0x06018000, + 0x01FE0000, + 0xF8000000, + 0x00000007, + 0x00001000, + 0x0000C030, + 0x0300C000, + 0x03000000, + 0x0000300C, + 0x0000300C, + 0x00000800, + 0x00000000, + 0x00000000, + 0x01800000, + 0x00000006, + 0x00002000, + 0x00000400, + 0x00000000, + 0x00C03000, + 0x00000003, + 0x00000000, + 0x00000000, + 0x00000200, + 0x00601806, + 0x00000000, + 0x80600000, + 0x80000601, + 0x00000601, + 0x00000100, + 0x00300C03, + 0xC0300C00, + 0xC0300000, + 0xC0000300, + 0x000C0300, + 0x00000080, +}; + +const unsigned long iocsr_scan_chain2_table[] = { + 0x000C0300, + 0x300C0000, + 0x0FF00000, + 0x00000000, + 0x000300C0, + 0x00008000, + 0x00080000, + 0x20000000, + 0x18000000, + 0x00000060, + 0x00018060, + 0x00004000, + 0x200300C0, + 0x0C030000, + 0x0C000000, + 0x00000030, + 0x0000C030, + 0x00002000, + 0x00018060, + 0x06018000, + 0x06000000, + 0x00010018, + 0x00006018, + 0x00001000, + 0x0000C030, + 0x00000000, + 0x03000000, + 0x0000000C, + 0x00C0300C, + 0x00000800, +}; + +const unsigned long iocsr_scan_chain3_table[] = { + 0x0C820D80, + 0x082000FF, + 0x0A804001, + 0x07900000, + 0x08020000, + 0x00100000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000000, + 0x00000021, + 0x82000004, + 0x05400000, + 0x03C80000, + 0x04010000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0xE4400000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x00000001, + 0x40000002, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x49034051, + 0x12481A02, + 0x802080D0, + 0x34051406, + 0x01A02490, + 0x280D0000, + 0x30C0680A, + 0x02490340, + 0xD000001A, + 0x0680A280, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x0A800001, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x0A800000, + 0x07900000, + 0x08020000, + 0x00100000, + 0xC8800000, + 0x00003001, + 0x00C00722, + 0x00000FF0, + 0x72200000, + 0x80000C00, + 0x05400000, + 0x02480000, + 0x04000000, + 0x00080000, + 0x05400000, + 0x03C80000, + 0x05400000, + 0x03C80000, + 0x6A1C0000, + 0x00001800, + 0x00600391, + 0x800E4400, + 0x1A870001, + 0x40000600, + 0x02A00040, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x02A00000, + 0x01E40000, + 0x72200000, + 0x80000C00, + 0x003001C8, + 0xC0072200, + 0x1C880000, + 0x20000300, + 0x00040000, + 0x50670000, + 0x00000010, + 0x24590000, + 0x00001000, + 0xA0000034, + 0x0D000001, + 0x40680208, + 0x41034051, + 0x02081A00, + 0x80A280D0, + 0x34051406, + 0x01A00040, + 0x080D0002, + 0x51406802, + 0x02490340, + 0xD012481A, + 0x06802080, + 0x10040000, + 0x00200000, + 0x10040000, + 0x00200000, + 0x15000000, + 0x0F200000, + 0x15000000, + 0x0F200000, + 0x01FE0000, + 0x00000000, + 0x01800E44, + 0x00391000, + 0x007F8006, + 0x00000000, + 0x99300001, + 0x34343400, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x01000000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xBB2CA3D0, + 0xF711451E, + 0x035E9248, + 0x821A0000, + 0x0000D000, + 0x01040680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x00003FC2, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00015000, + 0x0000F200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00600391, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x14864000, + 0xD9647A05, + 0xDA28A3D0, + 0xF711451E, + 0x0340D348, + 0x821A0186, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035ED3, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x0002A000, + 0x0001E400, + 0x5506A000, + 0x00E1D448, + 0x00000000, + 0xC880090C, + 0x00003001, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA24, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00002000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F3690D, + 0x1A041414, + 0x00D00000, + 0x04864000, + 0x69A47A01, + 0xBB2CA3DF, + 0xF51E791E, + 0x0340D348, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xD069A47A, + 0x1EBB2CA3, + 0x48F71145, + 0x00035E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0xAA0D4000, + 0x01C3A800, + 0xAA0D4000, + 0x01C3A890, + 0xAA0D4000, + 0x01C3A800, + 0x00040100, + 0x00000800, + 0x00000000, + 0x00001208, + 0x00482000, + 0x00008000, + 0x00000000, + 0x00410482, + 0x0006A000, + 0x0001B400, + 0x00020000, + 0x00000400, + 0x00020080, + 0x00000400, + 0x5506A000, + 0x00E1D400, + 0x00000000, + 0x0000090C, + 0x00000010, + 0x90400000, + 0x00000000, + 0x2020C243, + 0x2A835000, + 0x0070EA00, + 0x2A835000, + 0x0070EA24, + 0x2A835000, + 0x0070EA00, + 0x00010040, + 0x00000200, + 0x00000000, + 0x00000482, + 0x00120800, + 0x00400000, + 0x80000000, + 0x00104120, + 0x00000200, + 0xAC0D5F80, + 0xFFFFFFFF, + 0x14F1690D, + 0x1A041414, + 0x00D00000, + 0x18864000, + 0x69A47A06, + 0xDA28A3DF, + 0xF51E791E, + 0x034E9248, + 0x821A0000, + 0x0000D000, + 0x00000680, + 0xDF69A47A, + 0x1EDA28A3, + 0x48F51E79, + 0x00034E92, + 0x00080200, + 0x00001000, + 0x00080200, + 0x00001000, + 0x000A8000, + 0x00075000, + 0x541A8000, + 0x03875001, + 0x10000000, + 0x00000000, + 0x0080C000, + 0x41000000, + 0x04000002, + 0x00820000, + 0x00489800, + 0x801A1A1A, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x80000004, + 0x00000200, + 0x00000004, + 0x00040000, + 0x10000000, + 0x00000000, + 0x00000040, + 0x00010000, + 0x40002000, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x40000002, + 0x00000100, + 0x00000002, + 0x00020000, + 0x08000000, + 0x00000000, + 0x00000020, + 0x00008000, + 0x20001000, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x20000001, + 0x00000080, + 0x00000001, + 0x00010000, + 0x04000000, + 0x00FF0000, + 0x00000000, + 0x00004000, + 0x00000800, + 0xC0000001, + 0x00041419, + 0x40000000, + 0x04000816, + 0x000D0000, + 0x00006800, + 0x00000340, + 0xD000001A, + 0x06800000, + 0x00340000, + 0x0001A000, + 0x00000D00, + 0x40000068, + 0x1A000003, + 0x00D00000, + 0x00068000, + 0x00003400, + 0x000001A0, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x00000008, + 0x00000401, + 0x80000008, + 0x0000007F, + 0x20000000, + 0x00000000, + 0xE0000080, + 0x0000001F, + 0x00004000, +}; + + + +#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pinmux_config.h b/board/corecourse/ac550soc/qts/pinmux_config.h new file mode 100644 index 00000000000..2e8df563141 --- /dev/null +++ b/board/corecourse/ac550soc/qts/pinmux_config.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA PinMux configuration + */ + +#ifndef __SOCFPGA_PINMUX_CONFIG_H__ +#define __SOCFPGA_PINMUX_CONFIG_H__ + +const u8 sys_mgr_init_table[] = { + 0, /* EMACIO0 */ + 2, /* EMACIO1 */ + 2, /* EMACIO2 */ + 2, /* EMACIO3 */ + 2, /* EMACIO4 */ + 2, /* EMACIO5 */ + 2, /* EMACIO6 */ + 2, /* EMACIO7 */ + 2, /* EMACIO8 */ + 0, /* EMACIO9 */ + 2, /* EMACIO10 */ + 2, /* EMACIO11 */ + 2, /* EMACIO12 */ + 2, /* EMACIO13 */ + 0, /* EMACIO14 */ + 0, /* EMACIO15 */ + 0, /* EMACIO16 */ + 0, /* EMACIO17 */ + 0, /* EMACIO18 */ + 0, /* EMACIO19 */ + 3, /* FLASHIO0 */ + 0, /* FLASHIO1 */ + 3, /* FLASHIO2 */ + 3, /* FLASHIO3 */ + 0, /* FLASHIO4 */ + 0, /* FLASHIO5 */ + 0, /* FLASHIO6 */ + 0, /* FLASHIO7 */ + 0, /* FLASHIO8 */ + 3, /* FLASHIO9 */ + 3, /* FLASHIO10 */ + 3, /* FLASHIO11 */ + 0, /* GENERALIO0 */ + 1, /* GENERALIO1 */ + 1, /* GENERALIO2 */ + 0, /* GENERALIO3 */ + 0, /* GENERALIO4 */ + 0, /* GENERALIO5 */ + 0, /* GENERALIO6 */ + 1, /* GENERALIO7 */ + 1, /* GENERALIO8 */ + 0, /* GENERALIO9 */ + 0, /* GENERALIO10 */ + 0, /* GENERALIO11 */ + 0, /* GENERALIO12 */ + 0, /* GENERALIO13 */ + 0, /* GENERALIO14 */ + 0, /* GENERALIO15 */ + 0, /* GENERALIO16 */ + 0, /* GENERALIO17 */ + 0, /* GENERALIO18 */ + 0, /* GENERALIO19 */ + 0, /* GENERALIO20 */ + 0, /* GENERALIO21 */ + 0, /* GENERALIO22 */ + 0, /* GENERALIO23 */ + 0, /* GENERALIO24 */ + 0, /* GENERALIO25 */ + 0, /* GENERALIO26 */ + 0, /* GENERALIO27 */ + 0, /* GENERALIO28 */ + 0, /* GENERALIO29 */ + 0, /* GENERALIO30 */ + 0, /* GENERALIO31 */ + 2, /* MIXED1IO0 */ + 2, /* MIXED1IO1 */ + 2, /* MIXED1IO2 */ + 2, /* MIXED1IO3 */ + 2, /* MIXED1IO4 */ + 2, /* MIXED1IO5 */ + 2, /* MIXED1IO6 */ + 2, /* MIXED1IO7 */ + 2, /* MIXED1IO8 */ + 2, /* MIXED1IO9 */ + 2, /* MIXED1IO10 */ + 2, /* MIXED1IO11 */ + 2, /* MIXED1IO12 */ + 2, /* MIXED1IO13 */ + 0, /* MIXED1IO14 */ + 3, /* MIXED1IO15 */ + 3, /* MIXED1IO16 */ + 3, /* MIXED1IO17 */ + 3, /* MIXED1IO18 */ + 3, /* MIXED1IO19 */ + 3, /* MIXED1IO20 */ + 0, /* MIXED1IO21 */ + 0, /* MIXED2IO0 */ + 0, /* MIXED2IO1 */ + 0, /* MIXED2IO2 */ + 0, /* MIXED2IO3 */ + 0, /* MIXED2IO4 */ + 0, /* MIXED2IO5 */ + 0, /* MIXED2IO6 */ + 0, /* MIXED2IO7 */ + 0, /* GPLINMUX48 */ + 0, /* GPLINMUX49 */ + 0, /* GPLINMUX50 */ + 0, /* GPLINMUX51 */ + 0, /* GPLINMUX52 */ + 0, /* GPLINMUX53 */ + 0, /* GPLINMUX54 */ + 0, /* GPLINMUX55 */ + 0, /* GPLINMUX56 */ + 0, /* GPLINMUX57 */ + 0, /* GPLINMUX58 */ + 0, /* GPLINMUX59 */ + 0, /* GPLINMUX60 */ + 0, /* GPLINMUX61 */ + 0, /* GPLINMUX62 */ + 0, /* GPLINMUX63 */ + 0, /* GPLINMUX64 */ + 0, /* GPLINMUX65 */ + 0, /* GPLINMUX66 */ + 0, /* GPLINMUX67 */ + 0, /* GPLINMUX68 */ + 0, /* GPLINMUX69 */ + 0, /* GPLINMUX70 */ + 1, /* GPLMUX0 */ + 1, /* GPLMUX1 */ + 1, /* GPLMUX2 */ + 1, /* GPLMUX3 */ + 1, /* GPLMUX4 */ + 1, /* GPLMUX5 */ + 1, /* GPLMUX6 */ + 1, /* GPLMUX7 */ + 1, /* GPLMUX8 */ + 1, /* GPLMUX9 */ + 1, /* GPLMUX10 */ + 1, /* GPLMUX11 */ + 1, /* GPLMUX12 */ + 1, /* GPLMUX13 */ + 1, /* GPLMUX14 */ + 1, /* GPLMUX15 */ + 1, /* GPLMUX16 */ + 1, /* GPLMUX17 */ + 1, /* GPLMUX18 */ + 1, /* GPLMUX19 */ + 1, /* GPLMUX20 */ + 1, /* GPLMUX21 */ + 1, /* GPLMUX22 */ + 1, /* GPLMUX23 */ + 1, /* GPLMUX24 */ + 1, /* GPLMUX25 */ + 1, /* GPLMUX26 */ + 1, /* GPLMUX27 */ + 1, /* GPLMUX28 */ + 1, /* GPLMUX29 */ + 1, /* GPLMUX30 */ + 1, /* GPLMUX31 */ + 1, /* GPLMUX32 */ + 1, /* GPLMUX33 */ + 1, /* GPLMUX34 */ + 1, /* GPLMUX35 */ + 1, /* GPLMUX36 */ + 1, /* GPLMUX37 */ + 1, /* GPLMUX38 */ + 1, /* GPLMUX39 */ + 1, /* GPLMUX40 */ + 1, /* GPLMUX41 */ + 1, /* GPLMUX42 */ + 1, /* GPLMUX43 */ + 1, /* GPLMUX44 */ + 1, /* GPLMUX45 */ + 1, /* GPLMUX46 */ + 1, /* GPLMUX47 */ + 1, /* GPLMUX48 */ + 1, /* GPLMUX49 */ + 1, /* GPLMUX50 */ + 1, /* GPLMUX51 */ + 1, /* GPLMUX52 */ + 1, /* GPLMUX53 */ + 1, /* GPLMUX54 */ + 1, /* GPLMUX55 */ + 1, /* GPLMUX56 */ + 1, /* GPLMUX57 */ + 1, /* GPLMUX58 */ + 1, /* GPLMUX59 */ + 1, /* GPLMUX60 */ + 1, /* GPLMUX61 */ + 1, /* GPLMUX62 */ + 1, /* GPLMUX63 */ + 1, /* GPLMUX64 */ + 1, /* GPLMUX65 */ + 1, /* GPLMUX66 */ + 1, /* GPLMUX67 */ + 1, /* GPLMUX68 */ + 1, /* GPLMUX69 */ + 1, /* GPLMUX70 */ + 0, /* NANDUSEFPGA */ + 0, /* UART0USEFPGA */ + 0, /* RGMII1USEFPGA */ + 0, /* SPIS0USEFPGA */ + 1, /* CAN0USEFPGA */ + 0, /* I2C0USEFPGA */ + 0, /* SDMMCUSEFPGA */ + 0, /* QSPIUSEFPGA */ + 0, /* SPIS1USEFPGA */ + 0, /* RGMII0USEFPGA */ + 1, /* UART1USEFPGA */ + 1, /* CAN1USEFPGA */ + 0, /* USB1USEFPGA */ + 1, /* I2C3USEFPGA */ + 1, /* I2C2USEFPGA */ + 0, /* I2C1USEFPGA */ + 0, /* SPIM1USEFPGA */ + 0, /* USB0USEFPGA */ + 0 /* SPIM0USEFPGA */ +}; +#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/pll_config.h b/board/corecourse/ac550soc/qts/pll_config.h new file mode 100644 index 00000000000..673b9de864f --- /dev/null +++ b/board/corecourse/ac550soc/qts/pll_config.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + */ +/* + * Altera SoCFPGA Clock and PLL configuration + */ + +#ifndef __SOCFPGA_PLL_CONFIG_H__ +#define __SOCFPGA_PLL_CONFIG_H__ + +#define CFG_HPS_DBCTRL_STAYOSC1 1 + +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 71 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 17 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 + +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 + +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 + +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1800000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 1066666667 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 360000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 + +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 + +#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/corecourse/ac550soc/qts/sdram_config.h b/board/corecourse/ac550soc/qts/sdram_config.h new file mode 100644 index 00000000000..eae9f57dd9c --- /dev/null +++ b/board/corecourse/ac550soc/qts/sdram_config.h @@ -0,0 +1,349 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2022 Intel Corporation + * + */ +/* + * Altera SoCFPGA SDRAM configuration + * + */ + +#ifndef __SOCFPGA_SDRAM_CONFIG_H__ +#define __SOCFPGA_SDRAM_CONFIG_H__ + +/* SDRAM configuration */ +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 187 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 27 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x3FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 + +/* Sequencer auto configuration */ +#define RW_MGR_ACTIVATE_0_AND_1 0x0D +#define RW_MGR_ACTIVATE_0_AND_1_WAIT1 0x0E +#define RW_MGR_ACTIVATE_0_AND_1_WAIT2 0x10 +#define RW_MGR_ACTIVATE_1 0x0F +#define RW_MGR_CLEAR_DQS_ENABLE 0x49 +#define RW_MGR_GUARANTEED_READ 0x4C +#define RW_MGR_GUARANTEED_READ_CONT 0x54 +#define RW_MGR_GUARANTEED_WRITE 0x18 +#define RW_MGR_GUARANTEED_WRITE_WAIT0 0x1B +#define RW_MGR_GUARANTEED_WRITE_WAIT1 0x1F +#define RW_MGR_GUARANTEED_WRITE_WAIT2 0x19 +#define RW_MGR_GUARANTEED_WRITE_WAIT3 0x1D +#define RW_MGR_IDLE 0x00 +#define RW_MGR_IDLE_LOOP1 0x7B +#define RW_MGR_IDLE_LOOP2 0x7A +#define RW_MGR_INIT_RESET_0_CKE_0 0x6F +#define RW_MGR_INIT_RESET_1_CKE_0 0x74 +#define RW_MGR_LFSR_WR_RD_BANK_0 0x22 +#define RW_MGR_LFSR_WR_RD_BANK_0_DATA 0x25 +#define RW_MGR_LFSR_WR_RD_BANK_0_DQS 0x24 +#define RW_MGR_LFSR_WR_RD_BANK_0_NOP 0x23 +#define RW_MGR_LFSR_WR_RD_BANK_0_WAIT 0x32 +#define RW_MGR_LFSR_WR_RD_BANK_0_WL_1 0x21 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0 0x36 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA 0x39 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS 0x38 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP 0x37 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT 0x46 +#define RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1 0x35 +#define RW_MGR_MRS0_DLL_RESET 0x02 +#define RW_MGR_MRS0_DLL_RESET_MIRR 0x08 +#define RW_MGR_MRS0_USER 0x07 +#define RW_MGR_MRS0_USER_MIRR 0x0C +#define RW_MGR_MRS1 0x03 +#define RW_MGR_MRS1_MIRR 0x09 +#define RW_MGR_MRS2 0x04 +#define RW_MGR_MRS2_MIRR 0x0A +#define RW_MGR_MRS3 0x05 +#define RW_MGR_MRS3_MIRR 0x0B +#define RW_MGR_PRECHARGE_ALL 0x12 +#define RW_MGR_READ_B2B 0x59 +#define RW_MGR_READ_B2B_WAIT1 0x61 +#define RW_MGR_READ_B2B_WAIT2 0x6B +#define RW_MGR_REFRESH_ALL 0x14 +#define RW_MGR_RETURN 0x01 +#define RW_MGR_SGLE_READ 0x7D +#define RW_MGR_ZQCL 0x06 + +/* Sequencer defines configuration */ +#define AFI_CLK_FREQ 534 +#define AFI_RATE_RATIO 1 +#define CALIB_LFIFO_OFFSET 8 +#define CALIB_VFIFO_OFFSET 6 +#define ENABLE_SUPER_QUICK_CALIBRATION 0 +#define IO_DELAY_PER_DCHAIN_TAP 25 +#define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 +#define IO_DELAY_PER_OPA_TAP 234 +#define IO_DLL_CHAIN_LENGTH 8 +#define IO_DQDQS_OUT_PHASE_MAX 0 +#define IO_DQS_EN_DELAY_MAX 15 +#define IO_DQS_EN_DELAY_OFFSET 16 +#define IO_DQS_EN_PHASE_MAX 7 +#define IO_DQS_IN_DELAY_MAX 31 +#define IO_DQS_IN_RESERVE 4 +#define IO_DQS_OUT_RESERVE 4 +#define IO_IO_IN_DELAY_MAX 31 +#define IO_IO_OUT1_DELAY_MAX 31 +#define IO_IO_OUT2_DELAY_MAX 0 +#define IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS 0 +#define MAX_LATENCY_COUNT_WIDTH 5 +#define READ_VALID_FIFO_SIZE 16 +#define REG_FILE_INIT_SEQ_SIGNATURE 0x555504b5 +#define RW_MGR_MEM_ADDRESS_MIRRORING 0 +#define RW_MGR_MEM_DATA_MASK_WIDTH 4 +#define RW_MGR_MEM_DATA_WIDTH 32 +#define RW_MGR_MEM_DQ_PER_READ_DQS 8 +#define RW_MGR_MEM_DQ_PER_WRITE_DQS 8 +#define RW_MGR_MEM_IF_READ_DQS_WIDTH 4 +#define RW_MGR_MEM_IF_WRITE_DQS_WIDTH 4 +#define RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM 1 +#define RW_MGR_MEM_NUMBER_OF_RANKS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS 1 +#define RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS 1 +#define RW_MGR_TRUE_MEM_DATA_MASK_WIDTH 4 +#define TINIT_CNTR0_VAL 132 +#define TINIT_CNTR1_VAL 32 +#define TINIT_CNTR2_VAL 32 +#define TRESET_CNTR0_VAL 132 +#define TRESET_CNTR1_VAL 99 +#define TRESET_CNTR2_VAL 10 + +/* Sequencer ac_rom_init configuration */ +const u32 ac_rom_init[] = { + 0x20700000, + 0x20780000, + 0x10080831, + 0x10080930, + 0x10090006, + 0x100a0208, + 0x100b0000, + 0x10380400, + 0x10080849, + 0x100808c8, + 0x100a0006, + 0x10090210, + 0x100b0000, + 0x30780000, + 0x38780000, + 0x30780000, + 0x10680000, + 0x106b0000, + 0x10280400, + 0x10480000, + 0x1c980000, + 0x1c9b0000, + 0x1c980008, + 0x1c9b0008, + 0x38f80000, + 0x3cf80000, + 0x38780000, + 0x18180000, + 0x18980000, + 0x13580000, + 0x135b0000, + 0x13580008, + 0x135b0008, + 0x33780000, + 0x10580008, + 0x10780000 +}; + +/* Sequencer inst_rom_init configuration */ +const u32 inst_rom_init[] = { + 0x80000, + 0x80680, + 0x8180, + 0x8200, + 0x8280, + 0x8300, + 0x8380, + 0x8100, + 0x8480, + 0x8500, + 0x8580, + 0x8600, + 0x8400, + 0x800, + 0x8680, + 0x880, + 0xa680, + 0x80680, + 0x900, + 0x80680, + 0x980, + 0xa680, + 0x8680, + 0x80680, + 0xb68, + 0xcce8, + 0xae8, + 0x8ce8, + 0xb88, + 0xec88, + 0xa08, + 0xac88, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0x20ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x60e80, + 0x61080, + 0x61080, + 0x61080, + 0xa680, + 0x8680, + 0x80680, + 0xce00, + 0xcd80, + 0xe700, + 0xc00, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0x30ce0, + 0xd00, + 0x680, + 0x680, + 0x680, + 0x680, + 0x70e80, + 0x71080, + 0x71080, + 0x71080, + 0xa680, + 0x8680, + 0x80680, + 0x1158, + 0x6d8, + 0x80680, + 0x1168, + 0x7e8, + 0x7e8, + 0x87e8, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x1168, + 0x7e8, + 0x7e8, + 0xa7e8, + 0x80680, + 0x40e88, + 0x41088, + 0x41088, + 0x41088, + 0x40f68, + 0x410e8, + 0x410e8, + 0x410e8, + 0xa680, + 0x40fe8, + 0x410e8, + 0x410e8, + 0x410e8, + 0x41008, + 0x41088, + 0x41088, + 0x41088, + 0x1100, + 0xc680, + 0x8680, + 0xe680, + 0x80680, + 0x0, + 0x8000, + 0xa000, + 0xc000, + 0x80000, + 0x80, + 0x8080, + 0xa080, + 0xc080, + 0x80080, + 0x9180, + 0x8680, + 0xa680, + 0x80680, + 0x40f08, + 0x80680 +}; + +#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */ diff --git a/configs/socfpga_ac550soc_defconfig b/configs/socfpga_ac550soc_defconfig new file mode 100644 index 00000000000..143f5d0a043 --- /dev/null +++ b/configs/socfpga_ac550soc_defconfig @@ -0,0 +1,85 @@ +CONFIG_ARM=y +CONFIG_SYS_L2_PL310=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x800000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x4400 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_ac550soc" +CONFIG_DM_RESET=y +CONFIG_SPL_STACK=0x0 +CONFIG_SPL_TEXT_BASE=0xFFFF0000 +CONFIG_TARGET_SOCFPGA_CORECOURSE_AC550SOC=y +CONFIG_SPL_FS_FAT=y +# CONFIG_SPL_SPI is not set +CONFIG_TIMESTAMP=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_BOOTCOMMAND="run fatscript;bridge enable; run distro_bootcmd" +CONFIG_DEFAULT_FDT_FILE="socfpga_cyclone5_ac550soc.dtb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CLOCKS=y +CONFIG_SPL_PAD_TO=0x10000 +CONFIG_SPL_NO_BSS_LIMIT=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +# CONFIG_SPL_SYS_MMCSD_RAW_MODE is not set +CONFIG_SYS_MAXARGS=32 +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ff705000.spi.0:1m(u-boot),256k(env1),256k(env2),14848k(boot),16m(rootfs),-@1536k(UBI)" +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="corecourse" +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +# CONFIG_SPL_WDT is not set +CONFIG_SYS_TIMER_COUNTS_DOWN=y +# CONFIG_TOOLS_MKEFICAPSULE is not set +CONFIG_CMD_C5_PL330_DMA=y +CONFIG_NET_RANDOM_ETHADDR=y diff --git a/include/configs/socfpga_ac550soc.h b/include/configs/socfpga_ac550soc.h new file mode 100644 index 00000000000..48e02d61dc5 --- /dev/null +++ b/include/configs/socfpga_ac550soc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2025 Brian Sune + */ +#ifndef __CONFIG_CORESOURCE_AC550SOC_H__ +#define __CONFIG_CORESOURCE_AC550SOC_H__ + +#include + +/* The rest of the configuration is shared */ +#include + +#endif /* __CONFIG_CORESOURCE_AC550SOC_H__ */ -- cgit v1.3.1 From 62f7a94602094617ac384839ed695c2906893a88 Mon Sep 17 00:00:00 2001 From: Tien Fong Chee Date: Fri, 13 Feb 2026 20:27:23 +0800 Subject: Replace TARGET namespace and cleanup properly TARGET namespace is for machines / boards / what-have-you that building U-Boot for. Simply replace from TARGET to ARCH make things more clear and proper for ALL SoCFPGA. Signed-off-by: Brian Sune Reviewed-by: Tien Fong Chee # Conflicts: # drivers/ddr/altera/Makefile --- Kconfig | 4 +- arch/arm/Kconfig | 30 +++--- arch/arm/dts/socfpga_agilex-u-boot.dtsi | 2 +- arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 4 +- arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 6 +- arch/arm/mach-socfpga/Kconfig | 102 ++++++++++----------- arch/arm/mach-socfpga/Makefile | 32 +++---- arch/arm/mach-socfpga/board.c | 6 +- arch/arm/mach-socfpga/clock_manager.c | 8 +- arch/arm/mach-socfpga/config.mk | 4 +- .../mach-socfpga/include/mach/base_addr_soc64.h | 10 +- arch/arm/mach-socfpga/include/mach/clock_manager.h | 14 +-- arch/arm/mach-socfpga/include/mach/firewall.h | 2 +- arch/arm/mach-socfpga/include/mach/fpga_manager.h | 4 +- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 24 ++--- arch/arm/mach-socfpga/include/mach/misc.h | 10 +- arch/arm/mach-socfpga/include/mach/reset_manager.h | 6 +- .../include/mach/reset_manager_soc64.h | 2 +- arch/arm/mach-socfpga/include/mach/sdram.h | 4 +- .../arm/mach-socfpga/include/mach/system_manager.h | 6 +- .../include/mach/system_manager_soc64.h | 8 +- arch/arm/mach-socfpga/misc.c | 18 ++-- arch/arm/mach-socfpga/misc_soc64.c | 2 +- arch/arm/mach-socfpga/mmu-arm64_s10.c | 2 +- arch/arm/mach-socfpga/reset_manager_s10.c | 2 +- arch/arm/mach-socfpga/system_manager_soc64.c | 4 +- arch/arm/mach-socfpga/wrap_handoff_soc64.c | 4 +- common/Kconfig | 2 +- common/spl/Kconfig | 4 +- drivers/clk/altera/Makefile | 12 +-- drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 14 +-- drivers/ddr/altera/sdram_soc64.c | 14 +-- drivers/ddr/altera/sdram_soc64.h | 4 +- drivers/fpga/Kconfig | 2 +- drivers/fpga/Makefile | 4 +- drivers/fpga/altera.c | 8 +- drivers/mmc/socfpga_dw_mmc.c | 8 +- drivers/mtd/nand/raw/Kconfig | 2 +- drivers/net/Kconfig | 2 +- drivers/power/domain/Kconfig | 2 +- drivers/reset/reset-socfpga.c | 2 +- drivers/sysreset/Kconfig | 4 +- env/Kconfig | 2 +- include/configs/socfpga_common.h | 4 +- include/configs/socfpga_soc64_common.h | 10 +- scripts/Makefile.xpl | 6 +- 47 files changed, 216 insertions(+), 216 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index ce25ea24a60..a50b4c8c68a 100644 --- a/Kconfig +++ b/Kconfig @@ -524,8 +524,8 @@ config BUILD_TARGET default "u-boot-with-spl.bin" if MPC85xx && !E500MC && !E5500 && !E6500 && SPL default "u-boot-with-spl.imx" if ARCH_MX6 && SPL default "u-boot-with-spl.kwb" if ARMADA_32BIT && SPL - default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_ARRIA10 - default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_ARRIA10 + default "u-boot-with-spl.sfp" if ARCH_SOCFPGA_GEN5 default "u-boot.itb" if !BINMAN && SPL_LOAD_FIT && (ARCH_ROCKCHIP || \ RISCV || ARCH_ZYNQMP) default "u-boot.kwb" if (ARCH_KIRKWOOD || ARMADA_32BIT) && !SPL diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index cd6a454fd60..5508fce796a 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -30,7 +30,7 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 100000000 if ARCH_ZYNQMP - default 200000000 if TARGET_SOCFPGA_AGILEX5 || TARGET_SOCFPGA_AGILEX7M + default 200000000 if ARCH_SOCFPGA_AGILEX5 || ARCH_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system @@ -1145,35 +1145,35 @@ config ARCH_SNAPDRAGON config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R - select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_SOC64 - select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select ARCH_MISC_INIT if !ARCH_SOCFPGA_ARRIA10 + select ARM64 if ARCH_SOCFPGA_SOC64 + select CPU_V7A if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select DM select DM_SERIAL select GPIO_EXTRA_HEADER - select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select LMB_ARCH_MEM_MAP if TARGET_SOCFPGA_SOC64 + select ENABLE_ARM_SOC_BOOT0_HOOK if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select LMB_ARCH_MEM_MAP if ARCH_SOCFPGA_SOC64 select OF_CONTROL select SPL_DM_RESET if DM_RESET select SPL_DM_SERIAL select SPL_LIBCOMMON_SUPPORT select SPL_LIBGENERIC_SUPPORT select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64 - select SPL_DRIVERS_MISC if TARGET_SOCFPGA_SOC64 - select SPL_SOCFPGA_DT_REG if TARGET_SOCFPGA_SOC64 + select SPL_SEPARATE_BSS if ARCH_SOCFPGA_SOC64 + select SPL_DRIVERS_MISC if ARCH_SOCFPGA_SOC64 + select SPL_SOCFPGA_DT_REG if ARCH_SOCFPGA_SOC64 select SPL_SERIAL select SPL_SYSRESET select SPL_WATCHDOG select SUPPORT_SPL select SYS_NS16550 - select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 + select SYS_THUMB_BUILD if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 select SYSRESET - select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 - select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \ - TARGET_SOCFPGA_SOC64 - select SYSRESET_PSCI if TARGET_SOCFPGA_AGILEX5 - select USE_BOOTFILE if SPL_ATF && TARGET_SOCFPGA_SOC64 + select SYSRESET_SOCFPGA if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 + select SYSRESET_SOCFPGA_SOC64 if !ARCH_SOCFPGA_AGILEX5 && \ + ARCH_SOCFPGA_SOC64 + select SYSRESET_PSCI if ARCH_SOCFPGA_AGILEX5 + select USE_BOOTFILE if SPL_ATF && ARCH_SOCFPGA_SOC64 imply CMD_DM imply CMD_MTDPARTS imply CRC32_VERIFY diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi b/arch/arm/dts/socfpga_agilex-u-boot.dtsi index 770f6cad292..c0f932d0e11 100644 --- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex-u-boot.dtsi @@ -264,7 +264,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M &sdr { compatible = "intel,sdr-ctl-agilex7m"; reg = <0xf8020000 0x100>; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi index 37a3b14ed33..f2150b7eb7b 100644 --- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -8,7 +8,7 @@ #include "socfpga_agilex-u-boot.dtsi" -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX /{ chosen { stdout-path = "serial0:115200n8"; @@ -27,7 +27,7 @@ }; #endif -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +#ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M /{ model = "SoCFPGA Agilex7-M SoCDK"; chosen { diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi index 93a8e0697d6..88f0154463d 100644 --- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi +++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi @@ -28,7 +28,7 @@ os = "U-Boot"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80200000>; #else load = <0x00200000>; @@ -47,7 +47,7 @@ os = "arm-trusted-firmware"; arch = "arm64"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x80000000>; entry = <0x80000000>; #else @@ -106,7 +106,7 @@ arch = "arm64"; os = "linux"; compression = "none"; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) + #if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) load = <0x86000000>; entry = <0x86000000>; #else diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 69af0b48348..3a9e018ce23 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -1,15 +1,15 @@ if ARCH_SOCFPGA config ERR_PTR_OFFSET - default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range + default 0xfffec000 if ARCH_SOCFPGA_GEN5 # Boot ROM range config NR_DRAM_BANKS default 1 config SOCFPGA_SECURE_VAB_AUTH bool "Enable boot image authentication with Secure Device Manager" - depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \ - TARGET_SOCFPGA_AGILEX5 + depends on ARCH_SOCFPGA_AGILEX || ARCH_SOCFPGA_N5X || \ + ARCH_SOCFPGA_AGILEX5 select FIT_IMAGE_POST_PROCESS select SHA384 select SHA512 @@ -23,32 +23,32 @@ config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE depends on SOCFPGA_SECURE_VAB_AUTH config SPL_SIZE_LIMIT - default 0x10000 if TARGET_SOCFPGA_GEN5 + default 0x10000 if ARCH_SOCFPGA_GEN5 config SPL_SIZE_LIMIT_PROVIDE_STACK - default 0x200 if TARGET_SOCFPGA_GEN5 + default 0x200 if ARCH_SOCFPGA_GEN5 config SPL_STACK_R_ADDR - default 0x00800000 if TARGET_SOCFPGA_GEN5 + default 0x00800000 if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F - default y if TARGET_SOCFPGA_GEN5 + default y if ARCH_SOCFPGA_GEN5 config SPL_SYS_MALLOC_F_LEN - default 0x800 if TARGET_SOCFPGA_GEN5 + default 0x800 if ARCH_SOCFPGA_GEN5 config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE default 0xa2 config SYS_MALLOC_F_LEN - default 0x2000 if TARGET_SOCFPGA_ARRIA10 - default 0x2000 if TARGET_SOCFPGA_GEN5 + default 0x2000 if ARCH_SOCFPGA_ARRIA10 + default 0x2000 if ARCH_SOCFPGA_GEN5 config TEXT_BASE - default 0x01000040 if TARGET_SOCFPGA_ARRIA10 - default 0x01000040 if TARGET_SOCFPGA_GEN5 + default 0x01000040 if ARCH_SOCFPGA_ARRIA10 + default 0x01000040 if ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_AGILEX +config ARCH_SOCFPGA_AGILEX bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -58,9 +58,9 @@ config TARGET_SOCFPGA_AGILEX select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX7M +config ARCH_SOCFPGA_AGILEX7M bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -70,21 +70,21 @@ config TARGET_SOCFPGA_AGILEX7M select GICV2 select NCORE_CACHE select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_AGILEX5 +config ARCH_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF select CLK select FPGA_INTEL_SDM_MAILBOX select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 -config TARGET_SOCFPGA_ARRIA5 +config ARCH_SOCFPGA_ARRIA5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_ARRIA10 +config ARCH_SOCFPGA_ARRIA10 bool select GICV2 select SPL_ALTERA_SDRAM @@ -105,17 +105,17 @@ config TARGET_SOCFPGA_ARRIA10 config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM bool "Always reprogram Arria 10 FPGA" - depends on TARGET_SOCFPGA_ARRIA10 + depends on ARCH_SOCFPGA_ARRIA10 help Arria 10 FPGA is only programmed during the cold boot. This option forces the FPGA to be reprogrammed every reboot, allowing to change the bitstream and apply it with warm reboot. -config TARGET_SOCFPGA_CYCLONE5 +config ARCH_SOCFPGA_CYCLONE5 bool - select TARGET_SOCFPGA_GEN5 + select ARCH_SOCFPGA_GEN5 -config TARGET_SOCFPGA_GEN5 +config ARCH_SOCFPGA_GEN5 bool select SPL_ALTERA_SDRAM imply FPGA_SOCFPGA @@ -125,7 +125,7 @@ config TARGET_SOCFPGA_GEN5 imply SPL_SYS_MALLOC_SIMPLE imply SPL_USE_TINY_PRINTF -config TARGET_SOCFPGA_N5X +config ARCH_SOCFPGA_N5X bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN @@ -135,23 +135,23 @@ config TARGET_SOCFPGA_N5X select NCORE_CACHE select SPL_ALTERA_SDRAM select SPL_CLK if SPL - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 config TARGET_SOCFPGA_N5X_SOCDK bool "Intel eASIC SoCDK (N5X)" - select TARGET_SOCFPGA_N5X + select ARCH_SOCFPGA_N5X -config TARGET_SOCFPGA_SOC64 +config ARCH_SOCFPGA_SOC64 bool -config TARGET_SOCFPGA_STRATIX10 +config ARCH_SOCFPGA_STRATIX10 bool select ARMV8_MULTIENTRY select ARMV8_SET_SMPEN select BINMAN if SPL_ATF select FPGA_INTEL_SDM_MAILBOX select GICV2 - select TARGET_SOCFPGA_SOC64 + select ARCH_SOCFPGA_SOC64 choice prompt "Altera SOCFPGA board select" @@ -159,85 +159,85 @@ choice config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" - select TARGET_SOCFPGA_AGILEX + select ARCH_SOCFPGA_AGILEX config TARGET_SOCFPGA_AGILEX7M_SOCDK bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" - select TARGET_SOCFPGA_AGILEX7M + select ARCH_SOCFPGA_AGILEX7M config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" - select TARGET_SOCFPGA_AGILEX5 + select ARCH_SOCFPGA_AGILEX5 config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_ARRIA10_SOCDK bool "Altera SOCFPGA SoCDK (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_ARRIA5_SECU1 bool "ABB SECU1 (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 select VENDOR_KM config TARGET_SOCFPGA_ARRIA5_SOCDK bool "Altera SOCFPGA SoCDK (Arria V)" - select TARGET_SOCFPGA_ARRIA5 + select ARCH_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_CHAMELEONV3 bool "Google Chameleon v3 (Arria 10)" - select TARGET_SOCFPGA_ARRIA10 + select ARCH_SOCFPGA_ARRIA10 config TARGET_SOCFPGA_CYCLONE5_SOCDK bool "Altera SOCFPGA SoCDK (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1 bool "Devboards DBM-SoC1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_EBV_SOCRATES bool "EBV SoCrates (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_IS1 bool "IS1 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SOFTING_VINING_FPGA bool "Softing VIN|ING FPGA (Cyclone V)" select BOARD_LATE_INIT - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_SR1500 bool "SR1500 (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_STRATIX10_SOCDK bool "Intel SOCFPGA SoCDK (Stratix 10)" - select TARGET_SOCFPGA_STRATIX10 + select ARCH_SOCFPGA_STRATIX10 config TARGET_SOCFPGA_TERASIC_DE0_NANO bool "Terasic DE0-Nano-Atlas (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_NANO bool "Terasic DE10-Nano (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE10_STANDARD bool "Terasic DE10-Standard (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_DE1_SOC bool "Terasic DE1-SoC (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_TERASIC_SOCKIT bool "Terasic SoCkit (Cyclone V)" - select TARGET_SOCFPGA_CYCLONE5 + select ARCH_SOCFPGA_CYCLONE5 config TARGET_SOCFPGA_CORECOURSE_AC501SOC bool "CoreCourse AC501SoC (Cyclone V)" diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 4e85bfb00d4..b6f35ddacc4 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -10,7 +10,7 @@ obj-y += board.o obj-y += clock_manager.o obj-y += misc.o -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += clock_manager_gen5.o obj-y += misc_gen5.o obj-y += reset_manager_gen5.o @@ -21,14 +21,14 @@ obj-y += wrap_pll_config.o obj-y += fpga_manager.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += clock_manager_arria10.o obj-y += misc_arria10.o obj-y += pinmux_arria10.o obj-y += reset_manager_arria10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += clock_manager_s10.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -41,7 +41,7 @@ obj-y += wrap_handoff_soc64.o obj-y += wrap_pll_config_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -57,7 +57,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += clock_manager_agilex5.o obj-y += mailbox_s10.o obj-y += misc_soc64.o @@ -73,7 +73,7 @@ obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += clock_manager_agilex.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -89,7 +89,7 @@ obj-y += wrap_pll_config_soc64.o obj-y += altera-sysmgr.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o obj-y += mailbox_s10.o @@ -105,34 +105,34 @@ obj-y += wrap_pll_config_soc64.o endif ifdef CONFIG_XPL_BUILD -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 obj-y += spl_gen5.o obj-y += freeze_controller.o obj-y += wrap_iocsr_config.o obj-y += wrap_pinmux_config.o obj-y += wrap_sdram_config.o endif -ifdef CONFIG_TARGET_SOCFPGA_SOC64 +ifdef CONFIG_ARCH_SOCFPGA_SOC64 obj-y += firewall.o obj-y += spl_soc64.o endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif -ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 obj-y += spl_s10.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX +ifdef CONFIG_ARCH_SOCFPGA_AGILEX obj-y += spl_agilex.o endif -ifdef CONFIG_TARGET_SOCFPGA_N5X +ifdef CONFIG_ARCH_SOCFPGA_N5X obj-y += spl_n5x.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 +ifdef CONFIG_ARCH_SOCFPGA_AGILEX5 obj-y += spl_soc64.o obj-y += spl_agilex5.o endif -ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +ifdef CONFIG_ARCH_SOCFPGA_AGILEX7M obj-y += spl_agilex7m.o endif else @@ -140,7 +140,7 @@ obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o endif -ifdef CONFIG_TARGET_SOCFPGA_GEN5 +ifdef CONFIG_ARCH_SOCFPGA_GEN5 # QTS-generated config file wrappers CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR) CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR) diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index 7f65aed4540..4d7f0b9a79c 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -61,7 +61,7 @@ int board_init(void) int dram_init_banksize(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #ifndef CONFIG_SPL_BUILD struct spl_handoff *ho; @@ -72,7 +72,7 @@ int dram_init_banksize(void) #endif #else fdtdec_setup_memory_banksize(); -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -145,7 +145,7 @@ u8 socfpga_get_board_id(void) return board_id; } -#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_XPL_BUILD) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int board_fit_config_name_match(const char *name) { char board_name[10]; diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 134eaf08e0a..da71f5759db 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -18,7 +18,7 @@ void cm_wait_for_lock(u32 mask) u32 inter_val; u32 retry = 0; do { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) inter_val = readl(socfpga_get_clkmgr_addr() + CLKMGR_INTER) & mask; #else @@ -45,7 +45,7 @@ int cm_wait_for_fsm(void) int set_cpu_clk_info(void) { -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) /* Calculate the clock frequencies required for drivers */ cm_get_l4_sp_clk_hz(); cm_get_mmc_controller_clk_hz(); @@ -54,7 +54,7 @@ int set_cpu_clk_info(void) gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; gd->bd->bi_dsp_freq = 0; -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000; #else gd->bd->bi_ddr_freq = 0; @@ -63,7 +63,7 @@ int set_cpu_clk_info(void) return 0; } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz) { u32 reg; diff --git a/arch/arm/mach-socfpga/config.mk b/arch/arm/mach-socfpga/config.mk index 3909d399895..1ca1d33cb16 100644 --- a/arch/arm/mach-socfpga/config.mk +++ b/arch/arm/mach-socfpga/config.mk @@ -2,9 +2,9 @@ # # Brian Sune -ifeq ($(CONFIG_TARGET_SOCFPGA_CYCLONE5),y) +ifeq ($(CONFIG_ARCH_SOCFPGA_CYCLONE5),y) archprepare: socfpga_g5_handoff_prepare -else ifeq ($(CONFIG_TARGET_SOCFPGA_ARRIA5),y) +else ifeq ($(CONFIG_ARCH_SOCFPGA_ARRIA5),y) archprepare: socfpga_g5_handoff_prepare endif diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 074b9691af8..61982c2d508 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -7,7 +7,7 @@ #ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_ #define _SOCFPGA_SOC64_BASE_HARDWARE_H_ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOCFPGA_CCU_ADDRESS 0x1c000000 #define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000 #define SOCFPGA_SMMU_ADDRESS 0x16000000 @@ -47,9 +47,9 @@ #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 #define SOCFPGA_FW_MPFE_SCR_ADDRESS 0xf8020000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 @@ -84,6 +84,6 @@ #define SOCFPGA_OCRAM_ADDRESS 0xffe00000 #define GICD_BASE 0xfffc1000 #define GICC_BASE 0xfffc2000 -#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */ +#endif /* IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) */ #endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index f0431c081d8..48001dbff21 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -17,22 +17,22 @@ void cm_print_clock_quick_summary(void); unsigned long cm_get_mpu_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) int cm_set_qspi_controller_clk_hz(u32 clk_hz); #endif #endif -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) +#elif defined(CONFIG_ARCH_SOCFPGA_STRATIX10) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #include -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h b/arch/arm/mach-socfpga/include/mach/firewall.h index 2b436b64816..b47b577ae75 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -138,7 +138,7 @@ struct socfpga_firwall_l4_sys { #define MPUREGION0_ENABLE BIT(0) #define NONMPUREGION0_ENABLE BIT(8) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS + (reg)); \ writel(data, SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager.h b/arch/arm/mach-socfpga/include/mach/fpga_manager.h index 481b66bbd86..fc084823b51 100644 --- a/arch/arm/mach-socfpga/include/mach/fpga_manager.h +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager.h @@ -9,9 +9,9 @@ #include -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index b8f2f73e283..ae5af1f0100 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -19,7 +19,7 @@ #define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159 #define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53 #define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524D -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_MAGIC_PERI 0x50455249 #else #define SOC64_HANDOFF_MAGIC_MISC 0x4D495343 @@ -29,11 +29,11 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x634) /* DDR handoff */ #define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) @@ -43,9 +43,9 @@ #else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) #endif -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SOC64_HANDOFF_BASE 0xFFE5F000 #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630) @@ -76,17 +76,17 @@ #define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330) #define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0) #define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580) -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620) #define SOC64_HANDOFF_PERI_LEN 1 #define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634) #define SOC64_HANDOFF_SDRAM_LEN 5 #endif -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C) -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c) #define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610) #else @@ -96,9 +96,9 @@ #define SOC64_HANDOFF_MUX_LEN 96 #define SOC64_HANDOFF_IOCTL_LEN 96 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #define SOC64_HANDOFF_FPGA_LEN 42 -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_FPGA_LEN 44 #else #define SOC64_HANDOFF_FPGA_LEN 40 diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 0b80e952131..5a6a76b5ace 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -24,7 +24,7 @@ void socfpga_fpga_add(void *fpga_desc); static inline void socfpga_fpga_add(void *fpga_desc) {} #endif -#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +#ifdef CONFIG_ARCH_SOCFPGA_GEN5 void socfpga_sdram_remap_zero(void); static inline bool socfpga_is_booting_from_fpga(void) { @@ -35,14 +35,14 @@ static inline bool socfpga_is_booting_from_fpga(void) } #endif -#ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +#ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 void socfpga_init_security_policies(void); void socfpga_sdram_remap_zero(void); #endif -#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - defined(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if defined(CONFIG_ARCH_SOCFPGA_STRATIX10) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + defined(CONFIG_ARCH_SOCFPGA_AGILEX7M) int is_fpga_config_ready(void); #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index 1d68034cb55..97bb48474f3 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -39,11 +39,11 @@ void socfpga_per_reset_all(void); /* Create a human-readable reference to SoCFPGA reset. */ #define SOCFPGA_RESET(_name) RSTMGR_##_name -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include -#elif defined(CONFIG_TARGET_SOCFPGA_SOC64) +#elif defined(CONFIG_ARCH_SOCFPGA_SOC64) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h index 4b010be9ee8..5d72480dc13 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -39,7 +39,7 @@ void socfpga_bridges_reset(int enable, unsigned int mask); #define RSTMGR_STAT_SDMWARMRST 0x2 #define RSTMGR_STAT_MPU0RST_BITPOS 8 #define RSTMGR_STAT_L4WD0RST_BITPOS 16 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define RSTMGR_STAT_L4WD0RST_BIT 0x1F0000 #define RSTMGR_L4WD_MPU_WARMRESET_MASK (RSTMGR_STAT_SDMWARMRST | \ RSTMGR_STAT_L4WD0RST_BIT) diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h b/arch/arm/mach-socfpga/include/mach/sdram.h index 79cb9e6064a..9a261eb9383 100644 --- a/arch/arm/mach-socfpga/include/mach/sdram.h +++ b/arch/arm/mach-socfpga/include/mach/sdram.h @@ -7,9 +7,9 @@ #ifndef __ASSEMBLY__ -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 5603eaa3d02..3d5bd81e1b5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -8,7 +8,7 @@ phys_addr_t socfpga_get_sysmgr_addr(void); -#if defined(CONFIG_TARGET_SOCFPGA_SOC64) +#if defined(CONFIG_ARCH_SOCFPGA_SOC64) #include #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) @@ -85,9 +85,9 @@ phys_addr_t socfpga_get_sysmgr_addr(void); #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK BIT(1) #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK BIT(1) -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #include -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #include #endif diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index f768a3a55cb..8be98d0ee46 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -12,7 +12,7 @@ void sysmgr_pinmux_init(void); void populate_sysmgr_fpgaintf_module(void); void populate_sysmgr_pinmux(void); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define SYSMGR_SOC64_SILICONID_1 0x00 #define SYSMGR_SOC64_SILICONID_2 0x04 #define SYSMGR_SOC64_MPU_STATUS 0x10 @@ -62,7 +62,7 @@ void populate_sysmgr_pinmux(void); #else #define SYSMGR_SOC64_NAND_AXUSER 0x5c #define SYSMGR_SOC64_DMA_L3MASTER 0x74 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE 0xb8 #else #define SYSMGR_SOC64_HMC_CLK 0xb4 @@ -73,7 +73,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_SOC64_GPI 0xe8 #define SYSMGR_SOC64_MPU 0xf0 #define SYSMGR_SCRATCH_REG_0_QSPI_REFCLK_MASK GENMASK(27, 0) -#endif /*CONFIG_TARGET_SOCFPGA_AGILEX5*/ +#endif /*CONFIG_ARCH_SOCFPGA_AGILEX5*/ #define SYSMGR_SOC64_DMA 0x20 #define SYSMGR_SOC64_DMA_PERIPH 0x24 @@ -218,7 +218,7 @@ void populate_sysmgr_pinmux(void); #define SYSMGR_WDDBG_PAUSE_ALL_CPU 0xFF0F0F0F -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) #define SYSMGR_SOC64_DDR_MODE_MSK BIT(0) #endif diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 07694107c8a..1eef7893e54 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -54,7 +54,7 @@ struct bsel bsel_str[] = { int dram_init(void) { -#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct spl_handoff *ho; ho = bloblist_find(BLOBLISTT_U_BOOT_SPL_HANDOFF, sizeof(*ho)); @@ -65,7 +65,7 @@ int dram_init(void) #else if (fdtdec_setup_mem_size_base() != 0) return -EINVAL; -#endif /* HANDOFF && CONFIG_TARGET_SOCFPGA_AGILEX5 */ +#endif /* HANDOFF && CONFIG_ARCH_SOCFPGA_AGILEX5 */ return 0; } @@ -261,21 +261,21 @@ void socfpga_get_managers_addr(void) if (ret) hang(); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) { ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base); if (ret) hang(); } - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X)) ret = socfpga_get_base_addr("intel,n5x-clkmgr", &socfpga_clkmgr_base); - else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) + else if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base); diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 5222b384434..b74685df168 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -94,7 +94,7 @@ void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, int print_cpuinfo(void) { printf("CPU: Altera FPGA SoCFPGA Platform (ARMv8 64bit Cortex-%s)\n", - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); + IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) ? "A55/A76" : "A53"); return 0; } diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 1dc44ab4797..33520aae6cd 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -9,7 +9,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static struct mm_region socfpga_agilex5_mem_map[] = { { /* OCRAM 512KB */ diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index abb62a9b49f..67b16180ae7 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -79,7 +79,7 @@ static void socfpga_f2s_bridges_reset(int enable, unsigned int mask) u32 flaginstatus_idleack = 0; u32 flaginstatus_respempty = 0; - if (CONFIG_IS_ENABLED(TARGET_SOCFPGA_STRATIX10)) { + if (CONFIG_IS_ENABLED(ARCH_SOCFPGA_STRATIX10)) { /* Support fpga2soc and f2sdram */ brg_mask = mask & (RSTMGR_BRGMODRST_FPGA2SOC_MASK | RSTMGR_BRGMODRST_F2SDRAM0_MASK | diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 913f93c8f94..94624deef10 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -12,7 +12,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) /* * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse * generation and setting PORT_OVERCURRENT bit so that until we turn on the @@ -39,7 +39,7 @@ void sysmgr_pinmux_init(void) populate_sysmgr_pinmux(); populate_sysmgr_fpgaintf_module(); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sysmgr_config_usb3(); #endif } diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c index 7105cdc4905..ecde90f76f4 100644 --- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c +++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c @@ -29,13 +29,13 @@ static enum endianness check_endianness(u32 handoff) case SOC64_HANDOFF_MAGIC_DELAY: case SOC64_HANDOFF_MAGIC_CLOCK: case SOC64_HANDOFF_MAGIC_SDRAM: -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) case SOC64_HANDOFF_MAGIC_PERI: #else case SOC64_HANDOFF_MAGIC_MISC: #endif return BIG_ENDIAN; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) case SOC64_HANDOFF_DDR_UMCTL2_MAGIC: debug("%s: umctl2 handoff data\n", __func__); return LITTLE_ENDIAN; diff --git a/common/Kconfig b/common/Kconfig index 47d17f4e7c6..ee26bf8c96b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -55,7 +55,7 @@ config CONSOLE_RECORD_IN_SIZE config SYS_CBSIZE int "Console input buffer size" default 2048 if ARCH_TEGRA || ARCH_VERSAL || ARCH_ZYNQ || ARCH_ZYNQMP || \ - RCAR_GEN3 || TARGET_SOCFPGA_SOC64 + RCAR_GEN3 || ARCH_SOCFPGA_SOC64 default 512 if ARCH_MX5 || ARCH_MX6 || ARCH_MX7 || FSL_LSCH2 || \ FSL_LSCH3 || X86 default 256 if M68K || PPC diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2998b7acb75..996c9b8db4f 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -548,7 +548,7 @@ config SPL_SYS_MMCSD_RAW_MODE depends on SPL_DM_MMC || SPL_MMC default y if ARCH_SUNXI || ARCH_DAVINCI || ARCH_UNIPHIER || \ ARCH_MX6 || ARCH_MX7 || \ - ARCH_ROCKCHIP || ARCH_MVEBU || TARGET_SOCFPGA_GEN5 || \ + ARCH_ROCKCHIP || ARCH_MVEBU || ARCH_SOCFPGA_GEN5 || \ ARCH_AT91 || ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP54XX || AM33XX || AM43XX || \ TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED @@ -593,7 +593,7 @@ config SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR default 0x8a if ARCH_MX6 || ARCH_MX7 default 0x100 if ARCH_UNIPHIER default 0x0 if ARCH_MVEBU - default 0x200 if TARGET_SOCFPGA_GEN5 || ARCH_AT91 + default 0x200 if ARCH_SOCFPGA_GEN5 || ARCH_AT91 default 0x300 if ARCH_ZYNQ || ARCH_KEYSTONE || OMAP34XX || \ OMAP54XX || AM33XX || AM43XX || ARCH_K3 default 0x4000 if ARCH_ROCKCHIP diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index 858f828e537..693446b3d89 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,9 +3,9 @@ # Copyright (C) 2018-2021 Marek Vasut # -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += clk-agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += clk-mem-n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += clk-agilex5.o diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 4660d20deff..615e0421abf 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_SOC64 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10 || ARCH_SOCFPGA_SOC64 + select RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 + select SPL_RAM if ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_SOC64 help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 7ed43965be5..8259ab04a7e 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -7,11 +7,11 @@ # Copyright (C) 2014-2025 Altera Corporation ifdef CONFIG_$(PHASE_)ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o -obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o -obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += sdram_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o +obj-$(CONFIG_ARCH_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX5) += sdram_soc64.o sdram_agilex5.o iossm_mailbox.o +obj-$(CONFIG_ARCH_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c index 2d0093c591c..8ee7049b164 100644 --- a/drivers/ddr/altera/sdram_soc64.c +++ b/drivers/ddr/altera/sdram_soc64.c @@ -32,7 +32,7 @@ #define SINGLE_RANK_CLAMSHELL 0xc3c3 #define DUAL_RANK_CLAMSHELL 0xa5a5 -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) && !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg) { return readl(plat->iomhc + reg); @@ -106,7 +106,7 @@ int emif_reset(struct altera_sdram_plat *plat) } #endif -#if !(IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)) +#if !(IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)) int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() + @@ -347,7 +347,7 @@ static void sdram_set_firewall_non_f2sdram(struct bd_info *bd) } } -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) static void sdram_set_firewall_f2sdram(struct bd_info *bd) { u32 i, lower, upper; @@ -397,22 +397,22 @@ void sdram_set_firewall(struct bd_info *bd) { sdram_set_firewall_non_f2sdram(bd); -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) sdram_set_firewall_f2sdram(bd); #endif } static int altera_sdram_of_to_plat(struct udevice *dev) { -#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if !IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) struct altera_sdram_plat *plat = dev_get_plat(dev); fdt_addr_t addr; #endif /* These regs info are part of DDR handoff in bitstream */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_N5X) return 0; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) || IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 6fe0653922c..e8090f91002 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -15,13 +15,13 @@ struct altera_sdram_priv { struct reset_ctl_bulk resets; }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) struct altera_sdram_plat { fdt_addr_t mpfe_base_addr; bool dualport; bool dualemif; }; -#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#elif IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M) enum memory_type { DDR_MEMORY = 0, HBM_MEMORY diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index e2593057fac..1658c73bca4 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -46,7 +46,7 @@ config FPGA_CYCLON2 config FPGA_INTEL_SDM_MAILBOX bool "Enable Intel FPGA Full Reconfiguration SDM Mailbox driver" - depends on TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA_SOC64 select FPGA_ALTERA help Say Y here to enable the Intel FPGA Full Reconfig SDM Mailbox driver diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index f22d3b3d86e..ccfed94717e 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -21,6 +21,6 @@ obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o +obj-$(CONFIG_ARCH_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += socfpga_arria10.o endif diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 4a9aa74357e..822183c5785 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,8 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) #include #endif #include @@ -48,8 +48,8 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) int fpga_is_partial_data(int devnum, size_t img_len) { /* diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 6219284df3e..c8da6ead0ea 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -58,8 +58,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) u32 sdmmc_mask = ((priv->smplsel & 0x7) << SYSMGR_SDMMC_SMPLSEL_SHIFT) | ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Disable SDMMC clock. */ clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); @@ -95,8 +95,8 @@ static int socfpga_dwmci_clksel(struct dwmci_host *host) readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); #endif - if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) && - !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)) { + if (!IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) && + !IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX7M)) { /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 306175873fa..2999e6b1710 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -217,7 +217,7 @@ config NAND_DENALI bool select DEVRES select SYS_NAND_SELF_INIT - select SYS_NAND_ONFI_DETECTION if TARGET_SOCFPGA_SOC64 + select SYS_NAND_ONFI_DETECTION if ARCH_SOCFPGA_SOC64 imply CMD_NAND config NAND_DENALI_DT diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index fce8004e134..d3ef050d1a1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -194,7 +194,7 @@ config DWC_ETH_XGMAC_SOCFPGA select SYSCON select DWC_ETH_XGMAC depends on ARCH_SOCFPGA - default y if TARGET_SOCFPGA_AGILEX5 + default y if ARCH_SOCFPGA_AGILEX5 help The Synopsys Designware Ethernet XGMAC IP block with specific configuration used in Intel SoC FPGA chip. diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 935f282d6c5..2f63a8e54e5 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -20,7 +20,7 @@ config APPLE_PMGR_POWER_DOMAIN config AGILEX5_PMGR_POWER_DOMAIN bool "Enable the Agilex5 PMGR power domain driver" - depends on SPL_POWER_DOMAIN && TARGET_SOCFPGA_SOC64 + depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64 help Enable support for power gating peripherals' SRAM specified in the handoff data values obtained from the bitstream to reduce diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c index e57729f0ef9..36a205f9fca 100644 --- a/drivers/reset/reset-socfpga.c +++ b/drivers/reset/reset-socfpga.c @@ -115,7 +115,7 @@ static int socfpga_reset_remove(struct udevice *dev) if (socfpga_reset_keep_enabled()) { puts("Deasserting all peripheral resets\n"); writel(0, data->modrst_base + 4); - if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_ARRIA10)) + if (IS_ENABLED(CONFIG_ARCH_SOCFPGA_ARRIA10)) writel(0, data->modrst_base + 8); } diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 120e7510f15..16ef434a8d9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -196,14 +196,14 @@ config SYSRESET_SBI config SYSRESET_SOCFPGA bool "Enable support for Intel SOCFPGA family" - depends on ARCH_SOCFPGA && (TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10) + depends on ARCH_SOCFPGA && (ARCH_SOCFPGA_GEN5 || ARCH_SOCFPGA_ARRIA10) help This enables the system reset driver support for Intel SOCFPGA SoCs (Cyclone 5, Arria 5 and Arria 10). config SYSRESET_SOCFPGA_SOC64 bool "Enable support for Intel SOCFPGA SoC64 family (Stratix10/Agilex)" - depends on ARCH_SOCFPGA && TARGET_SOCFPGA_SOC64 + depends on ARCH_SOCFPGA && ARCH_SOCFPGA_SOC64 help This enables the system reset driver support for Intel SOCFPGA SoC64 SoCs. diff --git a/env/Kconfig b/env/Kconfig index b312f9b5324..2feff0b382e 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -975,7 +975,7 @@ config USE_BOOTFILE config BOOTFILE string "'bootfile' environment variable value" - default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 + default kernel.itb if SPL_ATF && ARCH_SOCFPGA_SOC64 depends on USE_BOOTFILE help The value to set the "bootfile" variable to. diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 2acfdc7df4a..36d6bfb3d03 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -11,10 +11,10 @@ * Memory configurations */ #define PHYS_SDRAM_1 0x0 -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) +#if defined(CONFIG_ARCH_SOCFPGA_GEN5) #define CFG_SYS_INIT_RAM_ADDR 0xFFFF0000 #define CFG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) +#elif defined(CONFIG_ARCH_SOCFPGA_ARRIA10) #define CFG_SYS_INIT_RAM_ADDR 0xFFE00000 /* SPL memory allocation configuration, this is for FAT implementation */ #define CFG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 3d09a06f63e..4d333c63ad9 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -41,7 +41,7 @@ /* * U-Boot run time memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_SYS_INIT_RAM_ADDR 0x0 #define CFG_SYS_INIT_RAM_SIZE 0x80000 #else @@ -118,7 +118,7 @@ #include -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define CFG_EXTRA_ENV_SETTINGS \ "kernel_addr_r=0x82000000\0" \ @@ -182,7 +182,7 @@ "smc_fid_wr=0xC2000008\0" \ "smc_fid_upd=0xC2000009\0 " \ BOOTENV -#endif /*#IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)*/ +#endif /*#IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5)*/ #else @@ -245,7 +245,7 @@ /* * External memory configurations */ -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX5) #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) #define CFG_SYS_SDRAM_BASE 0x80000000 @@ -270,7 +270,7 @@ /* * L4 Watchdog */ -#ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +#ifdef CONFIG_ARCH_SOCFPGA_STRATIX10 #ifndef __ASSEMBLY__ unsigned int cm_get_l4_sys_free_clk_hz(void); #define CFG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) diff --git a/scripts/Makefile.xpl b/scripts/Makefile.xpl index 55aeac1038e..c5ddf64c73f 100644 --- a/scripts/Makefile.xpl +++ b/scripts/Makefile.xpl @@ -268,11 +268,11 @@ ifneq ($(CONFIG_ARCH_EXYNOS)$(CONFIG_ARCH_S5PC1XX),) INPUTS-y += $(obj)/$(BOARD)-spl.bin endif -ifneq ($(CONFIG_TARGET_SOCFPGA_GEN5)$(CONFIG_TARGET_SOCFPGA_ARRIA10),) +ifneq ($(CONFIG_ARCH_SOCFPGA_GEN5)$(CONFIG_ARCH_SOCFPGA_ARRIA10),) INPUTS-y += $(obj)/$(SPL_BIN).sfp endif -INPUTS-$(CONFIG_TARGET_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex +INPUTS-$(CONFIG_ARCH_SOCFPGA_SOC64) += $(obj)/u-boot-spl-dtb.hex ifdef CONFIG_ARCH_SUNXI INPUTS-y += $(obj)/sunxi-spl.bin @@ -432,7 +432,7 @@ ifneq ($(CONFIG_$(PHASE_)TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_$(PHASE_)TEXT_BASE) endif -ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 +ifdef CONFIG_ARCH_SOCFPGA_ARRIA10 MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage_v1 else MKIMAGEFLAGS_$(SPL_BIN).sfp = -T socfpgaimage -- cgit v1.3.1 From 63d52576e7b7fc39a1e5685065384a4653e4a9ef Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 12 Feb 2026 21:44:55 +0100 Subject: disk: part_dos: Move header to the main include directory There are two different struct definitions for MBR partition table entries: one in part_dos.h and a nearly identical one in part_efi.h. To enable future consolidation of these two structures, move part_dos.h to the main include directory. This makes it accessible from other parts of the codebase, such as part_efi.h, and is the first step toward removing the redundant definition. Signed-off-by: Javier Martinez Canillas Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- disk/part_dos.c | 2 +- disk/part_dos.h | 37 ------------------------------------- include/part_dos.h | 37 +++++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 38 deletions(-) delete mode 100644 disk/part_dos.h create mode 100644 include/part_dos.h (limited to 'include') diff --git a/disk/part_dos.c b/disk/part_dos.c index 18dd35c9b98..2545cc6bf5d 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -19,7 +19,7 @@ #include #include #include -#include "part_dos.h" +#include #include #define DOS_PART_DEFAULT_SECTOR 512 diff --git a/disk/part_dos.h b/disk/part_dos.h deleted file mode 100644 index 50558224228..00000000000 --- a/disk/part_dos.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _DISK_PART_DOS_H -#define _DISK_PART_DOS_H - -#define DOS_PART_DISKSIG_OFFSET 0x1b8 -#define DOS_PART_TBL_OFFSET 0x1be -#define DOS_PART_MAGIC_OFFSET 0x1fe -#define DOS_PBR_FSTYPE_OFFSET 0x36 -#define DOS_PBR32_FSTYPE_OFFSET 0x52 -#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 -#define DOS_MBR 0 -#define DOS_PBR 1 -#define DOS_PART_TYPE_EXTENDED 0x05 -#define DOS_PART_TYPE_EXTENDED_LBA 0x0F -#define DOS_PART_TYPE_EXTENDED_LINUX 0x85 - -#define DOS_PART_DEFAULT_GAP 2048 - -typedef struct dos_partition { - unsigned char boot_ind; /* 0x80 - active */ - unsigned char head; /* starting head */ - unsigned char sector; /* starting sector */ - unsigned char cyl; /* starting cylinder */ - unsigned char sys_ind; /* What partition type */ - unsigned char end_head; /* end head */ - unsigned char end_sector; /* end sector */ - unsigned char end_cyl; /* end cylinder */ - unsigned char start4[4]; /* starting sector counting from 0 */ - unsigned char size4[4]; /* nr of sectors in partition */ -} dos_partition_t; - -#endif /* _DISK_PART_DOS_H */ diff --git a/include/part_dos.h b/include/part_dos.h new file mode 100644 index 00000000000..50558224228 --- /dev/null +++ b/include/part_dos.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + */ + +#ifndef _DISK_PART_DOS_H +#define _DISK_PART_DOS_H + +#define DOS_PART_DISKSIG_OFFSET 0x1b8 +#define DOS_PART_TBL_OFFSET 0x1be +#define DOS_PART_MAGIC_OFFSET 0x1fe +#define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR32_FSTYPE_OFFSET 0x52 +#define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 +#define DOS_MBR 0 +#define DOS_PBR 1 +#define DOS_PART_TYPE_EXTENDED 0x05 +#define DOS_PART_TYPE_EXTENDED_LBA 0x0F +#define DOS_PART_TYPE_EXTENDED_LINUX 0x85 + +#define DOS_PART_DEFAULT_GAP 2048 + +typedef struct dos_partition { + unsigned char boot_ind; /* 0x80 - active */ + unsigned char head; /* starting head */ + unsigned char sector; /* starting sector */ + unsigned char cyl; /* starting cylinder */ + unsigned char sys_ind; /* What partition type */ + unsigned char end_head; /* end head */ + unsigned char end_sector; /* end sector */ + unsigned char end_cyl; /* end cylinder */ + unsigned char start4[4]; /* starting sector counting from 0 */ + unsigned char size4[4]; /* nr of sectors in partition */ +} dos_partition_t; + +#endif /* _DISK_PART_DOS_H */ -- cgit v1.3.1 From 1450a4555d0533a0ca16df5bc6aa16f8162f91e1 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 12 Feb 2026 21:44:56 +0100 Subject: disk: part_dos: Align dos_partition_t with struct partition The dos_partition_t struct defined in part_dos.h is nearly identical to the struct partition defined in part_efi.h. They differ primarily in how define their starting sector and number of sectors fields. The former uses unsigned char arrays while the latter uses __le32 types. Using __le32 is preferable, as it removes the ambiguity and potential misuse of a raw byte array. This also aligns the structure with how the Linux kernel defines it nowadays, which is the original source of it. To prepare for future consolidation where one of the data structures can be removed, this change aligns both definitions and updates all accessors for dos_partition_t. Signed-off-by: Javier Martinez Canillas Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- disk/part_dos.c | 16 ++++++++-------- include/part_dos.h | 6 +++--- 2 files changed, 11 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/disk/part_dos.c b/disk/part_dos.c index 2545cc6bf5d..60c3d677369 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -49,8 +49,8 @@ static int get_bootable(dos_partition_t *p) static void print_one_part(dos_partition_t *p, lbaint_t ext_part_sector, int part_num, unsigned int disksig) { - lbaint_t lba_start = ext_part_sector + get_unaligned_le32(p->start4); - lbaint_t lba_size = get_unaligned_le32(p->size4); + lbaint_t lba_start = ext_part_sector + get_unaligned_le32(&p->start_sect); + lbaint_t lba_size = get_unaligned_le32(&p->nr_sects); printf("%3d\t%-10" LBAFlength "u\t%-10" LBAFlength "u\t%08x-%02x\t%02x%s%s\n", @@ -185,7 +185,7 @@ static void print_partition_extended(struct blk_desc *desc, for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { lbaint_t lba_start - = get_unaligned_le32 (pt->start4) + relative; + = get_unaligned_le32 (&pt->start_sect) + relative; print_partition_extended(desc, lba_start, !ext_part_sector ? lba_start : @@ -252,8 +252,8 @@ static int part_get_info_extended(struct blk_desc *desc, else info->blksz = DOS_PART_DEFAULT_SECTOR; info->start = (lbaint_t)(ext_part_sector + - get_unaligned_le32(pt->start4)); - info->size = (lbaint_t)get_unaligned_le32(pt->size4); + get_unaligned_le32(&pt->start_sect)); + info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); part_set_generic_name(desc, part_num, (char *)info->name); /* sprintf(info->type, "%d, pt->sys_ind); */ @@ -281,7 +281,7 @@ static int part_get_info_extended(struct blk_desc *desc, for (i = 0; i < 4; i++, pt++) { if (is_extended (pt->sys_ind)) { lbaint_t lba_start - = get_unaligned_le32 (pt->start4) + relative; + = get_unaligned_le32 (&pt->start_sect) + relative; return part_get_info_extended(desc, lba_start, ext_part_sector == 0 ? lba_start : relative, @@ -356,8 +356,8 @@ static void mbr_fill_pt_entry(dos_partition_t *pt, lbaint_t start, pt->sys_ind = sys_ind; lba_to_chs(start, &pt->cyl, &pt->head, &pt->sector); lba_to_chs(start + size - 1, &pt->end_cyl, &pt->end_head, &pt->end_sector); - put_unaligned_le32(relative, &pt->start4); - put_unaligned_le32(size, &pt->size4); + put_unaligned_le32(relative, &pt->start_sect); + put_unaligned_le32(size, &pt->nr_sects); } int write_mbr_partitions(struct blk_desc *dev, diff --git a/include/part_dos.h b/include/part_dos.h index 50558224228..92956d53063 100644 --- a/include/part_dos.h +++ b/include/part_dos.h @@ -30,8 +30,8 @@ typedef struct dos_partition { unsigned char end_head; /* end head */ unsigned char end_sector; /* end sector */ unsigned char end_cyl; /* end cylinder */ - unsigned char start4[4]; /* starting sector counting from 0 */ - unsigned char size4[4]; /* nr of sectors in partition */ -} dos_partition_t; + __le32 start_sect; /* starting sector counting from 0 */ + __le32 nr_sects; /* nr of sectors in partition */ +} __packed dos_partition_t; #endif /* _DISK_PART_DOS_H */ -- cgit v1.3.1 From aee9b7d0e0ba42caefc07c2c8d119b875dc58ba3 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 12 Feb 2026 21:44:57 +0100 Subject: disk: part_efi: Remove redundant struct partition definition Now that dos_partition_t and struct partition are identical, the duplicated data structure definition in the part_efi.h header can just be removed. This results in a single, shared definition for MBR partition table entries, instead of having the same definition in two different places. Signed-off-by: Javier Martinez Canillas Reviewed-by: Tom Rini Reviewed-by: Ilias Apalodimas --- disk/part_efi.c | 4 ++-- include/part_efi.h | 19 +++---------------- 2 files changed, 5 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/disk/part_efi.c b/disk/part_efi.c index fb1ed534f86..d8b17ec2e91 100644 --- a/disk/part_efi.c +++ b/disk/part_efi.c @@ -51,7 +51,7 @@ static inline u32 efi_crc32(const void *buf, u32 len) * Private function prototypes */ -static int pmbr_part_valid(struct partition *part); +static int pmbr_part_valid(dos_partition_t *part); static int is_pmbr_valid(legacy_mbr * mbr); static int is_gpt_valid(struct blk_desc *desc, u64 lba, gpt_header *pgpt_head, gpt_entry **pgpt_pte); @@ -990,7 +990,7 @@ int write_mbr_and_gpt_partitions(struct blk_desc *desc, void *buf) * * Returns: 1 if EFI GPT partition type is found. */ -static int pmbr_part_valid(struct partition *part) +static int pmbr_part_valid(dos_partition_t *part) { if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT && get_unaligned_le32(&part->start_sect) == 1UL) { diff --git a/include/part_efi.h b/include/part_efi.h index fb402df6f13..2cea5088046 100644 --- a/include/part_efi.h +++ b/include/part_efi.h @@ -18,6 +18,7 @@ #define _DISK_PART_EFI_H #include +#include #define MSDOS_MBR_SIGNATURE 0xAA55 #define MSDOS_MBR_BOOT_CODE_SIZE 440 @@ -77,20 +78,6 @@ /* linux/include/efi.h */ typedef u16 efi_char16_t; -/* based on linux/include/genhd.h */ -struct partition { - u8 boot_ind; /* 0x80 - active */ - u8 head; /* starting head */ - u8 sector; /* starting sector */ - u8 cyl; /* starting cylinder */ - u8 sys_ind; /* What partition type */ - u8 end_head; /* end head */ - u8 end_sector; /* end sector */ - u8 end_cyl; /* end cylinder */ - __le32 start_sect; /* starting sector counting from 0 */ - __le32 nr_sects; /* nr of sectors in partition */ -} __packed; - /* based on linux/fs/partitions/efi.h */ typedef struct _gpt_header { __le64 signature; @@ -134,7 +121,7 @@ typedef struct _legacy_mbr { u8 boot_code[MSDOS_MBR_BOOT_CODE_SIZE]; __le32 unique_mbr_signature; __le16 unknown; - struct partition partition_record[4]; + dos_partition_t partition_record[4]; __le16 signature; } __packed legacy_mbr; @@ -153,7 +140,7 @@ struct efi_partition_info { u8 system; u8 reserved[7]; union { - struct partition mbr; + dos_partition_t mbr; gpt_entry gpt; } info; } __packed; -- cgit v1.3.1 From 5e8025588862a1ec6da14af97e244a491d079e7f Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Thu, 12 Feb 2026 21:44:59 +0100 Subject: disk: part_dos: Refactor to allow retrieving raw MBR partition data Refactor the part_get_info_extended() helper function (which already recursively traverses DOS partitions) to optionally return the raw MBR partition structure (dos_partition_t). This allows other subsystems, such as EFI, to retrieve the partition details in the legacy MBR format. Signed-off-by: Javier Martinez Canillas Reviewed-by: Ilias Apalodimas --- disk/part_dos.c | 66 +++++++++++++++++++++++++++++++++++---------------------- include/part.h | 14 ++++++++++++ 2 files changed, 55 insertions(+), 25 deletions(-) (limited to 'include') diff --git a/disk/part_dos.c b/disk/part_dos.c index a69ad896210..4e1d01b2f21 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -204,7 +204,8 @@ static void print_partition_extended(struct blk_desc *desc, * @relative: Relative offset for the partition * @part_num: Current partition number * @which_part: Target partition number - * @info: Returns a pointer to the partition info + * @info: Returns partition information (optional) + * @mbr: Returns MBR partition entry (optional) * @disksig: Disk signature * * Return: 0 on success, negative on error @@ -212,7 +213,9 @@ static void print_partition_extended(struct blk_desc *desc, static int part_get_info_extended(struct blk_desc *desc, lbaint_t ext_part_sector, lbaint_t relative, int part_num, int which_part, - struct disk_partition *info, uint disksig) + struct disk_partition *info, + dos_partition_t *mbr, + uint disksig) { ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, desc->blksz); struct disk_partition wdinfo = { 0 }; @@ -243,9 +246,11 @@ static int part_get_info_extended(struct blk_desc *desc, if (CONFIG_IS_ENABLED(PARTITION_UUIDS) && !ext_part_sector) disksig = get_unaligned_le32(&buffer[DOS_PART_DISKSIG_OFFSET]); - ret = part_get_info_whole_disk(desc, &wdinfo); - if (ret) - return ret; + if (info) { + ret = part_get_info_whole_disk(desc, &wdinfo); + if (ret) + return ret; + } /* Print all primary/logical partitions */ pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET); @@ -258,25 +263,29 @@ static int part_get_info_extended(struct blk_desc *desc, (pt->sys_ind != 0) && (part_num == which_part) && (ext_part_sector == 0 || is_extended(pt->sys_ind) == 0)) { - if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) - info->blksz = wdinfo.blksz; - else - info->blksz = DOS_PART_DEFAULT_SECTOR; - info->start = (lbaint_t)(ext_part_sector + - get_unaligned_le32(&pt->start_sect)); - info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); - part_set_generic_name(desc, part_num, - (char *)info->name); - /* sprintf(info->type, "%d, pt->sys_ind); */ - strcpy((char *)info->type, "U-Boot"); - info->bootable = get_bootable(pt); - if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { - char str[12]; - - sprintf(str, "%08x-%02x", disksig, part_num); - disk_partition_set_uuid(info, str); + if (info) { + if (wdinfo.blksz > DOS_PART_DEFAULT_SECTOR) + info->blksz = wdinfo.blksz; + else + info->blksz = DOS_PART_DEFAULT_SECTOR; + info->start = (lbaint_t)(ext_part_sector + + get_unaligned_le32(&pt->start_sect)); + info->size = (lbaint_t)get_unaligned_le32(&pt->nr_sects); + part_set_generic_name(desc, part_num, + (char *)info->name); + /* sprintf(info->type, "%d, pt->sys_ind); */ + strcpy((char *)info->type, "U-Boot"); + info->bootable = get_bootable(pt); + if (CONFIG_IS_ENABLED(PARTITION_UUIDS)) { + char str[12]; + + sprintf(str, "%08x-%02x", disksig, part_num); + disk_partition_set_uuid(info, str); + } + info->sys_ind = pt->sys_ind; } - info->sys_ind = pt->sys_ind; + if (mbr) + memcpy(mbr, pt, sizeof(*mbr)); return 0; } @@ -296,7 +305,8 @@ static int part_get_info_extended(struct blk_desc *desc, return part_get_info_extended(desc, lba_start, ext_part_sector == 0 ? lba_start : relative, - part_num, which_part, info, disksig); + part_num, which_part, info, + mbr, disksig); } } @@ -328,7 +338,13 @@ static void __maybe_unused part_print_dos(struct blk_desc *desc) static int __maybe_unused part_get_info_dos(struct blk_desc *desc, int part, struct disk_partition *info) { - return part_get_info_extended(desc, 0, 0, 1, part, info, 0); + return part_get_info_extended(desc, 0, 0, 1, part, info, NULL, 0); +} + +int __maybe_unused part_get_mbr(struct blk_desc *desc, int part, + dos_partition_t *mbr) +{ + return part_get_info_extended(desc, 0, 0, 1, part, NULL, mbr, 0); } int is_valid_dos_buf(void *buf) diff --git a/include/part.h b/include/part.h index daebbbc2e68..aed089d00f6 100644 --- a/include/part.h +++ b/include/part.h @@ -704,6 +704,20 @@ int write_mbr_partitions(struct blk_desc *dev, int layout_mbr_partitions(struct disk_partition *p, int count, lbaint_t total_sectors); +/** + * part_get_mbr() - get the MBR partition record of a partition + * + * This function reads the MBR partition record for a given block + * device and partition number. + * + * @desc: block device descriptor + * @part: partition number for which to return the partition record + * @mbr: MBR partition record + * + * Return: 0 on success, otherwise error + */ +int part_get_mbr(struct blk_desc *desc, int part, dos_partition_t *mbr); + #endif #if CONFIG_IS_ENABLED(PARTITIONS) -- cgit v1.3.1 From 38ea3bfc6506174c3ae219b33171db2c2098afd1 Mon Sep 17 00:00:00 2001 From: Shantur Rathore Date: Wed, 11 Feb 2026 16:56:20 +0100 Subject: efi_var_file: refactor to move buffer functions Currently efi_var_file.c has functions to store/read EFI variables to/from memory buffer. These functions can be used with other EFI variable stores so move them out to efi_var_common.c Signed-off-by: Shantur Rathore Signed-off-by: Michal Simek Tested-by: Neil Armstrong # on AML-S905D3-CC Reviewed-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- include/efi_variable.h | 5 ++++ lib/efi_loader/Makefile | 2 +- lib/efi_loader/efi_var_common.c | 42 ++++++++++++++++++++++++++++++ lib/efi_loader/efi_var_file.c | 57 ----------------------------------------- lib/efi_loader/efi_variable.c | 17 ++++++++---- 5 files changed, 60 insertions(+), 63 deletions(-) (limited to 'include') diff --git a/include/efi_variable.h b/include/efi_variable.h index 4065cf45eca..ee68fa4a885 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -161,6 +161,11 @@ efi_status_t efi_var_to_file(void); efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t *lenp, u32 check_attr_mask); +/* GUID used by Shim to store the MOK database */ +#define SHIM_LOCK_GUID \ + EFI_GUID(0x605dab50, 0xe046, 0x4300, \ + 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) + /** * efi_var_restore() - restore EFI variables from buffer * diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index f490081f654..ca1775eb03b 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -53,7 +53,7 @@ ifeq ($(CONFIG_EFI_MM_COMM_TEE),y) obj-y += efi_variable_tee.o else obj-y += efi_variable.o -obj-y += efi_var_file.o +obj-$(CONFIG_EFI_VARIABLE_FILE_STORE) += efi_var_file.o obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o endif obj-y += efi_watchdog.o diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index 4b34a58b4cf..5ea1688dca3 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -41,6 +41,7 @@ static const struct efi_auth_var_name_type name_type[] = { static bool efi_secure_boot; static enum efi_secure_mode efi_secure_mode; +static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID; /** * efi_efi_get_variable() - retrieve value of a UEFI variable @@ -488,3 +489,44 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * return EFI_SUCCESS; } + +efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) +{ + struct efi_var_entry *var, *last_var; + u16 *data; + efi_status_t ret; + + if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC || + buf->crc32 != crc32(0, (u8 *)buf->var, + buf->length - sizeof(struct efi_var_file))) { + log_err("Invalid EFI variables file\n"); + return EFI_INVALID_PARAMETER; + } + + last_var = (struct efi_var_entry *)((u8 *)buf + buf->length); + for (var = buf->var; var < last_var; + var = (struct efi_var_entry *)ALIGN((uintptr_t)data + var->length, 8)) { + data = var->name + u16_strlen(var->name) + 1; + + /* + * Secure boot related and volatile variables shall only be + * restored from U-Boot's preseed. + */ + if (!safe && + (efi_auth_var_get_type(var->name, &var->guid) != + EFI_AUTH_VAR_NONE || + !guidcmp(&var->guid, &shim_lock_guid) || + !(var->attr & EFI_VARIABLE_NON_VOLATILE))) + continue; + if (!var->length) + continue; + if (efi_var_mem_find(&var->guid, var->name, NULL)) + continue; + ret = efi_var_mem_ins(var->name, &var->guid, var->attr, + var->length, data, 0, NULL, + var->time); + if (ret != EFI_SUCCESS) + log_err("Failed to set EFI variable %ls\n", var->name); + } + return EFI_SUCCESS; +} diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index f23a964a418..4061a463b58 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -14,17 +14,9 @@ #include #include #include -#include #define PART_STR_LEN 10 -/* GUID used by Shim to store the MOK database */ -#define SHIM_LOCK_GUID \ - EFI_GUID(0x605dab50, 0xe046, 0x4300, \ - 0xab, 0xb6, 0x3d, 0xd8, 0x10, 0xdd, 0x8b, 0x23) - -static const efi_guid_t shim_lock_guid = SHIM_LOCK_GUID; - /** * efi_set_blk_dev_to_system_partition() - select EFI system partition * @@ -59,7 +51,6 @@ static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void) */ efi_status_t efi_var_to_file(void) { -#ifdef CONFIG_EFI_VARIABLE_FILE_STORE efi_status_t ret; struct efi_var_file *buf; loff_t len; @@ -91,52 +82,6 @@ error: out: free(buf); return ret; -#else - return EFI_SUCCESS; -#endif -} - -efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) -{ - struct efi_var_entry *var, *last_var; - u16 *data; - efi_status_t ret; - - if (buf->reserved || buf->magic != EFI_VAR_FILE_MAGIC || - buf->crc32 != crc32(0, (u8 *)buf->var, - buf->length - sizeof(struct efi_var_file))) { - log_err("Invalid EFI variables file\n"); - return EFI_INVALID_PARAMETER; - } - - last_var = (struct efi_var_entry *)((u8 *)buf + buf->length); - for (var = buf->var; var < last_var; - var = (struct efi_var_entry *) - ALIGN((uintptr_t)data + var->length, 8)) { - - data = var->name + u16_strlen(var->name) + 1; - - /* - * Secure boot related and volatile variables shall only be - * restored from U-Boot's preseed. - */ - if (!safe && - (efi_auth_var_get_type(var->name, &var->guid) != - EFI_AUTH_VAR_NONE || - !guidcmp(&var->guid, &shim_lock_guid) || - !(var->attr & EFI_VARIABLE_NON_VOLATILE))) - continue; - if (!var->length) - continue; - if (efi_var_mem_find(&var->guid, var->name, NULL)) - continue; - ret = efi_var_mem_ins(var->name, &var->guid, var->attr, - var->length, data, 0, NULL, - var->time); - if (ret != EFI_SUCCESS) - log_err("Failed to set EFI variable %ls\n", var->name); - } - return EFI_SUCCESS; } /** @@ -155,7 +100,6 @@ efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) */ efi_status_t efi_var_from_file(void) { -#ifdef CONFIG_EFI_VARIABLE_FILE_STORE struct efi_var_file *buf; loff_t len; efi_status_t ret; @@ -180,6 +124,5 @@ efi_status_t efi_var_from_file(void) log_err("Invalid EFI variables file\n"); error: free(buf); -#endif return EFI_SUCCESS; } diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index f3533f4def3..6e45134c61b 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -397,11 +397,15 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, ret = EFI_SUCCESS; /* - * Write non-volatile EFI variables to file + * Write non-volatile EFI variables * TODO: check if a value change has occured to avoid superfluous writes */ - if (attributes & EFI_VARIABLE_NON_VOLATILE) + if (attributes & EFI_VARIABLE_NON_VOLATILE) { + if (IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) + return EFI_SUCCESS; + efi_var_to_file(); + } return EFI_SUCCESS; } @@ -594,9 +598,12 @@ efi_status_t efi_init_variables(void) if (ret != EFI_SUCCESS) return ret; - ret = efi_var_from_file(); - if (ret != EFI_SUCCESS) - return ret; + if (!IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) { + ret = efi_var_from_file(); + if (ret != EFI_SUCCESS) + return ret; + } + if (IS_ENABLED(CONFIG_EFI_VARIABLES_PRESEED)) { ret = efi_var_restore((struct efi_var_file *) __efi_var_file_begin, true); -- cgit v1.3.1 From 4fcc248c943b10889789f23b372ce37e06614a84 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 11 Feb 2026 16:56:21 +0100 Subject: efi_var: Unify read/write access helper function efi_var_to/from_file() suggest method where variables are placed. But there is no reason for it and generic name can be used to wire also different locations for variables. Signed-off-by: Michal Simek Reviewed-by: Ilias Apalodimas Tested-by: Neil Armstrong # on AML-S905D3-CC Reviewed-by: Heinrich Schuchardt --- include/efi_variable.h | 13 ++++--------- lib/efi_loader/efi_var_file.c | 8 ++++---- lib/efi_loader/efi_variable.c | 4 ++-- 3 files changed, 10 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/include/efi_variable.h b/include/efi_variable.h index ee68fa4a885..fc1184e5ca1 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -137,13 +137,11 @@ struct efi_var_file { }; /** - * efi_var_to_file() - save non-volatile variables as file - * - * File ubootefi.var is created on the EFI system partion. + * efi_var_to_storage() - save non-volatile variables * * Return: status code */ -efi_status_t efi_var_to_file(void); +efi_status_t efi_var_to_storage(void); /** * efi_var_collect() - collect variables in buffer @@ -178,17 +176,14 @@ efi_status_t __maybe_unused efi_var_collect(struct efi_var_file **bufp, loff_t * efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe); /** - * efi_var_from_file() - read variables from file - * - * File ubootefi.var is read from the EFI system partitions and the variables - * stored in the file are created. + * efi_var_from_storage() - read variables * * In case the file does not exist yet or a variable cannot be set EFI_SUCCESS * is returned. * * Return: status code */ -efi_status_t efi_var_from_file(void); +efi_status_t efi_var_from_storage(void); /** * efi_var_mem_init() - set-up variable list diff --git a/lib/efi_loader/efi_var_file.c b/lib/efi_loader/efi_var_file.c index 4061a463b58..9cda38f319e 100644 --- a/lib/efi_loader/efi_var_file.c +++ b/lib/efi_loader/efi_var_file.c @@ -43,13 +43,13 @@ static efi_status_t __maybe_unused efi_set_blk_dev_to_system_partition(void) } /** - * efi_var_to_file() - save non-volatile variables as file + * efi_var_to_storage() - save non-volatile variables as file * * File ubootefi.var is created on the EFI system partion. * * Return: status code */ -efi_status_t efi_var_to_file(void) +efi_status_t efi_var_to_storage(void) { efi_status_t ret; struct efi_var_file *buf; @@ -85,7 +85,7 @@ out: } /** - * efi_var_from_file() - read variables from file + * efi_var_from_storage() - read variables from file * * File ubootefi.var is read from the EFI system partitions and the variables * stored in the file are created. @@ -98,7 +98,7 @@ out: * * Return: status code */ -efi_status_t efi_var_from_file(void) +efi_status_t efi_var_from_storage(void) { struct efi_var_file *buf; loff_t len; diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 6e45134c61b..8512bc20f11 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -404,7 +404,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) return EFI_SUCCESS; - efi_var_to_file(); + efi_var_to_storage(); } return EFI_SUCCESS; @@ -599,7 +599,7 @@ efi_status_t efi_init_variables(void) return ret; if (!IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) { - ret = efi_var_from_file(); + ret = efi_var_from_storage(); if (ret != EFI_SUCCESS) return ret; } -- cgit v1.3.1 From 0f90b1e715f8abe41b0875752eb184f46032ff11 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 9 Feb 2026 09:30:18 +0800 Subject: treewide: Clean up DECLARE_GLOBAL_DATA_PTR usage Remove DECLARE_GLOBAL_DATA_PTR from files where gd is not used, and drop the unnecessary inclusion of asm/global_data.h. Headers should be included directly by the files that need them, rather than indirectly via global_data.h. Reviewed-by: Patrice Chotard #STMicroelectronics boards and STM32MP1 ram test driver Tested-by: Anshul Dalal #TI boards Acked-by: Yao Zi #TH1520 Signed-off-by: Peng Fan --- arch/arc/lib/bootm.c | 3 --- arch/arm/cpu/armv7/s5p4418/cpu.c | 3 --- arch/arm/mach-aspeed/ast2600/spl.c | 3 --- arch/arm/mach-imx/imx8/clock.c | 3 --- arch/arm/mach-imx/imx8/fdt.c | 3 --- arch/arm/mach-imx/imx8/iomux.c | 3 --- arch/arm/mach-imx/imx8m/clock_imx8mm.c | 3 --- arch/arm/mach-imx/imx8ulp/cgc.c | 3 --- arch/arm/mach-imx/imx8ulp/clock.c | 3 --- arch/arm/mach-imx/imx9/clock.c | 3 --- arch/arm/mach-imx/imx9/clock_root.c | 3 --- arch/arm/mach-imx/misc.c | 3 --- arch/arm/mach-imx/spl_imx_romapi.c | 3 --- arch/arm/mach-meson/board-axg.c | 3 --- arch/arm/mach-meson/board-g12a.c | 3 --- arch/arm/mach-meson/board-gx.c | 3 --- arch/arm/mach-socfpga/clock_manager_agilex.c | 3 --- arch/arm/mach-socfpga/clock_manager_agilex5.c | 3 --- arch/arm/mach-socfpga/clock_manager_n5x.c | 3 --- arch/arm/mach-socfpga/clock_manager_s10.c | 3 --- arch/arm/mach-socfpga/mailbox_s10.c | 3 --- arch/arm/mach-socfpga/misc_gen5.c | 3 --- arch/arm/mach-socfpga/misc_soc64.c | 3 --- arch/arm/mach-socfpga/mmu-arm64_s10.c | 3 --- arch/arm/mach-socfpga/reset_manager_s10.c | 3 --- arch/arm/mach-socfpga/spl_agilex.c | 3 --- arch/arm/mach-socfpga/spl_agilex5.c | 3 --- arch/arm/mach-socfpga/spl_agilex7m.c | 3 --- arch/arm/mach-socfpga/spl_gen5.c | 3 --- arch/arm/mach-socfpga/spl_n5x.c | 3 --- arch/arm/mach-socfpga/spl_s10.c | 3 --- arch/arm/mach-socfpga/system_manager_soc64.c | 3 --- arch/microblaze/lib/bootm.c | 3 --- arch/mips/mach-ath79/qca956x/ddr.c | 3 --- arch/mips/mach-mscc/cpu.c | 3 --- arch/mips/mach-mtmips/ddr_cal.c | 3 --- arch/mips/mach-octeon/cvmx-pko.c | 2 -- arch/nios2/lib/bootm.c | 3 --- arch/riscv/cpu/andes/spl.c | 3 --- arch/riscv/cpu/cv1800b/dram.c | 3 --- arch/riscv/cpu/generic/dram.c | 3 --- arch/riscv/cpu/k230/dram.c | 3 --- arch/riscv/cpu/th1520/spl.c | 2 -- arch/sh/lib/bootm.c | 3 --- arch/x86/cpu/ivybridge/model_206ax.c | 3 --- arch/x86/lib/init_helpers.c | 3 --- arch/x86/lib/zimage.c | 3 --- arch/xtensa/lib/time.c | 3 --- board/BuR/brsmarc1/board.c | 3 --- board/BuR/common/common.c | 3 --- board/Marvell/octeontx/smc.c | 3 --- board/Marvell/octeontx2/smc.c | 3 --- board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c | 2 -- board/advantech/imx8mp_rsb3720a1/spl.c | 2 -- board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c | 2 -- board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c | 3 --- board/andestech/voyager/voyager.c | 3 --- board/armltd/vexpress64/vexpress64.c | 3 --- board/beacon/imx8mm/spl.c | 3 --- board/beacon/imx8mn/spl.c | 3 --- board/beacon/imx8mp/spl.c | 3 --- board/beagle/beagleboneai64/beagleboneai64.c | 2 -- board/beagle/beagleplay/beagleplay.c | 2 -- board/broadcom/bcmns/ns.c | 3 --- board/cloos/imx8mm_phg/imx8mm_phg.c | 3 --- board/cloos/imx8mm_phg/spl.c | 3 --- board/compulab/imx8mm-cl-iot-gate/spl.c | 2 -- board/coreboot/coreboot/coreboot.c | 3 --- board/cssi/cmpc885/cmpc885.c | 2 -- board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c | 2 -- board/data_modul/imx8mm_edm_sbc/spl.c | 2 -- board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c | 2 -- board/data_modul/imx8mp_edm_sbc/spl.c | 2 -- board/dhelectronics/dh_imx8mp/common.c | 2 -- board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c | 2 -- board/dhelectronics/dh_imx8mp/spl.c | 2 -- board/emcraft/imx8mp_navqp/spl.c | 3 --- board/emulation/qemu-riscv/qemu-riscv.c | 2 -- board/engicam/imx8mm/icore_mx8mm.c | 2 -- board/engicam/imx8mm/spl.c | 2 -- board/engicam/imx8mp/icore_mx8mp.c | 3 --- board/engicam/imx8mp/spl.c | 3 --- board/gdsys/mpc8308/gazerbeam.c | 3 --- board/google/imx8mq_phanbell/imx8mq_phanbell.c | 3 --- board/highbank/highbank.c | 3 --- board/kontron/osm-s-mx8mp/osm-s-mx8mp.c | 3 --- board/kontron/osm-s-mx93/osm-s-mx93.c | 3 --- board/kontron/pitx_imx8m/pitx_imx8m.c | 2 -- board/mntre/imx8mq_reform2/imx8mq_reform2.c | 3 --- board/msc/sm2s_imx8mp/sm2s_imx8mp.c | 2 -- board/msc/sm2s_imx8mp/spl.c | 3 --- board/nxp/imx8mm_evk/spl.c | 3 --- board/nxp/imx8qm_mek/imx8qm_mek.c | 3 --- board/nxp/imx8qxp_mek/imx8qxp_mek.c | 3 --- board/phytec/imx8mp-libra-fpsc/spl.c | 3 --- board/phytec/phycore_imx8mm/phycore-imx8mm.c | 3 --- board/phytec/phycore_imx8mm/spl.c | 3 --- board/phytec/phycore_imx8mp/phycore-imx8mp.c | 3 --- board/phytec/phycore_imx8mp/spl.c | 3 --- board/phytec/phycore_imx93/phycore-imx93.c | 3 --- board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c | 3 --- board/polyhex/imx8mp_debix_model_a/spl.c | 3 --- board/purism/librem5/librem5.c | 2 -- board/purism/librem5/spl.c | 2 -- board/qualcomm/dragonboard410c/dragonboard410c.c | 3 --- board/qualcomm/dragonboard820c/dragonboard820c.c | 3 --- board/renesas/common/gen3-common.c | 3 --- board/renesas/common/gen4-common.c | 3 --- board/renesas/common/gen5-common.c | 3 --- board/ronetix/imx8mq-cm/imx8mq_cm.c | 2 -- board/samsung/common/exynos5-dt.c | 3 --- board/samsung/common/misc.c | 3 --- board/st/stm32f429-discovery/stm32f429-discovery.c | 3 --- board/st/stm32f429-evaluation/stm32f429-evaluation.c | 3 --- board/st/stm32f469-discovery/stm32f469-discovery.c | 3 --- board/st/stm32f746-disco/stm32f746-disco.c | 3 --- board/st/stm32h743-disco/stm32h743-disco.c | 3 --- board/st/stm32h743-eval/stm32h743-eval.c | 3 --- board/st/stm32h747-disco/stm32h747-disco.c | 3 --- board/st/stm32h750-art-pi/stm32h750-art-pi.c | 3 --- board/technexion/pico-imx8mq/pico-imx8mq.c | 3 --- board/ti/am62x/evm.c | 2 -- board/ti/am64x/evm.c | 2 -- board/ti/j784s4/evm.c | 2 -- board/toradex/apalis-imx8/apalis-imx8.c | 3 --- board/toradex/apalis_t30/apalis_t30.c | 3 --- board/toradex/colibri-imx8x/colibri-imx8x.c | 3 --- board/toradex/colibri_t20/colibri_t20.c | 3 --- board/toradex/common/tdx-cfg-block.c | 3 --- board/toradex/smarc-imx8mp/smarc-imx8mp.c | 3 --- board/toradex/smarc-imx8mp/spl.c | 3 --- board/toradex/verdin-imx8mm/spl.c | 3 --- board/toradex/verdin-imx8mm/verdin-imx8mm.c | 3 --- board/toradex/verdin-imx8mp/spl.c | 3 --- board/toradex/verdin-imx8mp/verdin-imx8mp.c | 3 --- board/xilinx/zynq/bootimg.c | 3 --- boot/bootmeth-uclass.c | 2 -- boot/fdt_simplefb.c | 3 --- boot/image-sig.c | 2 -- boot/image.c | 3 --- cmd/bloblist.c | 3 --- cmd/bootefi.c | 3 --- cmd/bootm.c | 3 --- cmd/date.c | 3 --- cmd/mem.c | 3 --- cmd/sound.c | 3 --- cmd/spl.c | 3 --- common/cli_hush.c | 3 --- common/stdio.c | 3 --- drivers/block/sandbox.c | 3 --- drivers/bootcount/pmic_pfuze100.c | 2 -- drivers/cache/sandbox_cache.c | 3 --- drivers/clk/altera/clk-agilex.c | 3 --- drivers/clk/altera/clk-agilex5.c | 3 --- drivers/clk/altera/clk-mem-n5x.c | 3 --- drivers/clk/altera/clk-n5x.c | 3 --- drivers/clk/rockchip/clk_px30.c | 3 --- drivers/clk/rockchip/clk_rk3308.c | 3 --- drivers/clk/rockchip/clk_rk3528.c | 2 -- drivers/clk/rockchip/clk_rk3568.c | 2 -- drivers/clk/rockchip/clk_rk3576.c | 2 -- drivers/clk/rockchip/clk_rk3588.c | 2 -- drivers/clk/rockchip/clk_rv1108.c | 3 --- drivers/clk/rockchip/clk_rv1126.c | 2 -- drivers/cpu/bcm283x_cpu.c | 3 --- drivers/cpu/cpu-uclass.c | 2 -- drivers/cpu/imx8_cpu.c | 3 --- drivers/cpu/mtk_cpu.c | 3 --- drivers/firmware/arm-ffa/arm-ffa-uclass.c | 3 --- drivers/firmware/arm-ffa/arm-ffa.c | 3 --- drivers/firmware/arm-ffa/ffa-emul-uclass.c | 3 --- drivers/firmware/arm-ffa/sandbox_ffa.c | 3 --- drivers/gpio/gpio-uclass.c | 3 --- drivers/gpio/nx_gpio.c | 3 --- drivers/i2c/mxc_i2c.c | 3 --- drivers/i2c/nx_i2c.c | 3 --- drivers/i2c/ocores_i2c.c | 3 --- drivers/i2c/soft_i2c.c | 3 --- drivers/i2c/synquacer_i2c.c | 2 -- drivers/mailbox/imx-mailbox.c | 2 -- drivers/misc/atsha204a-i2c.c | 3 --- drivers/misc/fs_loader.c | 3 --- drivers/misc/imx8/fuse.c | 3 --- drivers/mmc/ca_dw_mmc.c | 3 --- drivers/mmc/f_sdh30.c | 2 -- drivers/mmc/jz_mmc.c | 3 --- drivers/mmc/msm_sdhci.c | 3 --- drivers/mmc/mv_sdhci.c | 3 --- drivers/mtd/nand/raw/pxa3xx_nand.c | 3 --- drivers/mtd/nand/raw/tegra_nand.c | 3 --- drivers/mtd/nvmxip/nvmxip_qspi.c | 3 --- drivers/mtd/spi/sf-uclass.c | 3 --- drivers/net/dwmac_s700.c | 3 --- drivers/net/fec_mxc.c | 3 --- drivers/net/gmac_rockchip.c | 2 -- drivers/net/mvneta.c | 3 --- drivers/net/octeontx/smi.c | 3 --- drivers/net/phy/fixed.c | 3 --- drivers/net/phy/phy.c | 3 --- drivers/net/phy/xilinx_gmii2rgmii.c | 3 --- drivers/net/sandbox-raw.c | 3 --- drivers/net/sandbox.c | 3 --- drivers/net/ti/keystone_net.c | 3 --- drivers/net/xilinx_axi_emac.c | 3 --- drivers/pci/pci_octeontx.c | 3 --- drivers/pci/pcie_dw_meson.c | 3 --- drivers/pci/pcie_dw_qcom.c | 3 --- drivers/pci/pcie_dw_rockchip.c | 3 --- drivers/pci/pcie_dw_ti.c | 3 --- drivers/pci/pcie_layerscape.c | 3 --- drivers/pci/pcie_starfive_jh7110.c | 3 --- drivers/pci_endpoint/pci_ep-uclass.c | 3 --- drivers/phy/marvell/comphy_core.c | 3 --- drivers/phy/omap-usb2-phy.c | 3 --- drivers/phy/rockchip/phy-rockchip-pcie.c | 3 --- drivers/phy/rockchip/phy-rockchip-typec.c | 3 --- drivers/pinctrl/mtmips/pinctrl-mt7628.c | 3 --- drivers/pinctrl/nexell/pinctrl-nexell.c | 3 --- drivers/pinctrl/nexell/pinctrl-s5pxx18.c | 3 --- drivers/pinctrl/nxp/pinctrl-imx-mmio.c | 3 --- drivers/pinctrl/nxp/pinctrl-imx.c | 3 --- drivers/pinctrl/nxp/pinctrl-imx8.c | 3 --- drivers/pinctrl/nxp/pinctrl-mxs.c | 3 --- drivers/power/domain/imx8m-power-domain.c | 3 --- drivers/power/pmic/bd71837.c | 3 --- drivers/power/pmic/mc34708.c | 3 --- drivers/power/pmic/mp5416.c | 3 --- drivers/power/pmic/pca9450.c | 3 --- drivers/power/regulator/pwm_regulator.c | 3 --- drivers/pwm/pwm-sifive.c | 3 --- drivers/pwm/rk_pwm.c | 3 --- drivers/pwm/sunxi_pwm.c | 3 --- drivers/ram/stm32mp1/stm32mp1_tests.c | 3 --- drivers/reboot-mode/reboot-mode-gpio.c | 2 -- drivers/reboot-mode/reboot-mode-rtc.c | 2 -- drivers/remoteproc/rproc-uclass.c | 2 -- drivers/serial/ns16550.c | 3 --- drivers/serial/sandbox.c | 3 --- drivers/serial/serial_adi_uart4.c | 2 -- drivers/serial/serial_htif.c | 3 --- drivers/serial/serial_xen.c | 3 --- drivers/smem/msm_smem.c | 3 --- drivers/spi/ca_sflash.c | 3 --- drivers/spi/microchip_coreqspi.c | 2 -- drivers/spi/mvebu_a3700_spi.c | 3 --- drivers/spi/omap3_spi.c | 3 --- drivers/spi/spi-sunxi.c | 3 --- drivers/spi/spi-synquacer.c | 2 -- drivers/spi/spi-uclass.c | 3 --- drivers/spi/tegra210_qspi.c | 3 --- drivers/spmi/spmi-msm.c | 3 --- drivers/thermal/imx_tmu.c | 3 --- drivers/timer/ostm_timer.c | 3 --- drivers/timer/sp804_timer.c | 3 --- drivers/usb/common/common.c | 3 --- drivers/usb/phy/rockchip_usb2_phy.c | 3 --- drivers/usb/tcpm/tcpm.c | 2 -- drivers/video/hx8238d.c | 2 -- drivers/video/imx/mxc_ipuv3_fb.c | 3 --- drivers/video/nexell_display.c | 3 --- drivers/video/rockchip/rk_lvds.c | 3 --- drivers/video/rockchip/rk_mipi.c | 3 --- drivers/video/sandbox_sdl.c | 3 --- drivers/video/tidss/tidss_drv.c | 2 -- drivers/video/zynqmp/zynqmp_dpsub.c | 3 --- drivers/watchdog/armada-37xx-wdt.c | 3 --- drivers/watchdog/at91sam9_wdt.c | 3 --- drivers/watchdog/mt7621_wdt.c | 3 --- drivers/watchdog/orion_wdt.c | 3 --- drivers/watchdog/sbsa_gwdt.c | 3 --- drivers/watchdog/wdt-uclass.c | 3 --- fs/fs.c | 3 --- fs/ubifs/ubifs.c | 3 --- include/relocate.h | 2 -- lib/efi_loader/efi_capsule.c | 3 --- lib/efi_loader/efi_gop.c | 3 --- lib/efi_loader/efi_rng.c | 3 --- net/eth-uclass.c | 3 --- net/tftp.c | 3 --- net/wget.c | 3 --- test/cmd/exit.c | 3 --- test/cmd/test_echo.c | 3 --- test/cmd/test_pause.c | 3 --- test/dm/blk.c | 3 --- test/dm/i3c.c | 2 -- test/lib/test_print.c | 3 --- test/log/log_filter.c | 3 --- 287 files changed, 810 deletions(-) (limited to 'include') diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index b143392ee6c..91bce5235a5 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int cleanup_before_linux(void) { diff --git a/arch/arm/cpu/armv7/s5p4418/cpu.c b/arch/arm/cpu/armv7/s5p4418/cpu.c index 27ffb450378..2c550439559 100644 --- a/arch/arm/cpu/armv7/s5p4418/cpu.c +++ b/arch/arm/cpu/armv7/s5p4418/cpu.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -15,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifndef CONFIG_ARCH_CPU_INIT #error must be define the macro "CONFIG_ARCH_CPU_INIT" #endif diff --git a/arch/arm/mach-aspeed/ast2600/spl.c b/arch/arm/mach-aspeed/ast2600/spl.c index 0c5a82ed094..60f2c5d291e 100644 --- a/arch/arm/mach-aspeed/ast2600/spl.c +++ b/arch/arm/mach-aspeed/ast2600/spl.c @@ -9,9 +9,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong dummy) { diff --git a/arch/arm/mach-imx/imx8/clock.c b/arch/arm/mach-imx/imx8/clock.c index 4e49b5bf375..e37d3bf31e4 100644 --- a/arch/arm/mach-imx/imx8/clock.c +++ b/arch/arm/mach-imx/imx8/clock.c @@ -3,12 +3,9 @@ * Copyright 2018 NXP */ -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 mxc_get_clock(enum mxc_clock clk) { switch (clk) { diff --git a/arch/arm/mach-imx/imx8/fdt.c b/arch/arm/mach-imx/imx8/fdt.c index ce78c8ce919..8337edc2f62 100644 --- a/arch/arm/mach-imx/imx8/fdt.c +++ b/arch/arm/mach-imx/imx8/fdt.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -14,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static bool check_owned_resource(sc_rsrc_t rsrc_id) { bool owned; diff --git a/arch/arm/mach-imx/imx8/iomux.c b/arch/arm/mach-imx/imx8/iomux.c index 3e27d75827a..b6175a50226 100644 --- a/arch/arm/mach-imx/imx8/iomux.c +++ b/arch/arm/mach-imx/imx8/iomux.c @@ -4,13 +4,10 @@ */ #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * configures a single pad in the iomuxer */ diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 77c8efc7899..b7b3702041e 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR; static u32 get_root_clk(enum clk_root_index clock_id); diff --git a/arch/arm/mach-imx/imx8ulp/cgc.c b/arch/arm/mach-imx/imx8ulp/cgc.c index f9d8ed5b048..69585a3605b 100644 --- a/arch/arm/mach-imx/imx8ulp/cgc.c +++ b/arch/arm/mach-imx/imx8ulp/cgc.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct cgc1_regs *cgc1_regs = (struct cgc1_regs *)0x292C0000UL; static struct cgc2_regs *cgc2_regs = (struct cgc2_regs *)0x2da60000UL; diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c index c390f20d769..1b5cbd56f50 100644 --- a/arch/arm/mach-imx/imx8ulp/clock.c +++ b/arch/arm/mach-imx/imx8ulp/clock.c @@ -12,11 +12,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #define PLL_USB_EN_USB_CLKS_MASK (0x01 << 6) #define PLL_USB_PWR_MASK (0x01 << 12) #define PLL_USB_ENABLE_MASK (0x01 << 13) diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index e65cabef2c9..14a2bdf5762 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct anatop_reg *ana_regs = (struct anatop_reg *)ANATOP_BASE_ADDR; static struct imx_intpll_rate_table imx9_intpll_tbl[] = { diff --git a/arch/arm/mach-imx/imx9/clock_root.c b/arch/arm/mach-imx/imx9/clock_root.c index 5dbc398e97f..acf79a40584 100644 --- a/arch/arm/mach-imx/imx9/clock_root.c +++ b/arch/arm/mach-imx/imx9/clock_root.c @@ -11,11 +11,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct ccm_reg *ccm_reg = (struct ccm_reg *)CCM_BASE_ADDR; static enum ccm_clk_src clk_root_mux[][4] = { diff --git a/arch/arm/mach-imx/misc.c b/arch/arm/mach-imx/misc.c index 7452b82f110..90d91b2300a 100644 --- a/arch/arm/mach-imx/misc.c +++ b/arch/arm/mach-imx/misc.c @@ -6,14 +6,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* 1 second delay should be plenty of time for block reset. */ #define RESET_MAX_TIMEOUT 1000000 diff --git a/arch/arm/mach-imx/spl_imx_romapi.c b/arch/arm/mach-imx/spl_imx_romapi.c index b7008df8e35..d36536e600e 100644 --- a/arch/arm/mach-imx/spl_imx_romapi.c +++ b/arch/arm/mach-imx/spl_imx_romapi.c @@ -7,13 +7,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Caller need ensure the offset and size to align with page size */ ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf) { diff --git a/arch/arm/mach-meson/board-axg.c b/arch/arm/mach-meson/board-axg.c index 6535539184c..542792cad1b 100644 --- a/arch/arm/mach-meson/board-axg.c +++ b/arch/arm/mach-meson/board-axg.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(AXG_AO_SEC_GP_CFG0) & AXG_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-g12a.c b/arch/arm/mach-meson/board-g12a.c index dc4abe1e107..17722cb897d 100644 --- a/arch/arm/mach-meson/board-g12a.c +++ b/arch/arm/mach-meson/board-g12a.c @@ -12,13 +12,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(G12A_AO_SEC_GP_CFG0) & G12A_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-meson/board-gx.c b/arch/arm/mach-meson/board-gx.c index 0370ed57e20..d5c506df22b 100644 --- a/arch/arm/mach-meson/board-gx.c +++ b/arch/arm/mach-meson/board-gx.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int meson_get_boot_device(void) { return readl(GX_AO_SEC_GP_CFG0) & GX_AO_BOOT_DEVICE; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c index 9987d5bcee6..95c7f044952 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c index 7ec28d91ef3..fa068a9eeb1 100644 --- a/arch/arm/mach-socfpga/clock_manager_agilex5.c +++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_n5x.c b/arch/arm/mach-socfpga/clock_manager_n5x.c index c4c071330fc..8e47b4b8f5b 100644 --- a/arch/arm/mach-socfpga/clock_manager_n5x.c +++ b/arch/arm/mach-socfpga/clock_manager_n5x.c @@ -6,15 +6,12 @@ #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static ulong cm_get_rate_dm(u32 id) { struct udevice *dev; diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index d6c64e98010..fd27470f967 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -7,14 +7,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * function to write the bypass register which requires a poll of the * busy bit diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index f9c34e85711..5e8768168d3 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -8,15 +8,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MBOX_READL(reg) \ readl(SOCFPGA_MAILBOX_ADDRESS + (reg)) diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 5259ef54d73..ae33051c00f 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - static struct pl310_regs *const pl310 = (struct pl310_regs *)CFG_SYS_PL310_BASE; static struct nic301_registers *nic301_regs = diff --git a/arch/arm/mach-socfpga/misc_soc64.c b/arch/arm/mach-socfpga/misc_soc64.c index 5222b384434..356240a647e 100644 --- a/arch/arm/mach-socfpga/misc_soc64.c +++ b/arch/arm/mach-socfpga/misc_soc64.c @@ -17,11 +17,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - /* Agilex5 Sub Device Jtag ID List */ #define A3690_JTAG_ID 0x036090DD #define A3694_JTAG_ID 0x436090DD diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index 1dc44ab4797..1a7f8d42415 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -5,9 +5,6 @@ */ #include -#include - -DECLARE_GLOBAL_DATA_PTR; #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) static struct mm_region socfpga_agilex5_mem_map[] = { diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index abb62a9b49f..7e1ecc1cd1d 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_300MS 300 /* F2S manager registers */ diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c index 48f258a37b4..53a9aa55f80 100644 --- a/arch/arm/mach-socfpga/spl_agilex.c +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex5.c b/arch/arm/mach-socfpga/spl_agilex5.c index 1be347360f5..2c3e40b664a 100644 --- a/arch/arm/mach-socfpga/spl_agilex5.c +++ b/arch/arm/mach-socfpga/spl_agilex5.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 reset_flag(u32 flag) { /* Check rstmgr.stat for warm reset status */ diff --git a/arch/arm/mach-socfpga/spl_agilex7m.c b/arch/arm/mach-socfpga/spl_agilex7m.c index 90065ccee6f..7371202a712 100644 --- a/arch/arm/mach-socfpga/spl_agilex7m.c +++ b/arch/arm/mach-socfpga/spl_agilex7m.c @@ -15,14 +15,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index df79cfe0f7f..08b756db2ca 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 spl_boot_device(void) { const u32 bsel = readl(socfpga_get_sysmgr_addr() + diff --git a/arch/arm/mach-socfpga/spl_n5x.c b/arch/arm/mach-socfpga/spl_n5x.c index 81283ef7162..a49be837921 100644 --- a/arch/arm/mach-socfpga/spl_n5x.c +++ b/arch/arm/mach-socfpga/spl_n5x.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { int ret; diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index fa83ff96adc..a0d3c96d456 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c b/arch/arm/mach-socfpga/system_manager_soc64.c index 913f93c8f94..a5c0387190b 100644 --- a/arch/arm/mach-socfpga/system_manager_soc64.c +++ b/arch/arm/mach-socfpga/system_manager_soc64.c @@ -6,12 +6,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) /* * Setting RESET_PULSE_OVERRIDE bit for successful reset staggering pulse diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 4879a41aab3..2410515f4ac 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -17,12 +17,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static void boot_jump_linux(struct bootm_headers *images, int flag) { void (*thekernel)(char *cmdline, ulong rd, ulong dt); diff --git a/arch/mips/mach-ath79/qca956x/ddr.c b/arch/mips/mach-ath79/qca956x/ddr.c index 2e46e24f483..754e2573e37 100644 --- a/arch/mips/mach-ath79/qca956x/ddr.c +++ b/arch/mips/mach-ath79/qca956x/ddr.c @@ -5,7 +5,6 @@ * Based on QSDK */ -#include #include #include #include @@ -182,8 +181,6 @@ DDR_CTL_CONFIG_MISC_SRC1_SRAM_SYNC_SET(0x1) | \ DDR_CTL_CONFIG_MISC_SRC2_SRAM_SYNC_SET(0x1) -DECLARE_GLOBAL_DATA_PTR; - void qca956x_ddr_init(void) { u32 ddr_config, ddr_config2, ddr_config3, mod_val, \ diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 22b1b98e0ef..8ae6fb9437a 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -4,7 +4,6 @@ */ #include -#include #include #include @@ -14,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL diff --git a/arch/mips/mach-mtmips/ddr_cal.c b/arch/mips/mach-mtmips/ddr_cal.c index e2e1760a646..5fc4e0c49e8 100644 --- a/arch/mips/mach-mtmips/ddr_cal.c +++ b/arch/mips/mach-mtmips/ddr_cal.c @@ -7,13 +7,10 @@ #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define COARSE_MIN_START 6 #define FINE_MIN_START 15 #define COARSE_MAX_START 7 diff --git a/arch/mips/mach-octeon/cvmx-pko.c b/arch/mips/mach-octeon/cvmx-pko.c index 8a9181362bd..432488f7815 100644 --- a/arch/mips/mach-octeon/cvmx-pko.c +++ b/arch/mips/mach-octeon/cvmx-pko.c @@ -52,8 +52,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define CVMX_PKO_NQ_PER_PORT_MAX 32 static cvmx_pko_return_value_t cvmx_pko2_config_port(short ipd_port, diff --git a/arch/nios2/lib/bootm.c b/arch/nios2/lib/bootm.c index 71319839ba2..294ebfb508b 100644 --- a/arch/nios2/lib/bootm.c +++ b/arch/nios2/lib/bootm.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; #define NIOS_MAGIC 0x534f494e /* enable command line and initrd passing */ diff --git a/arch/riscv/cpu/andes/spl.c b/arch/riscv/cpu/andes/spl.c index a13dc4095a4..1e19fad9288 100644 --- a/arch/riscv/cpu/andes/spl.c +++ b/arch/riscv/cpu/andes/spl.c @@ -8,11 +8,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(RAM_SUPPORT) struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) { diff --git a/arch/riscv/cpu/cv1800b/dram.c b/arch/riscv/cpu/cv1800b/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/cv1800b/dram.c +++ b/arch/riscv/cpu/cv1800b/dram.c @@ -5,11 +5,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 91007c0a3d3..5d7659887b9 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -5,11 +5,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/k230/dram.c b/arch/riscv/cpu/k230/dram.c index b2d3e4fd6a9..5d7659887b9 100644 --- a/arch/riscv/cpu/k230/dram.c +++ b/arch/riscv/cpu/k230/dram.c @@ -3,13 +3,10 @@ * Copyright (C) 2018, Bin Meng */ -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/arch/riscv/cpu/th1520/spl.c b/arch/riscv/cpu/th1520/spl.c index b95470485f6..ceb934021d9 100644 --- a/arch/riscv/cpu/th1520/spl.c +++ b/arch/riscv/cpu/th1520/spl.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TH1520_SUBSYS_CLK (void __iomem *)(0xffff011000 + 0x220) #define TH1520_SUBSYS_CLK_VO_EN BIT(2) #define TH1520_SUBSYS_CLK_VI_EN BIT(1) diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index bb0f59e0aa2..1c118870dad 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -13,11 +13,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SH_SDRAM_OFFSET #define GET_INITRD_START(initrd, linux) (initrd - linux + CONFIG_SH_SDRAM_OFFSET) #else diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index b72de96a277..ed0ad686b3f 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void enable_vmx(void) { struct cpuid_result regs; diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index bd0efde00c1..96943cb8c46 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -5,13 +5,10 @@ */ #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - int init_cache_f_r(void) { bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) || diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 2ea9bcf59c2..a5f2231aa52 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -30,7 +30,6 @@ #include #include #include -#include #ifdef CONFIG_SYS_COREBOOT #include #endif @@ -38,8 +37,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * Memory lay-out: * diff --git a/arch/xtensa/lib/time.c b/arch/xtensa/lib/time.c index 319635c6b09..1fe33a4c62b 100644 --- a/arch/xtensa/lib/time.c +++ b/arch/xtensa/lib/time.c @@ -5,12 +5,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - #if XCHAL_HAVE_CCOUNT static ulong get_ccount(void) { diff --git a/board/BuR/brsmarc1/board.c b/board/BuR/brsmarc1/board.c index c05eec6b35e..01d7a8c39e2 100644 --- a/board/BuR/brsmarc1/board.c +++ b/board/BuR/brsmarc1/board.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ /* -- defines for used GPIO Hardware -- */ #define PER_RESET (2 * 32 + 0) -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_XPL_BUILD) static const struct ddr_data ddr3_data = { .datardsratio0 = MT41K256M16HA125E_RD_DQS, diff --git a/board/BuR/common/common.c b/board/BuR/common/common.c index 3513f43a9f5..bbafecd7909 100644 --- a/board/BuR/common/common.c +++ b/board/BuR/common/common.c @@ -13,12 +13,9 @@ #include #include #include -#include #include #include "bur_common.h" -DECLARE_GLOBAL_DATA_PTR; - /* --------------------------------------------------------------------------*/ int ft_board_setup(void *blob, struct bd_info *bd) diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c index 8df32049bda..ab6284a732c 100644 --- a/board/Marvell/octeontx/smc.c +++ b/board/Marvell/octeontx/smc.c @@ -5,13 +5,10 @@ * https://spdx.org/licenses */ -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/Marvell/octeontx2/smc.c b/board/Marvell/octeontx2/smc.c index 9e3169576c6..10645a74f69 100644 --- a/board/Marvell/octeontx2/smc.c +++ b/board/Marvell/octeontx2/smc.c @@ -5,15 +5,12 @@ * https://spdx.org/licenses */ -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - ssize_t smc_dram_size(unsigned int node) { struct pt_regs regs; diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 8c9e9830876..a9a12a4f659 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -26,8 +26,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_NAND_MXS static void setup_gpmi_nand(void) { diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 1f7c1f25adc..fb8e8437759 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -29,8 +29,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { #ifdef CONFIG_SPL_BOOTROM_SUPPORT diff --git a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c index accd300df04..fbe8b247e69 100644 --- a/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c +++ b/board/advantech/imx8qm_dmsse20_a1/imx8qm_dmsse20_a1.c @@ -16,8 +16,6 @@ #include /* #include */ -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c index 3def182f296..8214e627768 100644 --- a/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c +++ b/board/advantech/imx8qm_rom7720_a1/imx8qm_rom7720_a1.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/andestech/voyager/voyager.c b/board/andestech/voyager/voyager.c index dc8f1347775..23fd0910ef8 100644 --- a/board/andestech/voyager/voyager.c +++ b/board/andestech/voyager/voyager.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index e8f1c2fe9fe..d68da0e3d65 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - static const struct pl01x_serial_plat serial_plat = { .base = V2M_UART0, .type = TYPE_PL011, diff --git a/board/beacon/imx8mm/spl.c b/board/beacon/imx8mm/spl.c index 93ee5b7ee0c..1e5935788ff 100644 --- a/board/beacon/imx8mm/spl.c +++ b/board/beacon/imx8mm/spl.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/beacon/imx8mn/spl.c b/board/beacon/imx8mn/spl.c index e91d3fdcf5e..46db42ec921 100644 --- a/board/beacon/imx8mn/spl.c +++ b/board/beacon/imx8mn/spl.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -32,8 +31,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beacon/imx8mp/spl.c b/board/beacon/imx8mp/spl.c index 027fae38278..e82e385b774 100644 --- a/board/beacon/imx8mp/spl.c +++ b/board/beacon/imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/beagle/beagleboneai64/beagleboneai64.c b/board/beagle/beagleboneai64/beagleboneai64.c index 500fcc58ed8..27b1f22562c 100644 --- a/board/beagle/beagleboneai64/beagleboneai64.c +++ b/board/beagle/beagleboneai64/beagleboneai64.c @@ -13,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEBONEAI64_TIBOOT3_IMAGE_GUID, diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 9bc9ca30e95..70d296de9f8 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -14,8 +14,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = BEAGLEPLAY_TIBOOT3_IMAGE_GUID, diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c index 47a01227a35..cb53ec68cf8 100644 --- a/board/broadcom/bcmns/ns.c +++ b/board/broadcom/bcmns/ns.c @@ -9,12 +9,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { return fdtdec_setup_mem_size_base(); diff --git a/board/cloos/imx8mm_phg/imx8mm_phg.c b/board/cloos/imx8mm_phg/imx8mm_phg.c index 091c9a59a52..1ca1c07e08e 100644 --- a/board/cloos/imx8mm_phg/imx8mm_phg.c +++ b/board/cloos/imx8mm_phg/imx8mm_phg.c @@ -7,14 +7,11 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/cloos/imx8mm_phg/spl.c b/board/cloos/imx8mm_phg/spl.c index b8892ed2fcc..b2340a0ded3 100644 --- a/board/cloos/imx8mm_phg/spl.c +++ b/board/cloos/imx8mm_phg/spl.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/compulab/imx8mm-cl-iot-gate/spl.c b/board/compulab/imx8mm-cl-iot-gate/spl.c index 6d9af2538b6..daac6dca4ce 100644 --- a/board/compulab/imx8mm-cl-iot-gate/spl.c +++ b/board/compulab/imx8mm-cl-iot-gate/spl.c @@ -32,8 +32,6 @@ #include "ddr/ddr.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/coreboot/coreboot/coreboot.c b/board/coreboot/coreboot/coreboot.c index f2ca1076768..d0e8db6cdfe 100644 --- a/board/coreboot/coreboot/coreboot.c +++ b/board/coreboot/coreboot/coreboot.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int board_early_init_r(void) { diff --git a/board/cssi/cmpc885/cmpc885.c b/board/cssi/cmpc885/cmpc885.c index 49c13056edc..552349d104a 100644 --- a/board/cssi/cmpc885/cmpc885.c +++ b/board/cssi/cmpc885/cmpc885.c @@ -26,8 +26,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - #define ADDR_CPLD_R_RESET ((unsigned short __iomem *)CONFIG_CPLD_BASE) #define ADDR_CPLD_R_ETAT ((unsigned short __iomem *)(CONFIG_CPLD_BASE + 2)) #define ADDR_CPLD_R_TYPE ((unsigned char __iomem *)(CONFIG_CPLD_BASE + 3)) diff --git a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c index e271d060efa..ab4a484d393 100644 --- a/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mm_edm_sbc/imx8mm_data_modul_edm_sbc.c @@ -14,8 +14,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int board_late_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mm_edm_sbc/spl.c b/board/data_modul/imx8mm_edm_sbc/spl.c index a9ef049652a..c6a5740c7a7 100644 --- a/board/data_modul/imx8mm_edm_sbc/spl.c +++ b/board/data_modul/imx8mm_edm_sbc/spl.c @@ -27,8 +27,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c index d6f0a917023..5c319df1cde 100644 --- a/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c +++ b/board/data_modul/imx8mp_edm_sbc/imx8mp_data_modul_edm_sbc.c @@ -17,8 +17,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - static void dmo_setup_second_mac_address(void) { u8 enetaddr[6]; diff --git a/board/data_modul/imx8mp_edm_sbc/spl.c b/board/data_modul/imx8mp_edm_sbc/spl.c index f81b7274556..314f7e87a9d 100644 --- a/board/data_modul/imx8mp_edm_sbc/spl.c +++ b/board/data_modul/imx8mp_edm_sbc/spl.c @@ -28,8 +28,6 @@ #include "../common/common.h" -DECLARE_GLOBAL_DATA_PTR; - int data_modul_imx_edm_sbc_board_power_init(void) { struct udevice *dev; diff --git a/board/dhelectronics/dh_imx8mp/common.c b/board/dhelectronics/dh_imx8mp/common.c index f6db9f67804..5d89c94970d 100644 --- a/board/dhelectronics/dh_imx8mp/common.c +++ b/board/dhelectronics/dh_imx8mp/common.c @@ -8,8 +8,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - u8 dh_get_memcfg(void) { struct gpio_desc gpio[4]; diff --git a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c index 5c35a5bf447..3fe98d36f5b 100644 --- a/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c +++ b/board/dhelectronics/dh_imx8mp/imx8mp_dhcom_pdk2.c @@ -20,8 +20,6 @@ #include "../common/dh_common.h" #include "../common/dh_imx.h" -DECLARE_GLOBAL_DATA_PTR; - int mach_cpu_init(void) { icache_enable(); diff --git a/board/dhelectronics/dh_imx8mp/spl.c b/board/dhelectronics/dh_imx8mp/spl.c index 714f846521e..727e1ff3774 100644 --- a/board/dhelectronics/dh_imx8mp/spl.c +++ b/board/dhelectronics/dh_imx8mp/spl.c @@ -29,8 +29,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE) diff --git a/board/emcraft/imx8mp_navqp/spl.c b/board/emcraft/imx8mp_navqp/spl.c index 7f30f3af742..5ee94d078f8 100644 --- a/board/emcraft/imx8mp_navqp/spl.c +++ b/board/emcraft/imx8mp_navqp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/emulation/qemu-riscv/qemu-riscv.c b/board/emulation/qemu-riscv/qemu-riscv.c index 97c8211c100..ce5bc34ca71 100644 --- a/board/emulation/qemu-riscv/qemu-riscv.c +++ b/board/emulation/qemu-riscv/qemu-riscv.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_MTD_NOR_FLASH) int is_flash_available(void) { diff --git a/board/engicam/imx8mm/icore_mx8mm.c b/board/engicam/imx8mm/icore_mx8mm.c index 236337546ae..bb70e7d4ff8 100644 --- a/board/engicam/imx8mm/icore_mx8mm.c +++ b/board/engicam/imx8mm/icore_mx8mm.c @@ -19,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_FEC_MXC) #define FEC_RST_PAD IMX_GPIO_NR(3, 7) diff --git a/board/engicam/imx8mm/spl.c b/board/engicam/imx8mm/spl.c index d51ae241e85..5a6bcb1747a 100644 --- a/board/engicam/imx8mm/spl.c +++ b/board/engicam/imx8mm/spl.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/engicam/imx8mp/icore_mx8mp.c b/board/engicam/imx8mp/icore_mx8mp.c index bfdc447c478..864afa92aee 100644 --- a/board/engicam/imx8mp/icore_mx8mp.c +++ b/board/engicam/imx8mp/icore_mx8mp.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/engicam/imx8mp/spl.c b/board/engicam/imx8mp/spl.c index cd31aa6041d..c1aa28a17bc 100644 --- a/board/engicam/imx8mp/spl.c +++ b/board/engicam/imx8mp/spl.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/gdsys/mpc8308/gazerbeam.c b/board/gdsys/mpc8308/gazerbeam.c index 05e4d84460a..123dda21423 100644 --- a/board/gdsys/mpc8308/gazerbeam.c +++ b/board/gdsys/mpc8308/gazerbeam.c @@ -17,13 +17,10 @@ #include #include #include -#include #include "../common/ihs_mdio.h" #include "../../../drivers/sysinfo/gazerbeam.h" -DECLARE_GLOBAL_DATA_PTR; - struct ihs_mdio_info ihs_mdio_info[] = { { .fpga = NULL, .name = "ihs0", .base = 0x58 }, { .fpga = NULL, .name = "ihs1", .base = 0x58 }, diff --git a/board/google/imx8mq_phanbell/imx8mq_phanbell.c b/board/google/imx8mq_phanbell/imx8mq_phanbell.c index 9544d6dd19a..2f16f1da26c 100644 --- a/board/google/imx8mq_phanbell/imx8mq_phanbell.c +++ b/board/google/imx8mq_phanbell/imx8mq_phanbell.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 0ec88447384..62a7b5b0420 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include @@ -37,8 +36,6 @@ #define HB_SCU_A9_PWR_DORMANT 2 #define HB_SCU_A9_PWR_OFF 3 -DECLARE_GLOBAL_DATA_PTR; - void cphy_disable_overrides(void); /* diff --git a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c index 3db7176f723..739a78d2c8b 100644 --- a/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c +++ b/board/kontron/osm-s-mx8mp/osm-s-mx8mp.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - #if IS_ENABLED(CONFIG_KONTRON_HW_UID) struct uid_otp_loc uid_otp_locations[] = { { diff --git a/board/kontron/osm-s-mx93/osm-s-mx93.c b/board/kontron/osm-s-mx93/osm-s-mx93.c index d4645285771..b6feef549d1 100644 --- a/board/kontron/osm-s-mx93/osm-s-mx93.c +++ b/board/kontron/osm-s-mx93/osm-s-mx93.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include "../common/hw-uid.h" -DECLARE_GLOBAL_DATA_PTR; - int board_early_init_f(void) { return 0; diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index 2ee97169c6f..f71fa57b808 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c index 6ee1c5c52a1..bcb31564a73 100644 --- a/board/mntre/imx8mq_reform2/imx8mq_reform2.c +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) static iomux_v3_cfg_t const wdog_pads[] = { diff --git a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c index b1ce014bd55..b2f763dcc02 100644 --- a/board/msc/sm2s_imx8mp/sm2s_imx8mp.c +++ b/board/msc/sm2s_imx8mp/sm2s_imx8mp.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/msc/sm2s_imx8mp/spl.c b/board/msc/sm2s_imx8mp/spl.c index b1b5561838d..902179aad29 100644 --- a/board/msc/sm2s_imx8mp/spl.c +++ b/board/msc/sm2s_imx8mp/spl.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -33,8 +32,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/nxp/imx8mm_evk/spl.c b/board/nxp/imx8mm_evk/spl.c index cd251d274ff..5c588046ff4 100644 --- a/board/nxp/imx8mm_evk/spl.c +++ b/board/nxp/imx8mm_evk/spl.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -28,8 +27,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { diff --git a/board/nxp/imx8qm_mek/imx8qm_mek.c b/board/nxp/imx8qm_mek/imx8qm_mek.c index 72527f774ca..56f577714e7 100644 --- a/board/nxp/imx8qm_mek/imx8qm_mek.c +++ b/board/nxp/imx8qm_mek/imx8qm_mek.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/nxp/imx8qxp_mek/imx8qxp_mek.c b/board/nxp/imx8qxp_mek/imx8qxp_mek.c index adb9556a021..4bf6645b893 100644 --- a/board/nxp/imx8qxp_mek/imx8qxp_mek.c +++ b/board/nxp/imx8qxp_mek/imx8qxp_mek.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/phytec/imx8mp-libra-fpsc/spl.c b/board/phytec/imx8mp-libra-fpsc/spl.c index d704d588579..08111641aa6 100644 --- a/board/phytec/imx8mp-libra-fpsc/spl.c +++ b/board/phytec/imx8mp-libra-fpsc/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include "../common/imx8m_som_detection.h" #endif -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/phytec/phycore_imx8mm/phycore-imx8mm.c b/board/phytec/phycore_imx8mm/phycore-imx8mm.c index f6ae0bf0308..9f6a4ec704d 100644 --- a/board/phytec/phycore_imx8mm/phycore-imx8mm.c +++ b/board/phytec/phycore_imx8mm/phycore-imx8mm.c @@ -5,14 +5,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/phytec/phycore_imx8mm/spl.c b/board/phytec/phycore_imx8mm/spl.c index faff064779c..e688793bc74 100644 --- a/board/phytec/phycore_imx8mm/spl.c +++ b/board/phytec/phycore_imx8mm/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/phycore-imx8mp.c b/board/phytec/phycore_imx8mp/phycore-imx8mp.c index b345dc7c985..5f0a7ee6a94 100644 --- a/board/phytec/phycore_imx8mp/phycore-imx8mp.c +++ b/board/phytec/phycore_imx8mp/phycore-imx8mp.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -17,8 +16,6 @@ #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx8mp/spl.c b/board/phytec/phycore_imx8mp/spl.c index cb8e450b995..fc7aefd0073 100644 --- a/board/phytec/phycore_imx8mp/spl.c +++ b/board/phytec/phycore_imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include "lpddr4_timing.h" #include "../common/imx8m_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x51 #define EEPROM_ADDR_FALLBACK 0x59 diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c index cfc6d91f20f..cdaedd52c14 100644 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ b/board/phytec/phycore_imx93/phycore-imx93.c @@ -7,15 +7,12 @@ */ #include -#include #include #include #include #include "../common/imx93_som_detection.h" -DECLARE_GLOBAL_DATA_PTR; - #define EEPROM_ADDR 0x50 int board_init(void) diff --git a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c index c709d017483..7f0925074fa 100644 --- a/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c +++ b/board/polyhex/imx8mp_debix_model_a/imx8mp_debix_model_a.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void setup_fec(void) { struct iomuxc_gpr_base_regs *gpr = diff --git a/board/polyhex/imx8mp_debix_model_a/spl.c b/board/polyhex/imx8mp_debix_model_a/spl.c index 6cbd1815cad..c154ad7a1ce 100644 --- a/board/polyhex/imx8mp_debix_model_a/spl.c +++ b/board/polyhex/imx8mp_debix_model_a/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/purism/librem5/librem5.c b/board/purism/librem5/librem5.c index 5178ee6929d..a2bc0c08f0b 100644 --- a/board/purism/librem5/librem5.c +++ b/board/purism/librem5/librem5.c @@ -31,8 +31,6 @@ #include #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - int board_early_init_f(void) { return 0; diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index ed57554a2bc..568224f9732 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -29,8 +29,6 @@ #include #include "librem5.h" -DECLARE_GLOBAL_DATA_PTR; - void spl_dram_init(void) { /* ddr init */ diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 4698b9d5e3e..36e4d49046e 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -15,13 +15,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static u32 msm_board_serial(void) { struct mmc *mmc_dev; diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index 12a9273ec4b..236022a99f1 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ /* Strength (sdc1) */ #define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000) -DECLARE_GLOBAL_DATA_PTR; - static void sdhci_power_init(void) { const u32 TLMM_PULL_MASK = 0x3; diff --git a/board/renesas/common/gen3-common.c b/board/renesas/common/gen3-common.c index f89ae81e95e..5c543807b64 100644 --- a/board/renesas/common/gen3-common.c +++ b/board/renesas/common/gen3-common.c @@ -12,15 +12,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* If the firmware passed a device tree use it for e.g. U-Boot DRAM setup. */ extern u64 rcar_atf_boot_args[]; diff --git a/board/renesas/common/gen4-common.c b/board/renesas/common/gen4-common.c index 81c6f6f4c6d..ac87f2f08e3 100644 --- a/board/renesas/common/gen4-common.c +++ b/board/renesas/common/gen4-common.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/renesas/common/gen5-common.c b/board/renesas/common/gen5-common.c index 3b724e59049..c60a76c5038 100644 --- a/board/renesas/common/gen5-common.c +++ b/board/renesas/common/gen5-common.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -13,8 +12,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static void init_generic_timer(void) { const u32 freq = CONFIG_SYS_CLK_FREQ; diff --git a/board/ronetix/imx8mq-cm/imx8mq_cm.c b/board/ronetix/imx8mq-cm/imx8mq_cm.c index 602216854ba..e41cfefe375 100644 --- a/board/ronetix/imx8mq-cm/imx8mq_cm.c +++ b/board/ronetix/imx8mq-cm/imx8mq_cm.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 68edd1ec282..2ba2d6330fd 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -36,8 +35,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int exynos_set_regulator(const char *name, uint uv) { struct udevice *dev; diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index c134a9d70e2..85e564f27ee 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -37,8 +36,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SET_DFU_ALT_INFO void set_dfu_alt_info(char *interface, char *devstr) { diff --git a/board/st/stm32f429-discovery/stm32f429-discovery.c b/board/st/stm32f429-discovery/stm32f429-discovery.c index 4b0defda1ec..333b78c27f3 100644 --- a/board/st/stm32f429-discovery/stm32f429-discovery.c +++ b/board/st/stm32f429-discovery/stm32f429-discovery.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c index 88c825334a8..feba46d38e4 100644 --- a/board/st/stm32f429-evaluation/stm32f429-evaluation.c +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f469-discovery/stm32f469-discovery.c b/board/st/stm32f469-discovery/stm32f469-discovery.c index 7aab7f71d0c..d153efdc2b4 100644 --- a/board/st/stm32f469-discovery/stm32f469-discovery.c +++ b/board/st/stm32f469-discovery/stm32f469-discovery.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { int rv; diff --git a/board/st/stm32f746-disco/stm32f746-disco.c b/board/st/stm32f746-disco/stm32f746-disco.c index 07bc8a5f0a2..4b1e443100d 100644 --- a/board/st/stm32f746-disco/stm32f746-disco.c +++ b/board/st/stm32f746-disco/stm32f746-disco.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int dram_init(void) { #ifndef CONFIG_XPL_BUILD diff --git a/board/st/stm32h743-disco/stm32h743-disco.c b/board/st/stm32h743-disco/stm32h743-disco.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-disco/stm32h743-disco.c +++ b/board/st/stm32h743-disco/stm32h743-disco.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h743-eval/stm32h743-eval.c b/board/st/stm32h743-eval/stm32h743-eval.c index d00f55379c5..6c5c6710926 100644 --- a/board/st/stm32h743-eval/stm32h743-eval.c +++ b/board/st/stm32h743-eval/stm32h743-eval.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h747-disco/stm32h747-disco.c b/board/st/stm32h747-disco/stm32h747-disco.c index 645685a64f1..24a229bf0a2 100644 --- a/board/st/stm32h747-disco/stm32h747-disco.c +++ b/board/st/stm32h747-disco/stm32h747-disco.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/st/stm32h750-art-pi/stm32h750-art-pi.c b/board/st/stm32h750-art-pi/stm32h750-art-pi.c index 31c85c6816e..244bb5eefb3 100644 --- a/board/st/stm32h750-art-pi/stm32h750-art-pi.c +++ b/board/st/stm32h750-art-pi/stm32h750-art-pi.c @@ -7,9 +7,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { diff --git a/board/technexion/pico-imx8mq/pico-imx8mq.c b/board/technexion/pico-imx8mq/pico-imx8mq.c index 1659db112fa..5515fc09f99 100644 --- a/board/technexion/pico-imx8mq/pico-imx8mq.c +++ b/board/technexion/pico-imx8mq/pico-imx8mq.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index 2e8336900d1..49e58ad6d6c 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -32,8 +32,6 @@ #define board_is_am62x_lp_skevm() board_ti_k3_is("AM62-LP-SKEVM") #define board_is_am62x_sip_skevm() board_ti_k3_is("AM62SIP-SKEVM") -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(SPLASH_SCREEN) static struct splash_location default_splash_locations[] = { { diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index 25076a8a588..764e3011bac 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -27,8 +27,6 @@ #define board_is_am64x_skevm() (board_ti_k3_is("AM64-SKEVM") || \ board_ti_k3_is("AM64B-SKEVM")) -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM64X_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index cabb3017ee1..8a4d40a5a95 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -14,8 +14,6 @@ #include #include "../common/fdt_ops.h" -DECLARE_GLOBAL_DATA_PTR; - struct efi_fw_image fw_images[] = { { .image_type_id = AM69_SK_TIBOOT3_IMAGE_GUID, diff --git a/board/toradex/apalis-imx8/apalis-imx8.c b/board/toradex/apalis-imx8/apalis-imx8.c index a8c38208693..b915673d9e3 100644 --- a/board/toradex/apalis-imx8/apalis-imx8.c +++ b/board/toradex/apalis-imx8/apalis-imx8.c @@ -5,7 +5,6 @@ #include #include -#include #include #include @@ -24,8 +23,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 2c785da41ea..8dad41f4122 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include "pinmux-config-apalis_t30.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 diff --git a/board/toradex/colibri-imx8x/colibri-imx8x.c b/board/toradex/colibri-imx8x/colibri-imx8x.c index 2a71e7b92de..0a86420700d 100644 --- a/board/toradex/colibri-imx8x/colibri-imx8x.c +++ b/board/toradex/colibri-imx8x/colibri-imx8x.c @@ -5,7 +5,6 @@ #include #include -#include #include #include @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \ diff --git a/board/toradex/colibri_t20/colibri_t20.c b/board/toradex/colibri_t20/colibri_t20.c index 05c3377a60b..ccfe2c4933c 100644 --- a/board/toradex/colibri_t20/colibri_t20.c +++ b/board/toradex/colibri_t20/colibri_t20.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include "../common/tdx-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PMU_I2C_ADDRESS 0x34 #define MAX_I2C_RETRY 3 #define PMU_SUPPLYENE 0x14 diff --git a/board/toradex/common/tdx-cfg-block.c b/board/toradex/common/tdx-cfg-block.c index 0fc3759695f..e53530175ae 100644 --- a/board/toradex/common/tdx-cfg-block.c +++ b/board/toradex/common/tdx-cfg-block.c @@ -4,7 +4,6 @@ */ #include -#include #include "tdx-cfg-block.h" #include "tdx-eeprom.h" @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define TAG_VALID 0xcf01 #define TAG_MAC 0x0000 #define TAG_CAR_SERIAL 0x0021 diff --git a/board/toradex/smarc-imx8mp/smarc-imx8mp.c b/board/toradex/smarc-imx8mp/smarc-imx8mp.c index 915b413b15e..38fb3d61f5b 100644 --- a/board/toradex/smarc-imx8mp/smarc-imx8mp.c +++ b/board/toradex/smarc-imx8mp/smarc-imx8mp.c @@ -2,14 +2,11 @@ /* Copyright (C) 2024 Toradex */ #include -#include #include #include #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - int board_phys_sdram_size(phys_size_t *size) { if (!size) diff --git a/board/toradex/smarc-imx8mp/spl.c b/board/toradex/smarc-imx8mp/spl.c index 32233c0e1ab..511f62e871b 100644 --- a/board/toradex/smarc-imx8mp/spl.c +++ b/board/toradex/smarc-imx8mp/spl.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/toradex/verdin-imx8mm/spl.c b/board/toradex/verdin-imx8mm/spl.c index 3c2d0ba1dd4..10b9991e3bf 100644 --- a/board/toradex/verdin-imx8mm/spl.c +++ b/board/toradex/verdin-imx8mm/spl.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -27,8 +26,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC_BUS_ID 1 int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/toradex/verdin-imx8mm/verdin-imx8mm.c b/board/toradex/verdin-imx8mm/verdin-imx8mm.c index b4402415845..b56f5bf30a8 100644 --- a/board/toradex/verdin-imx8mm/verdin-imx8mm.c +++ b/board/toradex/verdin-imx8mm/verdin-imx8mm.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define I2C_PMIC 0 enum pcb_rev_t { diff --git a/board/toradex/verdin-imx8mp/spl.c b/board/toradex/verdin-imx8mp/spl.c index 8628112a782..b39058b1b5d 100644 --- a/board/toradex/verdin-imx8mp/spl.c +++ b/board/toradex/verdin-imx8mp/spl.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include "lpddr4_timing.h" -DECLARE_GLOBAL_DATA_PTR; - int spl_board_boot_device(enum boot_device boot_dev_spl) { return BOOT_DEVICE_BOOTROM; diff --git a/board/toradex/verdin-imx8mp/verdin-imx8mp.c b/board/toradex/verdin-imx8mp/verdin-imx8mp.c index 34ce25512e8..59b4607f065 100644 --- a/board/toradex/verdin-imx8mp/verdin-imx8mp.c +++ b/board/toradex/verdin-imx8mp/verdin-imx8mp.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include "../common/tdx-cfg-block.h" -DECLARE_GLOBAL_DATA_PTR; - #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) /* Verdin UART_3, Console/Debug UART */ diff --git a/board/xilinx/zynq/bootimg.c b/board/xilinx/zynq/bootimg.c index 9eb0735f55d..52400672799 100644 --- a/board/xilinx/zynq/bootimg.c +++ b/board/xilinx/zynq/bootimg.c @@ -5,15 +5,12 @@ #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define ZYNQ_IMAGE_PHDR_OFFSET 0x09C #define ZYNQ_IMAGE_FSBL_LEN_OFFSET 0x040 #define ZYNQ_PART_HDR_CHKSUM_WORD_COUNT 0x0F diff --git a/boot/bootmeth-uclass.c b/boot/bootmeth-uclass.c index a9709465f6e..c841dd0d6d4 100644 --- a/boot/bootmeth-uclass.c +++ b/boot/bootmeth-uclass.c @@ -19,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int bootmeth_get_state_desc(struct udevice *dev, char *buf, int maxsize) { const struct bootmeth_ops *ops = bootmeth_get_ops(dev); diff --git a/boot/fdt_simplefb.c b/boot/fdt_simplefb.c index 5822131767d..69c7c2e24c0 100644 --- a/boot/fdt_simplefb.c +++ b/boot/fdt_simplefb.c @@ -8,14 +8,11 @@ #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int fdt_simplefb_configure_node(void *blob, int off) { int xsize, ysize; diff --git a/boot/image-sig.c b/boot/image-sig.c index 6bc74866eae..4eab017bc2d 100644 --- a/boot/image-sig.c +++ b/boot/image-sig.c @@ -5,8 +5,6 @@ #include #include -#include -DECLARE_GLOBAL_DATA_PTR; #include #include #include diff --git a/boot/image.c b/boot/image.c index dd96f712b6f..3f745254763 100644 --- a/boot/image.c +++ b/boot/image.c @@ -24,12 +24,9 @@ #include #endif -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Set this if we have less than 4 MB of malloc() space */ #if CONFIG_SYS_MALLOC_LEN < (4096 * 1024) #define CONSERVE_MEMORY true diff --git a/cmd/bloblist.c b/cmd/bloblist.c index 333ae558142..318a1af0220 100644 --- a/cmd/bloblist.c +++ b/cmd/bloblist.c @@ -8,9 +8,6 @@ #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int do_bloblist_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/cmd/bootefi.c b/cmd/bootefi.c index b8f5bb35950..85f41c3b0a0 100644 --- a/cmd/bootefi.c +++ b/cmd/bootefi.c @@ -17,11 +17,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct efi_device_path *test_image_path; static struct efi_device_path *test_device_path; diff --git a/cmd/bootm.c b/cmd/bootm.c index 2c5aea26d98..ca7cec91fad 100644 --- a/cmd/bootm.c +++ b/cmd/bootm.c @@ -15,14 +15,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #if defined(CONFIG_CMD_IMI) static int image_info(unsigned long addr); #endif diff --git a/cmd/date.c b/cmd/date.c index 8614f022761..d047872289c 100644 --- a/cmd/date.c +++ b/cmd/date.c @@ -11,9 +11,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const char * const weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", diff --git a/cmd/mem.c b/cmd/mem.c index 8690fc1e4e6..68eb6989b94 100644 --- a/cmd/mem.c +++ b/cmd/mem.c @@ -28,15 +28,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Create a compile-time value */ #if MEM_SUPPORT_64BIT_DATA #define HELP_Q ", .q" diff --git a/cmd/sound.c b/cmd/sound.c index 8f67cbd96e1..7546059022f 100644 --- a/cmd/sound.c +++ b/cmd/sound.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; /* Initilaise sound subsystem */ static int do_init(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/spl.c b/cmd/spl.c index f591dc07fb6..ddbbd4a8172 100644 --- a/cmd/spl.c +++ b/cmd/spl.c @@ -9,11 +9,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static const char **subcmd_list[] = { [SPL_EXPORT_FDT] = (const char * []) { diff --git a/common/cli_hush.c b/common/cli_hush.c index fb087960c92..fe8fe93bd54 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -84,7 +84,6 @@ #include #include /* find_cmd */ #include -#include #endif #ifndef __U_BOOT__ #include /* isalpha, isdigit */ @@ -125,8 +124,6 @@ #endif #ifdef __U_BOOT__ -DECLARE_GLOBAL_DATA_PTR; - #define EXIT_SUCCESS 0 #define EOF -1 #define syntax() syntax_err() diff --git a/common/stdio.c b/common/stdio.c index 3eeb289dd8b..fc965944209 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -18,11 +18,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static struct stdio_dev devs; struct stdio_dev *stdio_devices[] = { NULL, NULL, NULL }; char *stdio_names[MAX_FILES] = { "stdin", "stdout", "stderr" }; diff --git a/drivers/block/sandbox.c b/drivers/block/sandbox.c index 9cb27561a97..4b3de0529ce 100644 --- a/drivers/block/sandbox.c +++ b/drivers/block/sandbox.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static unsigned long host_block_read(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *buffer) diff --git a/drivers/bootcount/pmic_pfuze100.c b/drivers/bootcount/pmic_pfuze100.c index 8c529f5592b..dd11344322b 100644 --- a/drivers/bootcount/pmic_pfuze100.c +++ b/drivers/bootcount/pmic_pfuze100.c @@ -13,8 +13,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define PFUZE_BC_MAGIC 0xdead struct bootcount_pmic_priv { diff --git a/drivers/cache/sandbox_cache.c b/drivers/cache/sandbox_cache.c index 375892fafb0..b27960f1bfa 100644 --- a/drivers/cache/sandbox_cache.c +++ b/drivers/cache/sandbox_cache.c @@ -6,9 +6,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int sandbox_get_info(struct udevice *dev, struct cache_info *info) { diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index fdbf834bb2f..9d49561512b 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; int pllgrp; diff --git a/drivers/clk/altera/clk-agilex5.c b/drivers/clk/altera/clk-agilex5.c index fb1e72ffc5c..92b91a9dfc8 100644 --- a/drivers/clk/altera/clk-agilex5.c +++ b/drivers/clk/altera/clk-agilex5.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define CLKMGR_CTRL_SWCTRLBTCLKEN_MASK BIT(8) #define CLKMGR_CTRL_SWCTRLBTCLKSEL_MASK BIT(9) diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c index b75f52d203b..ac59571a853 100644 --- a/drivers/clk/altera/clk-mem-n5x.c +++ b/drivers/clk/altera/clk-mem-n5x.c @@ -4,7 +4,6 @@ */ #include -#include #include #include "clk-mem-n5x.h" #include @@ -13,8 +12,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_mem_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c index 9e4e7a1d908..185c9028a78 100644 --- a/drivers/clk/altera/clk-n5x.c +++ b/drivers/clk/altera/clk-n5x.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -12,8 +11,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct socfpga_clk_plat { void __iomem *regs; }; diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c index b5054e84c32..d143a6b85ee 100644 --- a/drivers/clk/rockchip/clk_px30.c +++ b/drivers/clk/rockchip/clk_px30.c @@ -13,15 +13,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c index e73bb6790af..97043b8693c 100644 --- a/drivers/clk/rockchip/clk_rk3308.c +++ b/drivers/clk/rockchip/clk_rk3308.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 3200U * 1000000, VCO_MIN_HZ = 800 * 1000000, diff --git a/drivers/clk/rockchip/clk_rk3528.c b/drivers/clk/rockchip/clk_rk3528.c index d58557ff56d..bcdc0f930d2 100644 --- a/drivers/clk/rockchip/clk_rk3528.c +++ b/drivers/clk/rockchip/clk_rk3528.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) /* diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 533031caead..bb49af358e6 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -16,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #if CONFIG_IS_ENABLED(OF_PLATDATA) struct rk3568_clk_plat { struct dtd_rockchip_rk3568_cru dtd; diff --git a/drivers/clk/rockchip/clk_rk3576.c b/drivers/clk/rockchip/clk_rk3576.c index 125b08ee832..1026af27ca1 100644 --- a/drivers/clk/rockchip/clk_rk3576.c +++ b/drivers/clk/rockchip/clk_rk3576.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3576_24m_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rk3588.c b/drivers/clk/rockchip/clk_rk3588.c index 8c3a113526f..be401a9faee 100644 --- a/drivers/clk/rockchip/clk_rk3588.c +++ b/drivers/clk/rockchip/clk_rk3588.c @@ -17,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) static struct rockchip_pll_rate_table rk3588_pll_rates[] = { diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 75202a66aa6..e1b9ccf1236 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { VCO_MAX_HZ = 2400U * 1000000, VCO_MIN_HZ = 600 * 1000000, diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c index aeeea956914..39920d34b75 100644 --- a/drivers/clk/rockchip/clk_rv1126.c +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ { \ .rate = _rate##U, \ diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index 59a7b142c95..ad638cd8fff 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include "armv8_cpu.h" -DECLARE_GLOBAL_DATA_PTR; - struct bcm_plat { u64 release_addr; }; diff --git a/drivers/cpu/cpu-uclass.c b/drivers/cpu/cpu-uclass.c index 2c8e46c05e3..b73768de918 100644 --- a/drivers/cpu/cpu-uclass.c +++ b/drivers/cpu/cpu-uclass.c @@ -15,8 +15,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int cpu_probe_all(void) { int ret = uclass_probe_all(UCLASS_CPU); diff --git a/drivers/cpu/imx8_cpu.c b/drivers/cpu/imx8_cpu.c index 5f17122c36c..3cd00199548 100644 --- a/drivers/cpu/imx8_cpu.c +++ b/drivers/cpu/imx8_cpu.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define IMX_REV_LEN 4 struct cpu_imx_plat { const char *name; diff --git a/drivers/cpu/mtk_cpu.c b/drivers/cpu/mtk_cpu.c index 2a08be9b6d1..4f4e5480eac 100644 --- a/drivers/cpu/mtk_cpu.c +++ b/drivers/cpu/mtk_cpu.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct mtk_cpu_plat { struct regmap *hwver; }; diff --git a/drivers/firmware/arm-ffa/arm-ffa-uclass.c b/drivers/firmware/arm-ffa/arm-ffa-uclass.c index 96c64964bb7..76a8775e911 100644 --- a/drivers/firmware/arm-ffa/arm-ffa-uclass.c +++ b/drivers/firmware/arm-ffa/arm-ffa-uclass.c @@ -12,15 +12,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Error mapping declarations */ int ffa_to_std_errmap[MAX_NUMBER_FFA_ERR] = { diff --git a/drivers/firmware/arm-ffa/arm-ffa.c b/drivers/firmware/arm-ffa/arm-ffa.c index 94e6105cb38..9e6b5dcc542 100644 --- a/drivers/firmware/arm-ffa/arm-ffa.c +++ b/drivers/firmware/arm-ffa/arm-ffa.c @@ -10,12 +10,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * invoke_ffa_fn() - SMC wrapper * @args: FF-A ABI arguments to be copied to Xn registers diff --git a/drivers/firmware/arm-ffa/ffa-emul-uclass.c b/drivers/firmware/arm-ffa/ffa-emul-uclass.c index 1521d9b66ac..6198d687354 100644 --- a/drivers/firmware/arm-ffa/ffa-emul-uclass.c +++ b/drivers/firmware/arm-ffa/ffa-emul-uclass.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* The partitions (SPs) table */ static struct ffa_partition_desc sandbox_partitions[SANDBOX_PARTITIONS_CNT] = { { diff --git a/drivers/firmware/arm-ffa/sandbox_ffa.c b/drivers/firmware/arm-ffa/sandbox_ffa.c index 44b32a829dd..f1e8de4bf0d 100644 --- a/drivers/firmware/arm-ffa/sandbox_ffa.c +++ b/drivers/firmware/arm-ffa/sandbox_ffa.c @@ -8,13 +8,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * sandbox_ffa_discover() - perform sandbox FF-A discovery * @dev: The sandbox FF-A bus device diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 38151ef1bee..7651d5360d6 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -18,15 +18,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPIO_ALLOC_BITS 32 /** diff --git a/drivers/gpio/nx_gpio.c b/drivers/gpio/nx_gpio.c index 741b2ff7f17..5abbb34daea 100644 --- a/drivers/gpio/nx_gpio.c +++ b/drivers/gpio/nx_gpio.c @@ -7,12 +7,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct nx_gpio_regs { u32 data; /* Data register */ u32 outputenb; /* Output Enable register */ diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c index 2dfc1c4eab5..268bb39f009 100644 --- a/drivers/i2c/mxc_i2c.c +++ b/drivers/i2c/mxc_i2c.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define I2C_QUIRK_FLAG (1 << 0) #define IMX_I2C_REGSHIFT 2 diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 8562dd82bd6..706b7adefe8 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #define I2C_WRITE 0 @@ -45,8 +44,6 @@ #define DEFAULT_SPEED 100000 /* default I2C speed [Hz] */ -DECLARE_GLOBAL_DATA_PTR; - struct nx_i2c_regs { uint iiccon; uint iicstat; diff --git a/drivers/i2c/ocores_i2c.c b/drivers/i2c/ocores_i2c.c index cf714d22ee4..32704ee8854 100644 --- a/drivers/i2c/ocores_i2c.c +++ b/drivers/i2c/ocores_i2c.c @@ -12,7 +12,6 @@ * Andreas Larsson */ -#include #include #include #include @@ -75,8 +74,6 @@ struct ocores_i2c_bus { u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg); }; -DECLARE_GLOBAL_DATA_PTR; - /* Boolean attribute values */ enum { FALSE = 0, diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 79f7a320502..4102375e5b7 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -25,7 +25,6 @@ #endif #endif #include -#include #include #if defined(CONFIG_SOFT_I2C_GPIO_SCL) @@ -82,8 +81,6 @@ /* #define DEBUG_I2C */ -DECLARE_GLOBAL_DATA_PTR; - #ifndef I2C_SOFT_DECLARATIONS # define I2C_SOFT_DECLARATIONS #endif diff --git a/drivers/i2c/synquacer_i2c.c b/drivers/i2c/synquacer_i2c.c index 6672d9435e3..6e5722327c5 100644 --- a/drivers/i2c/synquacer_i2c.c +++ b/drivers/i2c/synquacer_i2c.c @@ -112,8 +112,6 @@ #define SPEED_FM 400 // Fast Mode #define SPEED_SM 100 // Standard Mode -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_i2c { void __iomem *base; unsigned long pclkrate; diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c index b1e0465e7a8..c7eaa3de96f 100644 --- a/drivers/mailbox/imx-mailbox.c +++ b/drivers/mailbox/imx-mailbox.c @@ -15,8 +15,6 @@ /* This driver only exposes the status bits to keep with the * polling methodology of u-boot. */ -DECLARE_GLOBAL_DATA_PTR; - #define IMX_MU_CHANS 24 #define IMX_MU_V2_PAR_OFF 0x4 diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c index 3b9046da880..aa3094fcc01 100644 --- a/drivers/misc/atsha204a-i2c.c +++ b/drivers/misc/atsha204a-i2c.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #define ATSHA204A_TRANSACTION_RETRY 5 #define ATSHA204A_EXECTIME 5000 -DECLARE_GLOBAL_DATA_PTR; - static inline u16 atsha204a_crc16(const u8 *buffer, size_t len) { return bitrev16(crc16(0, buffer, len)); diff --git a/drivers/misc/fs_loader.c b/drivers/misc/fs_loader.c index 2928cf75f89..6af4c7f15e7 100644 --- a/drivers/misc/fs_loader.c +++ b/drivers/misc/fs_loader.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -25,8 +24,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - /** * struct firmware - A place for storing firmware and its attribute data. * diff --git a/drivers/misc/imx8/fuse.c b/drivers/misc/imx8/fuse.c index 90d251a4405..872713e30b6 100644 --- a/drivers/misc/imx8/fuse.c +++ b/drivers/misc/imx8/fuse.c @@ -8,11 +8,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - #define FSL_ECC_WORD_START_1 0x10 #define FSL_ECC_WORD_END_1 0x10F diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index 1af5ec0532e..d5a4453a62e 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #define MIN_FREQ (400000) -DECLARE_GLOBAL_DATA_PTR; - struct ca_mmc_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mmc/f_sdh30.c b/drivers/mmc/f_sdh30.c index f47cf848521..f0356e1e960 100644 --- a/drivers/mmc/f_sdh30.c +++ b/drivers/mmc/f_sdh30.c @@ -29,8 +29,6 @@ struct f_sdh30_plat { const struct f_sdh30_data *data; }; -DECLARE_GLOBAL_DATA_PTR; - static void f_sdh30_e51_init(struct udevice *dev) { struct f_sdh30_plat *plat = dev_get_plat(dev); diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c index fc10bb256a4..651d9868305 100644 --- a/drivers/mmc/jz_mmc.c +++ b/drivers/mmc/jz_mmc.c @@ -8,7 +8,6 @@ #include #include -#include #include #include #include @@ -419,8 +418,6 @@ int jz_mmc_init(void __iomem *base) #else /* CONFIG_DM_MMC */ #include -DECLARE_GLOBAL_DATA_PTR; - static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data) { diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index 38dc36a2194..66f3cf2de4f 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -61,8 +60,6 @@ struct msm_sdhc_variant_info { u32 core_vendor_spec_capabilities0; }; -DECLARE_GLOBAL_DATA_PTR; - static int msm_sdc_clk_init(struct udevice *dev) { struct msm_sdhc *prv = dev_get_priv(dev); diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c index 2da5334c21f..a8b63a20387 100644 --- a/drivers/mmc/mv_sdhci.c +++ b/drivers/mmc/mv_sdhci.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #define MVSDH_NAME "mv_sdh" @@ -14,8 +13,6 @@ #define SDHCI_WINDOW_CTRL(win) (0x4080 + ((win) << 4)) #define SDHCI_WINDOW_BASE(win) (0x4084 + ((win) << 4)) -DECLARE_GLOBAL_DATA_PTR; - struct mv_sdhci_plat { struct mmc_config cfg; struct mmc mmc; diff --git a/drivers/mtd/nand/raw/pxa3xx_nand.c b/drivers/mtd/nand/raw/pxa3xx_nand.c index 7bf54fa4654..7324dc72e0a 100644 --- a/drivers/mtd/nand/raw/pxa3xx_nand.c +++ b/drivers/mtd/nand/raw/pxa3xx_nand.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -30,8 +29,6 @@ #include "pxa3xx_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define TIMEOUT_DRAIN_FIFO 5 /* in ms */ #define CHIP_DELAY_TIMEOUT 200 #define NAND_STOP_DELAY 40 diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c index ef43dcad079..0bee7eace90 100644 --- a/drivers/mtd/nand/raw/tegra_nand.c +++ b/drivers/mtd/nand/raw/tegra_nand.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include "tegra_nand.h" -DECLARE_GLOBAL_DATA_PTR; - #define NAND_CMD_TIMEOUT_MS 10 #define SKIPPED_SPARE_BYTES 4 diff --git a/drivers/mtd/nvmxip/nvmxip_qspi.c b/drivers/mtd/nvmxip/nvmxip_qspi.c index 1a109bee557..383971bea66 100644 --- a/drivers/mtd/nvmxip/nvmxip_qspi.c +++ b/drivers/mtd/nvmxip/nvmxip_qspi.c @@ -11,9 +11,6 @@ #include #include -#include -DECLARE_GLOBAL_DATA_PTR; - #define NVMXIP_QSPI_DRV_NAME "nvmxip_qspi" /** diff --git a/drivers/mtd/spi/sf-uclass.c b/drivers/mtd/spi/sf-uclass.c index 102a9236826..a9db5296b2d 100644 --- a/drivers/mtd/spi/sf-uclass.c +++ b/drivers/mtd/spi/sf-uclass.c @@ -11,13 +11,10 @@ #include #include #include -#include #include #include #include "sf_internal.h" -DECLARE_GLOBAL_DATA_PTR; - int spi_flash_read_dm(struct udevice *dev, u32 offset, size_t len, void *buf) { return log_ret(sf_get_ops(dev)->read(dev, offset, len, buf)); diff --git a/drivers/net/dwmac_s700.c b/drivers/net/dwmac_s700.c index 969d247b4f3..76daab961c0 100644 --- a/drivers/net/dwmac_s700.c +++ b/drivers/net/dwmac_s700.c @@ -5,7 +5,6 @@ * Actions DWMAC specific glue layer */ -#include #include #include #include @@ -24,8 +23,6 @@ #define RMII_REF_CLK_MFP_CTL0 (0x0 << 6) #define CLKO_25M_EN_MFP_CTL3 BIT(30) -DECLARE_GLOBAL_DATA_PTR; - static void dwmac_board_setup(void) { clrbits_le32(MFP_CTL0, (RMII_TXD01_MFP_CTL0 | RMII_RXD01_MFP_CTL0 | diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 1c51e936b5b..3d32bad0831 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -18,7 +18,6 @@ #include #include #include -#include #include #include @@ -36,8 +35,6 @@ #include "fec_mxc.h" #include -DECLARE_GLOBAL_DATA_PTR; - /* * Timeout the transfer after 5 mS. This is usually a bit more, since * the code in the tightloops this timeout is used in adds some overhead. diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index c8cfe7448d4..2b6080dd9ee 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -28,7 +27,6 @@ #include #include "designware.h" -DECLARE_GLOBAL_DATA_PTR; #define DELAY_ENABLE(soc, tx, rx) \ (((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \ ((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : soc##_RXCLK_DLY_ENA_GMAC_DISABLE)) diff --git a/drivers/net/mvneta.c b/drivers/net/mvneta.c index 1640868c24a..baa18202d6e 100644 --- a/drivers/net/mvneta.c +++ b/drivers/net/mvneta.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -37,8 +36,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MVNETA_NR_CPUS 1 #define ETH_HLEN 14 /* Total octets in header */ diff --git a/drivers/net/octeontx/smi.c b/drivers/net/octeontx/smi.c index 217bcac2ce2..5a822b64427 100644 --- a/drivers/net/octeontx/smi.c +++ b/drivers/net/octeontx/smi.c @@ -10,15 +10,12 @@ #include #include #include -#include #include #include #include #define PCI_DEVICE_ID_OCTEONTX_SMI 0xA02B -DECLARE_GLOBAL_DATA_PTR; - enum octeontx_smi_mode { CLAUSE22 = 0, CLAUSE45 = 1, diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c index 11d36164976..4ab709a14d5 100644 --- a/drivers/net/phy/fixed.c +++ b/drivers/net/phy/fixed.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int fixedphy_probe(struct phy_device *phydev) { diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index b58283fe3d5..d7e0c4fe02d 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -26,8 +25,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Generic PHY support and helper functions */ /** diff --git a/drivers/net/phy/xilinx_gmii2rgmii.c b/drivers/net/phy/xilinx_gmii2rgmii.c index e44b7b75bd5..f5a7dd349c9 100644 --- a/drivers/net/phy/xilinx_gmii2rgmii.c +++ b/drivers/net/phy/xilinx_gmii2rgmii.c @@ -8,9 +8,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GMII2RGMII_REG 0x10 #define ZYNQ_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100) diff --git a/drivers/net/sandbox-raw.c b/drivers/net/sandbox-raw.c index 1d716716778..c3d40f0b59e 100644 --- a/drivers/net/sandbox-raw.c +++ b/drivers/net/sandbox-raw.c @@ -12,9 +12,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static int reply_arp; static struct in_addr arp_ip; diff --git a/drivers/net/sandbox.c b/drivers/net/sandbox.c index 2011fd31f41..0ea50c484c0 100644 --- a/drivers/net/sandbox.c +++ b/drivers/net/sandbox.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include @@ -84,8 +83,6 @@ struct icmphdr { #define ICMP_ECHO_REPLY 0 #define IPPROTO_ICMP 1 -DECLARE_GLOBAL_DATA_PTR; - static const u8 null_ethaddr[6]; static bool skip_timeout; diff --git a/drivers/net/ti/keystone_net.c b/drivers/net/ti/keystone_net.c index d4abc9a0411..40c98e72e4d 100644 --- a/drivers/net/ti/keystone_net.c +++ b/drivers/net/ti/keystone_net.c @@ -7,7 +7,6 @@ */ #include #include -#include #include #include @@ -26,8 +25,6 @@ #include "cpsw_mdio.h" -DECLARE_GLOBAL_DATA_PTR; - #ifdef KEYSTONE2_EMAC_GIG_ENABLE #define emac_gigabit_enable(x) keystone2_eth_gigabit_enable(x) #else diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c index fb48feb4469..e9cc5db52d2 100644 --- a/drivers/net/xilinx_axi_emac.c +++ b/drivers/net/xilinx_axi_emac.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Link setup */ #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */ #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */ diff --git a/drivers/pci/pci_octeontx.c b/drivers/pci/pci_octeontx.c index 875cf7f7115..6752112a878 100644 --- a/drivers/pci/pci_octeontx.c +++ b/drivers/pci/pci_octeontx.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * This driver supports multiple types of operations / host bridges / busses: * diff --git a/drivers/pci/pcie_dw_meson.c b/drivers/pci/pcie_dw_meson.c index 483b07ce078..1eff6d1b0ed 100644 --- a/drivers/pci/pcie_dw_meson.c +++ b/drivers/pci/pcie_dw_meson.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -27,8 +26,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct meson_pcie - Amlogic Meson DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_qcom.c b/drivers/pci/pcie_dw_qcom.c index 978754e8472..10c45aaba20 100644 --- a/drivers/pci/pcie_dw_qcom.c +++ b/drivers/pci/pcie_dw_qcom.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - struct qcom_pcie; struct qcom_pcie_ops { diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 208aa30463a..61117fa95e6 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -24,8 +23,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_pcie - RK DW PCIe controller state * diff --git a/drivers/pci/pcie_dw_ti.c b/drivers/pci/pcie_dw_ti.c index dc6e65273b7..37c295fdd38 100644 --- a/drivers/pci/pcie_dw_ti.c +++ b/drivers/pci/pcie_dw_ti.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include "pcie_dw_common.h" -DECLARE_GLOBAL_DATA_PTR; - #define PCIE_VENDORID_MASK GENMASK(15, 0) #define PCIE_DEVICEID_SHIFT 16 diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c index 1be33095b9c..db7c4f47916 100644 --- a/drivers/pci/pcie_layerscape.c +++ b/drivers/pci/pcie_layerscape.c @@ -6,7 +6,6 @@ */ #include -#include #include #include #include @@ -16,8 +15,6 @@ #endif #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - LIST_HEAD(ls_pcie_list); unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) diff --git a/drivers/pci/pcie_starfive_jh7110.c b/drivers/pci/pcie_starfive_jh7110.c index 0908ae16b67..761e64be58a 100644 --- a/drivers/pci/pcie_starfive_jh7110.c +++ b/drivers/pci/pcie_starfive_jh7110.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -39,8 +38,6 @@ #define STG_SYSCON_RP_NEP_OFFSET 0xe8 #define STG_SYSCON_K_RP_NEP_MASK BIT(8) -DECLARE_GLOBAL_DATA_PTR; - struct starfive_pcie { struct pcie_plda plda; struct clk_bulk clks; diff --git a/drivers/pci_endpoint/pci_ep-uclass.c b/drivers/pci_endpoint/pci_ep-uclass.c index 902d1a51eaa..b71defe4019 100644 --- a/drivers/pci_endpoint/pci_ep-uclass.c +++ b/drivers/pci_endpoint/pci_ep-uclass.c @@ -13,12 +13,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr) { struct pci_ep_ops *ops = pci_ep_get_ops(dev); diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index a4121423873..b074d58f9f6 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #define COMPHY_MAX_CHIP 4 -DECLARE_GLOBAL_DATA_PTR; - static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { diff --git a/drivers/phy/omap-usb2-phy.c b/drivers/phy/omap-usb2-phy.c index 2be0178882a..6df4ff4eb05 100644 --- a/drivers/phy/omap-usb2-phy.c +++ b/drivers/phy/omap-usb2-phy.c @@ -6,7 +6,6 @@ * Written by Jean-Jacques Hiblot */ -#include #include #include #include @@ -39,8 +38,6 @@ #define USB2PHY_USE_CHG_DET_REG BIT(29) #define USB2PHY_DIS_CHG_DET BIT(28) -DECLARE_GLOBAL_DATA_PTR; - struct omap_usb2_phy { struct regmap *pwr_regmap; ulong flags; diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c index 660037034ec..5775101c4cb 100644 --- a/drivers/phy/rockchip/phy-rockchip-pcie.c +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c @@ -9,7 +9,6 @@ #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * The higher 16-bit of this register is used for write protection * only if BIT(x + 16) set to 1 the BIT(x) can be written. diff --git a/drivers/phy/rockchip/phy-rockchip-typec.c b/drivers/phy/rockchip/phy-rockchip-typec.c index 66d1d32d25c..305d5b0dd48 100644 --- a/drivers/phy/rockchip/phy-rockchip-typec.c +++ b/drivers/phy/rockchip/phy-rockchip-typec.c @@ -10,7 +10,6 @@ #include #include -#include #include #include #include @@ -21,8 +20,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define usleep_range(a, b) udelay((b)) #define CMN_SSM_BANDGAP (0x21 << 2) diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7628.c b/drivers/pinctrl/mtmips/pinctrl-mt7628.c index dc7acec4a77..be3a28eb94d 100644 --- a/drivers/pinctrl/mtmips/pinctrl-mt7628.c +++ b/drivers/pinctrl/mtmips/pinctrl-mt7628.c @@ -6,15 +6,12 @@ */ #include -#include #include #include #include #include "pinctrl-mtmips-common.h" -DECLARE_GLOBAL_DATA_PTR; - #define AGPIO_OFS 0 #define GPIOMODE1_OFS 0x24 #define GPIOMODE2_OFS 0x28 diff --git a/drivers/pinctrl/nexell/pinctrl-nexell.c b/drivers/pinctrl/nexell/pinctrl-nexell.c index d5be7baf50d..af1acd91649 100644 --- a/drivers/pinctrl/nexell/pinctrl-nexell.c +++ b/drivers/pinctrl/nexell/pinctrl-nexell.c @@ -7,13 +7,10 @@ #include #include -#include #include #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - /* given a pin-name, return the address of pin config registers */ unsigned long pin_to_bank_base(struct udevice *dev, const char *pin_name, u32 *pin) diff --git a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c index a6ae5764fbc..aeed3f1e1e1 100644 --- a/drivers/pinctrl/nexell/pinctrl-s5pxx18.c +++ b/drivers/pinctrl/nexell/pinctrl-s5pxx18.c @@ -9,15 +9,12 @@ #include #include -#include #include #include #include #include "pinctrl-nexell.h" #include "pinctrl-s5pxx18.h" -DECLARE_GLOBAL_DATA_PTR; - static void nx_gpio_set_bit(u32 *value, u32 bit, int enable) { register u32 newvalue; diff --git a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c index 2f4228a9fc5..7cdbbbba747 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-mmio.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-mmio.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_mmio(struct udevice *dev, struct udevice *config) { struct imx_pinctrl_priv *priv = dev_get_priv(dev); diff --git a/drivers/pinctrl/nxp/pinctrl-imx.c b/drivers/pinctrl/nxp/pinctrl-imx.c index 7d91ccfb26f..d8011768581 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx.c +++ b/drivers/pinctrl/nxp/pinctrl-imx.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -16,8 +15,6 @@ #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - int imx_pinctrl_set_state_common(struct udevice *dev, struct udevice *config, int pin_size, u32 **pin_data, int *npins) { diff --git a/drivers/pinctrl/nxp/pinctrl-imx8.c b/drivers/pinctrl/nxp/pinctrl-imx8.c index 9b3b5aec07a..23865ee6428 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx8.c +++ b/drivers/pinctrl/nxp/pinctrl-imx8.c @@ -9,14 +9,11 @@ #include #include #include -#include #include #include #include "pinctrl-imx.h" -DECLARE_GLOBAL_DATA_PTR; - #define PADRING_IFMUX_EN_SHIFT 31 #define PADRING_IFMUX_EN_MASK BIT(31) #define PADRING_GP_EN_SHIFT 30 diff --git a/drivers/pinctrl/nxp/pinctrl-mxs.c b/drivers/pinctrl/nxp/pinctrl-mxs.c index 85ab5fdf640..8b764738014 100644 --- a/drivers/pinctrl/nxp/pinctrl-mxs.c +++ b/drivers/pinctrl/nxp/pinctrl-mxs.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -15,8 +14,6 @@ #include #include "pinctrl-mxs.h" -DECLARE_GLOBAL_DATA_PTR; - struct mxs_pinctrl_priv { void __iomem *base; const struct mxs_regs *regs; diff --git a/drivers/power/domain/imx8m-power-domain.c b/drivers/power/domain/imx8m-power-domain.c index a7e64971a2a..1c731b897cc 100644 --- a/drivers/power/domain/imx8m-power-domain.c +++ b/drivers/power/domain/imx8m-power-domain.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define GPC_PGC_CPU_MAPPING 0x0ec #define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc diff --git a/drivers/power/pmic/bd71837.c b/drivers/power/pmic/bd71837.c index a5df2570fc3..13642794765 100644 --- a/drivers/power/pmic/bd71837.c +++ b/drivers/power/pmic/bd71837.c @@ -7,14 +7,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = BD718XX_REGULATOR_DRIVER}, diff --git a/drivers/power/pmic/mc34708.c b/drivers/power/pmic/mc34708.c index 43badb5767a..0ec52e25a9e 100644 --- a/drivers/power/pmic/mc34708.c +++ b/drivers/power/pmic/mc34708.c @@ -9,11 +9,8 @@ #include #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - static int mc34708_reg_count(struct udevice *dev) { return PMIC_NUM_OF_REGS; diff --git a/drivers/power/pmic/mp5416.c b/drivers/power/pmic/mp5416.c index 9d44f0ae655..899c2beeb37 100644 --- a/drivers/power/pmic/mp5416.c +++ b/drivers/power/pmic/mp5416.c @@ -9,9 +9,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const struct pmic_child_info pmic_children_info[] = { /* buck */ diff --git a/drivers/power/pmic/pca9450.c b/drivers/power/pmic/pca9450.c index e5c1f037b61..c95e6357ee8 100644 --- a/drivers/power/pmic/pca9450.c +++ b/drivers/power/pmic/pca9450.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -18,8 +17,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static const struct pmic_child_info pmic_children_info[] = { /* buck */ { .prefix = "b", .driver = PCA9450_REGULATOR_DRIVER}, diff --git a/drivers/power/regulator/pwm_regulator.c b/drivers/power/regulator/pwm_regulator.c index ff738faadc5..adde5156c76 100644 --- a/drivers/power/regulator/pwm_regulator.c +++ b/drivers/power/regulator/pwm_regulator.c @@ -11,12 +11,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct pwm_regulator_info { /* pwm id corresponding to the PWM driver */ int pwm_id; diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index e9777c71f5e..dea7bc57495 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -40,8 +39,6 @@ #define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0 #define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff -DECLARE_GLOBAL_DATA_PTR; - struct pwm_sifive_regs { unsigned long cfg; unsigned long cnt; diff --git a/drivers/pwm/rk_pwm.c b/drivers/pwm/rk_pwm.c index 0a64eb01dc2..b51dee31a98 100644 --- a/drivers/pwm/rk_pwm.c +++ b/drivers/pwm/rk_pwm.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct rockchip_pwm_data { struct rockchip_pwm_regs regs; unsigned int prescaler; diff --git a/drivers/pwm/sunxi_pwm.c b/drivers/pwm/sunxi_pwm.c index 2140a05b679..1dd2428da77 100644 --- a/drivers/pwm/sunxi_pwm.c +++ b/drivers/pwm/sunxi_pwm.c @@ -9,13 +9,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define OSC_24MHZ 24000000 struct sunxi_pwm_priv { diff --git a/drivers/ram/stm32mp1/stm32mp1_tests.c b/drivers/ram/stm32mp1/stm32mp1_tests.c index 6108faa7073..3b41d6045ad 100644 --- a/drivers/ram/stm32mp1/stm32mp1_tests.c +++ b/drivers/ram/stm32mp1/stm32mp1_tests.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include "stm32mp1_tests.h" @@ -19,8 +18,6 @@ #define PATTERN_DEFAULT "-" -DECLARE_GLOBAL_DATA_PTR; - static int get_bufsize(char *string, int argc, char *argv[], int arg_nb, size_t *bufsize, size_t default_size, size_t min_size) { diff --git a/drivers/reboot-mode/reboot-mode-gpio.c b/drivers/reboot-mode/reboot-mode-gpio.c index 22ee40c3433..8d3e53d50ee 100644 --- a/drivers/reboot-mode/reboot-mode-gpio.c +++ b/drivers/reboot-mode/reboot-mode-gpio.c @@ -10,8 +10,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { int ret; diff --git a/drivers/reboot-mode/reboot-mode-rtc.c b/drivers/reboot-mode/reboot-mode-rtc.c index 4f4ad63febc..adca584d622 100644 --- a/drivers/reboot-mode/reboot-mode-rtc.c +++ b/drivers/reboot-mode/reboot-mode-rtc.c @@ -9,8 +9,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int reboot_mode_get(struct udevice *dev, u32 *buf) { if (!buf) diff --git a/drivers/remoteproc/rproc-uclass.c b/drivers/remoteproc/rproc-uclass.c index 2dbd3a21cea..47cb64fec77 100644 --- a/drivers/remoteproc/rproc-uclass.c +++ b/drivers/remoteproc/rproc-uclass.c @@ -22,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - struct resource_table { u32 ver; u32 num; diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 4f7de3ea215..c885b46cf56 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ diff --git a/drivers/serial/sandbox.c b/drivers/serial/sandbox.c index cc0491bc3c8..658cbd2bbc9 100644 --- a/drivers/serial/sandbox.c +++ b/drivers/serial/sandbox.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static size_t _sandbox_serial_written = 1; static bool sandbox_serial_enabled = true; diff --git a/drivers/serial/serial_adi_uart4.c b/drivers/serial/serial_adi_uart4.c index 45f8315d0a0..784310ba231 100644 --- a/drivers/serial/serial_adi_uart4.c +++ b/drivers/serial/serial_adi_uart4.c @@ -80,8 +80,6 @@ #define ERXS BIT(8) #define ETXS BIT(9) -DECLARE_GLOBAL_DATA_PTR; - struct uart4_reg { u32 revid; u32 control; diff --git a/drivers/serial/serial_htif.c b/drivers/serial/serial_htif.c index 2a93bbbcc9f..690de3fc085 100644 --- a/drivers/serial/serial_htif.c +++ b/drivers/serial/serial_htif.c @@ -8,14 +8,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define HTIF_DATA_BITS 48 #define HTIF_DATA_MASK ((1ULL << HTIF_DATA_BITS) - 1) #define HTIF_DATA_SHIFT 0 diff --git a/drivers/serial/serial_xen.c b/drivers/serial/serial_xen.c index e05805f6372..4ba8d3ee641 100644 --- a/drivers/serial/serial_xen.c +++ b/drivers/serial/serial_xen.c @@ -7,7 +7,6 @@ #include #include #include -#include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - u32 console_evtchn; /* diff --git a/drivers/smem/msm_smem.c b/drivers/smem/msm_smem.c index b6b92d3530d..7a50d5a5792 100644 --- a/drivers/smem/msm_smem.c +++ b/drivers/smem/msm_smem.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -20,8 +19,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * The Qualcomm shared memory system is an allocate-only heap structure that * consists of one of more memory areas that can be accessed by the processors diff --git a/drivers/spi/ca_sflash.c b/drivers/spi/ca_sflash.c index db32e39add2..f00df93a5f5 100644 --- a/drivers/spi/ca_sflash.c +++ b/drivers/spi/ca_sflash.c @@ -21,9 +21,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; struct ca_sflash_regs { u32 idr; /* 0x00:Flash word ID Register */ diff --git a/drivers/spi/microchip_coreqspi.c b/drivers/spi/microchip_coreqspi.c index a84b257fb1a..b3ff611e8f7 100644 --- a/drivers/spi/microchip_coreqspi.c +++ b/drivers/spi/microchip_coreqspi.c @@ -18,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * QSPI Control register mask defines */ diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c index fde9b142fb8..79836d7e271 100644 --- a/drivers/spi/mvebu_a3700_spi.c +++ b/drivers/spi/mvebu_a3700_spi.c @@ -11,14 +11,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define MVEBU_SPI_A3700_XFER_RDY BIT(1) #define MVEBU_SPI_A3700_FIFO_FLUSH BIT(9) #define MVEBU_SPI_A3700_BYTE_LEN BIT(5) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 35bd8766097..b2d115aded4 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -20,13 +20,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct omap2_mcspi_platform_config { unsigned int regs_offset; }; diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c index e00532a371b..0bdc112d249 100644 --- a/drivers/spi/spi-sunxi.c +++ b/drivers/spi/spi-sunxi.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include @@ -35,8 +34,6 @@ #include -DECLARE_GLOBAL_DATA_PTR; - /* sun4i spi registers */ #define SUN4I_RXDATA_REG 0x00 #define SUN4I_TXDATA_REG 0x04 diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index a3c0ad17121..66c97da610b 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -99,8 +99,6 @@ #define TXBIT 1 #define RXBIT 2 -DECLARE_GLOBAL_DATA_PTR; - struct synquacer_spi_plat { void __iomem *base; bool aces, rtm; diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c index 49b584c648d..60401633341 100644 --- a/drivers/spi/spi-uclass.c +++ b/drivers/spi/spi-uclass.c @@ -12,14 +12,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SPI_DEFAULT_SPEED_HZ 100000 static int spi_set_speed_mode(struct udevice *bus, int speed, int mode) diff --git a/drivers/spi/tegra210_qspi.c b/drivers/spi/tegra210_qspi.c index b969a7993d4..0f77fbc8d41 100644 --- a/drivers/spi/tegra210_qspi.c +++ b/drivers/spi/tegra210_qspi.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include "tegra_spi.h" -DECLARE_GLOBAL_DATA_PTR; - /* COMMAND1 */ #define QSPI_CMD1_GO BIT(31) #define QSPI_CMD1_M_S BIT(30) diff --git a/drivers/spmi/spmi-msm.c b/drivers/spmi/spmi-msm.c index f3cd98c3db8..b89dd0b406b 100644 --- a/drivers/spmi/spmi-msm.c +++ b/drivers/spmi/spmi-msm.c @@ -10,13 +10,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* PMIC Arbiter configuration registers */ #define PMIC_ARB_VERSION 0x0000 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 diff --git a/drivers/thermal/imx_tmu.c b/drivers/thermal/imx_tmu.c index c8389d507ee..1bde4d07f52 100644 --- a/drivers/thermal/imx_tmu.c +++ b/drivers/thermal/imx_tmu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SITES_MAX 16 #define FLAGS_VER2 0x1 #define FLAGS_VER3 0x2 diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c index 314f956cdfb..3841d3c90d0 100644 --- a/drivers/timer/ostm_timer.c +++ b/drivers/timer/ostm_timer.c @@ -7,7 +7,6 @@ #include #include -#include #include #include #include @@ -22,8 +21,6 @@ #define OSTM_CTL 0x20 #define OSTM_CTL_D BIT(1) -DECLARE_GLOBAL_DATA_PTR; - struct ostm_priv { fdt_addr_t regs; }; diff --git a/drivers/timer/sp804_timer.c b/drivers/timer/sp804_timer.c index 3e57f4b98ba..05532e3330c 100644 --- a/drivers/timer/sp804_timer.c +++ b/drivers/timer/sp804_timer.c @@ -8,15 +8,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define SP804_TIMERX_LOAD 0x00 #define SP804_TIMERX_VALUE 0x04 #define SP804_TIMERX_CONTROL 0x08 diff --git a/drivers/usb/common/common.c b/drivers/usb/common/common.c index 13e9a61072a..22aa6525c96 100644 --- a/drivers/usb/common/common.c +++ b/drivers/usb/common/common.c @@ -7,14 +7,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static const char *const usb_dr_modes[] = { [USB_DR_MODE_UNKNOWN] = "", [USB_DR_MODE_HOST] = "host", diff --git a/drivers/usb/phy/rockchip_usb2_phy.c b/drivers/usb/phy/rockchip_usb2_phy.c index ce9a7b5b819..bdbd0d44813 100644 --- a/drivers/usb/phy/rockchip_usb2_phy.c +++ b/drivers/usb/phy/rockchip_usb2_phy.c @@ -5,15 +5,12 @@ #include #include -#include #include #include #include #include "../gadget/dwc2_udc_otg_priv.h" -DECLARE_GLOBAL_DATA_PTR; - #define BIT_WRITEABLE_SHIFT 16 struct usb2phy_reg { diff --git a/drivers/usb/tcpm/tcpm.c b/drivers/usb/tcpm/tcpm.c index 0aee57cb2f4..3061b466d7c 100644 --- a/drivers/usb/tcpm/tcpm.c +++ b/drivers/usb/tcpm/tcpm.c @@ -19,8 +19,6 @@ #include #include "tcpm-internal.h" -DECLARE_GLOBAL_DATA_PTR; - const char * const tcpm_states[] = { FOREACH_TCPM_STATE(GENERATE_TCPM_STRING) }; diff --git a/drivers/video/hx8238d.c b/drivers/video/hx8238d.c index f0220e4cc07..b6980b1aec1 100644 --- a/drivers/video/hx8238d.c +++ b/drivers/video/hx8238d.c @@ -16,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Register Address */ #define HX8238D_OUTPUT_CTRL_ADDR 0x01 #define HX8238D_LCD_AC_CTRL_ADDR 0x02 diff --git a/drivers/video/imx/mxc_ipuv3_fb.c b/drivers/video/imx/mxc_ipuv3_fb.c index ab416fdd33c..ef5d4faf3b3 100644 --- a/drivers/video/imx/mxc_ipuv3_fb.c +++ b/drivers/video/imx/mxc_ipuv3_fb.c @@ -21,7 +21,6 @@ #include "ipu_regs.h" #include "mxcfb.h" #include -#include #include #include #include @@ -37,8 +36,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static int mxcfb_map_video_memory(struct fb_info *fbi); static int mxcfb_unmap_video_memory(struct fb_info *fbi); diff --git a/drivers/video/nexell_display.c b/drivers/video/nexell_display.c index ea3776258a0..e0416b70ec0 100644 --- a/drivers/video/nexell_display.c +++ b/drivers/video/nexell_display.c @@ -16,14 +16,11 @@ #include #include #include /* For struct video_uc_plat */ -#include #include #include #include #include "videomodes.h" -DECLARE_GLOBAL_DATA_PTR; - #if !defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL) static struct nx_display_dev *dp_dev; #endif diff --git a/drivers/video/rockchip/rk_lvds.c b/drivers/video/rockchip/rk_lvds.c index c969dae30b6..97c8619a6d8 100644 --- a/drivers/video/rockchip/rk_lvds.c +++ b/drivers/video/rockchip/rk_lvds.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -19,8 +18,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /** * struct rk_lvds_priv - private rockchip lvds display driver info * diff --git a/drivers/video/rockchip/rk_mipi.c b/drivers/video/rockchip/rk_mipi.c index 0a603083ba9..e7b5973ca58 100644 --- a/drivers/video/rockchip/rk_mipi.c +++ b/drivers/video/rockchip/rk_mipi.c @@ -10,7 +10,6 @@ #include #include #include -#include #include "rk_mipi.h" #include #include @@ -22,8 +21,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - int rk_mipi_read_timing(struct udevice *dev, struct display_timing *timing) { diff --git a/drivers/video/sandbox_sdl.c b/drivers/video/sandbox_sdl.c index 69dfa930273..48da350080a 100644 --- a/drivers/video/sandbox_sdl.c +++ b/drivers/video/sandbox_sdl.c @@ -7,15 +7,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - enum { /* Default LCD size we support */ LCD_MAX_WIDTH = 1366, diff --git a/drivers/video/tidss/tidss_drv.c b/drivers/video/tidss/tidss_drv.c index 790ff6e591c..c231fd0341e 100644 --- a/drivers/video/tidss/tidss_drv.c +++ b/drivers/video/tidss/tidss_drv.c @@ -42,8 +42,6 @@ #include "tidss_regs.h" #include "tidss_oldi.h" -DECLARE_GLOBAL_DATA_PTR; - /* Panel parameters */ enum { LCD_MAX_WIDTH = 1920, diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c index a0efd3393f5..fba65bb3d5b 100644 --- a/drivers/video/zynqmp/zynqmp_dpsub.c +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -20,12 +20,9 @@ #include #include #include -#include #include "zynqmp_dpsub.h" -DECLARE_GLOBAL_DATA_PTR; - /* Maximum supported resolution */ #define WIDTH 1024 #define HEIGHT 768 diff --git a/drivers/watchdog/armada-37xx-wdt.c b/drivers/watchdog/armada-37xx-wdt.c index 4b51178e1b8..d7a6b8de492 100644 --- a/drivers/watchdog/armada-37xx-wdt.c +++ b/drivers/watchdog/armada-37xx-wdt.c @@ -7,14 +7,11 @@ #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct a37xx_wdt { void __iomem *sel_reg; void __iomem *reg; diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c index 72e13787448..2fb25126b8c 100644 --- a/drivers/watchdog/at91sam9_wdt.c +++ b/drivers/watchdog/at91sam9_wdt.c @@ -15,7 +15,6 @@ */ #include -#include #include #include #include @@ -23,8 +22,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, * use this to convert a watchdog diff --git a/drivers/watchdog/mt7621_wdt.c b/drivers/watchdog/mt7621_wdt.c index 6308d9632a8..08ef3d84e26 100644 --- a/drivers/watchdog/mt7621_wdt.c +++ b/drivers/watchdog/mt7621_wdt.c @@ -11,12 +11,9 @@ #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct mt762x_wdt { void __iomem *regs; }; diff --git a/drivers/watchdog/orion_wdt.c b/drivers/watchdog/orion_wdt.c index 4562b2a37e3..a2000b968c9 100644 --- a/drivers/watchdog/orion_wdt.c +++ b/drivers/watchdog/orion_wdt.c @@ -16,15 +16,12 @@ #include #include #include -#include #include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct orion_wdt_priv { void __iomem *reg; int wdt_counter_offset; diff --git a/drivers/watchdog/sbsa_gwdt.c b/drivers/watchdog/sbsa_gwdt.c index 03585529bb6..807884c5bc7 100644 --- a/drivers/watchdog/sbsa_gwdt.c +++ b/drivers/watchdog/sbsa_gwdt.c @@ -5,7 +5,6 @@ * Copyright 2020 NXP */ -#include #include #include #include @@ -15,8 +14,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* SBSA Generic Watchdog register definitions */ /* refresh frame */ #define SBSA_GWDT_WRR 0x000 diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c index b32590069d9..438833b2245 100644 --- a/drivers/watchdog/wdt-uclass.c +++ b/drivers/watchdog/wdt-uclass.c @@ -14,13 +14,10 @@ #include #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - #define WATCHDOG_TIMEOUT_SECS (CONFIG_WATCHDOG_TIMEOUT_MSECS / 1000) struct wdt_priv { diff --git a/fs/fs.c b/fs/fs.c index 319c55c440a..8ea50a6c13c 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -24,7 +24,6 @@ #include #include #include -#include #include #include #include @@ -34,8 +33,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - static struct blk_desc *fs_dev_desc; static int fs_dev_part; static struct disk_partition fs_partition; diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 40bad0e7da7..b0cc0d2e1b2 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -16,7 +16,6 @@ #include #include #include -#include #include "ubifs.h" #include #include @@ -31,8 +30,6 @@ #include #endif -DECLARE_GLOBAL_DATA_PTR; - /* compress.c */ /* diff --git a/include/relocate.h b/include/relocate.h index 8ca25e1105e..331be138728 100644 --- a/include/relocate.h +++ b/include/relocate.h @@ -8,9 +8,7 @@ #define _RELOCATE_H_ #ifndef USE_HOSTCC -#include -DECLARE_GLOBAL_DATA_PTR; #endif /** diff --git a/lib/efi_loader/efi_capsule.c b/lib/efi_loader/efi_capsule.c index 89e63ed8dd5..d66ddd1bbf8 100644 --- a/lib/efi_loader/efi_capsule.c +++ b/lib/efi_loader/efi_capsule.c @@ -21,7 +21,6 @@ #include #include #include -#include #include #include @@ -29,8 +28,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - const efi_guid_t efi_guid_capsule_report = EFI_CAPSULE_REPORT_GUID; static const efi_guid_t efi_guid_firmware_management_capsule_id = EFI_FIRMWARE_MANAGEMENT_CAPSULE_ID_GUID; diff --git a/lib/efi_loader/efi_gop.c b/lib/efi_loader/efi_gop.c index 3abb47d610e..9403e09691e 100644 --- a/lib/efi_loader/efi_gop.c +++ b/lib/efi_loader/efi_gop.c @@ -13,9 +13,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; static const efi_guid_t efi_gop_guid = EFI_GRAPHICS_OUTPUT_PROTOCOL_GUID; diff --git a/lib/efi_loader/efi_rng.c b/lib/efi_loader/efi_rng.c index 4734f95eee1..7810b4e47ea 100644 --- a/lib/efi_loader/efi_rng.c +++ b/lib/efi_loader/efi_rng.c @@ -10,9 +10,6 @@ #include #include #include -#include - -DECLARE_GLOBAL_DATA_PTR; const efi_guid_t efi_guid_rng_protocol = EFI_RNG_PROTOCOL_GUID; diff --git a/net/eth-uclass.c b/net/eth-uclass.c index a233912fd8e..5c437143a30 100644 --- a/net/eth-uclass.c +++ b/net/eth-uclass.c @@ -14,15 +14,12 @@ #include #include #include -#include #include #include #include #include "eth_internal.h" #include -DECLARE_GLOBAL_DATA_PTR; - /** * struct eth_device_priv - private structure for each Ethernet device * diff --git a/net/tftp.c b/net/tftp.c index 78ec44159c1..73d6a6a3c1b 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -16,12 +16,9 @@ #include #include #include -#include #include #include "bootp.h" -DECLARE_GLOBAL_DATA_PTR; - /* * We cannot use the 'tftpput' command in xPL phases. Given how the * support is integrated in the code, this is how we disable that support diff --git a/net/wget.c b/net/wget.c index d3642958bf0..49bfb9fcb96 100644 --- a/net/wget.c +++ b/net/wget.c @@ -4,7 +4,6 @@ * Copyright Duncan Hare 2017 */ -#include #include #include #include @@ -17,8 +16,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* The default, change with environment variable 'httpdstp' */ #define SERVER_PORT 80 diff --git a/test/cmd/exit.c b/test/cmd/exit.c index fdde054b928..e20bc5f7b98 100644 --- a/test/cmd/exit.c +++ b/test/cmd/exit.c @@ -7,11 +7,8 @@ #include #include -#include #include -DECLARE_GLOBAL_DATA_PTR; - /* Declare a new exit test */ #define EXIT_TEST(_name, _flags) UNIT_TEST(_name, _flags, exit) diff --git a/test/cmd/test_echo.c b/test/cmd/test_echo.c index 8b306cc907f..7ed534742f7 100644 --- a/test/cmd/test_echo.c +++ b/test/cmd/test_echo.c @@ -6,14 +6,11 @@ */ #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - struct test_data { char *cmd; char *expected; diff --git a/test/cmd/test_pause.c b/test/cmd/test_pause.c index 174c31a3852..b2cf60d3e74 100644 --- a/test/cmd/test_pause.c +++ b/test/cmd/test_pause.c @@ -5,12 +5,9 @@ * Copyright 2022, Samuel Dionne-Riel */ -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int lib_test_hush_pause(struct unit_test_state *uts) { /* Test default message */ diff --git a/test/dm/blk.c b/test/dm/blk.c index 1b928b27d9c..f67869107da 100644 --- a/test/dm/blk.c +++ b/test/dm/blk.c @@ -8,14 +8,11 @@ #include #include #include -#include #include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Test that block devices can be created */ static int dm_test_blk_base(struct unit_test_state *uts) { diff --git a/test/dm/i3c.c b/test/dm/i3c.c index 81336e67555..816ecabd722 100644 --- a/test/dm/i3c.c +++ b/test/dm/i3c.c @@ -8,8 +8,6 @@ #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Basic test of the i3c uclass */ static int dm_test_i3c_base(struct unit_test_state *uts) { diff --git a/test/lib/test_print.c b/test/lib/test_print.c index cd7f3f85769..2aeb034b121 100644 --- a/test/lib/test_print.c +++ b/test/lib/test_print.c @@ -7,13 +7,10 @@ #include #include -#include #include #include #include -DECLARE_GLOBAL_DATA_PTR; - static int test_print_freq(struct unit_test_state *uts, uint64_t freq, char *expected) { diff --git a/test/log/log_filter.c b/test/log/log_filter.c index 680c60164b6..147b83980cf 100644 --- a/test/log/log_filter.c +++ b/test/log/log_filter.c @@ -6,12 +6,9 @@ #include #include #include -#include #include #include -DECLARE_GLOBAL_DATA_PTR; - /* Test invalid options */ static int log_test_filter_invalid(struct unit_test_state *uts) { -- cgit v1.3.1 From 83b28b55d74f884a30c47238dc8bdf9fbe6e495c Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 13 Feb 2026 17:52:47 -0500 Subject: smbios: add support for dynamic generation of Type 9 system slot tables This commit introduces support for generating SMBIOS Type 9 (System Slot) tables using a hybrid approach: 1. Explicit Device Tree definitions: Child node under '/smbios/smbios/system-slot' will be interpreted as individual slot definitions. - Each child represents a slot (e.g., isa, pcmcia, etc.). - Properties follow the SMBIOS specification using lowercase hyphen-separated names such as 'slot-type', 'slot-id', 'segment-group-number', 'bus-number', 'slot-information', etc. - This approach allows full customization of each system slot and is especially suitable for platforms with well-defined slot topology. 2. Automatic detection fallback: If child node under '/smbios/smbios/system-slot' does not exist, the implementation will scan the entire device tree for nodes whose 'device_type' matches known slot-related types ("pci", "isa", "pcmcia", etc.). - When a match is found, default values or heuristics are applied to populate to the System Slot table. - This mode is useful for platforms that lack explicit SMBIOS nodes but still expose slot topology via standard DT conventions. Together, two approaches ensure that SMBIOS Type 9 entries are available whether explicitly described or automatically derived. Signed-off-by: Raymond Mao Tested-by: Ilias Apalodimas --- arch/arm/dts/smbios_generic.dtsi | 3 + cmd/smbios.c | 114 +++++++++++++++ include/smbios.h | 45 ++++++ include/smbios_def.h | 89 ++++++++++++ lib/smbios.c | 301 ++++++++++++++++++++++++++++++++++++++- 5 files changed, 549 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index fc168317c9e..4463dade217 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -77,6 +77,9 @@ SMBIOS_CACHE_OP_WB)>; }; }; + + system-slot { + }; }; }; }; diff --git a/cmd/smbios.c b/cmd/smbios.c index ed419f19028..f9b62e66229 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -119,6 +119,55 @@ static const struct str_lookup_table associativity_strings[] = { }; +static const struct str_lookup_table slot_type_strings[] = { + { SMBIOS_SYSSLOT_TYPE_OTHER, "Other" }, + { SMBIOS_SYSSLOT_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_TYPE_ISA, "ISA" }, + { SMBIOS_SYSSLOT_TYPE_PCI, "PCI" }, + { SMBIOS_SYSSLOT_TYPE_PCMCIA, "PC Card (PCMCIA)" }, + { SMBIOS_SYSSLOT_TYPE_PCIE, "PCI Express" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN2, "PCI Express Gen 2" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN3, "PCI Express Gen 3" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16, "PCI Express Gen 3 x16" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4, "PCI Express Gen 4" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8, "PCI Express Gen 4 x8" }, + { SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16, "PCI Express Gen 4 x16" }, +}; + +static const struct str_lookup_table slot_bus_width_strings[] = { + { SMBIOS_SYSSLOT_WIDTH_OTHER, "Other" }, + { SMBIOS_SYSSLOT_WIDTH_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_WIDTH_8BIT, "8 bit" }, + { SMBIOS_SYSSLOT_WIDTH_16BIT, "16 bit" }, + { SMBIOS_SYSSLOT_WIDTH_32BIT, "32 bit" }, + { SMBIOS_SYSSLOT_WIDTH_64BIT, "64 bit" }, + { SMBIOS_SYSSLOT_WIDTH_128BIT, "128 bit " }, + { SMBIOS_SYSSLOT_WIDTH_1X, "1x or x1" }, + { SMBIOS_SYSSLOT_WIDTH_2X, "2x or x2" }, + { SMBIOS_SYSSLOT_WIDTH_4X, "4x or x4" }, + { SMBIOS_SYSSLOT_WIDTH_8X, "8x or x8" }, + { SMBIOS_SYSSLOT_WIDTH_12X, "12x or x12" }, + { SMBIOS_SYSSLOT_WIDTH_16X, "16x or x16" }, + { SMBIOS_SYSSLOT_WIDTH_32X, "32x or x32" }, +}; + +static const struct str_lookup_table slot_usage_strings[] = { + { SMBIOS_SYSSLOT_USAGE_OTHER, "Other" }, + { SMBIOS_SYSSLOT_USAGE_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_USAGE_AVAILABLE, "Available" }, + { SMBIOS_SYSSLOT_USAGE_INUSE, "In use" }, + { SMBIOS_SYSSLOT_USAGE_NA, "Unavailable" }, +}; + +static const struct str_lookup_table slot_length_strings[] = { + { SMBIOS_SYSSLOT_LENG_OTHER, "Other" }, + { SMBIOS_SYSSLOT_LENG_UNKNOWN, "Unknown" }, + { SMBIOS_SYSSLOT_LENG_SHORT, "Short Length" }, + { SMBIOS_SYSSLOT_LENG_LONG, "Long Length" }, + { SMBIOS_SYSSLOT_LENG_2_5INDRV, "2.5 inch drive form factor" }, + { SMBIOS_SYSSLOT_LENG_3_5INDRV, "3.5 inch drive form factor" }, +}; + /** * smbios_get_string() - get SMBIOS string from table * @@ -403,6 +452,68 @@ static void smbios_print_type7(struct smbios_type7 *table) printf("\tInstalled Cache Size 2: 0x%08x\n", table->inst_size2.data); } +static void smbios_print_type9(struct smbios_type9 *table) +{ + int i; + u8 *addr = (u8 *)table + + offsetof(struct smbios_type9, slot_information); + + printf("System Slots:\n"); + smbios_print_str("Socket Designation", table, + table->socket_design); + smbios_print_lookup_str(slot_type_strings, + table->slot_type, + ARRAY_SIZE(slot_type_strings), + "Slot Type"); + smbios_print_lookup_str(slot_bus_width_strings, + table->slot_data_bus_width, + ARRAY_SIZE(slot_bus_width_strings), + "Slot Data Bus Width"); + smbios_print_lookup_str(slot_usage_strings, + table->current_usage, + ARRAY_SIZE(slot_usage_strings), + "Current Usage"); + smbios_print_lookup_str(slot_length_strings, + table->slot_length, + ARRAY_SIZE(slot_length_strings), + "Slot Length"); + printf("\tSlot ID: 0x%04x\n", table->slot_id); + printf("\tSlot Characteristics 1: 0x%04x\n", + table->slot_characteristics_1); + printf("\tSlot Characteristics 2: 0x%04x\n", + table->slot_characteristics_2); + printf("\tSegment Group Number (Base): 0x%04x\n", + table->segment_group_number); + printf("\tBus Number (Base): 0x%04x\n", table->bus_number); + printf("\tDevice/Function Number (Base): 0x%04x\n", + table->device_function_number.data); + printf("\tData Bus Width (Base): 0x%04x\n", + table->electrical_bus_width); + printf("\tPeer (S/B/D/F/Width) grouping count: 0x%04x\n", + table->peer_grouping_count); + printf("\tPeer (S/B/D/F/Width) groups:\n"); + for (i = 0; i < table->peer_grouping_count; i++) { + printf("\t\tPeer group[%03d]:\n", i); + if (CONFIG_IS_ENABLED(HEXDUMP)) + print_hex_dump("\t\t", DUMP_PREFIX_OFFSET, 16, 1, addr, + SMBIOS_TYPE9_PGROUP_SIZE, false); + addr += SMBIOS_TYPE9_PGROUP_SIZE; + } + printf("\n"); + + /* table->slot_information */ + printf("\tSlot Information: 0x%04x\n", *addr); + /* table->slot_physical_width */ + addr += sizeof(table->slot_information); + printf("\tSlot Physical Width: 0x%04x\n", *addr); + /* table->slot_pitch */ + addr += sizeof(table->slot_physical_width); + printf("\tSlot Pitch: 0x%04x\n", *(u16 *)addr); + /* table->slot_height */ + addr += sizeof(table->slot_pitch); + printf("\tSlot Height: 0x%04x\n", *addr); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -482,6 +593,9 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, case SMBIOS_CACHE_INFORMATION: smbios_print_type7((struct smbios_type7 *)pos); break; + case SMBIOS_SYSTEM_SLOTS: + smbios_print_type9((struct smbios_type9 *)pos); + break; case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; diff --git a/include/smbios.h b/include/smbios.h index f2f7483bce5..752a25250d3 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -264,6 +264,51 @@ struct __packed smbios_type7 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE9_PGROUP_SIZE 5 + +struct pci_attr_lookup_table { + const char *str; + u8 slot_type; + u8 data_bus_width; + u8 slot_length; + u8 chara1; + u8 chara2; +}; + +union dev_func_num { + struct { + u8 dev_num:5; + u8 func_num:3; + } fields; + u8 data; +}; + +struct __packed smbios_type9 { + struct smbios_header hdr; + u8 socket_design; + u8 slot_type; + u8 slot_data_bus_width; + u8 current_usage; + u8 slot_length; + u16 slot_id; + u8 slot_characteristics_1; + u8 slot_characteristics_2; + u16 segment_group_number; + u8 bus_number; + union dev_func_num device_function_number; + u8 electrical_bus_width; + u8 peer_grouping_count; + /* + * Dynamic bytes will be inserted here to store peer_groups. + * length is equal to 'peer_grouping_count' * 5 + */ + u8 slot_information; + u8 slot_physical_width; + u16 slot_pitch; + u8 slot_height; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index 81c5781217f..ef9cb02ed25 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -191,4 +191,93 @@ #define SMBIOS_CACHE_ASSOC_64WAY 13 #define SMBIOS_CACHE_ASSOC_20WAY 14 +/* + * System Slot + */ + +/* Slot Type */ +#define SMBIOS_SYSSLOT_TYPE_OTHER 1 +#define SMBIOS_SYSSLOT_TYPE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_TYPE_ISA 3 /* ISA */ +#define SMBIOS_SYSSLOT_TYPE_PCI 6 /* PCI */ +#define SMBIOS_SYSSLOT_TYPE_PCMCIA 7 /* PCMCIA */ +#define SMBIOS_SYSSLOT_TYPE_PCIE 0xa5 /* PCI Express */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX1 0xa6 /* PCI Express x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX2 0xa7 /* PCI Express x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX4 0xa8 /* PCI Express x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX8 0xa9 /* PCI Express x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEX16 0xaa /* PCI Express x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2 0xab /* PCI Express Gen 2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X1 0xac /* PCI Express Gen 2 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X2 0xad /* PCI Express Gen 2 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X4 0xae /* PCI Express Gen 2 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X8 0xaf /* PCI Express Gen 2 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN2X16 0xb0 /* PCI Express Gen 2 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3 0xb1 /* PCI Express Gen 3 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X1 0xb2 /* PCI Express Gen 3 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X2 0xb3 /* PCI Express Gen 3 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X4 0xb4 /* PCI Express Gen 3 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X8 0xb5 /* PCI Express Gen 3 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16 0xb6 /* PCI Express Gen 3 x16 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4 0xb8 /* PCI Express Gen 4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X1 0xb9 /* PCI Express Gen 4 x1 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X2 0xba /* PCI Express Gen 4 x2 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X4 0xbb /* PCI Express Gen 4 x4 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8 0xbc /* PCI Express Gen 4 x8 */ +#define SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16 0xbd /* PCI Express Gen 4 x16 */ + +/* Slot Data Bus Width */ +#define SMBIOS_SYSSLOT_WIDTH_OTHER 1 +#define SMBIOS_SYSSLOT_WIDTH_UNKNOWN 2 +#define SMBIOS_SYSSLOT_WIDTH_8BIT 3 +#define SMBIOS_SYSSLOT_WIDTH_16BIT 4 +#define SMBIOS_SYSSLOT_WIDTH_32BIT 5 +#define SMBIOS_SYSSLOT_WIDTH_64BIT 6 +#define SMBIOS_SYSSLOT_WIDTH_128BIT 7 +#define SMBIOS_SYSSLOT_WIDTH_1X 8 +#define SMBIOS_SYSSLOT_WIDTH_2X 9 +#define SMBIOS_SYSSLOT_WIDTH_4X 10 +#define SMBIOS_SYSSLOT_WIDTH_8X 11 +#define SMBIOS_SYSSLOT_WIDTH_12X 12 +#define SMBIOS_SYSSLOT_WIDTH_16X 13 +#define SMBIOS_SYSSLOT_WIDTH_32X 14 + +/* Current Usage */ +#define SMBIOS_SYSSLOT_USAGE_OTHER 1 +#define SMBIOS_SYSSLOT_USAGE_UNKNOWN 2 +#define SMBIOS_SYSSLOT_USAGE_AVAILABLE 3 +#define SMBIOS_SYSSLOT_USAGE_INUSE 4 +#define SMBIOS_SYSSLOT_USAGE_NA 5 + +/* Slot Length */ +#define SMBIOS_SYSSLOT_LENG_OTHER 1 +#define SMBIOS_SYSSLOT_LENG_UNKNOWN 2 +#define SMBIOS_SYSSLOT_LENG_SHORT 3 +#define SMBIOS_SYSSLOT_LENG_LONG 4 +#define SMBIOS_SYSSLOT_LENG_2_5INDRV 5 +#define SMBIOS_SYSSLOT_LENG_3_5INDRV 6 + +/* Slot Characteristics 1 */ +#define SMBIOS_SYSSLOT_CHAR_UND 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_5V 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_3_3V 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_SHARED 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARD16 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDBUS 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDZV 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_PCCARDMRR 0x80 /* BIT(7) */ + +/* Slot Characteristics 2 */ +#define SMBIOS_SYSSLOT_CHAR_PCIPME 1 /* BIT(0) */ +#define SMBIOS_SYSSLOT_CHAR_HOTPLUG 2 /* BIT(1) */ +#define SMBIOS_SYSSLOT_CHAR_PCISMB 4 /* BIT(2) */ +#define SMBIOS_SYSSLOT_CHAR_PCIBIF 8 /* BIT(3) */ +#define SMBIOS_SYSSLOT_CHAR_ASYNCRM 16 /* BIT(4) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL1 32 /* BIT(5) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL2 64 /* BIT(6) */ +#define SMBIOS_SYSSLOT_CHAR_FBCXL3 0x80 /* BIT(7) */ + +/* Slot segment group number */ +#define SMBIOS_SYSSLOT_SGGNUM_UND 0 + #endif /* _SMBIOS_DEF_H_ */ diff --git a/lib/smbios.c b/lib/smbios.c index 85508c06547..caeb309294d 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -66,11 +66,47 @@ struct map_sysinfo { static const struct map_sysinfo sysinfo_to_dt[] = { { .si_node = "system", .si_str = "product", .dt_str = "model", 2 }, - { .si_node = "system", .si_str = "manufacturer", .dt_str = "compatible", 1 }, - { .si_node = "baseboard", .si_str = "product", .dt_str = "model", 2 }, - { .si_node = "baseboard", .si_str = "manufacturer", .dt_str = "compatible", 1 }, + { .si_node = "system", .si_str = "manufacturer", + .dt_str = "compatible", 1 }, + { .si_node = "baseboard", .si_str = "product", + .dt_str = "model", 2 }, + { .si_node = "baseboard", .si_str = "manufacturer", + .dt_str = "compatible", 1 }, + { .si_node = "system-slot", .si_str = "slot-type", + .dt_str = "device_type", 0}, + { .si_node = "system-slot", .si_str = "segment-group-number", + .dt_str = "linux,pci-domain", 0}, }; +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) +static const struct pci_attr_lookup_table pci_attr[] = { + { "pci-host-ecam-generic", SMBIOS_SYSSLOT_TYPE_PCIE, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, SMBIOS_SYSSLOT_CHAR_PCIPME }, + { "pci-host-cam-generic", SMBIOS_SYSSLOT_TYPE_PCI, + SMBIOS_SYSSLOT_WIDTH_32BIT, SMBIOS_SYSSLOT_LENG_SHORT, + SMBIOS_SYSSLOT_CHAR_5V | SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME }, + { "pci-host-thunder-ecam", SMBIOS_SYSSLOT_TYPE_PCIEGEN3, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-octeontx-ecam", SMBIOS_SYSSLOT_TYPE_PCIEGEN3X16, + SMBIOS_SYSSLOT_WIDTH_16X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-thunder-pem", SMBIOS_SYSSLOT_TYPE_PCIEGEN4X8, + SMBIOS_SYSSLOT_WIDTH_8X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG }, + { "pci-host-octeontx2-pem", SMBIOS_SYSSLOT_TYPE_PCIEGEN4X16, + SMBIOS_SYSSLOT_WIDTH_16X, SMBIOS_SYSSLOT_LENG_LONG, + SMBIOS_SYSSLOT_CHAR_3_3V, + SMBIOS_SYSSLOT_CHAR_PCIPME | SMBIOS_SYSSLOT_CHAR_HOTPLUG | + SMBIOS_SYSSLOT_CHAR_PCIBIF }, +}; +#endif + /** * struct smbios_ctx - context for writing SMBIOS tables * @@ -95,6 +131,10 @@ struct smbios_ctx { char *last_str; }; +typedef int (*smbios_write_subnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type); + /** * Function prototype to write a specific type of SMBIOS structure * @@ -222,6 +262,7 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, { #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) int val; + const struct map_sysinfo *nprop; if (!ctx->dev) return val_def; @@ -240,6 +281,11 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, */ if (!ofnode_read_u32(ofnode_root(), prop, &val)) return val; + + /* If the node is still missing, try with the mapping values */ + nprop = convert_sysinfo_to_dt(ctx->subnode_name, prop); + if (!ofnode_read_u32(ofnode_root(), nprop->dt_str, &val)) + return val; #endif return val_def; } @@ -859,6 +905,252 @@ static int smbios_write_type7(ulong *current, int *handle, return len; } +static int smbios_scan_subnodes(ulong *current, struct smbios_ctx *ctx, + int *handle, smbios_write_subnode cb, int type) +{ + ofnode child; + int i; + int hdl_base = *handle; + int len = 0; + struct smbios_ctx ctx_bak; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (i = 0, child = ofnode_first_subnode(ctx->node); + ofnode_valid(child); child = ofnode_next_subnode(child), i++) { + ctx->node = child; + *handle = hdl_base + i; + len += cb(current, *handle, ctx, i, type); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + } + + return len; +} + +static void smbios_lookup_pci_attr(struct smbios_ctx *ctx, + struct smbios_type9 *t) +{ + const char *compatible; + u32 addr_cells, size_cells, total_cells; + const fdt32_t *reg; + int reglen; + int i; + + /* default attributes */ + t->slot_type = SMBIOS_SYSSLOT_TYPE_PCI; + t->slot_data_bus_width = SMBIOS_SYSSLOT_WIDTH_UNKNOWN; + t->slot_characteristics_1 = SMBIOS_SYSSLOT_CHAR_UND; + t->current_usage = SMBIOS_SYSSLOT_USAGE_UNKNOWN; + t->slot_length = SMBIOS_SYSSLOT_LENG_UNKNOWN; + t->segment_group_number = smbios_get_val_si(ctx, "segment-group-number", + SYSID_NONE, + SMBIOS_SYSSLOT_SGGNUM_UND); + + /* + * Get #address-cells and #size-cells dynamically + * Default 3 for #address-cells and 2 for #size-cells + */ + addr_cells = ofnode_read_u32_default(ctx->node, "#address-cells", 3); + size_cells = ofnode_read_u32_default(ctx->node, "#size-cells", 2); + total_cells = addr_cells + size_cells; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(ctx->node, "reg", ®len); + if (reg && reglen > addr_cells * sizeof(*reg)) { + /* First address-cell: Bus Number */ + if (addr_cells >= 1) + t->bus_number = fdt32_to_cpu(reg[0]); + /* Second address-cell: Device/Function */ + if (addr_cells >= 2) + t->device_function_number.data = fdt32_to_cpu(reg[1]); + /* + * Third address-cell 'Register Offset' and the following + * size-cell bytes are not useful for SMBIOS type 9, just + * ignore them. + */ + /* + * As neither PCI IRQ Routing Table ($PIRQ) nor FDT + * property to represent a Slot ID, try to derive a + * Slot ID programmatically. + */ + t->slot_id = t->device_function_number.fields.dev_num | + (t->bus_number << 5); + } + + /* Read 'compatible' property */ + compatible = ofnode_read_string(ctx->node, "compatible"); + if (!compatible) + return; + + for (i = 0; i < ARRAY_SIZE(pci_attr); i++) { + if (strstr(compatible, pci_attr[i].str)) { + t->slot_type = pci_attr[i].slot_type; + t->slot_data_bus_width = pci_attr[i].data_bus_width; + t->slot_length = pci_attr[i].slot_length; + t->slot_characteristics_1 = pci_attr[i].chara1; + t->slot_characteristics_2 = pci_attr[i].chara2; + /* mark it as in-use arbitrarily */ + t->current_usage = SMBIOS_SYSSLOT_USAGE_INUSE; + return; + } + } +} + +static void smbios_write_type9_fields(struct smbios_ctx *ctx, + struct smbios_type9 *t) +{ + t->slot_type = smbios_get_val_si(ctx, "slot-type", SYSID_NONE, + SMBIOS_SYSSLOT_TYPE_UNKNOWN); + t->slot_data_bus_width = + smbios_get_val_si(ctx, "data-bus-width", + SYSID_NONE, SMBIOS_SYSSLOT_WIDTH_UNKNOWN); + t->current_usage = smbios_get_val_si(ctx, "current-usage", SYSID_NONE, + SMBIOS_SYSSLOT_USAGE_UNKNOWN); + t->slot_length = smbios_get_val_si(ctx, "slot-length", SYSID_NONE, + SMBIOS_SYSSLOT_LENG_UNKNOWN); + t->slot_id = smbios_get_val_si(ctx, "slot-id", SYSID_NONE, 0); + t->slot_characteristics_1 = + smbios_get_val_si(ctx, "slot-characteristics-1", SYSID_NONE, + SMBIOS_SYSSLOT_CHAR_UND); + t->slot_characteristics_2 = smbios_get_val_si(ctx, + "slot-characteristics-2", + SYSID_NONE, 0); + t->segment_group_number = smbios_get_val_si(ctx, "segment-group-number", + SYSID_NONE, 0); + t->bus_number = smbios_get_val_si(ctx, "bus-number", SYSID_NONE, 0); + t->device_function_number.data = + smbios_get_val_si(ctx, "device-function-number", SYSID_NONE, 0); +} + +static int smbios_write_type9_1slot(ulong *current, int handle, + struct smbios_ctx *ctx, + int __maybe_unused idx, int devtype) +{ + struct smbios_type9 *t; + int len = sizeof(*t); + u8 pgroups_cnt; + u8 *eos_addr; + size_t pgroups_size; + void *wp; + + pgroups_cnt = smbios_get_val_si(ctx, "peer-grouping-count", + SYSID_NONE, 0); + pgroups_size = pgroups_cnt * SMBIOS_TYPE9_PGROUP_SIZE; + + /* + * reserve the space for the dynamic bytes of peer_groups. + * TODO: + * peer_groups = * SMBIOS_TYPE9_PGROUP_SIZE + */ + len += pgroups_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_SYSTEM_SLOTS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Write the general fields */ + t->peer_grouping_count = pgroups_cnt; + t->socket_design = smbios_add_prop_si(ctx, "socket-design", SYSID_NONE, + NULL); + t->electrical_bus_width = smbios_get_val_si(ctx, "data-bus-width", + SYSID_NONE, 0); + + /* skip the reserved peer groups and write the following fields from eos */ + /* t->slot_height */ + wp = eos_addr - sizeof(t->slot_height); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-height", SYSID_NONE, 0); + /* t->slot_pitch */ + wp -= sizeof(t->slot_pitch); + *((u16 *)wp) = smbios_get_val_si(ctx, "slot-pitch", SYSID_NONE, 0); + /* t->slot_physical_width */ + wp -= sizeof(t->slot_physical_width); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-physical-width", SYSID_NONE, 0); + /* t->slot_information */ + wp -= sizeof(t->slot_information); + *((u8 *)wp) = smbios_get_val_si(ctx, "slot-information", SYSID_NONE, 0); + + /* For PCI, some fields can be extracted from FDT node */ + if (devtype == SMBIOS_SYSSLOT_TYPE_PCI) + /* Populate PCI attributes from existing PCI properties */ + smbios_lookup_pci_attr(ctx, t); + else if (devtype == SMBIOS_SYSSLOT_TYPE_UNKNOWN) { + /* Properties that expected in smbios subnode 'system-slot' */ + smbios_write_type9_fields(ctx, t); + } + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_scan_slot_type(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int i = 0; + struct smbios_ctx ctx_bak; + ofnode child; + const struct map_sysinfo *prop; + int hdl_base = *handle; + int len = 0; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + prop = convert_sysinfo_to_dt(ctx->subnode_name, "slot-type"); + for (child = ofnode_first_subnode(ofnode_root()); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + const char *dev_type_str; + u8 dev_type = SMBIOS_SYSSLOT_TYPE_UNKNOWN; + + dev_type_str = ofnode_read_string(child, prop->dt_str); + if (!dev_type_str) + continue; + + if (!strcmp(dev_type_str, "pci")) + dev_type = SMBIOS_SYSSLOT_TYPE_PCI; + else if (!strcmp(dev_type_str, "isa")) + dev_type = SMBIOS_SYSSLOT_TYPE_ISA; + else if (!strcmp(dev_type_str, "pcmcia")) + dev_type = SMBIOS_SYSSLOT_TYPE_PCMCIA; + else + continue; + + *handle = hdl_base + i; + ctx->node = child; + len += smbios_write_type9_1slot(current, *handle, ctx, 0, + dev_type); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + i++; + } + + return len; +} + +static int smbios_write_type9(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int len; + + /* TODO: Get system slot information via pci subsystem */ + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + len = smbios_scan_subnodes(current, ctx, handle, + smbios_write_type9_1slot, + SMBIOS_SYSSLOT_TYPE_UNKNOWN); + if (len) + return len; + + /* if no subnode under 'system-slot', try scan the entire FDT */ + len = smbios_scan_slot_type(current, handle, ctx); + + return len; +} + #endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ static int smbios_write_type32(ulong *current, int *handle, @@ -905,6 +1197,9 @@ static struct smbios_write_method smbios_write_funcs[] = { { smbios_write_type7, "cache", }, #endif { smbios_write_type4, "processor"}, +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) + { smbios_write_type9, "system-slot"}, +#endif { smbios_write_type32, }, { smbios_write_type127 }, }; -- cgit v1.3.1 From 374896158b435843d8ecf2c04c9985b0321295e0 Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 13 Feb 2026 17:52:48 -0500 Subject: smbios: add support for dynamic generation of Type 16 table This commit implements SMBIOS Type 16 (Physical Memory Array) generation with a hybrid approach supporting both: 1. Explicit definition via Device Tree 'smbios' node: Child node under '/smbios/smbios/memory-array' will be used to populate as individual Type 16 structure directly. - Properties follow SMBIOS field names with lowercase letters and hyphen-separated words (e.g., 'memory-error-correction', 'maximum-capacity', 'extended-maximum-capacity', etc.). - This method supports precise platform-defined overrides and system descriptions. 2. Fallback to automatic DT-based discovery: If child node under '/smbios/smbios/memory-array' does not exist, the implementation will: - Scan all top-level 'memory@' nodes to populate Type 16 structure with inferred size and location data. - Scan nodes named or marked as 'memory-controller' and parse associated 'dimm@' subnodes (if present) to extract DIMM sizes and map them accordingly. This dual-mode support enables flexible firmware SMBIOS reporting while aligning with spec-compliant naming and runtime-detected memory topology. Type 16 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid increasing rom size for those platforms which only require basic SMBIOS support. Signed-off-by: Raymond Mao Tested-by: Ilias Apalodimas --- arch/arm/dts/smbios_generic.dtsi | 3 + cmd/smbios.c | 46 +++++++ drivers/sysinfo/smbios.c | 5 + include/smbios.h | 18 +++ include/smbios_def.h | 29 ++++ include/sysinfo.h | 4 + lib/smbios.c | 282 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 387 insertions(+) (limited to 'include') diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index 4463dade217..1a9adfaa409 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -80,6 +80,9 @@ system-slot { }; + + memory-array { + }; }; }; }; diff --git a/cmd/smbios.c b/cmd/smbios.c index f9b62e66229..3f7dd21f92e 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -168,6 +168,32 @@ static const struct str_lookup_table slot_length_strings[] = { { SMBIOS_SYSSLOT_LENG_3_5INDRV, "3.5 inch drive form factor" }, }; +static const struct str_lookup_table ma_location_strings[] = { + { SMBIOS_MA_LOCATION_OTHER, "Other" }, + { SMBIOS_MA_LOCATION_UNKNOWN, "Unknown" }, + { SMBIOS_MA_LOCATION_MOTHERBOARD, "System board or motherboard" }, +}; + +static const struct str_lookup_table ma_use_strings[] = { + { SMBIOS_MA_USE_OTHER, "Other" }, + { SMBIOS_MA_USE_UNKNOWN, "Unknown" }, + { SMBIOS_MA_USE_SYSTEM, "System memory" }, + { SMBIOS_MA_USE_VIDEO, "Video memory" }, + { SMBIOS_MA_USE_FLASH, "Flash memory" }, + { SMBIOS_MA_USE_NVRAM, "Non-volatile RAM" }, + { SMBIOS_MA_USE_CACHE, "Cache memory" }, +}; + +static const struct str_lookup_table ma_err_corr_strings[] = { + { SMBIOS_MA_ERRCORR_OTHER, "Other" }, + { SMBIOS_MA_ERRCORR_UNKNOWN, "Unknown" }, + { SMBIOS_MA_ERRCORR_NONE, "None" }, + { SMBIOS_MA_ERRCORR_PARITY, "Parity" }, + { SMBIOS_MA_ERRCORR_SBITECC, "Single-bit ECC" }, + { SMBIOS_MA_ERRCORR_MBITECC, "Multi-bit ECC" }, + { SMBIOS_MA_ERRCORR_CRC, "CRC" }, +}; + /** * smbios_get_string() - get SMBIOS string from table * @@ -514,6 +540,23 @@ static void smbios_print_type9(struct smbios_type9 *table) printf("\tSlot Height: 0x%04x\n", *addr); } +static void smbios_print_type16(struct smbios_type16 *table) +{ + printf("Physical Memory Array:\n"); + smbios_print_lookup_str(ma_location_strings, table->location, + ARRAY_SIZE(ma_location_strings), "Location"); + smbios_print_lookup_str(ma_use_strings, table->use, + ARRAY_SIZE(ma_use_strings), "Use"); + smbios_print_lookup_str(ma_err_corr_strings, table->mem_err_corr, + ARRAY_SIZE(ma_err_corr_strings), + "Memory Error Correction"); + printf("\tMaximum Capacity: 0x%08x\n", table->max_cap); + printf("\tMemory Error Information Handle: 0x%04x\n", + table->mem_err_info_hdl); + printf("\tNumber of Memory Devices: 0x%04x\n", table->num_of_mem_dev); + printf("\tExtended Maximum Capacity: 0x%016llx\n", table->ext_max_cap); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -596,6 +639,9 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, case SMBIOS_SYSTEM_SLOTS: smbios_print_type9((struct smbios_type9 *)pos); break; + case SMBIOS_PHYS_MEMORY_ARRAY: + smbios_print_type16((struct smbios_type16 *)pos); + break; case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; diff --git a/drivers/sysinfo/smbios.c b/drivers/sysinfo/smbios.c index 99104274f72..ff5873c940e 100644 --- a/drivers/sysinfo/smbios.c +++ b/drivers/sysinfo/smbios.c @@ -24,6 +24,7 @@ struct sysinfo_plat_priv { struct smbios_type7 t7[SYSINFO_CACHE_LVL_MAX]; u16 cache_handles[SYSINFO_CACHE_LVL_MAX]; u8 cache_level; + u16 marray_handles[SYSINFO_MEM_HANDLE_MAX]; }; static void smbios_cache_info_dump(struct smbios_type7 *cache_info) @@ -165,6 +166,10 @@ static int sysinfo_plat_get_data(struct udevice *dev, int id, void **buf, *buf = &priv->cache_handles[0]; *size = sizeof(priv->cache_handles); break; + case SYSID_SM_MEMARRAY_HANDLE: + *buf = &priv->marray_handles[0]; + *size = sizeof(priv->marray_handles); + break; default: return -EOPNOTSUPP; } diff --git a/include/smbios.h b/include/smbios.h index 752a25250d3..293d6795cf3 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -309,6 +309,24 @@ struct __packed smbios_type9 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +enum { + SMBIOS_MEM_NONE = 0, + SMBIOS_MEM_CUSTOM = 1, + SMBIOS_MEM_FDT_MEM_NODE = 2, + SMBIOS_MEM_FDT_MEMCON_NODE = 3 +}; + +struct __packed smbios_type16 { + struct smbios_header hdr; + u8 location; + u8 use; + u8 mem_err_corr; + u32 max_cap; + u16 mem_err_info_hdl; + u16 num_of_mem_dev; + u64 ext_max_cap; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index ef9cb02ed25..c6850a5d6f5 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -280,4 +280,33 @@ /* Slot segment group number */ #define SMBIOS_SYSSLOT_SGGNUM_UND 0 +/* Physical Memory Array */ + +/* Location */ +#define SMBIOS_MA_LOCATION_OTHER 1 +#define SMBIOS_MA_LOCATION_UNKNOWN 2 +#define SMBIOS_MA_LOCATION_MOTHERBOARD 3 + +/* Use */ +#define SMBIOS_MA_USE_OTHER 1 +#define SMBIOS_MA_USE_UNKNOWN 2 +#define SMBIOS_MA_USE_SYSTEM 3 +#define SMBIOS_MA_USE_VIDEO 4 +#define SMBIOS_MA_USE_FLASH 5 +#define SMBIOS_MA_USE_NVRAM 6 +#define SMBIOS_MA_USE_CACHE 7 + +/* Error Correction Type */ +#define SMBIOS_MA_ERRCORR_OTHER 1 +#define SMBIOS_MA_ERRCORR_UNKNOWN 2 +#define SMBIOS_MA_ERRCORR_NONE 3 +#define SMBIOS_MA_ERRCORR_PARITY 4 +#define SMBIOS_MA_ERRCORR_SBITECC 5 +#define SMBIOS_MA_ERRCORR_MBITECC 6 +#define SMBIOS_MA_ERRCORR_CRC 7 + +/* Error Information Handle */ +#define SMBIOS_MA_ERRINFO_NONE 0xFFFE +#define SMBIOS_MA_ERRINFO_NOERR 0xFFFF + #endif /* _SMBIOS_DEF_H_ */ diff --git a/include/sysinfo.h b/include/sysinfo.h index e87cf969fcd..54eb64a204a 100644 --- a/include/sysinfo.h +++ b/include/sysinfo.h @@ -12,6 +12,7 @@ struct udevice; #define SYSINFO_CACHE_LVL_MAX 3 +#define SYSINFO_MEM_HANDLE_MAX 8 /* * This uclass encapsulates hardware methods to gather information about a @@ -149,6 +150,9 @@ enum sysinfo_id { SYSID_SM_CACHE_INFO_END = SYSID_SM_CACHE_INST_SIZE2 + SYSINFO_CACHE_LVL_MAX - 1, + /* Memory Array (Type 16) */ + SYSID_SM_MEMARRAY_HANDLE, + /* For show_board_info() */ SYSID_BOARD_MODEL, SYSID_BOARD_MANUFACTURER, diff --git a/lib/smbios.c b/lib/smbios.c index caeb309294d..27c9c975cf2 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -290,6 +290,49 @@ static int smbios_get_val_si(struct smbios_ctx * __maybe_unused ctx, return val_def; } +#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) +static u64 smbios_get_u64_si(struct smbios_ctx * __maybe_unused ctx, + const char * __maybe_unused prop, + int __maybe_unused sysinfo_id, u64 val_def) +{ + size_t len; + void *data; + const fdt32_t *prop_val; + int prop_len; + u64 val = 0; + + if (!ctx->dev) + return val_def; + + if (!sysinfo_get_data(ctx->dev, sysinfo_id, &data, &len)) + return *((u64 *)data); + + if (!IS_ENABLED(CONFIG_OF_CONTROL) || !prop || !ofnode_valid(ctx->node)) + return val_def; + + prop_val = ofnode_read_prop(ctx->node, prop, &prop_len); + if (!prop_val || prop_len < sizeof(fdt32_t) || + prop_len % sizeof(fdt32_t)) { + /* + * If the node or property is not valid fallback and try the root + */ + prop_val = ofnode_read_prop(ofnode_root(), prop, &prop_len); + if (!prop_val || prop_len < sizeof(fdt32_t) || + prop_len % sizeof(fdt32_t)) + return val_def; + } + + /* 64-bit: or 32-bit */ + if (prop_len >= sizeof(fdt32_t) * 2) { + val = ((u64)fdt32_to_cpu(prop_val[0]) << 32) | + fdt32_to_cpu(prop_val[1]); + } else { + val = fdt32_to_cpu(prop_val[0]); + } + return val; +} +#endif + /** * smbios_add_prop_si() - Add a property from the devicetree or sysinfo * @@ -1151,6 +1194,244 @@ static int smbios_write_type9(ulong *current, int *handle, return len; } +static u64 smbios_pop_size_from_memory_node(ofnode node) +{ + const fdt32_t *reg; + int len; + u64 size_bytes; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return 0; + + /* Combine hi/lo for size (typically 64-bit) */ + size_bytes = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + + return size_bytes; +} + +static int +smbios_write_type16_sum_memory_nodes(ulong *current, int handle, + struct smbios_ctx *ctx, u16 cnt, u64 size) +{ + struct smbios_type16 *t; + int len = sizeof(*t); + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_PHYS_MEMORY_ARRAY, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* default attributes */ + t->location = SMBIOS_MA_LOCATION_MOTHERBOARD; + t->use = SMBIOS_MA_USE_SYSTEM; + t->mem_err_corr = SMBIOS_MA_ERRCORR_UNKNOWN; + t->mem_err_info_hdl = SMBIOS_MA_ERRINFO_NONE; + t->num_of_mem_dev = cnt; + + /* Use extended field */ + t->max_cap = cpu_to_le32(0x80000000); + t->ext_max_cap = cpu_to_le64(size >> 10); /* In KB */ + + /* Save the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + *((u16 *)hdl) = handle; + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static void +smbios_pop_type16_from_memcontroller_node(ofnode node, struct smbios_type16 *t) +{ + ofnode child; + int count = 0; + u64 total = 0; + + /* default attributes */ + t->location = SMBIOS_MA_LOCATION_MOTHERBOARD; + t->use = SMBIOS_MA_USE_SYSTEM; + t->mem_err_info_hdl = SMBIOS_MA_ERRINFO_NONE; + + /* Check custom property 'ecc-enabled' */ + if (ofnode_read_bool(node, "ecc-enabled")) + t->mem_err_corr = SMBIOS_MA_ERRCORR_SBITECC; + else + t->mem_err_corr = SMBIOS_MA_ERRCORR_UNKNOWN; + + /* Read subnodes with 'size' property */ + for (child = ofnode_first_subnode(node); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + u64 sz = 0; + const fdt32_t *size; + int len; + + size = ofnode_read_prop(child, "size", &len); + if (!size || len < sizeof(fdt32_t) || len % sizeof(fdt32_t)) + continue; + + /* 64-bit size: or 32-bit size */ + if (len >= sizeof(fdt32_t) * 2) + sz = ((u64)fdt32_to_cpu(size[0]) << 32) | + fdt32_to_cpu(size[1]); + else + sz = fdt32_to_cpu(size[0]); + + count++; + total += sz; + } + + /* + * Number of memory devices associated with this array + * (i.e., how many Type17 entries link to this Type16 array) + */ + t->num_of_mem_dev = count; + + /* Use extended field */ + t->max_cap = cpu_to_le32(0x80000000); + t->ext_max_cap = cpu_to_le64(total >> 10); /* In KB */ +} + +static void smbios_pop_type16_si(struct smbios_ctx *ctx, + struct smbios_type16 *t) +{ + t->location = smbios_get_val_si(ctx, "location", SYSID_NONE, + SMBIOS_MA_LOCATION_UNKNOWN); + t->use = smbios_get_val_si(ctx, "use", SYSID_NONE, + SMBIOS_MA_USE_UNKNOWN); + t->mem_err_corr = smbios_get_val_si(ctx, "memory-error-correction", SYSID_NONE, + SMBIOS_MA_ERRCORR_UNKNOWN); + t->max_cap = smbios_get_val_si(ctx, "maximum-capacity", SYSID_NONE, 0); + t->mem_err_info_hdl = smbios_get_val_si(ctx, "memory-error-information-handle", + SYSID_NONE, SMBIOS_MA_ERRINFO_NONE); + t->num_of_mem_dev = smbios_get_val_si(ctx, "number-of-memory-devices", SYSID_NONE, 1); + t->ext_max_cap = smbios_get_u64_si(ctx, "extended-maximum-capacity", SYSID_NONE, 0); +} + +static int smbios_write_type16_1array(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type16 *t; + int len = sizeof(*t); + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_PHYS_MEMORY_ARRAY, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) + smbios_pop_type16_si(ctx, t); + else if (type == SMBIOS_MEM_FDT_MEMCON_NODE) + smbios_pop_type16_from_memcontroller_node(ctx->node, t); + + /* Save the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + *((u16 *)hdl + idx) = handle; + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type16(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + int len; + struct smbios_ctx ctx_bak; + ofnode child; + int idx; + u64 total = 0; + int count = 0; + int hdl_base = *handle; + + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + /* Step 1: Scan any subnode exists under 'memory-array' */ + len = smbios_scan_subnodes(current, ctx, handle, + smbios_write_type16_1array, + SMBIOS_MEM_CUSTOM); + if (len) + return len; + + /* Step 2: Scan 'memory' node from the entire FDT */ + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *str; + + /* Look up for 'device_type = "memory"' */ + str = ofnode_read_string(child, "device_type"); + if (str && !strcmp(str, "memory")) { + count++; + total += smbios_pop_size_from_memory_node(child); + } + } + /* + * Generate one type16 instance for all 'memory' nodes, + * use idx=0 implicitly + */ + if (count) + len += smbios_write_type16_sum_memory_nodes(current, *handle, + ctx, count, total); + + /* Step 3: Scan 'memory-controller' node from the entire FDT */ + /* idx starts from 1 */ + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + for (idx = 1, child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *compat; + const char *name; + + /* + * Look up for node with name or property 'compatible' + * containing 'memory-controller'. + */ + name = ofnode_get_name(child); + compat = ofnode_read_string(child, "compatible"); + if ((!compat || !strstr(compat, "memory-controller")) && + (!name || !strstr(name, "memory-controller"))) + continue; + + *handle = hdl_base + idx; + ctx->node = child; + /* + * Generate one type16 instance for each 'memory-controller' + * node, sum the 'size' of all subnodes. + */ + len += smbios_write_type16_1array(current, *handle, ctx, idx, + SMBIOS_MEM_FDT_MEMCON_NODE); + idx++; + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + } + + return len; +} + #endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ static int smbios_write_type32(ulong *current, int *handle, @@ -1199,6 +1480,7 @@ static struct smbios_write_method smbios_write_funcs[] = { { smbios_write_type4, "processor"}, #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) { smbios_write_type9, "system-slot"}, + { smbios_write_type16, "memory-array"}, #endif { smbios_write_type32, }, { smbios_write_type127 }, -- cgit v1.3.1 From 23674dee60240393dd17836c05df5b4f4aa01e5c Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 13 Feb 2026 17:52:49 -0500 Subject: smbios: add support for dynamic generation of Type 17 table This commit implements SMBIOS Type 17 (Memory Device) generation with a hybrid approach supporting both: 1. Explicit definition via Device Tree 'smbios' node: Child node under '/smbios/smbios/memory-device' will be used to populate as individual Type 17 structure directly. - Properties follow SMBIOS field names with lowercase letters and hyphen-separated words (e.g., 'physical-memory-array-handle', ' memory-error-information-handle', 'configured-memory-speed', etc.). - This method supports precise platform-defined overrides and system descriptions. 2. Fallback to automatic DT-based discovery: If child node under '/smbios/smbios/memory-device' does not exist, the implementation will: - Scan all top-level 'memory@' nodes to populate Type 17 structure with inferred size and location data. - Scan nodes named or marked as 'memory-controller' and parse associated 'dimm@' subnodes (if present) to extract DIMM sizes and map them accordingly. This dual-mode support enables flexible firmware SMBIOS reporting while aligning with spec-compliant naming and runtime-detected memory topology. Type 17 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid increasing rom size for those platforms which only require basic SMBIOS support. Signed-off-by: Raymond Mao Tested-by: Ilias Apalodimas --- arch/arm/dts/smbios_generic.dtsi | 3 + cmd/smbios.c | 126 +++++++++++++ include/smbios.h | 45 +++++ include/smbios_def.h | 127 +++++++++++++ lib/smbios.c | 376 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 677 insertions(+) (limited to 'include') diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index 1a9adfaa409..fd2df8d02e0 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -83,6 +83,9 @@ memory-array { }; + + memory-device { + }; }; }; }; diff --git a/cmd/smbios.c b/cmd/smbios.c index 3f7dd21f92e..39c9c44a28e 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -194,6 +194,74 @@ static const struct str_lookup_table ma_err_corr_strings[] = { { SMBIOS_MA_ERRCORR_CRC, "CRC" }, }; +static const struct str_lookup_table md_form_factor_strings[] = { + { SMBIOS_MD_FF_OTHER, "Other" }, + { SMBIOS_MD_FF_UNKNOWN, "Unknown" }, + { SMBIOS_MD_FF_SIMM, "SIMM" }, + { SMBIOS_MD_FF_SIP, "SIP" }, + { SMBIOS_MD_FF_CHIP, "Chip" }, + { SMBIOS_MD_FF_DIP, "DIP" }, + { SMBIOS_MD_FF_ZIP, "ZIP" }, + { SMBIOS_MD_FF_PROPCARD, "Proprietary Card" }, + { SMBIOS_MD_FF_DIMM, "DIMM" }, + { SMBIOS_MD_FF_TSOP, "TSOP" }, + { SMBIOS_MD_FF_ROC, "Row of chips" }, + { SMBIOS_MD_FF_RIMM, "RIMM" }, + { SMBIOS_MD_FF_SODIMM, "SODIMM" }, + { SMBIOS_MD_FF_SRIMM, "SRIMM" }, + { SMBIOS_MD_FF_FBDIMM, "FB-DIMM" }, + { SMBIOS_MD_FF_DIE, "Die" }, +}; + +static const struct str_lookup_table md_type_strings[] = { + { SMBIOS_MD_TYPE_OTHER, "Other" }, + { SMBIOS_MD_TYPE_UNKNOWN, "Unknown" }, + { SMBIOS_MD_TYPE_DRAM, "DRAM" }, + { SMBIOS_MD_TYPE_EDRAM, "EDRAM" }, + { SMBIOS_MD_TYPE_VRAM, "VRAM" }, + { SMBIOS_MD_TYPE_SRAM, "SRAM" }, + { SMBIOS_MD_TYPE_RAM, "RAM" }, + { SMBIOS_MD_TYPE_ROM, "ROM" }, + { SMBIOS_MD_TYPE_FLASH, "FLASH" }, + { SMBIOS_MD_TYPE_EEPROM, "EEPROM" }, + { SMBIOS_MD_TYPE_FEPROM, "FEPROM" }, + { SMBIOS_MD_TYPE_EPROM, "EPROM" }, + { SMBIOS_MD_TYPE_CDRAM, "CDRAM" }, + { SMBIOS_MD_TYPE_3DRAM, "3DRAM" }, + { SMBIOS_MD_TYPE_SDRAM, "SDRAM" }, + { SMBIOS_MD_TYPE_SGRAM, "SGRAM" }, + { SMBIOS_MD_TYPE_RDRAM, "RDRAM" }, + { SMBIOS_MD_TYPE_DDR, "DDR" }, + { SMBIOS_MD_TYPE_DDR2, "DDR2" }, + { SMBIOS_MD_TYPE_DDR2FBD, "DDR2 FB-DIMM" }, + { SMBIOS_MD_TYPE_RSVD1, "Reserved" }, + { SMBIOS_MD_TYPE_RSVD2, "Reserved" }, + { SMBIOS_MD_TYPE_DSVD3, "Reserved" }, + { SMBIOS_MD_TYPE_DDR3, "DDR3" }, + { SMBIOS_MD_TYPE_FBD2, "FBD2" }, + { SMBIOS_MD_TYPE_DDR4, "DDR4" }, + { SMBIOS_MD_TYPE_LPDDR, "LPDDR" }, + { SMBIOS_MD_TYPE_LPDDR2, "LPDDR2" }, + { SMBIOS_MD_TYPE_LPDDR3, "LPDDR3" }, + { SMBIOS_MD_TYPE_LPDDR4, "LPDDR4" }, + { SMBIOS_MD_TYPE_LNVD, "Logical non-volatile device" }, + { SMBIOS_MD_TYPE_HBM, "HBM" }, + { SMBIOS_MD_TYPE_HBM2, "HBM2" }, + { SMBIOS_MD_TYPE_DDR5, "DDR5" }, + { SMBIOS_MD_TYPE_LPDDR5, "LPDDR5" }, + { SMBIOS_MD_TYPE_HBM3, "HBM3" }, +}; + +static const struct str_lookup_table md_tech_strings[] = { + { SMBIOS_MD_TECH_OTHER, "Other" }, + { SMBIOS_MD_TECH_UNKNOWN, "Unknown" }, + { SMBIOS_MD_TECH_DRAM, "DRAM" }, + { SMBIOS_MD_TECH_NVDIMMN, "NVDIMM-N" }, + { SMBIOS_MD_TECH_NVDIMMF, "NVDIMM-F" }, + { SMBIOS_MD_TECH_NVDIMMP, "NVDIMM-P" }, + { SMBIOS_MD_TECH_OPTANE, "Intel Optane persistent memory" }, +}; + /** * smbios_get_string() - get SMBIOS string from table * @@ -557,6 +625,61 @@ static void smbios_print_type16(struct smbios_type16 *table) printf("\tExtended Maximum Capacity: 0x%016llx\n", table->ext_max_cap); } +static void smbios_print_type17(struct smbios_type17 *table) +{ + printf("Memory Device:\n"); + printf("\tPhysical Memory Array Handle: 0x%04x\n", + table->phy_mem_array_hdl); + printf("\tMemory Error Information Handle: 0x%04x\n", + table->mem_err_info_hdl); + printf("\tTotal Width: 0x%04x\n", table->total_width); + printf("\tData Width: 0x%04x\n", table->data_width); + printf("\tSize: 0x%04x\n", table->size); + smbios_print_lookup_str(md_form_factor_strings, table->form_factor, + ARRAY_SIZE(md_form_factor_strings), + "Form Factor"); + printf("\tDevice Set: 0x%04x\n", table->dev_set); + smbios_print_str("Device Locator", table, table->dev_locator); + smbios_print_str("Bank Locator", table, table->bank_locator); + smbios_print_lookup_str(md_type_strings, table->mem_type, + ARRAY_SIZE(md_type_strings), "Memory Type"); + printf("\tType Detail: 0x%04x\n", table->type_detail); + printf("\tSpeed: 0x%04x\n", table->speed); + smbios_print_str("Manufacturer", table, table->manufacturer); + smbios_print_str("Serial Number", table, table->serial_number); + smbios_print_str("Asset Tag", table, table->asset_tag); + smbios_print_str("Part Number", table, table->part_number); + printf("\tAttributes: 0x%04x\n", table->attributes); + printf("\tExtended Size: 0x%08x\n", table->ext_size); + printf("\tConfigured Memory Speed: 0x%04x\n", table->config_mem_speed); + printf("\tMinimum voltage: 0x%04x\n", table->min_voltage); + printf("\tMaximum voltage: 0x%04x\n", table->max_voltage); + printf("\tConfigured voltage: 0x%04x\n", table->config_voltage); + smbios_print_lookup_str(md_tech_strings, table->mem_tech, + ARRAY_SIZE(md_tech_strings), + "Memory Technology"); + printf("\tMemory Operating Mode Capability: 0x%04x\n", + table->mem_op_mode_cap); + smbios_print_str("Firmware Version", table, table->fw_ver); + printf("\tModule Manufacturer ID: 0x%04x\n", table->module_man_id); + printf("\tModule Product ID: 0x%04x\n", table->module_prod_id); + printf("\tMemory Subsystem Controller Manufacturer ID: 0x%04x\n", + table->mem_subsys_con_man_id); + printf("\tMemory Subsystem Controller Product ID: 0x%04x\n", + table->mem_subsys_con_prod_id); + printf("\tNon-volatile Size: 0x%016llx\n", table->nonvolatile_size); + printf("\tVolatile Size: 0x%016llx\n", table->volatile_size); + printf("\tCache Size: 0x%016llx\n", table->cache_size); + printf("\tLogical Size: 0x%016llx\n", table->logical_size); + printf("\tExtended Speed: 0x%04x\n", table->ext_speed); + printf("\tExtended Configured Memory Speed: 0x%04x\n", + table->ext_config_mem_speed); + printf("\tPMIC0 Manufacturer ID: 0x%04x\n", table->pmic0_man_id); + printf("\tPMIC0 Revision Number: 0x%04x\n", table->pmic0_rev_num); + printf("\tRCD Manufacturer ID: 0x%04x\n", table->rcd_man_id); + printf("\tRCD Revision Number: 0x%04x\n", table->rcd_rev_num); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -642,6 +765,9 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, case SMBIOS_PHYS_MEMORY_ARRAY: smbios_print_type16((struct smbios_type16 *)pos); break; + case SMBIOS_MEMORY_DEVICE: + smbios_print_type17((struct smbios_type17 *)pos); + break; case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; diff --git a/include/smbios.h b/include/smbios.h index 293d6795cf3..2deafea9aa1 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -327,6 +327,51 @@ struct __packed smbios_type16 { u64 ext_max_cap; char eos[SMBIOS_STRUCT_EOS_BYTES]; }; + +struct __packed smbios_type17 { + struct smbios_header hdr; + u16 phy_mem_array_hdl; + u16 mem_err_info_hdl; + u16 total_width; + u16 data_width; + u16 size; + u8 form_factor; + u8 dev_set; + u8 dev_locator; + u8 bank_locator; + u8 mem_type; + u16 type_detail; + u16 speed; + u8 manufacturer; + u8 serial_number; + u8 asset_tag; + u8 part_number; + u8 attributes; + u32 ext_size; + u16 config_mem_speed; + u16 min_voltage; + u16 max_voltage; + u16 config_voltage; + u8 mem_tech; + u16 mem_op_mode_cap; + u8 fw_ver; + u16 module_man_id; + u16 module_prod_id; + u16 mem_subsys_con_man_id; + u16 mem_subsys_con_prod_id; + u64 nonvolatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; + u32 ext_speed; + u32 ext_config_mem_speed; + u16 pmic0_man_id; + u16 pmic0_rev_num; + u16 rcd_man_id; + u16 rcd_rev_num; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index c6850a5d6f5..ce913f2f32a 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -309,4 +309,131 @@ #define SMBIOS_MA_ERRINFO_NONE 0xFFFE #define SMBIOS_MA_ERRINFO_NOERR 0xFFFF +/* Memory Device */ + +/* Size */ + +#define SMBIOS_MD_SIZE_UNKNOWN 0xFFFF +#define SMBIOS_MD_SIZE_EXT 0x7FFF + +/* Form Factor */ +#define SMBIOS_MD_FF_OTHER 1 +#define SMBIOS_MD_FF_UNKNOWN 2 +#define SMBIOS_MD_FF_SIMM 3 +#define SMBIOS_MD_FF_SIP 4 +#define SMBIOS_MD_FF_CHIP 5 +#define SMBIOS_MD_FF_DIP 6 +#define SMBIOS_MD_FF_ZIP 7 +#define SMBIOS_MD_FF_PROPCARD 8 +#define SMBIOS_MD_FF_DIMM 9 +#define SMBIOS_MD_FF_TSOP 10 +#define SMBIOS_MD_FF_ROC 11 +#define SMBIOS_MD_FF_RIMM 12 +#define SMBIOS_MD_FF_SODIMM 13 +#define SMBIOS_MD_FF_SRIMM 14 +#define SMBIOS_MD_FF_FBDIMM 15 +#define SMBIOS_MD_FF_DIE 16 + +/* Device set */ +#define SMBIOS_MD_DEVSET_NONE 0 +#define SMBIOS_MD_DEVSET_UNKNOWN 0xFF + +/* Speed */ +#define SMBIOS_MD_SPEED_UNKNOWN 0 +#define SMBIOS_MD_SPEED_EXT 0xFFFF + +/* Attributes */ +#define SMBIOS_MD_ATTR_RANK_UNKNOWN 0 + +/* Configured Memory Speed */ +#define SMBIOS_MD_CONFSPEED_UNKNOWN 0 +#define SMBIOS_MD_CONFSPEED_EXT 0xFFFF + +/* Voltage */ +#define SMBIOS_MD_VOLTAGE_UNKNOWN 0 + +/* Type */ +#define SMBIOS_MD_TYPE_OTHER 1 +#define SMBIOS_MD_TYPE_UNKNOWN 2 +#define SMBIOS_MD_TYPE_DRAM 3 +#define SMBIOS_MD_TYPE_EDRAM 4 +#define SMBIOS_MD_TYPE_VRAM 5 +#define SMBIOS_MD_TYPE_SRAM 6 +#define SMBIOS_MD_TYPE_RAM 7 +#define SMBIOS_MD_TYPE_ROM 8 +#define SMBIOS_MD_TYPE_FLASH 9 +#define SMBIOS_MD_TYPE_EEPROM 10 +#define SMBIOS_MD_TYPE_FEPROM 11 +#define SMBIOS_MD_TYPE_EPROM 12 +#define SMBIOS_MD_TYPE_CDRAM 13 +#define SMBIOS_MD_TYPE_3DRAM 14 +#define SMBIOS_MD_TYPE_SDRAM 15 +#define SMBIOS_MD_TYPE_SGRAM 16 +#define SMBIOS_MD_TYPE_RDRAM 17 +#define SMBIOS_MD_TYPE_DDR 18 +#define SMBIOS_MD_TYPE_DDR2 19 +#define SMBIOS_MD_TYPE_DDR2FBD 20 +#define SMBIOS_MD_TYPE_RSVD1 21 +#define SMBIOS_MD_TYPE_RSVD2 22 +#define SMBIOS_MD_TYPE_DSVD3 23 +#define SMBIOS_MD_TYPE_DDR3 24 +#define SMBIOS_MD_TYPE_FBD2 25 +#define SMBIOS_MD_TYPE_DDR4 26 +#define SMBIOS_MD_TYPE_LPDDR 27 +#define SMBIOS_MD_TYPE_LPDDR2 28 +#define SMBIOS_MD_TYPE_LPDDR3 29 +#define SMBIOS_MD_TYPE_LPDDR4 30 +#define SMBIOS_MD_TYPE_LNVD 31 +#define SMBIOS_MD_TYPE_HBM 32 +#define SMBIOS_MD_TYPE_HBM2 33 +#define SMBIOS_MD_TYPE_DDR5 34 +#define SMBIOS_MD_TYPE_LPDDR5 35 +#define SMBIOS_MD_TYPE_HBM3 36 + +/* Type Detail */ +#define SMBIOS_MD_TD_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_TD_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_TD_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_TD_FP 8 /* BIT(3) */ +#define SMBIOS_MD_TD_SC 0x10 /* BIT(4) */ +#define SMBIOS_MD_TD_PS 0x20 /* BIT(5) */ +#define SMBIOS_MD_TD_RAMBUS 0x40 /* BIT(6) */ +#define SMBIOS_MD_TD_SYNC 0x80 /* BIT(7) */ +#define SMBIOS_MD_TD_CMOS 0x100 /* BIT(8) */ +#define SMBIOS_MD_TD_EDO 0x200 /* BIT(9) */ +#define SMBIOS_MD_TD_WINDRAM 0x400 /* BIT(10) */ +#define SMBIOS_MD_TD_CACHEDRAM 0x800 /* BIT(11) */ +#define SMBIOS_MD_TD_NV 0x1000 /* BIT(12) */ +#define SMBIOS_MD_TD_RGSTD 0x2000 /* BIT(13) */ +#define SMBIOS_MD_TD_UNRGSTD 0x4000 /* BIT(14) */ +#define SMBIOS_MD_TD_LRDIMM 0x8000 /* BIT(15) */ + +/* Technology */ +#define SMBIOS_MD_TECH_OTHER 1 +#define SMBIOS_MD_TECH_UNKNOWN 2 +#define SMBIOS_MD_TECH_DRAM 3 +#define SMBIOS_MD_TECH_NVDIMMN 4 +#define SMBIOS_MD_TECH_NVDIMMF 5 +#define SMBIOS_MD_TECH_NVDIMMP 6 +#define SMBIOS_MD_TECH_OPTANE 7 + +/* Operating Mode Capability */ +#define SMBIOS_MD_OPMC_RSVD 1 /* BIT(0), set to 0 */ +#define SMBIOS_MD_OPMC_OTHER 2 /* BIT(1) */ +#define SMBIOS_MD_OPMC_UNKNOWN 4 /* BIT(2) */ +#define SMBIOS_MD_OPMC_VM 8 /* BIT(3) */ +#define SMBIOS_MD_OPMC_BYTEAPM 0x10 /* BIT(4) */ +#define SMBIOS_MD_OPMC_BLKAPM 0x20 /* BIT(5) */ +/* Bit 6:15 Reserved, set to 0 */ + +/* Non-volatile / Volatile / Cache / Logical portion Size */ +#define SMBIOS_MD_PORT_SIZE_NONE 0 +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_HI 0xFFFFFFFF +#define SMBIOS_MD_PORT_SIZE_UNKNOWN_LO 0xFFFFFFFF +#define SMBIOS_MS_PORT_SIZE_UNKNOWN 0xFFFFFFFFFFFFFFFF + +/* Error Information Handle */ +#define SMBIOS_MD_ERRINFO_NONE 0xFFFE +#define SMBIOS_MD_ERRINFO_NOERR 0xFFFF + #endif /* _SMBIOS_DEF_H_ */ diff --git a/lib/smbios.c b/lib/smbios.c index 27c9c975cf2..7c6ad63b1c7 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -135,6 +135,14 @@ typedef int (*smbios_write_subnode)(ulong *current, int handle, struct smbios_ctx *ctx, int idx, int type); +typedef int (*smbios_write_memnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type); + +typedef int (*smbios_write_memctrlnode)(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 base, u64 sz); + /** * Function prototype to write a specific type of SMBIOS structure * @@ -1432,6 +1440,373 @@ static int smbios_write_type16(ulong *current, int *handle, return len; } +static void smbios_pop_type17_general_si(struct smbios_ctx *ctx, + struct smbios_type17 *t) +{ + t->mem_err_info_hdl = + smbios_get_val_si(ctx, "memory-error-information-handle", + SYSID_NONE, SMBIOS_MD_ERRINFO_NONE); + t->total_width = smbios_get_val_si(ctx, "total-width", SYSID_NONE, 0); + t->data_width = smbios_get_val_si(ctx, "data-width", SYSID_NONE, 0); + t->form_factor = smbios_get_val_si(ctx, "form-factor", + SYSID_NONE, SMBIOS_MD_FF_UNKNOWN); + t->dev_set = smbios_get_val_si(ctx, "device-set", SYSID_NONE, + SMBIOS_MD_DEVSET_UNKNOWN); + t->dev_locator = smbios_add_prop_si(ctx, "device-locator", SYSID_NONE, + NULL); + t->bank_locator = smbios_add_prop_si(ctx, "bank-locator", SYSID_NONE, + NULL); + t->mem_type = smbios_get_val_si(ctx, "memory-type", + SYSID_NONE, SMBIOS_MD_TYPE_UNKNOWN); + t->type_detail = smbios_get_val_si(ctx, "type-detail", + SYSID_NONE, SMBIOS_MD_TD_UNKNOWN); + t->speed = smbios_get_val_si(ctx, "speed", SYSID_NONE, + SMBIOS_MD_SPEED_UNKNOWN); + t->manufacturer = smbios_add_prop_si(ctx, "manufacturer", SYSID_NONE, + NULL); + t->serial_number = smbios_add_prop_si(ctx, "serial-number", SYSID_NONE, + NULL); + t->asset_tag = smbios_add_prop_si(ctx, "asset-tag", SYSID_NONE, NULL); + t->part_number = smbios_add_prop_si(ctx, "part-number", SYSID_NONE, + NULL); + t->attributes = smbios_get_val_si(ctx, "attributes", SYSID_NONE, + SMBIOS_MD_ATTR_RANK_UNKNOWN); + t->config_mem_speed = smbios_get_val_si(ctx, "configured-memory-speed", + SYSID_NONE, + SMBIOS_MD_CONFSPEED_UNKNOWN); + t->min_voltage = smbios_get_val_si(ctx, "minimum-voltage", SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->max_voltage = smbios_get_val_si(ctx, "maximum-voltage", SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->config_voltage = smbios_get_val_si(ctx, "configured-voltage", + SYSID_NONE, + SMBIOS_MD_VOLTAGE_UNKNOWN); + t->mem_tech = smbios_get_val_si(ctx, "memory-technology", + SYSID_NONE, SMBIOS_MD_TECH_UNKNOWN); + t->mem_op_mode_cap = + smbios_get_val_si(ctx, "memory-operating-mode-capability", + SYSID_NONE, SMBIOS_MD_OPMC_UNKNOWN); + t->fw_ver = smbios_add_prop_si(ctx, "firmware-version", SYSID_NONE, + NULL); + t->module_man_id = smbios_get_val_si(ctx, "module-manufacturer-id", + SYSID_NONE, 0); + t->module_prod_id = smbios_get_val_si(ctx, "module-product-id", + SYSID_NONE, 0); + t->mem_subsys_con_man_id = + smbios_get_val_si(ctx, + "memory-subsystem-controller-manufacturer-id", + SYSID_NONE, 0); + t->mem_subsys_con_prod_id = + smbios_get_val_si(ctx, + "memory-subsystem-controller-product-id", + SYSID_NONE, 0); + t->nonvolatile_size = smbios_get_u64_si(ctx, "non-volatile-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->volatile_size = smbios_get_u64_si(ctx, "volatile-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->cache_size = smbios_get_u64_si(ctx, "cache-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->logical_size = smbios_get_u64_si(ctx, "logical-size", + SYSID_NONE, + SMBIOS_MS_PORT_SIZE_UNKNOWN); + t->ext_speed = smbios_get_val_si(ctx, "extended-speed", SYSID_NONE, 0); + t->ext_config_mem_speed = + smbios_get_val_si(ctx, "extended-configured-memory-speed", + SYSID_NONE, 0); + t->pmic0_man_id = smbios_get_val_si(ctx, "pmic0-manufacturer-id", + SYSID_NONE, 0); + t->pmic0_rev_num = smbios_get_val_si(ctx, "pmic0-revision-number", + SYSID_NONE, 0); + t->rcd_man_id = smbios_get_val_si(ctx, "rcd-manufacturer-id", + SYSID_NONE, 0); + t->rcd_rev_num = smbios_get_val_si(ctx, "rcd-revision-number", + SYSID_NONE, 0); +} + +static void +smbios_pop_type17_size_from_memory_node(ofnode node, struct smbios_type17 *t) +{ + const fdt32_t *reg; + int len; + u64 sz; + u32 size_mb; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return; + + /* Combine hi/lo for size (typically 64-bit) */ + sz = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + + /* Convert size to MB */ + size_mb = (u32)(sz >> 20); /* 1 MB = 2^20 */ + if (size_mb < SMBIOS_MD_SIZE_EXT) { + t->size = cpu_to_le16(size_mb); + t->ext_size = 0; + return; + } + + t->size = cpu_to_le16(SMBIOS_MD_SIZE_EXT); /* Signal extended used */ + t->ext_size = cpu_to_le32((u32)(sz >> 10)); /* In KB */ +} + +static void smbios_pop_type17_size_si(struct smbios_ctx *ctx, + struct smbios_type17 *t) +{ + t->size = smbios_get_val_si(ctx, "size", SYSID_NONE, + SMBIOS_MD_SIZE_UNKNOWN); + t->ext_size = smbios_get_val_si(ctx, "extended-size", SYSID_NONE, 0); +} + +static int +smbios_scan_memctrl_subnode(ulong *current, int *handle, struct smbios_ctx *ctx, + int idx, smbios_write_memctrlnode cb) +{ + int total_len = 0; + ofnode child; + int i = 0; + int hdl_base = *handle; + u64 base = 0; + + /* + * Enumerate all subnodes of 'memory-controller' that contain 'size' + * property and generate one instance for each. + */ + for (child = ofnode_first_subnode(ctx->node); ofnode_valid(child); + child = ofnode_next_subnode(child)) { + u64 sz = 0; + const fdt32_t *size; + int proplen; + + size = ofnode_read_prop(child, "size", &proplen); + if (!size || proplen < sizeof(fdt32_t) || + proplen % sizeof(fdt32_t)) + continue; + + /* 64-bit size: or 32-bit size */ + if (proplen >= sizeof(fdt32_t) * 2) + sz = ((u64)fdt32_to_cpu(size[0]) << 32) | + fdt32_to_cpu(size[1]); + else + sz = fdt32_to_cpu(size[0]); + + *handle = hdl_base + i; + total_len += cb(current, *handle, ctx, idx, base, sz); + base += sz; + i++; + } + + return total_len; +} + +static int +smbios_write_type17_from_memctrl_node(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 __maybe_unused base, u64 sz) +{ + struct smbios_type17 *t; + int len; + u8 *eos_addr; + u32 size_mb; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_DEVICE, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->phy_mem_array_hdl = *((u16 *)hdl + idx); + + /* Convert to MB */ + size_mb = (u32)(sz >> 20); + if (size_mb < SMBIOS_MD_SIZE_EXT) { + /* Use 16-bit size field */ + t->size = cpu_to_le16(size_mb); /* In MB */ + t->ext_size = cpu_to_le32(0); + } else { + /* Signal use of extended size field */ + t->size = cpu_to_le16(SMBIOS_MD_SIZE_EXT); + t->ext_size = cpu_to_le32((u32)(sz >> 10)); /* In KB */ + } + + /* Write other general fields */ + smbios_pop_type17_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type17_mem(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type17 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_DEVICE, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) { + smbios_pop_type17_size_si(ctx, t); + + t->phy_mem_array_hdl = + smbios_get_val_si(ctx, "physical-memory-array-handle", + SYSID_NONE, 0); + } else if (type == SMBIOS_MEM_FDT_MEM_NODE) { + smbios_pop_type17_size_from_memory_node(ctx->node, t); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->phy_mem_array_hdl = *((u16 *)hdl + idx); + } + + /* Write other general fields */ + smbios_pop_type17_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_scan_mem_nodes(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memnode mem_cb, + int *idx) +{ + int len = 0; + struct smbios_ctx ctx_bak; + ofnode child; + int hdl_base = *handle; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *str; + + /* Look up for 'device_type = "memory"' */ + str = ofnode_read_string(child, "device_type"); + if (!str || strcmp(str, "memory")) + continue; + + ctx->node = child; + *handle = hdl_base + *idx; + /* Generate one instance for each 'memory' node */ + len += mem_cb(current, *handle, ctx, *idx, + SMBIOS_MEM_FDT_MEM_NODE); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + (*idx)++; + } + + return len; +} + +static int smbios_scan_mctrl_subnodes(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memctrlnode mctrl_wcb, + int *idx) +{ + int len = 0; + struct smbios_ctx ctx_bak; + ofnode child; + + memcpy(&ctx_bak, ctx, sizeof(ctx_bak)); + + for (child = ofnode_first_subnode(ofnode_root()); + ofnode_valid(child); child = ofnode_next_subnode(child)) { + const char *compat; + const char *name; + + /* + * Look up for node with name or property 'compatible' + * containing 'memory-controller'. + */ + name = ofnode_get_name(child); + compat = ofnode_read_string(child, "compatible"); + if ((!compat || !strstr(compat, "memory-controller")) && + (!name || !strstr(name, "memory-controller"))) + continue; + + (*handle)++; + ctx->node = child; + /* + * Generate one instance for each subnode of + * 'memory-controller' which contains property 'size'. + */ + len += smbios_scan_memctrl_subnode(current, handle, ctx, + *idx, mctrl_wcb); + memcpy(ctx, &ctx_bak, sizeof(*ctx)); + (*idx)++; + } + return len; +} + +static int smbios_write_type1719(ulong *current, int *handle, + struct smbios_ctx *ctx, + smbios_write_memnode mem_cb, + smbios_write_memctrlnode mctrl_wcb) +{ + int len = 0; + int idx; + + if (!IS_ENABLED(CONFIG_OF_CONTROL)) + return 0; /* Error, return 0-length */ + + /* Step 1: Scan any subnode exists */ + len = smbios_scan_subnodes(current, ctx, handle, mem_cb, + SMBIOS_MEM_CUSTOM); + if (len) + return len; + + /* Step 2: Scan 'memory' node from the entire FDT */ + idx = 0; + len += smbios_scan_mem_nodes(current, handle, ctx, mem_cb, &idx); + + /* Step 3: Scan 'memory-controller' node from the entire FDT */ + len += smbios_scan_mctrl_subnodes(current, handle, ctx, mctrl_wcb, &idx); + + return len; +} + +static int smbios_write_type17(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + return smbios_write_type1719(current, handle, ctx, + smbios_write_type17_mem, + smbios_write_type17_from_memctrl_node); +} + #endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ static int smbios_write_type32(ulong *current, int *handle, @@ -1481,6 +1856,7 @@ static struct smbios_write_method smbios_write_funcs[] = { #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) { smbios_write_type9, "system-slot"}, { smbios_write_type16, "memory-array"}, + { smbios_write_type17, "memory-device"}, #endif { smbios_write_type32, }, { smbios_write_type127 }, -- cgit v1.3.1 From 41b7a09d24d878f748eba87ae85575043224148b Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 13 Feb 2026 17:52:50 -0500 Subject: smbios: add support for dynamic generation of Type 19 table This commit implements SMBIOS Type 19 (Memory Array Mapped Address) generation with a hybrid approach supporting both: 1. Explicit definition via Device Tree 'smbios' node: Child node under '/smbios/smbios/memory-array-mapped-address' will be used to populate as individual Type 19 structure directly. - Properties follow SMBIOS field names with lowercase letters and hyphen-separated words (e.g., 'starting-address', 'ending-address', 'partition-width', etc.). - This method supports precise platform-defined overrides and system descriptions. 2. Fallback to automatic DT-based discovery: If child node under '/smbios/smbios/memory-array-mapped-address' does not exist, the implementation will: - Scan all top-level 'memory@' nodes to populate Type 19 structure with inferred size and location data. - Scan nodes named or marked as 'memory-controller' and parse associated 'dimm@' subnodes (if present) to extract DIMM sizes and map them accordingly. This dual-mode support enables flexible firmware SMBIOS reporting while aligning with spec-compliant naming and runtime-detected memory topology. Type 19 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid increasing rom size for those platforms which only require basic SMBIOS support. Signed-off-by: Raymond Mao Tested-by: Ilias Apalodimas --- arch/arm/dts/smbios_generic.dtsi | 3 + cmd/smbios.c | 14 ++++ include/smbios.h | 11 +++ include/smbios_def.h | 5 ++ lib/smbios.c | 150 +++++++++++++++++++++++++++++++++++++++ 5 files changed, 183 insertions(+) (limited to 'include') diff --git a/arch/arm/dts/smbios_generic.dtsi b/arch/arm/dts/smbios_generic.dtsi index fd2df8d02e0..fe16037fc20 100644 --- a/arch/arm/dts/smbios_generic.dtsi +++ b/arch/arm/dts/smbios_generic.dtsi @@ -86,6 +86,9 @@ memory-device { }; + + memory-array-mapped-address { + }; }; }; }; diff --git a/cmd/smbios.c b/cmd/smbios.c index 39c9c44a28e..671c14e05b5 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -680,6 +680,17 @@ static void smbios_print_type17(struct smbios_type17 *table) printf("\tRCD Revision Number: 0x%04x\n", table->rcd_rev_num); } +static void smbios_print_type19(struct smbios_type19 *table) +{ + printf("Memory Array Mapped Address:\n"); + printf("\tStarting Address: 0x%08x\n", table->start_addr); + printf("\tEnding Address: 0x%08x\n", table->end_addr); + printf("\tMemory Array Handle: 0x%04x\n", table->mem_array_hdl); + printf("\tPartition Width: 0x%04x\n", table->partition_wid); + printf("\tExtended Starting Address: 0x%016llx\n", table->ext_start_addr); + printf("\tExtended Ending Address: 0x%016llx\n", table->ext_end_addr); +} + static void smbios_print_type127(struct smbios_type127 *table) { printf("End Of Table\n"); @@ -768,6 +779,9 @@ static int do_smbios(struct cmd_tbl *cmdtp, int flag, int argc, case SMBIOS_MEMORY_DEVICE: smbios_print_type17((struct smbios_type17 *)pos); break; + case SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS: + smbios_print_type19((struct smbios_type19 *)pos); + break; case SMBIOS_END_OF_TABLE: smbios_print_type127((struct smbios_type127 *)pos); break; diff --git a/include/smbios.h b/include/smbios.h index 2deafea9aa1..e4b5ff314d9 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -372,6 +372,17 @@ struct __packed smbios_type17 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +struct __packed smbios_type19 { + struct smbios_header hdr; + u32 start_addr; + u32 end_addr; + u16 mem_array_hdl; + u8 partition_wid; + u64 ext_start_addr; + u64 ext_end_addr; + char eos[SMBIOS_STRUCT_EOS_BYTES]; +}; + struct __packed smbios_type32 { u8 type; u8 length; diff --git a/include/smbios_def.h b/include/smbios_def.h index ce913f2f32a..ae50e1a808e 100644 --- a/include/smbios_def.h +++ b/include/smbios_def.h @@ -436,4 +436,9 @@ #define SMBIOS_MD_ERRINFO_NONE 0xFFFE #define SMBIOS_MD_ERRINFO_NOERR 0xFFFF +/* Memory Array Mapped Address */ + +/* Partition Width */ +#define SMBIOS_MAMA_PW_DEF 1 /* not partitioned */ + #endif /* _SMBIOS_DEF_H_ */ diff --git a/lib/smbios.c b/lib/smbios.c index 7c6ad63b1c7..d5f18c8bd69 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -1807,6 +1807,155 @@ static int smbios_write_type17(ulong *current, int *handle, smbios_write_type17_from_memctrl_node); } +static void smbios_pop_type19_general_si(struct smbios_ctx *ctx, + struct smbios_type19 *t) +{ + t->partition_wid = + smbios_get_val_si(ctx, "partition-width ", + SYSID_NONE, SMBIOS_MAMA_PW_DEF); +} + +static void smbios_pop_type19_addr_si(struct smbios_ctx *ctx, + struct smbios_type19 *t) +{ + t->start_addr = smbios_get_val_si(ctx, "starting-address", SYSID_NONE, + 0); + t->end_addr = smbios_get_val_si(ctx, "ending-address", SYSID_NONE, 0); + t->ext_start_addr = smbios_get_u64_si(ctx, "extended-starting-address", + SYSID_NONE, 0); + t->ext_end_addr = smbios_get_u64_si(ctx, "extended-ending-address", + SYSID_NONE, 0); +} + +static void +smbios_pop_type19_addr_from_memory_node(ofnode node, struct smbios_type19 *t) +{ + const fdt32_t *reg; + int len; + u64 sz; + u64 addr; + + /* Read property 'reg' from the node */ + reg = ofnode_read_prop(node, "reg", &len); + if (!reg || len < sizeof(fdt32_t) * 4 || len % sizeof(fdt32_t)) + return; + + /* Combine hi/lo for size and address (typically 64-bit) */ + sz = ((u64)fdt32_to_cpu(reg[2]) << 32) | fdt32_to_cpu(reg[3]); + addr = ((u64)fdt32_to_cpu(reg[0]) << 32) | fdt32_to_cpu(reg[1]); + + t->ext_start_addr = cpu_to_le64(addr); + t->ext_end_addr = cpu_to_le64(addr + sz - 1); + + /* If address range fits in 32-bit, populate legacy fields */ + if ((addr + sz - 1) <= 0xFFFFFFFFULL) { + t->start_addr = cpu_to_le32((u32)addr); + t->end_addr = cpu_to_le32((u32)(addr + sz - 1)); + } else { + t->start_addr = cpu_to_le32(0xFFFFFFFF); + t->end_addr = cpu_to_le32(0xFFFFFFFF); + } +} + +static int +smbios_write_type19_from_memctrl_node(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + u64 base, u64 sz) +{ + struct smbios_type19 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->mem_array_hdl = *((u16 *)hdl + idx); + + t->ext_start_addr = cpu_to_le64(base); + t->ext_end_addr = cpu_to_le64(base + sz - 1); + + if ((base + sz - 1) <= 0xFFFFFFFFULL) { + t->start_addr = cpu_to_le32((u32)base); + t->end_addr = cpu_to_le32((u32)(base + sz - 1)); + } else { + t->start_addr = cpu_to_le32(0xFFFFFFFF); + t->end_addr = cpu_to_le32(0xFFFFFFFF); + } + + /* Write other general fields */ + smbios_pop_type19_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type19_mem(ulong *current, int handle, + struct smbios_ctx *ctx, int idx, + int type) +{ + struct smbios_type19 *t; + int len; + u8 *eos_addr; + void *hdl; + size_t hdl_size; + + len = sizeof(*t); + t = map_sysmem(*current, len); + memset(t, 0, len); + + fill_smbios_header(t, SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, len, handle); + + /* eos is at the end of the structure */ + eos_addr = (u8 *)t + len - sizeof(t->eos); + smbios_set_eos(ctx, eos_addr); + + if (type == SMBIOS_MEM_CUSTOM) { + smbios_pop_type19_addr_si(ctx, t); + t->mem_array_hdl = smbios_get_val_si(ctx, "memory-array-handle", + SYSID_NONE, 0); + } else if (type == SMBIOS_MEM_FDT_MEM_NODE) { + smbios_pop_type19_addr_from_memory_node(ctx->node, t); + /* Read the memory array handles */ + if (!sysinfo_get_data(ctx->dev, SYSID_SM_MEMARRAY_HANDLE, &hdl, + &hdl_size) && + hdl_size == SYSINFO_MEM_HANDLE_MAX * sizeof(u16)) + t->mem_array_hdl = *((u16 *)hdl + idx); + } + + /* Write other general fields */ + smbios_pop_type19_general_si(ctx, t); + + len = t->hdr.length + smbios_string_table_len(ctx); + *current += len; + unmap_sysmem(t); + + return len; +} + +static int smbios_write_type19(ulong *current, int *handle, + struct smbios_ctx *ctx) +{ + return smbios_write_type1719(current, handle, ctx, + smbios_write_type19_mem, + smbios_write_type19_from_memctrl_node); +} + #endif /* #if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLE_VERBOSE) */ static int smbios_write_type32(ulong *current, int *handle, @@ -1857,6 +2006,7 @@ static struct smbios_write_method smbios_write_funcs[] = { { smbios_write_type9, "system-slot"}, { smbios_write_type16, "memory-array"}, { smbios_write_type17, "memory-device"}, + { smbios_write_type19, "memory-array-mapped-address"}, #endif { smbios_write_type32, }, { smbios_write_type127 }, -- cgit v1.3.1 From 4c816ddbadb1bd8bfe09a457538d4f518151fd6d Mon Sep 17 00:00:00 2001 From: Raymond Mao Date: Fri, 13 Feb 2026 17:52:51 -0500 Subject: smbios: print the properties only when they exist in a specified version of spec By checking the payload length, we can know the version of the spec and skip the ones which are not expected to exist. Signed-off-by: Raymond Mao Tested-by: Ilias Apalodimas --- cmd/smbios.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++---------- include/smbios.h | 32 ++++++++++++++++++++++++++++ 2 files changed, 86 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/cmd/smbios.c b/cmd/smbios.c index 671c14e05b5..3fafa46d0a5 100644 --- a/cmd/smbios.c +++ b/cmd/smbios.c @@ -348,6 +348,8 @@ static void smbios_print_type0(struct smbios_type0 *table) printf("\tBIOS ROM Size: 0x%02x\n", table->bios_rom_size); printf("\tBIOS Characteristics: 0x%016llx\n", table->bios_characteristics); + if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V24) + return; printf("\tBIOS Characteristics Extension Byte 1: 0x%02x\n", table->bios_characteristics_ext1); printf("\tBIOS Characteristics Extension Byte 2: 0x%02x\n", @@ -360,6 +362,8 @@ static void smbios_print_type0(struct smbios_type0 *table) table->ec_major_release); printf("\tEmbedded Controller Firmware Minor Release: 0x%02x\n", table->ec_minor_release); + if (table->hdr.length < SMBIOS_TYPE0_LENGTH_V31) + return; printf("\tExtended BIOS ROM Size: 0x%04x\n", table->extended_bios_rom_size); } @@ -371,17 +375,16 @@ static void smbios_print_type1(struct smbios_type1 *table) smbios_print_str("Product Name", table, table->product_name); smbios_print_str("Version", table, table->version); smbios_print_str("Serial Number", table, table->serial_number); - if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V21) { - printf("\tUUID: %pUl\n", table->uuid); - smbios_print_lookup_str(wakeup_type_strings, - table->wakeup_type, - ARRAY_SIZE(wakeup_type_strings), - "Wake-up Type"); - } - if (table->hdr.length >= SMBIOS_TYPE1_LENGTH_V24) { - smbios_print_str("SKU Number", table, table->sku_number); - smbios_print_str("Family", table, table->family); - } + if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V21) + return; + printf("\tUUID: %pUl\n", table->uuid); + smbios_print_lookup_str(wakeup_type_strings, table->wakeup_type, + ARRAY_SIZE(wakeup_type_strings), + "Wake-up Type"); + if (table->hdr.length < SMBIOS_TYPE1_LENGTH_V24) + return; + smbios_print_str("SKU Number", table, table->sku_number); + smbios_print_str("Family", table, table->family); } static void smbios_print_type2(struct smbios_type2 *table) @@ -501,21 +504,31 @@ static void smbios_print_type4(struct smbios_type4 *table) printf("\tL1 Cache Handle: 0x%04x\n", table->l1_cache_handle); printf("\tL2 Cache Handle: 0x%04x\n", table->l2_cache_handle); printf("\tL3 Cache Handle: 0x%04x\n", table->l3_cache_handle); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V23) + return; smbios_print_str("Serial Number", table, table->serial_number); smbios_print_str("Asset Tag", table, table->asset_tag); smbios_print_str("Part Number", table, table->part_number); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V25) + return; printf("\tCore Count: 0x%02x\n", table->core_count); printf("\tCore Enabled: 0x%02x\n", table->core_enabled); printf("\tThread Count: 0x%02x\n", table->thread_count); printf("\tProcessor Characteristics: 0x%04x\n", table->processor_characteristics); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V26) + return; smbios_print_lookup_str(processor_family_strings, table->processor_family2, ARRAY_SIZE(processor_family_strings), "Processor Family 2"); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V30) + return; printf("\tCore Count 2: 0x%04x\n", table->core_count2); printf("\tCore Enabled 2: 0x%04x\n", table->core_enabled2); printf("\tThread Count 2: 0x%04x\n", table->thread_count2); + if (table->hdr.length < SMBIOS_TYPE4_LENGTH_V36) + return; printf("\tThread Enabled: 0x%04x\n", table->thread_enabled); } @@ -529,6 +542,8 @@ static void smbios_print_type7(struct smbios_type7 *table) printf("\tInstalled Size: 0x%04x\n", table->inst_size.data); printf("\tSupported SRAM Type: 0x%04x\n", table->supp_sram_type.data); printf("\tCurrent SRAM Type: 0x%04x\n", table->curr_sram_type.data); + if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V21) + return; printf("\tCache Speed: 0x%02x\n", table->speed); smbios_print_lookup_str(err_corr_type_strings, table->err_corr_type, @@ -542,6 +557,8 @@ static void smbios_print_type7(struct smbios_type7 *table) table->associativity, ARRAY_SIZE(associativity_strings), "Associativity"); + if (table->hdr.length < SMBIOS_TYPE7_LENGTH_V31) + return; printf("\tMaximum Cache Size 2: 0x%08x\n", table->max_size2.data); printf("\tInstalled Cache Size 2: 0x%08x\n", table->inst_size2.data); } @@ -574,8 +591,12 @@ static void smbios_print_type9(struct smbios_type9 *table) printf("\tSlot ID: 0x%04x\n", table->slot_id); printf("\tSlot Characteristics 1: 0x%04x\n", table->slot_characteristics_1); + if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V21) + return; printf("\tSlot Characteristics 2: 0x%04x\n", table->slot_characteristics_2); + if (table->hdr.length < SMBIOS_TYPE9_LENGTH_V26) + return; printf("\tSegment Group Number (Base): 0x%04x\n", table->segment_group_number); printf("\tBus Number (Base): 0x%04x\n", table->bus_number); @@ -611,6 +632,8 @@ static void smbios_print_type9(struct smbios_type9 *table) static void smbios_print_type16(struct smbios_type16 *table) { printf("Physical Memory Array:\n"); + if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V21) + return; smbios_print_lookup_str(ma_location_strings, table->location, ARRAY_SIZE(ma_location_strings), "Location"); smbios_print_lookup_str(ma_use_strings, table->use, @@ -622,12 +645,16 @@ static void smbios_print_type16(struct smbios_type16 *table) printf("\tMemory Error Information Handle: 0x%04x\n", table->mem_err_info_hdl); printf("\tNumber of Memory Devices: 0x%04x\n", table->num_of_mem_dev); + if (table->hdr.length < SMBIOS_TYPE16_LENGTH_V27) + return; printf("\tExtended Maximum Capacity: 0x%016llx\n", table->ext_max_cap); } static void smbios_print_type17(struct smbios_type17 *table) { printf("Memory Device:\n"); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V21) + return; printf("\tPhysical Memory Array Handle: 0x%04x\n", table->phy_mem_array_hdl); printf("\tMemory Error Information Handle: 0x%04x\n", @@ -644,17 +671,27 @@ static void smbios_print_type17(struct smbios_type17 *table) smbios_print_lookup_str(md_type_strings, table->mem_type, ARRAY_SIZE(md_type_strings), "Memory Type"); printf("\tType Detail: 0x%04x\n", table->type_detail); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V23) + return; printf("\tSpeed: 0x%04x\n", table->speed); smbios_print_str("Manufacturer", table, table->manufacturer); smbios_print_str("Serial Number", table, table->serial_number); smbios_print_str("Asset Tag", table, table->asset_tag); smbios_print_str("Part Number", table, table->part_number); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V26) + return; printf("\tAttributes: 0x%04x\n", table->attributes); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V27) + return; printf("\tExtended Size: 0x%08x\n", table->ext_size); printf("\tConfigured Memory Speed: 0x%04x\n", table->config_mem_speed); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V28) + return; printf("\tMinimum voltage: 0x%04x\n", table->min_voltage); printf("\tMaximum voltage: 0x%04x\n", table->max_voltage); printf("\tConfigured voltage: 0x%04x\n", table->config_voltage); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V32) + return; smbios_print_lookup_str(md_tech_strings, table->mem_tech, ARRAY_SIZE(md_tech_strings), "Memory Technology"); @@ -671,6 +708,8 @@ static void smbios_print_type17(struct smbios_type17 *table) printf("\tVolatile Size: 0x%016llx\n", table->volatile_size); printf("\tCache Size: 0x%016llx\n", table->cache_size); printf("\tLogical Size: 0x%016llx\n", table->logical_size); + if (table->hdr.length < SMBIOS_TYPE17_LENGTH_V33) + return; printf("\tExtended Speed: 0x%04x\n", table->ext_speed); printf("\tExtended Configured Memory Speed: 0x%04x\n", table->ext_config_mem_speed); @@ -683,10 +722,14 @@ static void smbios_print_type17(struct smbios_type17 *table) static void smbios_print_type19(struct smbios_type19 *table) { printf("Memory Array Mapped Address:\n"); + if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V21) + return; printf("\tStarting Address: 0x%08x\n", table->start_addr); printf("\tEnding Address: 0x%08x\n", table->end_addr); printf("\tMemory Array Handle: 0x%04x\n", table->mem_array_hdl); printf("\tPartition Width: 0x%04x\n", table->partition_wid); + if (table->hdr.length < SMBIOS_TYPE19_LENGTH_V27) + return; printf("\tExtended Starting Address: 0x%016llx\n", table->ext_start_addr); printf("\tExtended Ending Address: 0x%016llx\n", table->ext_end_addr); } diff --git a/include/smbios.h b/include/smbios.h index e4b5ff314d9..39090d3ba18 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -110,10 +110,42 @@ struct __packed smbios_type0 { char eos[SMBIOS_STRUCT_EOS_BYTES]; }; +#define SMBIOS_TYPE0_LENGTH_V24 0x18 +#define SMBIOS_TYPE0_LENGTH_V31 0x1a + #define SMBIOS_TYPE1_LENGTH_V20 0x08 #define SMBIOS_TYPE1_LENGTH_V21 0x19 #define SMBIOS_TYPE1_LENGTH_V24 0x1b +#define SMBIOS_TYPE4_LENGTH_V20 0x1a +#define SMBIOS_TYPE4_LENGTH_V23 0x23 +#define SMBIOS_TYPE4_LENGTH_V25 0x28 +#define SMBIOS_TYPE4_LENGTH_V26 0x2a +#define SMBIOS_TYPE4_LENGTH_V30 0x30 +#define SMBIOS_TYPE4_LENGTH_V36 0x32 + +#define SMBIOS_TYPE7_LENGTH_V20 0x0f +#define SMBIOS_TYPE7_LENGTH_V21 0x13 +#define SMBIOS_TYPE7_LENGTH_V31 0x1b + +#define SMBIOS_TYPE9_LENGTH_V20 0x0c +#define SMBIOS_TYPE9_LENGTH_V21 0x0d +#define SMBIOS_TYPE9_LENGTH_V26 0x11 + +#define SMBIOS_TYPE16_LENGTH_V21 0x0f +#define SMBIOS_TYPE16_LENGTH_V27 0x17 + +#define SMBIOS_TYPE17_LENGTH_V21 0x15 +#define SMBIOS_TYPE17_LENGTH_V23 0x1b +#define SMBIOS_TYPE17_LENGTH_V26 0x1c +#define SMBIOS_TYPE17_LENGTH_V27 0x22 +#define SMBIOS_TYPE17_LENGTH_V28 0x28 +#define SMBIOS_TYPE17_LENGTH_V32 0x54 +#define SMBIOS_TYPE17_LENGTH_V33 0x5c + +#define SMBIOS_TYPE19_LENGTH_V21 0x0f +#define SMBIOS_TYPE19_LENGTH_V27 0x1f + struct __packed smbios_type1 { struct smbios_header hdr; u8 manufacturer; -- cgit v1.3.1 From 27e1924ffaa9361542d4cf75a9b73613fa45d007 Mon Sep 17 00:00:00 2001 From: Niko Mauno Date: Wed, 4 Feb 2026 15:17:35 +0200 Subject: bootcount: Use predefined count/magic bit masks Use predefined bit masks in operations where only the magic half or only the count half of the 32-bit value are processed. Signed-off-by: Niko Mauno Reviewed-by: Tom Rini --- drivers/bootcount/bootcount.c | 12 ++++++------ drivers/bootcount/bootcount_at91.c | 7 ++++--- drivers/bootcount/bootcount_davinci.c | 6 +++--- include/bootcount.h | 5 +++++ 4 files changed, 18 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/drivers/bootcount/bootcount.c b/drivers/bootcount/bootcount.c index 343b8a34414..454e50591df 100644 --- a/drivers/bootcount/bootcount.c +++ b/drivers/bootcount/bootcount.c @@ -19,7 +19,7 @@ __weak void bootcount_store(ulong a) uintptr_t flush_end; #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) - raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | a); + raw_bootcount_store(reg, (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | a); flush_end = roundup(CONFIG_SYS_BOOTCOUNT_ADDR + 4, CONFIG_SYS_CACHELINE_SIZE); @@ -40,10 +40,10 @@ __weak ulong bootcount_load(void) #if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return (tmp & 0x0000ffff); + return (tmp & BOOTCOUNT_COUNT_MASK); #else if (raw_bootcount_load(reg + 4) != CONFIG_SYS_BOOTCOUNT_MAGIC) return 0; @@ -74,10 +74,10 @@ static int bootcount_mem_get(struct udevice *dev, u32 *a) if (priv->singleword) { u32 tmp = raw_bootcount_load(reg); - if ((tmp & 0xffff0000) != (magic & 0xffff0000)) + if ((tmp & BOOTCOUNT_MAGIC_MASK) != (magic & BOOTCOUNT_MAGIC_MASK)) return -ENODEV; - *a = (tmp & 0x0000ffff); + *a = (tmp & BOOTCOUNT_COUNT_MASK); } else { if (raw_bootcount_load(reg + 4) != magic) return -ENODEV; @@ -98,7 +98,7 @@ static int bootcount_mem_set(struct udevice *dev, const u32 a) uintptr_t flush_end; if (priv->singleword) { - raw_bootcount_store(reg, (magic & 0xffff0000) | a); + raw_bootcount_store(reg, (magic & BOOTCOUNT_MAGIC_MASK) | a); flush_end = roundup(priv->base + 4, CONFIG_SYS_CACHELINE_SIZE); } else { diff --git a/drivers/bootcount/bootcount_at91.c b/drivers/bootcount/bootcount_at91.c index 1a06db1fb74..1322abe921e 100644 --- a/drivers/bootcount/bootcount_at91.c +++ b/drivers/bootcount/bootcount_at91.c @@ -3,6 +3,7 @@ #include #include #include +#include /* * We combine the CONFIG_SYS_BOOTCOUNT_MAGIC and bootcount in one 32-bit @@ -13,7 +14,7 @@ void bootcount_store(ulong a) { at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; - writel((CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff), + writel((CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK), &gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); } @@ -22,8 +23,8 @@ ulong bootcount_load(void) at91_gpbr_t *gpbr = (at91_gpbr_t *) ATMEL_BASE_GPBR; ulong val = readl(&gpbr->reg[AT91_GPBR_INDEX_BOOTCOUNT]); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c index 6326957d7b0..a03d160a4cd 100644 --- a/drivers/bootcount/bootcount_davinci.c +++ b/drivers/bootcount/bootcount_davinci.c @@ -24,7 +24,7 @@ void bootcount_store(ulong a) writel(RTC_KICK0R_WE, ®->kick0r); writel(RTC_KICK1R_WE, ®->kick1r); raw_bootcount_store(®->scratch2, - (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); + (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK) | (a & BOOTCOUNT_COUNT_MASK)); } ulong bootcount_load(void) @@ -34,8 +34,8 @@ ulong bootcount_load(void) (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; val = raw_bootcount_load(®->scratch2); - if ((val & 0xffff0000) != (CONFIG_SYS_BOOTCOUNT_MAGIC & 0xffff0000)) + if ((val & BOOTCOUNT_MAGIC_MASK) != (CONFIG_SYS_BOOTCOUNT_MAGIC & BOOTCOUNT_MAGIC_MASK)) return 0; else - return val & 0x0000ffff; + return val & BOOTCOUNT_COUNT_MASK; } diff --git a/include/bootcount.h b/include/bootcount.h index 847c0f02d98..86474569d36 100644 --- a/include/bootcount.h +++ b/include/bootcount.h @@ -10,6 +10,7 @@ #include #include #include +#include #ifdef CONFIG_DM_BOOTCOUNT @@ -59,6 +60,10 @@ int dm_bootcount_set(struct udevice *dev, u32 bootcount); #endif +/* Bit masks for magic and count parts in single word scheme */ +#define BOOTCOUNT_MAGIC_MASK GENMASK(31, 16) +#define BOOTCOUNT_COUNT_MASK GENMASK(15, 0) + /** bootcount_store() - store the current bootcount */ void bootcount_store(ulong); -- cgit v1.3.1 From 4267b414dca17ba0ec842072fd0f2fb21e35319f Mon Sep 17 00:00:00 2001 From: Julien Masson Date: Fri, 20 Feb 2026 13:33:03 -0600 Subject: power: regulator: add MediaTek MT6357 driver Add a driver for the power regulators of the MediaTek MT6357 PMIC chip. Signed-off-by: Julien Masson Co-developed-by: Macpaul Lin Signed-off-by: Macpaul Lin Signed-off-by: David Lechner Signed-off-by: Peng Fan --- MAINTAINERS | 2 + drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/mt6357_regulator.c | 512 +++++++++++++++++++++++++++++ include/power/mt6357.h | 159 +++++++++ 5 files changed, 683 insertions(+) create mode 100644 drivers/power/regulator/mt6357_regulator.c create mode 100644 include/power/mt6357.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index f8d4f6ee8b2..7e9697491ca 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -432,6 +432,7 @@ F: drivers/net/phy/mediatek/ F: drivers/phy/phy-mtk-* F: drivers/pinctrl/mediatek/ F: drivers/power/domain/mtk-power-domain.c +F: drivers/power/regulator/mt*.c F: drivers/pci/pcie_mediatek_gen3.c F: drivers/pci/pcie_mediatek.c F: drivers/pwm/pwm-mtk.c @@ -448,6 +449,7 @@ F: drivers/reset/reset-mediatek.c F: drivers/serial/serial_mtk.c F: include/dt-bindings/clock/mediatek,* F: include/dt-bindings/power/mediatek,* +F: include/power/mt*.h F: tools/mtk_image.c F: tools/mtk_image.h F: tools/mtk_nand_headers.c diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index bd9ccd26981..60f20213bad 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -521,3 +521,12 @@ config DM_REGULATOR_CPCAP REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP PMIC and implements get/set api for voltage and state. + +config DM_REGULATOR_MT6357 + bool "Enable driver for MediaTek MT6357 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6357 PMIC. + This driver supports the control of different power rails of device + through regulator interface. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index ee8f56ea3b9..72acea28859 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -47,3 +47,4 @@ obj-$(CONFIG_$(PHASE_)DM_REGULATOR_ANATOP) += anatop_regulator.o obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6357) += mt6357_regulator.o diff --git a/drivers/power/regulator/mt6357_regulator.c b/drivers/power/regulator/mt6357_regulator.c new file mode 100644 index 00000000000..533cc22b93a --- /dev/null +++ b/drivers/power/regulator/mt6357_regulator.c @@ -0,0 +1,512 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * MT6357 regulator driver + * + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson + */ + +#include +#include +#include +#include + +enum mt6357_regulator_type { + MT6357_REG_TYPE_RANGE, + MT6357_REG_TYPE_TABLE, + MT6357_REG_TYPE_FIXED, +}; + +struct mt6357_linear_range { + unsigned int min; + unsigned int min_sel; + unsigned int max_sel; + unsigned int step; +}; + +struct mt6357_regulator_desc { + const char *name; + const char *of_match; + enum mt6357_regulator_type type; + int id; + unsigned int n_voltages; + const unsigned int *volt_table; + const struct mt6357_linear_range *linear_ranges; + int n_linear_ranges; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; +}; + +struct mt6357_regulator_info { + struct mt6357_regulator_desc desc; + const u32 *index_table; + unsigned int n_table; + u32 vsel_shift; + u32 da_vsel_reg; + u32 da_vsel_mask; + u32 da_vsel_shift; +}; + +/* Initialize struct mt6357_linear_range for regulators */ +#define REGULATOR_LINEAR_RANGE(_min_uV, _min_sel, _max_sel, _step_uV) \ +{ \ + .min = _min_uV, \ + .min_sel = _min_sel, \ + .max_sel = _max_sel, \ + .step = _step_uV, \ +} + +#define MT6357_BUCK(match, vreg, min, max, step, \ + volt_ranges, vosel_reg, vosel_mask, _da_vsel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel_reg, \ + .vsel_mask = vosel_mask, \ + .enable_reg = MT6357_BUCK_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_BUCK_##vreg##_DBG0, \ + .da_vsel_mask = _da_vsel_mask, \ + .da_vsel_shift = 0, \ + } + +#define MT6357_LDO(match, vreg, ldo_volt_table, \ + ldo_index_table, enreg, vosel, \ + vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_TABLE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ARRAY_SIZE(ldo_volt_table), \ + .volt_table = ldo_volt_table, \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask << 8, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .index_table = ldo_index_table, \ + .n_table = ARRAY_SIZE(ldo_index_table), \ + } + +#define MT6357_LDO1(match, vreg, min, max, step, volt_ranges, \ + enreg, vosel, vosel_mask) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_RANGE, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = ((max) - (min)) / (step) + 1, \ + .linear_ranges = volt_ranges, \ + .n_linear_ranges = ARRAY_SIZE(volt_ranges), \ + .vsel_reg = vosel, \ + .vsel_mask = vosel_mask, \ + .enable_reg = enreg, \ + .enable_mask = BIT(0), \ + }, \ + .da_vsel_reg = MT6357_LDO_##vreg##_DBG0, \ + .da_vsel_mask = 0x7f, \ + .da_vsel_shift = 8, \ + } + +#define MT6357_REG_FIXED(match, vreg, volt) \ + [MT6357_ID_##vreg] = { \ + .desc = { \ + .name = #vreg, \ + .of_match = of_match_ptr(match), \ + .type = MT6357_REG_TYPE_FIXED, \ + .id = MT6357_ID_##vreg, \ + .n_voltages = 1, \ + .enable_reg = MT6357_LDO_##vreg##_CON0, \ + .enable_mask = BIT(0), \ + .min_uV = volt, \ + }, \ + } + +static int mt6357_range_find_value(const struct mt6357_linear_range *r, + unsigned int sel, + unsigned int *val) +{ + if (!val || sel < r->min_sel || sel > r->max_sel) + return -EINVAL; + + *val = r->min + r->step * (sel - r->min_sel); + + return 0; +} + +static int mt6357_range_find_selector(const struct mt6357_linear_range *r, + int val, unsigned int *sel) +{ + int num_vals = r->max_sel - r->min_sel + 1; + int ret = -EINVAL; + + if (val >= r->min && val <= r->min + r->step * (num_vals - 1)) { + if (r->step) { + *sel = r->min_sel + ((val - r->min) / r->step); + ret = 0; + } else { + *sel = r->min_sel; + ret = 0; + } + } + return ret; +} + +static int mt6357_get_enable(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6357_set_enable(struct udevice *dev, bool enable) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6357_get_value(struct udevice *dev) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + unsigned int val_uV; + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + selector = pmic_reg_read(dev->parent, info->da_vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->da_vsel_mask) >> info->da_vsel_shift; + ret = mt6357_range_find_value(info->desc.linear_ranges, selector, &val_uV); + if (ret < 0) + return ret; + + return val_uV; + case MT6357_REG_TYPE_TABLE: + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector = (selector & info->desc.vsel_mask) >> 8; + pvol = info->index_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == selector) + return info->desc.volt_table[idx]; + } + + return -EINVAL; + case MT6357_REG_TYPE_FIXED: + return info->desc.min_uV; + default: + return -EINVAL; + } +} + +static int mt6357_set_value(struct udevice *dev, int uvolt) +{ + struct mt6357_regulator_info *info = dev_get_priv(dev); + int selector, idx, ret; + const u32 *pvol; + + switch (info->desc.type) { + case MT6357_REG_TYPE_RANGE: + ret = mt6357_range_find_selector(info->desc.linear_ranges, uvolt, + &selector); + if (ret < 0) + return ret; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector); + case MT6357_REG_TYPE_TABLE: + pvol = info->desc.volt_table; + + for (idx = 0; idx < info->desc.n_voltages; idx++) { + if (pvol[idx] == uvolt) { + selector = info->index_table[idx]; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, selector << 8); + } + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static const int vxo22_voltages[] = { + 2200000, + 2400000, +}; + +static const int vefuse_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vcn33_voltages[] = { + 3300000, + 3400000, + 3500000, +}; + +static const int vcama_voltages[] = { + 2500000, + 2800000, +}; + +static const int vcamd_voltages[] = { + 1000000, + 1100000, + 1200000, + 1300000, + 1500000, + 1800000, +}; + +static const int vldo28_voltages[] = { + 2800000, + 3000000, +}; + +static const int vdram_voltages[] = { + 1100000, + 1200000, +}; + +static const int vsim_voltages[] = { + 1700000, + 1800000, + 2700000, + 3000000, + 3100000, +}; + +static const int vibr_voltages[] = { + 1200000, + 1300000, + 1500000, + 1800000, + 2000000, + 2800000, + 3000000, + 3300000, +}; + +static const int vmc_voltages[] = { + 1800000, + 2900000, + 3000000, + 3300000, +}; + +static const int vmch_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vemc_voltages[] = { + 2900000, + 3000000, + 3300000, +}; + +static const int vusb_voltages[] = { + 3000000, + 3100000, +}; + +static const int vmc_idx[] = { + 4, 10, 11, 13, +}; + +static const int vmch_idx[] = { + 2, 3, 5, +}; + +static const int vemc_idx[] = { + 2, 3, 5, +}; + +static const int vusb_idx[] = { + 3, 4, +}; + +static const int vxo22_idx[] = { + 0, 2, +}; + +static const int vefuse_idx[] = { + 0, 1, 2, 4, 9, 10, 11, 13, +}; + +static const int vcn33_idx[] = { + 1, 2, 3, +}; + +static const int vcama_idx[] = { + 7, 10, +}; + +static const int vcamd_idx[] = { + 4, 5, 6, 7, 9, 12, +}; + +static const int vldo28_idx[] = { + 1, 3, +}; + +static const int vdram_idx[] = { + 1, 2, +}; + +static const int vsim_idx[] = { + 3, 4, 8, 11, 12, +}; + +static const int vibr_idx[] = { + 0, 1, 2, 4, 5, 9, 11, 13, +}; + +static const struct mt6357_linear_range buck_volt_range1[] = { + REGULATOR_LINEAR_RANGE(518750, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range2[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250), +}; + +static const struct mt6357_linear_range buck_volt_range3[] = { + REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000), +}; + +static const struct mt6357_linear_range buck_volt_range4[] = { + REGULATOR_LINEAR_RANGE(1200000, 0, 0x7f, 12500), +}; + +/* The array is indexed by id(MT6357_ID_XXX) */ +static struct mt6357_regulator_info mt6357_regulators[] = { + /* Bucks */ + MT6357_BUCK("buck-vcore", VCORE, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VCORE_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vproc", VPROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_BUCK_VPROC_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vmodem", VMODEM, 500000, 1293750, 6250, + buck_volt_range2, MT6357_BUCK_VMODEM_ELR0, 0x7f, 0x7f), + MT6357_BUCK("buck-vpa", VPA, 500000, 3650000, 50000, + buck_volt_range3, MT6357_BUCK_VPA_CON1, 0x3f, 0x3f), + MT6357_BUCK("buck-vs1", VS1, 1200000, 2787500, 12500, + buck_volt_range4, MT6357_BUCK_VS1_ELR0, 0x7f, 0x7f), + + /* LDOs */ + MT6357_LDO("ldo-vcama", VCAMA, vcama_voltages, vcama_idx, + MT6357_LDO_VCAMA_CON0, MT6357_VCAMA_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcamd", VCAMD, vcamd_voltages, vcamd_idx, + MT6357_LDO_VCAMD_CON0, MT6357_VCAMD_ANA_CON0, 0xf), + MT6357_LDO("ldo-vcn33-bt", VCN33_BT, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_0, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vcn33-wifi", VCN33_WIFI, vcn33_voltages, vcn33_idx, + MT6357_LDO_VCN33_CON0_1, MT6357_VCN33_ANA_CON0, 0x3), + MT6357_LDO("ldo-vdram", VDRAM, vdram_voltages, vdram_idx, + MT6357_LDO_VDRAM_CON0, MT6357_VDRAM_ELR_2, 0x3), + MT6357_LDO("ldo-vefuse", VEFUSE, vefuse_voltages, vefuse_idx, + MT6357_LDO_VEFUSE_CON0, MT6357_VEFUSE_ANA_CON0, 0xf), + MT6357_LDO("ldo-vemc", VEMC, vemc_voltages, vemc_idx, + MT6357_LDO_VEMC_CON0, MT6357_VEMC_ANA_CON0, 0x7), + MT6357_LDO("ldo-vibr", VIBR, vibr_voltages, vibr_idx, + MT6357_LDO_VIBR_CON0, MT6357_VIBR_ANA_CON0, 0xf), + MT6357_LDO("ldo-vldo28", VLDO28, vldo28_voltages, vldo28_idx, + MT6357_LDO_VLDO28_CON0_0, MT6357_VLDO28_ANA_CON0, 0x3), + MT6357_LDO("ldo-vmc", VMC, vmc_voltages, vmc_idx, + MT6357_LDO_VMC_CON0, MT6357_VMC_ANA_CON0, 0xf), + MT6357_LDO("ldo-vmch", VMCH, vmch_voltages, vmch_idx, + MT6357_LDO_VMCH_CON0, MT6357_VMCH_ANA_CON0, 0x7), + MT6357_LDO("ldo-vsim1", VSIM1, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM1_CON0, MT6357_VSIM1_ANA_CON0, 0xf), + MT6357_LDO("ldo-vsim2", VSIM2, vsim_voltages, vsim_idx, + MT6357_LDO_VSIM2_CON0, MT6357_VSIM2_ANA_CON0, 0xf), + MT6357_LDO("ldo-vusb33", VUSB33, vusb_voltages, vusb_idx, + MT6357_LDO_VUSB33_CON0_0, MT6357_VUSB33_ANA_CON0, 0x7), + MT6357_LDO("ldo-vxo22", VXO22, vxo22_voltages, vxo22_idx, + MT6357_LDO_VXO22_CON0, MT6357_VXO22_ANA_CON0, 0x3), + + MT6357_LDO1("ldo-vsram-proc", VSRAM_PROC, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_PROC_CON0, + MT6357_LDO_VSRAM_CON0, 0x7f), + MT6357_LDO1("ldo-vsram-others", VSRAM_OTHERS, 518750, 1312500, 6250, + buck_volt_range1, MT6357_LDO_VSRAM_OTHERS_CON0, + MT6357_LDO_VSRAM_CON1, 0x7f), + + MT6357_REG_FIXED("ldo-vaud28", VAUD28, 2800000), + MT6357_REG_FIXED("ldo-vaux18", VAUX18, 1800000), + MT6357_REG_FIXED("ldo-vcamio18", VCAMIO, 1800000), + MT6357_REG_FIXED("ldo-vcn18", VCN18, 1800000), + MT6357_REG_FIXED("ldo-vcn28", VCN28, 2800000), + MT6357_REG_FIXED("ldo-vfe28", VFE28, 2800000), + MT6357_REG_FIXED("ldo-vio18", VIO18, 1800000), + MT6357_REG_FIXED("ldo-vio28", VIO28, 2800000), + MT6357_REG_FIXED("ldo-vrf12", VRF12, 1200000), + MT6357_REG_FIXED("ldo-vrf18", VRF18, 1800000), +}; + +static int mt6357_regulator_probe(struct udevice *dev) +{ + struct mt6357_regulator_info *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < ARRAY_SIZE(mt6357_regulators); i++) { + if (!strcmp(dev->name, mt6357_regulators[i].desc.of_match)) { + *priv = mt6357_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6357_regulator_ops = { + .get_value = mt6357_get_value, + .set_value = mt6357_set_value, + .get_enable = mt6357_get_enable, + .set_enable = mt6357_set_enable, +}; + +U_BOOT_DRIVER(mt6357_regulator) = { + .name = MT6357_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6357_regulator_ops, + .probe = mt6357_regulator_probe, + .priv_auto = sizeof(struct mt6357_regulator_info), +}; diff --git a/include/power/mt6357.h b/include/power/mt6357.h new file mode 100644 index 00000000000..b7ee9d64386 --- /dev/null +++ b/include/power/mt6357.h @@ -0,0 +1,159 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2026 BayLibre, SAS. + * Author: Julien Masson + */ + +#ifndef _REGULATOR_MT6357_H_ +#define _REGULATOR_MT6357_H_ + +#define MT6357_REGULATOR_DRIVER "mt6357_regulator" + +enum { + /* Bucks */ + MT6357_ID_VCORE, + MT6357_ID_VMODEM, + MT6357_ID_VPA, + MT6357_ID_VPROC, + MT6357_ID_VS1, + + /* LDOs */ + MT6357_ID_VAUX18, + MT6357_ID_VAUD28, + MT6357_ID_VCAMA, + MT6357_ID_VCAMD, + MT6357_ID_VCAMIO, + MT6357_ID_VCN18, + MT6357_ID_VCN28, + MT6357_ID_VCN33_BT, + MT6357_ID_VCN33_WIFI, + MT6357_ID_VDRAM, + MT6357_ID_VEFUSE, + MT6357_ID_VEMC, + MT6357_ID_VFE28, + MT6357_ID_VIBR, + MT6357_ID_VIO18, + MT6357_ID_VIO28, + MT6357_ID_VLDO28, + MT6357_ID_VMC, + MT6357_ID_VMCH, + MT6357_ID_VRF12, + MT6357_ID_VRF18, + MT6357_ID_VSIM1, + MT6357_ID_VSIM2, + MT6357_ID_VSRAM_OTHERS, + MT6357_ID_VSRAM_PROC, + MT6357_ID_VUSB33, + MT6357_ID_VXO22, +}; + +/* PMIC Registers */ +#define MT6357_BUCK_TOP_CLK_CON0 0x140c +#define MT6357_BUCK_TOP_CLK_HWEN_CON0 0x1412 +#define MT6357_BUCK_TOP_CLK_MISC_CON0 0x1418 +#define MT6357_BUCK_TOP_INT_CON0 0x141a +#define MT6357_BUCK_TOP_INT_MASK_CON0 0x1420 +#define MT6357_BUCK_TOP_SLP_CON0 0x142c +#define MT6357_BUCK_TOP_OC_CON0 0x1434 +#define MT6357_BUCK_TOP_K_CON0 0x1436 +#define MT6357_BUCK_VPROC_CON0 0x1488 +#define MT6357_BUCK_VPROC_DBG0 0x14a2 +#define MT6357_BUCK_VPROC_ELR0 0x14aa +#define MT6357_BUCK_VCORE_CON0 0x1508 +#define MT6357_BUCK_VCORE_DBG0 0x1522 +#define MT6357_BUCK_VCORE_ELR0 0x152a +#define MT6357_BUCK_VMODEM_CON0 0x1588 +#define MT6357_BUCK_VMODEM_DBG0 0x15a2 +#define MT6357_BUCK_VMODEM_ELR0 0x15aa +#define MT6357_BUCK_VS1_CON0 0x1608 +#define MT6357_BUCK_VS1_DBG0 0x1622 +#define MT6357_BUCK_VS1_ELR0 0x1632 +#define MT6357_BUCK_VPA_CON0 0x1688 +#define MT6357_BUCK_VPA_CON1 0x168a +#define MT6357_BUCK_VPA_DBG0 0x1692 +#define MT6357_BUCK_VPA_DLC_CON0 0x1698 +#define MT6357_BUCK_VPA_MSFG_CON0 0x169e +#define MT6357_LDO_TOP_CLK_DCM_CON0 0x188c +#define MT6357_LDO_TOP_CLK_VIO28_CON0 0x188e +#define MT6357_LDO_TOP_CLK_VIO18_CON0 0x1890 +#define MT6357_LDO_TOP_CLK_VAUD28_CON0 0x1892 +#define MT6357_LDO_TOP_CLK_VDRAM_CON0 0x1894 +#define MT6357_LDO_TOP_CLK_VSRAM_PROC_CON0 0x1896 +#define MT6357_LDO_TOP_CLK_VSRAM_OTHERS_CON0 0x1898 +#define MT6357_LDO_TOP_CLK_VAUX18_CON0 0x189a +#define MT6357_LDO_TOP_CLK_VUSB33_CON0 0x189c +#define MT6357_LDO_TOP_CLK_VEMC_CON0 0x189e +#define MT6357_LDO_TOP_CLK_VXO22_CON0 0x18a0 +#define MT6357_LDO_TOP_CLK_VSIM1_CON0 0x18a2 +#define MT6357_LDO_TOP_CLK_VSIM2_CON0 0x18a4 +#define MT6357_LDO_TOP_CLK_VCAMD_CON0 0x18a6 +#define MT6357_LDO_TOP_CLK_VCAMIO_CON0 0x18a8 +#define MT6357_LDO_TOP_CLK_VEFUSE_CON0 0x18aa +#define MT6357_LDO_TOP_CLK_VCN33_CON0 0x18ac +#define MT6357_LDO_TOP_CLK_VCN18_CON0 0x18ae +#define MT6357_LDO_TOP_CLK_VCN28_CON0 0x18b0 +#define MT6357_LDO_TOP_CLK_VIBR_CON0 0x18b2 +#define MT6357_LDO_TOP_CLK_VFE28_CON0 0x18b4 +#define MT6357_LDO_TOP_CLK_VMCH_CON0 0x18b6 +#define MT6357_LDO_TOP_CLK_VMC_CON0 0x18b8 +#define MT6357_LDO_TOP_CLK_VRF18_CON0 0x18ba +#define MT6357_LDO_TOP_CLK_VLDO28_CON0 0x18bc +#define MT6357_LDO_TOP_CLK_VRF12_CON0 0x18be +#define MT6357_LDO_TOP_CLK_VCAMA_CON0 0x18c0 +#define MT6357_LDO_TOP_CLK_TREF_CON0 0x18c2 +#define MT6357_LDO_TOP_INT_CON0 0x18c4 +#define MT6357_LDO_TOP_INT_MASK_CON0 0x18d0 +#define MT6357_LDO_TEST_CON0 0x18e4 +#define MT6357_LDO_TOP_WDT_CON0 0x18e6 +#define MT6357_LDO_TOP_RSV_CON0 0x18e8 +#define MT6357_LDO_VXO22_CON0 0x1908 +#define MT6357_LDO_VAUX18_CON0 0x191c +#define MT6357_LDO_VAUD28_CON0 0x1930 +#define MT6357_LDO_VIO28_CON0 0x1944 +#define MT6357_LDO_VIO18_CON0 0x1958 +#define MT6357_LDO_VDRAM_CON0 0x196c +#define MT6357_LDO_VEMC_CON0 0x1988 +#define MT6357_LDO_VUSB33_CON0_0 0x199c +#define MT6357_LDO_VSRAM_PROC_CON0 0x19b2 +#define MT6357_LDO_VSRAM_PROC_DBG0 0x19cc +#define MT6357_LDO_VSRAM_OTHERS_CON0 0x19d0 +#define MT6357_LDO_VSRAM_OTHERS_DBG0 0x19ea +#define MT6357_LDO_VSRAM_WDT_DBG0 0x19f6 +#define MT6357_LDO_VSRAM_CON0 0x19fa +#define MT6357_LDO_VSRAM_CON1 0x19fc +#define MT6357_LDO_VFE28_CON0 0x1a08 +#define MT6357_LDO_VRF18_CON0 0x1a1c +#define MT6357_LDO_VRF12_CON0 0x1a30 +#define MT6357_LDO_VEFUSE_CON0 0x1a44 +#define MT6357_LDO_VCN18_CON0 0x1a58 +#define MT6357_LDO_VCAMA_CON0 0x1a6c +#define MT6357_LDO_VCAMD_CON0 0x1a88 +#define MT6357_LDO_VCAMIO_CON0 0x1a9c +#define MT6357_LDO_VMC_CON0 0x1ab0 +#define MT6357_LDO_VMCH_CON0 0x1ac4 +#define MT6357_LDO_VSIM1_CON0 0x1ad8 +#define MT6357_LDO_VSIM2_CON0 0x1aec +#define MT6357_LDO_VIBR_CON0 0x1b08 +#define MT6357_LDO_VCN33_CON0_0 0x1b1c +#define MT6357_LDO_VCN33_CON0_1 0x1b2a +#define MT6357_LDO_VLDO28_CON0_0 0x1b32 +#define MT6357_LDO_GOFF2_RSV_CON0 0x1b48 +#define MT6357_LDO_VCN28_CON0 0x1b88 +#define MT6357_LDO_TREF_CON0 0x1b9e +#define MT6357_LDO_GOFF3_RSV_CON0 0x1bae +#define MT6357_VXO22_ANA_CON0 0x1c18 +#define MT6357_VCN33_ANA_CON0 0x1c1c +#define MT6357_VEMC_ANA_CON0 0x1c20 +#define MT6357_VLDO28_ANA_CON0 0x1c24 +#define MT6357_VIBR_ANA_CON0 0x1c2c +#define MT6357_VSIM1_ANA_CON0 0x1c30 +#define MT6357_VSIM2_ANA_CON0 0x1c34 +#define MT6357_VMCH_ANA_CON0 0x1c38 +#define MT6357_VMC_ANA_CON0 0x1c3c +#define MT6357_VUSB33_ANA_CON0 0x1c88 +#define MT6357_VCAMA_ANA_CON0 0x1c8c +#define MT6357_VEFUSE_ANA_CON0 0x1c90 +#define MT6357_VCAMD_ANA_CON0 0x1c94 +#define MT6357_VDRAM_ELR_2 0x1cac + +#endif -- cgit v1.3.1 From 5419cf43cf085ff7541f299cf4db764d1adec021 Mon Sep 17 00:00:00 2001 From: Bo-Chen Chen Date: Fri, 20 Feb 2026 13:33:04 -0600 Subject: power: regulator: mt6359: add driver for MT6359P Add a new regulator driver for MT6359P and similar PMIC chips. The MT6359P is a eco version for MT6359 regulator. For the MT8391 platform, we use the MT6359P (MT6365) as the main PMIC. The MT6359 and MT6359P have different register maps. Therefore, on the MT8391 platform, we only provide support for the MT6359P. If support for the MT6359 PMIC it can be added later. Signed-off-by: Bo-Chen Chen Signed-off-by: David Lechner Signed-off-by: Peng Fan --- drivers/power/regulator/Kconfig | 9 + drivers/power/regulator/Makefile | 1 + drivers/power/regulator/mt6359_regulator.c | 711 +++++++++++++++++++++++++++++ include/power/mt6359.h | 225 +++++++++ include/power/mt6359p.h | 230 ++++++++++ 5 files changed, 1176 insertions(+) create mode 100644 drivers/power/regulator/mt6359_regulator.c create mode 100644 include/power/mt6359.h create mode 100644 include/power/mt6359p.h (limited to 'include') diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index 60f20213bad..2c982873a92 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -530,3 +530,12 @@ config DM_REGULATOR_MT6357 MediaTek MT6357 PMIC. This driver supports the control of different power rails of device through regulator interface. + +config DM_REGULATOR_MT6359 + bool "Enable driver for MediaTek MT6359 PMIC regulators" + depends on DM_REGULATOR && DM_PMIC_MTK_PWRAP + help + Say y here to select this option to enable the power regulator of + MediaTek MT6359 PMIC. + This driver supports the control of different power rails of device + through regulator interface. diff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile index 72acea28859..9e303d4f7f8 100644 --- a/drivers/power/regulator/Makefile +++ b/drivers/power/regulator/Makefile @@ -48,3 +48,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS65219) += tps65219_regulator.o obj-$(CONFIG_REGULATOR_RZG2L_USBPHY) += rzg2l-usbphy-regulator.o obj-$(CONFIG_$(PHASE_)DM_REGULATOR_CPCAP) += cpcap_regulator.o obj-$(CONFIG_DM_REGULATOR_MT6357) += mt6357_regulator.o +obj-$(CONFIG_DM_REGULATOR_MT6359) += mt6359_regulator.o diff --git a/drivers/power/regulator/mt6359_regulator.c b/drivers/power/regulator/mt6359_regulator.c new file mode 100644 index 00000000000..cdafcfcb25e --- /dev/null +++ b/drivers/power/regulator/mt6359_regulator.c @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +enum mt6359_regulator_type { + MT6359_REG_TYPE_LINEAR, + MT6359_REG_TYPE_TABLE, + MT6359_REG_TYPE_FIXED, + MT6359_REG_TYPE_VEMC, +}; + +struct regulator_desc { + const char *name; + const char *of_match; + enum mt6359_regulator_type type; + int id; + unsigned int uV_step; + unsigned int n_voltages; + const unsigned int *volt_table; + unsigned int min_uV; + unsigned int vsel_reg; + unsigned int vsel_mask; + unsigned int enable_reg; + unsigned int enable_mask; + unsigned int fixed_uV; +}; + +/* + * MT6359 regulators' information + * + * @desc: standard fields of regulator description. + * @status_reg: for query status of regulators. + * @qi: Mask for query enable signal status of regulators. + * @modeset_reg: for operating AUTO/PWM mode register. + * @modeset_mask: MASK for operating modeset register. + */ +struct mt6359_regulator_info { + struct regulator_desc desc; + u32 status_reg; + u32 qi; + u32 modeset_reg; + u32 modeset_mask; + u32 lp_mode_reg; + u32 lp_mode_mask; +}; + +#define MT6359_BUCK(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, \ + _vsel_reg, _vsel_mask, \ + _lp_mode_reg, _lp_mode_shift, \ + _modeset_reg, _modeset_shift) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ + .lp_mode_reg = _lp_mode_reg, \ + .lp_mode_mask = BIT(_lp_mode_shift), \ + .modeset_reg = _modeset_reg, \ + .modeset_mask = BIT(_modeset_shift), \ +} + +#define MT6359_LDO_LINEAR(match, _name, _min, _max, _step, \ + _enable_reg, _status_reg, _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_LINEAR, \ + .id = MT6359_ID_##_name, \ + .uV_step = (_step), \ + .n_voltages = ((_max) - (_min)) / (_step) + 1, \ + .min_uV = (_min), \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_LDO(match, _name, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask, _en_delay) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_TABLE, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359_REG_FIXED(match, _name, _enable_reg, \ + _status_reg, _fixed_volt) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = MT6359_REG_TYPE_FIXED, \ + .id = MT6359_ID_##_name, \ + .n_voltages = 1, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(0), \ + .fixed_uV = (_fixed_volt), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +#define MT6359P_LDO1(match, _name, _type, _tmp_volt_table, \ + _enable_reg, _enable_mask, _status_reg, \ + _vsel_reg, _vsel_mask) \ +[MT6359_ID_##_name] = { \ + .desc = { \ + .name = #_name, \ + .of_match = of_match_ptr(match), \ + .type = _type, \ + .id = MT6359_ID_##_name, \ + .n_voltages = ARRAY_SIZE(_tmp_volt_table), \ + .volt_table = _tmp_volt_table, \ + .vsel_reg = _vsel_reg, \ + .vsel_mask = _vsel_mask, \ + .enable_reg = _enable_reg, \ + .enable_mask = BIT(_enable_mask), \ + }, \ + .status_reg = _status_reg, \ + .qi = BIT(0), \ +} + +static const unsigned int vsim1_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static const unsigned int vibr_voltages[] = { + 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000, + 0, 3000000, 0, 3300000, +}; + +static const unsigned int vrf12_voltages[] = { + 0, 0, 1100000, 1200000, 1300000, +}; + +static const unsigned int volt18_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, +}; + +static const unsigned int vcn13_voltages[] = { + 900000, 1000000, 0, 1200000, 1300000, +}; + +static const unsigned int vcn33_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000, +}; + +static const unsigned int vefuse_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000, +}; + +static const unsigned int vxo22_voltages[] = { + 1800000, 0, 0, 0, 2200000, +}; + +static const unsigned int vrfck_voltages_1[] = { + 1240000, 1600000, +}; + +static const unsigned int vio28_voltages[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000, +}; + +static const unsigned int vemc_voltages_1[] = { + 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000, + 3300000, +}; + +static const unsigned int va12_voltages[] = { + 0, 0, 0, 0, 0, 0, 1200000, 1300000, +}; + +static const unsigned int va09_voltages[] = { + 0, 0, 800000, 900000, 0, 0, 1200000, +}; + +static const unsigned int vrf18_voltages[] = { + 0, 0, 0, 0, 0, 1700000, 1800000, 1810000, +}; + +static const unsigned int vbbck_voltages[] = { + 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000, +}; + +static const unsigned int vsim2_voltages[] = { + 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000, +}; + +static int mt6359_set_voltage_sel_regmap(struct udevice *dev, + struct mt6359_regulator_info *info, + unsigned int sel) +{ + sel <<= ffs(info->desc.vsel_mask) - 1; + + return pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); +} + +static int mt6359p_vemc_set_voltage_sel(struct udevice *dev, + struct mt6359_regulator_info *info, unsigned int sel) +{ + int ret; + + sel <<= ffs(info->desc.vsel_mask) - 1; + ret = pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, MT6359P_TMA_KEY); + if (ret) + return ret; + + ret = pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR); + if (ret < 0) + return ret; + + switch (ret) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + ret = pmic_clrsetbits(dev->parent, info->desc.vsel_reg + 0x2, + info->desc.vsel_mask, sel); + if (ret) + return ret; + + break; + default: + return -EINVAL; + } + + return pmic_reg_write(dev->parent, MT6359P_TMA_KEY_ADDR, 0); +} + +static int mt6359_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359p_vemc_get_voltage_sel(struct udevice *dev, struct mt6359_regulator_info *info) +{ + int selector; + + switch (pmic_reg_read(dev->parent, MT6359P_VM_MODE_ADDR)) { + case 0: + /* If HW trapping is 0, use VEMC_VOSEL_0 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg); + break; + case 1: + /* If HW trapping is 1, use VEMC_VOSEL_1 */ + selector = pmic_reg_read(dev->parent, info->desc.vsel_reg + 0x2); + break; + default: + return -EINVAL; + } + if (selector < 0) + return selector; + + selector &= info->desc.vsel_mask; + selector >>= ffs(info->desc.vsel_mask) - 1; + + return selector; +} + +static int mt6359_get_enable(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int ret; + + ret = pmic_reg_read(dev->parent, info->desc.enable_reg); + if (ret < 0) + return ret; + + return ret & info->desc.enable_mask ? true : false; +} + +static int mt6359_set_enable(struct udevice *dev, bool enable) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + + return pmic_clrsetbits(dev->parent, info->desc.enable_reg, + info->desc.enable_mask, + enable ? info->desc.enable_mask : 0); +} + +static int mt6359_get_value(struct udevice *dev) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.min_uV + (info->desc.uV_step * selector); + case MT6359_REG_TYPE_TABLE: + /* Get selection */ + selector = mt6359_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + case MT6359_REG_TYPE_FIXED: + return info->desc.fixed_uV; + case MT6359_REG_TYPE_VEMC: + /* Get selection */ + selector = mt6359p_vemc_get_voltage_sel(dev, info); + if (selector < 0) + return -EINVAL; + + /* Get voltage value */ + if (!info->desc.volt_table) { + dev_err(dev, "invalid voltage table for %s\n", info->desc.name); + return -EINVAL; + } + + if (selector >= info->desc.n_voltages) + return -EINVAL; + + return info->desc.volt_table[selector]; + default: + return -EINVAL; + } +} + +static int mt6359_set_value(struct udevice *dev, int uvolt) +{ + struct mt6359_regulator_info *info = dev_get_priv(dev); + int selector; + int i; + + switch (info->desc.type) { + case MT6359_REG_TYPE_LINEAR: + /* Find selection */ + if (uvolt < info->desc.min_uV) + return -EINVAL; + selector = DIV_ROUND_UP(uvolt - info->desc.min_uV, info->desc.uV_step); + if (selector < 0) + return -EINVAL; + + /* Set selection */ + return mt6359_set_voltage_sel_regmap(dev, info, selector); + case MT6359_REG_TYPE_TABLE: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359_set_voltage_sel_regmap(dev, info, i); + } + + return -EINVAL; + case MT6359_REG_TYPE_VEMC: + /* Find selection */ + for (i = 0; i < info->desc.n_voltages; i++) { + if (info->desc.volt_table[i] == uvolt) + return mt6359p_vemc_set_voltage_sel(dev, info, i); + } + + return -EINVAL; + default: + return -EINVAL; + } +} + +static struct mt6359_regulator_info mt6359p_regulators[] = { + MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500, + MT6359_RG_BUCK_VS1_EN_ADDR, + MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR, + MT6359_RG_BUCK_VS1_VOSEL_MASK << + MT6359_RG_BUCK_VS1_VOSEL_SHIFT, + MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT, + MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT), + MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250, + MT6359_RG_BUCK_VGPU11_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR, + MT6359_RG_BUCK_VGPU11_VOSEL_MASK << + MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250, + MT6359_RG_BUCK_VMODEM_EN_ADDR, + MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR, + MT6359_RG_BUCK_VMODEM_VOSEL_MASK << + MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT, + MT6359_RG_BUCK_VMODEM_LP_ADDR, + MT6359_RG_BUCK_VMODEM_LP_SHIFT, + MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT), + MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPU_EN_ADDR, + MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR, + MT6359_RG_BUCK_VPU_VOSEL_MASK << + MT6359_RG_BUCK_VPU_VOSEL_SHIFT, + MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT, + MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT), + MT6359_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250, + MT6359_RG_BUCK_VCORE_EN_ADDR, + MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR, + MT6359_RG_BUCK_VCORE_VOSEL_MASK << + MT6359_RG_BUCK_VCORE_VOSEL_SHIFT, + MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT, + MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT), + MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500, + MT6359_RG_BUCK_VS2_EN_ADDR, + MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR, + MT6359_RG_BUCK_VS2_VOSEL_MASK << + MT6359_RG_BUCK_VS2_VOSEL_SHIFT, + MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT, + MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT), + MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000, + MT6359_RG_BUCK_VPA_EN_ADDR, + MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR, + MT6359_RG_BUCK_VPA_VOSEL_MASK << + MT6359_RG_BUCK_VPA_VOSEL_SHIFT, + MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT, + MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT), + MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC2_EN_ADDR, + MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC2_VOSEL_MASK << + MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC2_LP_ADDR, + MT6359_RG_BUCK_VPROC2_LP_SHIFT, + MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT), + MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250, + MT6359_RG_BUCK_VPROC1_EN_ADDR, + MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR, + MT6359_RG_BUCK_VPROC1_VOSEL_MASK << + MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT, + MT6359_RG_BUCK_VPROC1_LP_ADDR, + MT6359_RG_BUCK_VPROC1_LP_SHIFT, + MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT), + MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, 400000, 1193750, 6250, + MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR, + MT6359_DA_VGPU11_EN_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR, + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK << + MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT, + MT6359_RG_BUCK_VGPU11_LP_ADDR, + MT6359_RG_BUCK_VGPU11_LP_SHIFT, + MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT), + MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR, + MT6359P_DA_VAUD18_B_EN_ADDR, 1800000), + MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages, + MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT, + MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR, + MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vibr", VIBR, vibr_voltages, + MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT, + MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR, + MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages, + MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT, + MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR, + MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR, + MT6359P_DA_VUSB_B_EN_ADDR, 3000000), + MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR, + MT6359P_DA_VSRAM_PROC2_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT), + MT6359_LDO("ldo_vio18", VIO18, volt18_voltages, + MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT, + MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR, + MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages, + MT6359P_RG_LDO_VCAMIO_EN_ADDR, + MT6359P_RG_LDO_VCAMIO_EN_SHIFT, + MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR, + MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT, + 1290), + MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR, + MT6359P_DA_VCN18_B_EN_ADDR, 1800000), + MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR, + MT6359P_DA_VFE28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages, + MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT, + MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR, + MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_0_ADDR, + MT6359_RG_LDO_VCN33_1_EN_0_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_1_EN_1_ADDR, + MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT, + MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR, + MT6359_RG_VCN33_1_VOSEL_MASK << + MT6359_RG_VCN33_1_VOSEL_SHIFT, 240), + MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR, + MT6359P_DA_VAUX18_B_EN_ADDR, 1800000), + MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT), + MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, + MT6359P_RG_LDO_VEFUSE_EN_ADDR, + MT6359P_RG_LDO_VEFUSE_EN_SHIFT, + MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR, + MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT, + 240), + MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages, + MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT, + MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR, + MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1, + MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT, + MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR, + MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT, + 480), + MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR, + MT6359P_DA_VBIF28_B_EN_ADDR, 2800000), + MT6359_LDO("ldo_vio28", VIO28, vio28_voltages, + MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT, + MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR, + MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT, + 1920), + MT6359P_LDO1("ldo_vemc_1", VEMC, MT6359_REG_TYPE_VEMC, vemc_voltages_1, + MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT, + MT6359P_DA_VEMC_B_EN_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR, + MT6359P_RG_LDO_VEMC_VOSEL_0_MASK << + MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT), + MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_0_ADDR, + MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages, + MT6359P_RG_LDO_VCN33_2_EN_1_ADDR, + MT6359_RG_LDO_VCN33_2_EN_1_SHIFT, + MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR, + MT6359_RG_VCN33_2_VOSEL_MASK << + MT6359_RG_VCN33_2_VOSEL_SHIFT, 240), + MT6359_LDO("ldo_va12", VA12, va12_voltages, + MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT, + MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR, + MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_va09", VA09, va09_voltages, + MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT, + MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR, + MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT, + 960), + MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages, + MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT, + MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR, + MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT, + 240), + MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_MD_EN_ADDR, + MT6359P_DA_VSRAM_MD_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT), + MT6359_LDO("ldo_vufs", VUFS, volt18_voltages, + MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT, + MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR, + MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vm18", VM18, volt18_voltages, + MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT, + MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR, + MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT, + 1920), + MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages, + MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT, + MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR, + MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR, + MT6359P_DA_VSRAM_PROC1_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT), + MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages, + MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT, + MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR, + MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT, + 480), + MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB, + 500000, 1293750, 6250, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR, + MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR, + MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR, + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK << + MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT), +}; + +static int mt6359_regulator_probe(struct udevice *dev) +{ + struct mt6359_regulator_info *priv = dev_get_priv(dev); + int i, hw_ver; + + hw_ver = pmic_reg_read(dev->parent, MT6359P_HWCID); + if (hw_ver < MT6359P_CHIP_VER) { + dev_err(dev, "mt6359 is not supported. Only support mt6359p, hw_ver(%d)\n", + hw_ver); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(mt6359p_regulators); i++) { + if (!strcmp(dev->name, mt6359p_regulators[i].desc.of_match)) { + *priv = mt6359p_regulators[i]; + return 0; + } + } + + return -ENOENT; +} + +static const struct dm_regulator_ops mt6359_regulator_ops = { + .get_value = mt6359_get_value, + .set_value = mt6359_set_value, + .get_enable = mt6359_get_enable, + .set_enable = mt6359_set_enable, +}; + +U_BOOT_DRIVER(mt6359_regulator) = { + .name = MT6359_REGULATOR_DRIVER, + .id = UCLASS_REGULATOR, + .ops = &mt6359_regulator_ops, + .probe = mt6359_regulator_probe, + .priv_auto = sizeof(struct mt6359_regulator_info), +}; diff --git a/include/power/mt6359.h b/include/power/mt6359.h new file mode 100644 index 00000000000..1e0380e87b0 --- /dev/null +++ b/include/power/mt6359.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#ifndef __MT6359_H_ +#define __MT6359_H_ + +#define MT6359_REGULATOR_DRIVER "mt6359_regulator" + +enum { + MT6359_ID_VS1 = 0, + MT6359_ID_VGPU11, + MT6359_ID_VMODEM, + MT6359_ID_VPU, + MT6359_ID_VCORE, + MT6359_ID_VS2, + MT6359_ID_VPA, + MT6359_ID_VPROC2, + MT6359_ID_VPROC1, + MT6359_ID_VCORE_SSHUB, + MT6359_ID_VGPU11_SSHUB = MT6359_ID_VCORE_SSHUB, + MT6359_ID_VAUD18 = 10, + MT6359_ID_VSIM1, + MT6359_ID_VIBR, + MT6359_ID_VRF12, + MT6359_ID_VUSB, + MT6359_ID_VSRAM_PROC2, + MT6359_ID_VIO18, + MT6359_ID_VCAMIO, + MT6359_ID_VCN18, + MT6359_ID_VFE28, + MT6359_ID_VCN13, + MT6359_ID_VCN33_1_BT, + MT6359_ID_VCN33_1_WIFI, + MT6359_ID_VAUX18, + MT6359_ID_VSRAM_OTHERS, + MT6359_ID_VEFUSE, + MT6359_ID_VXO22, + MT6359_ID_VRFCK, + MT6359_ID_VBIF28, + MT6359_ID_VIO28, + MT6359_ID_VEMC, + MT6359_ID_VCN33_2_BT, + MT6359_ID_VCN33_2_WIFI, + MT6359_ID_VA12, + MT6359_ID_VA09, + MT6359_ID_VRF18, + MT6359_ID_VSRAM_MD, + MT6359_ID_VUFS, + MT6359_ID_VM18, + MT6359_ID_VBBCK, + MT6359_ID_VSRAM_PROC1, + MT6359_ID_VSIM2, + MT6359_ID_VSRAM_OTHERS_SSHUB, + MT6359_ID_RG_MAX, +}; + + +/* PMIC Registers */ +#define MT6359_BUCK_VPU_CON0 0x1488 +#define MT6359_BUCK_VPU_DBG1 0x14a8 +#define MT6359_BUCK_VPU_ELR0 0x14ac +#define MT6359_BUCK_VCORE_CON0 0x1508 +#define MT6359_BUCK_VCORE_DBG1 0x1528 +#define MT6359_BUCK_VGPU11_CON0 0x1588 +#define MT6359_BUCK_VGPU11_DBG1 0x15a8 +#define MT6359_BUCK_VMODEM_CON0 0x1688 +#define MT6359_BUCK_VMODEM_DBG1 0x16a8 +#define MT6359_BUCK_VMODEM_ELR0 0x16ae +#define MT6359_BUCK_VPROC1_CON0 0x1708 +#define MT6359_BUCK_VPROC1_DBG1 0x1728 +#define MT6359_BUCK_VPROC1_ELR0 0x172e +#define MT6359_BUCK_VPROC2_CON0 0x1788 +#define MT6359_BUCK_VPROC2_DBG1 0x17a8 +#define MT6359_BUCK_VPROC2_ELR0 0x17b2 +#define MT6359_BUCK_VS1_CON0 0x1808 +#define MT6359_BUCK_VS1_DBG1 0x1828 +#define MT6359_BUCK_VS1_ELR0 0x1834 +#define MT6359_BUCK_VS2_CON0 0x1888 +#define MT6359_BUCK_VS2_DBG1 0x18a8 +#define MT6359_BUCK_VS2_ELR0 0x18b4 +#define MT6359_BUCK_VPA_CON0 0x1908 +#define MT6359_BUCK_VPA_CON1 0x190e +#define MT6359_BUCK_VPA_DBG1 0x1916 +#define MT6359_VGPUVCORE_ANA_CON2 0x198e +#define MT6359_VGPUVCORE_ANA_CON13 0x19a4 +#define MT6359_VPROC1_ANA_CON3 0x19b2 +#define MT6359_VPROC2_ANA_CON3 0x1a0e +#define MT6359_VMODEM_ANA_CON3 0x1a1a +#define MT6359_VPU_ANA_CON3 0x1a26 +#define MT6359_VS1_ANA_CON0 0x1a2c +#define MT6359_VS2_ANA_CON0 0x1a34 +#define MT6359_VPA_ANA_CON0 0x1a3c + +#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0 +#define MT6359_RG_BUCK_VPU_LP_SHIFT 1 +#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1 +#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0 +#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0 +#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1 +#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1 +#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0 +#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1 +#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1 +#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0 +#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1 +#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1 +#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0 +#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0 +#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1 +#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1 +#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0 +#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0 +#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1 +#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1 +#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0 +#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0 +#define MT6359_RG_BUCK_VS1_LP_SHIFT 1 +#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1 +#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0 +#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0 +#define MT6359_RG_BUCK_VS2_LP_SHIFT 1 +#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1 +#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0 +#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F +#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0 +#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0 +#define MT6359_RG_BUCK_VPA_LP_SHIFT 1 +#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1 +#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F +#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0 +#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1 +#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2 +#define MT6359_RG_VGPU11_FCCM_SHIFT 9 +#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13 +#define MT6359_RG_VCORE_FCCM_SHIFT 5 +#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3 +#define MT6359_RG_VPROC1_FCCM_SHIFT 1 +#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3 +#define MT6359_RG_VPROC2_FCCM_SHIFT 1 +#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3 +#define MT6359_RG_VMODEM_FCCM_SHIFT 1 +#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3 +#define MT6359_RG_VPU_FCCM_SHIFT 1 +#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0 +#define MT6359_RG_VS1_FPWM_SHIFT 3 +#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0 +#define MT6359_RG_VS2_FPWM_SHIFT 3 +#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0 +#define MT6359_RG_VPA_MODESET_SHIFT 1 +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0 +#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0 +#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15 +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F +#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1 +#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8 +#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF +#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM1_VOSEL_MASK 0xF +#define MT6359_RG_VSIM1_VOSEL_SHIFT 8 +#define MT6359_RG_VSIM2_VOSEL_MASK 0xF +#define MT6359_RG_VSIM2_VOSEL_SHIFT 8 +#define MT6359_RG_VIO28_VOSEL_MASK 0xF +#define MT6359_RG_VIO28_VOSEL_SHIFT 8 +#define MT6359_RG_VIBR_VOSEL_MASK 0xF +#define MT6359_RG_VIBR_VOSEL_SHIFT 8 +#define MT6359_RG_VRF18_VOSEL_MASK 0xF +#define MT6359_RG_VRF18_VOSEL_SHIFT 8 +#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF +#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8 +#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF +#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8 +#define MT6359_RG_VIO18_VOSEL_MASK 0xF +#define MT6359_RG_VIO18_VOSEL_SHIFT 8 +#define MT6359_RG_VM18_VOSEL_MASK 0xF +#define MT6359_RG_VM18_VOSEL_SHIFT 8 +#define MT6359_RG_VUFS_VOSEL_MASK 0xF +#define MT6359_RG_VUFS_VOSEL_SHIFT 8 +#define MT6359_RG_VRF12_VOSEL_MASK 0xF +#define MT6359_RG_VRF12_VOSEL_SHIFT 8 +#define MT6359_RG_VCN13_VOSEL_MASK 0xF +#define MT6359_RG_VCN13_VOSEL_SHIFT 8 +#define MT6359_RG_VA09_VOSEL_MASK 0xF +#define MT6359_RG_VA09_VOSEL_SHIFT 8 +#define MT6359_RG_VA12_VOSEL_MASK 0xF +#define MT6359_RG_VA12_VOSEL_SHIFT 8 +#define MT6359_RG_VXO22_VOSEL_MASK 0xF +#define MT6359_RG_VXO22_VOSEL_SHIFT 8 +#define MT6359_RG_VRFCK_VOSEL_MASK 0xF +#define MT6359_RG_VRFCK_VOSEL_SHIFT 8 + +#endif diff --git a/include/power/mt6359p.h b/include/power/mt6359p.h new file mode 100644 index 00000000000..506b5d38c68 --- /dev/null +++ b/include/power/mt6359p.h @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2026 MediaTek Inc. All Rights Reserved. + * Author: Bo-Chen Chen + */ + +#ifndef __MT6359P_H_ +#define __MT6359P_H_ + +#define MT6359P_CHIP_VER 0x5930 + +/* PMIC Registers */ +#define MT6359P_HWCID 0x8 +#define MT6359P_TOP_TRAP 0x50 +#define MT6359P_TOP_TMA_KEY 0x3a8 +#define MT6359P_BUCK_VCORE_ELR0 0x152c +#define MT6359P_BUCK_VGPU11_SSHUB_CON0 0x15aa +#define MT6359P_BUCK_VGPU11_ELR0 0x15b4 +#define MT6359P_LDO_VSRAM_PROC1_ELR 0x1b44 +#define MT6359P_LDO_VSRAM_PROC2_ELR 0x1b46 +#define MT6359P_LDO_VSRAM_OTHERS_ELR 0x1b48 +#define MT6359P_LDO_VSRAM_MD_ELR 0x1b4a +#define MT6359P_LDO_VEMC_ELR_0 0x1b4c +#define MT6359P_LDO_VFE28_CON0 0x1b88 +#define MT6359P_LDO_VFE28_MON 0x1b8c +#define MT6359P_LDO_VXO22_CON0 0x1b9a +#define MT6359P_LDO_VXO22_MON 0x1b9e +#define MT6359P_LDO_VRF18_CON0 0x1bac +#define MT6359P_LDO_VRF18_MON 0x1bb0 +#define MT6359P_LDO_VRF12_CON0 0x1bbe +#define MT6359P_LDO_VRF12_MON 0x1bc2 +#define MT6359P_LDO_VEFUSE_CON0 0x1bd0 +#define MT6359P_LDO_VEFUSE_MON 0x1bd4 +#define MT6359P_LDO_VCN33_1_CON0 0x1be2 +#define MT6359P_LDO_VCN33_1_MON 0x1be6 +#define MT6359P_LDO_VCN33_1_MULTI_SW 0x1bf4 +#define MT6359P_LDO_VCN33_2_CON0 0x1c08 +#define MT6359P_LDO_VCN33_2_MON 0x1c0c +#define MT6359P_LDO_VCN33_2_MULTI_SW 0x1c1a +#define MT6359P_LDO_VCN13_CON0 0x1c1c +#define MT6359P_LDO_VCN13_MON 0x1c20 +#define MT6359P_LDO_VCN18_CON0 0x1c2e +#define MT6359P_LDO_VCN18_MON 0x1c32 +#define MT6359P_LDO_VA09_CON0 0x1c40 +#define MT6359P_LDO_VA09_MON 0x1c44 +#define MT6359P_LDO_VCAMIO_CON0 0x1c52 +#define MT6359P_LDO_VCAMIO_MON 0x1c56 +#define MT6359P_LDO_VA12_CON0 0x1c64 +#define MT6359P_LDO_VA12_MON 0x1c68 +#define MT6359P_LDO_VAUX18_CON0 0x1c88 +#define MT6359P_LDO_VAUX18_MON 0x1c8c +#define MT6359P_LDO_VAUD18_CON0 0x1c9a +#define MT6359P_LDO_VAUD18_MON 0x1c9e +#define MT6359P_LDO_VIO18_CON0 0x1cac +#define MT6359P_LDO_VIO18_MON 0x1cb0 +#define MT6359P_LDO_VEMC_CON0 0x1cbe +#define MT6359P_LDO_VEMC_MON 0x1cc2 +#define MT6359P_LDO_VSIM1_CON0 0x1cd0 +#define MT6359P_LDO_VSIM1_MON 0x1cd4 +#define MT6359P_LDO_VSIM2_CON0 0x1ce2 +#define MT6359P_LDO_VSIM2_MON 0x1ce6 +#define MT6359P_LDO_VUSB_CON0 0x1d08 +#define MT6359P_LDO_VUSB_MON 0x1d0c +#define MT6359P_LDO_VRFCK_CON0 0x1d1c +#define MT6359P_LDO_VRFCK_MON 0x1d20 +#define MT6359P_LDO_VBBCK_CON0 0x1d2e +#define MT6359P_LDO_VBBCK_MON 0x1d32 +#define MT6359P_LDO_VBIF28_CON0 0x1d40 +#define MT6359P_LDO_VBIF28_MON 0x1d44 +#define MT6359P_LDO_VIBR_CON0 0x1d52 +#define MT6359P_LDO_VIBR_MON 0x1d56 +#define MT6359P_LDO_VIO28_CON0 0x1d64 +#define MT6359P_LDO_VIO28_MON 0x1d68 +#define MT6359P_LDO_VM18_CON0 0x1d88 +#define MT6359P_LDO_VM18_MON 0x1d8c +#define MT6359P_LDO_VUFS_CON0 0x1d9a +#define MT6359P_LDO_VUFS_MON 0x1d9e +#define MT6359P_LDO_VSRAM_PROC1_CON0 0x1e88 +#define MT6359P_LDO_VSRAM_PROC1_MON 0x1e8c +#define MT6359P_LDO_VSRAM_PROC2_CON0 0x1ea8 +#define MT6359P_LDO_VSRAM_PROC2_MON 0x1eac +#define MT6359P_LDO_VSRAM_OTHERS_CON0 0x1f08 +#define MT6359P_LDO_VSRAM_OTHERS_MON 0x1f0c +#define MT6359P_LDO_VSRAM_OTHERS_SSHUB 0x1f28 +#define MT6359P_LDO_VSRAM_MD_CON0 0x1f2e +#define MT6359P_LDO_VSRAM_MD_MON 0x1f32 +#define MT6359P_VCN33_1_ANA_CON0 0x1f98 +#define MT6359P_VCN33_2_ANA_CON0 0x1f9c +#define MT6359P_VSIM1_ANA_CON0 0x1fa2 +#define MT6359P_VSIM2_ANA_CON0 0x1fa6 +#define MT6359P_VIO28_ANA_CON0 0x1faa +#define MT6359P_VIBR_ANA_CON0 0x1fae +#define MT6359P_VFE28_ELR_4 0x1fc0 +#define MT6359P_VRF18_ANA_CON0 0x2008 +#define MT6359P_VEFUSE_ANA_CON0 0x200c +#define MT6359P_VCAMIO_ANA_CON0 0x2014 +#define MT6359P_VIO18_ANA_CON0 0x201c +#define MT6359P_VM18_ANA_CON0 0x2020 +#define MT6359P_VUFS_ANA_CON0 0x2024 +#define MT6359P_VRF12_ANA_CON0 0x202a +#define MT6359P_VCN13_ANA_CON0 0x202e +#define MT6359P_VRF18_ELR_3 0x204e +#define MT6359P_VXO22_ANA_CON0 0x2088 +#define MT6359P_VRFCK_ANA_CON0 0x208c +#define MT6359P_VBBCK_ANA_CON0 0x2096 + +#define MT6359P_RG_BUCK_VCORE_VOSEL_ADDR MT6359P_BUCK_VCORE_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR MT6359P_BUCK_VGPU11_ELR0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR MT6359P_BUCK_VGPU11_SSHUB_CON0 +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK 0x7F +#define MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT 4 +#define MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC1_ELR +#define MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359P_LDO_VSRAM_PROC2_ELR +#define MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_ELR +#define MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359P_LDO_VSRAM_MD_ELR +#define MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR MT6359P_LDO_VEMC_ELR_0 +#define MT6359P_RG_LDO_VEMC_VOSEL_0_MASK 0xF +#define MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT 0 +#define MT6359P_RG_LDO_VFE28_EN_ADDR MT6359P_LDO_VFE28_CON0 +#define MT6359P_DA_VFE28_B_EN_ADDR MT6359P_LDO_VFE28_MON +#define MT6359P_RG_LDO_VXO22_EN_ADDR MT6359P_LDO_VXO22_CON0 +#define MT6359P_RG_LDO_VXO22_EN_SHIFT 0 +#define MT6359P_DA_VXO22_B_EN_ADDR MT6359P_LDO_VXO22_MON +#define MT6359P_RG_LDO_VRF18_EN_ADDR MT6359P_LDO_VRF18_CON0 +#define MT6359P_RG_LDO_VRF18_EN_SHIFT 0 +#define MT6359P_DA_VRF18_B_EN_ADDR MT6359P_LDO_VRF18_MON +#define MT6359P_RG_LDO_VRF12_EN_ADDR MT6359P_LDO_VRF12_CON0 +#define MT6359P_RG_LDO_VRF12_EN_SHIFT 0 +#define MT6359P_DA_VRF12_B_EN_ADDR MT6359P_LDO_VRF12_MON +#define MT6359P_RG_LDO_VEFUSE_EN_ADDR MT6359P_LDO_VEFUSE_CON0 +#define MT6359P_RG_LDO_VEFUSE_EN_SHIFT 0 +#define MT6359P_DA_VEFUSE_B_EN_ADDR MT6359P_LDO_VEFUSE_MON +#define MT6359P_RG_LDO_VCN33_1_EN_0_ADDR MT6359P_LDO_VCN33_1_CON0 +#define MT6359P_DA_VCN33_1_B_EN_ADDR MT6359P_LDO_VCN33_1_MON +#define MT6359P_RG_LDO_VCN33_1_EN_1_ADDR MT6359P_LDO_VCN33_1_MULTI_SW +#define MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT 15 +#define MT6359P_RG_LDO_VCN33_2_EN_0_ADDR MT6359P_LDO_VCN33_2_CON0 +#define MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT 0 +#define MT6359P_DA_VCN33_2_B_EN_ADDR MT6359P_LDO_VCN33_2_MON +#define MT6359P_RG_LDO_VCN33_2_EN_1_ADDR MT6359P_LDO_VCN33_2_MULTI_SW +#define MT6359P_RG_LDO_VCN13_EN_ADDR MT6359P_LDO_VCN13_CON0 +#define MT6359P_RG_LDO_VCN13_EN_SHIFT 0 +#define MT6359P_DA_VCN13_B_EN_ADDR MT6359P_LDO_VCN13_MON +#define MT6359P_RG_LDO_VCN18_EN_ADDR MT6359P_LDO_VCN18_CON0 +#define MT6359P_DA_VCN18_B_EN_ADDR MT6359P_LDO_VCN18_MON +#define MT6359P_RG_LDO_VA09_EN_ADDR MT6359P_LDO_VA09_CON0 +#define MT6359P_RG_LDO_VA09_EN_SHIFT 0 +#define MT6359P_DA_VA09_B_EN_ADDR MT6359P_LDO_VA09_MON +#define MT6359P_RG_LDO_VCAMIO_EN_ADDR MT6359P_LDO_VCAMIO_CON0 +#define MT6359P_RG_LDO_VCAMIO_EN_SHIFT 0 +#define MT6359P_DA_VCAMIO_B_EN_ADDR MT6359P_LDO_VCAMIO_MON +#define MT6359P_RG_LDO_VA12_EN_ADDR MT6359P_LDO_VA12_CON0 +#define MT6359P_RG_LDO_VA12_EN_SHIFT 0 +#define MT6359P_DA_VA12_B_EN_ADDR MT6359P_LDO_VA12_MON +#define MT6359P_RG_LDO_VAUX18_EN_ADDR MT6359P_LDO_VAUX18_CON0 +#define MT6359P_DA_VAUX18_B_EN_ADDR MT6359P_LDO_VAUX18_MON +#define MT6359P_RG_LDO_VAUD18_EN_ADDR MT6359P_LDO_VAUD18_CON0 +#define MT6359P_DA_VAUD18_B_EN_ADDR MT6359P_LDO_VAUD18_MON +#define MT6359P_RG_LDO_VIO18_EN_ADDR MT6359P_LDO_VIO18_CON0 +#define MT6359P_RG_LDO_VIO18_EN_SHIFT 0 +#define MT6359P_DA_VIO18_B_EN_ADDR MT6359P_LDO_VIO18_MON +#define MT6359P_RG_LDO_VEMC_EN_ADDR MT6359P_LDO_VEMC_CON0 +#define MT6359P_RG_LDO_VEMC_EN_SHIFT 0 +#define MT6359P_DA_VEMC_B_EN_ADDR MT6359P_LDO_VEMC_MON +#define MT6359P_RG_LDO_VSIM1_EN_ADDR MT6359P_LDO_VSIM1_CON0 +#define MT6359P_RG_LDO_VSIM1_EN_SHIFT 0 +#define MT6359P_DA_VSIM1_B_EN_ADDR MT6359P_LDO_VSIM1_MON +#define MT6359P_RG_LDO_VSIM2_EN_ADDR MT6359P_LDO_VSIM2_CON0 +#define MT6359P_RG_LDO_VSIM2_EN_SHIFT 0 +#define MT6359P_DA_VSIM2_B_EN_ADDR MT6359P_LDO_VSIM2_MON +#define MT6359P_RG_LDO_VUSB_EN_0_ADDR MT6359P_LDO_VUSB_CON0 +#define MT6359P_DA_VUSB_B_EN_ADDR MT6359P_LDO_VUSB_MON +#define MT6359P_RG_LDO_VRFCK_EN_ADDR MT6359P_LDO_VRFCK_CON0 +#define MT6359P_RG_LDO_VRFCK_EN_SHIFT 0 +#define MT6359P_DA_VRFCK_B_EN_ADDR MT6359P_LDO_VRFCK_MON +#define MT6359P_RG_LDO_VBBCK_EN_ADDR MT6359P_LDO_VBBCK_CON0 +#define MT6359P_RG_LDO_VBBCK_EN_SHIFT 0 +#define MT6359P_DA_VBBCK_B_EN_ADDR MT6359P_LDO_VBBCK_MON +#define MT6359P_RG_LDO_VBIF28_EN_ADDR MT6359P_LDO_VBIF28_CON0 +#define MT6359P_DA_VBIF28_B_EN_ADDR MT6359P_LDO_VBIF28_MON +#define MT6359P_RG_LDO_VIBR_EN_ADDR MT6359P_LDO_VIBR_CON0 +#define MT6359P_RG_LDO_VIBR_EN_SHIFT 0 +#define MT6359P_DA_VIBR_B_EN_ADDR MT6359P_LDO_VIBR_MON +#define MT6359P_RG_LDO_VIO28_EN_ADDR MT6359P_LDO_VIO28_CON0 +#define MT6359P_RG_LDO_VIO28_EN_SHIFT 0 +#define MT6359P_DA_VIO28_B_EN_ADDR MT6359P_LDO_VIO28_MON +#define MT6359P_RG_LDO_VM18_EN_ADDR MT6359P_LDO_VM18_CON0 +#define MT6359P_RG_LDO_VM18_EN_SHIFT 0 +#define MT6359P_DA_VM18_B_EN_ADDR MT6359P_LDO_VM18_MON +#define MT6359P_RG_LDO_VUFS_EN_ADDR MT6359P_LDO_VUFS_CON0 +#define MT6359P_RG_LDO_VUFS_EN_SHIFT 0 +#define MT6359P_DA_VUFS_B_EN_ADDR MT6359P_LDO_VUFS_MON +#define MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359P_LDO_VSRAM_PROC1_CON0 +#define MT6359P_DA_VSRAM_PROC1_B_EN_ADDR MT6359P_LDO_VSRAM_PROC1_MON +#define MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359P_LDO_VSRAM_PROC2_CON0 +#define MT6359P_DA_VSRAM_PROC2_B_EN_ADDR MT6359P_LDO_VSRAM_PROC2_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_CON0 +#define MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_MON +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359P_LDO_VSRAM_OTHERS_SSHUB +#define MT6359P_RG_LDO_VSRAM_MD_EN_ADDR MT6359P_LDO_VSRAM_MD_CON0 +#define MT6359P_DA_VSRAM_MD_B_EN_ADDR MT6359P_LDO_VSRAM_MD_MON +#define MT6359P_RG_VCN33_1_VOSEL_ADDR MT6359P_VCN33_1_ANA_CON0 +#define MT6359P_RG_VCN33_2_VOSEL_ADDR MT6359P_VCN33_2_ANA_CON0 +#define MT6359P_RG_VSIM1_VOSEL_ADDR MT6359P_VSIM1_ANA_CON0 +#define MT6359P_RG_VSIM2_VOSEL_ADDR MT6359P_VSIM2_ANA_CON0 +#define MT6359P_RG_VIO28_VOSEL_ADDR MT6359P_VIO28_ANA_CON0 +#define MT6359P_RG_VIBR_VOSEL_ADDR MT6359P_VIBR_ANA_CON0 +#define MT6359P_RG_VRF18_VOSEL_ADDR MT6359P_VRF18_ANA_CON0 +#define MT6359P_RG_VEFUSE_VOSEL_ADDR MT6359P_VEFUSE_ANA_CON0 +#define MT6359P_RG_VCAMIO_VOSEL_ADDR MT6359P_VCAMIO_ANA_CON0 +#define MT6359P_RG_VIO18_VOSEL_ADDR MT6359P_VIO18_ANA_CON0 +#define MT6359P_RG_VM18_VOSEL_ADDR MT6359P_VM18_ANA_CON0 +#define MT6359P_RG_VUFS_VOSEL_ADDR MT6359P_VUFS_ANA_CON0 +#define MT6359P_RG_VRF12_VOSEL_ADDR MT6359P_VRF12_ANA_CON0 +#define MT6359P_RG_VCN13_VOSEL_ADDR MT6359P_VCN13_ANA_CON0 +#define MT6359P_RG_VA09_VOSEL_ADDR MT6359P_VRF18_ELR_3 +#define MT6359P_RG_VA12_VOSEL_ADDR MT6359P_VFE28_ELR_4 +#define MT6359P_RG_VXO22_VOSEL_ADDR MT6359P_VXO22_ANA_CON0 +#define MT6359P_RG_VRFCK_VOSEL_ADDR MT6359P_VRFCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_ADDR MT6359P_VBBCK_ANA_CON0 +#define MT6359P_RG_VBBCK_VOSEL_MASK 0xF +#define MT6359P_RG_VBBCK_VOSEL_SHIFT 4 +#define MT6359P_VM_MODE_ADDR MT6359P_TOP_TRAP +#define MT6359P_TMA_KEY_ADDR MT6359P_TOP_TMA_KEY + +#define MT6359P_TMA_KEY 0x9CA6 + +#endif -- cgit v1.3.1 From 49aa5b83622ab1936201610286a234b59b7ea35f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Fri, 13 Feb 2026 06:15:06 +0100 Subject: imx: scu_api: implement sc_misc_get_boot_type add function sc_misc_get_boot_type() which returns the boot type. Signed-off-by: Heiko Schocher Signed-off-by: Walter Schweizer Reviewed-by: Peng Fan --- drivers/misc/imx8/scu_api.c | 25 +++++++++++++++++++++++++ include/firmware/imx/sci/sci.h | 1 + 2 files changed, 26 insertions(+) (limited to 'include') diff --git a/drivers/misc/imx8/scu_api.c b/drivers/misc/imx8/scu_api.c index d9cc7acb970..c15a4a629ad 100644 --- a/drivers/misc/imx8/scu_api.c +++ b/drivers/misc/imx8/scu_api.c @@ -374,6 +374,31 @@ void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status) __func__, status, RPC_R8(&msg)); } +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type) +{ + struct udevice *dev = gd->arch.scu_dev; + int size = sizeof(struct sc_rpc_msg_s); + struct sc_rpc_msg_s msg; + int ret; + + if (!dev) + hang(); + + RPC_VER(&msg) = SC_RPC_VERSION; + RPC_SIZE(&msg) = 1U; + RPC_SVC(&msg) = (u8)SC_RPC_SVC_MISC; + RPC_FUNC(&msg) = (u8)MISC_FUNC_GET_BOOT_TYPE; + + ret = misc_call(dev, SC_FALSE, &msg, size, &msg, size); + if (ret < 0) + return ret; + + if (type) + *type = (u8)RPC_U8(&msg, 0U); + + return 0; +} + int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx) { struct udevice *dev = gd->arch.scu_dev; diff --git a/include/firmware/imx/sci/sci.h b/include/firmware/imx/sci/sci.h index 876d52cac35..7f4ca735663 100644 --- a/include/firmware/imx/sci/sci.h +++ b/include/firmware/imx/sci/sci.h @@ -86,6 +86,7 @@ int sc_misc_get_control(sc_ipc_t ipc, sc_rsrc_t resource, sc_ctrl_t ctrl, u32 *val); void sc_misc_get_boot_dev(sc_ipc_t ipc, sc_rsrc_t *boot_dev); void sc_misc_boot_status(sc_ipc_t ipc, sc_misc_boot_status_t status); +int sc_misc_get_boot_type(sc_ipc_t ipc, sc_misc_bt_t *type); int sc_misc_get_boot_container(sc_ipc_t ipc, u8 *idx); void sc_misc_build_info(sc_ipc_t ipc, u32 *build, u32 *commit); int sc_misc_otp_fuse_read(sc_ipc_t ipc, u32 word, u32 *val); -- cgit v1.3.1 From cc832b676456c11cd730dd75f0c122991268e64d Mon Sep 17 00:00:00 2001 From: Adrian Freihofer Date: Tue, 17 Feb 2026 17:39:11 +0100 Subject: siemens: capricorn: protect environment With ENV_WRITEABLE_LIST only specific environment variables lisetd in CFG_ENV_FLAGS_LIST_STATIC are read from the u-boot environment storage. All other environment variables are set to default values and are not written back to the storage. The u-boot environment usually stays for the lifetime of the product. There is no A/B copy mechanism as for the firmware itself. That means that incompatible changes to environment variables in future u-boot versions may lead to serious issues if the old environment is used with a new u-boot version or vice versa. Having this protection in place ensures that only a limited set of environment variables are persisted across u-boot versions. All the macros not listed in CFG_ENV_FLAGS_LIST_STATIC are now part of the u-boot binary which is redundant and immutable. This guarantees that the u-boot version and the default values of these environment variables are always in sync and cannot be changed at runtime. ustate and rastate are not relevant for u-boot itself. ustate is used by swupdate which persists the transaction state in the environment. rastate is a similar variable used by another user space application. Signed-off-by: Adrian Freihofer Signed-off-by: Heiko Schocher Reviewed-by: Peng Fan Signed-off-by: Adrian Freihofer Signed-off-by: Heiko Schocher Reviewed-by: Peng Fan --- configs/imx8qxp_capricorn.config | 1 + include/configs/capricorn-common.h | 13 +++++++++++++ 2 files changed, 14 insertions(+) (limited to 'include') diff --git a/configs/imx8qxp_capricorn.config b/configs/imx8qxp_capricorn.config index 626634cb09c..2bae5b1a862 100644 --- a/configs/imx8qxp_capricorn.config +++ b/configs/imx8qxp_capricorn.config @@ -12,6 +12,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_REDUNDANT=y CONFIG_ENV_MMC_EMMC_HW_PARTITION=2 +CONFIG_ENV_WRITEABLE_LIST=y CONFIG_DM_GPIO=y CONFIG_AHAB_BOOT=y diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 7120a44d186..ee13d2ab950 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -38,6 +38,19 @@ #define CFG_EXTRA_ENV_SETTINGS \ AHAB_ENV +#ifdef CONFIG_ENV_WRITEABLE_LIST +#define CFG_ENV_FLAGS_LIST_STATIC \ + "bootcount:dw," \ + "bootdelay:sw," \ + "bootlimit:dw," \ + "partitionset_active:sw," \ + "rastate:dw," \ + "sig_a:sw,sig_b:sw," \ + "target_env:sw," \ + "upgrade_available:dw," \ + "ustate:dw" +#endif + /* Default location for tftp and bootm */ /* On CCP board, USDHC1 is for eMMC */ -- cgit v1.3.1 From 7b60cd933bc1db31c94483f6aeb9289722427c5e Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Tue, 24 Feb 2026 09:45:04 -0600 Subject: usb: gadget: Mark udc_disconnect as static With the last external callers of udc_disconnect long removed, mark this function as static now and remove it from headers. Signed-off-by: Tom Rini Reviewed-by: Mattijs Korpershoek Link: https://patch.msgid.link/20260224154504.85301-1-trini@konsulko.com Signed-off-by: Mattijs Korpershoek --- arch/arm/include/asm/bootm.h | 2 -- drivers/usb/gadget/ci_udc.c | 2 +- include/usb.h | 9 --------- include/usb/udc.h | 1 - 4 files changed, 1 insertion(+), 13 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/bootm.h b/arch/arm/include/asm/bootm.h index 439e43c2d01..762f00e6900 100644 --- a/arch/arm/include/asm/bootm.h +++ b/arch/arm/include/asm/bootm.h @@ -8,8 +8,6 @@ #ifndef ARM_BOOTM_H #define ARM_BOOTM_H -extern void udc_disconnect(void); - #ifdef CONFIG_SUPPORT_PASSING_ATAGS # define BOOTM_ENABLE_TAGS 1 #else diff --git a/drivers/usb/gadget/ci_udc.c b/drivers/usb/gadget/ci_udc.c index 046bb335ecb..4729570c525 100644 --- a/drivers/usb/gadget/ci_udc.c +++ b/drivers/usb/gadget/ci_udc.c @@ -990,7 +990,7 @@ int dm_usb_gadget_handle_interrupts(struct udevice *dev) return value; } -void udc_disconnect(void) +static void udc_disconnect(void) { struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor; /* disable pullup */ diff --git a/include/usb.h b/include/usb.h index be37ed272e1..dab23753f0c 100644 --- a/include/usb.h +++ b/include/usb.h @@ -208,15 +208,6 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); #define USB_UHCI_VEND_ID 0x8086 #define USB_UHCI_DEV_ID 0x7112 -/* - * PXA25x can only act as USB device. There are drivers - * which works with USB CDC gadgets implementations. - * Some of them have common routines which can be used - * in boards init functions e.g. udc_disconnect() used for - * forced device disconnection from host. - */ -extern void udc_disconnect(void); - /* * board-specific hardware initialization, called by * usb drivers and u-boot commands diff --git a/include/usb/udc.h b/include/usb/udc.h index 749b3a3f015..c5e431813be 100644 --- a/include/usb/udc.h +++ b/include/usb/udc.h @@ -39,7 +39,6 @@ int udc_endpoint_write(struct usb_endpoint_instance *endpoint); void udc_setup_ep(struct usb_device_instance *device, unsigned int ep, struct usb_endpoint_instance *endpoint); void udc_connect(void); -void udc_disconnect(void); void udc_enable(struct usb_device_instance *device); void udc_disable(void); void udc_startup_events(struct usb_device_instance *device); -- cgit v1.3.1 From 52877548d38ddb9e218347066187606d96767621 Mon Sep 17 00:00:00 2001 From: Jonas Karlman Date: Sat, 31 Jan 2026 23:38:23 +0000 Subject: arch: arm: rockchip: Add initial support for RK3506 Rockchip RK3506 is a ARM-based SoC with tri-core Cortex-A7. Add initial arch support for the RK3506 SoC. Signed-off-by: Jonas Karlman Acked-by: Mattijs Korpershoek # drivers/usb/gadget Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rk3506/boot0.h | 9 ++ arch/arm/include/asm/arch-rk3506/gpio.h | 9 ++ arch/arm/mach-rockchip/Kconfig | 44 +++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3506/Kconfig | 15 ++++ arch/arm/mach-rockchip/rk3506/Makefile | 5 ++ arch/arm/mach-rockchip/rk3506/clk_rk3506.c | 16 ++++ arch/arm/mach-rockchip/rk3506/rk3506.c | 125 ++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3506/syscon_rk3506.c | 19 ++++ drivers/usb/gadget/Kconfig | 1 + include/configs/rk3506_common.h | 38 ++++++++ 11 files changed, 282 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3506/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3506/gpio.h create mode 100644 arch/arm/mach-rockchip/rk3506/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3506/Makefile create mode 100644 arch/arm/mach-rockchip/rk3506/clk_rk3506.c create mode 100644 arch/arm/mach-rockchip/rk3506/rk3506.c create mode 100644 arch/arm/mach-rockchip/rk3506/syscon_rk3506.c create mode 100644 include/configs/rk3506_common.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-rk3506/boot0.h b/arch/arm/include/asm/arch-rk3506/boot0.h new file mode 100644 index 00000000000..8ae46f25a87 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/boot0.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3506/gpio.h b/arch/arm/include/asm/arch-rk3506/gpio.h new file mode 100644 index 00000000000..5516e649b80 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3506/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 5eac0cb7d94..5c37bf54deb 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -318,6 +318,49 @@ config ROCKCHIP_RK3399 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UARTs, SPI, I2C and PWMs. +config ROCKCHIP_RK3506 + bool "Support Rockchip RK3506" + select CPU_V7A + select SUPPORT_SPL + select SPL + select CLK + select PINCTRL + select RAM + select REGMAP + select SYSCON + select BOARD_LATE_INIT + select DM_REGULATOR_FIXED + select DM_RESET + imply BOOTSTD_FULL + imply DM_RNG + imply ENV_RELOC_GD_ENV_ADDR + imply FIT + imply LEGACY_IMAGE_FORMAT + imply MISC + imply MISC_INIT_R + imply OF_LIBFDT_OVERLAY + imply OF_LIVE + imply RNG_ROCKCHIP + imply ROCKCHIP_COMMON_BOARD + imply ROCKCHIP_COMMON_STACK_ADDR + imply ROCKCHIP_EXTERNAL_TPL + imply ROCKCHIP_OTP + imply SPL_ARMV7_SET_CORTEX_SMPEN + imply SPL_CLK + imply SPL_DM_SEQ_ALIAS + imply SPL_FIT_SIGNATURE + imply SPL_LOAD_FIT + imply SPL_OF_CONTROL + imply SPL_PINCTRL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_SERIAL + imply SPL_SYSCON + imply SYS_ARCH_TIMER + imply SYSRESET + help + The Rockchip RK3506 is a ARM-based SoC with a tri-core Cortex-A7. + config ROCKCHIP_RK3528 bool "Support Rockchip RK3528" select ARM64 @@ -746,6 +789,7 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3506/Kconfig" source "arch/arm/mach-rockchip/rk3528/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rk3576/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 06fb527b21a..d3bc0689f89 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += rk3308/ obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ +obj-$(CONFIG_ROCKCHIP_RK3506) += rk3506/ obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RK3576) += rk3576/ diff --git a/arch/arm/mach-rockchip/rk3506/Kconfig b/arch/arm/mach-rockchip/rk3506/Kconfig new file mode 100644 index 00000000000..92f187458c6 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Kconfig @@ -0,0 +1,15 @@ +if ROCKCHIP_RK3506 + +config ROCKCHIP_BOOT_MODE_REG + default 0xff910200 + +config ROCKCHIP_STIMER_BASE + default 0xff980000 + +config SYS_SOC + default "rk3506" + +config SYS_CONFIG_NAME + default "rk3506_common" + +endif diff --git a/arch/arm/mach-rockchip/rk3506/Makefile b/arch/arm/mach-rockchip/rk3506/Makefile new file mode 100644 index 00000000000..a1760bd0f0a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +obj-y += rk3506.o +obj-y += clk_rk3506.o +obj-y += syscon_rk3506.o diff --git a/arch/arm/mach-rockchip/rk3506/clk_rk3506.c b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c new file mode 100644 index 00000000000..96723f403cf --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/clk_rk3506.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3506_cru), devp); +} + +void *rockchip_get_cru(void) +{ + return (void *)RK3506_CRU_BASE; +} diff --git a/arch/arm/mach-rockchip/rk3506/rk3506.c b/arch/arm/mach-rockchip/rk3506/rk3506.c new file mode 100644 index 00000000000..2ed1dcc128e --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/rk3506.c @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#define LOG_CATEGORY LOGC_ARCH + +#include +#include +#include +#include + +#define SGRF_BASE 0xff210000 + +#define FIREWALL_DDR_BASE 0xff5f0000 +#define FW_DDR_MST1_REG 0x24 +#define FW_DDR_MST2_REG 0x28 +#define FW_DDR_MST3_REG 0x2c + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/soc/mmc@ff480000", + [BROM_BOOTSOURCE_SD] = "/soc/mmc@ff480000", +}; + +void board_debug_uart_init(void) +{ +} + +int arch_cpu_init(void) +{ + u32 val; + + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return 0; + + /* Select non-secure OTPC */ + rk_clrreg(SGRF_BASE + 0x100, BIT(1)); + + /* Set the sdmmc/emmc to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the fspi to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac0 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + writel(val & 0xf0ffffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); + + /* Set the mac1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + writel(val & 0xfffffff0, FIREWALL_DDR_BASE + FW_DDR_MST2_REG); + + /* Set the otg1 to access ddr memory */ + val = readl(FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + writel(val & 0xfff0ffff, FIREWALL_DDR_BASE + FW_DDR_MST3_REG); + + return 0; +} + +#define HP_TIMER_BASE CONFIG_ROCKCHIP_STIMER_BASE +#define HP_CTRL_REG 0x04 +#define TIMER_EN BIT(0) +#define HP_LOAD_COUNT0_REG 0x14 +#define HP_LOAD_COUNT1_REG 0x18 + +void rockchip_stimer_init(void) +{ + u32 reg; + + if (!IS_ENABLED(CONFIG_XPL_BUILD)) + return; + + reg = readl(HP_TIMER_BASE + HP_CTRL_REG); + if (reg & TIMER_EN) + return; + + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); + writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); + writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); +} + +#define RK3506_OTP_CPU_CODE_OFFSET 0x02 +#define RK3506_OTP_SPECIFICATION_OFFSET 0x08 + +int checkboard(void) +{ + u8 cpu_code[2], specification; + struct udevice *dev; + char suffix[2]; + int ret; + + if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC)) + return 0; + + ret = uclass_get_device_by_driver(UCLASS_MISC, + DM_DRIVER_GET(rockchip_otp), &dev); + if (ret) { + log_debug("Could not find otp device, ret=%d\n", ret); + return 0; + } + + /* cpu-code: SoC model, e.g. 0x35 0x06 */ + ret = misc_read(dev, RK3506_OTP_CPU_CODE_OFFSET, cpu_code, 2); + if (ret < 0) { + log_debug("Could not read cpu-code, ret=%d\n", ret); + return 0; + } + + /* specification: SoC variant, e.g. 0xA for RK3506J */ + ret = misc_read(dev, RK3506_OTP_SPECIFICATION_OFFSET, &specification, 1); + if (ret < 0) { + log_debug("Could not read specification, ret=%d\n", ret); + return 0; + } + specification &= 0x1f; + + /* for RK3506J i.e. '@' + 0xA = 'J' */ + suffix[0] = specification > 1 ? '@' + specification : '\0'; + suffix[1] = '\0'; + + printf("SoC: RK%02x%02x%s\n", cpu_code[0], cpu_code[1], suffix); + + return 0; +} diff --git a/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c new file mode 100644 index 00000000000..2548b0fa2d3 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3506/syscon_rk3506.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright Contributors to the U-Boot project. + +#include +#include + +static const struct udevice_id rk3506_syscon_ids[] = { + { .compatible = "rockchip,rk3506-grf", .data = ROCKCHIP_SYSCON_GRF }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3506_syscon) = { + .name = "rockchip_rk3506_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3506_syscon_ids, +#if CONFIG_IS_ENABLED(OF_REAL) + .bind = dm_scan_fdt_dev, +#endif +}; diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index ebb306852a6..baa2eb61ea3 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -89,6 +89,7 @@ config USB_GADGET_PRODUCT_NUM default 0x350b if ROCKCHIP_RK3588 default 0x350c if ROCKCHIP_RK3528 default 0x350e if ROCKCHIP_RK3576 + default 0x350f if ROCKCHIP_RK3506 default 0x4ee0 if ARCH_SNAPDRAGON default 0x0 help diff --git a/include/configs/rk3506_common.h b/include/configs/rk3506_common.h new file mode 100644 index 00000000000..5e4ef67289f --- /dev/null +++ b/include/configs/rk3506_common.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright Contributors to the U-Boot project. */ + +#ifndef __CONFIG_RK3506_COMMON_H +#define __CONFIG_RK3506_COMMON_H + +#define CFG_CPUID_OFFSET 0xa + +#include "rockchip-common.h" + +#define CFG_IRAM_BASE 0xfff80000 + +#define CFG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xc0000000 + +#ifndef ROCKCHIP_DEVICE_SETTINGS +#define ROCKCHIP_DEVICE_SETTINGS +#endif + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00500000\0" \ + "script_offset_f=0xffe000\0" \ + "script_size_f=0x2000\0" \ + "pxefile_addr_r=0x00600000\0" \ + "kernel_addr_r=0x02080000\0" \ + "kernel_comp_addr_r=0x08000000\0" \ + "fdt_addr_r=0x01e00000\0" \ + "fdtoverlay_addr_r=0x01f00000\0" \ + "ramdisk_addr_r=0x06000000\0" \ + "kernel_comp_size=0x2000000\0" + +#define CFG_EXTRA_ENV_SETTINGS \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + "boot_targets=" BOOT_TARGETS "\0" + +#endif /* __CONFIG_RK3506_COMMON_H */ -- cgit v1.3.1 From 4dcff3b572a1d67c35b7ed71253a6d85aefe4e9b Mon Sep 17 00:00:00 2001 From: Andreas Schwab Date: Wed, 28 Jan 2026 17:51:02 +0100 Subject: sifive: switch to OF_UPSTREAM Tested on HiFive Unleashed and HiFive Unmatched, both SPIFlash and MMC boot. Signed-off-by: Andreas Schwab Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/fu540/Kconfig | 1 + arch/riscv/cpu/fu740/Kconfig | 1 + arch/riscv/dts/Makefile | 2 - arch/riscv/dts/fu540-c000-u-boot.dtsi | 16 +- arch/riscv/dts/fu540-c000.dtsi | 286 ---------------------- arch/riscv/dts/fu740-c000.dtsi | 326 -------------------------- arch/riscv/dts/hifive-unleashed-a00.dts | 105 --------- arch/riscv/dts/hifive-unmatched-a00.dts | 246 ------------------- configs/sifive_unleashed_defconfig | 2 +- configs/sifive_unmatched_defconfig | 2 +- drivers/clk/sifive/fu540-prci.c | 8 +- include/dt-bindings/clock/sifive-fu540-prci.h | 18 -- 12 files changed, 16 insertions(+), 997 deletions(-) delete mode 100644 arch/riscv/dts/fu540-c000.dtsi delete mode 100644 arch/riscv/dts/fu740-c000.dtsi delete mode 100644 arch/riscv/dts/hifive-unleashed-a00.dts delete mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts delete mode 100644 include/dt-bindings/clock/sifive-fu540-prci.h (limited to 'include') diff --git a/arch/riscv/cpu/fu540/Kconfig b/arch/riscv/cpu/fu540/Kconfig index c68209d8fb2..f2934cb33e7 100644 --- a/arch/riscv/cpu/fu540/Kconfig +++ b/arch/riscv/cpu/fu540/Kconfig @@ -39,6 +39,7 @@ config SIFIVE_FU540 imply PWM_SIFIVE imply DM_I2C imply SYS_I2C_OCORES + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig index d7ca9687171..66f9a8d5fa5 100644 --- a/arch/riscv/cpu/fu740/Kconfig +++ b/arch/riscv/cpu/fu740/Kconfig @@ -40,6 +40,7 @@ config SIFIVE_FU740 imply DM_I2C imply SYS_I2C_OCORES imply SPL_I2C + imply OF_UPSTREAM if ENV_IS_IN_SPI_FLASH diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 9b347fc3b50..8e591cb7aa9 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,8 +9,6 @@ dtb-$(CONFIG_TARGET_MILKV_DUO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_TARGET_LICHEERV_NANO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb -dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index 360679a1781..19c7d6ccaca 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -7,11 +7,11 @@ / { cpus { - assigned-clocks = <&prci PRCI_CLK_COREPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_COREPLL>; assigned-clock-rates = <1000000000>; bootph-pre-ram; cpu0: cpu@0 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; status = "okay"; cpu0_intc: interrupt-controller { @@ -19,28 +19,28 @@ }; }; cpu1: cpu@1 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu1_intc: interrupt-controller { bootph-pre-ram; }; }; cpu2: cpu@2 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu2_intc: interrupt-controller { bootph-pre-ram; }; }; cpu3: cpu@3 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu3_intc: interrupt-controller { bootph-pre-ram; }; }; cpu4: cpu@4 { - clocks = <&prci PRCI_CLK_COREPLL>; + clocks = <&prci FU540_PRCI_CLK_COREPLL>; bootph-pre-ram; cpu4_intc: interrupt-controller { bootph-pre-ram; @@ -80,7 +80,7 @@ reg = <0x0 0x100b0000 0x0 0x0800 0x0 0x100b2000 0x0 0x2000 0x0 0x100b8000 0x0 0x1000>; - clocks = <&prci PRCI_CLK_DDRPLL>; + clocks = <&prci FU540_PRCI_CLK_DDRPLL>; clock-frequency = <933333324>; bootph-pre-ram; }; @@ -100,7 +100,7 @@ }; ð0 { - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>; + assigned-clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>; assigned-clock-rates = <125000000>; }; diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi deleted file mode 100644 index 7db86105348..00000000000 --- a/arch/riscv/dts/fu540-c000.dtsi +++ /dev/null @@ -1,286 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -/dts-v1/; - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,e51", "sifive,rocket0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - reg = <0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <1>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <2>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <3>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <32>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <64>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <32>; - mmu-type = "riscv,sv39"; - reg = <4>; - riscv,isa = "rv64imafdc"; - tlb-split; - next-level-cache = <&l2cache>; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <53>; - interrupt-controller; - interrupts-extended = < - &cpu0_intc 0xffffffff - &cpu1_intc 0xffffffff &cpu1_intc 9 - &cpu2_intc 0xffffffff &cpu2_intc 9 - &cpu3_intc 0xffffffff &cpu3_intc 9 - &cpu4_intc 0xffffffff &cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu540-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <4>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - dma: dma@3000000 { - compatible = "sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic0>; - interrupts = <23 24 25 26 27 28 29 30>; - #dma-cells = <1>; - }; - uart1: serial@10011000 { - compatible = "sifive,fu540-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <5>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu540-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <50>; - clocks = <&prci PRCI_CLK_TLCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000 - 0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <51>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000 - 0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi2: spi@10050000 { - compatible = "sifive,fu540-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <6>; - clocks = <&prci PRCI_CLK_TLCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <53>; - reg = <0x0 0x10090000 0x0 0x2000 - 0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci PRCI_CLK_GEMGXLPLL>, - <&prci PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <42 43 44 45>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu540-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <46 47 48 49>; - clocks = <&prci PRCI_CLK_TLCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - l2cache: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <1024>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <1 2 3>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu540-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>, - <14>, <15>, <16>, <17>, <18>, <19>, <20>, - <21>, <22>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci PRCI_CLK_TLCLK>; - status = "disabled"; - }; - }; -}; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi deleted file mode 100644 index 7b77c13496d..00000000000 --- a/arch/riscv/dts/fu740-c000.dtsi +++ /dev/null @@ -1,326 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -/dts-v1/; - -#include - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = ð0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,bullet0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - reg = <0x0>; - riscv,isa = "rv64imac"; - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x1>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x2>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x3>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x4>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - #address-cells = <0>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <69>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 0xffffffff>, - <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, - <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, - <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, - <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu740-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <39>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - uart1: serial@10011000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <40>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c1: i2c@10031000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10031000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <53>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000>, - <0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <41>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000>, - <0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <42>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi0: spi@10050000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <43>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000>, - <0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>, - <&prci FU740_PRCI_CLK_GEMGXLPLL>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <44>, <45>, <46>, <47>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <48>, <49>, <50>, <51>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - #pwm-cells = <3>; - status = "disabled"; - }; - ccache: cache-controller@2010000 { - compatible = "sifive,fu740-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <19>, <21>, <22>, <20>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>, <31>, <32>, <33>, <34>, <35>, <36>, - <37>, <38>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci FU740_PRCI_CLK_PCLK>; - status = "disabled"; - }; - pcie@e00000000 { - compatible = "sifive,fu740-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - reg = <0xe 0x00000000 0x0 0x80000000>, - <0xd 0xf0000000 0x0 0x10000000>, - <0x0 0x100d0000 0x0 0x1000>; - reg-names = "dbi", "config", "mgmt"; - device_type = "pci"; - dma-coherent; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ - <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ - <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ - <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ - num-lanes = <0x8>; - interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; - interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-parent = <&plic0>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, - <0x0 0x0 0x0 0x2 &plic0 58>, - <0x0 0x0 0x0 0x3 &plic0 59>, - <0x0 0x0 0x0 0x4 &plic0 60>; - clock-names = "pcie_aux"; - clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>; - pwren-gpios = <&gpio 5 0>; - reset-gpios = <&gpio 8 0>; - resets = <&prci 4>; - status = "okay"; - }; - }; -}; diff --git a/arch/riscv/dts/hifive-unleashed-a00.dts b/arch/riscv/dts/hifive-unleashed-a00.dts deleted file mode 100644 index 4a2729f5ca3..00000000000 --- a/arch/riscv/dts/hifive-unleashed-a00.dts +++ /dev/null @@ -1,105 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2018-2019 SiFive, Inc */ - -#include "fu540-c000.dtsi" -#include - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - #address-cells = <2>; - #size-cells = <2>; - model = "SiFive HiFive Unleashed A00"; - compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = ; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x2 0x00000000>; - }; - - soc { - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <33333333>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - clock-output-names = "rtcclk"; - }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio 10 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "issi,is25wp256", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&qspi2 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; -}; diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts deleted file mode 100644 index c4ed9efdff0..00000000000 --- a/arch/riscv/dts/hifive-unmatched-a00.dts +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0 OR MIT) -/* Copyright (c) 2020 SiFive, Inc */ - -#include "fu740-c000.dtsi" -#include -#include - -/* Clock frequency (in Hz) of the PCB crystal for rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "SiFive HiFive Unmatched A00"; - compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", - "sifive,fu740"; - - chosen { - stdout-path = "serial0"; - }; - - cpus { - timebase-frequency = ; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x4 0x00000000>; - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = ; - clock-output-names = "rtcclk"; - }; - - gpio-poweroff { - compatible = "gpio-poweroff"; - gpios = <&gpio 2 GPIO_ACTIVE_LOW>; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - vcc-supply = <&vdd_bpro>; - interrupt-parent = <&gpio>; - interrupts = <6 IRQ_TYPE_LEVEL_LOW>; - }; - - eeprom@54 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x54>; - vcc-supply = <&vdd_bpro>; - label = "board-id"; - pagesize = <16>; - read-only; - size = <256>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio>; - interrupts = <1 IRQ_TYPE_LEVEL_LOW>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - wdt { - compatible = "dlg,da9063-watchdog"; - }; - - regulators { - vdd_bcore: bcores-merged { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <4800000>; - regulator-max-microamp = <4800000>; - regulator-always-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2400000>; - regulator-max-microamp = <2400000>; - regulator-always-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1060000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <1500000>; - regulator-always-on; - }; - - vdd_bmem_bio: bmem-bio-merged { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ld09: ldo9 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spi0 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <&gpio 15 GPIO_ACTIVE_LOW>; - }; -}; - -ð0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", - "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", - "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", - "EN_VDD_SD", "SD_CD"; -}; diff --git a/configs/sifive_unleashed_defconfig b/configs/sifive_unleashed_defconfig index 59e58fcb6dd..e89d391b3d2 100644 --- a/configs/sifive_unleashed_defconfig +++ b/configs/sifive_unleashed_defconfig @@ -6,7 +6,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="hifive-unleashed-a00" +CONFIG_DEFAULT_DEVICE_TREE="sifive/hifive-unleashed-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe70 diff --git a/configs/sifive_unmatched_defconfig b/configs/sifive_unmatched_defconfig index 25c07d1e1ca..9e01a3e4608 100644 --- a/configs/sifive_unmatched_defconfig +++ b/configs/sifive_unmatched_defconfig @@ -7,7 +7,7 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00" +CONFIG_DEFAULT_DEVICE_TREE="sifive/hifive-unmatched-a00" CONFIG_DM_RESET=y CONFIG_SPL_MMC=y CONFIG_SPL_STACK=0x81cfe60 diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index e55a26ab8fd..5d0b08d3755 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -59,25 +59,25 @@ static const struct __prci_clock_ops sifive_fu540_prci_tlclksel_clk_ops = { /* List of clock controls provided by the PRCI */ static struct __prci_clock __prci_init_clocks_fu540[] = { - [PRCI_CLK_COREPLL] = { + [FU540_PRCI_CLK_COREPLL] = { .name = "corepll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_corepll_data, }, - [PRCI_CLK_DDRPLL] = { + [FU540_PRCI_CLK_DDRPLL] = { .name = "ddrpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_ddrpll_data, }, - [PRCI_CLK_GEMGXLPLL] = { + [FU540_PRCI_CLK_GEMGXLPLL] = { .name = "gemgxlpll", .parent_name = "hfclk", .ops = &sifive_fu540_prci_wrpll_clk_ops, .pwd = &__prci_gemgxlpll_data, }, - [PRCI_CLK_TLCLK] = { + [FU540_PRCI_CLK_TLCLK] = { .name = "tlclk", .parent_name = "corepll", .ops = &sifive_fu540_prci_tlclksel_clk_ops, diff --git a/include/dt-bindings/clock/sifive-fu540-prci.h b/include/dt-bindings/clock/sifive-fu540-prci.h deleted file mode 100644 index 6a0b70a37d7..00000000000 --- a/include/dt-bindings/clock/sifive-fu540-prci.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2018-2019 SiFive, Inc. - * Wesley Terpstra - * Paul Walmsley - */ - -#ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H -#define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H - -/* Clock indexes for use by Device Tree data and the PRCI driver */ - -#define PRCI_CLK_COREPLL 0 -#define PRCI_CLK_DDRPLL 1 -#define PRCI_CLK_GEMGXLPLL 2 -#define PRCI_CLK_TLCLK 3 - -#endif -- cgit v1.3.1 From 1ab6d0d6bd472944ea25c5db13dd221d6aeb6ac0 Mon Sep 17 00:00:00 2001 From: Vincent Stehlé Date: Mon, 9 Mar 2026 17:36:36 +0100 Subject: efi_loader: export efi_ecpt_guid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Export the ECPT GUID, to prepare accessing it from more than one location. The C file containing the GUID is compiled only when CONFIG_EFI_ECPT is set; gate the export accordingly. Signed-off-by: Vincent Stehlé Cc: Heinrich Schuchardt Cc: Ilias Apalodimas Cc: Tom Rini Reviewed-by: Ilias Apalodimas Reviewed-by: Heinrich Schuchardt --- include/efi_loader.h | 4 ++++ lib/efi_loader/efi_conformance.c | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 3e70ac07055..0ebc80e0af0 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -387,6 +387,10 @@ extern const efi_guid_t efi_guid_capsule_report; extern const efi_guid_t efi_guid_firmware_management_protocol; /* GUID for the ESRT */ extern const efi_guid_t efi_esrt_guid; +/* GUID for the ECPT */ +#if CONFIG_IS_ENABLED(EFI_ECPT) +extern const efi_guid_t efi_ecpt_guid; +#endif /* GUID of the SMBIOS table */ extern const efi_guid_t smbios_guid; extern const efi_guid_t smbios3_guid; diff --git a/lib/efi_loader/efi_conformance.c b/lib/efi_loader/efi_conformance.c index 2d31800ccb8..470141af483 100644 --- a/lib/efi_loader/efi_conformance.c +++ b/lib/efi_loader/efi_conformance.c @@ -12,7 +12,7 @@ #include #include -static const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; +const efi_guid_t efi_ecpt_guid = EFI_CONFORMANCE_PROFILES_TABLE_GUID; /** * efi_ecpt_register() - Install the ECPT system table. -- cgit v1.3.1 From 94c5c0835bccdb0763c25af7fdf72cdd2b9f7e5a Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Fri, 13 Mar 2026 12:20:37 +0100 Subject: efi_loader: avoid superfluous variable store writes on unchanged data Every SetVariable() call triggers efi_var_mem_ins() followed by efi_var_to_storage(), even when the variable value is not actually changing. This is unfriendly to flash-backed stores that suffer wear from unnecessary erase/write cycles. Add a change-detection path to efi_var_mem_ins(): when size2 == 0 (i.e. not an append) and the caller passes a non-NULL changep flag, look up the existing variable and compare attributes, length, time and data byte-by-byte. If everything matches, set *changep = false and return EFI_SUCCESS without touching the variable buffer. Both efi_set_variable_int() and efi_set_variable_runtime() now check the flag and skip efi_var_mem_del() / efi_var_to_storage() when nothing changed. Introduce efi_memcmp_runtime() - a runtime-safe byte-by-byte memory comparison helper, following the same pattern as the existing efi_memcpy_runtime(). The standard memcmp() is not available after ExitBootServices() and calling it from Linux will crash. Tested-by: Heinrich Schuchardt Reviewed-by: Heinrich Schuchardt Signed-off-by: Michal Simek Reviewed-by: Ilias Apalodimas --- include/efi_loader.h | 3 +++ include/efi_variable.h | 8 +++++++- lib/efi_loader/efi_runtime.c | 24 ++++++++++++++++++++++++ lib/efi_loader/efi_var_common.c | 2 +- lib/efi_loader/efi_var_mem.c | 29 ++++++++++++++++++++++++++++- lib/efi_loader/efi_variable.c | 27 ++++++++++++++++++--------- 6 files changed, 81 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/include/efi_loader.h b/include/efi_loader.h index 0ebc80e0af0..3a4d502631c 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1148,6 +1148,9 @@ struct pkcs7_message *efi_parse_pkcs7_header(const void *buf, /* runtime implementation of memcpy() */ void efi_memcpy_runtime(void *dest, const void *src, size_t n); +/* runtime implementation of memcmp() */ +int efi_memcmp_runtime(const void *s1, const void *s2, size_t n); + /* commonly used helper functions */ u16 *efi_create_indexed_name(u16 *buffer, size_t buffer_size, const char *name, unsigned int index); diff --git a/include/efi_variable.h b/include/efi_variable.h index fc1184e5ca1..c3229c717d8 100644 --- a/include/efi_variable.h +++ b/include/efi_variable.h @@ -216,6 +216,11 @@ void efi_var_mem_del(struct efi_var_entry *var); * The variable is appended without checking if a variable of the same name * already exists. The two data buffers are concatenated. * + * When @changep is non-NULL and @size2 is 0, the function compares the new + * value against an existing variable with the same name and vendor. If + * attributes and data are identical the insertion is skipped and *@changep + * is set to false, avoiding superfluous writes. + * * @variable_name: variable name * @vendor: GUID * @attributes: variable attributes @@ -224,13 +229,14 @@ void efi_var_mem_del(struct efi_var_entry *var); * @size2: size of the second data field * @data2: second data buffer * @time: time of authentication (as seconds since start of epoch) + * @changep: pointer to change flag (may be NULL) * Result: status code */ efi_status_t efi_var_mem_ins(const u16 *variable_name, const efi_guid_t *vendor, u32 attributes, const efi_uintn_t size1, const void *data1, const efi_uintn_t size2, const void *data2, - const u64 time); + const u64 time, bool *changep); /** * efi_var_mem_free() - determine free memory for variables diff --git a/lib/efi_loader/efi_runtime.c b/lib/efi_loader/efi_runtime.c index 35eb6a77766..73d4097464c 100644 --- a/lib/efi_loader/efi_runtime.c +++ b/lib/efi_loader/efi_runtime.c @@ -209,6 +209,30 @@ void __efi_runtime efi_memcpy_runtime(void *dest, const void *src, size_t n) *d++ = *s++; } +/** + * efi_memcmp_runtime() - compare memory areas + * + * At runtime memcmp() is not available. + * + * @s1: first memory area + * @s2: second memory area + * @n: number of bytes to compare + * Return: 0 if equal, negative if s1 < s2, positive if s1 > s2 + */ +int __efi_runtime efi_memcmp_runtime(const void *s1, const void *s2, size_t n) +{ + const u8 *pos1 = s1; + const u8 *pos2 = s2; + + for (; n; --n) { + if (*pos1 != *pos2) + return *pos1 - *pos2; + ++pos1; + ++pos2; + } + return 0; +} + /** * efi_update_table_header_crc32() - Update crc32 in table header * diff --git a/lib/efi_loader/efi_var_common.c b/lib/efi_loader/efi_var_common.c index c89a4fce4ff..d63c2d1b1cd 100644 --- a/lib/efi_loader/efi_var_common.c +++ b/lib/efi_loader/efi_var_common.c @@ -526,7 +526,7 @@ efi_status_t efi_var_restore(struct efi_var_file *buf, bool safe) continue; ret = efi_var_mem_ins(var->name, &var->guid, var->attr, var->length, data, 0, NULL, - var->time); + var->time, NULL); if (ret != EFI_SUCCESS) log_err("Failed to set EFI variable %ls\n", var->name); } diff --git a/lib/efi_loader/efi_var_mem.c b/lib/efi_loader/efi_var_mem.c index 31180df9e3a..8d5f99f4870 100644 --- a/lib/efi_loader/efi_var_mem.c +++ b/lib/efi_loader/efi_var_mem.c @@ -159,12 +159,39 @@ efi_status_t __efi_runtime efi_var_mem_ins( const efi_guid_t *vendor, u32 attributes, const efi_uintn_t size1, const void *data1, const efi_uintn_t size2, const void *data2, - const u64 time) + const u64 time, bool *changep) { u16 *data; struct efi_var_entry *var; u32 var_name_len; + if (changep) + *changep = true; + + /* + * If this is not an append (size2 == 0), check whether the variable + * already exists with identical attributes and data. When nothing + * changed we can skip the write and avoid superfluous erases. + */ + if (!size2 && changep) { + struct efi_var_entry *old; + + old = efi_var_mem_find(vendor, variable_name, NULL); + if (old && old->attr == attributes && + old->length == size1 && old->time == time) { + u16 *old_data; + + for (old_data = old->name; *old_data; ++old_data) + ; + ++old_data; + + if (!efi_memcmp_runtime(old_data, data1, size1)) { + *changep = false; + return EFI_SUCCESS; + } + } + } + var = (struct efi_var_entry *) ((uintptr_t)efi_var_buf + efi_var_buf->length); var_name_len = u16_strlen(variable_name) + 1; diff --git a/lib/efi_loader/efi_variable.c b/lib/efi_loader/efi_variable.c index 8512bc20f11..9923936c1b5 100644 --- a/lib/efi_loader/efi_variable.c +++ b/lib/efi_loader/efi_variable.c @@ -277,6 +277,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, struct efi_var_entry *var; efi_uintn_t ret; bool append, delete; + bool changed = false; u64 time = 0; enum efi_auth_var_type var_type; @@ -366,6 +367,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, if (delete) { /* EFI_NOT_FOUND has been handled before */ attributes = var->attr; + changed = true; ret = EFI_SUCCESS; } else if (append && var) { /* @@ -380,15 +382,19 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, ret = efi_var_mem_ins(variable_name, vendor, attributes & ~EFI_VARIABLE_APPEND_WRITE, var->length, old_data, data_size, data, - time); + time, &changed); } else { ret = efi_var_mem_ins(variable_name, vendor, attributes, - data_size, data, 0, NULL, time); + data_size, data, 0, NULL, time, + &changed); } if (ret != EFI_SUCCESS) return ret; + if (!changed) + return EFI_SUCCESS; + efi_var_mem_del(var); if (var_type == EFI_AUTH_VAR_PK) @@ -396,10 +402,7 @@ efi_status_t efi_set_variable_int(const u16 *variable_name, else ret = EFI_SUCCESS; - /* - * Write non-volatile EFI variables - * TODO: check if a value change has occured to avoid superfluous writes - */ + /* Write non-volatile EFI variables to storage */ if (attributes & EFI_VARIABLE_NON_VOLATILE) { if (IS_ENABLED(CONFIG_EFI_VARIABLE_NO_STORE)) return EFI_SUCCESS; @@ -498,6 +501,7 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, struct efi_var_entry *var; efi_uintn_t ret; bool append, delete; + bool changed = false; u64 time = 0; if (!IS_ENABLED(CONFIG_EFI_RT_VOLATILE_STORE)) @@ -549,6 +553,7 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, if (delete) { /* EFI_NOT_FOUND has been handled before */ attributes = var->attr; + changed = true; ret = EFI_SUCCESS; } else if (append && var) { u16 *old_data = (void *)((uintptr_t)var->name + @@ -556,15 +561,19 @@ efi_set_variable_runtime(u16 *variable_name, const efi_guid_t *vendor, ret = efi_var_mem_ins(variable_name, vendor, attributes, var->length, old_data, data_size, data, - time); + time, &changed); } else { ret = efi_var_mem_ins(variable_name, vendor, attributes, - data_size, data, 0, NULL, time); + data_size, data, 0, NULL, time, + &changed); } if (ret != EFI_SUCCESS) return ret; - /* We are always inserting new variables, get rid of the old copy */ + + if (!changed) + return EFI_SUCCESS; + efi_var_mem_del(var); return EFI_SUCCESS; -- cgit v1.3.1 From 8f83a4596677fe6a3f3b587b76d460644205a922 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Tue, 29 Jul 2025 18:07:22 +0200 Subject: cmd/exception: missing include string.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When building qemu_arm64_defconfig with CMD_EXCEPTION a build error occurs: In file included from cmd/arm/exception64.c:87: include/exception.h: In function ‘exception_complete’: include/exception.h:41:23: error: implicit declaration of function ‘strlen’ [-Wimplicit-function-declaration] 41 | len = strlen(argv[1]); | ^~~~~~ Add the missing include. Signed-off-by: Heinrich Schuchardt Reviewed-by: Ilias Apalodimas Reviewed-by: Tom Rini --- include/exception.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/exception.h b/include/exception.h index a7f21e73d75..0d4dff49954 100644 --- a/include/exception.h +++ b/include/exception.h @@ -6,6 +6,7 @@ */ #include +#include static int do_exception(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -- cgit v1.3.1 From e1cc7117b6302464977fffca3e2c05bf8f3f6c77 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Mon, 2 Mar 2026 13:20:02 +0800 Subject: imx9: scmi: Get DDR size through SM SCMI API System Manager(SM) has implemented the MISC protocol to retrieve DDR information. Using this API, U-Boot can obtain the DDR size dynamically instead of relying on static configuration macros. This change addresses the DDR ECC enabled case, where 1/8 of the total DDR size is reserved for ECC data. The scmi_misc_ddrinfo() returns the DDR size with EEC overhead already deducted. Implementation details: - Query the DDR size via scmi_misc_ddrinfo() - Replace direct REG_DDR_CS[0,1]_BNDS register reads with SCMI call - Switch from PHYS_SDRAM[x]_SIZE macros to runtime detection - For backward compatibility with older SM firmware, fall back to static PHYS_SDRAM[x]_SIZE configuration if the SCMI call fails Signed-off-by: Ye Li Signed-off-by: Alice Guo Reviewed-by: Peng Fan --- arch/arm/include/asm/mach-imx/sys_proto.h | 37 +++++++++++++++ arch/arm/mach-imx/imx9/scmi/soc.c | 75 +++++++++++++++++++++++++------ include/scmi_protocols.h | 3 +- 3 files changed, 100 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index 46da7a1eff5..13857b921a0 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -254,6 +254,43 @@ struct scmi_rom_passover_get_out { u32 passover[(sizeof(rom_passover_t) + 8) / 4]; }; +/** + * struct scmi_ddr_info_out - Get DDR memory region info + * @status: Error code + * @attributes: Region attributes: + * Bit[31] ECC enable. + * Set to 1 if ECC enabled. + * Set to 0 if ECC disabled or not configured. + * Bits[30:18] Reserved, must be zero. + * Bits[17:16] Number of DDR memory regions. + * Bits[15:11] Reserved, must be zero. + * Bits[10:8] Width. + * Bus width is 16 << this field. + * So 0=16, 1=32, 2=64, etc. + * Bits[7:5] Reserved, must be zero. + * Bits[4:0] DDR type. + * Set to 0 if LPDDR5. + * Set to 1 if LPDDR5X. + * Set to 2 if LPDDR4. + * Set to 3 if LPDDR4X + * @mts: DDR speed in megatransfers per second + * @startlow: The lower 32 bits of the physical start address of the region + * @starthigh: The upper 32 bits of the physical start address of the region + * @endlow: The lower 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + * @endhigh: The upper 32 bits of the physical end address of the region. This + * excludes any DDR used to store ECC data + */ +struct scmi_ddr_info_out { + s32 status; + u32 attributes; + u32 mts; + u32 startlow; + u32 starthigh; + u32 endlow; + u32 endhigh; +}; + #endif /* For i.MX ULP */ diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 17269ddd2fc..29232f3b391 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -58,6 +58,34 @@ uint32_t scmi_get_rom_data(rom_passover_t *rom_data) return 0; } +int scmi_misc_ddrinfo(u32 ddrc_id, struct scmi_ddr_info_out *out) +{ + u32 in = ddrc_id; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_IMX_MISC, + .message_id = SCMI_MISC_DDR_INFO_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)out, + .out_msg_sz = sizeof(*out), + }; + int ret; + struct udevice *dev; + + ret = uclass_get_device_by_name(UCLASS_CLK, "protocol@14", &dev); + if (ret) + return ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret != 0 || out->status != 0) { + printf("Failed to get ddr cfg, scmi_err = %d\n", + out->status); + return -EINVAL; + } + + return 0; +} + #if IS_ENABLED(CONFIG_ENV_IS_IN_MMC) __weak int board_mmc_get_env_dev(int devno) { @@ -335,25 +363,44 @@ void enable_caches(void) __weak int board_phys_sdram_size(phys_size_t *size) { + struct scmi_ddr_info_out ddr_info = {0}; + int ret; + u32 ddrc_id = 0, ddrc_num = 1; phys_size_t start, end; - phys_size_t val; if (!size) return -EINVAL; - val = readl(REG_DDR_CS0_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size = end - start; - - val = readl(REG_DDR_CS1_BNDS); - start = (val >> 16) << 24; - end = (val & 0xFFFF); - end = end ? end + 1 : 0; - end = end << 24; - *size += end - start; + *size = 0; + do { + ret = scmi_misc_ddrinfo(ddrc_id++, &ddr_info); + if (ret) { + /* if get DDR info failed, fall to default config */ + *size = PHYS_SDRAM_SIZE; +#ifdef PHYS_SDRAM_2_SIZE + *size += PHYS_SDRAM_2_SIZE; +#endif + return 0; + } else { + ddrc_num = ((ddr_info.attributes >> 16) & 0x3); + start = ddr_info.starthigh; + start <<= 32; + start += ddr_info.startlow; + + end = ddr_info.endhigh; + end <<= 32; + end += ddr_info.endlow; + + *size += end + 1 - start; + + debug("ddr info attr 0x%x, start 0x%x 0x%x, end 0x%x 0x%x, mts %u\n", + ddr_info.attributes, ddr_info.starthigh, ddr_info.startlow, + ddr_info.endhigh, ddr_info.endlow, ddr_info.mts); + } + } while (ddrc_id < ddrc_num); + + /* SM reports total DDR size, need remove secure memory */ + *size -= PHYS_SDRAM - 0x80000000; return 0; } diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index ecab021b472..555ffa0a61b 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -54,7 +54,8 @@ enum scmi_discovery_id { }; enum scmi_imx_misc_message_id { - SCMI_MISC_ROM_PASSOVER_GET = 0x7 + SCMI_MISC_ROM_PASSOVER_GET = 0x7, + SCMI_MISC_DDR_INFO_GET = 0x22, }; /* -- cgit v1.3.1 From d55cc91ab4745338494b7546b286d73913ec1a27 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 2 Mar 2026 13:20:14 +0800 Subject: board: nxp: imx952_evk: Add i.MX952 15x15 lpddr4x board support Add support for i.MX952 15x15 lpddr4x board support. Signed-off-by: Peng Fan Signed-off-by: Ye Li Signed-off-by: Alice Guo --- arch/arm/mach-imx/Makefile | 2 +- arch/arm/mach-imx/imx9/Kconfig | 12 +++ board/nxp/imx952_evk/Kconfig | 12 +++ board/nxp/imx952_evk/MAINTAINERS | 6 ++ board/nxp/imx952_evk/Makefile | 14 +++ board/nxp/imx952_evk/imx952_evk.c | 26 ++++++ board/nxp/imx952_evk/imx952_evk.env | 137 ++++++++++++++++++++++++++++ board/nxp/imx952_evk/spl.c | 113 +++++++++++++++++++++++ configs/imx952_evk_defconfig | 175 ++++++++++++++++++++++++++++++++++++ doc/board/nxp/imx952_evk.rst | 112 +++++++++++++++++++++++ doc/board/nxp/index.rst | 1 + include/configs/imx952_evk.h | 25 ++++++ 12 files changed, 634 insertions(+), 1 deletion(-) create mode 100644 board/nxp/imx952_evk/Kconfig create mode 100644 board/nxp/imx952_evk/MAINTAINERS create mode 100644 board/nxp/imx952_evk/Makefile create mode 100644 board/nxp/imx952_evk/imx952_evk.c create mode 100644 board/nxp/imx952_evk/imx952_evk.env create mode 100644 board/nxp/imx952_evk/spl.c create mode 100644 configs/imx952_evk_defconfig create mode 100644 doc/board/nxp/imx952_evk.rst create mode 100644 include/configs/imx952_evk.h (limited to 'include') diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 0f6e737c0b9..bf6820de655 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -223,7 +223,7 @@ endif ifeq ($(CONFIG_ARCH_IMX9)$(CONFIG_ARCH_IMX8ULP), y) -ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94))),) +ifneq ($(and $(CONFIG_BINMAN),$(or $(CONFIG_IMX95),$(CONFIG_IMX94),$(CONFIG_IMX952))),) SPL: spl/u-boot-spl.bin FORCE $(call if_changed,mkimage) diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 716940930a6..6e0958c0842 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -162,6 +162,17 @@ config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 +config TARGET_IMX952_EVK + bool "imx952_evk" + select IMX_SM_CPU + select IMX_SM_LMM + select IMX952 + select REGMAP + select SYSCON + imply BOOTSTD_BOOTCOMMAND + imply BOOTSTD_FULL + imply OF_UPSTREAM + endchoice source "board/nxp/imx91_evk/Kconfig" @@ -175,5 +186,6 @@ source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" source "board/toradex/smarc-imx95/Kconfig" +source "board/nxp/imx952_evk/Kconfig" endif diff --git a/board/nxp/imx952_evk/Kconfig b/board/nxp/imx952_evk/Kconfig new file mode 100644 index 00000000000..96f01323aca --- /dev/null +++ b/board/nxp/imx952_evk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX952_EVK + +config SYS_BOARD + default "imx952_evk" + +config SYS_VENDOR + default "nxp" + +config SYS_CONFIG_NAME + default "imx952_evk" + +endif diff --git a/board/nxp/imx952_evk/MAINTAINERS b/board/nxp/imx952_evk/MAINTAINERS new file mode 100644 index 00000000000..cc004f9467e --- /dev/null +++ b/board/nxp/imx952_evk/MAINTAINERS @@ -0,0 +1,6 @@ +i.MX952 EVK BOARD +M: Alice Guo +S: Maintained +F: board/nxp/imx952_evk/ +F: include/configs/imx952_evk.h +F: configs/imx952_evk_defconfig diff --git a/board/nxp/imx952_evk/Makefile b/board/nxp/imx952_evk/Makefile new file mode 100644 index 00000000000..1581721dc78 --- /dev/null +++ b/board/nxp/imx952_evk/Makefile @@ -0,0 +1,14 @@ +# +# Copyright 2025-2026 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Add include path for NXP device tree header files from Linux. +ccflags-y += -I$(srctree)/dts/upstream/src/arm64/freescale/ + +obj-y += imx952_evk.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/nxp/imx952_evk/imx952_evk.c b/board/nxp/imx952_evk/imx952_evk.c new file mode 100644 index 00000000000..2a61817939e --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include +#include +#include + +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC)) + board_late_mmc_env_init(); + + env_set("sec_boot", "no"); +#ifdef CONFIG_AHAB_BOOT + env_set("sec_boot", "yes"); +#endif + + return 0; +} diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env new file mode 100644 index 00000000000..6ecaf9724c1 --- /dev/null +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -0,0 +1,137 @@ +#ifdef CONFIG_ANDROID_SUPPORT +splashpos=m,m +splashimage=0x9FFF0000 +emmc_dev=0 +sd_dev=1 +#else + +#ifdef CONFIG_AHAB_BOOT +sec_boot=yes +#else +sec_boot=no +#endif + +jh_root_dtb=imx952-evk-root.dtb +jh_mmcboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + if run loadimage; then + run mmcboot; + else run jh_netboot; fi; +jh_netboot=setenv fdtfile ${jh_root_dtb}; + setenv jh_root_mem 0x58000000@0x90000000,0x300000000@0x180000000; + setenv jh_clk kvm.enable_virt_at_load=false cpuidle.off=1 clk_ignore_unused kvm-arm.mode=nvhe; run netboot; + +domu-android-auto=no +xenhyper_bootargs=console=dtuart dom0_mem=4096M dom0_max_vcpus=2 pci-passthrough=on +xenlinux_bootargs= +xenlinux_console=hvc0 earlycon=xen +xenlinux_addr=0x9c000000 +dom0fdt_file=CONFIG_DEFAULT_FDT_FILE +xenboot_common=${get_cmd} ${loadaddr} xen; + ${get_cmd} ${fdt_addr} ${dom0fdt_file}; + ${get_cmd} ${xenlinux_addr} ${image}; + fdt addr ${fdt_addr}; + fdt resize 256; + fdt mknode /chosen module@0; + fdt set /chosen/module@0 reg <0x00000000 ${xenlinux_addr} 0x00000000 0x${filesize}>; + fdt set /chosen/module@0 bootargs "${bootargs} ${xenlinux_bootargs}"; + fdt set /soc/bus@49000000/iommu@490d0000 status disabled; + fdt set /chosen/module@0 compatible "xen,linux-zimage" "xen,multiboot-module"; + setenv bootargs ${xenhyper_bootargs}; + booti ${loadaddr} - ${fdt_addr}; +xennetboot=setenv get_cmd dhcp;setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run netargs;run xenboot_common; +xenmmcboot=setenv get_cmd "fatload mmc ${mmcdev}:${mmcpart}";setenv console ${xenlinux_console};setenv jh_clk kvm.enable_virt_at_load=false clk_ignore_unused;run mmcargs;run xenboot_common; + +sr_ir_v2_cmd=cp.b ${fdtcontroladdr} ${fdt_addr_r} 0x10000; fdt addr ${fdt_addr_r}; + fdt set /soc/bus@44000000/mailbox@445b0000/sram@445b1000/scmi-sram-section@0 reg <0x00000000 0x00000080>; + fdt rm /soc/mailbox@47530000; + fdt rm /soc/usb@4c010010; + +initrd_addr=0x93800000 +emmc_dev=0 +sd_dev=1 +scriptaddr=0x93500000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +image=Image +splashimage=0xA0000000 +console=ttyLP0,115200 earlycon +fdt_addr_r=0x93000000 +fdt_addr=0x93000000 +cntr_addr=0xA8000000 +cntr_file=os_cntr_signed.bin +boot_fit=no +fdtfile=CONFIG_DEFAULT_FDT_FILE +bootm_size=0x10000000 +mmcdev=CONFIG_SYS_MMC_ENV_DEV +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=${mmcroot} +prepare_mcore=setenv mcore_args pd_ignore_unused; +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} +loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} +auth_os=booti ${cntr_addr} +boot_os=booti ${loadaddr} - ${fdt_addr_r}; +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${sec_boot} = yes; then + run auth_os; + else + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if run loadfdt; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +netargs=setenv bootargs ${jh_clk} ${mcore_args} console=${console} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if test ${sec_boot} = yes; then + ${get_cmd} ${cntr_addr} ${cntr_file}; + run auth_os; + else + ${get_cmd} ${loadaddr} ${image}; + if test ${boot_fit} = yes || test ${boot_fit} = try; then + bootm ${loadaddr}; + else + if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then + run boot_os; + else + echo WARN: Cannot load the DT; + fi; + fi; + fi; +bsp_bootcmd=echo Running BSP bootcmd ...; + mmc dev ${mmcdev}; if mmc rescan; then + if run loadbootscript; then + run bootscript; + else + if test ${sec_boot} = yes; then + if run loadcntr; then + run mmcboot; + else run netboot; + fi; + else + if run loadimage; then + run mmcboot; + else run netboot; + fi; + fi; + fi; + fi; + +#endif diff --git a/board/nxp/imx952_evk/spl.c b/board/nxp/imx952_evk/spl.c new file mode 100644 index 00000000000..de9256dc267 --- /dev/null +++ b/board/nxp/imx952_evk/spl.c @@ -0,0 +1,113 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025-2026 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + case USB2_BOOT: + return BOOT_DEVICE_BOARD; + case QSPI_BOOT: + return BOOT_DEVICE_SPI; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + puts("Normal Boot\n"); + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +static void xspi_nor_reset(void) +{ + int ret; + struct gpio_desc desc; + + ret = dm_gpio_lookup_name("GPIO5_11", &desc); + if (ret) { + printf("%s lookup GPIO5_11 failed ret = %d\n", __func__, ret); + return; + } + + ret = dm_gpio_request(&desc, "XSPI_RST_B"); + if (ret) { + printf("%s request XSPI_RST_B failed ret = %d\n", __func__, ret); + return; + } + + /* assert the XSPI_RST_B */ + dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE | GPIOD_ACTIVE_LOW); + udelay(200); /* 50 ns at least, so use 200ns */ + dm_gpio_set_value(&desc, 0); /* deassert the XSPI_RST_B */ +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + +#ifdef CONFIG_SPL_RECOVER_DATA_SECTION + if (IS_ENABLED(CONFIG_SPL_BUILD)) + spl_save_restore_data(); +#endif + + timer_init(); + + /* Need dm_init() to run before any SCMI calls can be made. */ + spl_early_init(); + + /* Need enable SCMI drivers and ELE driver before enabling console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* if MU not probed, nothing can output, just hang here */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + xspi_nor_reset(); + + board_init_r(NULL, 0); +} + +#ifdef CONFIG_ANDROID_SUPPORT +int board_get_emmc_id(void) +{ + return 0; +} +#endif diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig new file mode 100644 index 00000000000..a700aea67a1 --- /dev/null +++ b/configs/imx952_evk_defconfig @@ -0,0 +1,175 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="imx952_evk" +CONFIG_NR_DRAM_BANKS=3 +CONFIG_SF_DEFAULT_SPEED=200000000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx952-evk" +CONFIG_TARGET_IMX952_EVK=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_SPL_OF_LIBFDT_ASSUME_MASK=0x0 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_OF_BOARD_FIXUP=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" +CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_OPTEE_RPMB=y +CONFIG_CMD_OPTEE=y +CONFIG_CMD_PCI=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +# CONFIG_BOOTDEV_ETH is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYS_RX_ETH_BUFFER=8 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +# CONFIG_SCMI_AGENT_SMCCC is not set +# CONFIG_SCMI_AGENT_OPTEE is not set +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_ADP5585_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_SOFT_RESET=y +CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MT35XU=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PCIE_DW_IMX=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_CMD_POWEROFF=y +CONFIG_SYSRESET_PSCI=y +CONFIG_TEE=y +CONFIG_OPTEE=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="FSL" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/doc/board/nxp/imx952_evk.rst b/doc/board/nxp/imx952_evk.rst new file mode 100644 index 00000000000..f5f4d8d4b0c --- /dev/null +++ b/doc/board/nxp/imx952_evk.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +imx952_evk +========== + +U-Boot for the NXP i.MX952 15x15 LPDDR4X EVK board + +Quick Start +----------- + +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Get ahab-container.img +---------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-ele-imx-2.0.5-50c4793.bin + $ sh firmware-ele-imx-2.0.5-50c4793.bin --auto-accept + $ cp firmware-ele-imx-2.0.5-50c4793/mx952a0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: srctree is U-Boot source directory + +.. code-block:: bash + + $ wget https://nl2-nxrm.sw.nxp.com/repository/IMX_Yocto_Internal_Mirror_Recent/firmware-imx-8.32-c0491e4.bin + $ sh firmware-imx-8.32-c0491e4.bin --auto-accept + $ cp firmware-imx-8.32-c0491e4/firmware/ddr/synopsys/lpddr4x*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: srctree is U-Boot source directory +Get OEI from: https://github.com/nxp-imx/imx-oei +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone https://github.com/nxp-imx/imx-oei/ -b lf-6.18.2-imx952-er1 + $ cd imx-oei + $ make board=mx952lp4x-15 oei=ddr DEBUG=1 all + $ cp build/mx952lp4x-15/ddr/oei-m33-ddr.bin $(srctree) + +Get and Build System Manager Image +---------------------------------- + +Note: srctree is U-Boot source directory +Get System Manager from: https://github.com/nxp-imx/imx-sm +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ sudo apt -y install make gcc g++-multilib srecord + $ wget https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ tar xvf arm-gnu-toolchain-14.2.rel1-x86_64-arm-none-eabi.tar.xz + $ export TOOLS=$PWD + $ git clone https://github.com/nxp-imx/imx-sm/ -b lf-6.18.2-imx952-er1 + $ cd imx-sm + $ make config=mx952evk all + $ cp build/mx952evk/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf-6.18.2-imx952-er1 + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ unset LDFLAGS + $ unset AS + $ git clone https://github.com/nxp-imx/imx-atf/ -b lf-6.18.2-imx952-er1 + $ cd imx-atf + $ make PLAT=imx952 bl31 + $ cp build/imx952/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-poky-linux- + $ make imx952_evk_defconfig + $ make + +Copy flash.bin to the MicroSD card: + +.. code-block:: bash + + $ sudo dd if=flash.bin of=/dev/sd[x] bs=1k seek=32 conv=fsync + +Boot +---- + +Set i.MX952 boot device to MicroSD card diff --git a/doc/board/nxp/index.rst b/doc/board/nxp/index.rst index 01d3468a47d..8cd24aecf33 100644 --- a/doc/board/nxp/index.rst +++ b/doc/board/nxp/index.rst @@ -19,6 +19,7 @@ NXP Semiconductors imx93_frdm imx943_evk imx95_evk + imx952_evk imxrt1020-evk imxrt1050-evk imxrt1170-evk diff --git a/include/configs/imx952_evk.h b/include/configs/imx952_evk.h new file mode 100644 index 00000000000..4ff56eb8adf --- /dev/null +++ b/include/configs/imx952_evk.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2025-2026 NXP + */ + +#ifndef __IMX952_EVK_H +#define __IMX952_EVK_H + +#include +#include +#include + +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 + +#define PHYS_SDRAM_SIZE 0x70000000 /* 2GB - 256MB DDR */ +#define PHYS_SDRAM_2_SIZE 0x380000000 /* 14GB */ + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif -- cgit v1.3.1 From b51e59c8b34c780e28728bc0cb58783855c7ffbf Mon Sep 17 00:00:00 2001 From: Jamie Gibbons Date: Fri, 16 Jan 2026 14:08:30 +0000 Subject: riscv: Add support for BeagleV-Fire Bring U-Boot support for the BeagleV-Fire by adding a device tree and supporting board files etc. Signed-off-by: Jamie Gibbons Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 4 ++ board/beagle/beaglev_fire/Kconfig | 43 ++++++++++++ board/beagle/beaglev_fire/MAINTAINERS | 7 ++ board/beagle/beaglev_fire/Makefile | 6 ++ board/beagle/beaglev_fire/beaglev_fire.c | 117 +++++++++++++++++++++++++++++++ configs/beaglev_fire_defconfig | 29 ++++++++ include/configs/beaglev_fire.h | 57 +++++++++++++++ 7 files changed, 263 insertions(+) create mode 100644 board/beagle/beaglev_fire/Kconfig create mode 100644 board/beagle/beaglev_fire/MAINTAINERS create mode 100644 board/beagle/beaglev_fire/Makefile create mode 100644 board/beagle/beaglev_fire/beaglev_fire.c create mode 100644 configs/beaglev_fire_defconfig create mode 100644 include/configs/beaglev_fire.h (limited to 'include') diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 79867656b15..ad7589123c6 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -17,6 +17,9 @@ config TARGET_ANDES_VOYAGER config TARGET_BANANAPI_F3 bool "Support BananaPi F3 Board" +config TARGET_BEAGLEBOARD_BEAGLEVFIRE + bool "Support BeagleBoard BeagleV-Fire Board (based on Microchip MPFS)" + config TARGET_K230_CANMV bool "Support K230 CanMV Board" @@ -106,6 +109,7 @@ config SPL_ZERO_MEM_BEFORE_USE source "board/andestech/ae350/Kconfig" source "board/andestech/voyager/Kconfig" source "board/aspeed/ibex_ast2700/Kconfig" +source "board/beagle/beaglev_fire/Kconfig" source "board/canaan/k230_canmv/Kconfig" source "board/emulation/qemu-riscv/Kconfig" source "board/microchip/mpfs_generic/Kconfig" diff --git a/board/beagle/beaglev_fire/Kconfig b/board/beagle/beaglev_fire/Kconfig new file mode 100644 index 00000000000..7a8ecac8703 --- /dev/null +++ b/board/beagle/beaglev_fire/Kconfig @@ -0,0 +1,43 @@ +if TARGET_BEAGLEBOARD_BEAGLEVFIRE + +config SYS_BOARD + default "beaglev_fire" + +config SYS_VENDOR + default "beagle" + +config SYS_CPU + default "mpfs" + +config SYS_CONFIG_NAME + default "beaglev_fire" + +config TEXT_BASE + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select MICROCHIP_MPFS + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + imply SMP + imply CMD_DHCP + imply CMD_EXT2 + imply CMD_EXT4 + imply CMD_FAT + imply CMD_FS_GENERIC + imply CMD_NET + imply CMD_PING + imply CMD_MMC + imply DOS_PARTITION + imply EFI_PARTITION + imply IP_DYN + imply ISO_PARTITION + imply PHY_LIB + imply PHY_VITESSE + imply DM_MAILBOX + imply MPFS_MBOX + imply MISC + imply MPFS_SYSCONTROLLER +endif diff --git a/board/beagle/beaglev_fire/MAINTAINERS b/board/beagle/beaglev_fire/MAINTAINERS new file mode 100644 index 00000000000..a5dad93ee99 --- /dev/null +++ b/board/beagle/beaglev_fire/MAINTAINERS @@ -0,0 +1,7 @@ +BeagleBoard MPFS BeagleV-Fire +M: Cyril Jean +M: Jamie Gibbons +S: Maintained +F: board/beagle/beaglev_fire/ +F: include/configs/beaglev_fire.h +F: configs/beaglev_fire_defconfig \ No newline at end of file diff --git a/board/beagle/beaglev_fire/Makefile b/board/beagle/beaglev_fire/Makefile new file mode 100644 index 00000000000..a4109a8aad4 --- /dev/null +++ b/board/beagle/beaglev_fire/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2023 Microchip Technology Inc. +# + +obj-y += beaglev_fire.o \ No newline at end of file diff --git a/board/beagle/beaglev_fire/beaglev_fire.c b/board/beagle/beaglev_fire/beaglev_fire.c new file mode 100644 index 00000000000..b2f18c455b7 --- /dev/null +++ b/board/beagle/beaglev_fire/beaglev_fire.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2023 Microchip Technology Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define MPFS_SYSREG_SOFT_RESET ((unsigned int *)0x20002088) +#define PERIPH_RESET_VALUE 0x800001e8u + +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) +static unsigned char mac_addr[6]; +#endif + +int board_init(void) +{ + /* For now nothing to do here. */ + + return 0; +} + +int board_early_init_f(void) +{ + unsigned int val; + + /* Reset uart, mmc peripheral */ + val = readl(MPFS_SYSREG_SOFT_RESET); + val = (val & ~(PERIPH_RESET_VALUE)); + writel(val, MPFS_SYSREG_SOFT_RESET); + + return 0; +} + +int board_late_init(void) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + u8 device_serial_number[16] = {0}; + void *blob = (void *)gd->fdt_blob; + struct udevice *dev; + struct mpfs_sys_serv *sys_serv_priv; + + ret = uclass_get_device_by_name(UCLASS_MISC, "syscontroller", &dev); + if (ret) { + debug("%s: system controller setup failed\n", __func__); + return ret; + } + + sys_serv_priv = devm_kzalloc(dev, sizeof(*sys_serv_priv), GFP_KERNEL); + if (!sys_serv_priv) + return -ENOMEM; + + sys_serv_priv->dev = dev; + + sys_serv_priv->sys_controller = mpfs_syscontroller_get(dev); + ret = IS_ERR(sys_serv_priv->sys_controller); + if (ret) { + debug("%s: Failed to register system controller sub device ret=%d\n", __func__, ret); + return -ENODEV; + } + + ret = mpfs_syscontroller_read_sernum(sys_serv_priv, device_serial_number); + if (ret) { + printf("Cannot read device serial number\n"); + return -EINVAL; + } + + /* Update MAC address with device serial number */ + mac_addr[0] = 0x00; + mac_addr[1] = 0x04; + mac_addr[2] = 0xA3; + mac_addr[3] = device_serial_number[2]; + mac_addr[4] = device_serial_number[1]; + mac_addr[5] = device_serial_number[0]; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + + mpfs_syscontroller_process_dtbo(sys_serv_priv); +#endif + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ +#if IS_ENABLED(CONFIG_MPFS_SYSCONTROLLER) + u32 ret; + int node; + + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } +#endif + + return 0; +} \ No newline at end of file diff --git a/configs/beaglev_fire_defconfig b/configs/beaglev_fire_defconfig new file mode 100644 index 00000000000..9ebb08abbfe --- /dev/null +++ b/configs/beaglev_fire_defconfig @@ -0,0 +1,29 @@ +CONFIG_RISCV=y +CONFIG_SYS_MALLOC_LEN=0x800000 +CONFIG_SYS_MALLOC_F_LEN=0x2800 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="microchip/mpfs-beaglev-fire" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_BOOTM_LEN=0x4000000 +CONFIG_SYS_LOAD_ADDR=0x80200000 +CONFIG_TARGET_BEAGLEBOARD_BEAGLEVFIRE=y +CONFIG_ARCH_RV64I=y +CONFIG_RISCV_SMODE=y +CONFIG_FIT=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_DEFAULT_FDT_FILE="microchip/mpfs-beaglev-fire.dtb" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=282 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_SYS_PROMPT="RISC-V # " +CONFIG_CMD_GPIO=y +CONFIG_OF_UPSTREAM=y +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_MPFS_GPIO=y +CONFIG_MMC_SPI=y +CONFIG_SYSRESET=y diff --git a/include/configs/beaglev_fire.h b/include/configs/beaglev_fire.h new file mode 100644 index 00000000000..e3ee0f02f2d --- /dev/null +++ b/include/configs/beaglev_fire.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023 Microchip Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 + +/* Environment options */ + +#if defined(CONFIG_CMD_DHCP) +#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +#define BOOT_TARGET_DEVICES_DHCP(func) +#endif + +#if defined(CONFIG_CMD_MMC) +#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_DEVICES_MMC(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_DEVICES_MMC(func)\ + BOOT_TARGET_DEVICES_DHCP(func) + +#define BOOTENV_DESIGN_OVERLAYS \ + "design_overlays=" \ + "if test -n ${no_of_overlays}; then " \ + "setenv inc 1; " \ + "setenv idx 0; " \ + "fdt resize ${dtbo_size}; " \ + "while test $idx -ne ${no_of_overlays}; do " \ + "setenv dtbo_name dtbo_image${idx}; " \ + "setenv fdt_cmd \"fdt apply $\"$dtbo_name; " \ + "run fdt_cmd; " \ + "setexpr idx $inc + $idx; " \ + "done; " \ + "fi;\0 " \ + +#include + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootm_size=0x10000000\0" \ + "kernel_addr_r=0x80200000\0" \ + "fdt_addr_r=0x8a000000\0" \ + "fdtoverlay_addr_r=0x8a080000\0" \ + "ramdisk_addr_r=0x8aa00000\0" \ + "scriptaddr=0x8e000000\0" \ + BOOTENV_DESIGN_OVERLAYS \ + BOOTENV \ + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 290d17490e79abb108ee081ce43d51027814487f Mon Sep 17 00:00:00 2001 From: Irving-CH Lin Date: Tue, 3 Mar 2026 13:54:54 -0600 Subject: dt-bindings: clock: Add MediaTek MT8189 clock Add IDs for the clocks of MediaTek MT8189 SoC. Signed-off-by: Irving-CH Lin Reviewed-by: Julien Stephan Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-6-ee85f8dd2f0d@baylibre.com Signed-off-by: David Lechner --- include/dt-bindings/clock/mediatek,mt8189-clk.h | 580 ++++++++++++++++++++++++ 1 file changed, 580 insertions(+) create mode 100644 include/dt-bindings/clock/mediatek,mt8189-clk.h (limited to 'include') diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h new file mode 100644 index 00000000000..ffbc1814f28 --- /dev/null +++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h @@ -0,0 +1,580 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#ifndef _DT_BINDINGS_CLK_MT8189_H +#define _DT_BINDINGS_CLK_MT8189_H + +/* TOPCKGEN */ +#define CLK_TOP_AXI_SEL 0 +#define CLK_TOP_AXI_PERI_SEL 1 +#define CLK_TOP_AXI_U_SEL 2 +#define CLK_TOP_BUS_AXIMEM_SEL 3 +#define CLK_TOP_DISP0_SEL 4 +#define CLK_TOP_MMINFRA_SEL 5 +#define CLK_TOP_UART_SEL 6 +#define CLK_TOP_SPI0_SEL 7 +#define CLK_TOP_SPI1_SEL 8 +#define CLK_TOP_SPI2_SEL 9 +#define CLK_TOP_SPI3_SEL 10 +#define CLK_TOP_SPI4_SEL 11 +#define CLK_TOP_SPI5_SEL 12 +#define CLK_TOP_MSDC_MACRO_0P_SEL 13 +#define CLK_TOP_MSDC50_0_HCLK_SEL 14 +#define CLK_TOP_MSDC50_0_SEL 15 +#define CLK_TOP_AES_MSDCFDE_SEL 16 +#define CLK_TOP_MSDC_MACRO_1P_SEL 17 +#define CLK_TOP_MSDC30_1_SEL 18 +#define CLK_TOP_MSDC30_1_HCLK_SEL 19 +#define CLK_TOP_MSDC_MACRO_2P_SEL 20 +#define CLK_TOP_MSDC30_2_SEL 21 +#define CLK_TOP_MSDC30_2_HCLK_SEL 22 +#define CLK_TOP_AUD_INTBUS_SEL 23 +#define CLK_TOP_ATB_SEL 24 +#define CLK_TOP_DISP_PWM_SEL 25 +#define CLK_TOP_USB_TOP_P0_SEL 26 +#define CLK_TOP_USB_XHCI_P0_SEL 27 +#define CLK_TOP_USB_TOP_P1_SEL 28 +#define CLK_TOP_USB_XHCI_P1_SEL 29 +#define CLK_TOP_USB_TOP_P2_SEL 30 +#define CLK_TOP_USB_XHCI_P2_SEL 31 +#define CLK_TOP_USB_TOP_P3_SEL 32 +#define CLK_TOP_USB_XHCI_P3_SEL 33 +#define CLK_TOP_USB_TOP_P4_SEL 34 +#define CLK_TOP_USB_XHCI_P4_SEL 35 +#define CLK_TOP_I2C_SEL 36 +#define CLK_TOP_SENINF_SEL 37 +#define CLK_TOP_SENINF1_SEL 38 +#define CLK_TOP_AUD_ENGEN1_SEL 39 +#define CLK_TOP_AUD_ENGEN2_SEL 40 +#define CLK_TOP_AES_UFSFDE_SEL 41 +#define CLK_TOP_U_SEL 42 +#define CLK_TOP_U_MBIST_SEL 43 +#define CLK_TOP_AUD_1_SEL 44 +#define CLK_TOP_AUD_2_SEL 45 +#define CLK_TOP_VENC_SEL 46 +#define CLK_TOP_VDEC_SEL 47 +#define CLK_TOP_PWM_SEL 48 +#define CLK_TOP_AUDIO_H_SEL 49 +#define CLK_TOP_MCUPM_SEL 50 +#define CLK_TOP_MEM_SUB_SEL 51 +#define CLK_TOP_MEM_SUB_PERI_SEL 52 +#define CLK_TOP_MEM_SUB_U_SEL 53 +#define CLK_TOP_EMI_N_SEL 54 +#define CLK_TOP_DSI_OCC_SEL 55 +#define CLK_TOP_AP2CONN_HOST_SEL 56 +#define CLK_TOP_IMG1_SEL 57 +#define CLK_TOP_IPE_SEL 58 +#define CLK_TOP_CAM_SEL 59 +#define CLK_TOP_CAMTM_SEL 60 +#define CLK_TOP_DSP_SEL 61 +#define CLK_TOP_SR_PKA_SEL 62 +#define CLK_TOP_DXCC_SEL 63 +#define CLK_TOP_MFG_REF_SEL 64 +#define CLK_TOP_MDP0_SEL 65 +#define CLK_TOP_DP_SEL 66 +#define CLK_TOP_EDP_SEL 67 +#define CLK_TOP_EDP_FAVT_SEL 68 +#define CLK_TOP_ETH_250M_SEL 69 +#define CLK_TOP_ETH_62P4M_PTP_SEL 70 +#define CLK_TOP_ETH_50M_RMII_SEL 71 +#define CLK_TOP_SFLASH_SEL 72 +#define CLK_TOP_GCPU_SEL 73 +#define CLK_TOP_MAC_TL_SEL 74 +#define CLK_TOP_VDSTX_DG_CTS_SEL 75 +#define CLK_TOP_PLL_DPIX_SEL 76 +#define CLK_TOP_ECC_SEL 77 +#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78 +#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79 +#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80 +#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81 +#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82 +#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83 +#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84 +#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85 +#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86 +#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87 +#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88 +#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89 +#define CLK_TOP_APLL_FMI2S_MCK_SEL 90 +#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91 +#define CLK_TOP_MFG_SEL_MFGPLL 92 +#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93 +#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95 +#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96 +#define CLK_TOP_APLL12_CK_DIV_FMI2S 97 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98 +#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99 +#define CLK_TOP_MAINPLL_D3 100 +#define CLK_TOP_MAINPLL_D4 101 +#define CLK_TOP_MAINPLL_D4_D2 102 +#define CLK_TOP_MAINPLL_D4_D4 103 +#define CLK_TOP_MAINPLL_D4_D8 104 +#define CLK_TOP_MAINPLL_D5 105 +#define CLK_TOP_MAINPLL_D5_D2 106 +#define CLK_TOP_MAINPLL_D5_D4 107 +#define CLK_TOP_MAINPLL_D5_D8 108 +#define CLK_TOP_MAINPLL_D6 109 +#define CLK_TOP_MAINPLL_D6_D2 110 +#define CLK_TOP_MAINPLL_D6_D4 111 +#define CLK_TOP_MAINPLL_D6_D8 112 +#define CLK_TOP_MAINPLL_D7 113 +#define CLK_TOP_MAINPLL_D7_D2 114 +#define CLK_TOP_MAINPLL_D7_D4 115 +#define CLK_TOP_MAINPLL_D7_D8 116 +#define CLK_TOP_MAINPLL_D9 117 +#define CLK_TOP_UNIVPLL_D2 118 +#define CLK_TOP_UNIVPLL_D3 119 +#define CLK_TOP_UNIVPLL_D4 120 +#define CLK_TOP_UNIVPLL_D4_D2 121 +#define CLK_TOP_UNIVPLL_D4_D4 122 +#define CLK_TOP_UNIVPLL_D4_D8 123 +#define CLK_TOP_UNIVPLL_D5 124 +#define CLK_TOP_UNIVPLL_D5_D2 125 +#define CLK_TOP_UNIVPLL_D5_D4 126 +#define CLK_TOP_UNIVPLL_D6 127 +#define CLK_TOP_UNIVPLL_D6_D2 128 +#define CLK_TOP_UNIVPLL_D6_D4 129 +#define CLK_TOP_UNIVPLL_D6_D8 130 +#define CLK_TOP_UNIVPLL_D6_D16 131 +#define CLK_TOP_UNIVPLL_D7 132 +#define CLK_TOP_UNIVPLL_D7_D2 133 +#define CLK_TOP_UNIVPLL_D7_D3 134 +#define CLK_TOP_LVDSTX_DG_CTS 135 +#define CLK_TOP_UNIVPLL_192M 136 +#define CLK_TOP_UNIVPLL_192M_D2 137 +#define CLK_TOP_UNIVPLL_192M_D4 138 +#define CLK_TOP_UNIVPLL_192M_D8 139 +#define CLK_TOP_UNIVPLL_192M_D10 140 +#define CLK_TOP_UNIVPLL_192M_D16 141 +#define CLK_TOP_UNIVPLL_192M_D32 142 +#define CLK_TOP_APLL1_D2 143 +#define CLK_TOP_APLL1_D4 144 +#define CLK_TOP_APLL1_D8 145 +#define CLK_TOP_APLL1_D3 146 +#define CLK_TOP_APLL2_D2 147 +#define CLK_TOP_APLL2_D4 148 +#define CLK_TOP_APLL2_D8 149 +#define CLK_TOP_APLL2_D3 150 +#define CLK_TOP_MMPLL_D4 151 +#define CLK_TOP_MMPLL_D4_D2 152 +#define CLK_TOP_MMPLL_D4_D4 153 +#define CLK_TOP_VPLL_DPIX 154 +#define CLK_TOP_MMPLL_D5 155 +#define CLK_TOP_MMPLL_D5_D2 156 +#define CLK_TOP_MMPLL_D5_D4 157 +#define CLK_TOP_MMPLL_D6 158 +#define CLK_TOP_MMPLL_D6_D2 159 +#define CLK_TOP_MMPLL_D7 160 +#define CLK_TOP_MMPLL_D9 161 +#define CLK_TOP_TVDPLL1_D2 162 +#define CLK_TOP_TVDPLL1_D4 163 +#define CLK_TOP_TVDPLL1_D8 164 +#define CLK_TOP_TVDPLL1_D16 165 +#define CLK_TOP_TVDPLL2_D2 166 +#define CLK_TOP_TVDPLL2_D4 167 +#define CLK_TOP_TVDPLL2_D8 168 +#define CLK_TOP_TVDPLL2_D16 169 +#define CLK_TOP_ETHPLL_D2 170 +#define CLK_TOP_ETHPLL_D8 171 +#define CLK_TOP_ETHPLL_D10 172 +#define CLK_TOP_MSDCPLL_D2 173 +#define CLK_TOP_VOWPLL 174 +#define CLK_TOP_UFSPLL_D2 175 +#define CLK_TOP_F26M_CK_D2 176 +#define CLK_TOP_OSC_D2 177 +#define CLK_TOP_OSC_D4 178 +#define CLK_TOP_OSC_D8 179 +#define CLK_TOP_OSC_D16 180 +#define CLK_TOP_OSC_D3 181 +#define CLK_TOP_OSC_D7 182 +#define CLK_TOP_OSC_D10 183 +#define CLK_TOP_OSC_D20 184 +#define CLK_TOP_FMCNT_P0_EN 185 +#define CLK_TOP_FMCNT_P1_EN 186 +#define CLK_TOP_FMCNT_P2_EN 187 +#define CLK_TOP_FMCNT_P3_EN 188 +#define CLK_TOP_FMCNT_P4_EN 189 +#define CLK_TOP_USB_F26M_CK_EN 190 +#define CLK_TOP_SSPXTP_F26M_CK_EN 191 +#define CLK_TOP_USB2_PHY_RF_P0_EN 192 +#define CLK_TOP_USB2_PHY_RF_P1_EN 193 +#define CLK_TOP_USB2_PHY_RF_P2_EN 194 +#define CLK_TOP_USB2_PHY_RF_P3_EN 195 +#define CLK_TOP_USB2_PHY_RF_P4_EN 196 +#define CLK_TOP_USB2_26M_CK_P0_EN 197 +#define CLK_TOP_USB2_26M_CK_P1_EN 198 +#define CLK_TOP_USB2_26M_CK_P2_EN 199 +#define CLK_TOP_USB2_26M_CK_P3_EN 200 +#define CLK_TOP_USB2_26M_CK_P4_EN 201 +#define CLK_TOP_F26M_CK_EN 202 +#define CLK_TOP_AP2CON_EN 203 +#define CLK_TOP_EINT_N_EN 204 +#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 205 +#define CLK_TOP_DRAMULP_CK_EN 206 +#define CLK_TOP_EINT_E_EN 207 +#define CLK_TOP_EINT_W_EN 208 +#define CLK_TOP_EINT_S_EN 209 + +/* INFRACFG_AO */ +#define CLK_IFRAO_CQ_DMA_FPC 0 +#define CLK_IFRAO_DEBUGSYS 1 +#define CLK_IFRAO_DBG_TRACE 2 +#define CLK_IFRAO_CQ_DMA 3 + +/* APMIXEDSYS */ +#define CLK_APMIXED_ARMPLL_LL 0 +#define CLK_APMIXED_ARMPLL_BL 1 +#define CLK_APMIXED_CCIPLL 2 +#define CLK_APMIXED_MAINPLL 3 +#define CLK_APMIXED_UNIVPLL 4 +#define CLK_APMIXED_MMPLL 5 +#define CLK_APMIXED_MFGPLL 6 +#define CLK_APMIXED_APLL1 7 +#define CLK_APMIXED_APLL2 8 +#define CLK_APMIXED_EMIPLL 9 +#define CLK_APMIXED_APUPLL2 10 +#define CLK_APMIXED_APUPLL 11 +#define CLK_APMIXED_TVDPLL1 12 +#define CLK_APMIXED_TVDPLL2 13 +#define CLK_APMIXED_ETHPLL 14 +#define CLK_APMIXED_MSDCPLL 15 +#define CLK_APMIXED_UFSPLL 16 + +/* PERICFG_AO */ +#define CLK_PERAO_UART0 0 +#define CLK_PERAO_UART1 1 +#define CLK_PERAO_UART2 2 +#define CLK_PERAO_UART3 3 +#define CLK_PERAO_PWM_H 4 +#define CLK_PERAO_PWM_B 5 +#define CLK_PERAO_PWM_FB1 6 +#define CLK_PERAO_PWM_FB2 7 +#define CLK_PERAO_PWM_FB3 8 +#define CLK_PERAO_PWM_FB4 9 +#define CLK_PERAO_DISP_PWM0 10 +#define CLK_PERAO_DISP_PWM1 11 +#define CLK_PERAO_SPI0_B 12 +#define CLK_PERAO_SPI1_B 13 +#define CLK_PERAO_SPI2_B 14 +#define CLK_PERAO_SPI3_B 15 +#define CLK_PERAO_SPI4_B 16 +#define CLK_PERAO_SPI5_B 17 +#define CLK_PERAO_SPI0_H 18 +#define CLK_PERAO_SPI1_H 19 +#define CLK_PERAO_SPI2_H 20 +#define CLK_PERAO_SPI3_H 21 +#define CLK_PERAO_SPI4_H 22 +#define CLK_PERAO_SPI5_H 23 +#define CLK_PERAO_AXI 24 +#define CLK_PERAO_AHB_APB 25 +#define CLK_PERAO_TL 26 +#define CLK_PERAO_REF 27 +#define CLK_PERAO_I2C 28 +#define CLK_PERAO_DMA_B 29 +#define CLK_PERAO_SSUSB0_REF 30 +#define CLK_PERAO_SSUSB0_FRMCNT 31 +#define CLK_PERAO_SSUSB0_SYS 32 +#define CLK_PERAO_SSUSB0_XHCI 33 +#define CLK_PERAO_SSUSB0_F 34 +#define CLK_PERAO_SSUSB0_H 35 +#define CLK_PERAO_SSUSB1_REF 36 +#define CLK_PERAO_SSUSB1_FRMCNT 37 +#define CLK_PERAO_SSUSB1_SYS 38 +#define CLK_PERAO_SSUSB1_XHCI 39 +#define CLK_PERAO_SSUSB1_F 40 +#define CLK_PERAO_SSUSB1_H 41 +#define CLK_PERAO_SSUSB2_REF 42 +#define CLK_PERAO_SSUSB2_FRMCNT 43 +#define CLK_PERAO_SSUSB2_SYS 44 +#define CLK_PERAO_SSUSB2_XHCI 45 +#define CLK_PERAO_SSUSB2_F 46 +#define CLK_PERAO_SSUSB2_H 47 +#define CLK_PERAO_SSUSB3_REF 48 +#define CLK_PERAO_SSUSB3_FRMCNT 49 +#define CLK_PERAO_SSUSB3_SYS 50 +#define CLK_PERAO_SSUSB3_XHCI 51 +#define CLK_PERAO_SSUSB3_F 52 +#define CLK_PERAO_SSUSB3_H 53 +#define CLK_PERAO_SSUSB4_REF 54 +#define CLK_PERAO_SSUSB4_FRMCNT 55 +#define CLK_PERAO_SSUSB4_SYS 56 +#define CLK_PERAO_SSUSB4_XHCI 57 +#define CLK_PERAO_SSUSB4_F 58 +#define CLK_PERAO_SSUSB4_H 59 +#define CLK_PERAO_MSDC0 60 +#define CLK_PERAO_MSDC0_H 61 +#define CLK_PERAO_MSDC0_FAES 62 +#define CLK_PERAO_MSDC0_MST_F 63 +#define CLK_PERAO_MSDC0_SLV_H 64 +#define CLK_PERAO_MSDC1 65 +#define CLK_PERAO_MSDC1_H 66 +#define CLK_PERAO_MSDC1_MST_F 67 +#define CLK_PERAO_MSDC1_SLV_H 68 +#define CLK_PERAO_MSDC2 69 +#define CLK_PERAO_MSDC2_H 70 +#define CLK_PERAO_MSDC2_MST_F 71 +#define CLK_PERAO_MSDC2_SLV_H 72 +#define CLK_PERAO_SFLASH 73 +#define CLK_PERAO_SFLASH_F 74 +#define CLK_PERAO_SFLASH_H 75 +#define CLK_PERAO_SFLASH_P 76 +#define CLK_PERAO_AUDIO0 77 +#define CLK_PERAO_AUDIO1 78 +#define CLK_PERAO_AUDIO2 79 +#define CLK_PERAO_AUXADC_26M 80 + +/* UFSCFG_AO_REG */ +#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1 +#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2 +#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3 +#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4 +#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5 + +/* UFSCFG_PDN_REG */ +#define CLK_UFSCFG_REG_UFSHCI_UFS 0 +#define CLK_UFSCFG_REG_UFSHCI_AES 1 +#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2 +#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3 + +/* IMP_IIC_WRAP_WS */ +#define CLK_IMPWS_I2C2 0 + +/* IMP_IIC_WRAP_E */ +#define CLK_IMPE_I2C0 0 +#define CLK_IMPE_I2C1 1 + +/* IMP_IIC_WRAP_S */ +#define CLK_IMPS_I2C3 0 +#define CLK_IMPS_I2C4 1 +#define CLK_IMPS_I2C5 2 +#define CLK_IMPS_I2C6 3 + +/* IMP_IIC_WRAP_EN */ +#define CLK_IMPEN_I2C7 0 +#define CLK_IMPEN_I2C8 1 + +/* MFG */ +#define CLK_MFG_BG3D 0 + +/* DISPSYS_CONFIG */ +#define CLK_MM_DISP_OVL0_4L 0 +#define CLK_MM_DISP_OVL1_4L 1 +#define CLK_MM_VPP_RSZ0 2 +#define CLK_MM_VPP_RSZ1 3 +#define CLK_MM_DISP_RDMA0 4 +#define CLK_MM_DISP_RDMA1 5 +#define CLK_MM_DISP_COLOR0 6 +#define CLK_MM_DISP_COLOR1 7 +#define CLK_MM_DISP_CCORR0 8 +#define CLK_MM_DISP_CCORR1 9 +#define CLK_MM_DISP_CCORR2 10 +#define CLK_MM_DISP_CCORR3 11 +#define CLK_MM_DISP_AAL0 12 +#define CLK_MM_DISP_AAL1 13 +#define CLK_MM_DISP_GAMMA0 14 +#define CLK_MM_DISP_GAMMA1 15 +#define CLK_MM_DISP_DITHER0 16 +#define CLK_MM_DISP_DITHER1 17 +#define CLK_MM_DISP_DSC_WRAP0 18 +#define CLK_MM_VPP_MERGE0 19 +#define CLK_MMSYS_0_DISP_DVO 20 +#define CLK_MMSYS_0_DISP_DSI0 21 +#define CLK_MM_DP_INTF0 22 +#define CLK_MM_DPI0 23 +#define CLK_MM_DISP_WDMA0 24 +#define CLK_MM_DISP_WDMA1 25 +#define CLK_MM_DISP_FAKE_ENG0 26 +#define CLK_MM_DISP_FAKE_ENG1 27 +#define CLK_MM_SMI_LARB 28 +#define CLK_MM_DISP_MUTEX0 29 +#define CLK_MM_DIPSYS_CONFIG 30 +#define CLK_MM_DUMMY 31 +#define CLK_MMSYS_1_DISP_DSI0 32 +#define CLK_MMSYS_1_LVDS_ENCODER 33 +#define CLK_MMSYS_1_DPI0 34 +#define CLK_MMSYS_1_DISP_DVO 35 +#define CLK_MM_DP_INTF 36 +#define CLK_MMSYS_1_LVDS_ENCODER_CTS 37 +#define CLK_MMSYS_1_DISP_DVO_AVT 38 + +/* IMGSYS1 */ +#define CLK_IMGSYS1_LARB9 0 +#define CLK_IMGSYS1_LARB11 1 +#define CLK_IMGSYS1_DIP 2 +#define CLK_IMGSYS1_GALS 3 + +/* IMGSYS2 */ +#define CLK_IMGSYS2_LARB9 0 +#define CLK_IMGSYS2_LARB11 1 +#define CLK_IMGSYS2_MFB 2 +#define CLK_IMGSYS2_WPE 3 +#define CLK_IMGSYS2_MSS 4 +#define CLK_IMGSYS2_GALS 5 + +/* VDEC_CORE */ +#define CLK_VDEC_CORE_LARB_CKEN 0 +#define CLK_VDEC_CORE_VDEC_CKEN 1 +#define CLK_VDEC_CORE_VDEC_ACTIVE 2 + +/* VENC_GCON */ +#define CLK_VEN1_CKE0_LARB 0 +#define CLK_VEN1_CKE1_VENC 1 +#define CLK_VEN1_CKE2_JPGENC 2 +#define CLK_VEN1_CKE3_JPGDEC 3 +#define CLK_VEN1_CKE4_JPGDEC_C1 4 +#define CLK_VEN1_CKE5_GALS 5 +#define CLK_VEN1_CKE6_GALS_SRAM 6 + +/* VLPCFG_REG */ +#define CLK_VLPCFG_REG_SCP 0 +#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1 +#define CLK_VLPCFG_REG_DPMSRCK_TEST 2 +#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3 +#define CLK_VLPCFG_REG_DPMSRULP_TEST 4 +#define CLK_VLPCFG_REG_SPMI_P_MST 5 +#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7 +#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9 +#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10 +#define CLK_VLPCFG_REG_DVFSRC 11 +#define CLK_VLPCFG_REG_PWM_VLP 12 +#define CLK_VLPCFG_REG_SRCK 13 +#define CLK_VLPCFG_REG_SSPM_F26M 14 +#define CLK_VLPCFG_REG_SSPM_F32K 15 +#define CLK_VLPCFG_REG_SSPM_ULPOSC 16 +#define CLK_VLPCFG_REG_VLP_32K_COM 17 +#define CLK_VLPCFG_REG_VLP_26M_COM 18 + +/* VLP_CKSYS */ +#define CLK_VLP_CK_SCP_SEL 0 +#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1 +#define CLK_VLP_CK_SPMI_P_MST_SEL 2 +#define CLK_VLP_CK_DVFSRC_SEL 3 +#define CLK_VLP_CK_PWM_VLP_SEL 4 +#define CLK_VLP_CK_AXI_VLP_SEL 5 +#define CLK_VLP_CK_SYSTIMER_26M_SEL 6 +#define CLK_VLP_CK_SSPM_SEL 7 +#define CLK_VLP_CK_SSPM_F26M_SEL 8 +#define CLK_VLP_CK_SRCK_SEL 9 +#define CLK_VLP_CK_SCP_SPI_SEL 10 +#define CLK_VLP_CK_SCP_IIC_SEL 11 +#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12 +#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13 +#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14 +#define CLK_VLP_CK_APXGPT_26M_SEL 15 +#define CLK_VLP_CK_VADSP_SEL 16 +#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17 +#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18 +#define CLK_VLP_CK_CAMTG0_SEL 19 +#define CLK_VLP_CK_CAMTG1_SEL 20 +#define CLK_VLP_CK_CAMTG2_SEL 21 +#define CLK_VLP_CK_AUD_ADC_SEL 22 +#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23 +#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24 +#define CLK_VLP_CK_SEJ_13M_EN 25 +#define CLK_VLP_CK_SEJ_26M_EN 26 +#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 27 + +/* SCP_IIC */ +#define CLK_SCP_IIC_I2C0_W1S 0 +#define CLK_SCP_IIC_I2C1_W1S 1 + +/* SCP */ +#define CLK_SCP_SET_SPI0 0 +#define CLK_SCP_SET_SPI1 1 + +/* CAMSYS_MAIN */ +#define CLK_CAM_M_LARB13 0 +#define CLK_CAM_M_LARB14 1 +#define CLK_CAM_M_CAMSYS_MAIN_CAM 2 +#define CLK_CAM_M_CAMSYS_MAIN_CAMTG 3 +#define CLK_CAM_M_SENINF 4 +#define CLK_CAM_M_CAMSV1 5 +#define CLK_CAM_M_CAMSV2 6 +#define CLK_CAM_M_CAMSV3 7 +#define CLK_CAM_M_FAKE_ENG 8 +#define CLK_CAM_M_CAM2MM_GALS 9 +#define CLK_CAM_M_CAMSV4 10 +#define CLK_CAM_M_PDA 11 + +/* CAMSYS_RAWA */ +#define CLK_CAM_RA_CAMSYS_RAWA_LARBX 0 +#define CLK_CAM_RA_CAMSYS_RAWA_CAM 1 +#define CLK_CAM_RA_CAMSYS_RAWA_CAMTG 2 + +/* CAMSYS_RAWB */ +#define CLK_CAM_RB_CAMSYS_RAWB_LARBX 0 +#define CLK_CAM_RB_CAMSYS_RAWB_CAM 1 +#define CLK_CAM_RB_CAMSYS_RAWB_CAMTG 2 + +/* IPESYS */ +#define CLK_IPE_LARB19 0 +#define CLK_IPE_LARB20 1 +#define CLK_IPE_SMI_SUBCOM 2 +#define CLK_IPE_FD 3 +#define CLK_IPE_FE 4 +#define CLK_IPE_RSC 5 +#define CLK_IPESYS_GALS 6 + +/* VLPCFG_AO_REG */ +#define CLK_VLPCFG_AO_APEINT_RX 0 + +/* DVFSRC_TOP */ +#define CLK_DVFSRC_TOP_DVFSRC_EN 0 + +/* MMINFRA_CONFIG */ +#define CLK_MMINFRA_GCE_D 0 +#define CLK_MMINFRA_GCE_M 1 +#define CLK_MMINFRA_SMI 2 +#define CLK_MMINFRA_GCE_26M 3 + +/* GCE_D */ +#define CLK_GCE_D_TOP 0 + +/* GCE_M */ +#define CLK_GCE_M_TOP 0 + +/* MDPSYS_CONFIG */ +#define CLK_MDP_MUTEX0 0 +#define CLK_MDP_APB_BUS 1 +#define CLK_MDP_SMI0 2 +#define CLK_MDP_RDMA0 3 +#define CLK_MDP_RDMA2 4 +#define CLK_MDP_HDR0 5 +#define CLK_MDP_AAL0 6 +#define CLK_MDP_RSZ0 7 +#define CLK_MDP_TDSHP0 8 +#define CLK_MDP_COLOR0 9 +#define CLK_MDP_WROT0 10 +#define CLK_MDP_FAKE_ENG0 11 +#define CLK_MDPSYS_CONFIG 12 +#define CLK_MDP_RDMA1 13 +#define CLK_MDP_RDMA3 14 +#define CLK_MDP_HDR1 15 +#define CLK_MDP_AAL1 16 +#define CLK_MDP_RSZ1 17 +#define CLK_MDP_TDSHP1 18 +#define CLK_MDP_COLOR1 19 +#define CLK_MDP_WROT1 20 +#define CLK_MDP_RSZ2 21 +#define CLK_MDP_WROT2 22 +#define CLK_MDP_RSZ3 23 +#define CLK_MDP_WROT3 24 +#define CLK_MDP_BIRSZ0 25 +#define CLK_MDP_BIRSZ1 26 + +/* DBGAO */ +#define CLK_DBGAO_ATB_EN 0 + +/* DEM */ +#define CLK_DEM_ATB_EN 0 +#define CLK_DEM_BUSCLK_EN 1 +#define CLK_DEM_SYSCLK_EN 2 + +#endif /* _DT_BINDINGS_CLK_MT8189_H */ -- cgit v1.3.1 From fcbf81694c9399a71ac100b4de15089c3e09dd8c Mon Sep 17 00:00:00 2001 From: Quentin Schulz Date: Thu, 20 Nov 2025 13:48:06 +0100 Subject: led: remove legacy API No user of the legacy LED API anymore (except Sunxi with the PinePhone but that is now a Sunxi-specific implementation), so let's remove anything related. Signed-off-by: Quentin Schulz --- README | 26 ---- arch/m68k/lib/bootm.c | 3 - board/isee/igep00x0/igep00x0.c | 1 - boot/image.c | 4 - cmd/Makefile | 1 - cmd/ide.c | 4 - cmd/legacy_led.c | 186 ------------------------ common/board_f.c | 1 - common/board_r.c | 11 -- drivers/led/Kconfig | 323 ----------------------------------------- drivers/misc/Makefile | 2 - drivers/misc/gpio_led.c | 52 ------- drivers/misc/status_led.c | 124 ---------------- include/status_led.h | 115 --------------- 14 files changed, 853 deletions(-) delete mode 100644 cmd/legacy_led.c delete mode 100644 drivers/misc/status_led.c delete mode 100644 include/status_led.h (limited to 'include') diff --git a/README b/README index 20a73bab802..38fcb23531c 100644 --- a/README +++ b/README @@ -597,32 +597,6 @@ The following options need to be configured: A byte containing the id of the VLAN. -- Status LED: CONFIG_LED_STATUS - - Several configurations allow to display the current - status using a LED. For instance, the LED will blink - fast while running U-Boot code, stop blinking as - soon as a reply to a BOOTP request was received, and - start blinking slow once the Linux kernel is running - (supported by a status LED driver in the Linux - kernel). Defining CONFIG_LED_STATUS enables this - feature in U-Boot. - - Additional options: - - CONFIG_LED_STATUS_GPIO - The status LED can be connected to a GPIO pin. - In such cases, the gpio_led driver can be used as a - status LED backend implementation. Define CONFIG_LED_STATUS_GPIO - to include the gpio_led driver in the U-Boot binary. - - CFG_GPIO_LED_INVERTED_TABLE - Some GPIO connected LEDs may have inverted polarity in which - case the GPIO high value corresponds to LED off state and - GPIO low value corresponds to LED on state. - In such cases CFG_GPIO_LED_INVERTED_TABLE may be defined - with a list of GPIO LEDs that have inverted polarity. - - I2C Support: CFG_SYS_NUM_I2C_BUSES Hold the number of i2c buses you want to use. diff --git a/arch/m68k/lib/bootm.c b/arch/m68k/lib/bootm.c index 3dcff8076e3..1fa112f8dbf 100644 --- a/arch/m68k/lib/bootm.c +++ b/arch/m68k/lib/bootm.c @@ -15,9 +15,6 @@ #include #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -# include -#endif DECLARE_GLOBAL_DATA_PTR; diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index c21b083b62a..4dc7b608f0f 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/boot/image.c b/boot/image.c index abac2c7034b..28b367c6b54 100644 --- a/boot/image.c +++ b/boot/image.c @@ -15,10 +15,6 @@ #include #include -#ifdef CONFIG_SHOW_BOOT_PROGRESS -#include -#endif - #if CONFIG_IS_ENABLED(FIT) || CONFIG_IS_ENABLED(OF_LIBFDT) #include #include diff --git a/cmd/Makefile b/cmd/Makefile index 25479907797..969f3b6386d 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -105,7 +105,6 @@ obj-$(CONFIG_CMD_IRQ) += irq.o obj-$(CONFIG_CMD_ITEST) += itest.o obj-$(CONFIG_CMD_JFFS2) += jffs2.o obj-$(CONFIG_CMD_CRAMFS) += cramfs.o -obj-$(CONFIG_LED_STATUS_CMD) += legacy_led.o obj-$(CONFIG_CMD_LED) += led.o obj-$(CONFIG_CMD_LICENSE) += license.o obj-y += load.o diff --git a/cmd/ide.c b/cmd/ide.c index ed30f946866..f99fb6f5824 100644 --- a/cmd/ide.c +++ b/cmd/ide.c @@ -21,10 +21,6 @@ #include -#ifdef CONFIG_LED_STATUS -# include -#endif - /* Current I/O Device */ static int curr_device; diff --git a/cmd/legacy_led.c b/cmd/legacy_led.c deleted file mode 100644 index db312ae6e2d..00000000000 --- a/cmd/legacy_led.c +++ /dev/null @@ -1,186 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2010 - * Jason Kridner - * - * Based on cmd_led.c patch from: - * http://www.mail-archive.com/u-boot@lists.denx.de/msg06873.html - * (C) Copyright 2008 - * Ulf Samuelsson - */ - -#include -#include -#include -#include - -struct led_tbl_s { - char *string; /* String for use in the command */ - led_id_t mask; /* Mask used for calling __led_set() */ - void (*off)(void); /* Optional function for turning LED off */ - void (*on)(void); /* Optional function for turning LED on */ - void (*toggle)(void);/* Optional function for toggling LED */ -}; - -typedef struct led_tbl_s led_tbl_t; - -static const led_tbl_t led_commands[] = { -#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC -#ifdef CONFIG_LED_STATUS0 - { "0", CONFIG_LED_STATUS_BIT, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS1 - { "1", CONFIG_LED_STATUS_BIT1, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS2 - { "2", CONFIG_LED_STATUS_BIT2, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS3 - { "3", CONFIG_LED_STATUS_BIT3, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS4 - { "4", CONFIG_LED_STATUS_BIT4, NULL, NULL, NULL }, -#endif -#ifdef CONFIG_LED_STATUS5 - { "5", CONFIG_LED_STATUS_BIT5, NULL, NULL, NULL }, -#endif -#endif -#ifdef CONFIG_LED_STATUS_GREEN - { "green", CONFIG_LED_STATUS_GREEN, green_led_off, green_led_on, NULL }, -#endif -#ifdef CONFIG_LED_STATUS_YELLOW - { "yellow", CONFIG_LED_STATUS_YELLOW, yellow_led_off, yellow_led_on, - NULL }, -#endif -#ifdef CONFIG_LED_STATUS_RED - { "red", CONFIG_LED_STATUS_RED, red_led_off, red_led_on, NULL }, -#endif -#ifdef CONFIG_LED_STATUS_BLUE - { "blue", CONFIG_LED_STATUS_BLUE, blue_led_off, blue_led_on, NULL }, -#endif - { NULL, 0, NULL, NULL, NULL } -}; - -enum led_cmd { LED_ON, LED_OFF, LED_TOGGLE, LED_BLINK }; - -enum led_cmd get_led_cmd(char *var) -{ - if (strcmp(var, "off") == 0) - return LED_OFF; - if (strcmp(var, "on") == 0) - return LED_ON; - if (strcmp(var, "toggle") == 0) - return LED_TOGGLE; - if (strcmp(var, "blink") == 0) - return LED_BLINK; - - return -1; -} - -/* - * LED drivers providing a blinking LED functionality, like the - * PCA9551, can override this empty weak function - */ -void __weak __led_blink(led_id_t mask, int freq) -{ -} - -int do_legacy_led(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) -{ - int i, match = 0; - enum led_cmd cmd; - int freq; - - /* Validate arguments */ - if ((argc < 3) || (argc > 4)) - return CMD_RET_USAGE; - - cmd = get_led_cmd(argv[2]); - if (cmd < 0) { - return CMD_RET_USAGE; - } - - for (i = 0; led_commands[i].string; i++) { - if ((strcmp("all", argv[1]) == 0) || - (strcmp(led_commands[i].string, argv[1]) == 0)) { - match = 1; - switch (cmd) { - case LED_ON: - if (led_commands[i].on) - led_commands[i].on(); - else - __led_set(led_commands[i].mask, - CONFIG_LED_STATUS_ON); - break; - case LED_OFF: - if (led_commands[i].off) - led_commands[i].off(); - else - __led_set(led_commands[i].mask, - CONFIG_LED_STATUS_OFF); - break; - case LED_TOGGLE: - if (led_commands[i].toggle) - led_commands[i].toggle(); - else - __led_toggle(led_commands[i].mask); - break; - case LED_BLINK: - if (argc != 4) - return CMD_RET_USAGE; - - freq = dectoul(argv[3], NULL); - __led_blink(led_commands[i].mask, freq); - } - /* Need to set only 1 led if led_name wasn't 'all' */ - if (strcmp("all", argv[1]) != 0) - break; - } - } - - /* If we ran out of matches, print Usage */ - if (!match) { - return CMD_RET_USAGE; - } - - return 0; -} - -U_BOOT_CMD( - led, 4, 1, do_legacy_led, - "[" -#ifdef CONFIG_LED_STATUS_BOARD_SPECIFIC -#ifdef CONFIG_LED_STATUS0 - "0|" -#endif -#ifdef CONFIG_LED_STATUS1 - "1|" -#endif -#ifdef CONFIG_LED_STATUS2 - "2|" -#endif -#ifdef CONFIG_LED_STATUS3 - "3|" -#endif -#ifdef CONFIG_LED_STATUS4 - "4|" -#endif -#ifdef CONFIG_LED_STATUS5 - "5|" -#endif -#endif -#ifdef CONFIG_LED_STATUS_GREEN - "green|" -#endif -#ifdef CONFIG_LED_STATUS_YELLOW - "yellow|" -#endif -#ifdef CONFIG_LED_STATUS_RED - "red|" -#endif -#ifdef CONFIG_LED_STATUS_BLUE - "blue|" -#endif - "all] [on|off|toggle|blink] [blink-freq in ms]", - "[led_name] [on|off|toggle|blink] sets or clears led(s)" -); diff --git a/common/board_f.c b/common/board_f.c index c8a612d6070..211ba6b9ada 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include #include diff --git a/common/board_r.c b/common/board_r.c index 76f9fc090fb..8cf0e14679c 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -52,7 +52,6 @@ #include #include #include -#include #include #include #include @@ -482,17 +481,8 @@ static int initr_malloc_bootparams(void) } #endif -static int initr_status_led(void) -{ - status_led_init(); - - return 0; -} - static int initr_boot_led_blink(void) { - status_led_boot_blink(); - led_boot_blink(); return 0; @@ -758,7 +748,6 @@ static void initcall_run_r(void) #if defined(CONFIG_MICROBLAZE) || defined(CONFIG_M68K) INITCALL(timer_init); /* initialize timer */ #endif - INITCALL(initr_status_led); INITCALL(initr_boot_led_blink); /* PPC has a udelay(20) here dating from 2002. Why? */ #if CONFIG_IS_ENABLED(BOARD_LATE_INIT) diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index 1cd3638cb16..de95a1debdc 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -138,327 +138,4 @@ config SPL_LED_GPIO This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. -config LED_STATUS - bool "Enable legacy status LED API" - depends on !LED - help - Allows common u-boot commands to use a board's leds to - provide status for activities like booting and downloading files. - -if LED_STATUS - -# Hidden constants - -config LED_STATUS_OFF - int - default 0 - -config LED_STATUS_BLINKING - int - default 1 - -config LED_STATUS_ON - int - default 2 - -# Hidden constants end - -config LED_STATUS_GPIO - bool "GPIO status LED implementation" - help - The status LED can be connected to a GPIO pin. In such cases, the - gpio_led driver can be used as a status LED backend implementation. - -config LED_STATUS_BOARD_SPECIFIC - bool "Specific board" - default y - help - LED support is only for a specific board. - -comment "LEDs parameters" - -config LED_STATUS0 - bool "Enable status LED 0" - -if LED_STATUS0 - -config LED_STATUS_BIT - int "identification" - help - CONFIG_LED_STATUS_BIT is passed into the __led_* functions to identify - which LED is being acted on. As such, the chosen value must be unique - with respect to the other CONFIG_LED_STATUS_BIT's. Mapping the value - to a physical LED is the responsibility of the __led_* function. - -config LED_STATUS_STATE - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ: - LED_STATUS_PERIOD = CONFIG_SYS_HZ/LED_STATUS_FREQ - Values range: 2 - 10 - -endif # LED_STATUS0 - -config LED_STATUS1 - bool "Enable status LED 1" - -if LED_STATUS1 - -config LED_STATUS_BIT1 - int "identification" - help - CONFIG_LED_STATUS_BIT1 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE1 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ1 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ1: - LED_STATUS_PERIOD1 = CONFIG_SYS_HZ/LED_STATUS_FREQ1 - Values range: 2 - 10 - -endif # LED_STATUS1 - -config LED_STATUS2 - bool "Enable status LED 2" - -if LED_STATUS2 - -config LED_STATUS_BIT2 - int "identification" - help - CONFIG_LED_STATUS_BIT2 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE2 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ2 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ2: - LED_STATUS_PERIOD2 = CONFIG_SYS_HZ/LED_STATUS_FREQ2 - Values range: 2 - 10 - -endif # LED_STATUS2 - -config LED_STATUS3 - bool "Enable status LED 3" - -if LED_STATUS3 - -config LED_STATUS_BIT3 - int "identification" - help - CONFIG_LED_STATUS_BIT3 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE3 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ3 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ3: - LED_STATUS_PERIOD3 = CONFIG_SYS_HZ/LED_STATUS_FREQ3 - Values range: 2 - 10 - -endif # LED_STATUS3 - -config LED_STATUS4 - bool "Enable status LED 4" - -if LED_STATUS4 - -config LED_STATUS_BIT4 - int "identification" - help - CONFIG_LED_STATUS_BIT4 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE4 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ4 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ4: - LED_STATUS_PERIOD4 = CONFIG_SYS_HZ/LED_STATUS_FREQ4 - Values range: 2 - 10 - -endif # LED_STATUS4 - -config LED_STATUS5 - bool "Enable status LED 5" - -if LED_STATUS5 - -config LED_STATUS_BIT5 - int "identification" - help - CONFIG_LED_STATUS_BIT5 is passed into the __led_* functions to - identify which LED is being acted on. As such, the chosen value must - be unique with respect to the other CONFIG_LED_STATUS_BIT's. Mapping - the value to a physical LED is the responsibility of the __led_* - function. - -config LED_STATUS_STATE5 - int "initial state" - range LED_STATUS_OFF LED_STATUS_ON - default LED_STATUS_OFF - help - Should be set one of the following: - 0 - off - 1 - blinking - 2 - on - -config LED_STATUS_FREQ5 - int "blink frequency" - range 2 10 - default 2 - help - The LED blink period calculated from LED_STATUS_FREQ5: - LED_STATUS_PERIOD5 = CONFIG_SYS_HZ/LED_STATUS_FREQ5 - Values range: 2 - 10 - -endif # LED_STATUS5 - -config LED_STATUS_BOOT_ENABLE - bool "Enable BOOT LED" - help - Enable to turn an LED on when the board is booting. - -if LED_STATUS_BOOT_ENABLE - -config LED_STATUS_BOOT - int "LED to light when the board is booting" - help - Valid enabled LED device number. - -endif # LED_STATUS_BOOT_ENABLE - -config LED_STATUS_RED_ENABLE - bool "Enable red LED" - help - Enable red status LED. - -if LED_STATUS_RED_ENABLE - -config LED_STATUS_RED - int "Red LED identification" - help - Valid enabled LED device number. - -endif # LED_STATUS_RED_ENABLE - -config LED_STATUS_YELLOW_ENABLE - bool "Enable yellow LED" - help - Enable yellow status LED. - -if LED_STATUS_YELLOW_ENABLE - -config LED_STATUS_YELLOW - int "Yellow LED identification" - help - Valid enabled LED device number. - -endif # LED_STATUS_YELLOW_ENABLE - -config LED_STATUS_BLUE_ENABLE - bool "Enable blue LED" - help - Enable blue status LED. - -if LED_STATUS_BLUE_ENABLE - -config LED_STATUS_BLUE - int "Blue LED identification" - help - Valid enabled LED device number. - -endif # LED_STATUS_BLUE_ENABLE - -config LED_STATUS_GREEN_ENABLE - bool "Enable green LED" - help - Enable green status LED. - -if LED_STATUS_GREEN_ENABLE - -config LED_STATUS_GREEN - int "Green LED identification" - help - Valid enabled LED device number (0-5). - -endif # LED_STATUS_GREEN_ENABLE - -config LED_STATUS_CMD - bool "Enable status LED commands" - -endif # LED_STATUS - endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 1d950f7a0ab..e2170212e5a 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -48,8 +48,6 @@ obj-$(CONFIG_IHS_FPGA) += ihs_fpga.o obj-$(CONFIG_IMX8) += imx8/ obj-$(CONFIG_IMX_ELE) += imx_ele/ obj-$(CONFIG_K3_FUSE) += k3_fuse.o -obj-$(CONFIG_LED_STATUS) += status_led.o -obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o obj-$(CONFIG_$(PHASE_)LS2_SFP) += ls2_sfp.o obj-$(CONFIG_$(PHASE_)MXC_OCOTP) += mxc_ocotp.o diff --git a/drivers/misc/gpio_led.c b/drivers/misc/gpio_led.c index e63689967a7..69b2e2f76bd 100644 --- a/drivers/misc/gpio_led.c +++ b/drivers/misc/gpio_led.c @@ -1,55 +1,3 @@ -/* - * Status LED driver based on GPIO access conventions of Linux - * - * Copyright (C) 2010 Thomas Chou - * Licensed under the GPL-2 or later. - */ - -#include -#include - -#ifndef CFG_GPIO_LED_INVERTED_TABLE -#define CFG_GPIO_LED_INVERTED_TABLE {} -#endif - -static led_id_t gpio_led_inv[] = CFG_GPIO_LED_INVERTED_TABLE; - -static int gpio_led_gpio_value(led_id_t mask, int state) -{ - int i, gpio_value = (state == CONFIG_LED_STATUS_ON); - - for (i = 0; i < ARRAY_SIZE(gpio_led_inv); i++) { - if (gpio_led_inv[i] == mask) - gpio_value = !gpio_value; - } - - return gpio_value; -} - -void __led_init(led_id_t mask, int state) -{ - int gpio_value; - - if (gpio_request(mask, "gpio_led") != 0) { - printf("%s: failed requesting GPIO%lu!\n", __func__, mask); - return; - } - - gpio_value = gpio_led_gpio_value(mask, state); - gpio_direction_output(mask, gpio_value); -} - -void __led_set(led_id_t mask, int state) -{ - int gpio_value = gpio_led_gpio_value(mask, state); - - gpio_set_value(mask, gpio_value); -} - -void __led_toggle(led_id_t mask) -{ - gpio_set_value(mask, !gpio_get_value(mask)); -} #ifdef CONFIG_GPIO_LED_STUBS diff --git a/drivers/misc/status_led.c b/drivers/misc/status_led.c deleted file mode 100644 index 3b1baa4f840..00000000000 --- a/drivers/misc/status_led.c +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#include -#include - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * U-Boot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -/* ------------------------------------------------------------------------- */ - -typedef struct { - led_id_t mask; - int state; - int period; - int cnt; -} led_dev_t; - -led_dev_t led_dev[] = { - { CONFIG_LED_STATUS_BIT, - CONFIG_LED_STATUS_STATE, - LED_STATUS_PERIOD, - 0, - }, -#if defined(CONFIG_LED_STATUS1) - { CONFIG_LED_STATUS_BIT1, - CONFIG_LED_STATUS_STATE1, - LED_STATUS_PERIOD1, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS2) - { CONFIG_LED_STATUS_BIT2, - CONFIG_LED_STATUS_STATE2, - LED_STATUS_PERIOD2, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS3) - { CONFIG_LED_STATUS_BIT3, - CONFIG_LED_STATUS_STATE3, - LED_STATUS_PERIOD3, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS4) - { CONFIG_LED_STATUS_BIT4, - CONFIG_LED_STATUS_STATE4, - LED_STATUS_PERIOD4, - 0, - }, -#endif -#if defined(CONFIG_LED_STATUS5) - { CONFIG_LED_STATUS_BIT5, - CONFIG_LED_STATUS_STATE5, - LED_STATUS_PERIOD5, - 0, - }, -#endif -}; - -#define MAX_LED_DEV (sizeof(led_dev)/sizeof(led_dev_t)) - -static int status_led_init_done = 0; - -void status_led_init(void) -{ - led_dev_t *ld; - int i; - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) - __led_init (ld->mask, ld->state); - status_led_init_done = 1; -} - -void status_led_tick(ulong timestamp) -{ - led_dev_t *ld; - int i; - - if (!status_led_init_done) - status_led_init(); - - for (i = 0, ld = led_dev; i < MAX_LED_DEV; i++, ld++) { - - if (ld->state != CONFIG_LED_STATUS_BLINKING) - continue; - - if (++ld->cnt >= ld->period) { - __led_toggle (ld->mask); - ld->cnt -= ld->period; - } - - } -} - -void status_led_set(int led, int state) -{ - led_dev_t *ld; - - if (led < 0 || led >= MAX_LED_DEV) - return; - - if (!status_led_init_done) - status_led_init(); - - ld = &led_dev[led]; - - ld->state = state; - if (state == CONFIG_LED_STATUS_BLINKING) { - ld->cnt = 0; /* always start with full period */ - state = CONFIG_LED_STATUS_ON; /* always start with LED _ON_ */ - } - __led_set (ld->mask, state); -} diff --git a/include/status_led.h b/include/status_led.h deleted file mode 100644 index 1282022253e..00000000000 --- a/include/status_led.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2000-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * The purpose of this code is to signal the operational status of a - * target which usually boots over the network; while running in - * PCBoot, a status LED is blinking. As soon as a valid BOOTP reply - * message has been received, the LED is turned off. The Linux - * kernel, once it is running, will start blinking the LED again, - * with another frequency. - */ - -#ifndef _STATUS_LED_H_ -#define _STATUS_LED_H_ - -#ifdef CONFIG_LED_STATUS - -#define LED_STATUS_PERIOD (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ) -#ifdef CONFIG_LED_STATUS1 -#define LED_STATUS_PERIOD1 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ1) -#endif /* CONFIG_LED_STATUS1 */ -#ifdef CONFIG_LED_STATUS2 -#define LED_STATUS_PERIOD2 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ2) -#endif /* CONFIG_LED_STATUS2 */ -#ifdef CONFIG_LED_STATUS3 -#define LED_STATUS_PERIOD3 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ3) -#endif /* CONFIG_LED_STATUS3 */ -#ifdef CONFIG_LED_STATUS4 -#define LED_STATUS_PERIOD4 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ4) -#endif /* CONFIG_LED_STATUS4 */ -#ifdef CONFIG_LED_STATUS5 -#define LED_STATUS_PERIOD5 (CONFIG_SYS_HZ / CONFIG_LED_STATUS_FREQ5) -#endif /* CONFIG_LED_STATUS5 */ - -void status_led_init(void); -void status_led_tick(unsigned long timestamp); -void status_led_set(int led, int state); - -static inline void status_led_boot_blink(void) -{ -#ifdef CONFIG_LED_STATUS_BOOT_ENABLE - status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_BLINKING); -#endif -} - -/***** MVS v1 **********************************************************/ -#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) -# define STATUS_LED_PAR im_ioport.iop_pdpar -# define STATUS_LED_DIR im_ioport.iop_pddir -# undef STATUS_LED_ODR -# define STATUS_LED_DAT im_ioport.iop_pddat - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -/***** Someone else defines these *************************************/ -#elif defined(STATUS_LED_PAR) - /* - * ADVICE: Define in your board configuration file rather than - * filling this file up with lots of custom board stuff. - */ - -#elif defined(CONFIG_LED_STATUS_BOARD_SPECIFIC) -/* led_id_t is unsigned long mask */ -typedef unsigned long led_id_t; - -extern void __led_toggle (led_id_t mask); -extern void __led_init (led_id_t mask, int state); -extern void __led_set (led_id_t mask, int state); -void __led_blink(led_id_t mask, int freq); -#else -# error Status LED configuration missing -#endif -/************************************************************************/ - -#ifndef CONFIG_LED_STATUS_BOARD_SPECIFIC -# include -#endif - -#else - -static inline void status_led_init(void) { } -static inline void status_led_set(int led, int state) { } -static inline void status_led_boot_blink(void) { } - -#endif /* CONFIG_LED_STATUS */ - -/* - * Coloured LEDs API - */ -#ifndef __ASSEMBLY__ -void coloured_LED_init(void); -void red_led_on(void); -void red_led_off(void); -void green_led_on(void); -void green_led_off(void); -void yellow_led_on(void); -void yellow_led_off(void); -void blue_led_on(void); -void blue_led_off(void); -#else - .extern LED_init - .extern red_led_on - .extern red_led_off - .extern yellow_led_on - .extern yellow_led_off - .extern green_led_on - .extern green_led_off - .extern blue_led_on - .extern blue_led_off -#endif - -#endif /* _STATUS_LED_H_ */ -- cgit v1.3.1 From 5cc969caf0ba247d8464af1fd87110e73309e37d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Mar 2026 19:36:12 -0700 Subject: bootstage: Add some missing dummy functions Neither bootstage_fdt_add_report() nor bootstage_report() has a dummy double for when bootstage is disabled. Add them. Signed-off-by: Simon Glass Reviewed-by: Tom Rini --- include/bootstage.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/bootstage.h b/include/bootstage.h index 528d0ca0614..62fb99110f0 100644 --- a/include/bootstage.h +++ b/include/bootstage.h @@ -435,6 +435,14 @@ static inline uint32_t bootstage_accum(enum bootstage_id id) return 0; } +static inline void bootstage_report(void) +{ +} + +static inline void bootstage_fdt_add_report(void) +{ +} + static inline int bootstage_stash(void *base, int size) { return 0; /* Pretend to succeed */ -- cgit v1.3.1 From 1ec3ee670de6b2f8f96cd7c15f7e22e89a06bb2d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Mar 2026 19:36:13 -0700 Subject: bootm: Create bootm_final() for pre-boot cleanup There are various functions which announce that booting is imminent and do related preparation. Most of these are arch-specific. In practice, most archs do a similar thing. It would be better to have a common function, with perhaps some events for things that are really arch- and board-specific. Create a new bootm_final() function with the common pre-boot steps: printing the "Starting kernel" message, recording bootstage data, optionally writing bootstage to the FDT and printing a report, and removing active devices. Be careful to avoid using BIT() macros which are not available with host tools. Signed-off-by: Simon Glass Reviewed-by: Tom Rini --- boot/bootm.c | 22 ++++++++++++++++++++++ include/bootm.h | 10 ++++++++++ 2 files changed, 32 insertions(+) (limited to 'include') diff --git a/boot/bootm.c b/boot/bootm.c index 4bdca22ea8c..cba10b5dce7 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -7,6 +7,7 @@ #ifndef USE_HOSTCC #include #include +#include #include #include #include @@ -1194,6 +1195,27 @@ void __weak switch_to_non_secure_mode(void) { } +void bootm_final(int flag) +{ + printf("\nStarting kernel ...%s\n\n", + (flag & BOOTM_STATE_OS_FAKE_GO) ? + " (fake run for tracing)" : ""); + + bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel"); + + if (IS_ENABLED(CONFIG_BOOTSTAGE_FDT) && IS_ENABLED(CONFIG_CMD_FDT)) + bootstage_fdt_add_report(); + if (IS_ENABLED(CONFIG_BOOTSTAGE_REPORT)) + bootstage_report(); + + /* + * Call remove function of all devices with a removal flag set. + * This may be useful for last-stage operations, like cancelling + * of DMA operation or releasing device internal buffers. + */ + dm_remove_devices_active(); +} + #else /* USE_HOSTCC */ #if defined(CONFIG_FIT_SIGNATURE) diff --git a/include/bootm.h b/include/bootm.h index 4060cec7fc0..f6958be751a 100644 --- a/include/bootm.h +++ b/include/bootm.h @@ -321,4 +321,14 @@ void zimage_dump(struct boot_params *base_ptr, bool show_cmdline); */ int bootm_boot_start(ulong addr, const char *cmdline); +/** + * bootm_final() - Announce and do cleanup before boot + * + * This performs the common pre-boot steps: printing the "Starting kernel" + * message, recording bootstage data, and removing active devices. + * + * @flag: Boot state flags (BOOTM_STATE_OS_FAKE_GO prints a fake-run message) + */ +void bootm_final(int flag); + #endif -- cgit v1.3.1 From 0a1f0404a6f4faeab78cd040e25a7fee87837104 Mon Sep 17 00:00:00 2001 From: Svyatoslav Ryhel Date: Fri, 6 Feb 2026 16:33:38 +0200 Subject: power: regulator: cpcap: remove bit_offset_from_cpcap_lowest_voltage The bit_offset_from_cpcap_lowest_voltage value was inherited from the downstream kernel as a quirk. With the correct voltage table, it is no longer needed. An additional benefit is that SW1, SW2, and SW4 now share the same voltage table. Signed-off-by: Svyatoslav Ryhel --- drivers/power/regulator/cpcap_regulator.c | 53 +++++++++++++++---------------- include/power/cpcap.h | 48 +++++++++------------------- 2 files changed, 40 insertions(+), 61 deletions(-) (limited to 'include') diff --git a/drivers/power/regulator/cpcap_regulator.c b/drivers/power/regulator/cpcap_regulator.c index 04cd6651374..15426675066 100644 --- a/drivers/power/regulator/cpcap_regulator.c +++ b/drivers/power/regulator/cpcap_regulator.c @@ -55,7 +55,7 @@ #define CPCAP_REG(_reg, _assignment_reg, _assignment_mask, _mode_mask, \ _volt_mask, _volt_shft, _mode_val, _off_mode_val, _val_tbl, \ - _mode_cntr, _volt_trans_time, _turn_on_time, _bit_offset) { \ + _mode_cntr, _volt_trans_time, _turn_on_time) { \ .reg = CPCAP_REG_##_reg, \ .assignment_reg = CPCAP_REG_##_assignment_reg, \ .assignment_mask = CPCAP_BIT_##_assignment_mask, \ @@ -69,60 +69,59 @@ .mode_cntr = _mode_cntr, \ .volt_trans_time = _volt_trans_time, \ .turn_on_time = _turn_on_time, \ - .bit_offset_from_cpcap_lowest_voltage = _bit_offset, \ } static const struct cpcap_regulator_data tegra20_regulators[CPCAP_REGULATORS_COUNT] = { /* BUCK */ [CPCAP_SW1] = CPCAP_REG(S1C1, ASSIGN2, SW1_SEL, 0x6f00, 0x007f, - 0, 0x6800, 0, sw1_val_tbl, 0, 0, 1500, 0x0c), + 0, 0x6800, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW2] = CPCAP_REG(S2C1, ASSIGN2, SW2_SEL, 0x6f00, 0x007f, - 0, 0x4804, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4804, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW3] = CPCAP_REG(S3C, ASSIGN2, SW3_SEL, 0x0578, 0x0003, - 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0, 0), + 0, 0x043c, 0, sw3_val_tbl, 0, 0, 0), [CPCAP_SW4] = CPCAP_REG(S4C1, ASSIGN2, SW4_SEL, 0x6f00, 0x007f, - 0, 0x4909, 0, sw2_sw4_val_tbl, 0, 0, 1500, 0x18), + 0, 0x4909, 0, sw_val_tbl, 0, 0, 1500), [CPCAP_SW5] = CPCAP_REG(S5C, ASSIGN2, SW5_SEL, 0x0028, 0x0000, - 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500, 0), + 0, 0x0020, 0, sw5_val_tbl, 0, 0, 1500), [CPCAP_SW6] = CPCAP_REG(S6C, ASSIGN2, SW6_SEL, 0x0000, 0x0000, - 0, 0, 0, unknown_val_tbl, 0, 0, 0, 0), + 0, 0, 0, unknown_val_tbl, 0, 0, 0), /* LDO */ [CPCAP_VCAM] = CPCAP_REG(VCAMC, ASSIGN2, VCAM_SEL, 0x0087, 0x0030, - 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000, 0), + 4, 0x7, 0, vcam_val_tbl, 0, 420, 1000), [CPCAP_VCSI] = CPCAP_REG(VCSIC, ASSIGN3, VCSI_SEL, 0x0047, 0x0010, - 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000, 0), + 4, 0x7, 0, vcsi_val_tbl, 0, 350, 1000), [CPCAP_VDAC] = CPCAP_REG(VDACC, ASSIGN3, VDAC_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdac_val_tbl, 0, 420, 1000), [CPCAP_VDIG] = CPCAP_REG(VDIGC, ASSIGN2, VDIG_SEL, 0x0087, 0x0030, - 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vdig_val_tbl, 0, 420, 1000), [CPCAP_VFUSE] = CPCAP_REG(VFUSEC, ASSIGN3, VFUSE_SEL, 0x00a0, 0x000f, - 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000, 0), + 0, 0x0, 0, vfuse_val_tbl, 0, 420, 1000), [CPCAP_VHVIO] = CPCAP_REG(VHVIOC, ASSIGN3, VHVIO_SEL, 0x0017, 0x0000, - 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000, 0), + 0, 0x2, 0, vhvio_val_tbl, 0, 0, 1000), [CPCAP_VSDIO] = CPCAP_REG(VSDIOC, ASSIGN2, VSDIO_SEL, 0x0087, 0x0038, - 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000, 0), + 3, 0x2, 0, vsdio_val_tbl, 0, 420, 1000), [CPCAP_VPLL] = CPCAP_REG(VPLLC, ASSIGN3, VPLL_SEL, 0x0047, 0x0018, - 3, 0x1, 0, vpll_val_tbl, 0, 420, 100, 0), + 3, 0x1, 0, vpll_val_tbl, 0, 420, 100), [CPCAP_VRF1] = CPCAP_REG(VRF1C, ASSIGN3, VRF1_SEL, 0x00ac, 0x0002, - 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000, 0), + 1, 0x0, 0, vrf1_val_tbl, 0, 10, 1000), [CPCAP_VRF2] = CPCAP_REG(VRF2C, ASSIGN3, VRF2_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000, 0), + 3, 0x0, 0, vrf2_val_tbl, 0, 10, 1000), [CPCAP_VRFREF] = CPCAP_REG(VRFREFC, ASSIGN3, VRFREF_SEL, 0x0023, 0x0008, - 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100, 0), + 3, 0x0, 0, vrfref_val_tbl, 0, 420, 100), [CPCAP_VWLAN1] = CPCAP_REG(VWLAN1C, ASSIGN3, VWLAN1_SEL, 0x0047, 0x0010, - 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000, 0), + 4, 0x0, 0, vwlan1_val_tbl, 0, 420, 1000), [CPCAP_VWLAN2] = CPCAP_REG(VWLAN2C, ASSIGN3, VWLAN2_SEL, 0x020c, 0x00c0, - 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000, 0), + 6, 0xd, 0, vwlan2_val_tbl, 0, 420, 1000), [CPCAP_VSIM] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x0023, 0x0008, - 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000, 0), + 3, 0x0, 0, vsim_val_tbl, 0, 420, 1000), [CPCAP_VSIMCARD] = CPCAP_REG(VSIMC, ASSIGN3, NONE, 0x1e80, 0x0008, - 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000, 0), + 3, 0x1E00, 0, vsimcard_val_tbl, 0, 420, 1000), [CPCAP_VVIB] = CPCAP_REG(VVIBC, ASSIGN3, VVIB_SEL, 0x0001, 0x000c, - 2, 0x1, 0, vvib_val_tbl, 0, 500, 500, 0), + 2, 0x1, 0, vvib_val_tbl, 0, 500, 500), [CPCAP_VUSB] = CPCAP_REG(VUSBC, ASSIGN3, VUSB_SEL, 0x011c, 0x0040, - 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000, 0), + 6, 0xc, 0, vusb_val_tbl, 0, 0, 1000), [CPCAP_VAUDIO] = CPCAP_REG(VAUDIOC, ASSIGN4, VAUDIO_SEL, 0x0016, 0x0001, - 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000, 0), + 0, 0x5, 0, vaudio_val_tbl, 0, 0, 1000), }; static int cpcap_regulator_get_value(struct udevice *dev) @@ -139,7 +138,6 @@ static int cpcap_regulator_get_value(struct udevice *dev) return 0; value &= regulator->volt_mask; - value -= regulator->bit_offset_from_cpcap_lowest_voltage; return regulator->val_tbl[value >> volt_shift]; } @@ -164,7 +162,6 @@ static int cpcap_regulator_set_value(struct udevice *dev, int uV) value = regulator->val_tbl_sz; value <<= volt_shift; - value += regulator->bit_offset_from_cpcap_lowest_voltage; } ret = pmic_clrsetbits(dev->parent, regulator->reg, regulator->volt_mask, diff --git a/include/power/cpcap.h b/include/power/cpcap.h index bb0e28cec55..b035b84840f 100644 --- a/include/power/cpcap.h +++ b/include/power/cpcap.h @@ -297,32 +297,21 @@ static const char * const cpcap_regulator_to_name[] = { }; static const u32 unknown_val_tbl[] = { 0, }; -static const u32 sw1_val_tbl[] = { 750000, 762500, 775000, 787500, 800000, - 812500, 825000, 837500, 850000, 862500, - 875000, 887500, 900000, 912500, 925000, - 937500, 950000, 962500, 975000, 987500, - 1000000, 1012500, 1025000, 1037500, - 1050000, 1062500, 1075000, 1087500, - 1100000, 1112500, 1125000, 1137500, - 1150000, 1162500, 1175000, 1187500, - 1200000, 1212500, 1225000, 1237500, - 1250000, 1262500, 1275000, 1287500, - 1300000, 1312500, 1325000, 1337500, - 1350000, 1362500, 1375000, 1387500, - 1400000, 1412500, 1425000, 1437500, - 1450000, 1462500, 1475000 }; -static const u32 sw2_sw4_val_tbl[] = { 900000, 912500, 925000, 937500, 950000, - 962500, 975000, 987500, 1000000, 1012500, - 1025000, 1037500, 1050000, 1062500, - 1075000, 1087500, 1100000, 1112500, - 1125000, 1137500, 1150000, 1162500, - 1175000, 1187500, 1200000, 1212500, - 1225000, 1237500, 1250000, 1262500, - 1275000, 1287500, 1300000, 1312500, - 1325000, 1337500, 1350000, 1362500, - 1375000, 1387500, 1400000, 1412500, - 1425000, 1437500, 1450000, 1462500, - 1475000 }; +static const u32 sw_val_tbl[] = { 600000, 612500, 625000, 637500, 650000, + 662500, 675000, 687500, 700000, 712500, + 725000, 737500, 750000, 762500, 775000, + 787500, 800000, 812500, 825000, 837500, + 850000, 862500, 875000, 887500, 900000, + 912500, 925000, 937500, 950000, 962500, + 975000, 987500, 1000000, 1012500, 1025000, + 1037500, 1050000, 1062500, 1075000, 1087500, + 1100000, 1112500, 1125000, 1137500, 1150000, + 1162500, 1175000, 1187500, 1200000, 1212500, + 1225000, 1237500, 1250000, 1262500, 1275000, + 1287500, 1300000, 1312500, 1325000, 1337500, + 1350000, 1362500, 1375000, 1387500, 1400000, + 1412500, 1425000, 1437500, 1450000, 1462500, + 1475000, }; static const u32 sw3_val_tbl[] = { 1350000, 1800000, 1850000, 1875000 }; static const u32 sw5_val_tbl[] = { 0, 5050000 }; static const u32 vcam_val_tbl[] = { 2600000, 2700000, 2800000, 2900000 }; @@ -361,13 +350,6 @@ struct cpcap_regulator_data { u32 mode_cntr; u32 volt_trans_time; /* in micro seconds */ u32 turn_on_time; /* in micro seconds */ - - /* - * Bit difference between lowest value in val_tbl and start of voltage - * table setting in cpcap. Use this for switchers that have many too - * many voltages to list in val_tbl. - */ - u32 bit_offset_from_cpcap_lowest_voltage; }; #endif /* _CPCAP_H_ */ -- cgit v1.3.1 From 264cbb187180b633130070eeae815d15ea6534dd Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 11 Mar 2026 22:39:35 +0300 Subject: scmi: pinctrl: add pinctrl message IDs Add all the pinctrl message IDs. I renamed SCMI_MSG_PINCTRL_CONFIG_SET to SCMI_PINCTRL_SETTINGS_CONFIGURE so the naming matches the spec better. Signed-off-by: Dan Carpenter Reviewed-by: Peng Fan Reviewed-by: Linus Walleij Signed-off-by: Peng Fan --- drivers/pinctrl/nxp/pinctrl-imx-scmi.c | 2 +- include/scmi_protocols.h | 9 ++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c index 3cc2b85e151..dcd76fdc571 100644 --- a/drivers/pinctrl/nxp/pinctrl-imx-scmi.c +++ b/drivers/pinctrl/nxp/pinctrl-imx-scmi.c @@ -70,7 +70,7 @@ static int imx_pinconf_scmi_set(struct udevice *dev, u32 mux_ofs, u32 mux, u32 c in.attributes = num_cfgs << PINCTRL_NUM_CFGS_SHIFT; msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_PINCTRL, - SCMI_MSG_PINCTRL_CONFIG_SET, in, out); + SCMI_PINCTRL_SETTINGS_CONFIGURE, in, out); ret = devm_scmi_process_msg(dev, &msg); if (ret || out.status) { diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 555ffa0a61b..e1d788058fb 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -1089,7 +1089,14 @@ struct scmi_voltd_level_get_out { /* SCMI Pinctrl Protocol */ enum scmi_pinctrl_message_id { - SCMI_MSG_PINCTRL_CONFIG_SET = 0x6 + SCMI_PINCTRL_ATTRIBUTES = 0x3, + SCMI_PINCTRL_LIST_ASSOCIATIONS = 0x4, + SCMI_PINCTRL_SETTINGS_GET = 0x5, + SCMI_PINCTRL_SETTINGS_CONFIGURE = 0x6, + SCMI_PINCTRL_REQUEST = 0x7, + SCMI_PINCTRL_RELEASE = 0x8, + SCMI_PINCTRL_NAME_GET = 0x9, + SCMI_PINCTRL_SET_PERMISSIONS = 0xA, }; struct scmi_pin_config { -- cgit v1.3.1 From 33dbe00fbb21cd2494e374ead8ab5dc8a8dca8b6 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 11 Mar 2026 22:39:39 +0300 Subject: scmi: update comments for scmi_pinctrl_config_set_in() Delete some extra space characters to make checkpatch.pl happy: WARNING: please, no space before tabs Signed-off-by: Dan Carpenter Acked-by: Peng Fan Signed-off-by: Peng Fan --- include/scmi_protocols.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index e1d788058fb..d5175551490 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -1108,14 +1108,14 @@ struct scmi_pin_config { * struct scmi_pinctrl_config_set_in - Message payload for PAD_CONFIG_SET command * @identifier: Identifier for the pin or group. * @function_id: Identifier for the function selected to be enabled - * for the selected pin or group. This field is set to - * 0xFFFFFFFF if no function should be enabled by the - * pin or group. + * for the selected pin or group. This field is set to + * 0xFFFFFFFF if no function should be enabled by the + * pin or group. * @attributes: Bits[31:11] Reserved, must be zero. - * Bit[10] Function valid. - * Bits[9:2] Number of configurations to set. - * Bits[1:0] Selector: Whether the identifier field - * refers to a pin or a group. + * Bit[10] Function valid. + * Bits[9:2] Number of configurations to set. + * Bits[1:0] Selector: Whether the identifier field + * refers to a pin or a group. * @configs: Array of configurations. */ struct scmi_pinctrl_config_set_in { -- cgit v1.3.1 From 0cb160f1b62905c701569850d3a4d1b46b3dc100 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 11 Mar 2026 22:41:25 +0300 Subject: scmi: pinctrl: add pinctrl driver for SCMI This driver adds the base support of pinctrl over SCMI. The driver does two main things. First, it allows you to configure the initial pin states. Secondly, it's used a base to build a GPIO driver on top of it. To configure the states then add a pinmux config to the scmi_pinctrl section: scmi_pinctrl: protocol@19 { reg = <0x19>; pinmux1: pinmux_test { pinmux = <0 1 0xFFFFFFFF 18 1 0 2 0xFFFFFFFF 18 1 0 3 0xFFFFFFFF 18 1>; function = "f_gpio1"; groups = "grp_1", "grp_3"; }; }; Under linux the pinctrl subsystem will parse the function and group properties and use that to handle muxing. However, under u-boot the pin muxing is done using the "pinmux" property, which feeds raw SCMI pinctrl PINCTRL_SETTINGS_CONFIGURE commands to the server. The numbers are: selector, identifier, function_id, config_type, and config_value. In the example above, it sets pins 1, 2, and 3 to 1. The linux-kernel ignores this pinmux property. Signed-off-by: Dan Carpenter Reviewed-by: Peng Fan Signed-off-by: Peng Fan --- drivers/firmware/scmi/Makefile | 1 + drivers/firmware/scmi/pinctrl.c | 365 ++++++++++++++++++++++++++++++ drivers/firmware/scmi/scmi_agent-uclass.c | 4 +- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-scmi.c | 365 ++++++++++++++++++++++++++++++ include/scmi_agent-uclass.h | 2 +- include/scmi_protocols.h | 356 +++++++++++++++++++++++++++++ 8 files changed, 1100 insertions(+), 3 deletions(-) create mode 100644 drivers/firmware/scmi/pinctrl.c create mode 100644 drivers/pinctrl/pinctrl-scmi.c (limited to 'include') diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile index 6129726f817..761d89a1161 100644 --- a/drivers/firmware/scmi/Makefile +++ b/drivers/firmware/scmi/Makefile @@ -5,5 +5,6 @@ obj-$(CONFIG_SCMI_AGENT_SMCCC) += smccc_agent.o obj-$(CONFIG_SCMI_AGENT_MAILBOX) += mailbox_agent.o obj-$(CONFIG_SCMI_AGENT_OPTEE) += optee_agent.o obj-$(CONFIG_SCMI_POWER_DOMAIN) += pwdom.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl.o obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o sandbox-scmi_devices.o obj-y += vendors/imx/ diff --git a/drivers/firmware/scmi/pinctrl.c b/drivers/firmware/scmi/pinctrl.c new file mode 100644 index 00000000000..47f7a8ad9b8 --- /dev/null +++ b/drivers/firmware/scmi/pinctrl.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#define LOG_CATEGORY UCLASS_PINCTRL + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static int map_config_param_to_scmi(u32 config_param) +{ + switch (config_param) { + case PIN_CONFIG_BIAS_BUS_HOLD: + return SCMI_PIN_BIAS_BUS_HOLD; + case PIN_CONFIG_BIAS_DISABLE: + return SCMI_PIN_BIAS_DISABLE; + case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: + return SCMI_PIN_BIAS_HIGH_IMPEDANCE; + case PIN_CONFIG_BIAS_PULL_DOWN: + return SCMI_PIN_BIAS_PULL_DOWN; + case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: + return SCMI_PIN_BIAS_PULL_DEFAULT; + case PIN_CONFIG_BIAS_PULL_UP: + return SCMI_PIN_BIAS_PULL_UP; + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + return SCMI_PIN_DRIVE_OPEN_DRAIN; + case PIN_CONFIG_DRIVE_OPEN_SOURCE: + return SCMI_PIN_DRIVE_OPEN_SOURCE; + case PIN_CONFIG_DRIVE_PUSH_PULL: + return SCMI_PIN_DRIVE_PUSH_PULL; + case PIN_CONFIG_DRIVE_STRENGTH: + return SCMI_PIN_DRIVE_STRENGTH; + case PIN_CONFIG_INPUT_DEBOUNCE: + return SCMI_PIN_INPUT_DEBOUNCE; + case PIN_CONFIG_INPUT_ENABLE: + return SCMI_PIN_INPUT_MODE; + case PIN_CONFIG_INPUT_SCHMITT: + return SCMI_PIN_INPUT_SCHMITT; + case PIN_CONFIG_LOW_POWER_MODE: + return SCMI_PIN_LOW_POWER_MODE; + case PIN_CONFIG_OUTPUT_ENABLE: + return SCMI_PIN_OUTPUT_MODE; + case PIN_CONFIG_OUTPUT: + return SCMI_PIN_OUTPUT_VALUE; + case PIN_CONFIG_POWER_SOURCE: + return SCMI_PIN_POWER_SOURCE; + case PIN_CONFIG_SLEW_RATE: + return SCMI_PIN_SLEW_RATE; + } + + return -EINVAL; +} + +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions) +{ + struct scmi_pinctrl_protocol_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PROTOCOL_ATTRIBUTES, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (num_groups) + *num_groups = FIELD_GET(GENMASK(31, 16), out.attr_low); + if (num_pins) + *num_pins = FIELD_GET(GENMASK(15, 0), out.attr_low); + if (num_functions) + *num_functions = FIELD_GET(GENMASK(15, 0), out.attr_high); + + return 0; +} + +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name) +{ + struct scmi_pinctrl_attrs_in in; + struct scmi_pinctrl_attrs_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_ATTRIBUTES, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.select_type = select_type; + in.id = selector; + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + if (gpio) + *gpio = FIELD_GET(BIT(17), out.attr); + if (count) + *count = FIELD_GET(GENMASK(15, 0), out.attr); + if (name) + strncpy(name, out.name, sizeof(out.name)); + + return 0; +} + +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out) +{ + struct scmi_pinctrl_list_associations_in in; + struct scmi_pinctrl_list_associations_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_LIST_ASSOCIATIONS, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + num_out * sizeof(out->array[0]); + unsigned int count; + int ret = -EINVAL; + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.select_type = select_type; + in.id = selector; + in.index = 0; + + while (num_out > 0) { + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + + count = FIELD_GET(GENMASK(11, 0), out->flags); + if (count > num_out) + return -EINVAL; + memcpy(&output[in.index], out->array, count * sizeof(u16)); + num_out -= count; + in.index += count; + } +free: + kfree(out); + return ret; +} + +#define SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION -2u + +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value) +{ + struct scmi_pinctrl_settings_get_in in; + struct scmi_pinctrl_settings_get_out *out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_GET, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + }; + size_t out_sz = sizeof(*out) + (sizeof(u32) * 2); + u32 num_configs; + int ret; + + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_ALL) { + /* FIXME: implement */ + return -EIO; + } + + out = kzalloc(out_sz, GFP_KERNEL); + if (!out) + return -ENOMEM; + + msg.out_msg = (u8 *)out; + msg.out_msg_sz = out_sz; + in.id = selector; + in.attr = 0; + if (config_type == SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr = FIELD_PREP(GENMASK(19, 18), 2); + in.attr |= FIELD_PREP(GENMASK(17, 16), select_type); + if (config_type != SCMI_PINCTRL_CONFIG_SETTINGS_FUNCTION) + in.attr |= FIELD_PREP(GENMASK(7, 0), config_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out->status) { + ret = scmi_to_linux_errno(out->status); + goto free; + } + num_configs = FIELD_GET(GENMASK(7, 0), out->num_configs); + if (out->num_configs == 0) { + *value = out->function_selected; + goto free; + } + if (num_configs != 1) { + ret = -EINVAL; + goto free; + } + + *value = out->configs[1]; +free: + kfree(out); + return ret; +} + +static int scmi_pinctrl_settings_configure_helper(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + u32 function_id, + u16 num_configs, u32 *configs) +{ + struct scmi_pinctrl_settings_configure_in *in; + struct scmi_pinctrl_settings_configure_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_SETTINGS_CONFIGURE, + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + size_t in_sz = sizeof(*in) + (num_configs * sizeof(u32) * 2); + int ret; + + in = kzalloc(in_sz, GFP_KERNEL); + if (!in) + return -ENOMEM; + + msg.in_msg = (u8 *)in; + msg.in_msg_sz = in_sz; + in->id = selector; + in->function_id = function_id; + in->attr = 0; + in->attr |= FIELD_PREP(GENMASK(9, 2), num_configs); + in->attr |= FIELD_PREP(GENMASK(1, 0), select_type); + memcpy(in->configs, configs, num_configs * sizeof(u32) * 2); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + goto free; + if (out.status) { + ret = scmi_to_linux_errno(out.status); + goto free; + } +free: + kfree(in); + return ret; +} + +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, + selector, + SCMI_PINCTRL_FUNCTION_NONE, + num_configs, configs); +} + +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument) +{ + u32 config_value[2]; + int scmi_config; + + /* see stmfx_pinctrl_conf_set() */ + scmi_config = map_config_param_to_scmi(param); + if (scmi_config < 0) + return scmi_config; + + config_value[0] = scmi_config; + config_value[1] = argument; + + return scmi_pinctrl_settings_configure(dev, select_type, selector, 1, + &config_value[0]); +} + +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id) +{ + return scmi_pinctrl_settings_configure_helper(dev, select_type, selector, + function_id, 0, NULL); +} + +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_request_in in; + struct scmi_pinctrl_request_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_REQUEST, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector) +{ + struct scmi_pinctrl_release_in in; + struct scmi_pinctrl_release_out out; + struct scmi_msg msg = { + .protocol_id = SCMI_PROTOCOL_ID_PINCTRL, + .message_id = SCMI_PINCTRL_RELEASE, + .in_msg = (u8 *)&in, + .in_msg_sz = sizeof(in), + .out_msg = (u8 *)&out, + .out_msg_sz = sizeof(out), + }; + int ret; + + in.id = selector; + in.flags = FIELD_PREP(GENMASK(1, 0), select_type); + + ret = devm_scmi_process_msg(dev, &msg); + if (ret) + return ret; + if (out.status) + return scmi_to_linux_errno(out.status); + + return 0; +} + diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index ad825d66da2..cd458a7f458 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -106,7 +106,7 @@ struct udevice *scmi_get_protocol(struct udevice *dev, proto = priv->voltagedom_dev; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: proto = priv->pinctrl_dev; break; @@ -179,7 +179,7 @@ static int scmi_add_protocol(struct udevice *dev, priv->voltagedom_dev = proto; break; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) case SCMI_PROTOCOL_ID_PINCTRL: priv->pinctrl_dev = proto; break; diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 73dd5ff4a79..d9d4f7ceb83 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -291,6 +291,15 @@ config PINCTRL_SANDBOX Currently, this driver actually does nothing but print debug messages when pinctrl operations are invoked. +config PINCTRL_SCMI + bool "Support SCMI pin controllers" + depends on PINCTRL_FULL && SCMI_FIRMWARE + help + This is for pinctrl over the SCMI protocol. This allows the + initial pin configuration to be set up from the device tree. The + gpio_scmi driver is built on top of this driver if GPIO is + required. + config PINCTRL_SINGLE bool "Single register pin-control and pin-multiplex driver" depends on DM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 4fb6cef3113..29fb9b484d0 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_NEXELL) += nexell/ obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o diff --git a/drivers/pinctrl/pinctrl-scmi.c b/drivers/pinctrl/pinctrl-scmi.c new file mode 100644 index 00000000000..63d4f8ffeb5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-scmi.c @@ -0,0 +1,365 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2026 Linaro Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +static const struct pinconf_param pinctrl_scmi_conf_params[] = { + { "bias-bus-hold", PIN_CONFIG_BIAS_BUS_HOLD, 0}, + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-high-impedance", PIN_CONFIG_BIAS_HIGH_IMPEDANCE, 0 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 0 }, + { "bias-pull-pin-default", PIN_CONFIG_BIAS_PULL_PIN_DEFAULT, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, + { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, + { "input-schmitt", PIN_CONFIG_INPUT_SCHMITT, 0 }, + { "low-power-mode", PIN_CONFIG_LOW_POWER_MODE, 0 }, + { "output-mode", PIN_CONFIG_OUTPUT_ENABLE, 0 }, + { "output-value", PIN_CONFIG_OUTPUT, 0 }, + { "power-source", PIN_CONFIG_POWER_SOURCE, 0 }, + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 }, + /* The SCMI spec also include "default", "pull-mode" and "input-value */ +}; + +static bool valid_selector(struct udevice *dev, enum select_type select_type, u32 selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (select_type == SCMI_PIN) + return selector < priv->num_pins; + if (select_type == SCMI_GROUP) + return selector < priv->num_groups; + if (select_type == SCMI_FUNCTION) + return selector < priv->num_functions; + + return false; +} + +static int pinctrl_scmi_get_pins_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_pins; +} + +static int pinctrl_scmi_get_groups_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_groups; +} + +static int pinctrl_scmi_get_functions_count(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + return priv->num_functions; +} + +static const char *pinctrl_scmi_get_pin_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_pins) + return NULL; + + return (const char *)priv->pin_info[selector].name; +} + +static const char *pinctrl_scmi_get_group_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_groups) + return NULL; + + return (const char *)priv->group_info[selector].name; +} + +static const char *pinctrl_scmi_get_function_name(struct udevice *dev, unsigned int selector) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (selector >= priv->num_functions) + return NULL; + + return (const char *)priv->function_info[selector].name; +} + +static int pinctrl_scmi_pinmux_set(struct udevice *dev, u32 pin, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (pin >= priv->num_pins || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_PIN, pin, function); +} + +static int pinctrl_scmi_pinmux_group_set(struct udevice *dev, u32 group, u32 function) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + + if (group >= priv->num_groups || function >= priv->num_functions) + return -EINVAL; + + return scmi_pinctrl_set_function(dev, SCMI_GROUP, group, function); +} + +static int pinctrl_scmi_set_state(struct udevice *dev, struct udevice *config) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + /* batch the setup into 20 lines at a go (there are 5 u32s in a config) */ + const int batch_count = 20 * 5; + u32 prev_type = -1u; + u32 prev_selector; + u32 *configs; + const u32 *prop; + int offset, cnt, len; + int ret = 0; + + prop = dev_read_prop(config, "pinmux", &len); + if (!prop) + return 0; + + if (len % sizeof(u32) * 5) { + dev_err(dev, "invalid pin configuration: len=%d\n", len); + return -FDT_ERR_BADSTRUCTURE; + } + + configs = kcalloc(batch_count, sizeof(u32), GFP_KERNEL); + if (!configs) + return -ENOMEM; + + offset = 0; + cnt = 0; + while (offset + 4 < len / sizeof(u32)) { + u32 select_type = fdt32_to_cpu(prop[offset]); + u32 selector = fdt32_to_cpu(prop[offset + 1]); + u32 function = fdt32_to_cpu(prop[offset + 2]); + u32 config_type = fdt32_to_cpu(prop[offset + 3]); + u32 config_value = fdt32_to_cpu(prop[offset + 4]); + + if (select_type > SCMI_GROUP || + !valid_selector(dev, select_type, selector) || + (function != SCMI_PINCTRL_FUNCTION_NONE && + function > priv->num_functions)) { + dev_err(dev, "invalid pinctrl data (%u %u %u %u %u)\n", + select_type, selector, function, config_type, + config_value); + ret = -EINVAL; + goto free; + } + + if (function != SCMI_PINCTRL_FUNCTION_NONE) { + if (cnt) { + ret = scmi_pinctrl_settings_configure(dev, + prev_type, + prev_selector, + cnt / 2, configs); + if (ret) + goto free; + prev_type = -1u; + cnt = 0; + } + scmi_pinctrl_set_function(dev, select_type, selector, function); + offset += 5; + continue; + } + + if (cnt == batch_count) + goto set; + + if (prev_type == -1u) + goto store; + + if (select_type == prev_type && selector == prev_selector) + goto store; +set: + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); + if (ret) + goto free; + cnt = 0; +store: + prev_type = select_type; + prev_selector = selector; + configs[cnt++] = config_type; + configs[cnt++] = config_value; + offset += 5; + } + + if (cnt) + ret = scmi_pinctrl_settings_configure(dev, prev_type, prev_selector, + cnt / 2, configs); +free: + kfree(configs); + if (ret) + dev_err(dev, "set_state() failed: %d\n", ret); + + return ret; +} + +static int get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + u32 value; + int ret; + + ret = scmi_pinctrl_settings_get_one(dev, SCMI_PIN, selector, + SCMI_PIN_INPUT_VALUE, &value); + if (ret) { + dev_err(dev, "settings_get() failed: %d\n", ret); + return ret; + } + + snprintf(buf, size, "%d", value); + return 0; +} + +static int pinctrl_scmi_pinconf_set(struct udevice *dev, u32 pin, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_PIN, pin, param, argument); +} + +static int pinctrl_scmi_pinconf_group_set(struct udevice *dev, u32 group, u32 param, u32 argument) +{ + return scmi_pinctrl_settings_configure_one(dev, SCMI_GROUP, group, param, argument); +} + +static struct pinctrl_ops scmi_pinctrl_ops = { + .get_pins_count = pinctrl_scmi_get_pins_count, + .get_pin_name = pinctrl_scmi_get_pin_name, + + .get_groups_count = pinctrl_scmi_get_groups_count, + .get_group_name = pinctrl_scmi_get_group_name, + + .get_functions_count = pinctrl_scmi_get_functions_count, + .get_function_name = pinctrl_scmi_get_function_name, + + .pinmux_set = pinctrl_scmi_pinmux_set, + .pinmux_group_set = pinctrl_scmi_pinmux_group_set, + + .pinconf_num_params = ARRAY_SIZE(pinctrl_scmi_conf_params), + .pinconf_params = pinctrl_scmi_conf_params, + + .pinconf_set = pinctrl_scmi_pinconf_set, + .pinconf_group_set = pinctrl_scmi_pinconf_group_set, + .set_state = pinctrl_scmi_set_state, + .get_pin_muxing = get_pin_muxing, +}; + +static int scmi_pinctrl_probe(struct udevice *dev) +{ + struct pinctrl_scmi_priv *priv = dev_get_priv(dev); + int ret; + int i; + + ret = devm_scmi_of_get_channel(dev); + if (ret) { + dev_err(dev, "get_channel() failed: %d\n", ret); + return ret; + } + + ret = scmi_pinctrl_protocol_attrs(dev, &priv->num_pins, + &priv->num_groups, + &priv->num_functions); + if (ret) { + dev_err(dev, "failed to get protocol attributes: %d\n", ret); + return ret; + } + + priv->pin_info = devm_kcalloc(dev, priv->num_pins, + sizeof(*priv->pin_info), GFP_KERNEL); + priv->group_info = devm_kcalloc(dev, priv->num_groups, + sizeof(*priv->group_info), GFP_KERNEL); + priv->function_info = devm_kcalloc(dev, priv->num_functions, + sizeof(*priv->function_info), GFP_KERNEL); + if (!priv->pin_info || !priv->group_info || !priv->function_info) + return -ENOMEM; + + for (i = 0; i < priv->num_pins; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_PIN, i, NULL, NULL, + priv->pin_info[i].name); + if (ret) + return ret; + } + + for (i = 0; i < priv->num_groups; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_GROUP, i, NULL, + &priv->group_info[i].num_pins, + priv->group_info[i].name); + if (ret) { + dev_err(dev, "loading group %d failed: %d\n", i, ret); + return ret; + } + priv->group_info[i].pins = devm_kcalloc(dev, + priv->group_info[i].num_pins, + sizeof(*priv->group_info[i].pins), + GFP_KERNEL); + if (!priv->group_info[i].pins) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_GROUP, i, + priv->group_info[i].pins, + priv->group_info[i].num_pins); + if (ret) { + dev_err(dev, "list association %d failed for group: %d\n", i, ret); + return ret; + } + } + + for (i = 0; i < priv->num_functions; i++) { + ret = scmi_pinctrl_attrs(dev, SCMI_FUNCTION, i, NULL, + &priv->function_info[i].num_groups, + priv->function_info[i].name); + if (ret) { + dev_err(dev, "loading function %d failed: %d\n", i, ret); + return ret; + } + priv->function_info[i].groups = devm_kcalloc(dev, + priv->function_info[i].num_groups, + sizeof(*priv->function_info[i].groups), + GFP_KERNEL); + if (!priv->function_info[i].groups) + return -ENOMEM; + + ret = scmi_pinctrl_list_associations(dev, SCMI_FUNCTION, i, + priv->function_info[i].groups, + priv->function_info[i].num_groups); + if (ret) { + dev_err(dev, "list association %d failed for function: %d\n", i, ret); + return ret; + } + } + + return 0; +} + +U_BOOT_DRIVER(pinctrl_scmi) = { + .name = "scmi_pinctrl", + .id = UCLASS_PINCTRL, + .ops = &scmi_pinctrl_ops, + .probe = scmi_pinctrl_probe, + .priv_auto = sizeof(struct pinctrl_scmi_priv), +}; + +static struct scmi_proto_match match[] = { + { .proto_id = SCMI_PROTOCOL_ID_PINCTRL }, + { /* Sentinel */ } +}; + +U_BOOT_SCMI_PROTO_DRIVER(pinctrl_scmi, match); + diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h index 9b36d3ae67b..c40b448bcba 100644 --- a/include/scmi_agent-uclass.h +++ b/include/scmi_agent-uclass.h @@ -52,7 +52,7 @@ struct scmi_agent_priv { #if IS_ENABLED(CONFIG_DM_REGULATOR_SCMI) struct udevice *voltagedom_dev; #endif -#if IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) +#if IS_ENABLED(CONFIG_PINCTRL_SCMI) || IS_ENABLED(CONFIG_PINCTRL_IMX_SCMI) struct udevice *pinctrl_dev; #endif #if IS_ENABLED(CONFIG_SCMI_ID_VENDOR_80) diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index d5175551490..a8fd0a5a729 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -1147,4 +1147,360 @@ struct scmi_perf_in { struct scmi_perf_out { s32 status; }; + +#define SCMI_PIN_NAME_LEN 16 + +struct pin_info { + char name[SCMI_PIN_NAME_LEN]; +}; + +struct group_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *pins; + u32 num_pins; +}; + +struct function_info { + char name[SCMI_PIN_NAME_LEN]; + u16 *groups; + u32 num_groups; +}; + +/* This is used by both the SCMI pinctrl and gpio drivers */ +struct pinctrl_scmi_priv { + int num_pins; + struct pin_info *pin_info; + int num_groups; + struct group_info *group_info; + int num_functions; + struct function_info *function_info; +}; + +/* SCMI Pinctrl selector type */ +enum select_type { + SCMI_PIN, + SCMI_GROUP, + SCMI_FUNCTION, +}; + +/** + * struct scmi_pinctrl_protocol_attrs_out - Response to SCMI_PROTOCOL_ATTRIBUTES + * command. + * @status: SCMI command status + * @attr_low: Number of pins and groups + * @attr_high: Number of functions + */ +struct scmi_pinctrl_protocol_attrs_out { + s32 status; + u32 attr_low; + u32 attr_high; +}; + +/** + * struct scmi_pinctrl_attrs_in - Parameters for SCMI_PINCTRL_ATTRIBUTES command + * @id: Identifier for pin, group or function + * @select_type: Pin, group or function + */ +struct scmi_pinctrl_attrs_in { + u32 id; + u32 select_type; +}; + +/** + * struct scmi_pinctrl_attrs_out - Response to SCMI_PINCTRL_ATTRIBUTES command + * @status: SCMI command status + * @attr: GPIO, number of pins or groups + * @name: Name of pin, group or function + */ +struct scmi_pinctrl_attrs_out { + s32 status; + u32 attr; + u8 name[SCMI_PIN_NAME_LEN]; +}; + +/** + * struct scmi_pinctrl_list_associations_in - Parameters for + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @id: Identifier for group or function + * @select_type: Group or function + * @index: Index within the group or function + */ +struct scmi_pinctrl_list_associations_in { + u32 id; + u32 select_type; + u32 index; +}; + +/** + * struct scmi_pinctrl_list_associations_out - Response to + * SCMI_PINCTRL_LIST_ASSOCIATIONS command + * @status: SCMI command status + * @flags: Number of items returned and number still remaining + * @array: List of groups or pins + */ +struct scmi_pinctrl_list_associations_out { + s32 status; + u32 flags; + u16 array[]; +}; + +/** + * struct scmi_pinctrl_settings_get_in - Parameters for + * SCMI_PINCTRL_SETTINGS_GET command + * @id: Identifier for pin or group + * @attr: Config flag: one setting, function or all settings + * Selector: Pin or Group + * Skip: Number of config types to skip + * Config type: Type of config to read + */ +struct scmi_pinctrl_settings_get_in { + u32 id; + u32 attr; +}; + +#define SCMI_PINCTRL_CONFIG_SETTINGS_ALL -2u /* This is an internal magic number */ +#define SCMI_PINCTRL_FUNCTION_NONE 0xFFFFFFFF + +/** + * struct scmi_pinctrl_settings_get_out - Response to SCMI_PINCTRL_SETTINGS_GET + * command + * @status: SCMI command status + * @function_selected: The function enabled by the pin or group + * @num_configs: The number of settings returned and number still remaining + * @configs: The list of config data + */ +struct scmi_pinctrl_settings_get_out { + s32 status; + u32 function_selected; + u32 num_configs; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_in - Parameters for + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @id: Identifier for pin or group + * @function_id: The function to enable for this pin or group (optional) + * @attr: Function id: Set the function or not + * Number of configs to set + * Selector: pin or group + * @configs: List of config type value pairs + */ +struct scmi_pinctrl_settings_configure_in { + u32 id; + u32 function_id; + u32 attr; + u32 configs[]; +}; + +/** + * struct scmi_pinctrl_settings_configure_out - Response to + * SCMI_PINCTRL_SETTINGS_CONFIGURE command + * @status: SCMI command status + */ +struct scmi_pinctrl_settings_configure_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_request_in - Parameters for SCMI_PINCTRL_REQUEST command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_request_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_request_out - Response to SCMI_PINCTRL_REQUEST command + * @status: SCMI command status + */ +struct scmi_pinctrl_request_out { + s32 status; +}; + +/** + * struct scmi_pinctrl_release_in - Parameters for SCMI_PINCTRL_RELEASE command + * @id: Identifier for pin or group + * @flags: Pin, group or function + */ +struct scmi_pinctrl_release_in { + u32 id; + u32 flags; +}; + +/** + * struct scmi_pinctrl_release_out - Response to SCMI_PINCTRL_RELEASE command + * @status: SCMI command status + */ +struct scmi_pinctrl_release_out { + s32 status; +}; + +/* SCMI Pinctrl Config Types */ +enum scmi_config_type { + SCMI_PIN_DEFUALT = 0, + SCMI_PIN_BIAS_BUS_HOLD = 1, + SCMI_PIN_BIAS_DISABLE = 2, + SCMI_PIN_BIAS_HIGH_IMPEDANCE = 3, + SCMI_PIN_BIAS_PULL_UP = 4, + SCMI_PIN_BIAS_PULL_DEFAULT = 5, + SCMI_PIN_BIAS_PULL_DOWN = 6, + SCMI_PIN_DRIVE_OPEN_DRAIN = 7, + SCMI_PIN_DRIVE_OPEN_SOURCE = 8, + SCMI_PIN_DRIVE_PUSH_PULL = 9, + SCMI_PIN_DRIVE_STRENGTH = 10, + SCMI_PIN_INPUT_DEBOUNCE = 11, + SCMI_PIN_INPUT_MODE = 12, + SCMI_PIN_PULL_MODE = 13, + SCMI_PIN_INPUT_VALUE = 14, + SCMI_PIN_INPUT_SCHMITT = 15, + SCMI_PIN_LOW_POWER_MODE = 16, + SCMI_PIN_OUTPUT_MODE = 17, + SCMI_PIN_OUTPUT_VALUE = 18, + SCMI_PIN_POWER_SOURCE = 19, + SCMI_PIN_SLEW_RATE = 20, +}; + +/** + * scmi_pinctrl_protocol_attrs - get pinctrl information + * @dev: SCMI protocol device + * @num_pins: Number of pins + * @num_groups: Number of groups + * @num_functions: Number of functions + * + * Obtain the number of pins, groups and functions. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_protocol_attrs(struct udevice *dev, int *num_pins, + int *num_groups, int *num_functions); + +/** + * scmi_pinctrl_attrs - get information for a specific pin, group or function + * @dev: SCMI protocol device + * @select_type: pin, group or function + * @selector: id of pin, group or function + * @gpio: set to true if the pin or group supports gpio + * @count: number of groups in function or pins in group + * @name: name of pin, group or function + * + * Obtain information about a specific pin, group or function. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_attrs(struct udevice *dev, enum select_type select_type, + unsigned int selector, bool *gpio, unsigned int *count, + char *name); + +/** + * scmi_pinctrl_request - claim a pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Claim ownership of a pin or group. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_request(struct udevice *dev, enum select_type select_type, + unsigned int selector); +/** + * scmi_pinctrl_release - release a claimed pin or group + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * + * Release a pin or group that you previously claimed. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_release(struct udevice *dev, enum select_type select_type, + unsigned int selector); + +/** + * scmi_pinctrl_list_associations - get list of pins in group or groups in function + * @dev: SCMI protocol device + * @select_type: group or function + * @selector: id of group or function + * @output: list of groups in function or pins in group + * @num_out: How many groups are in the function or pins in the group + * + * Obtain the list of groups or pins in the function or group respectively. + * We know how many items will be in the list from calling scmi_pinctrl_attrs(). + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_list_associations(struct udevice *dev, + enum select_type select_type, + unsigned int selector, + unsigned short *output, + unsigned short num_out); + +/** + * scmi_pinctrl_settings_get_one - get a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @config_type: Which configuration type to read + * @value: returned configuration value + * + * This reads a single config setting. Most importantly the + * SCMI_PIN_INPUT_VALUE setting is used to read from a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_get_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 config_type, u32 *value); + +/** + * scmi_pinctrl_settings_configure - set multiple configuration settings + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @num_configs: number of settings to set + * @configs: Config type and value pairs + * + * Configure multiple settings at once to reduce overhead. The + * SCMI_PIN_OUTPUT_VALUE setting is used to write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure(struct udevice *dev, enum select_type select_type, + unsigned int selector, u16 num_configs, + u32 *configs); + +/** + * scmi_pinctrl_settings_configure_one - set a configuration setting + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @param: The setting type to configure + * @argument: The value of the configuration + * + * Configure a single setting. The SCMI_PIN_OUTPUT_VALUE setting is used to + * write to a pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_settings_configure_one(struct udevice *dev, enum select_type select_type, + unsigned int selector, + u32 param, u32 argument); + +/** + * scmi_pinctrl_set_function - set the function for a group or pin + * @dev: SCMI protocol device + * @select_type: pin or group + * @selector: id of pin or group + * @function_id: id of the function + * + * Set the function for a group or pin. + * + * Return: 0 on success, error code on failure + */ +int scmi_pinctrl_set_function(struct udevice *dev, enum select_type select_type, + unsigned int selector, u32 function_id); + #endif /* _SCMI_PROTOCOLS_H */ -- cgit v1.3.1 From 67fc505228558efa19380542d801807fa9eee054 Mon Sep 17 00:00:00 2001 From: Han Xu Date: Wed, 25 Feb 2026 15:13:32 -0600 Subject: mmc: Add support for eMMC 5.1B specification Add support for eMMC specification version 5.1B by defining MMC_VERSION_5_1B and including it in the version array. eMMC 5.1B (JESD84-B51B) is a minor revision of the 5.1 specification that primarily addresses MDT (Manufacturing Date) adjustment for dates beyond 2025. This aligns with the Linux kernel commit 9996707822f82 ("mmc: core: Adjust MDT beyond 2025"). Since the manufacturing date field is not currently used in U-Boot, this change has no functional impact beyond proper device recognition. It allows the driver to correctly identify and initialize eMMC devices that report version 5.1B in their Extended CSD register. Signed-off-by: Han Xu Signed-off-by: Peng Fan --- drivers/mmc/mmc.c | 3 ++- include/mmc.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index c5705f4f215..f0e38efb262 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2343,7 +2343,8 @@ static int mmc_startup_v4(struct mmc *mmc) MMC_VERSION_4_41, MMC_VERSION_4_5, MMC_VERSION_5_0, - MMC_VERSION_5_1 + MMC_VERSION_5_1, + MMC_VERSION_5_1B }; #if CONFIG_IS_ENABLED(MMC_TINY) diff --git a/include/mmc.h b/include/mmc.h index 51d3f2f8dd5..9509c9e9543 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -54,6 +54,7 @@ struct bd_info; #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0) +#define MMC_VERSION_5_1B MAKE_MMC_VERSION(5, 1, 0xB) #define MMC_CAP(mode) (1 << mode) #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS)) -- cgit v1.3.1 From 07de5c1e0199b98c9d164482fd2ca0c1fc12be2d Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Fri, 6 Mar 2026 13:48:07 +0100 Subject: arm64: versal2: Fix UFS boot command sequence The BOOTENV_DEV_UFS macro is incomplete - it only initializes UFS and scans SCSI devices but does not actually boot anything. This causes the boot sequence to stop after scsi scan without loading a kernel. Update BOOTENV_DEV_UFS to set the devnum environment variable to the UFS instance number, initialize the device using $devnum, and delegate the boot process to the shared scsi_boot script. Remove the explicit scsi scan, as it is already handled by scsi_boot. This matches the pattern used by other boot device macros and ensures that UFS devices can successfully boot using the distro boot framework. Signed-off-by: Padmarao Begari Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/5447ce1d5c4a21b0b62ce76ad642296110364041.1772801284.git.michal.simek@amd.com --- include/configs/amd_versal2.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/amd_versal2.h b/include/configs/amd_versal2.h index 404af2cd4c6..38d0bfc315b 100644 --- a/include/configs/amd_versal2.h +++ b/include/configs/amd_versal2.h @@ -108,7 +108,8 @@ #define BOOT_TARGET_DEVICES_UFS(func) func(UFS, ufs, 0) #define BOOTENV_DEV_UFS(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" #devtypel " init " #instance "; scsi scan;\0" + "bootcmd_" #devtypel "=devnum=" #instance "; " \ + #devtypel " init $devnum; run scsi_boot\0" #define BOOTENV_DEV_NAME_UFS(devtypeu, devtypel, instance) \ "ufs " -- cgit v1.3.1 From e853610b560c072dd7207f2ccff01772aff1b748 Mon Sep 17 00:00:00 2001 From: Anshul Dalal Date: Fri, 6 Mar 2026 17:32:37 +0530 Subject: include: env: ti: move board specific scripts out of ti_common bootcmd_ti_mmc had cpsw0_qsgmii_phyinit related scripts even though this was only relevant for the j721e/j7200 SoCs. This patch instead factors out those scripts into a generic 'board_init' which is called as part of bootcmd_ti_mmc. This allows boards to more easily add custom behaviour to the ti_mmc bootflow instead of having to modify the ti_common.env file. Signed-off-by: Anshul Dalal --- board/ti/j7200/j7200.env | 8 ++++++++ board/ti/j721e/j721e.env | 8 ++++++++ include/env/ti/ti_common.env | 8 +++----- 3 files changed, 19 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/board/ti/j7200/j7200.env b/board/ti/j7200/j7200.env index e22a954d8db..7bb63825c52 100644 --- a/board/ti/j7200/j7200.env +++ b/board/ti/j7200/j7200.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J7200_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7200-mcu-r5f0_1-fw 2 /lib/firmware/j7200-main-r5f0_0-fw 3 /lib/firmware/j7200-main-r5f0_1-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env index 34f5f63d60a..9ecf7bfabde 100644 --- a/board/ti/j721e/j721e.env +++ b/board/ti/j721e/j721e.env @@ -37,3 +37,11 @@ main_cpsw0_qsgmii_phyinit= #if CONFIG_TARGET_J721E_A72_EVM rproc_fw_binaries= 1 /lib/firmware/j7-mcu-r5f0_1-fw 2 /lib/firmware/j7-main-r5f0_0-fw 3 /lib/firmware/j7-main-r5f0_1-fw 4 /lib/firmware/j7-main-r5f1_0-fw 5 /lib/firmware/j7-main-r5f1_1-fw 6 /lib/firmware/j7-c66_0-fw 7 /lib/firmware/j7-c66_1-fw 8 /lib/firmware/j7-c71_0-fw #endif + +#if CONFIG_CMD_REMOTEPROC +board_init= + if env exists do_main_cpsw0_qsgmii_phyinit; + then run main_cpsw0_qsgmii_phyinit; + fi; + run boot_rprocs; +#endif diff --git a/include/env/ti/ti_common.env b/include/env/ti/ti_common.env index a0ed83f52ac..62b93eb25c4 100644 --- a/include/env/ti/ti_common.env +++ b/include/env/ti/ti_common.env @@ -24,12 +24,10 @@ get_fit_config=setexpr name_fit_config gsub / _ conf-${fdtfile} run_fit=run get_fit_config; bootm ${addr_fit}#${name_fit_config}${overlaystring} bootcmd_ti_mmc= run init_${boot}; -#if CONFIG_CMD_REMOTEPROC - if env exists do_main_cpsw0_qsgmii_phyinit; - then run main_cpsw0_qsgmii_phyinit; + if test -n ${board_init}; then + echo Running board_init ...; + run board_init; fi; - run boot_rprocs; -#endif if test ${boot_fit} -eq 1; then run get_fit_${boot}; run get_fit_overlaystring; run run_fit; else; -- cgit v1.3.1 From 5e23f7f9f3b3c8fe78ed3aadeed9b187ba8930da Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Fri, 13 Mar 2026 11:42:25 +0100 Subject: fs/squashfs: squashfs.h: include file should be self dependent MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise, we get a lot of errors when including this file. Signed-off-by: Richard Genoud Reviewed-by: Tom Rini Reviewed-by: Miquel Raynal Reviewed-by: João Marcos Costa --- include/squashfs.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/squashfs.h b/include/squashfs.h index 7489eefa1f2..83ed8a49442 100644 --- a/include/squashfs.h +++ b/include/squashfs.h @@ -10,7 +10,10 @@ #ifndef _SQFS_H_ #define _SQFS_H_ -struct disk_partition; +#include +#include +#include +#include int sqfs_opendir(const char *filename, struct fs_dir_stream **dirsp); int sqfs_readdir(struct fs_dir_stream *dirs, struct fs_dirent **dentp); -- cgit v1.3.1 From 6494e823b46ced400764b6203d7480c9e3badc20 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Fri, 13 Mar 2026 11:42:26 +0100 Subject: spl: add squashfs support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implement spl_load_image_sqfs() in spl code. This will be used in MMC to read a file from a squashfs partition. Also, loosen squashfs read checks on file size by not failing when a bigger size than the actual file size is requested. (Just read the file) This is needed for FIT loading, because the length is ALIGNed. Signed-off-by: Richard Genoud Reviewed-by: Miquel Raynal Reviewed-by: João Marcos Costa --- common/spl/Makefile | 1 + common/spl/spl_squashfs.c | 78 +++++++++++++++++++++++++++++++++++++++++++++++ fs/squashfs/sqfs.c | 12 +++----- include/part.h | 1 + include/spl.h | 6 ++++ 5 files changed, 91 insertions(+), 7 deletions(-) create mode 100644 common/spl/spl_squashfs.c (limited to 'include') diff --git a/common/spl/Makefile b/common/spl/Makefile index 4c9482bd309..53cc45fc5b9 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)OPENSBI) += spl_opensbi.o obj-$(CONFIG_$(PHASE_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(PHASE_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(PHASE_)FS_EXT4) += spl_ext.o +obj-$(CONFIG_$(PHASE_)FS_SQUASHFS) += spl_squashfs.o obj-$(CONFIG_$(PHASE_)LOAD_IMX_CONTAINER) += spl_imx_container.o obj-$(CONFIG_$(PHASE_)SATA) += spl_sata.o obj-$(CONFIG_$(PHASE_)NVME) += spl_nvme.o diff --git a/common/spl/spl_squashfs.c b/common/spl/spl_squashfs.c new file mode 100644 index 00000000000..d3b1c70bfc4 --- /dev/null +++ b/common/spl/spl_squashfs.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Paratronic + * Copyright (C) 2026 Bootlin + * + * Author: Richard Genoud + * + */ + +#include +#include +#include +#include +#include +#include +#include + +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + struct legacy_img_hdr *header; + char *filename = load->priv; + loff_t actread; + int ret; + + ret = sqfs_read(filename, buf, file_offset, size, &actread); + if (ret) + return ret; + + if (CONFIG_IS_ENABLED(OS_BOOT)) { + header = (struct legacy_img_hdr *)buf; + if (image_get_magic(header) != FDT_MAGIC) + return size; + } + + return actread; +} + +int spl_load_image_sqfs(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + struct blk_desc *block_dev, int partition, + const char *filename) +{ + int err; + loff_t size = 0; + struct spl_load_info load; + struct disk_partition part_info = {}; + + err = part_get_info(block_dev, partition, &part_info); + if (err) { + printf("spl: no partition table found\n"); + goto end; + } + + err = sqfs_probe(block_dev, &part_info); + if (err) { + printf("spl: sqfs probe err part_name:%s type=%s err=%d\n", + part_info.name, part_info.type, err); + goto end; + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT_FULL)) { + err = sqfs_size(filename, &size); + if (err) + goto end; + } + + spl_load_init(&load, spl_fit_read, (void *)filename, 1); + + err = spl_load(spl_image, bootdev, &load, size, 0); + +end: + if (err < 0) + printf("%s: error reading image %s, err - %d\n", + __func__, filename, err); + + return err; +} diff --git a/fs/squashfs/sqfs.c b/fs/squashfs/sqfs.c index 9cb8b4afcdd..543db8c7e9e 100644 --- a/fs/squashfs/sqfs.c +++ b/fs/squashfs/sqfs.c @@ -1490,13 +1490,11 @@ static int sqfs_read_nest(const char *filename, void *buf, loff_t offset, goto out; } - /* If the user specifies a length, check its sanity */ - if (len) { - if (len > finfo.size) { - ret = -EINVAL; - goto out; - } - + /* + * For FIT loading, the len is ALIGN, so it may exceed the actual size. + * Let's just read the max. + */ + if (len && len < finfo.size) { finfo.size = len; } else { len = finfo.size; diff --git a/include/part.h b/include/part.h index daebbbc2e68..9679521825f 100644 --- a/include/part.h +++ b/include/part.h @@ -461,6 +461,7 @@ ulong disk_blk_erase(struct udevice *dev, lbaint_t start, lbaint_t blkcnt); #ifdef CONFIG_XPL_BUILD # define part_print_ptr(x) NULL # if defined(CONFIG_SPL_FS_EXT4) || defined(CONFIG_SPL_FS_FAT) || \ + defined(CONFIG_SPL_FS_SQUASHFS) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION) || \ defined(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE) # define part_get_info_ptr(x) x diff --git a/include/spl.h b/include/spl.h index 06dc28362d3..5078d7525ab 100644 --- a/include/spl.h +++ b/include/spl.h @@ -882,6 +882,12 @@ int spl_blk_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, enum uclass_id uclass_id, int devnum, int partnum); +/* SPL SQUASHFS image functions */ +int spl_load_image_sqfs(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + struct blk_desc *block_dev, int partition, + const char *filename); + /** * spl_early_init() - Set up device tree and driver model in SPL if enabled * -- cgit v1.3.1 From 29cb951e8ca6a9feecd920da31af9f18918057fe Mon Sep 17 00:00:00 2001 From: Daniel Palmer Date: Wed, 11 Mar 2026 07:06:18 +0900 Subject: fs: fat: Refactor dirty flag handling Refactor the dirty flag handling a little bit so an inline function is called instead of directly stuffing a value into the variable. This allows variable that holds the flag to be completely removed if its not used i.e. CONFIG_FAT_WIRTE=n Signed-off-by: Daniel Palmer --- fs/fat/fat.c | 2 +- fs/fat/fat_write.c | 9 ++++----- include/fat.h | 26 ++++++++++++++++++++++++++ 3 files changed, 31 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 85b511f75af..31c136e3b9e 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -832,7 +832,7 @@ static int get_fs_info(fsdata *mydata) } mydata->fatbufnum = -1; - mydata->fat_dirty = 0; + fat_mark_clean(mydata); mydata->fatbuf = malloc_cache_aligned(FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 02e006f7c9e..c98b530f747 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -225,9 +225,9 @@ static int flush_dirty_fat_buffer(fsdata *mydata) __u32 startblock = mydata->fatbufnum * FATBUFBLOCKS; debug("debug: evicting %d, dirty: %d\n", mydata->fatbufnum, - (int)mydata->fat_dirty); + (int)fat_is_dirty(mydata)); - if ((!mydata->fat_dirty) || (mydata->fatbufnum == -1)) + if (!fat_is_dirty(mydata) || (mydata->fatbufnum == -1)) return 0; /* Cap length if fatlength is not a multiple of FATBUFBLOCKS */ @@ -250,7 +250,7 @@ static int flush_dirty_fat_buffer(fsdata *mydata) return -1; } } - mydata->fat_dirty = 0; + fat_mark_clean(mydata); return 0; } @@ -486,8 +486,7 @@ static int set_fatent_value(fsdata *mydata, __u32 entry, __u32 entry_value) mydata->fatbufnum = bufnum; } - /* Mark as dirty */ - mydata->fat_dirty = 1; + fat_mark_dirty(mydata); /* Set the actual entry */ switch (mydata->fatsize) { diff --git a/include/fat.h b/include/fat.h index bdf430f7067..40da0370a44 100644 --- a/include/fat.h +++ b/include/fat.h @@ -165,7 +165,9 @@ typedef struct { int fatsize; /* Size of FAT in bits */ __u32 fatlength; /* Length of FAT in sectors */ __u16 fat_sect; /* Starting sector of the FAT */ +#ifdef CONFIG_FAT_WRITE __u8 fat_dirty; /* Set if fatbuf has been modified */ +#endif __u32 rootdir_sect; /* Start sector of root directory */ __u16 sect_size; /* Size of sectors in bytes */ __u16 clust_size; /* Size of clusters in sectors */ @@ -190,6 +192,30 @@ static inline u32 sect_to_clust(fsdata *fsdata, int sect) return (sect - fsdata->data_begin) / fsdata->clust_size; } +static inline void fat_mark_clean(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 0; +#endif +} + +static inline void fat_mark_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + fsdata->fat_dirty = 1; +#endif +} + +static inline bool fat_is_dirty(fsdata *fsdata) +{ +#ifdef CONFIG_FAT_WRITE + if (fsdata->fat_dirty) + return true; +#endif + + return false; +} + int file_fat_detectfs(void); int fat_exists(const char *filename); int fat_size(const char *filename, loff_t *size); -- cgit v1.3.1 From 77801f4b644b61e8a626a8a07b8249b8d29b118b Mon Sep 17 00:00:00 2001 From: Primoz Fiser Date: Tue, 17 Mar 2026 13:31:26 +0100 Subject: board: phytec: phycore-imx91-93: Add phyCORE-i.MX91 support As the PHYTEC phyCORE-i.MX91 [1] is just another variant of the existing PHYTEC phyCORE-i.MX93 SoM but with i.MX91 SoC populated instead, add it to the existing board-code "phycore_imx93", and rename that board to "phycore_imx91_93" to reflect the dual SoCs support. While at it, also rename and change common files accordingly. This way i.MX91 and i.MX93 SoC variants of the phyCORE SoM share most of the code and documentation without duplication, while maintaining own device-tree and defconfigs for each CPU variant. Supported features: - 1GB LPDDR4 RAM - Debug UART - EEPROM - eMMC - Ethernet - SD-card - USB Product page SoM: [1] https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ Signed-off-by: Primoz Fiser --- .../dts/imx91-93-phyboard-segin-common-u-boot.dtsi | 228 ++ arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi | 18 + arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi | 221 +- arch/arm/mach-imx/imx9/Kconfig | 10 +- arch/arm/mach-imx/imx9/soc.c | 3 +- board/phytec/common/Kconfig | 6 +- board/phytec/common/Makefile | 2 +- board/phytec/common/imx91_93_som_detection.c | 114 + board/phytec/common/imx91_93_som_detection.h | 51 + board/phytec/common/imx93_som_detection.c | 111 - board/phytec/common/imx93_som_detection.h | 51 - board/phytec/phycore_imx91_93/Kconfig | 47 + board/phytec/phycore_imx91_93/MAINTAINERS | 16 + board/phytec/phycore_imx91_93/Makefile | 19 + .../phytec/phycore_imx91_93/lpddr4_timing_imx91.c | 1998 ++++++++++++++++++ .../phytec/phycore_imx91_93/lpddr4_timing_imx93.c | 2217 ++++++++++++++++++++ board/phytec/phycore_imx91_93/phycore-imx91-93.c | 103 + board/phytec/phycore_imx91_93/phycore_imx91_93.env | 16 + board/phytec/phycore_imx91_93/spl.c | 202 ++ board/phytec/phycore_imx93/Kconfig | 41 - board/phytec/phycore_imx93/MAINTAINERS | 12 - board/phytec/phycore_imx93/Makefile | 14 - board/phytec/phycore_imx93/lpddr4_timing.c | 2217 -------------------- board/phytec/phycore_imx93/phycore-imx93.c | 103 - board/phytec/phycore_imx93/phycore_imx93.env | 14 - board/phytec/phycore_imx93/spl.c | 194 -- configs/imx91-phycore_defconfig | 167 ++ configs/imx93-phycore_defconfig | 2 +- doc/board/phytec/imx91-93-phycore.rst | 83 + doc/board/phytec/imx93-phycore.rst | 61 - doc/board/phytec/index.rst | 2 +- include/configs/phycore_imx91_93.h | 28 + include/configs/phycore_imx93.h | 28 - 33 files changed, 5325 insertions(+), 3074 deletions(-) create mode 100644 arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi create mode 100644 arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi create mode 100644 board/phytec/common/imx91_93_som_detection.c create mode 100644 board/phytec/common/imx91_93_som_detection.h delete mode 100644 board/phytec/common/imx93_som_detection.c delete mode 100644 board/phytec/common/imx93_som_detection.h create mode 100644 board/phytec/phycore_imx91_93/Kconfig create mode 100644 board/phytec/phycore_imx91_93/MAINTAINERS create mode 100644 board/phytec/phycore_imx91_93/Makefile create mode 100644 board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c create mode 100644 board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c create mode 100644 board/phytec/phycore_imx91_93/phycore-imx91-93.c create mode 100644 board/phytec/phycore_imx91_93/phycore_imx91_93.env create mode 100644 board/phytec/phycore_imx91_93/spl.c delete mode 100644 board/phytec/phycore_imx93/Kconfig delete mode 100644 board/phytec/phycore_imx93/MAINTAINERS delete mode 100644 board/phytec/phycore_imx93/Makefile delete mode 100644 board/phytec/phycore_imx93/lpddr4_timing.c delete mode 100644 board/phytec/phycore_imx93/phycore-imx93.c delete mode 100644 board/phytec/phycore_imx93/phycore_imx93.env delete mode 100644 board/phytec/phycore_imx93/spl.c create mode 100644 configs/imx91-phycore_defconfig create mode 100644 doc/board/phytec/imx91-93-phycore.rst delete mode 100644 doc/board/phytec/imx93-phycore.rst create mode 100644 include/configs/phycore_imx91_93.h delete mode 100644 include/configs/phycore_imx93.h (limited to 'include') diff --git a/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi new file mode 100644 index 00000000000..64ed7af9946 --- /dev/null +++ b/arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + * + */ + +/ { + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog3>; + bootph-pre-ram; + bootph-some-ram; + }; + + aliases { + ethernet0 = &fec; + ethernet1 = &eqos; + }; + + bootstd { + bootph-verify; + compatible = "u-boot,boot-std"; + + filename-prefixes = "/", "/boot/"; + bootdev-order = "mmc0", "mmc1", "ethernet"; + + rauc { + compatible = "u-boot,distro-rauc"; + }; + + script { + compatible = "u-boot,script"; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&{/soc@0} { + bootph-all; + bootph-pre-ram; +}; + +&aips1 { + bootph-pre-ram; + bootph-all; +}; + +&aips2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&aips3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&iomuxc { + bootph-pre-ram; + bootph-some-ram; +}; + +®_usdhc2_vmmc { + u-boot,off-on-delay-us = <20000>; + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_lpi2c3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_pmic { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_reg_usdhc2_vmmc { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_cd { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_default { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_100mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&pinctrl_usdhc2_200mhz { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio3 { + bootph-pre-ram; + bootph-some-ram; +}; + +&gpio4 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpuart1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&usdhc2 { + bootph-pre-ram; + bootph-some-ram; + fsl,signal-voltage-switch-extra-delay-ms = <8>; +}; + +&lpi2c1 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c2 { + bootph-pre-ram; + bootph-some-ram; +}; + +&lpi2c3 { + bootph-pre-ram; + bootph-some-ram; + + pmic@25 { + bootph-pre-ram; + bootph-some-ram; + + regulators { + bootph-pre-ram; + bootph-some-ram; + }; + }; + + eeprom@50 { + bootph-pre-ram; + bootph-some-ram; + }; +}; + +&s4muap { + bootph-pre-ram; + bootph-some-ram; + status = "okay"; +}; + +&clk { + bootph-all; + bootph-pre-ram; + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-rates; + /delete-property/ assigned-clock-parents; +}; + +&osc_32k { + bootph-all; + bootph-pre-ram; +}; + +&osc_24m { + bootph-all; + bootph-pre-ram; +}; + +&clk_ext1 { + bootph-all; + bootph-pre-ram; +}; + +&wdog3 { + bootph-all; + bootph-pre-ram; +}; diff --git a/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi new file mode 100644 index 00000000000..5d788854de5 --- /dev/null +++ b/arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + * + */ + +#include "imx91-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" + +/ { + /* + * The phyCORE-i.MX91 u-boot uses the imx91-phyboard-segin.dts as + * reference, but does only make use of its SoM (phyCORE) contained + * periphery. + */ + model = "PHYTEC phyCORE-i.MX91"; +}; diff --git a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi index 646b617949d..b80ce20e942 100644 --- a/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +++ b/arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi @@ -9,6 +9,7 @@ */ #include "imx93-u-boot.dtsi" +#include "imx91-93-phyboard-segin-common-u-boot.dtsi" / { /* @@ -17,224 +18,4 @@ * periphery. */ model = "PHYTEC phyCORE-i.MX93"; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog3>; - bootph-pre-ram; - bootph-some-ram; - }; - - aliases { - ethernet0 = &fec; - ethernet1 = &eqos; - }; - - bootstd { - bootph-verify; - compatible = "u-boot,boot-std"; - - filename-prefixes = "/", "/boot/"; - bootdev-order = "mmc0", "mmc1", "ethernet"; - - rauc { - compatible = "u-boot,distro-rauc"; - }; - - script { - compatible = "u-boot,script"; - }; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&{/soc@0} { - bootph-all; - bootph-pre-ram; -}; - -&aips1 { - bootph-pre-ram; - bootph-all; -}; - -&aips2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&aips3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&iomuxc { - bootph-pre-ram; - bootph-some-ram; -}; - -®_usdhc2_vmmc { - u-boot,off-on-delay-us = <20000>; - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_lpi2c3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_pmic { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_reg_usdhc2_vmmc { - bootph-pre-ram; -}; - -&pinctrl_uart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc1_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_cd { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_default { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_100mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&pinctrl_usdhc2_200mhz { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio3 { - bootph-pre-ram; - bootph-some-ram; -}; - -&gpio4 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpuart1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&usdhc2 { - bootph-pre-ram; - bootph-some-ram; - fsl,signal-voltage-switch-extra-delay-ms = <8>; -}; - -&lpi2c1 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c2 { - bootph-pre-ram; - bootph-some-ram; -}; - -&lpi2c3 { - bootph-pre-ram; - bootph-some-ram; - - pmic@25 { - bootph-pre-ram; - bootph-some-ram; - - regulators { - bootph-pre-ram; - bootph-some-ram; - }; - }; - - eeprom@50 { - bootph-pre-ram; - bootph-some-ram; - }; -}; - -&s4muap { - bootph-pre-ram; - bootph-some-ram; - status = "okay"; -}; - -&clk { - bootph-all; - bootph-pre-ram; - /delete-property/ assigned-clocks; - /delete-property/ assigned-clock-rates; - /delete-property/ assigned-clock-parents; -}; - -&osc_32k { - bootph-all; - bootph-pre-ram; -}; - -&osc_24m { - bootph-all; - bootph-pre-ram; -}; - -&clk_ext1 { - bootph-all; - bootph-pre-ram; -}; - -&wdog3 { - bootph-all; - bootph-pre-ram; }; diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 6e0958c0842..fef1980ccef 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -129,6 +129,14 @@ config TARGET_KONTRON_MX93 Kontron Electronics BL i.MX93 using SoM module conformant to OSM standard 1.1 size S. +config TARGET_PHYCORE_IMX91 + bool "phycore_imx91" + select IMX91 + select IMX9_LPDDR4X + imply OF_UPSTREAM + select OF_BOARD_FIXUP + select OF_BOARD_SETUP + config TARGET_PHYCORE_IMX93 bool "phycore_imx93" select IMX93 @@ -181,7 +189,7 @@ source "board/nxp/imx93_evk/Kconfig" source "board/nxp/imx93_frdm/Kconfig" source "board/nxp/imx93_qsb/Kconfig" source "board/kontron/osm-s-mx93/Kconfig" -source "board/phytec/phycore_imx93/Kconfig" +source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 583c3a5a464..44b3e0f5310 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -664,7 +664,8 @@ int low_drive_freq_update(void *blob) return 0; } -#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) +#if defined(CONFIG_OF_BOARD_FIXUP) && !defined(CONFIG_TARGET_PHYCORE_IMX93) && \ + !defined(CONFIG_TARGET_PHYCORE_IMX91) #ifndef CONFIG_XPL_BUILD int board_fix_fdt(void *fdt) { diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index a72f66ee3f5..6afd03086f7 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -19,13 +19,13 @@ config PHYTEC_IMX8M_SOM_DETECTION Support of I2C EEPROM based SoM detection. Supported for PHYTEC i.MX8MM/i.MX8MP boards -config PHYTEC_IMX93_SOM_DETECTION - bool "Support SoM detection for i.MX93 PHYTEC platforms" +config PHYTEC_IMX91_93_SOM_DETECTION + bool "Support SoM detection for i.MX91/93 PHYTEC platforms" depends on ARCH_IMX9 && PHYTEC_SOM_DETECTION default y help Support of I2C EEPROM based SoM detection. Supported - for PHYTEC i.MX93 based boards + for PHYTEC i.MX91/93 based boards config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" diff --git a/board/phytec/common/Makefile b/board/phytec/common/Makefile index 948f9dab626..e09dea01d49 100644 --- a/board/phytec/common/Makefile +++ b/board/phytec/common/Makefile @@ -10,4 +10,4 @@ endif obj-y += phytec_som_detection.o phytec_som_detection_blocks.o obj-$(CONFIG_ARCH_K3) += am6_som_detection.o k3/ obj-$(CONFIG_ARCH_IMX8M) += imx8m_som_detection.o -obj-$(CONFIG_ARCH_IMX9) += imx93_som_detection.o +obj-$(CONFIG_ARCH_IMX9) += imx91_93_som_detection.o diff --git a/board/phytec/common/imx91_93_som_detection.c b/board/phytec/common/imx91_93_som_detection.c new file mode 100644 index 00000000000..bcc5500ae9f --- /dev/null +++ b/board/phytec/common/imx91_93_som_detection.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#include +#include +#include +#include +#include + +#include "imx91_93_som_detection.h" + +extern struct phytec_eeprom_data eeprom_data; + +#if IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) + +/* Check if the SoM is actually one of the following products: + * - i.MX91 + * - i.MX93 + * + * Returns 0 in case it's a known SoM. Otherwise, returns 1. + */ +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) +{ + u8 som; + + if (!data) + data = &eeprom_data; + + /* Early API revisions are not supported */ + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return 1; + + som = data->payload.data.data_api2.som_no; + debug("%s: som id: %u\n", __func__, som); + + if (som == PHYTEC_IMX91_93_SOM && (is_imx91() || is_imx93())) + return 0; + + pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); + return 1; +} + +/* + * Filter PHYTEC i.MX91/93 SoM options by option index + * + * Returns: + * - option value + * - PHYTEC_EEPROM_INVAL when the data is invalid + * + */ +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) +{ + char *opt; + u8 opt_id; + + if (!data) + data = &eeprom_data; + + if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) + return PHYTEC_EEPROM_INVAL; + + opt = phytec_get_opt(data); + if (opt) + opt_id = PHYTEC_GET_OPTION(opt[idx]); + else + opt_id = PHYTEC_EEPROM_INVAL; + + debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id); + return opt_id; +} + +/* + * Filter PHYTEC i.MX91/93 SoM voltage + * + * Returns: + * - PHYTEC_IMX91_93_VOLTAGE_1V8 or PHYTEC_IMX91_93_VOLTAGE_3V3 + * - PHYTEC_EEPROM_INVAL when the data is invalid + * + */ +enum phytec_imx91_93_voltage __maybe_unused +phytec_imx91_93_get_voltage(struct phytec_eeprom_data *data) +{ + u8 option = phytec_imx91_93_get_opt(data, PHYTEC_IMX91_93_OPT_FEAT); + + if (option == PHYTEC_EEPROM_INVAL) + return PHYTEC_IMX91_93_VOLTAGE_INVALID; + return (option & 0x01) ? PHYTEC_IMX91_93_VOLTAGE_1V8 : + PHYTEC_IMX91_93_VOLTAGE_3V3; +} + +#else + +inline u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data) +{ + return 1; +} + +inline u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx) +{ + return PHYTEC_EEPROM_INVAL; +} + +inline enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage + (struct phytec_eeprom_data *data) +{ + return PHYTEC_EEPROM_INVAL; +} + +#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX91_93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx91_93_som_detection.h b/board/phytec/common/imx91_93_som_detection.h new file mode 100644 index 00000000000..05ea4cf0868 --- /dev/null +++ b/board/phytec/common/imx91_93_som_detection.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2026 PHYTEC Messtechnik GmbH + * Author: Primoz Fiser + */ + +#ifndef _PHYTEC_IMX91_93_SOM_DETECTION_H +#define _PHYTEC_IMX91_93_SOM_DETECTION_H + +#include "phytec_som_detection.h" + +#define PHYTEC_IMX91_93_SOM 77 + +enum phytec_imx91_93_option_index { + PHYTEC_IMX91_93_OPT_DDR = 0, + PHYTEC_IMX91_93_OPT_EMMC = 1, + PHYTEC_IMX91_93_OPT_CPU = 2, + PHYTEC_IMX91_93_OPT_FREQ = 3, + PHYTEC_IMX91_93_OPT_NPU = 4, + PHYTEC_IMX91_93_OPT_DISP = 5, + PHYTEC_IMX91_93_OPT_ETH = 6, + PHYTEC_IMX91_93_OPT_FEAT = 7, + PHYTEC_IMX91_93_OPT_TEMP = 8, + PHYTEC_IMX91_93_OPT_BOOT = 9, + PHYTEC_IMX91_93_OPT_LED = 10, + PHYTEC_IMX91_93_OPT_EEPROM = 11, +}; + +enum phytec_imx91_93_voltage { + PHYTEC_IMX91_93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_VOLTAGE_3V3 = 0, + PHYTEC_IMX91_93_VOLTAGE_1V8 = 1, +}; + +enum phytec_imx91_93_ddr_eeprom_code { + PHYTEC_IMX91_93_DDR_INVALID = PHYTEC_EEPROM_INVAL, + PHYTEC_IMX91_93_LPDDR4X_512MB = 0, + PHYTEC_IMX91_93_LPDDR4X_1GB = 1, + PHYTEC_IMX91_93_LPDDR4X_2GB = 2, + PHYTEC_IMX91_93_LPDDR4_512MB = 3, + PHYTEC_IMX91_93_LPDDR4_1GB = 4, + PHYTEC_IMX91_93_LPDDR4_2GB = 5, +}; + +u8 __maybe_unused phytec_imx91_93_detect(struct phytec_eeprom_data *data); +u8 __maybe_unused phytec_imx91_93_get_opt(struct phytec_eeprom_data *data, + enum phytec_imx91_93_option_index idx); +enum phytec_imx91_93_voltage __maybe_unused phytec_imx91_93_get_voltage + (struct phytec_eeprom_data *data); + +#endif /* _PHYTEC_IMX91_93_SOM_DETECTION_H */ diff --git a/board/phytec/common/imx93_som_detection.c b/board/phytec/common/imx93_som_detection.c deleted file mode 100644 index eb9574d43b5..00000000000 --- a/board/phytec/common/imx93_som_detection.c +++ /dev/null @@ -1,111 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Primoz Fiser - */ - -#include -#include -#include -#include -#include - -#include "imx93_som_detection.h" - -extern struct phytec_eeprom_data eeprom_data; - -#if IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) - -/* Check if the SoM is actually one of the following products: - * - i.MX93 - * - * Returns 0 in case it's a known SoM. Otherwise, returns 1. - */ -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) -{ - u8 som; - - if (!data) - data = &eeprom_data; - - /* Early API revisions are not supported */ - if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) - return 1; - - som = data->payload.data.data_api2.som_no; - debug("%s: som id: %u\n", __func__, som); - - if (som == PHYTEC_IMX93_SOM && is_imx93()) - return 0; - - pr_err("%s: SoM ID does not match. Wrong EEPROM data?\n", __func__); - return 1; -} - -/* - * Filter PHYTEC i.MX93 SoM options by option index - * - * Returns: - * - option value - * - PHYTEC_EEPROM_INVAL when the data is invalid - * - */ -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) -{ - char *opt; - u8 opt_id; - - if (!data) - data = &eeprom_data; - - if (!data->valid || data->payload.api_rev < PHYTEC_API_REV2) - return PHYTEC_EEPROM_INVAL; - - opt = phytec_get_opt(data); - if (opt) - opt_id = PHYTEC_GET_OPTION(opt[idx]); - else - opt_id = PHYTEC_EEPROM_INVAL; - - debug("%s: opt[%d] id: %u\n", __func__, idx, opt_id); - return opt_id; -} - -/* - * Filter PHYTEC i.MX93 SoM voltage - * - * Returns: - * - PHYTEC_IMX93_VOLTAGE_1V8 or PHYTEC_IMX93_VOLTAGE_3V3 - * - PHYTEC_EEPROM_INVAL when the data is invalid - * - */ -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage(struct phytec_eeprom_data *data) -{ - u8 option = phytec_imx93_get_opt(data, PHYTEC_IMX93_OPT_FEAT); - - if (option == PHYTEC_EEPROM_INVAL) - return PHYTEC_IMX93_VOLTAGE_INVALID; - return (option & 0x01) ? PHYTEC_IMX93_VOLTAGE_1V8 : PHYTEC_IMX93_VOLTAGE_3V3; -} - -#else - -inline u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data) -{ - return 1; -} - -inline u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx) -{ - return PHYTEC_EEPROM_INVAL; -} - -inline enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage - (struct phytec_eeprom_data *data) -{ - return PHYTEC_EEPROM_INVAL; -} - -#endif /* IS_ENABLED(CONFIG_PHYTEC_IMX93_SOM_DETECTION) */ diff --git a/board/phytec/common/imx93_som_detection.h b/board/phytec/common/imx93_som_detection.h deleted file mode 100644 index a0803b47cbe..00000000000 --- a/board/phytec/common/imx93_som_detection.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Author: Primoz Fiser - */ - -#ifndef _PHYTEC_IMX93_SOM_DETECTION_H -#define _PHYTEC_IMX93_SOM_DETECTION_H - -#include "phytec_som_detection.h" - -#define PHYTEC_IMX93_SOM 77 - -enum phytec_imx93_option_index { - PHYTEC_IMX93_OPT_DDR = 0, - PHYTEC_IMX93_OPT_EMMC = 1, - PHYTEC_IMX93_OPT_CPU = 2, - PHYTEC_IMX93_OPT_FREQ = 3, - PHYTEC_IMX93_OPT_NPU = 4, - PHYTEC_IMX93_OPT_DISP = 5, - PHYTEC_IMX93_OPT_ETH = 6, - PHYTEC_IMX93_OPT_FEAT = 7, - PHYTEC_IMX93_OPT_TEMP = 8, - PHYTEC_IMX93_OPT_BOOT = 9, - PHYTEC_IMX93_OPT_LED = 10, - PHYTEC_IMX93_OPT_EEPROM = 11, -}; - -enum phytec_imx93_voltage { - PHYTEC_IMX93_VOLTAGE_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_VOLTAGE_3V3 = 0, - PHYTEC_IMX93_VOLTAGE_1V8 = 1, -}; - -enum phytec_imx93_ddr_eeprom_code { - PHYTEC_IMX93_DDR_INVALID = PHYTEC_EEPROM_INVAL, - PHYTEC_IMX93_LPDDR4X_512MB = 0, - PHYTEC_IMX93_LPDDR4X_1GB = 1, - PHYTEC_IMX93_LPDDR4X_2GB = 2, - PHYTEC_IMX93_LPDDR4_512MB = 3, - PHYTEC_IMX93_LPDDR4_1GB = 4, - PHYTEC_IMX93_LPDDR4_2GB = 5, -}; - -u8 __maybe_unused phytec_imx93_detect(struct phytec_eeprom_data *data); -u8 __maybe_unused phytec_imx93_get_opt(struct phytec_eeprom_data *data, - enum phytec_imx93_option_index idx); -enum phytec_imx93_voltage __maybe_unused phytec_imx93_get_voltage - (struct phytec_eeprom_data *data); - -#endif /* _PHYTEC_IMX93_SOM_DETECTION_H */ diff --git a/board/phytec/phycore_imx91_93/Kconfig b/board/phytec/phycore_imx91_93/Kconfig new file mode 100644 index 00000000000..87fd915e5a8 --- /dev/null +++ b/board/phytec/phycore_imx91_93/Kconfig @@ -0,0 +1,47 @@ + +if TARGET_PHYCORE_IMX91 || TARGET_PHYCORE_IMX93 + +config SYS_BOARD + default "phycore_imx91_93" + +config SYS_VENDOR + default "phytec" + +config SYS_CONFIG_NAME + default "phycore_imx91_93" + +config PHYCORE_IMX91_93_RAM_TYPE_FIX + bool "Set phyCORE-i.MX91/93 RAM type and size fix instead of detecting" + default false + help + RAM type and size is being automatically detected with the help + of the PHYTEC EEPROM introspection data. + Set RAM type to a fix value instead. + +choice + prompt "phyCORE-i.MX91/93 RAM type" + depends on PHYCORE_IMX91_93_RAM_TYPE_FIX + default PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB + bool "LPDDR4 1GB RAM" + help + Set RAM type fixed to LPDDR4 and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB + bool "LPDDR4X 1GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB + for phyCORE-i.MX91/93. + +config PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB + bool "LPDDR4X 2GB RAM" + help + Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB + for phyCORE-i.MX91/93. + +endchoice + +source "board/phytec/common/Kconfig" +endif diff --git a/board/phytec/phycore_imx91_93/MAINTAINERS b/board/phytec/phycore_imx91_93/MAINTAINERS new file mode 100644 index 00000000000..573d1c36a5e --- /dev/null +++ b/board/phytec/phycore_imx91_93/MAINTAINERS @@ -0,0 +1,16 @@ +phyCORE-i.MX91/93 +M: Mathieu Othacehe +R: Christoph Stoidner +L: upstream@lists.phytec.de +W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ +S: Maintained +F: arch/arm/dts/imx91-93-phyboard-segin-common-u-boot.dtsi +F: arch/arm/dts/imx91-phyboard-segin-u-boot.dtsi +F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi +F: board/phytec/phycore_imx91_93/ +F: board/phytec/common/imx91_93_som_detection.c +F: board/phytec/common/imx91_93_som_detection.h +F: configs/imx91-phycore_defconfig +F: configs/imx93-phycore_defconfig +F: include/configs/phycore_imx91_93.h +F: doc/board/phytec/imx91-93-phycore.rst diff --git a/board/phytec/phycore_imx91_93/Makefile b/board/phytec/phycore_imx91_93/Makefile new file mode 100644 index 00000000000..976ecb306f7 --- /dev/null +++ b/board/phytec/phycore_imx91_93/Makefile @@ -0,0 +1,19 @@ +# +# Copyright 2022 NXP +# Copyright (C) 2023 PHYTEC Messtechnik GmbH +# Christoph Stoidner +# Copyright (C) 2024 Mathieu Othacehe +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += phycore-imx91-93.o + +ifdef CONFIG_XPL_BUILD +obj-y += spl.o +ifdef CONFIG_IMX91 +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx91.o +else +obj-$(CONFIG_IMX9_LPDDR4X) += lpddr4_timing_imx93.o +endif +endif diff --git a/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c new file mode 100644 index 00000000000..ddc8094f080 --- /dev/null +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx91.c @@ -0,0 +1,1998 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright 2024 NXP + * Copyright (C) 2025 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * + * Code generated with DDR Tool v3.3.0_1.8-d1cdb7d3. + * DDR PHY FW2022.01 + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x13542110}, + {0x4e300104, 0xF8990011}, + {0x4e300108, 0x636E88CC}, + {0x4e30010C, 0x00614070}, + {0x4e300124, 0x124E0000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x31D00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x0000001A}, + {0x4e300254, 0x00A000A0}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x1633160D}, + {0x4e300304, 0x00A0180C}, + {0x4e300308, 0x0C280927}, + }, + { + {0x01, 0xC4}, + {0x02, 0x24}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x010A1100}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0xBABA0068}, + {0x4e30010C, 0x00610158}, + {0x4e300124, 0x09270000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30400000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x0000000D}, + {0x4e300254, 0x004C004C}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xA4}, + {0x02, 0x52}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x23}, + {0x0b, 0x44}, + {0x0c, 0x49}, + {0x0e, 0x4A}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x1ff}, + {0x1015f, 0x1ff}, + {0x1105f, 0x1ff}, + {0x1115f, 0x1ff}, + {0x11005f, 0x1ff}, + {0x11015f, 0x1ff}, + {0x11105f, 0x1ff}, + {0x11115f, 0x1ff}, + {0x21005f, 0x1ff}, + {0x21015f, 0x1ff}, + {0x21105f, 0x1ff}, + {0x21115f, 0x1ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0xa}, + {0x1200c5, 0x2}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x1}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x61f}, + {0x10149, 0x61f}, + {0x11049, 0x61f}, + {0x11149, 0x61f}, + {0x110049, 0x61f}, + {0x110149, 0x61f}, + {0x111049, 0x61f}, + {0x111149, 0x61f}, + {0x210049, 0x61f}, + {0x210149, 0x61f}, + {0x211049, 0x61f}, + {0x211149, 0x61f}, + {0x43, 0x7f}, + {0x1043, 0x7f}, + {0x2043, 0x7f}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x11}, + {0x2009b, 0x2}, + {0x20008, 0x258}, + {0x120008, 0x12c}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x104}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x41}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + 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{0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x4b0}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x52a4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x52a4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xa400}, + {0x54033, 0x2352}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xa400}, + {0x54039, 0x2352}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a00}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a00}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2309}, + {0x54034, 0x4400}, + {0x54035, 0x49}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2309}, + {0x5403a, 0x4400}, + {0x5403b, 0x49}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0x960}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x24c4}, + {0x5401a, 0x23}, + {0x5401b, 0x4944}, + {0x5401c, 0x4a08}, + {0x5401e, 0x4}, + {0x5401f, 0x24c4}, + {0x54020, 0x23}, + {0x54021, 0x4944}, + {0x54022, 0x4a08}, + {0x54024, 0x4}, + {0x54032, 0xc400}, + {0x54033, 0x2324}, + {0x54034, 0x4400}, + {0x54035, 0x849}, + {0x54036, 0x4a}, + {0x54037, 0x400}, + {0x54038, 0xc400}, + {0x54039, 0x2324}, + {0x5403a, 0x4400}, + {0x5403b, 0x849}, + {0x5403c, 0x4a}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x2a3}, + {0x2000c, 0x96}, + {0x2000d, 0x5dc}, + {0x2000e, 0x2c}, + {0x12000b, 0x152}, + {0x12000c, 0x4b}, + {0x12000d, 0x2ee}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 2400mts 1D */ + .drate = 2400, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1200mts 1D */ + .drate = 1200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 2400mts 2D */ + .drate = 2400, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 2400, 1200, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c new file mode 100644 index 00000000000..f1261f6a92a --- /dev/null +++ b/board/phytec/phycore_imx91_93/lpddr4_timing_imx93.c @@ -0,0 +1,2217 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2024 NXP + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Christoph Stoidner + * + * Code generated with DDR Tool v3.1.0_7.4. + */ + +#include +#include + +/* Initialize DDRC registers */ +static struct dram_cfg_param ddr_ddrc_cfg[] = { + {0x4e300110, 0x44100001}, + {0x4e300000, 0x8000bf}, + {0x4e300008, 0x0}, + {0x4e300080, 0x80000412}, + {0x4e300084, 0x0}, + {0x4e300114, 0x1002}, + {0x4e300260, 0x80}, + {0x4e300f04, 0x80}, + {0x4e300800, 0x43b30002}, + {0x4e300804, 0x1f1f1f1f}, + {0x4e301000, 0x0}, + {0x4e301240, 0x0}, + {0x4e301244, 0x0}, + {0x4e301248, 0x0}, + {0x4e30124c, 0x0}, + {0x4e301250, 0x0}, + {0x4e301254, 0x0}, + {0x4e301258, 0x0}, + {0x4e30125c, 0x0}, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + {0x4e300100, 0x24A0321B}, + {0x4e300104, 0xF8EE001B}, + {0x4e300108, 0x2F2E3233}, + {0x4e30010C, 0x0005C18B}, + {0x4e300124, 0x1C790000}, + {0x4e300160, 0x00009102}, + {0x4e30016C, 0x35F00000}, + {0x4e300170, 0x8B0B0608}, + {0x4e300250, 0x00000028}, + {0x4e300254, 0x00FE00FE}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + {0x4e300300, 0x224F2213}, + {0x4e300304, 0x00FE2213}, + {0x4e300308, 0x0A380E3D}, + }, + { + {0x01, 0xE4}, + {0x02, 0x36}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x124F2100}, + {0x4e300104, 0xF877000E}, + {0x4e300108, 0x1816E4AA}, + {0x4e30010C, 0x005101E6}, + {0x4e300124, 0x0E3C0000}, + {0x4e300160, 0x00009101}, + {0x4e30016C, 0x30900000}, + {0x4e300170, 0x8A0A0508}, + {0x4e300250, 0x00000014}, + {0x4e300254, 0x007B007B}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0xB4}, + {0x02, 0x1B}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, + {0x16, 0x04}, + }, + 0, + }, + { + { + {0x4e300100, 0x00051000}, + {0x4e300104, 0xF855000A}, + {0x4e300108, 0x6E620A48}, + {0x4e30010C, 0x0031010D}, + {0x4e300124, 0x04C50000}, + {0x4e300160, 0x00009100}, + {0x4e30016C, 0x30000000}, + {0x4e300170, 0x89090408}, + {0x4e300250, 0x00000007}, + {0x4e300254, 0x00240024}, + {0x4e300258, 0x00000008}, + {0x4e30025C, 0x00000400}, + }, + { + {0x01, 0x94}, + {0x02, 0x9}, + {0x03, 0x22}, + {0x0b, 0x44}, + {0x0c, 0x1E}, + {0x0e, 0x12}, + {0x16, 0x04}, + }, + 1, + }, + +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { + {0x100a0, 0x0}, + {0x100a1, 0x1}, + {0x100a2, 0x2}, + {0x100a3, 0x3}, + {0x100a4, 0x4}, + {0x100a5, 0x5}, + {0x100a6, 0x6}, + {0x100a7, 0x7}, + {0x110a0, 0x0}, + {0x110a1, 0x1}, + {0x110a2, 0x2}, + {0x110a3, 0x3}, + {0x110a4, 0x4}, + {0x110a5, 0x5}, + {0x110a6, 0x6}, + {0x110a7, 0x7}, + {0x1005f, 0x5ff}, + {0x1015f, 0x5ff}, + {0x1105f, 0x5ff}, + {0x1115f, 0x5ff}, + {0x11005f, 0x5ff}, + {0x11015f, 0x5ff}, + {0x11105f, 0x5ff}, + {0x11115f, 0x5ff}, + {0x21005f, 0x5ff}, + {0x21015f, 0x5ff}, + {0x21105f, 0x5ff}, + {0x21115f, 0x5ff}, + {0x55, 0x1ff}, + {0x1055, 0x1ff}, + {0x2055, 0x1ff}, + {0x200c5, 0x19}, + {0x1200c5, 0xb}, + {0x2200c5, 0x7}, + {0x2002e, 0x2}, + {0x12002e, 0x2}, + {0x22002e, 0x2}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x1e3}, + {0x2003a, 0x2}, + {0x2007d, 0x212}, + {0x2007c, 0x61}, + {0x120024, 0x1e3}, + {0x2003a, 0x2}, + {0x12007d, 0x212}, + {0x12007c, 0x61}, + {0x220024, 0x1e3}, + {0x2003a, 0x2}, + {0x22007d, 0x212}, + {0x22007c, 0x61}, + {0x20056, 0x3}, + {0x120056, 0x3}, + {0x220056, 0x3}, + {0x1004d, 0x600}, + {0x1014d, 0x600}, + {0x1104d, 0x600}, + {0x1114d, 0x600}, + {0x11004d, 0x600}, + {0x11014d, 0x600}, + {0x11104d, 0x600}, + {0x11114d, 0x600}, + {0x21004d, 0x600}, + {0x21014d, 0x600}, + {0x21104d, 0x600}, + {0x21114d, 0x600}, + {0x10049, 0x604}, + {0x10149, 0x604}, + {0x11049, 0x604}, + {0x11149, 0x604}, + {0x110049, 0x604}, + {0x110149, 0x604}, + {0x111049, 0x604}, + {0x111149, 0x604}, + {0x210049, 0x604}, + {0x210149, 0x604}, + {0x211049, 0x604}, + {0x211149, 0x604}, + {0x43, 0x60}, + {0x1043, 0x60}, + {0x2043, 0x60}, + {0x20018, 0x1}, + {0x20075, 0x4}, + {0x20050, 0x0}, + {0x2009b, 0x2}, + {0x20008, 0x3a5}, + {0x120008, 0x1d3}, + {0x220008, 0x9c}, + {0x20088, 0x9}, + {0x200b2, 0x104}, + {0x10043, 0x5a1}, + {0x10143, 0x5a1}, + {0x11043, 0x5a1}, + {0x11143, 0x5a1}, + {0x1200b2, 0x104}, + {0x110043, 0x5a1}, + {0x110143, 0x5a1}, + {0x111043, 0x5a1}, + {0x111143, 0x5a1}, + {0x2200b2, 0x104}, + {0x210043, 0x5a1}, + {0x210143, 0x5a1}, + {0x211043, 0x5a1}, + {0x211143, 0x5a1}, + {0x200fa, 0x2}, + {0x1200fa, 0x2}, + {0x2200fa, 0x2}, + {0x20019, 0x1}, + {0x120019, 0x1}, + {0x220019, 0x1}, + {0x200f0, 0x600}, + {0x200f1, 0x0}, + {0x200f2, 0x4444}, + {0x200f3, 0x8888}, + {0x200f4, 0x5655}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0xf000}, + {0x1004a, 0x500}, + {0x1104a, 0x500}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0x20021, 0x0}, + {0x200c7, 0x21}, + {0x1200c7, 0x21}, + {0x200ca, 0x24}, + {0x1200ca, 0x24}, +}; + +/* PHY trained csr */ +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + {0x1005f, 0x0}, + {0x1015f, 0x0}, + {0x1105f, 0x0}, + {0x1115f, 0x0}, + {0x11005f, 0x0}, + {0x11015f, 0x0}, + {0x11105f, 0x0}, + {0x11115f, 0x0}, + {0x21005f, 0x0}, + {0x21015f, 0x0}, + {0x21105f, 0x0}, + {0x21115f, 0x0}, + {0x55, 0x0}, + {0x1055, 0x0}, + {0x2055, 0x0}, + {0x200c5, 0x0}, + {0x1200c5, 0x0}, + {0x2200c5, 0x0}, + {0x2002e, 0x0}, + {0x12002e, 0x0}, + {0x22002e, 0x0}, + {0x90204, 0x0}, + {0x190204, 0x0}, + {0x290204, 0x0}, + {0x20024, 0x0}, + {0x2003a, 0x0}, + {0x2007d, 0x0}, + {0x2007c, 0x0}, + {0x120024, 0x0}, + {0x12007d, 0x0}, + {0x12007c, 0x0}, + {0x220024, 0x0}, + {0x22007d, 0x0}, + {0x22007c, 0x0}, + {0x20056, 0x0}, + {0x120056, 0x0}, + {0x220056, 0x0}, + {0x1004d, 0x0}, + {0x1014d, 0x0}, + {0x1104d, 0x0}, + {0x1114d, 0x0}, + {0x11004d, 0x0}, + {0x11014d, 0x0}, + {0x11104d, 0x0}, + {0x11114d, 0x0}, + {0x21004d, 0x0}, + {0x21014d, 0x0}, + {0x21104d, 0x0}, + {0x21114d, 0x0}, + {0x10049, 0x0}, + {0x10149, 0x0}, + {0x11049, 0x0}, + {0x11149, 0x0}, + {0x110049, 0x0}, + {0x110149, 0x0}, + {0x111049, 0x0}, + {0x111149, 0x0}, + {0x210049, 0x0}, + {0x210149, 0x0}, + {0x211049, 0x0}, + {0x211149, 0x0}, + {0x43, 0x0}, + {0x1043, 0x0}, + {0x2043, 0x0}, + {0x20018, 0x0}, + {0x20075, 0x0}, + {0x20050, 0x0}, + {0x2009b, 0x0}, + {0x20008, 0x0}, + {0x120008, 0x0}, + {0x220008, 0x0}, + {0x20088, 0x0}, + {0x200b2, 0x0}, + {0x10043, 0x0}, + {0x10143, 0x0}, + {0x11043, 0x0}, + {0x11143, 0x0}, + {0x1200b2, 0x0}, + {0x110043, 0x0}, + {0x110143, 0x0}, + {0x111043, 0x0}, + {0x111143, 0x0}, + {0x2200b2, 0x0}, + {0x210043, 0x0}, + {0x210143, 0x0}, + {0x211043, 0x0}, + {0x211143, 0x0}, + {0x200fa, 0x0}, + {0x1200fa, 0x0}, + {0x2200fa, 0x0}, + {0x20019, 0x0}, + {0x120019, 0x0}, + {0x220019, 0x0}, + {0x200f0, 0x0}, + {0x200f1, 0x0}, + {0x200f2, 0x0}, + {0x200f3, 0x0}, + {0x200f4, 0x0}, + {0x200f5, 0x0}, + {0x200f6, 0x0}, + {0x200f7, 0x0}, + {0x1004a, 0x0}, + {0x1104a, 0x0}, + {0x20025, 0x0}, + {0x2002d, 0x0}, + {0x12002d, 0x0}, + {0x22002d, 0x0}, + {0x2002c, 0x0}, + {0xd0000, 0x0}, + {0x90000, 0x0}, + {0x90001, 0x0}, + {0x90002, 0x0}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x0}, + {0x90029, 0x0}, + {0x9002a, 0x0}, + {0x9002b, 0x0}, + {0x9002c, 0x0}, + {0x9002d, 0x0}, + {0x9002e, 0x0}, + {0x9002f, 0x0}, + {0x90030, 0x0}, + {0x90031, 0x0}, + {0x90032, 0x0}, + {0x90033, 0x0}, + {0x90034, 0x0}, + {0x90035, 0x0}, + {0x90036, 0x0}, + {0x90037, 0x0}, + {0x90038, 0x0}, + {0x90039, 0x0}, + {0x9003a, 0x0}, + {0x9003b, 0x0}, + {0x9003c, 0x0}, + {0x9003d, 0x0}, + {0x9003e, 0x0}, + {0x9003f, 0x0}, + {0x90040, 0x0}, + {0x90041, 0x0}, + {0x90042, 0x0}, + {0x90043, 0x0}, + {0x90044, 0x0}, + {0x90045, 0x0}, + {0x90046, 0x0}, + {0x90047, 0x0}, + {0x90048, 0x0}, + {0x90049, 0x0}, + {0x9004a, 0x0}, + {0x9004b, 0x0}, + {0x9004c, 0x0}, + {0x9004d, 0x0}, + {0x9004e, 0x0}, + {0x9004f, 0x0}, + {0x90050, 0x0}, + {0x90051, 0x0}, + {0x90052, 0x0}, + {0x90053, 0x0}, + {0x90054, 0x0}, + {0x90055, 0x0}, + {0x90056, 0x0}, + {0x90057, 0x0}, + {0x90058, 0x0}, + {0x90059, 0x0}, + {0x9005a, 0x0}, + {0x9005b, 0x0}, + {0x9005c, 0x0}, + {0x9005d, 0x0}, + {0x9005e, 0x0}, + {0x9005f, 0x0}, + {0x90060, 0x0}, + {0x90061, 0x0}, + {0x90062, 0x0}, + {0x90063, 0x0}, + {0x90064, 0x0}, + {0x90065, 0x0}, + {0x90066, 0x0}, + {0x90067, 0x0}, + {0x90068, 0x0}, + {0x90069, 0x0}, + {0x9006a, 0x0}, + {0x9006b, 0x0}, + {0x9006c, 0x0}, + {0x9006d, 0x0}, + {0x9006e, 0x0}, + {0x9006f, 0x0}, + {0x90070, 0x0}, + {0x90071, 0x0}, + {0x90072, 0x0}, + {0x90073, 0x0}, + {0x90074, 0x0}, + {0x90075, 0x0}, + {0x90076, 0x0}, + {0x90077, 0x0}, + {0x90078, 0x0}, + {0x90079, 0x0}, + {0x9007a, 0x0}, + {0x9007b, 0x0}, + {0x9007c, 0x0}, + {0x9007d, 0x0}, + {0x9007e, 0x0}, + {0x9007f, 0x0}, + {0x90080, 0x0}, + {0x90081, 0x0}, + {0x90082, 0x0}, + {0x90083, 0x0}, + {0x90084, 0x0}, + {0x90085, 0x0}, + {0x90086, 0x0}, + {0x90087, 0x0}, + {0x90088, 0x0}, + {0x90089, 0x0}, + {0x9008a, 0x0}, + {0x9008b, 0x0}, + {0x9008c, 0x0}, + {0x9008d, 0x0}, + {0x9008e, 0x0}, + {0x9008f, 0x0}, + {0x90090, 0x0}, + {0x90091, 0x0}, + {0x90092, 0x0}, + {0x90093, 0x0}, + {0x90094, 0x0}, + {0x90095, 0x0}, + {0x90096, 0x0}, + {0x90097, 0x0}, + {0x90098, 0x0}, + {0x90099, 0x0}, + {0x9009a, 0x0}, + {0x9009b, 0x0}, + {0x9009c, 0x0}, + {0x9009d, 0x0}, + {0x9009e, 0x0}, + {0x9009f, 0x0}, + {0x900a0, 0x0}, + {0x900a1, 0x0}, + {0x900a2, 0x0}, + {0x900a3, 0x0}, + {0x900a4, 0x0}, + {0x900a5, 0x0}, + {0x900a6, 0x0}, + {0x900a7, 0x0}, + {0x900a8, 0x0}, + {0x900a9, 0x0}, + {0x40000, 0x0}, + {0x40020, 0x0}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x0}, + {0x40021, 0x0}, + {0x40041, 0x0}, + {0x40061, 0x0}, + {0x40002, 0x0}, + {0x40022, 0x0}, + {0x40042, 0x0}, + {0x40062, 0x0}, + {0x40003, 0x0}, + {0x40023, 0x0}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x0}, + {0x40024, 0x0}, + {0x40044, 0x0}, + {0x40064, 0x0}, + {0x40005, 0x0}, + {0x40025, 0x0}, + {0x40045, 0x0}, + {0x40065, 0x0}, + {0x40006, 0x0}, + {0x40026, 0x0}, + {0x40046, 0x0}, + {0x40066, 0x0}, + {0x40007, 0x0}, + {0x40027, 0x0}, + {0x40047, 0x0}, + {0x40067, 0x0}, + {0x40008, 0x0}, + {0x40028, 0x0}, + {0x40048, 0x0}, + {0x40068, 0x0}, + {0x40009, 0x0}, + {0x40029, 0x0}, + {0x40049, 0x0}, + {0x40069, 0x0}, + {0x4000a, 0x0}, + {0x4002a, 0x0}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x0}, + {0x4002b, 0x0}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x0}, + {0x4002c, 0x0}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0x0}, + {0x4002d, 0x0}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x0}, + {0x4002e, 0x0}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x0}, + {0x4002f, 0x0}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x0}, + {0x40030, 0x0}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x0}, + {0x40031, 0x0}, + {0x40051, 0x0}, + {0x40071, 0x0}, + {0x40012, 0x0}, + {0x40032, 0x0}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x0}, + {0x40033, 0x0}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x0}, + {0x40034, 0x0}, + {0x40054, 0x0}, + {0x40074, 0x0}, + {0x40015, 0x0}, + {0x40035, 0x0}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x0}, + {0x40036, 0x0}, + {0x40056, 0x0}, + {0x40076, 0x0}, + {0x40017, 0x0}, + {0x40037, 0x0}, + {0x40057, 0x0}, + {0x40077, 0x0}, + {0x40018, 0x0}, + {0x40038, 0x0}, + {0x40058, 0x0}, + {0x40078, 0x0}, + {0x40019, 0x0}, + {0x40039, 0x0}, + {0x40059, 0x0}, + {0x40079, 0x0}, + {0x4001a, 0x0}, + {0x4003a, 0x0}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x0}, + {0x900ac, 0x0}, + {0x900ad, 0x0}, + {0x900ae, 0x0}, + {0x900af, 0x0}, + {0x900b0, 0x0}, + {0x900b1, 0x0}, + {0x900b2, 0x0}, + {0x900b3, 0x0}, + {0x900b4, 0x0}, + {0x900b5, 0x0}, + {0x900b6, 0x0}, + {0x900b7, 0x0}, + {0x900b8, 0x0}, + {0x900b9, 0x0}, + {0x900ba, 0x0}, + {0x900bb, 0x0}, + {0x900bc, 0x0}, + {0x900bd, 0x0}, + {0x900be, 0x0}, + {0x900bf, 0x0}, + {0x900c0, 0x0}, + {0x900c1, 0x0}, + {0x900c2, 0x0}, + {0x900c3, 0x0}, + {0x900c4, 0x0}, + {0x900c5, 0x0}, + {0x900c6, 0x0}, + {0x900c7, 0x0}, + {0x900c8, 0x0}, + {0x900c9, 0x0}, + {0x900ca, 0x0}, + {0x900cb, 0x0}, + {0x900cc, 0x0}, + {0x900cd, 0x0}, + {0x900ce, 0x0}, + {0x900cf, 0x0}, + {0x900d0, 0x0}, + {0x900d1, 0x0}, + {0x900d2, 0x0}, + {0x900d3, 0x0}, + {0x900d4, 0x0}, + {0x900d5, 0x0}, + {0x900d6, 0x0}, + {0x900d7, 0x0}, + {0x900d8, 0x0}, + {0x900d9, 0x0}, + {0x900da, 0x0}, + {0x900db, 0x0}, + {0x900dc, 0x0}, + {0x900dd, 0x0}, + {0x900de, 0x0}, + {0x900df, 0x0}, + {0x900e0, 0x0}, + {0x900e1, 0x0}, + {0x900e2, 0x0}, + {0x900e3, 0x0}, + {0x900e4, 0x0}, + {0x900e5, 0x0}, + {0x900e6, 0x0}, + {0x900e7, 0x0}, + {0x900e8, 0x0}, + {0x900e9, 0x0}, + {0x900ea, 0x0}, + {0x900eb, 0x0}, + {0x900ec, 0x0}, + {0x900ed, 0x0}, + {0x900ee, 0x0}, + {0x900ef, 0x0}, + {0x900f0, 0x0}, + {0x900f1, 0x0}, + {0x900f2, 0x0}, + {0x900f3, 0x0}, + {0x900f4, 0x0}, + {0x900f5, 0x0}, + {0x900f6, 0x0}, + {0x900f7, 0x0}, + {0x900f8, 0x0}, + {0x900f9, 0x0}, + {0x900fa, 0x0}, + {0x900fb, 0x0}, + {0x900fc, 0x0}, + {0x900fd, 0x0}, + {0x900fe, 0x0}, + {0x900ff, 0x0}, + {0x90100, 0x0}, + {0x90101, 0x0}, + {0x90102, 0x0}, + {0x90103, 0x0}, + {0x90104, 0x0}, + {0x90105, 0x0}, + {0x90106, 0x0}, + {0x90107, 0x0}, + {0x90108, 0x0}, + {0x90109, 0x0}, + {0x9010a, 0x0}, + {0x9010b, 0x0}, + {0x9010c, 0x0}, + {0x9010d, 0x0}, + {0x9010e, 0x0}, + {0x9010f, 0x0}, + {0x90110, 0x0}, + {0x90111, 0x0}, + {0x90112, 0x0}, + {0x90113, 0x0}, + {0x90114, 0x0}, + {0x90115, 0x0}, + {0x90116, 0x0}, + {0x90117, 0x0}, + {0x90118, 0x0}, + {0x90119, 0x0}, + {0x9011a, 0x0}, + {0x9011b, 0x0}, + {0x9011c, 0x0}, + {0x9011d, 0x0}, + {0x9011e, 0x0}, + {0x9011f, 0x0}, + {0x90120, 0x0}, + {0x90121, 0x0}, + {0x90122, 0x0}, + {0x90123, 0x0}, + {0x90124, 0x0}, + {0x90125, 0x0}, + {0x90126, 0x0}, + {0x90127, 0x0}, + {0x90128, 0x0}, + {0x90129, 0x0}, + {0x9012a, 0x0}, + {0x9012b, 0x0}, + {0x9012c, 0x0}, + {0x9012d, 0x0}, + {0x9012e, 0x0}, + {0x9012f, 0x0}, + {0x90130, 0x0}, + {0x90131, 0x0}, + {0x90132, 0x0}, + {0x90133, 0x0}, + {0x90134, 0x0}, + {0x90135, 0x0}, + {0x90136, 0x0}, + {0x90137, 0x0}, + {0x90138, 0x0}, + {0x90139, 0x0}, + {0x9013a, 0x0}, + {0x9013b, 0x0}, + {0x9013c, 0x0}, + {0x9013d, 0x0}, + {0x9013e, 0x0}, + {0x9013f, 0x0}, + {0x90140, 0x0}, + {0x90141, 0x0}, + {0x90142, 0x0}, + {0x90143, 0x0}, + {0x90144, 0x0}, + {0x90145, 0x0}, + {0x90146, 0x0}, + {0x90147, 0x0}, + {0x90148, 0x0}, + {0x90149, 0x0}, + {0x9014a, 0x0}, + {0x9014b, 0x0}, + {0x9014c, 0x0}, + {0x9014d, 0x0}, + {0x9014e, 0x0}, + {0x9014f, 0x0}, + {0x90150, 0x0}, + {0x90151, 0x0}, + {0x90152, 0x0}, + {0x90153, 0x0}, + {0x90154, 0x0}, + {0x90155, 0x0}, + {0x90156, 0x0}, + {0x90157, 0x0}, + {0x90158, 0x0}, + {0x90159, 0x0}, + {0x9015a, 0x0}, + {0x9015b, 0x0}, + {0x9015c, 0x0}, + {0x9015d, 0x0}, + {0x9015e, 0x0}, + {0x9015f, 0x0}, + {0x90160, 0x0}, + {0x90161, 0x0}, + {0x90162, 0x0}, + {0x90163, 0x0}, + {0x90164, 0x0}, + {0x90165, 0x0}, + {0x90166, 0x0}, + {0x90167, 0x0}, + {0x90168, 0x0}, + {0x90169, 0x0}, + {0x9016a, 0x0}, + {0x9016b, 0x0}, + {0x9016c, 0x0}, + {0x9016d, 0x0}, + {0x9016e, 0x0}, + {0x9016f, 0x0}, + {0x90170, 0x0}, + {0x90171, 0x0}, + {0x90172, 0x0}, + {0x90173, 0x0}, + {0x90174, 0x0}, + {0x90175, 0x0}, + {0x90176, 0x0}, + {0x90177, 0x0}, + {0x90178, 0x0}, + {0x90179, 0x0}, + {0x9017a, 0x0}, + {0x9017b, 0x0}, + {0x9017c, 0x0}, + {0x9017d, 0x0}, + {0x9017e, 0x0}, + {0x9017f, 0x0}, + {0x90180, 0x0}, + {0x90181, 0x0}, + {0x90182, 0x0}, + {0x90183, 0x0}, + {0x90184, 0x0}, + {0x90006, 0x0}, + {0x90007, 0x0}, + {0x90008, 0x0}, + {0x90009, 0x0}, + {0x9000a, 0x0}, + {0x9000b, 0x0}, + {0xd00e7, 0x0}, + {0x90017, 0x0}, + {0x9001f, 0x0}, + {0x90026, 0x0}, + {0x400d0, 0x0}, + {0x400d1, 0x0}, + {0x400d2, 0x0}, + {0x400d3, 0x0}, + {0x400d4, 0x0}, + {0x400d5, 0x0}, + {0x400d6, 0x0}, + {0x400d7, 0x0}, + {0x200be, 0x0}, + {0x2000b, 0x0}, + {0x2000c, 0x0}, + {0x2000d, 0x0}, + {0x2000e, 0x0}, + {0x12000b, 0x0}, + {0x12000c, 0x0}, + {0x12000d, 0x0}, + {0x12000e, 0x0}, + {0x22000b, 0x0}, + {0x22000c, 0x0}, + {0x22000d, 0x0}, + {0x22000e, 0x0}, + {0x9000c, 0x0}, + {0x9000d, 0x0}, + {0x9000e, 0x0}, + {0x9000f, 0x0}, + {0x90010, 0x0}, + {0x90011, 0x0}, + {0x90012, 0x0}, + {0x90013, 0x0}, + {0x20010, 0x0}, + {0x20011, 0x0}, + {0x120010, 0x0}, + {0x120011, 0x0}, + {0x40080, 0x0}, + {0x40081, 0x0}, + {0x40082, 0x0}, + {0x40083, 0x0}, + {0x40084, 0x0}, + {0x40085, 0x0}, + {0x140080, 0x0}, + {0x140081, 0x0}, + {0x140082, 0x0}, + {0x140083, 0x0}, + {0x140084, 0x0}, + {0x140085, 0x0}, + {0x240080, 0x0}, + {0x240081, 0x0}, + {0x240082, 0x0}, + {0x240083, 0x0}, + {0x240084, 0x0}, + {0x240085, 0x0}, + {0x400fd, 0x0}, + {0x400f1, 0x0}, + {0x10011, 0x0}, + {0x10012, 0x0}, + {0x10013, 0x0}, + {0x10018, 0x0}, + {0x10002, 0x0}, + {0x100b2, 0x0}, + {0x101b4, 0x0}, + {0x102b4, 0x0}, + {0x103b4, 0x0}, + {0x104b4, 0x0}, + {0x105b4, 0x0}, + {0x106b4, 0x0}, + {0x107b4, 0x0}, + {0x108b4, 0x0}, + {0x11011, 0x0}, + {0x11012, 0x0}, + {0x11013, 0x0}, + {0x11018, 0x0}, + {0x11002, 0x0}, + {0x110b2, 0x0}, + {0x111b4, 0x0}, + {0x112b4, 0x0}, + {0x113b4, 0x0}, + {0x114b4, 0x0}, + {0x115b4, 0x0}, + {0x116b4, 0x0}, + {0x117b4, 0x0}, + {0x118b4, 0x0}, + {0x20089, 0x0}, + {0xc0080, 0x0}, + {0x200cb, 0x0}, + {0x10068, 0x0}, + {0x10069, 0x0}, + {0x10168, 0x0}, + {0x10169, 0x0}, + {0x10268, 0x0}, + {0x10269, 0x0}, + {0x10368, 0x0}, + {0x10369, 0x0}, + {0x10468, 0x0}, + {0x10469, 0x0}, + {0x10568, 0x0}, + {0x10569, 0x0}, + {0x10668, 0x0}, + {0x10669, 0x0}, + {0x10768, 0x0}, + {0x10769, 0x0}, + {0x10868, 0x0}, + {0x10869, 0x0}, + {0x100aa, 0x0}, + {0x10062, 0x0}, + {0x10001, 0x0}, + {0x100a0, 0x0}, + {0x100a1, 0x0}, + {0x100a2, 0x0}, + {0x100a3, 0x0}, + {0x100a4, 0x0}, + {0x100a5, 0x0}, + {0x100a6, 0x0}, + {0x100a7, 0x0}, + {0x11068, 0x0}, + {0x11069, 0x0}, + {0x11168, 0x0}, + {0x11169, 0x0}, + {0x11268, 0x0}, + {0x11269, 0x0}, + {0x11368, 0x0}, + {0x11369, 0x0}, + {0x11468, 0x0}, + {0x11469, 0x0}, + {0x11568, 0x0}, + {0x11569, 0x0}, + {0x11668, 0x0}, + {0x11669, 0x0}, + {0x11768, 0x0}, + {0x11769, 0x0}, + {0x11868, 0x0}, + {0x11869, 0x0}, + {0x110aa, 0x0}, + {0x11062, 0x0}, + {0x11001, 0x0}, + {0x110a0, 0x0}, + {0x110a1, 0x0}, + {0x110a2, 0x0}, + {0x110a3, 0x0}, + {0x110a4, 0x0}, + {0x110a5, 0x0}, + {0x110a6, 0x0}, + {0x110a7, 0x0}, + {0x80, 0x0}, + {0x1080, 0x0}, + {0x2080, 0x0}, + {0x10020, 0x0}, + {0x10080, 0x0}, + {0x10081, 0x0}, + {0x100d0, 0x0}, + {0x100d1, 0x0}, + {0x1008c, 0x0}, + {0x1008d, 0x0}, + {0x10180, 0x0}, + {0x10181, 0x0}, + {0x101d0, 0x0}, + {0x101d1, 0x0}, + {0x1018c, 0x0}, + {0x1018d, 0x0}, + {0x100c0, 0x0}, + {0x100c1, 0x0}, + {0x101c0, 0x0}, + {0x101c1, 0x0}, + {0x102c0, 0x0}, + {0x102c1, 0x0}, + {0x103c0, 0x0}, + {0x103c1, 0x0}, + {0x104c0, 0x0}, + {0x104c1, 0x0}, + {0x105c0, 0x0}, + {0x105c1, 0x0}, + {0x106c0, 0x0}, + {0x106c1, 0x0}, + {0x107c0, 0x0}, + {0x107c1, 0x0}, + {0x108c0, 0x0}, + {0x108c1, 0x0}, + {0x100ae, 0x0}, + {0x100af, 0x0}, + {0x11020, 0x0}, + {0x11080, 0x0}, + {0x11081, 0x0}, + {0x110d0, 0x0}, + {0x110d1, 0x0}, + {0x1108c, 0x0}, + {0x1108d, 0x0}, + {0x11180, 0x0}, + {0x11181, 0x0}, + {0x111d0, 0x0}, + {0x111d1, 0x0}, + {0x1118c, 0x0}, + {0x1118d, 0x0}, + {0x110c0, 0x0}, + {0x110c1, 0x0}, + {0x111c0, 0x0}, + {0x111c1, 0x0}, + {0x112c0, 0x0}, + {0x112c1, 0x0}, + {0x113c0, 0x0}, + {0x113c1, 0x0}, + {0x114c0, 0x0}, + {0x114c1, 0x0}, + {0x115c0, 0x0}, + {0x115c1, 0x0}, + {0x116c0, 0x0}, + {0x116c1, 0x0}, + {0x117c0, 0x0}, + {0x117c1, 0x0}, + {0x118c0, 0x0}, + {0x118c1, 0x0}, + {0x110ae, 0x0}, + {0x110af, 0x0}, + {0x90201, 0x0}, + {0x90202, 0x0}, + {0x90203, 0x0}, + {0x90205, 0x0}, + {0x90206, 0x0}, + {0x90207, 0x0}, + {0x90208, 0x0}, + {0x20020, 0x0}, + {0x100080, 0x0}, + {0x101080, 0x0}, + {0x102080, 0x0}, + {0x110020, 0x0}, + {0x110080, 0x0}, + {0x110081, 0x0}, + {0x1100d0, 0x0}, + {0x1100d1, 0x0}, + {0x11008c, 0x0}, + {0x11008d, 0x0}, + {0x110180, 0x0}, + {0x110181, 0x0}, + {0x1101d0, 0x0}, + {0x1101d1, 0x0}, + {0x11018c, 0x0}, + {0x11018d, 0x0}, + {0x1100c0, 0x0}, + {0x1100c1, 0x0}, + {0x1101c0, 0x0}, + {0x1101c1, 0x0}, + {0x1102c0, 0x0}, + {0x1102c1, 0x0}, + {0x1103c0, 0x0}, + {0x1103c1, 0x0}, + {0x1104c0, 0x0}, + {0x1104c1, 0x0}, + {0x1105c0, 0x0}, + {0x1105c1, 0x0}, + {0x1106c0, 0x0}, + {0x1106c1, 0x0}, + {0x1107c0, 0x0}, + {0x1107c1, 0x0}, + {0x1108c0, 0x0}, + {0x1108c1, 0x0}, + {0x1100ae, 0x0}, + {0x1100af, 0x0}, + {0x111020, 0x0}, + {0x111080, 0x0}, + {0x111081, 0x0}, + {0x1110d0, 0x0}, + {0x1110d1, 0x0}, + {0x11108c, 0x0}, + {0x11108d, 0x0}, + {0x111180, 0x0}, + {0x111181, 0x0}, + {0x1111d0, 0x0}, + {0x1111d1, 0x0}, + {0x11118c, 0x0}, + {0x11118d, 0x0}, + {0x1110c0, 0x0}, + {0x1110c1, 0x0}, + {0x1111c0, 0x0}, + {0x1111c1, 0x0}, + {0x1112c0, 0x0}, + {0x1112c1, 0x0}, + {0x1113c0, 0x0}, + {0x1113c1, 0x0}, + {0x1114c0, 0x0}, + {0x1114c1, 0x0}, + {0x1115c0, 0x0}, + {0x1115c1, 0x0}, + {0x1116c0, 0x0}, + {0x1116c1, 0x0}, + {0x1117c0, 0x0}, + {0x1117c1, 0x0}, + {0x1118c0, 0x0}, + {0x1118c1, 0x0}, + {0x1110ae, 0x0}, + {0x1110af, 0x0}, + {0x190201, 0x0}, + {0x190202, 0x0}, + {0x190203, 0x0}, + {0x190205, 0x0}, + {0x190206, 0x0}, + {0x190207, 0x0}, + {0x190208, 0x0}, + {0x120020, 0x0}, + {0x200080, 0x0}, + {0x201080, 0x0}, + {0x202080, 0x0}, + {0x210020, 0x0}, + {0x210080, 0x0}, + {0x210081, 0x0}, + {0x2100d0, 0x0}, + {0x2100d1, 0x0}, + {0x21008c, 0x0}, + {0x21008d, 0x0}, + {0x210180, 0x0}, + {0x210181, 0x0}, + {0x2101d0, 0x0}, + {0x2101d1, 0x0}, + {0x21018c, 0x0}, + {0x21018d, 0x0}, + {0x2100c0, 0x0}, + {0x2100c1, 0x0}, + {0x2101c0, 0x0}, + {0x2101c1, 0x0}, + {0x2102c0, 0x0}, + {0x2102c1, 0x0}, + {0x2103c0, 0x0}, + {0x2103c1, 0x0}, + {0x2104c0, 0x0}, + {0x2104c1, 0x0}, + {0x2105c0, 0x0}, + {0x2105c1, 0x0}, + {0x2106c0, 0x0}, + {0x2106c1, 0x0}, + {0x2107c0, 0x0}, + {0x2107c1, 0x0}, + {0x2108c0, 0x0}, + {0x2108c1, 0x0}, + {0x2100ae, 0x0}, + {0x2100af, 0x0}, + {0x211020, 0x0}, + {0x211080, 0x0}, + {0x211081, 0x0}, + {0x2110d0, 0x0}, + {0x2110d1, 0x0}, + {0x21108c, 0x0}, + {0x21108d, 0x0}, + {0x211180, 0x0}, + {0x211181, 0x0}, + {0x2111d0, 0x0}, + {0x2111d1, 0x0}, + {0x21118c, 0x0}, + {0x21118d, 0x0}, + {0x2110c0, 0x0}, + {0x2110c1, 0x0}, + {0x2111c0, 0x0}, + {0x2111c1, 0x0}, + {0x2112c0, 0x0}, + {0x2112c1, 0x0}, + {0x2113c0, 0x0}, + {0x2113c1, 0x0}, + {0x2114c0, 0x0}, + {0x2114c1, 0x0}, + {0x2115c0, 0x0}, + {0x2115c1, 0x0}, + {0x2116c0, 0x0}, + {0x2116c1, 0x0}, + {0x2117c0, 0x0}, + {0x2117c1, 0x0}, + {0x2118c0, 0x0}, + {0x2118c1, 0x0}, + {0x2110ae, 0x0}, + {0x2110af, 0x0}, + {0x290201, 0x0}, + {0x290202, 0x0}, + {0x290203, 0x0}, + {0x290205, 0x0}, + {0x290206, 0x0}, + {0x290207, 0x0}, + {0x290208, 0x0}, + {0x220020, 0x0}, + {0x20077, 0x0}, + {0x20072, 0x0}, + {0x20073, 0x0}, + {0x400c0, 0x0}, + {0x10040, 0x0}, + {0x10140, 0x0}, + {0x10240, 0x0}, + {0x10340, 0x0}, + {0x10440, 0x0}, + {0x10540, 0x0}, + {0x10640, 0x0}, + {0x10740, 0x0}, + {0x10840, 0x0}, + {0x11040, 0x0}, + {0x11140, 0x0}, + {0x11240, 0x0}, + {0x11340, 0x0}, + {0x11440, 0x0}, + {0x11540, 0x0}, + {0x11640, 0x0}, + {0x11740, 0x0}, + {0x11840, 0x0}, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x131f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x2236}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x2236}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp1_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x1}, + {0x54003, 0x74a}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x1bb4}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, + {0x5401e, 0x4}, + {0x5401f, 0x1bb4}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, + {0x54024, 0x4}, + {0x54032, 0xb400}, + {0x54033, 0x221b}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0xb400}, + {0x54039, 0x221b}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P2 message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp2_cfg[] = { + {0xd0000, 0x0}, + {0x54002, 0x102}, + {0x54003, 0x270}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x121f}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54012, 0x110}, + {0x54019, 0x994}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1200}, + {0x5401e, 0x4}, + {0x5401f, 0x994}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1200}, + {0x54024, 0x4}, + {0x54032, 0x9400}, + {0x54033, 0x2209}, + {0x54034, 0x4400}, + {0x54035, 0x1e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0x9400}, + {0x54039, 0x2209}, + {0x5403a, 0x4400}, + {0x5403b, 0x1e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + {0xd0000, 0x0}, + {0x54003, 0xe94}, + {0x54004, 0x4}, + {0x54006, 0x14}, + {0x54008, 0x61}, + {0x54009, 0xc8}, + {0x5400b, 0x4}, + {0x5400d, 0x100}, + {0x5400f, 0x100}, + {0x54010, 0x2080}, + {0x54012, 0x110}, + {0x54019, 0x36e4}, + {0x5401a, 0x22}, + {0x5401b, 0x1e44}, + {0x5401c, 0x1208}, + {0x5401e, 0x4}, + {0x5401f, 0x36e4}, + {0x54020, 0x22}, + {0x54021, 0x1e44}, + {0x54022, 0x1208}, + {0x54024, 0x4}, + {0x54032, 0xe400}, + {0x54033, 0x2236}, + {0x54034, 0x4400}, + {0x54035, 0x81e}, + {0x54036, 0x12}, + {0x54037, 0x400}, + {0x54038, 0xe400}, + {0x54039, 0x2236}, + {0x5403a, 0x4400}, + {0x5403b, 0x81e}, + {0x5403c, 0x12}, + {0x5403d, 0x400}, + {0xd0000, 0x1} +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param ddr_phy_pie[] = { + {0xd0000, 0x0}, + {0x90000, 0x10}, + {0x90001, 0x400}, + {0x90002, 0x10e}, + {0x90003, 0x0}, + {0x90004, 0x0}, + {0x90005, 0x8}, + {0x90029, 0xb}, + {0x9002a, 0x480}, + {0x9002b, 0x109}, + {0x9002c, 0x8}, + {0x9002d, 0x448}, + {0x9002e, 0x139}, + {0x9002f, 0x8}, + {0x90030, 0x478}, + {0x90031, 0x109}, + {0x90032, 0x0}, + {0x90033, 0xe8}, + {0x90034, 0x109}, + {0x90035, 0x2}, + {0x90036, 0x10}, + {0x90037, 0x139}, + {0x90038, 0xb}, + {0x90039, 0x7c0}, + {0x9003a, 0x139}, + {0x9003b, 0x44}, + {0x9003c, 0x633}, + {0x9003d, 0x159}, + {0x9003e, 0x14f}, + {0x9003f, 0x630}, + {0x90040, 0x159}, + {0x90041, 0x47}, + {0x90042, 0x633}, + {0x90043, 0x149}, + {0x90044, 0x4f}, + {0x90045, 0x633}, + {0x90046, 0x179}, + {0x90047, 0x8}, + {0x90048, 0xe0}, + {0x90049, 0x109}, + {0x9004a, 0x0}, + {0x9004b, 0x7c8}, + {0x9004c, 0x109}, + {0x9004d, 0x0}, + {0x9004e, 0x1}, + {0x9004f, 0x8}, + {0x90050, 0x30}, + {0x90051, 0x65a}, + {0x90052, 0x9}, + {0x90053, 0x0}, + {0x90054, 0x45a}, + {0x90055, 0x9}, + {0x90056, 0x0}, + {0x90057, 0x448}, + {0x90058, 0x109}, + {0x90059, 0x40}, + {0x9005a, 0x633}, + {0x9005b, 0x179}, + {0x9005c, 0x1}, + {0x9005d, 0x618}, + {0x9005e, 0x109}, + {0x9005f, 0x40c0}, + {0x90060, 0x633}, + {0x90061, 0x149}, + {0x90062, 0x8}, + {0x90063, 0x4}, + {0x90064, 0x48}, + {0x90065, 0x4040}, + {0x90066, 0x633}, + {0x90067, 0x149}, + {0x90068, 0x0}, + {0x90069, 0x4}, + {0x9006a, 0x48}, + {0x9006b, 0x40}, + {0x9006c, 0x633}, + {0x9006d, 0x149}, + {0x9006e, 0x0}, + {0x9006f, 0x658}, + {0x90070, 0x109}, + {0x90071, 0x10}, + {0x90072, 0x4}, + {0x90073, 0x18}, + {0x90074, 0x0}, + {0x90075, 0x4}, + {0x90076, 0x78}, + {0x90077, 0x549}, + {0x90078, 0x633}, + {0x90079, 0x159}, + {0x9007a, 0xd49}, + {0x9007b, 0x633}, + {0x9007c, 0x159}, + {0x9007d, 0x94a}, + {0x9007e, 0x633}, + {0x9007f, 0x159}, + {0x90080, 0x441}, + {0x90081, 0x633}, + {0x90082, 0x149}, + {0x90083, 0x42}, + {0x90084, 0x633}, + {0x90085, 0x149}, + {0x90086, 0x1}, + {0x90087, 0x633}, + {0x90088, 0x149}, + {0x90089, 0x0}, + {0x9008a, 0xe0}, + {0x9008b, 0x109}, + {0x9008c, 0xa}, + {0x9008d, 0x10}, + {0x9008e, 0x109}, + {0x9008f, 0x9}, + {0x90090, 0x3c0}, + {0x90091, 0x149}, + {0x90092, 0x9}, + {0x90093, 0x3c0}, + {0x90094, 0x159}, + {0x90095, 0x18}, + {0x90096, 0x10}, + {0x90097, 0x109}, + {0x90098, 0x0}, + {0x90099, 0x3c0}, + {0x9009a, 0x109}, + {0x9009b, 0x18}, + {0x9009c, 0x4}, + {0x9009d, 0x48}, + {0x9009e, 0x18}, + {0x9009f, 0x4}, + {0x900a0, 0x58}, + {0x900a1, 0xb}, + {0x900a2, 0x10}, + {0x900a3, 0x109}, + {0x900a4, 0x1}, + {0x900a5, 0x10}, + {0x900a6, 0x109}, + {0x900a7, 0x5}, + {0x900a8, 0x7c0}, + {0x900a9, 0x109}, + {0x40000, 0x811}, + {0x40020, 0x880}, + {0x40040, 0x0}, + {0x40060, 0x0}, + {0x40001, 0x4008}, + {0x40021, 0x83}, + {0x40041, 0x4f}, + {0x40061, 0x0}, + {0x40002, 0x4040}, + {0x40022, 0x83}, + {0x40042, 0x51}, + {0x40062, 0x0}, + {0x40003, 0x811}, + {0x40023, 0x880}, + {0x40043, 0x0}, + {0x40063, 0x0}, + {0x40004, 0x720}, + {0x40024, 0xf}, + {0x40044, 0x1740}, + {0x40064, 0x0}, + {0x40005, 0x16}, + {0x40025, 0x83}, + {0x40045, 0x4b}, + {0x40065, 0x0}, + {0x40006, 0x716}, + {0x40026, 0xf}, + {0x40046, 0x2001}, + {0x40066, 0x0}, + {0x40007, 0x716}, + {0x40027, 0xf}, + {0x40047, 0x2800}, + {0x40067, 0x0}, + {0x40008, 0x716}, + {0x40028, 0xf}, + {0x40048, 0xf00}, + {0x40068, 0x0}, + {0x40009, 0x720}, + {0x40029, 0xf}, + {0x40049, 0x1400}, + {0x40069, 0x0}, + {0x4000a, 0xe08}, + {0x4002a, 0xc15}, + {0x4004a, 0x0}, + {0x4006a, 0x0}, + {0x4000b, 0x625}, + {0x4002b, 0x15}, + {0x4004b, 0x0}, + {0x4006b, 0x0}, + {0x4000c, 0x4028}, + {0x4002c, 0x80}, + {0x4004c, 0x0}, + {0x4006c, 0x0}, + {0x4000d, 0xe08}, + {0x4002d, 0xc1a}, + {0x4004d, 0x0}, + {0x4006d, 0x0}, + {0x4000e, 0x625}, + {0x4002e, 0x1a}, + {0x4004e, 0x0}, + {0x4006e, 0x0}, + {0x4000f, 0x4040}, + {0x4002f, 0x80}, + {0x4004f, 0x0}, + {0x4006f, 0x0}, + {0x40010, 0x2604}, + {0x40030, 0x15}, + {0x40050, 0x0}, + {0x40070, 0x0}, + {0x40011, 0x708}, + {0x40031, 0x5}, + {0x40051, 0x0}, + {0x40071, 0x2002}, + {0x40012, 0x8}, + {0x40032, 0x80}, + {0x40052, 0x0}, + {0x40072, 0x0}, + {0x40013, 0x2604}, + {0x40033, 0x1a}, + {0x40053, 0x0}, + {0x40073, 0x0}, + {0x40014, 0x708}, + {0x40034, 0xa}, + {0x40054, 0x0}, + {0x40074, 0x2002}, + {0x40015, 0x4040}, + {0x40035, 0x80}, + {0x40055, 0x0}, + {0x40075, 0x0}, + {0x40016, 0x60a}, + {0x40036, 0x15}, + {0x40056, 0x1200}, + {0x40076, 0x0}, + {0x40017, 0x61a}, + {0x40037, 0x15}, + {0x40057, 0x1300}, + {0x40077, 0x0}, + {0x40018, 0x60a}, + {0x40038, 0x1a}, + {0x40058, 0x1200}, + {0x40078, 0x0}, + {0x40019, 0x642}, + {0x40039, 0x1a}, + {0x40059, 0x1300}, + {0x40079, 0x0}, + {0x4001a, 0x4808}, + {0x4003a, 0x880}, + {0x4005a, 0x0}, + {0x4007a, 0x0}, + {0x900aa, 0x0}, + {0x900ab, 0x790}, + {0x900ac, 0x11a}, + {0x900ad, 0x8}, + {0x900ae, 0x7aa}, + {0x900af, 0x2a}, + {0x900b0, 0x10}, + {0x900b1, 0x7b2}, + {0x900b2, 0x2a}, + {0x900b3, 0x0}, + {0x900b4, 0x7c8}, + {0x900b5, 0x109}, + {0x900b6, 0x10}, + {0x900b7, 0x10}, + {0x900b8, 0x109}, + {0x900b9, 0x10}, + {0x900ba, 0x2a8}, + {0x900bb, 0x129}, + {0x900bc, 0x8}, + {0x900bd, 0x370}, + {0x900be, 0x129}, + {0x900bf, 0xa}, + {0x900c0, 0x3c8}, + {0x900c1, 0x1a9}, + {0x900c2, 0xc}, + {0x900c3, 0x408}, + {0x900c4, 0x199}, + {0x900c5, 0x14}, + {0x900c6, 0x790}, + {0x900c7, 0x11a}, + {0x900c8, 0x8}, + {0x900c9, 0x4}, + {0x900ca, 0x18}, + {0x900cb, 0xe}, + {0x900cc, 0x408}, + {0x900cd, 0x199}, + {0x900ce, 0x8}, + {0x900cf, 0x8568}, + {0x900d0, 0x108}, + {0x900d1, 0x18}, + {0x900d2, 0x790}, + {0x900d3, 0x16a}, + {0x900d4, 0x8}, + {0x900d5, 0x1d8}, + {0x900d6, 0x169}, + {0x900d7, 0x10}, + {0x900d8, 0x8558}, + {0x900d9, 0x168}, + {0x900da, 0x1ff8}, + {0x900db, 0x85a8}, + {0x900dc, 0x1e8}, + {0x900dd, 0x50}, + {0x900de, 0x798}, + {0x900df, 0x16a}, + {0x900e0, 0x60}, + {0x900e1, 0x7a0}, + {0x900e2, 0x16a}, + {0x900e3, 0x8}, + {0x900e4, 0x8310}, + {0x900e5, 0x168}, + {0x900e6, 0x8}, + {0x900e7, 0xa310}, + {0x900e8, 0x168}, + {0x900e9, 0xa}, + {0x900ea, 0x408}, + {0x900eb, 0x169}, + {0x900ec, 0x6e}, + {0x900ed, 0x0}, + {0x900ee, 0x68}, + {0x900ef, 0x0}, + {0x900f0, 0x408}, + {0x900f1, 0x169}, + {0x900f2, 0x0}, + {0x900f3, 0x8310}, + {0x900f4, 0x168}, + {0x900f5, 0x0}, + {0x900f6, 0xa310}, + {0x900f7, 0x168}, + {0x900f8, 0x1ff8}, + {0x900f9, 0x85a8}, + {0x900fa, 0x1e8}, + {0x900fb, 0x68}, + {0x900fc, 0x798}, + {0x900fd, 0x16a}, + {0x900fe, 0x78}, + {0x900ff, 0x7a0}, + {0x90100, 0x16a}, + {0x90101, 0x68}, + {0x90102, 0x790}, + {0x90103, 0x16a}, + {0x90104, 0x8}, + {0x90105, 0x8b10}, + {0x90106, 0x168}, + {0x90107, 0x8}, + {0x90108, 0xab10}, + {0x90109, 0x168}, + {0x9010a, 0xa}, + {0x9010b, 0x408}, + {0x9010c, 0x169}, + {0x9010d, 0x58}, + {0x9010e, 0x0}, + {0x9010f, 0x68}, + {0x90110, 0x0}, + {0x90111, 0x408}, + {0x90112, 0x169}, + {0x90113, 0x0}, + {0x90114, 0x8b10}, + {0x90115, 0x168}, + {0x90116, 0x1}, + {0x90117, 0xab10}, + {0x90118, 0x168}, + {0x90119, 0x0}, + {0x9011a, 0x1d8}, + {0x9011b, 0x169}, + {0x9011c, 0x80}, + {0x9011d, 0x790}, + {0x9011e, 0x16a}, + {0x9011f, 0x18}, + {0x90120, 0x7aa}, + {0x90121, 0x6a}, + {0x90122, 0xa}, + {0x90123, 0x0}, + {0x90124, 0x1e9}, + {0x90125, 0x8}, + {0x90126, 0x8080}, + {0x90127, 0x108}, + {0x90128, 0xf}, + {0x90129, 0x408}, + {0x9012a, 0x169}, + {0x9012b, 0xc}, + {0x9012c, 0x0}, + {0x9012d, 0x68}, + {0x9012e, 0x9}, + {0x9012f, 0x0}, + {0x90130, 0x1a9}, + {0x90131, 0x0}, + {0x90132, 0x408}, + {0x90133, 0x169}, + {0x90134, 0x0}, + {0x90135, 0x8080}, + {0x90136, 0x108}, + {0x90137, 0x8}, + {0x90138, 0x7aa}, + {0x90139, 0x6a}, + {0x9013a, 0x0}, + {0x9013b, 0x8568}, + {0x9013c, 0x108}, + {0x9013d, 0xb7}, + {0x9013e, 0x790}, + {0x9013f, 0x16a}, + {0x90140, 0x1f}, + {0x90141, 0x0}, + {0x90142, 0x68}, + {0x90143, 0x8}, + {0x90144, 0x8558}, + {0x90145, 0x168}, + {0x90146, 0xf}, + {0x90147, 0x408}, + {0x90148, 0x169}, + {0x90149, 0xd}, + {0x9014a, 0x0}, + {0x9014b, 0x68}, + {0x9014c, 0x0}, + {0x9014d, 0x408}, + {0x9014e, 0x169}, + {0x9014f, 0x0}, + {0x90150, 0x8558}, + {0x90151, 0x168}, + {0x90152, 0x8}, + {0x90153, 0x3c8}, + {0x90154, 0x1a9}, + {0x90155, 0x3}, + {0x90156, 0x370}, + {0x90157, 0x129}, + {0x90158, 0x20}, + {0x90159, 0x2aa}, + {0x9015a, 0x9}, + {0x9015b, 0x8}, + {0x9015c, 0xe8}, + {0x9015d, 0x109}, + {0x9015e, 0x0}, + {0x9015f, 0x8140}, + {0x90160, 0x10c}, + {0x90161, 0x10}, + {0x90162, 0x8138}, + {0x90163, 0x104}, + {0x90164, 0x8}, + {0x90165, 0x448}, + {0x90166, 0x109}, + {0x90167, 0xf}, + {0x90168, 0x7c0}, + {0x90169, 0x109}, + {0x9016a, 0x0}, + {0x9016b, 0xe8}, + {0x9016c, 0x109}, + {0x9016d, 0x47}, + {0x9016e, 0x630}, + {0x9016f, 0x109}, + {0x90170, 0x8}, + {0x90171, 0x618}, + {0x90172, 0x109}, + {0x90173, 0x8}, + {0x90174, 0xe0}, + {0x90175, 0x109}, + {0x90176, 0x0}, + {0x90177, 0x7c8}, + {0x90178, 0x109}, + {0x90179, 0x8}, + {0x9017a, 0x8140}, + {0x9017b, 0x10c}, + {0x9017c, 0x0}, + {0x9017d, 0x478}, + {0x9017e, 0x109}, + {0x9017f, 0x0}, + {0x90180, 0x1}, + {0x90181, 0x8}, + {0x90182, 0x8}, + {0x90183, 0x4}, + {0x90184, 0x0}, + {0x90006, 0x8}, + {0x90007, 0x7c8}, + {0x90008, 0x109}, + {0x90009, 0x0}, + {0x9000a, 0x400}, + {0x9000b, 0x106}, + {0xd00e7, 0x400}, + {0x90017, 0x0}, + {0x9001f, 0x2b}, + {0x90026, 0x69}, + {0x400d0, 0x0}, + {0x400d1, 0x101}, + {0x400d2, 0x105}, + {0x400d3, 0x107}, + {0x400d4, 0x10f}, + {0x400d5, 0x202}, + {0x400d6, 0x20a}, + {0x400d7, 0x20b}, + {0x2003a, 0x2}, + {0x200be, 0x3}, + {0x2000b, 0x41a}, + {0x2000c, 0xe9}, + {0x2000d, 0x91c}, + {0x2000e, 0x2c}, + {0x12000b, 0x20d}, + {0x12000c, 0x74}, + {0x12000d, 0x48e}, + {0x12000e, 0x2c}, + {0x22000b, 0xb0}, + {0x22000c, 0x27}, + {0x22000d, 0x186}, + {0x22000e, 0x10}, + {0x9000c, 0x0}, + {0x9000d, 0x173}, + {0x9000e, 0x60}, + {0x9000f, 0x6110}, + {0x90010, 0x2152}, + {0x90011, 0xdfbd}, + {0x90012, 0x2060}, + {0x90013, 0x6152}, + {0x20010, 0x5a}, + {0x20011, 0x3}, + {0x120010, 0x5a}, + {0x120011, 0x3}, + {0x40080, 0xe0}, + {0x40081, 0x12}, + {0x40082, 0xe0}, + {0x40083, 0x12}, + {0x40084, 0xe0}, + {0x40085, 0x12}, + {0x140080, 0xe0}, + {0x140081, 0x12}, + {0x140082, 0xe0}, + {0x140083, 0x12}, + {0x140084, 0xe0}, + {0x140085, 0x12}, + {0x240080, 0xe0}, + {0x240081, 0x12}, + {0x240082, 0xe0}, + {0x240083, 0x12}, + {0x240084, 0xe0}, + {0x240085, 0x12}, + {0x400fd, 0xf}, + {0x400f1, 0xe}, + {0x10011, 0x1}, + {0x10012, 0x1}, + {0x10013, 0x180}, + {0x10018, 0x1}, + {0x10002, 0x6209}, + {0x100b2, 0x1}, + {0x101b4, 0x1}, + {0x102b4, 0x1}, + {0x103b4, 0x1}, + {0x104b4, 0x1}, + {0x105b4, 0x1}, + {0x106b4, 0x1}, + {0x107b4, 0x1}, + {0x108b4, 0x1}, + {0x11011, 0x1}, + {0x11012, 0x1}, + {0x11013, 0x180}, + {0x11018, 0x1}, + {0x11002, 0x6209}, + {0x110b2, 0x1}, + {0x111b4, 0x1}, + {0x112b4, 0x1}, + {0x113b4, 0x1}, + {0x114b4, 0x1}, + {0x115b4, 0x1}, + {0x116b4, 0x1}, + {0x117b4, 0x1}, + {0x118b4, 0x1}, + {0x20089, 0x1}, + {0x20088, 0x19}, + {0xc0080, 0x0}, + {0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; + +void set_dram_timings_2gb_lpddr4x(void) +{ + /* Initialize DDRC registers */ + dram_timing.ddrc_cfg[1].val = 0x8000ff; + dram_timing.ddrc_cfg[3].val = 0x80000512; + + /* dram fsp cfg */ + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B; + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233; + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B; + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213; + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13; + + dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100; + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA; + dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA; + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13; + + dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000; + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48; + dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034; + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13; + + /* P0 message block parameter for training firmware */ + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308; + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13; + + /* P1 message block parameter for training firmware */ + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308; + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308; + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13; + + /* P2 message block parameter for training firmware */ + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300; + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300; + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13; + + /* P0 2D message block parameter for training firmware */ + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308; + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13; +} + +/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */ +void set_dram_timings_1gb_lpddr4x_900mhz(void) +{ + /* Initialize DDRC registers */ + dram_timing.ddrc_cfg[6].val = 0x4080; + + /* dram fsp cfg */ + dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100; + dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E; + dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA; + dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6; + dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000; + dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101; + dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000; + dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508; + dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014; + dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B; + dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B; + dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A; + dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E; + dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4; + dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B; + dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15; + + dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA; + dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15; + + dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48; + dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2; + dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; + dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15; + + /* PHY Initialize Configuration */ + dram_timing.ddrphy_cfg[31].val = 0xb; + dram_timing.ddrphy_cfg[86].val = 0x1d3; + dram_timing.ddrphy_cfg[90].val = 0x10c; + dram_timing.ddrphy_cfg[95].val = 0x10c; + dram_timing.ddrphy_cfg[100].val = 0x10c; + dram_timing.ddrphy_cfg[122].val = 0x1; + /** + * NOTE: + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119 + * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not + * present in the ddr_ddrphy_cfg array. However they were present in array + * generated with previous DDR Tool v3.1.0_7.4. We simply set both values + * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid + * any negative side-effects. + */ + dram_timing.ddrphy_cfg[119].val = 0x400; + dram_timing.ddrphy_cfg[120].val = 0x400; + + /** + * NOTE: + * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101 + * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present + * in the ddr_ddrphy_trained_csr array. However they were present in array + * generated with previous DDR Tool v3.1.0_7.4. We simply set both values + * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid + * any negative side-effects. + */ + /* PHY trained csr */ + dram_timing.ddrphy_trained_csr[101].val = 0x0; + dram_timing.ddrphy_trained_csr[102].val = 0x0; + + /* P0 message block parameter for training firmware */ + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a; + dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15; + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4; + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2; + dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508; + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4; + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2; + dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; + dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508; + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400; + dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b; + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15; + dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400; + dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b; + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; + dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15; + + /* P1 message block parameter for training firmware */ + dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15; + dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508; + dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508; + dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b; + dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b; + dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15; + + /* P2 message block parameter for training firmware */ + dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15; + dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500; + dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500; + dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209; + dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209; + dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; + dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15; + + /* P0 2D message block parameter for training firmware */ + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a; + dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15; + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4; + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2; + dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508; + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4; + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2; + dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; + dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508; + dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400; + dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b; + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15; + dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400; + dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b; + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; + dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15; + + /* DRAM PHY init engine image */ + dram_timing.ddrphy_pie[483].val = 0x20d; + dram_timing.ddrphy_pie[484].val = 0x74; + dram_timing.ddrphy_pie[485].val = 0x48e; + + /* P0 3733mts 1D */ + dram_timing.fsp_msg[0].drate = 1866; + + /* P0 1866mts 2D */ + dram_timing.fsp_msg[3].drate = 1866; + + /* ddr timing config params */ + dram_timing.fsp_table[0] = 1866; +} diff --git a/board/phytec/phycore_imx91_93/phycore-imx91-93.c b/board/phytec/phycore_imx91_93/phycore-imx91-93.c new file mode 100644 index 00000000000..2605a3bd09e --- /dev/null +++ b/board/phytec/phycore_imx91_93/phycore-imx91-93.c @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include + +#include "../common/imx91_93_som_detection.h" + +#define EEPROM_ADDR 0x50 + +int board_init(void) +{ + int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); + + if (ret) + printf("%s: EEPROM data init failed\n", __func__); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ + switch (get_boot_device()) { + case SD2_BOOT: + env_set_ulong("mmcdev", 1); + if (!env_get("boot_targets")) + env_set("boot_targets", "mmc1 mmc0 ethernet"); + break; + case MMC1_BOOT: + env_set_ulong("mmcdev", 0); + break; + case USB_BOOT: + printf("Detect USB boot. Will enter fastboot mode!\n"); + if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) + env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); + break; + default: + break; + } + + return 0; +} + +static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) +{ + enum phytec_imx91_93_voltage voltage = phytec_imx91_93_get_voltage(data); + int offset; + + if (voltage == PHYTEC_IMX91_93_VOLTAGE_INVALID) + goto err; + + if (voltage == PHYTEC_IMX91_93_VOLTAGE_1V8) { + offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", + 0x42850000); + if (offset) + fdt_delprop(blob, offset, "no-1-8-v"); + else + goto err; + } + + return; +err: + printf("Could not detect eMMC VDD-IO. Fall back to default.\n"); +} + +int board_fix_fdt(void *blob) +{ + struct phytec_eeprom_data data; + + phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR); + + emmc_fixup(blob, &data); + + /* Update dtb clocks for low drive mode */ + if (is_voltage_mode(VOLT_LOW_DRIVE)) + low_drive_freq_update(blob); + + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + emmc_fixup(blob, NULL); + + /** + * NOTE: VOLT_LOW_DRIVE fixup is done by the ft_system_setup() + * in arch/arm/mach-imx/imx9/soc.c for Linux device-tree. + */ + + return 0; +} diff --git a/board/phytec/phycore_imx91_93/phycore_imx91_93.env b/board/phytec/phycore_imx91_93/phycore_imx91_93.env new file mode 100644 index 00000000000..a39359869d6 --- /dev/null +++ b/board/phytec/phycore_imx91_93/phycore_imx91_93.env @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +boot_script_dhcp=net_boot_fit.scr.uimg +console=ttyLP0 +emmc_dev=0 /* This is needed by built-in uuu flash scripts */ +fdt_addr_r=0x90000000 +fdtfile=DEFAULT_FDT_FILE +fdtoverlay_addr_r=0x900c0000 +ip_dyn=yes +kernel_addr_r=0x88000000 +nfsroot=/srv/nfs +#ifdef CONFIG_IMX93 +prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" +#endif +scriptaddr=0x83500000 +sd_dev=1 /* This is needed by built-in uuu flash scripts */ diff --git a/board/phytec/phycore_imx91_93/spl.c b/board/phytec/phycore_imx91_93/spl.c new file mode 100644 index 00000000000..92441c5af32 --- /dev/null +++ b/board/phytec/phycore_imx91_93/spl.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Author: Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/imx91_93_som_detection.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define EEPROM_ADDR 0x50 + +/* + * Prototypes of automatically generated ram config file + */ +void set_dram_timings_2gb_lpddr4x(void); +void set_dram_timings_1gb_lpddr4x_900mhz(void); + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); + + puts("Normal Boot\n"); +} + +void spl_dram_init(void) +{ + int ret; + enum phytec_imx91_93_ddr_eeprom_code ddr_opt = PHYTEC_IMX91_93_DDR_INVALID; + + ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); + if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) + goto out; + + ret = phytec_imx91_93_detect(NULL); + if (!ret) + phytec_print_som_info(NULL); + + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_1GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_IMX91_93_RAM_TYPE_LPDDR4X_2GB)) + ddr_opt = PHYTEC_IMX91_93_LPDDR4X_2GB; + } else { + ddr_opt = phytec_imx91_93_get_opt(NULL, PHYTEC_IMX91_93_OPT_DDR); + } + + switch (ddr_opt) { + case PHYTEC_IMX91_93_LPDDR4_1GB: + /* Timings statically set for i.MX91 LPDDR4 1GB. */ + break; + case PHYTEC_IMX91_93_LPDDR4X_1GB: + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) + set_dram_timings_1gb_lpddr4x_900mhz(); + break; + case PHYTEC_IMX91_93_LPDDR4X_2GB: + if (IS_ENABLED(CONFIG_IMX93)) + set_dram_timings_2gb_lpddr4x(); + break; + default: + goto out; + } + ddr_init(&dram_timing); + return; +out: + puts("Could not detect correct RAM type and size. Fall back to default.\n"); + if (IS_ENABLED(CONFIG_IMX93) && is_voltage_mode(VOLT_LOW_DRIVE)) + set_dram_timings_1gb_lpddr4x_900mhz(); + ddr_init(&dram_timing); +} + +int power_init_board(void) +{ + struct udevice *dev; + int ret; + unsigned int val = 0, buck_val; + + ret = pmic_get("pmic@25", &dev); + if (ret == -ENODEV) { + puts("No pca9450@25\n"); + return 0; + } + + if (ret != 0) + return ret; + + /* BUCKxOUT_DVS0/1 control BUCK123 output */ + pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); + + /* enable DVS control through PMIC_STBY_REQ */ + pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); + + ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); + if (ret < 0) + return ret; + val = ret; + + if (is_voltage_mode(VOLT_LOW_DRIVE)) { + buck_val = 0x0c; /* 0.8v for Low drive mode */ + printf("PMIC: Low Drive Voltage Mode\n"); + } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { + buck_val = 0x10; /* 0.85v for Nominal drive mode */ + printf("PMIC: Nominal Voltage Mode\n"); + } else { + buck_val = 0x14; /* 0.9v for Over drive mode */ + printf("PMIC: Over Drive Voltage Mode\n"); + } + + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); + } else { + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); + pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); + } + + /* set standby voltage to 0.65v */ + if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); + else + pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); + + /* I2C_LT_EN*/ + pmic_reg_write(dev, 0xa, 0x3); + + return 0; +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + timer_init(); + + arch_cpu_init(); + + spl_early_init(); + + preloader_console_init(); + + ret = imx9_probe_mu(); + if (ret) { + printf("Fail to init ELE API\n"); + } else { + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + } + + clock_init_late(); + + power_init_board(); + + if (!is_voltage_mode(VOLT_LOW_DRIVE)) + set_arm_core_max_clk(); + + /* Init power of mix */ + soc_power_init(); + + /* Setup TRDC for DDR access */ + trdc_init(); + + /* DDR initialization */ + spl_dram_init(); + + if (IS_ENABLED(CONFIG_IMX93)) { + /* Put M33 into CPUWAIT for following kick */ + ret = m33_prepare(); + if (!ret) + printf("M33 prepare ok\n"); + } + + board_init_r(NULL, 0); +} diff --git a/board/phytec/phycore_imx93/Kconfig b/board/phytec/phycore_imx93/Kconfig deleted file mode 100644 index 09f26e89e33..00000000000 --- a/board/phytec/phycore_imx93/Kconfig +++ /dev/null @@ -1,41 +0,0 @@ - -if TARGET_PHYCORE_IMX93 - -config SYS_BOARD - default "phycore_imx93" - -config SYS_VENDOR - default "phytec" - -config SYS_CONFIG_NAME - default "phycore_imx93" - -config PHYCORE_IMX93_RAM_TYPE_FIX - bool "Set phyCORE-i.MX93 RAM type and size fix instead of detecting" - default false - help - RAM type and size is being automatically detected with the help - of the PHYTEC EEPROM introspection data. - Set RAM type to a fix value instead. - -choice - prompt "phyCORE-i.MX93 RAM type" - depends on PHYCORE_IMX93_RAM_TYPE_FIX - default PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB - bool "LPDDR4X 1GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 1GB - for phyCORE-i.MX93. - -config PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB - bool "LPDDR4X 2GB RAM" - help - Set RAM type fixed to LPDDR4X and RAM size fixed to 2GB - for phyCORE-i.MX93. - -endchoice - -source "board/phytec/common/Kconfig" -endif diff --git a/board/phytec/phycore_imx93/MAINTAINERS b/board/phytec/phycore_imx93/MAINTAINERS deleted file mode 100644 index 0b087bf1ef2..00000000000 --- a/board/phytec/phycore_imx93/MAINTAINERS +++ /dev/null @@ -1,12 +0,0 @@ -phyCORE-i.MX93 -M: Mathieu Othacehe -R: Christoph Stoidner -L: upstream@lists.phytec.de -W: https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/ -S: Maintained -F: arch/arm/dts/imx93-phyboard-segin-u-boot.dtsi -F: board/phytec/phycore_imx93/ -F: board/phytec/common/imx93_som_detection.c -F: board/phytec/common/imx93_som_detection.h -F: configs/imx93-phycore_defconfig -F: include/configs/phycore_imx93.h diff --git a/board/phytec/phycore_imx93/Makefile b/board/phytec/phycore_imx93/Makefile deleted file mode 100644 index dd5085e160f..00000000000 --- a/board/phytec/phycore_imx93/Makefile +++ /dev/null @@ -1,14 +0,0 @@ -# -# Copyright 2022 NXP -# Copyright (C) 2023 PHYTEC Messtechnik GmbH -# Christoph Stoidner -# Copyright (C) 2024 Mathieu Othacehe -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += phycore-imx93.o - -ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4_timing.o -endif diff --git a/board/phytec/phycore_imx93/lpddr4_timing.c b/board/phytec/phycore_imx93/lpddr4_timing.c deleted file mode 100644 index f1261f6a92a..00000000000 --- a/board/phytec/phycore_imx93/lpddr4_timing.c +++ /dev/null @@ -1,2217 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2024 NXP - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - * Christoph Stoidner - * - * Code generated with DDR Tool v3.1.0_7.4. - */ - -#include -#include - -/* Initialize DDRC registers */ -static struct dram_cfg_param ddr_ddrc_cfg[] = { - {0x4e300110, 0x44100001}, - {0x4e300000, 0x8000bf}, - {0x4e300008, 0x0}, - {0x4e300080, 0x80000412}, - {0x4e300084, 0x0}, - {0x4e300114, 0x1002}, - {0x4e300260, 0x80}, - {0x4e300f04, 0x80}, - {0x4e300800, 0x43b30002}, - {0x4e300804, 0x1f1f1f1f}, - {0x4e301000, 0x0}, - {0x4e301240, 0x0}, - {0x4e301244, 0x0}, - {0x4e301248, 0x0}, - {0x4e30124c, 0x0}, - {0x4e301250, 0x0}, - {0x4e301254, 0x0}, - {0x4e301258, 0x0}, - {0x4e30125c, 0x0}, -}; - -/* dram fsp cfg */ -static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { - { - { - {0x4e300100, 0x24A0321B}, - {0x4e300104, 0xF8EE001B}, - {0x4e300108, 0x2F2E3233}, - {0x4e30010C, 0x0005C18B}, - {0x4e300124, 0x1C790000}, - {0x4e300160, 0x00009102}, - {0x4e30016C, 0x35F00000}, - {0x4e300170, 0x8B0B0608}, - {0x4e300250, 0x00000028}, - {0x4e300254, 0x00FE00FE}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - {0x4e300300, 0x224F2213}, - {0x4e300304, 0x00FE2213}, - {0x4e300308, 0x0A380E3D}, - }, - { - {0x01, 0xE4}, - {0x02, 0x36}, - {0x03, 0x22}, - {0x0b, 0x44}, - {0x0c, 0x1E}, - {0x0e, 0x12}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x124F2100}, - {0x4e300104, 0xF877000E}, - {0x4e300108, 0x1816E4AA}, - {0x4e30010C, 0x005101E6}, - {0x4e300124, 0x0E3C0000}, - {0x4e300160, 0x00009101}, - {0x4e30016C, 0x30900000}, - {0x4e300170, 0x8A0A0508}, - {0x4e300250, 0x00000014}, - {0x4e300254, 0x007B007B}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0xB4}, - {0x02, 0x1B}, - {0x03, 0x22}, - {0x0b, 0x44}, - {0x0c, 0x1E}, - {0x0e, 0x12}, - {0x16, 0x04}, - }, - 0, - }, - { - { - {0x4e300100, 0x00051000}, - {0x4e300104, 0xF855000A}, - {0x4e300108, 0x6E620A48}, - {0x4e30010C, 0x0031010D}, - {0x4e300124, 0x04C50000}, - {0x4e300160, 0x00009100}, - {0x4e30016C, 0x30000000}, - {0x4e300170, 0x89090408}, - {0x4e300250, 0x00000007}, - {0x4e300254, 0x00240024}, - {0x4e300258, 0x00000008}, - {0x4e30025C, 0x00000400}, - }, - { - {0x01, 0x94}, - {0x02, 0x9}, - {0x03, 0x22}, - {0x0b, 0x44}, - {0x0c, 0x1E}, - {0x0e, 0x12}, - {0x16, 0x04}, - }, - 1, - }, - -}; - -/* PHY Initialize Configuration */ -static struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x0}, - {0x100a1, 0x1}, - {0x100a2, 0x2}, - {0x100a3, 0x3}, - {0x100a4, 0x4}, - {0x100a5, 0x5}, - {0x100a6, 0x6}, - {0x100a7, 0x7}, - {0x110a0, 0x0}, - {0x110a1, 0x1}, - {0x110a2, 0x2}, - {0x110a3, 0x3}, - {0x110a4, 0x4}, - {0x110a5, 0x5}, - {0x110a6, 0x6}, - {0x110a7, 0x7}, - {0x1005f, 0x5ff}, - {0x1015f, 0x5ff}, - {0x1105f, 0x5ff}, - {0x1115f, 0x5ff}, - {0x11005f, 0x5ff}, - {0x11015f, 0x5ff}, - {0x11105f, 0x5ff}, - {0x11115f, 0x5ff}, - {0x21005f, 0x5ff}, - {0x21015f, 0x5ff}, - {0x21105f, 0x5ff}, - {0x21115f, 0x5ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0xb}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1e3}, - {0x2003a, 0x2}, - {0x2007d, 0x212}, - {0x2007c, 0x61}, - {0x120024, 0x1e3}, - {0x2003a, 0x2}, - {0x12007d, 0x212}, - {0x12007c, 0x61}, - {0x220024, 0x1e3}, - {0x2003a, 0x2}, - {0x22007d, 0x212}, - {0x22007c, 0x61}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0x600}, - {0x1014d, 0x600}, - {0x1104d, 0x600}, - {0x1114d, 0x600}, - {0x11004d, 0x600}, - {0x11014d, 0x600}, - {0x11104d, 0x600}, - {0x11114d, 0x600}, - {0x21004d, 0x600}, - {0x21014d, 0x600}, - {0x21104d, 0x600}, - {0x21114d, 0x600}, - {0x10049, 0x604}, - {0x10149, 0x604}, - {0x11049, 0x604}, - {0x11149, 0x604}, - {0x110049, 0x604}, - {0x110149, 0x604}, - {0x111049, 0x604}, - {0x111149, 0x604}, - {0x210049, 0x604}, - {0x210149, 0x604}, - {0x211049, 0x604}, - {0x211149, 0x604}, - {0x43, 0x60}, - {0x1043, 0x60}, - {0x2043, 0x60}, - {0x20018, 0x1}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x2009b, 0x2}, - {0x20008, 0x3a5}, - {0x120008, 0x1d3}, - {0x220008, 0x9c}, - {0x20088, 0x9}, - {0x200b2, 0x104}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x1200b2, 0x104}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x2200b2, 0x104}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x200fa, 0x2}, - {0x1200fa, 0x2}, - {0x2200fa, 0x2}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x600}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5655}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x1004a, 0x500}, - {0x1104a, 0x500}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0x20021, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, -}; - -/* PHY trained csr */ -static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { - {0x1005f, 0x0}, - {0x1015f, 0x0}, - {0x1105f, 0x0}, - {0x1115f, 0x0}, - {0x11005f, 0x0}, - {0x11015f, 0x0}, - {0x11105f, 0x0}, - {0x11115f, 0x0}, - {0x21005f, 0x0}, - {0x21015f, 0x0}, - {0x21105f, 0x0}, - {0x21115f, 0x0}, - {0x55, 0x0}, - {0x1055, 0x0}, - {0x2055, 0x0}, - {0x200c5, 0x0}, - {0x1200c5, 0x0}, - {0x2200c5, 0x0}, - {0x2002e, 0x0}, - {0x12002e, 0x0}, - {0x22002e, 0x0}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x0}, - {0x2003a, 0x0}, - {0x2007d, 0x0}, - {0x2007c, 0x0}, - {0x120024, 0x0}, - {0x12007d, 0x0}, - {0x12007c, 0x0}, - {0x220024, 0x0}, - {0x22007d, 0x0}, - {0x22007c, 0x0}, - {0x20056, 0x0}, - {0x120056, 0x0}, - {0x220056, 0x0}, - {0x1004d, 0x0}, - {0x1014d, 0x0}, - {0x1104d, 0x0}, - {0x1114d, 0x0}, - {0x11004d, 0x0}, - {0x11014d, 0x0}, - {0x11104d, 0x0}, - {0x11114d, 0x0}, - {0x21004d, 0x0}, - {0x21014d, 0x0}, - {0x21104d, 0x0}, - {0x21114d, 0x0}, - {0x10049, 0x0}, - {0x10149, 0x0}, - {0x11049, 0x0}, - {0x11149, 0x0}, - {0x110049, 0x0}, - {0x110149, 0x0}, - {0x111049, 0x0}, - {0x111149, 0x0}, - {0x210049, 0x0}, - {0x210149, 0x0}, - {0x211049, 0x0}, - {0x211149, 0x0}, - {0x43, 0x0}, - {0x1043, 0x0}, - {0x2043, 0x0}, - {0x20018, 0x0}, - {0x20075, 0x0}, - {0x20050, 0x0}, - {0x2009b, 0x0}, - {0x20008, 0x0}, - {0x120008, 0x0}, - {0x220008, 0x0}, - {0x20088, 0x0}, - {0x200b2, 0x0}, - {0x10043, 0x0}, - {0x10143, 0x0}, - {0x11043, 0x0}, - {0x11143, 0x0}, - {0x1200b2, 0x0}, - {0x110043, 0x0}, - {0x110143, 0x0}, - {0x111043, 0x0}, - {0x111143, 0x0}, - {0x2200b2, 0x0}, - {0x210043, 0x0}, - {0x210143, 0x0}, - {0x211043, 0x0}, - {0x211143, 0x0}, - {0x200fa, 0x0}, - {0x1200fa, 0x0}, - {0x2200fa, 0x0}, - {0x20019, 0x0}, - {0x120019, 0x0}, - {0x220019, 0x0}, - {0x200f0, 0x0}, - {0x200f1, 0x0}, - {0x200f2, 0x0}, - {0x200f3, 0x0}, - {0x200f4, 0x0}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0x0}, - {0x1004a, 0x0}, - {0x1104a, 0x0}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x2002c, 0x0}, - {0xd0000, 0x0}, - {0x90000, 0x0}, - {0x90001, 0x0}, - {0x90002, 0x0}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x0}, - {0x90029, 0x0}, - {0x9002a, 0x0}, - {0x9002b, 0x0}, - {0x9002c, 0x0}, - {0x9002d, 0x0}, - {0x9002e, 0x0}, - {0x9002f, 0x0}, - {0x90030, 0x0}, - {0x90031, 0x0}, - {0x90032, 0x0}, - {0x90033, 0x0}, - {0x90034, 0x0}, - {0x90035, 0x0}, - {0x90036, 0x0}, - {0x90037, 0x0}, - {0x90038, 0x0}, - {0x90039, 0x0}, - {0x9003a, 0x0}, - {0x9003b, 0x0}, - {0x9003c, 0x0}, - {0x9003d, 0x0}, - {0x9003e, 0x0}, - {0x9003f, 0x0}, - {0x90040, 0x0}, - {0x90041, 0x0}, - {0x90042, 0x0}, - {0x90043, 0x0}, - {0x90044, 0x0}, - {0x90045, 0x0}, - {0x90046, 0x0}, - {0x90047, 0x0}, - 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{0x1100c0, 0x0}, - {0x1100c1, 0x0}, - {0x1101c0, 0x0}, - {0x1101c1, 0x0}, - {0x1102c0, 0x0}, - {0x1102c1, 0x0}, - {0x1103c0, 0x0}, - {0x1103c1, 0x0}, - {0x1104c0, 0x0}, - {0x1104c1, 0x0}, - {0x1105c0, 0x0}, - {0x1105c1, 0x0}, - {0x1106c0, 0x0}, - {0x1106c1, 0x0}, - {0x1107c0, 0x0}, - {0x1107c1, 0x0}, - {0x1108c0, 0x0}, - {0x1108c1, 0x0}, - {0x1100ae, 0x0}, - {0x1100af, 0x0}, - {0x111020, 0x0}, - {0x111080, 0x0}, - {0x111081, 0x0}, - {0x1110d0, 0x0}, - {0x1110d1, 0x0}, - {0x11108c, 0x0}, - {0x11108d, 0x0}, - {0x111180, 0x0}, - {0x111181, 0x0}, - {0x1111d0, 0x0}, - {0x1111d1, 0x0}, - {0x11118c, 0x0}, - {0x11118d, 0x0}, - {0x1110c0, 0x0}, - {0x1110c1, 0x0}, - {0x1111c0, 0x0}, - {0x1111c1, 0x0}, - {0x1112c0, 0x0}, - {0x1112c1, 0x0}, - {0x1113c0, 0x0}, - {0x1113c1, 0x0}, - {0x1114c0, 0x0}, - {0x1114c1, 0x0}, - {0x1115c0, 0x0}, - {0x1115c1, 0x0}, - {0x1116c0, 0x0}, - {0x1116c1, 0x0}, - {0x1117c0, 0x0}, - {0x1117c1, 0x0}, - {0x1118c0, 0x0}, - {0x1118c1, 0x0}, - {0x1110ae, 0x0}, - {0x1110af, 0x0}, - {0x190201, 0x0}, - {0x190202, 0x0}, - {0x190203, 0x0}, - {0x190205, 0x0}, - {0x190206, 0x0}, - {0x190207, 0x0}, - {0x190208, 0x0}, - {0x120020, 0x0}, - {0x200080, 0x0}, - {0x201080, 0x0}, - {0x202080, 0x0}, - {0x210020, 0x0}, - {0x210080, 0x0}, - {0x210081, 0x0}, - {0x2100d0, 0x0}, - {0x2100d1, 0x0}, - {0x21008c, 0x0}, - {0x21008d, 0x0}, - {0x210180, 0x0}, - {0x210181, 0x0}, - {0x2101d0, 0x0}, - {0x2101d1, 0x0}, - {0x21018c, 0x0}, - {0x21018d, 0x0}, - {0x2100c0, 0x0}, - {0x2100c1, 0x0}, - {0x2101c0, 0x0}, - {0x2101c1, 0x0}, - {0x2102c0, 0x0}, - {0x2102c1, 0x0}, - {0x2103c0, 0x0}, - {0x2103c1, 0x0}, - {0x2104c0, 0x0}, - {0x2104c1, 0x0}, - {0x2105c0, 0x0}, - {0x2105c1, 0x0}, - {0x2106c0, 0x0}, - {0x2106c1, 0x0}, - {0x2107c0, 0x0}, - {0x2107c1, 0x0}, - {0x2108c0, 0x0}, - {0x2108c1, 0x0}, - {0x2100ae, 0x0}, - {0x2100af, 0x0}, - {0x211020, 0x0}, - {0x211080, 0x0}, - {0x211081, 0x0}, - {0x2110d0, 0x0}, - {0x2110d1, 0x0}, - {0x21108c, 0x0}, - {0x21108d, 0x0}, - {0x211180, 0x0}, - {0x211181, 0x0}, - {0x2111d0, 0x0}, - {0x2111d1, 0x0}, - {0x21118c, 0x0}, - {0x21118d, 0x0}, - {0x2110c0, 0x0}, - {0x2110c1, 0x0}, - {0x2111c0, 0x0}, - {0x2111c1, 0x0}, - {0x2112c0, 0x0}, - {0x2112c1, 0x0}, - {0x2113c0, 0x0}, - {0x2113c1, 0x0}, - {0x2114c0, 0x0}, - {0x2114c1, 0x0}, - {0x2115c0, 0x0}, - {0x2115c1, 0x0}, - {0x2116c0, 0x0}, - {0x2116c1, 0x0}, - {0x2117c0, 0x0}, - {0x2117c1, 0x0}, - {0x2118c0, 0x0}, - {0x2118c1, 0x0}, - {0x2110ae, 0x0}, - {0x2110af, 0x0}, - {0x290201, 0x0}, - {0x290202, 0x0}, - {0x290203, 0x0}, - {0x290205, 0x0}, - {0x290206, 0x0}, - {0x290207, 0x0}, - {0x290208, 0x0}, - {0x220020, 0x0}, - {0x20077, 0x0}, - {0x20072, 0x0}, - {0x20073, 0x0}, - {0x400c0, 0x0}, - {0x10040, 0x0}, - {0x10140, 0x0}, - {0x10240, 0x0}, - {0x10340, 0x0}, - {0x10440, 0x0}, - {0x10540, 0x0}, - {0x10640, 0x0}, - {0x10740, 0x0}, - {0x10840, 0x0}, - {0x11040, 0x0}, - {0x11140, 0x0}, - {0x11240, 0x0}, - {0x11340, 0x0}, - {0x11440, 0x0}, - {0x11540, 0x0}, - {0x11640, 0x0}, - {0x11740, 0x0}, - {0x11840, 0x0}, -}; - -/* P0 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x14}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x22}, - {0x5401b, 0x1e44}, - {0x5401c, 0x1208}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x22}, - {0x54021, 0x1e44}, - {0x54022, 0x1208}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x2236}, - {0x54034, 0x4400}, - {0x54035, 0x81e}, - {0x54036, 0x12}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x2236}, - {0x5403a, 0x4400}, - {0x5403b, 0x81e}, - {0x5403c, 0x12}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P1 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x1}, - {0x54003, 0x74a}, - {0x54004, 0x4}, - {0x54006, 0x14}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x1bb4}, - {0x5401a, 0x22}, - {0x5401b, 0x1e44}, - {0x5401c, 0x1208}, - {0x5401e, 0x4}, - {0x5401f, 0x1bb4}, - {0x54020, 0x22}, - {0x54021, 0x1e44}, - {0x54022, 0x1208}, - {0x54024, 0x4}, - {0x54032, 0xb400}, - {0x54033, 0x221b}, - {0x54034, 0x4400}, - {0x54035, 0x81e}, - {0x54036, 0x12}, - {0x54037, 0x400}, - {0x54038, 0xb400}, - {0x54039, 0x221b}, - {0x5403a, 0x4400}, - {0x5403b, 0x81e}, - {0x5403c, 0x12}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P2 message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x270}, - {0x54004, 0x4}, - {0x54006, 0x14}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54012, 0x110}, - {0x54019, 0x994}, - {0x5401a, 0x22}, - {0x5401b, 0x1e44}, - {0x5401c, 0x1200}, - {0x5401e, 0x4}, - {0x5401f, 0x994}, - {0x54020, 0x22}, - {0x54021, 0x1e44}, - {0x54022, 0x1200}, - {0x54024, 0x4}, - {0x54032, 0x9400}, - {0x54033, 0x2209}, - {0x54034, 0x4400}, - {0x54035, 0x1e}, - {0x54036, 0x12}, - {0x54037, 0x400}, - {0x54038, 0x9400}, - {0x54039, 0x2209}, - {0x5403a, 0x4400}, - {0x5403b, 0x1e}, - {0x5403c, 0x12}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* P0 2D message block parameter for training firmware */ -static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xe94}, - {0x54004, 0x4}, - {0x54006, 0x14}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x4}, - {0x5400d, 0x100}, - {0x5400f, 0x100}, - {0x54010, 0x2080}, - {0x54012, 0x110}, - {0x54019, 0x36e4}, - {0x5401a, 0x22}, - {0x5401b, 0x1e44}, - {0x5401c, 0x1208}, - {0x5401e, 0x4}, - {0x5401f, 0x36e4}, - {0x54020, 0x22}, - {0x54021, 0x1e44}, - {0x54022, 0x1208}, - {0x54024, 0x4}, - {0x54032, 0xe400}, - {0x54033, 0x2236}, - {0x54034, 0x4400}, - {0x54035, 0x81e}, - {0x54036, 0x12}, - {0x54037, 0x400}, - {0x54038, 0xe400}, - {0x54039, 0x2236}, - {0x5403a, 0x4400}, - {0x5403b, 0x81e}, - {0x5403c, 0x12}, - {0x5403d, 0x400}, - {0xd0000, 0x1} -}; - -/* DRAM PHY init engine image */ -static struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xb}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x633}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x633}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x633}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x30}, - {0x90051, 0x65a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x45a}, - {0x90055, 0x9}, - {0x90056, 0x0}, - {0x90057, 0x448}, - {0x90058, 0x109}, - {0x90059, 0x40}, - {0x9005a, 0x633}, - {0x9005b, 0x179}, - {0x9005c, 0x1}, - {0x9005d, 0x618}, - {0x9005e, 0x109}, - {0x9005f, 0x40c0}, - {0x90060, 0x633}, - {0x90061, 0x149}, - {0x90062, 0x8}, - {0x90063, 0x4}, - {0x90064, 0x48}, - {0x90065, 0x4040}, - {0x90066, 0x633}, - {0x90067, 0x149}, - {0x90068, 0x0}, - {0x90069, 0x4}, - {0x9006a, 0x48}, - {0x9006b, 0x40}, - {0x9006c, 0x633}, - {0x9006d, 0x149}, - {0x9006e, 0x0}, - {0x9006f, 0x658}, - {0x90070, 0x109}, - {0x90071, 0x10}, - {0x90072, 0x4}, - {0x90073, 0x18}, - {0x90074, 0x0}, - {0x90075, 0x4}, - {0x90076, 0x78}, - {0x90077, 0x549}, - {0x90078, 0x633}, - {0x90079, 0x159}, - {0x9007a, 0xd49}, - {0x9007b, 0x633}, - {0x9007c, 0x159}, - {0x9007d, 0x94a}, - {0x9007e, 0x633}, - {0x9007f, 0x159}, - {0x90080, 0x441}, - {0x90081, 0x633}, - {0x90082, 0x149}, - {0x90083, 0x42}, - {0x90084, 0x633}, - {0x90085, 0x149}, - {0x90086, 0x1}, - {0x90087, 0x633}, - {0x90088, 0x149}, - {0x90089, 0x0}, - {0x9008a, 0xe0}, - {0x9008b, 0x109}, - {0x9008c, 0xa}, - {0x9008d, 0x10}, - {0x9008e, 0x109}, - {0x9008f, 0x9}, - {0x90090, 0x3c0}, - {0x90091, 0x149}, - {0x90092, 0x9}, - {0x90093, 0x3c0}, - {0x90094, 0x159}, - {0x90095, 0x18}, - {0x90096, 0x10}, - {0x90097, 0x109}, - {0x90098, 0x0}, - {0x90099, 0x3c0}, - {0x9009a, 0x109}, - {0x9009b, 0x18}, - {0x9009c, 0x4}, - {0x9009d, 0x48}, - {0x9009e, 0x18}, - {0x9009f, 0x4}, - {0x900a0, 0x58}, - {0x900a1, 0xb}, - {0x900a2, 0x10}, - {0x900a3, 0x109}, - {0x900a4, 0x1}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x900a7, 0x5}, - {0x900a8, 0x7c0}, - {0x900a9, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x625}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x625}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900aa, 0x0}, - {0x900ab, 0x790}, - {0x900ac, 0x11a}, - {0x900ad, 0x8}, - {0x900ae, 0x7aa}, - {0x900af, 0x2a}, - {0x900b0, 0x10}, - {0x900b1, 0x7b2}, - {0x900b2, 0x2a}, - {0x900b3, 0x0}, - {0x900b4, 0x7c8}, - {0x900b5, 0x109}, - {0x900b6, 0x10}, - {0x900b7, 0x10}, - {0x900b8, 0x109}, - {0x900b9, 0x10}, - {0x900ba, 0x2a8}, - {0x900bb, 0x129}, - {0x900bc, 0x8}, - {0x900bd, 0x370}, - {0x900be, 0x129}, - {0x900bf, 0xa}, - {0x900c0, 0x3c8}, - {0x900c1, 0x1a9}, - {0x900c2, 0xc}, - {0x900c3, 0x408}, - {0x900c4, 0x199}, - {0x900c5, 0x14}, - {0x900c6, 0x790}, - {0x900c7, 0x11a}, - {0x900c8, 0x8}, - {0x900c9, 0x4}, - {0x900ca, 0x18}, - {0x900cb, 0xe}, - {0x900cc, 0x408}, - {0x900cd, 0x199}, - {0x900ce, 0x8}, - {0x900cf, 0x8568}, - {0x900d0, 0x108}, - {0x900d1, 0x18}, - {0x900d2, 0x790}, - {0x900d3, 0x16a}, - {0x900d4, 0x8}, - {0x900d5, 0x1d8}, - {0x900d6, 0x169}, - {0x900d7, 0x10}, - {0x900d8, 0x8558}, - {0x900d9, 0x168}, - {0x900da, 0x1ff8}, - {0x900db, 0x85a8}, - {0x900dc, 0x1e8}, - {0x900dd, 0x50}, - {0x900de, 0x798}, - {0x900df, 0x16a}, - {0x900e0, 0x60}, - {0x900e1, 0x7a0}, - {0x900e2, 0x16a}, - {0x900e3, 0x8}, - {0x900e4, 0x8310}, - {0x900e5, 0x168}, - {0x900e6, 0x8}, - {0x900e7, 0xa310}, - {0x900e8, 0x168}, - {0x900e9, 0xa}, - {0x900ea, 0x408}, - {0x900eb, 0x169}, - {0x900ec, 0x6e}, - {0x900ed, 0x0}, - {0x900ee, 0x68}, - {0x900ef, 0x0}, - {0x900f0, 0x408}, - {0x900f1, 0x169}, - {0x900f2, 0x0}, - {0x900f3, 0x8310}, - {0x900f4, 0x168}, - {0x900f5, 0x0}, - {0x900f6, 0xa310}, - {0x900f7, 0x168}, - {0x900f8, 0x1ff8}, - {0x900f9, 0x85a8}, - {0x900fa, 0x1e8}, - {0x900fb, 0x68}, - {0x900fc, 0x798}, - {0x900fd, 0x16a}, - {0x900fe, 0x78}, - {0x900ff, 0x7a0}, - {0x90100, 0x16a}, - {0x90101, 0x68}, - {0x90102, 0x790}, - {0x90103, 0x16a}, - {0x90104, 0x8}, - {0x90105, 0x8b10}, - {0x90106, 0x168}, - {0x90107, 0x8}, - {0x90108, 0xab10}, - {0x90109, 0x168}, - {0x9010a, 0xa}, - {0x9010b, 0x408}, - {0x9010c, 0x169}, - {0x9010d, 0x58}, - {0x9010e, 0x0}, - {0x9010f, 0x68}, - {0x90110, 0x0}, - {0x90111, 0x408}, - {0x90112, 0x169}, - {0x90113, 0x0}, - {0x90114, 0x8b10}, - {0x90115, 0x168}, - {0x90116, 0x1}, - {0x90117, 0xab10}, - {0x90118, 0x168}, - {0x90119, 0x0}, - {0x9011a, 0x1d8}, - {0x9011b, 0x169}, - {0x9011c, 0x80}, - {0x9011d, 0x790}, - {0x9011e, 0x16a}, - {0x9011f, 0x18}, - {0x90120, 0x7aa}, - {0x90121, 0x6a}, - {0x90122, 0xa}, - {0x90123, 0x0}, - {0x90124, 0x1e9}, - {0x90125, 0x8}, - {0x90126, 0x8080}, - {0x90127, 0x108}, - {0x90128, 0xf}, - {0x90129, 0x408}, - {0x9012a, 0x169}, - {0x9012b, 0xc}, - {0x9012c, 0x0}, - {0x9012d, 0x68}, - {0x9012e, 0x9}, - {0x9012f, 0x0}, - {0x90130, 0x1a9}, - {0x90131, 0x0}, - {0x90132, 0x408}, - {0x90133, 0x169}, - {0x90134, 0x0}, - {0x90135, 0x8080}, - {0x90136, 0x108}, - {0x90137, 0x8}, - {0x90138, 0x7aa}, - {0x90139, 0x6a}, - {0x9013a, 0x0}, - {0x9013b, 0x8568}, - {0x9013c, 0x108}, - {0x9013d, 0xb7}, - {0x9013e, 0x790}, - {0x9013f, 0x16a}, - {0x90140, 0x1f}, - {0x90141, 0x0}, - {0x90142, 0x68}, - {0x90143, 0x8}, - {0x90144, 0x8558}, - {0x90145, 0x168}, - {0x90146, 0xf}, - {0x90147, 0x408}, - {0x90148, 0x169}, - {0x90149, 0xd}, - {0x9014a, 0x0}, - {0x9014b, 0x68}, - {0x9014c, 0x0}, - {0x9014d, 0x408}, - {0x9014e, 0x169}, - {0x9014f, 0x0}, - {0x90150, 0x8558}, - {0x90151, 0x168}, - {0x90152, 0x8}, - {0x90153, 0x3c8}, - {0x90154, 0x1a9}, - {0x90155, 0x3}, - {0x90156, 0x370}, - {0x90157, 0x129}, - {0x90158, 0x20}, - {0x90159, 0x2aa}, - {0x9015a, 0x9}, - {0x9015b, 0x8}, - {0x9015c, 0xe8}, - {0x9015d, 0x109}, - {0x9015e, 0x0}, - {0x9015f, 0x8140}, - {0x90160, 0x10c}, - {0x90161, 0x10}, - {0x90162, 0x8138}, - {0x90163, 0x104}, - {0x90164, 0x8}, - {0x90165, 0x448}, - {0x90166, 0x109}, - {0x90167, 0xf}, - {0x90168, 0x7c0}, - {0x90169, 0x109}, - {0x9016a, 0x0}, - {0x9016b, 0xe8}, - {0x9016c, 0x109}, - {0x9016d, 0x47}, - {0x9016e, 0x630}, - {0x9016f, 0x109}, - {0x90170, 0x8}, - {0x90171, 0x618}, - {0x90172, 0x109}, - {0x90173, 0x8}, - {0x90174, 0xe0}, - {0x90175, 0x109}, - {0x90176, 0x0}, - {0x90177, 0x7c8}, - {0x90178, 0x109}, - {0x90179, 0x8}, - {0x9017a, 0x8140}, - {0x9017b, 0x10c}, - {0x9017c, 0x0}, - {0x9017d, 0x478}, - {0x9017e, 0x109}, - {0x9017f, 0x0}, - {0x90180, 0x1}, - {0x90181, 0x8}, - {0x90182, 0x8}, - {0x90183, 0x4}, - {0x90184, 0x0}, - {0x90006, 0x8}, - {0x90007, 0x7c8}, - {0x90008, 0x109}, - {0x90009, 0x0}, - {0x9000a, 0x400}, - {0x9000b, 0x106}, - {0xd00e7, 0x400}, - {0x90017, 0x0}, - {0x9001f, 0x2b}, - {0x90026, 0x69}, - {0x400d0, 0x0}, - {0x400d1, 0x101}, - {0x400d2, 0x105}, - {0x400d3, 0x107}, - {0x400d4, 0x10f}, - {0x400d5, 0x202}, - {0x400d6, 0x20a}, - {0x400d7, 0x20b}, - {0x2003a, 0x2}, - {0x200be, 0x3}, - {0x2000b, 0x41a}, - {0x2000c, 0xe9}, - {0x2000d, 0x91c}, - {0x2000e, 0x2c}, - {0x12000b, 0x20d}, - {0x12000c, 0x74}, - {0x12000d, 0x48e}, - {0x12000e, 0x2c}, - {0x22000b, 0xb0}, - {0x22000c, 0x27}, - {0x22000d, 0x186}, - {0x22000e, 0x10}, - {0x9000c, 0x0}, - {0x9000d, 0x173}, - {0x9000e, 0x60}, - {0x9000f, 0x6110}, - {0x90010, 0x2152}, - {0x90011, 0xdfbd}, - {0x90012, 0x2060}, - {0x90013, 0x6152}, - {0x20010, 0x5a}, - {0x20011, 0x3}, - {0x120010, 0x5a}, - {0x120011, 0x3}, - {0x40080, 0xe0}, - {0x40081, 0x12}, - {0x40082, 0xe0}, - {0x40083, 0x12}, - {0x40084, 0xe0}, - {0x40085, 0x12}, - {0x140080, 0xe0}, - {0x140081, 0x12}, - {0x140082, 0xe0}, - {0x140083, 0x12}, - {0x140084, 0xe0}, - {0x140085, 0x12}, - {0x240080, 0xe0}, - {0x240081, 0x12}, - {0x240082, 0xe0}, - {0x240083, 0x12}, - {0x240084, 0xe0}, - {0x240085, 0x12}, - {0x400fd, 0xf}, - {0x400f1, 0xe}, - {0x10011, 0x1}, - {0x10012, 0x1}, - {0x10013, 0x180}, - {0x10018, 0x1}, - {0x10002, 0x6209}, - {0x100b2, 0x1}, - {0x101b4, 0x1}, - {0x102b4, 0x1}, - {0x103b4, 0x1}, - {0x104b4, 0x1}, - {0x105b4, 0x1}, - {0x106b4, 0x1}, - {0x107b4, 0x1}, - {0x108b4, 0x1}, - {0x11011, 0x1}, - {0x11012, 0x1}, - {0x11013, 0x180}, - {0x11018, 0x1}, - {0x11002, 0x6209}, - {0x110b2, 0x1}, - {0x111b4, 0x1}, - {0x112b4, 0x1}, - {0x113b4, 0x1}, - {0x114b4, 0x1}, - {0x115b4, 0x1}, - {0x116b4, 0x1}, - {0x117b4, 0x1}, - {0x118b4, 0x1}, - {0x20089, 0x1}, - {0x20088, 0x19}, - {0xc0080, 0x0}, - {0xd0000, 0x1}, -}; - -static struct dram_fsp_msg ddr_dram_fsp_msg[] = { - { - /* P0 3733mts 1D */ - .drate = 3733, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp0_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), - }, - { - /* P1 1866mts 1D */ - .drate = 1866, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp1_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), - }, - { - /* P2 625mts 1D */ - .drate = 625, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, - { - /* P0 3733mts 2D */ - .drate = 3733, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = ddr_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), - }, -}; - -/* ddr timing config params */ -struct dram_timing_info dram_timing = { - .ddrc_cfg = ddr_ddrc_cfg, - .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), - .ddrphy_cfg = ddr_ddrphy_cfg, - .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), - .fsp_msg = ddr_dram_fsp_msg, - .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), - .ddrphy_trained_csr = ddr_ddrphy_trained_csr, - .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), - .ddrphy_pie = ddr_phy_pie, - .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3733, 1866, 625, }, - .fsp_cfg = ddr_dram_fsp_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), -}; - -void set_dram_timings_2gb_lpddr4x(void) -{ - /* Initialize DDRC registers */ - dram_timing.ddrc_cfg[1].val = 0x8000ff; - dram_timing.ddrc_cfg[3].val = 0x80000512; - - /* dram fsp cfg */ - dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x24AB321B; - dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x2F2EE233; - dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x015B015B; - dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x015B2213; - dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x13; - - dram_timing.fsp_cfg[1].ddrc_cfg[0].val = 0x12552100; - dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x1816B4AA; - dram_timing.fsp_cfg[1].ddrc_cfg[9].val = 0x00AA00AA; - dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x13; - - dram_timing.fsp_cfg[2].ddrc_cfg[0].val = 0x00061000; - dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E62FA48; - dram_timing.fsp_cfg[2].ddrc_cfg[9].val = 0x00340034; - dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x13; - - /* P0 message block parameter for training firmware */ - dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; - dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1308; - dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; - dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1308; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; - dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x13; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; - dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x13; - - /* P1 message block parameter for training firmware */ - dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1308; - dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1308; - dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; - dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x13; - dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; - dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x13; - - /* P2 message block parameter for training firmware */ - dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1300; - dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1300; - dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; - dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x13; - dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; - dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x13; - - /* P0 2D message block parameter for training firmware */ - dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1308; - dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1308; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; - dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x13; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; - dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x13; -} - -/* Generated with DDR Tool v3.3.0_7.8-d1cdb7d3 */ -void set_dram_timings_1gb_lpddr4x_900mhz(void) -{ - /* Initialize DDRC registers */ - dram_timing.ddrc_cfg[6].val = 0x4080; - - /* dram fsp cfg */ - dram_timing.fsp_cfg[0].ddrc_cfg[0].val = 0x124F2100; - dram_timing.fsp_cfg[0].ddrc_cfg[1].val = 0xF877000E; - dram_timing.fsp_cfg[0].ddrc_cfg[2].val = 0x181AE4AA; - dram_timing.fsp_cfg[0].ddrc_cfg[3].val = 0x005101E6; - dram_timing.fsp_cfg[0].ddrc_cfg[4].val = 0x0E3C0000; - dram_timing.fsp_cfg[0].ddrc_cfg[5].val = 0x00009101; - dram_timing.fsp_cfg[0].ddrc_cfg[6].val = 0x30900000; - dram_timing.fsp_cfg[0].ddrc_cfg[7].val = 0x8A0A0508; - dram_timing.fsp_cfg[0].ddrc_cfg[8].val = 0x00000014; - dram_timing.fsp_cfg[0].ddrc_cfg[9].val = 0x007B007B; - dram_timing.fsp_cfg[0].ddrc_cfg[12].val = 0x1128110B; - dram_timing.fsp_cfg[0].ddrc_cfg[13].val = 0x007B140A; - dram_timing.fsp_cfg[0].ddrc_cfg[14].val = 0x0620071E; - dram_timing.fsp_cfg[0].mr_cfg[0].val = 0xB4; - dram_timing.fsp_cfg[0].mr_cfg[1].val = 0x1B; - dram_timing.fsp_cfg[0].mr_cfg[2].val = 0xE2; - dram_timing.fsp_cfg[0].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[0].mr_cfg[5].val = 0x15; - - dram_timing.fsp_cfg[1].ddrc_cfg[2].val = 0x181AE4AA; - dram_timing.fsp_cfg[1].mr_cfg[2].val = 0xE2; - dram_timing.fsp_cfg[1].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[1].mr_cfg[5].val = 0x15; - - dram_timing.fsp_cfg[2].ddrc_cfg[2].val = 0x6E660A48; - dram_timing.fsp_cfg[2].mr_cfg[2].val = 0xE2; - dram_timing.fsp_cfg[2].mr_cfg[4].val = 0x20; - dram_timing.fsp_cfg[2].mr_cfg[5].val = 0x15; - - /* PHY Initialize Configuration */ - dram_timing.ddrphy_cfg[31].val = 0xb; - dram_timing.ddrphy_cfg[86].val = 0x1d3; - dram_timing.ddrphy_cfg[90].val = 0x10c; - dram_timing.ddrphy_cfg[95].val = 0x10c; - dram_timing.ddrphy_cfg[100].val = 0x10c; - dram_timing.ddrphy_cfg[122].val = 0x1; - /** - * NOTE: - * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 119 - * (reg=0x1004a, val=0x500) and 120 (reg=0x1104a, val=0x500) are not - * present in the ddr_ddrphy_cfg array. However they were present in array - * generated with previous DDR Tool v3.1.0_7.4. We simply set both values - * to default value of 0x400 (read with dwc_ddrphy_apb_rd()) here to avoid - * any negative side-effects. - */ - dram_timing.ddrphy_cfg[119].val = 0x400; - dram_timing.ddrphy_cfg[120].val = 0x400; - - /** - * NOTE: - * In the output from DDR Tool v3.3.0_7.8-d1cdb7d3, array members 101 - * (reg=0x1004a, val=0x0) and 120 (reg=0x1104a, val=0x0) are not present - * in the ddr_ddrphy_trained_csr array. However they were present in array - * generated with previous DDR Tool v3.1.0_7.4. We simply set both values - * to default 0x0 (like all other ddrphy_trained_csr values) here to avoid - * any negative side-effects. - */ - /* PHY trained csr */ - dram_timing.ddrphy_trained_csr[101].val = 0x0; - dram_timing.ddrphy_trained_csr[102].val = 0x0; - - /* P0 message block parameter for training firmware */ - dram_timing.fsp_msg[0].fsp_cfg[1].val = 0x74a; - dram_timing.fsp_msg[0].fsp_cfg[3].val = 0x15; - dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x1bb4; - dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xe2; - dram_timing.fsp_msg[0].fsp_cfg[12].val = 0x2044; - dram_timing.fsp_msg[0].fsp_cfg[13].val = 0x1508; - dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x1bb4; - dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xe2; - dram_timing.fsp_msg[0].fsp_cfg[17].val = 0x2044; - dram_timing.fsp_msg[0].fsp_cfg[18].val = 0x1508; - dram_timing.fsp_msg[0].fsp_cfg[20].val = 0xb400; - dram_timing.fsp_msg[0].fsp_cfg[21].val = 0xe21b; - dram_timing.fsp_msg[0].fsp_cfg[23].val = 0x820; - dram_timing.fsp_msg[0].fsp_cfg[24].val = 0x15; - dram_timing.fsp_msg[0].fsp_cfg[26].val = 0xb400; - dram_timing.fsp_msg[0].fsp_cfg[27].val = 0xe21b; - dram_timing.fsp_msg[0].fsp_cfg[29].val = 0x820; - dram_timing.fsp_msg[0].fsp_cfg[30].val = 0x15; - - /* P1 message block parameter for training firmware */ - dram_timing.fsp_msg[1].fsp_cfg[4].val = 0x15; - dram_timing.fsp_msg[1].fsp_cfg[12].val = 0xe2; - dram_timing.fsp_msg[1].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[1].fsp_cfg[14].val = 0x1508; - dram_timing.fsp_msg[1].fsp_cfg[17].val = 0xe2; - dram_timing.fsp_msg[1].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[1].fsp_cfg[19].val = 0x1508; - dram_timing.fsp_msg[1].fsp_cfg[22].val = 0xe21b; - dram_timing.fsp_msg[1].fsp_cfg[24].val = 0x820; - dram_timing.fsp_msg[1].fsp_cfg[25].val = 0x15; - dram_timing.fsp_msg[1].fsp_cfg[28].val = 0xe21b; - dram_timing.fsp_msg[1].fsp_cfg[30].val = 0x820; - dram_timing.fsp_msg[1].fsp_cfg[31].val = 0x15; - - /* P2 message block parameter for training firmware */ - dram_timing.fsp_msg[2].fsp_cfg[4].val = 0x15; - dram_timing.fsp_msg[2].fsp_cfg[12].val = 0xe2; - dram_timing.fsp_msg[2].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[2].fsp_cfg[14].val = 0x1500; - dram_timing.fsp_msg[2].fsp_cfg[17].val = 0xe2; - dram_timing.fsp_msg[2].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[2].fsp_cfg[19].val = 0x1500; - dram_timing.fsp_msg[2].fsp_cfg[22].val = 0xe209; - dram_timing.fsp_msg[2].fsp_cfg[24].val = 0x20; - dram_timing.fsp_msg[2].fsp_cfg[25].val = 0x15; - dram_timing.fsp_msg[2].fsp_cfg[28].val = 0xe209; - dram_timing.fsp_msg[2].fsp_cfg[30].val = 0x20; - dram_timing.fsp_msg[2].fsp_cfg[31].val = 0x15; - - /* P0 2D message block parameter for training firmware */ - dram_timing.fsp_msg[3].fsp_cfg[1].val = 0x74a; - dram_timing.fsp_msg[3].fsp_cfg[3].val = 0x15; - dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x1bb4; - dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xe2; - dram_timing.fsp_msg[3].fsp_cfg[13].val = 0x2044; - dram_timing.fsp_msg[3].fsp_cfg[14].val = 0x1508; - dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x1bb4; - dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xe2; - dram_timing.fsp_msg[3].fsp_cfg[18].val = 0x2044; - dram_timing.fsp_msg[3].fsp_cfg[19].val = 0x1508; - dram_timing.fsp_msg[3].fsp_cfg[21].val = 0xb400; - dram_timing.fsp_msg[3].fsp_cfg[22].val = 0xe21b; - dram_timing.fsp_msg[3].fsp_cfg[24].val = 0x820; - dram_timing.fsp_msg[3].fsp_cfg[25].val = 0x15; - dram_timing.fsp_msg[3].fsp_cfg[27].val = 0xb400; - dram_timing.fsp_msg[3].fsp_cfg[28].val = 0xe21b; - dram_timing.fsp_msg[3].fsp_cfg[30].val = 0x820; - dram_timing.fsp_msg[3].fsp_cfg[31].val = 0x15; - - /* DRAM PHY init engine image */ - dram_timing.ddrphy_pie[483].val = 0x20d; - dram_timing.ddrphy_pie[484].val = 0x74; - dram_timing.ddrphy_pie[485].val = 0x48e; - - /* P0 3733mts 1D */ - dram_timing.fsp_msg[0].drate = 1866; - - /* P0 1866mts 2D */ - dram_timing.fsp_msg[3].drate = 1866; - - /* ddr timing config params */ - dram_timing.fsp_table[0] = 1866; -} diff --git a/board/phytec/phycore_imx93/phycore-imx93.c b/board/phytec/phycore_imx93/phycore-imx93.c deleted file mode 100644 index 036c9f5de7e..00000000000 --- a/board/phytec/phycore_imx93/phycore-imx93.c +++ /dev/null @@ -1,103 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Christoph Stoidner - * Copyright (C) 2024 Mathieu Othacehe - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - */ - -#include -#include -#include -#include - -#include "../common/imx93_som_detection.h" - -#define EEPROM_ADDR 0x50 - -int board_init(void) -{ - int ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); - - if (ret) - printf("%s: EEPROM data init failed\n", __func__); - - return 0; -} - -int board_mmc_get_env_dev(int devno) -{ - return devno; -} - -int board_late_init(void) -{ - switch (get_boot_device()) { - case SD2_BOOT: - env_set_ulong("mmcdev", 1); - if (!env_get("boot_targets")) - env_set("boot_targets", "mmc1 mmc0 ethernet"); - break; - case MMC1_BOOT: - env_set_ulong("mmcdev", 0); - break; - case USB_BOOT: - printf("Detect USB boot. Will enter fastboot mode!\n"); - if (!strcmp(env_get("bootcmd"), env_get_default("bootcmd"))) - env_set("bootcmd", "fastboot 0; bootflow scan -lb;"); - break; - default: - break; - } - - return 0; -} - -static void emmc_fixup(void *blob, struct phytec_eeprom_data *data) -{ - enum phytec_imx93_voltage voltage = phytec_imx93_get_voltage(data); - int offset; - - if (voltage == PHYTEC_IMX93_VOLTAGE_INVALID) - goto err; - - if (voltage == PHYTEC_IMX93_VOLTAGE_1V8) { - offset = fdt_node_offset_by_compat_reg(blob, "fsl,imx93-usdhc", - 0x42850000); - if (offset) - fdt_delprop(blob, offset, "no-1-8-v"); - else - goto err; - } - - return; -err: - printf("Could not detect eMMC VDD-IO. Fall back to default.\n"); -} - -int board_fix_fdt(void *blob) -{ - struct phytec_eeprom_data data; - - phytec_eeprom_data_setup(&data, 2, EEPROM_ADDR); - - emmc_fixup(blob, &data); - - /* Update dtb clocks for low drive mode */ - if (is_voltage_mode(VOLT_LOW_DRIVE)) - low_drive_freq_update(blob); - - return 0; -} - -int ft_board_setup(void *blob, struct bd_info *bd) -{ - emmc_fixup(blob, NULL); - - /** - * NOTE: VOLT_LOW_DRIVE fixup is done by the ft_system_setup() - * in arch/arm/mach-imx/imx9/soc.c for Linux device-tree. - */ - - return 0; -} diff --git a/board/phytec/phycore_imx93/phycore_imx93.env b/board/phytec/phycore_imx93/phycore_imx93.env deleted file mode 100644 index c8fb3a875da..00000000000 --- a/board/phytec/phycore_imx93/phycore_imx93.env +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ - -boot_script_dhcp=net_boot_fit.scr.uimg -console=ttyLP0 -emmc_dev=0 /* This is needed by built-in uuu flash scripts */ -fdt_addr_r=0x90000000 -fdtfile=DEFAULT_FDT_FILE -fdtoverlay_addr_r=0x900c0000 -ip_dyn=yes -kernel_addr_r=0x88000000 -nfsroot=/srv/nfs -prepare_mcore=setenv optargs "${optargs} clk-imx93.mcore_booted" -scriptaddr=0x83500000 -sd_dev=1 /* This is needed by built-in uuu flash scripts */ diff --git a/board/phytec/phycore_imx93/spl.c b/board/phytec/phycore_imx93/spl.c deleted file mode 100644 index aa7d562911a..00000000000 --- a/board/phytec/phycore_imx93/spl.c +++ /dev/null @@ -1,194 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Author: Christoph Stoidner - * Copyright (C) 2024 Mathieu Othacehe - * Copyright (C) 2024 PHYTEC Messtechnik GmbH - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../common/imx93_som_detection.h" - -DECLARE_GLOBAL_DATA_PTR; - -#define EEPROM_ADDR 0x50 - -/* - * Prototypes of automatically generated ram config file - */ -void set_dram_timings_2gb_lpddr4x(void); -void set_dram_timings_1gb_lpddr4x_900mhz(void); - -int spl_board_boot_device(enum boot_device boot_dev_spl) -{ - return BOOT_DEVICE_BOOTROM; -} - -void spl_board_init(void) -{ - int ret; - - ret = ele_start_rng(); - if (ret) - printf("Fail to start RNG: %d\n", ret); - - puts("Normal Boot\n"); -} - -void spl_dram_init(void) -{ - int ret; - enum phytec_imx93_ddr_eeprom_code ddr_opt = PHYTEC_IMX93_DDR_INVALID; - - ret = phytec_eeprom_data_setup(NULL, CONFIG_PHYTEC_EEPROM_BUS, EEPROM_ADDR); - if (ret && !IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) - goto out; - - ret = phytec_imx93_detect(NULL); - if (!ret) - phytec_print_som_info(NULL); - - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_FIX)) { - if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_1GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_1GB; - else if (IS_ENABLED(CONFIG_PHYCORE_IMX93_RAM_TYPE_LPDDR4X_2GB)) - ddr_opt = PHYTEC_IMX93_LPDDR4X_2GB; - } else { - ddr_opt = phytec_imx93_get_opt(NULL, PHYTEC_IMX93_OPT_DDR); - } - - switch (ddr_opt) { - case PHYTEC_IMX93_LPDDR4X_1GB: - if (is_voltage_mode(VOLT_LOW_DRIVE)) - set_dram_timings_1gb_lpddr4x_900mhz(); - break; - case PHYTEC_IMX93_LPDDR4X_2GB: - set_dram_timings_2gb_lpddr4x(); - break; - default: - goto out; - } - ddr_init(&dram_timing); - return; -out: - puts("Could not detect correct RAM type and size. Fall back to default.\n"); - if (is_voltage_mode(VOLT_LOW_DRIVE)) - set_dram_timings_1gb_lpddr4x_900mhz(); - ddr_init(&dram_timing); -} - -int power_init_board(void) -{ - struct udevice *dev; - int ret; - unsigned int val = 0, buck_val; - - ret = pmic_get("pmic@25", &dev); - if (ret == -ENODEV) { - puts("No pca9450@25\n"); - return 0; - } - - if (ret != 0) - return ret; - - /* BUCKxOUT_DVS0/1 control BUCK123 output */ - pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29); - - /* enable DVS control through PMIC_STBY_REQ */ - pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59); - - ret = pmic_reg_read(dev, PCA9450_PWR_CTRL); - if (ret < 0) - return ret; - val = ret; - - if (is_voltage_mode(VOLT_LOW_DRIVE)) { - buck_val = 0x0c; /* 0.8v for Low drive mode */ - printf("PMIC: Low Drive Voltage Mode\n"); - } else if (is_voltage_mode(VOLT_NOMINAL_DRIVE)) { - buck_val = 0x10; /* 0.85v for Nominal drive mode */ - printf("PMIC: Nominal Voltage Mode\n"); - } else { - buck_val = 0x14; /* 0.9v for Over drive mode */ - printf("PMIC: Over Drive Voltage Mode\n"); - } - - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val); - } else { - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, buck_val + 0x4); - pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, buck_val + 0x4); - } - - /* set standby voltage to 0.65v */ - if (val & PCA9450_REG_PWRCTRL_TOFF_DEB) - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x0); - else - pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x4); - - /* I2C_LT_EN*/ - pmic_reg_write(dev, 0xa, 0x3); - - return 0; -} - -void board_init_f(ulong dummy) -{ - int ret; - - /* Clear the BSS. */ - memset(__bss_start, 0, __bss_end - __bss_start); - - timer_init(); - - arch_cpu_init(); - - spl_early_init(); - - preloader_console_init(); - - ret = imx9_probe_mu(); - if (ret) { - printf("Fail to init ELE API\n"); - } else { - debug("SOC: 0x%x\n", gd->arch.soc_rev); - debug("LC: 0x%x\n", gd->arch.lifecycle); - } - - clock_init_late(); - - power_init_board(); - - if (!is_voltage_mode(VOLT_LOW_DRIVE)) - set_arm_core_max_clk(); - - /* Init power of mix */ - soc_power_init(); - - /* Setup TRDC for DDR access */ - trdc_init(); - - /* DDR initialization */ - spl_dram_init(); - - /* Put M33 into CPUWAIT for following kick */ - ret = m33_prepare(); - if (!ret) - printf("M33 prepare ok\n"); - - board_init_r(NULL, 0); -} diff --git a/configs/imx91-phycore_defconfig b/configs/imx91-phycore_defconfig new file mode 100644 index 00000000000..b1e13bade84 --- /dev/null +++ b/configs/imx91-phycore_defconfig @@ -0,0 +1,167 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x80200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x18000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" +CONFIG_NR_DRAM_BANKS=2 +CONFIG_PHYTEC_SOM_DETECTION=y +CONFIG_PHYTEC_EEPROM_BUS=2 +CONFIG_ENV_SIZE=0x10000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_IMX_CONFIG="arch/arm/mach-imx/imx9/imximage.cfg" +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="freescale/imx91-phyboard-segin" +CONFIG_TARGET_PHYCORE_IMX91=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204E0000 +CONFIG_SPL_TEXT_BASE=0x204A0000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x20498000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x80400000 +CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x720000 +CONFIG_CMD_DEKBLOB=y +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x88000000 +CONFIG_SYS_MEMTEST_START=0x80000000 +CONFIG_SYS_MEMTEST_END=0x90000000 +CONFIG_REMAKE_ELF=y +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEFAULT_FDT_FILE="oftree" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_MAX_SIZE=0x26000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_BOOTROM_SUPPORT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x83200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_POWER=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="u-boot=> " +# CONFIG_CMD_BOOTDEV is not set +# CONFIG_CMD_BOOTMETH is not set +# CONFIG_CMD_BOOTSTD is not set +CONFIG_CMD_ERASEENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_EEPROM=y +CONFIG_SYS_I2C_EEPROM_BUS=2 +CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 +CONFIG_SYS_EEPROM_SIZE=4096 +CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=5 +CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_POWEROFF=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EFIDEBUG=y +CONFIG_CMD_RTC=y +CONFIG_CMD_TIME=y +CONFIG_CMD_GETTIME=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_REDUNDANT=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_DEVICE_INDEX=1 +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK_IMX93=y +CONFIG_SAVED_DRAM_TIMING_BASE=0x2049C000 +CONFIG_DFU_MMC=y +CONFIG_DFU_RAM=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82800000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_GPIO_HOG=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_I2C_EEPROM=y +CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_IMX=y +CONFIG_FEC_MXC=y +CONFIG_MII=y +CONFIG_PHY_TI_GENERIC=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX93=y +CONFIG_POWER_DOMAIN=y +CONFIG_DM_PMIC=y +CONFIG_DM_PMIC_PCA9450=y +CONFIG_SPL_DM_PMIC_PCA9450=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_PCA9450=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SYSRESET=y +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="PHYTEC" +CONFIG_USB_GADGET_VENDOR_NUM=0x1fc9 +CONFIG_USB_GADGET_PRODUCT_NUM=0x0152 +CONFIG_CI_UDC=y +CONFIG_ULP_WATCHDOG=y +# CONFIG_RSA is not set +# CONFIG_SPL_SHA256 is not set +CONFIG_LZO=y +CONFIG_BZIP2=y diff --git a/configs/imx93-phycore_defconfig b/configs/imx93-phycore_defconfig index 3fb6e7b5f1d..6ae6e405fbf 100644 --- a/configs/imx93-phycore_defconfig +++ b/configs/imx93-phycore_defconfig @@ -5,7 +5,7 @@ CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x20000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SOURCE_FILE="phycore_imx93" +CONFIG_ENV_SOURCE_FILE="phycore_imx91_93" CONFIG_NR_DRAM_BANKS=2 CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_PHYTEC_EEPROM_BUS=2 diff --git a/doc/board/phytec/imx91-93-phycore.rst b/doc/board/phytec/imx91-93-phycore.rst new file mode 100644 index 00000000000..42bcda100e0 --- /dev/null +++ b/doc/board/phytec/imx91-93-phycore.rst @@ -0,0 +1,83 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +phyCORE-i.MX 91/93 +================== + +U-Boot for the phyCORE-i.MX 91/93. Both SoC variants, that is i.MX 91 and i.MX 93, +are supported by same board code, however each variant uses different defconfig +and ATF/ELE firmware blobs. Please follow the correct steps for the populated SoC. + +Quick Start +----------- + +- Get and Build the ARM Trusted firmware +- Get the DDR firmware +- Get ahab-container.img +- Build U-Boot + +Get and Build the ARM Trusted firmware +-------------------------------------- + +Note: srctree is U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx91 bl31 + $ cp build/imx91/release/bl31.bin $(srctree) + +For phyCORE-i.MX 93 variant: + +.. code-block:: bash + + $ unset LDFLAGS + $ make PLAT=imx93 bl31 + $ cp build/imx93/release/bl31.bin $(srctree) + +Get the DDR firmware +-------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin + $ chmod +x firmware-imx-8.21.bin + $ ./firmware-imx-8.21.bin + $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) + +Get ahab-container.img +--------------------------------------- + +.. code-block:: bash + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-1.3.0-17945fc.bin + $ chmod +x firmware-ele-imx-1.3.0-17945fc.bin + $ ./firmware-ele-imx-1.3.0-17945fc.bin + $ cp firmware-ele-imx-1.3.0-17945fc/mx91a0-ahab-container.img $(srctree) + $ cp firmware-ele-imx-1.3.0-17945fc/mx93a1-ahab-container.img $(srctree) + +Build U-Boot +------------ + +For phyCORE-i.MX 91 variant: + +.. code-block:: bash + + $ make imx91-phycore_defconfig + $ make + +For phyCORE-i.MX 93 variant: + +.. code-block:: bash + + $ make imx93-phycore_defconfig + $ make + +Burn the flash.bin to MicroSD card offset 32KB: + +.. code-block:: bash + + $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc diff --git a/doc/board/phytec/imx93-phycore.rst b/doc/board/phytec/imx93-phycore.rst deleted file mode 100644 index bd110a3ebee..00000000000 --- a/doc/board/phytec/imx93-phycore.rst +++ /dev/null @@ -1,61 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ - -phyCORE-i.MX 93 -=============== - -U-Boot for the phyCORE-i.MX 93. - -Quick Start ------------ - -- Get and Build the ARM Trusted firmware -- Get the DDR firmware -- Get ahab-container.img -- Build U-Boot - -Get and Build the ARM Trusted firmware --------------------------------------- - -Note: srctree is U-Boot source directory -Get ATF from: https://github.com/nxp-imx/imx-atf/ -branch: lf_v2.8 - -.. code-block:: bash - - $ unset LDFLAGS - $ make PLAT=imx93 bl31 - $ cp build/imx93/release/bl31.bin $(srctree) - -Get the DDR firmware --------------------- - -.. code-block:: bash - - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.21.bin - $ chmod +x firmware-imx-8.21.bin - $ ./firmware-imx-8.21.bin - $ cp firmware-imx-8.21/firmware/ddr/synopsys/lpddr4*.bin $(srctree) - -Get ahab-container.img ---------------------------------------- - -.. code-block:: bash - - $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-sentinel-0.11.bin - $ chmod +x firmware-sentinel-0.11.bin - $ ./firmware-sentinel-0.11.bin - $ cp firmware-sentinel-0.11/mx93a1-ahab-container.img $(srctree) - -Build U-Boot ------------- - -.. code-block:: bash - - $ make imx93-phycore_defconfig - $ make - -Burn the flash.bin to MicroSD card offset 32KB: - -.. code-block:: bash - - $ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc diff --git a/doc/board/phytec/index.rst b/doc/board/phytec/index.rst index dd9edd792f4..4519079ab3d 100644 --- a/doc/board/phytec/index.rst +++ b/doc/board/phytec/index.rst @@ -8,7 +8,7 @@ PHYTEC imx8mp-libra-fpsc imx8mm-phygate-tauri-l - imx93-phycore + imx91-93-phycore phycore-am62x phycore-am62ax phycore-am64x diff --git a/include/configs/phycore_imx91_93.h b/include/configs/phycore_imx91_93.h new file mode 100644 index 00000000000..02fa1d9b274 --- /dev/null +++ b/include/configs/phycore_imx91_93.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + * Christoph Stoidner + * Copyright (C) 2024 Mathieu Othacehe + */ + +#ifndef __PHYCORE_IMX91_93_H +#define __PHYCORE_IMX91_93_H + +#include +#include + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#endif /* __PHYCORE_IMX91_93_H */ diff --git a/include/configs/phycore_imx93.h b/include/configs/phycore_imx93.h deleted file mode 100644 index 07364dff403..00000000000 --- a/include/configs/phycore_imx93.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2022 NXP - * Copyright (C) 2023 PHYTEC Messtechnik GmbH - * Christoph Stoidner - * Copyright (C) 2024 Mathieu Othacehe - */ - -#ifndef __PHYCORE_IMX93_H -#define __PHYCORE_IMX93_H - -#include -#include - -#define CFG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#define CFG_SYS_INIT_RAM_ADDR 0x80000000 -#define CFG_SYS_INIT_RAM_SIZE 0x200000 - -#define CFG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM 0x80000000 -#define PHYS_SDRAM_SIZE 0x80000000 - -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG3_BASE_ADDR - -#endif /* __PHYCORE_IMX93_H */ -- cgit v1.3.1 From de27ed88b32ff050b9e8e113d5474042f25efb3d Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Mon, 23 Mar 2026 14:47:31 +0100 Subject: env: tq: add shareable environment settings Prepare moving boiler plate code out of board confguration header and prepare to share a lot of things between boards. Signed-off-by: Markus Niebel Signed-off-by: Max Merchel --- include/env/tq/mmc.env | 82 ++++++++++++++++++++++++++++++++++++++++ include/env/tq/nfs.env | 51 +++++++++++++++++++++++++ include/env/tq/spi.env | 23 +++++++++++ include/env/tq/tq-imx-shared.env | 38 +++++++++++++++++++ include/env/tq/ubi.env | 47 +++++++++++++++++++++++ 5 files changed, 241 insertions(+) create mode 100644 include/env/tq/mmc.env create mode 100644 include/env/tq/nfs.env create mode 100644 include/env/tq/spi.env create mode 100644 include/env/tq/tq-imx-shared.env create mode 100644 include/env/tq/ubi.env (limited to 'include') diff --git a/include/env/tq/mmc.env b/include/env/tq/mmc.env new file mode 100644 index 00000000000..abf561f8467 --- /dev/null +++ b/include/env/tq/mmc.env @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared mmc environment for TQ boards + */ + +addmmc= + setenv bootargs "${bootargs}" + root=/dev/mmcblk"${mmcblkdev}"p"${mmcrootpart}" "${rootfsmode}" rootwait; + +get_blockcount= + setexpr blkc "${filesize}" + 0x1ff; + setexpr blkc "${blkc}" / 0x200; + +load_mmc= + mmc dev "${mmcdev}"; mmc rescan; + load mmc "${mmcdev}":"${mmcpart}" "${kernel_addr_r}" /boot/"${image}"; + load mmc "${mmcdev}":"${mmcpart}" "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + load mmc "${mmcdev}":"${mmcpart}" "${fdtoverlay_addr_r}" + /boot/"${overlay}" && fdt apply "${fdtoverlay_addr_r}"; + done; + +mmcargs=run addtty addmmc + +mmcboot= + echo "Booting from mmc ..."; + setenv bootargs && run mmcargs && + if run load_mmc; then + run boot_os; + else + echo "ERROR: loading from mmc"; + fi; + +mmcpart=2 + +mmc_finish_update_uboot= + mmc write "${loadaddr}" "${update_start_blk}" "${blkc}"; + mmc dev "${mmcdev}" 0; + setenv update_part; + setenv update_start_blk; + setenv blkc; + +mmc_prepare_update_uboot= + echo "Write U-Boot to mmc "${mmcdev}" ..."; + mmc dev "${mmcdev}"; mmc rescan; + run get_blockcount; + setenv update_start_blk "${uboot_mmc_start}"; + setenv update_part 0; + +mmc_switch_part= + mmc partconf "${mmcdev}" update_part; + mmc dev "${mmcdev}" "${update_part}"; + +mmcrootpart=2 + +update_uboot_mmc= + run check_ipaddr; + if tftp "${uboot}"; then + run mmc_prepare_update_uboot; + if itest "${blkc}" >= "${uboot_mmc_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + if itest "${mmcdev}" == "${emmc_dev}"; then + run mmc_switch_part; + if itest "${update_part}" > 0 ; then + if env exists emmc_bootp_start; then + setenv update_start_blk "${emmc_bootp_start}"; + else + echo "ERROR: eMMC boot partition block unset"; + exit; + fi; + fi; + fi; + run mmc_finish_update_uboot; + fi; diff --git a/include/env/tq/nfs.env b/include/env/tq/nfs.env new file mode 100644 index 00000000000..53fcbd0d152 --- /dev/null +++ b/include/env/tq/nfs.env @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared nfs environment for TQ boards + */ + +addnfs= + setenv bootargs "${bootargs}" root=/dev/nfs rw + nfsroot="${serverip}":"${rootpath}",v3,tcp + +load_nfs= + nfs "${kernel_addr_r}" "${serverip}":"${rootpath}"/boot/"${image}"; + nfs "${fdt_addr_r}" "${serverip}":"${rootpath}"/boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + nfs "${fdtoverlay_addr_r}" + "${serverip}":"${rootpath}"/boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + +load_tftp= + tftp "${kernel_addr_r}" "${image}"; + tftp "${fdt_addr_r}" "${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + if tftp "${fdtoverlay_addr_r}" "${overlay}"; then + fdt apply "${fdtoverlay_addr_r}"; + else + exit; + fi; + done; + +netargs=run addnfs addip addtty + +netloadcmd=load_tftp + +nfsboot= + echo "Booting from NFS ..."; + setenv bootargs; + run netargs; + run check_ipaddr; + if run ${netloadcmd}; then + run boot_os; + else + echo "ERROR: loading from NFS"; + fi; diff --git a/include/env/tq/spi.env b/include/env/tq/spi.env new file mode 100644 index 00000000000..47dcfea7d3f --- /dev/null +++ b/include/env/tq/spi.env @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared spi environment for TQ boards + */ + +update_uboot_spi= + run check_ipaddr; + if tftp ${uboot}; then + if itest "${filesize}" >= "${uboot_spi_size}"; then + echo "ERROR: size to large ..."; + exit; + fi; + echo "Write u-boot image to SPI NOR ..."; + if sf probe; then + run write_uboot_spi; + fi; + fi; + +write_uboot_spi=sf update "${loadaddr}" "${uboot_spi_start}" "${filesize}" diff --git a/include/env/tq/tq-imx-shared.env b/include/env/tq/tq-imx-shared.env new file mode 100644 index 00000000000..d4e42f8b536 --- /dev/null +++ b/include/env/tq/tq-imx-shared.env @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared environment for TQ imx boards + */ + +#ifdef CONFIG_CMD_SF +#include "spi.env" +#ifdef CONFIG_CMD_UBIFS +#include "ubi.env" +#endif /* CONFIG_CMD_UBIFS */ +#endif /* CONFIG_CMD_SF */ + +#ifdef CONFIG_CMD_MMC +#include "mmc.env" +#endif + +#ifdef CONFIG_CMD_NFS +#include "nfs.env" +#endif + +addip= + run check_ipaddr; + setenv bootargs "${bootargs}" + ip="${ipaddr}":"${serverip}":"${gatewayip}":"${netmask}":"${hostname}":"${netdev}":off + +addtty=setenv bootargs "${bootargs}" "${console}" + +check_ipaddr= + if test -z "${ipaddr}" || test -z "${serverip}"; then + echo "ipaddr or serverip unset, falling back to DHCP..."; + dhcp; + fi; + +rootfsmode=ro diff --git a/include/env/tq/ubi.env b/include/env/tq/ubi.env new file mode 100644 index 00000000000..01243d2eb53 --- /dev/null +++ b/include/env/tq/ubi.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * shared ubi environment for TQ boards + */ + +addubi= + setenv bootargs "${bootargs}" rootfstype=ubifs ubi.mtd="${ubimtdname}" + root=ubi0:"${ubirootfsvol}" "${rootfsmode}" rootwait; + +load_spi= + if sf probe; then + if ubi part "${ubirootfspart}"; then + if ubifsmount ubi0:"${ubirootfsvol}"; then + ubifsload "${kernel_addr_r}" /boot/"${image}"; + ubifsload "${fdt_addr_r}" /boot/"${fdtfile}"; + fdt address "${fdt_addr_r}"; + fdt resize 0x100000; + for overlay in "${fdt_overlays}"; do + ubifsload "${fdtoverlay_addr_r}" + /boot/"${overlay}" && + fdt apply "${fdtoverlay_addr_r}"; + done; + ubifsumount; + fi; + ubi detach; + fi; + fi + +ubiargs=run addubi addtty + +ubiboot= + echo "Booting from UBI ..."; + setenv bootargs; + run ubiargs; + if run load_spi; then + run boot_os; + else + echo "ERROR: loading kernel"; + fi; + +ubimtdname=mtdname +ubirootfspart=ubi +ubirootfsvol=root -- cgit v1.3.1 From 6c591676a93019ef663492f388991e21efd41ae2 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Mon, 23 Mar 2026 14:47:32 +0100 Subject: configs: tqma6.h: remove unused define for PHYS_SDRAM_SIZE Remove the definition of PHYS_SDRAM_SIZE as it is not used. Signed-off-by: Max Merchel --- include/configs/tqma6.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'include') diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 5e89cd6937a..7c59b722e2f 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -16,14 +16,6 @@ #include "mx6_common.h" -#if defined(CONFIG_TQMA6S) -#define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_TQMA6DL) -#define PHYS_SDRAM_SIZE (SZ_1G) -#elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (SZ_1G) -#endif - /* SPI Flash */ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K -- cgit v1.3.1 From b08dc109dadbeefb6488cccfb9ae501940058313 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Mon, 23 Mar 2026 14:47:33 +0100 Subject: configs: tqma6.h: remove unused define for PFUZE100_I2C Remove the definition of CFG_POWER_PFUZE100_I2C_ADDR and TQMA6_PFUZE100_I2C_BUS as it is not used. Signed-off-by: Max Merchel --- include/configs/tqma6.h | 5 ----- 1 file changed, 5 deletions(-) (limited to 'include') diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 7c59b722e2f..bb335ee1b41 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -20,11 +20,6 @@ #define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K -#if !defined(CONFIG_DM_PMIC) -#define CFG_POWER_PFUZE100_I2C_ADDR 0x08 -#define TQMA6_PFUZE100_I2C_BUS 2 -#endif - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -- cgit v1.3.1 From 8ff44f6f6152ac8ba6c71cd00868fdf349fe39d8 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Mon, 23 Mar 2026 14:47:34 +0100 Subject: board: tqma6: change to use shareable tq environment Create tqma6 environment file and remove CFG_FEC_MXC_PHYADDR as it comes from device tree. Signed-off-by: Max Merchel --- board/tq/tqma6/tqma6.env | 47 +++++++++ include/configs/tqma6.h | 244 +++---------------------------------------- include/configs/tqma6_mba6.h | 3 - 3 files changed, 61 insertions(+), 233 deletions(-) create mode 100644 board/tq/tqma6/tqma6.env (limited to 'include') diff --git a/board/tq/tqma6/tqma6.env b/board/tq/tqma6/tqma6.env new file mode 100644 index 00000000000..b1d7e5cbbcf --- /dev/null +++ b/board/tq/tqma6/tqma6.env @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2024-2026 TQ-Systems GmbH , + * D-82229 Seefeld, Germany. + * Author: Max Merchel + * + * TQMa6 environment + */ + +#include + +board=tqma6 +boot_os=bootz "${kernel_addr_r}" - "${fdt_addr_r}" +emmc_bootp_start=TQMA6_MMC_UBOOT_SECTOR_START +emmc_dev=0 +fdt_addr_r=TQMA6_FDT_ADDRESS +fdtoverlay_addr_r=TQMA6_FDT_OVERLAY_ADDR +image=zImage +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +pxefile_addr_r=CONFIG_SYS_LOAD_ADDR +ramdisk_addr_r=TQMA6_INITRD_ADDRESS +mmcautodetect=yes +mmcblkdev=0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +netdev=eth0 +sd_dev=1 +uboot=u-boot-with-spl.imx +uboot_mmc_start=TQMA6_MMC_UBOOT_SECTOR_START +uboot_mmc_size=TQMA6_MMC_UBOOT_SECTOR_COUNT +uboot_spi_sector_size=TQMA6_SPI_FLASH_SECTOR_SIZE +uboot_spi_start=TQMA6_SPI_UBOOT_START +uboot_spi_size=TQMA6_SPI_UBOOT_SIZE + +#ifdef CONFIG_USB_FUNCTION_FASTBOOT + +/* 0=user 1=boot1 2=boot2 */ +fastboot_mmc_boot_partition = 1 + +fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV :0 + +fastboot_raw_partition_bootloader= + TQMA6_MMC_UBOOT_SECTOR_START TQMA6_MMC_UBOOT_SECTOR_COUNT mmcpart + "${fastboot_mmc_boot_partition}" + +fastbootcmd=fastboot usb 0 + +#endif /* CONFIG_USB_FUNCTION_FASTBOOT */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index bb335ee1b41..3c6678aa2b8 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -7,243 +7,22 @@ * Configuration settings for the TQ-Systems TQMa6 module. */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* place code in last 4 MiB of RAM */ +#ifndef __TQMA6_CONFIG_H +#define __TQMA6_CONFIG_H #include "mx6_common.h" -/* SPI Flash */ - -#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K - /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#if defined(CONFIG_TQMA6X_MMC_BOOT) - -#define TQMA6_UBOOT_OFFSET SZ_1K -#define TQMA6_UBOOT_SECTOR_START 0x2 -#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe - -#define TQMA6_FDT_OFFSET (2 * SZ_1M) -#define TQMA6_FDT_SECTOR_START 0x1000 -#define TQMA6_FDT_SECTOR_COUNT 0x800 - -#define TQMA6_KERNEL_SECTOR_START 0x2000 -#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "loadimage=mmc dev ${mmcdev}; " \ - "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ - "loadfdt=mmc dev ${mmcdev}; " \ - "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_kernel=run kernel_name; " \ - "if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${kernel_size}; then " \ - "mmc write ${loadaddr} " \ - "${kernel_start} ${blkc}; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${fdt_size}; then " \ - "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - -#elif defined(CONFIG_TQMA6X_SPI_BOOT) - -#define TQMA6_UBOOT_OFFSET 0x400 -#define TQMA6_UBOOT_SECTOR_START 0x0 -/* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define TQMA6_UBOOT_SECTOR_COUNT 0x8 -#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ - TQMA6_UBOOT_SECTOR_COUNT) - -#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ - CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) - -#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ -#define TQMA6_FDT_SECTOR_COUNT 0x01 - -#define TQMA6_KERNEL_SECTOR_START 0x10 -#define TQMA6_KERNEL_SECTOR_COUNT 0x60 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "mmcblkdev=0\0" \ - "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ - "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr blkc ${filesize} + " \ - __stringify(TQMA6_UBOOT_OFFSET) "; " \ - "setexpr size ${uboot_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${blkc} <= ${size}; then " \ - "sf probe; " \ - "sf erase 0 ${size}; " \ - "sf write ${loadaddr} ${uboot_offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv blkc; setenv size \0" \ - "update_kernel=run kernel_name; if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "loadimage=sf probe; " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${loadaddr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - "loadfdt=sf probe; " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${fdt_addr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" -#else - -#error "need to define boot source" - -#endif - /* 128 MiB offset as in ARM related docu for linux suggested */ #define TQMA6_FDT_ADDRESS 0x18000000 -/* set to a resonable value, changeable by user */ -#define TQMA6_CMA_SIZE 160M +/* 256KiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_256K) */ +#define TQMA6_FDT_OVERLAY_ADDR 0x18040000 -#define CFG_EXTRA_ENV_SETTINGS \ - "board=tqma6\0" \ - "uimage=uImage\0" \ - "zimage=zImage\0" \ - "boot_type=bootz\0" \ - "kernel_name=if test \"${boot_type}\" != bootz; then " \ - "setenv kernel ${uimage}; " \ - "else setenv kernel ${zimage}; fi\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ - "initrd_high=0xffffffff\0" \ - "rootfsmode=ro\0" \ - "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ - "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "addfb=setenv bootargs ${bootargs} " \ - "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ - "mmcpart=2\0" \ - "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb addcma\0" \ - "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ - "rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "setenv bootargs; " \ - "run mmcargs; " \ - "run loadimage; " \ - "if run loadfdt; then " \ - "echo boot device tree kernel ...; " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "${boot_type}; " \ - "fi;\0" \ - "setenv bootargs \0" \ - "netdev=eth0\0" \ - "rootpath=/srv/nfs/tqma6\0" \ - "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb addcma\0" \ - "addnfs=setenv bootargs ${bootargs} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ - "addip_static=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test \"${ipmode}\" != static; then " \ - "run addip_dynamic; else run addip_static; fi\0" \ - "set_getcmd=if test \"${ipmode}\" != static; then " \ - "setenv getcmd dhcp; setenv autoload yes; " \ - "else setenv getcmd tftp; setenv autoload no; fi\0" \ - "netboot=echo Booting from net ...; " \ - "run kernel_name; " \ - "run set_getcmd; " \ - "setenv bootargs; " \ - "run netargs; " \ - "if ${getcmd} ${kernel}; then " \ - "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "fi; " \ - "fi; " \ - "echo ... failed\0" \ - "panicboot=echo No boot device !!! reset\0" \ - TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ +/* 16MiB above TQMA6_FDT_ADDRESS (TQMA6_FDT_ADDRESS + SZ_16M) */ +#define TQMA6_INITRD_ADDRESS 0x19000000 /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -252,6 +31,13 @@ #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define TQMA6_MMC_UBOOT_SECTOR_START 0x2 +#define TQMA6_MMC_UBOOT_SECTOR_COUNT 0x7fe + +#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K +#define TQMA6_SPI_UBOOT_START 0x400 +#define TQMA6_SPI_UBOOT_SIZE 0xc0000 + /* * All the defines above are for the TQMa6 SoM * @@ -265,6 +51,4 @@ #error "No baseboard for the TQMa6 defined!" #endif -/* Support at least the sensor on TQMa6 SOM */ - -#endif /* __CONFIG_H */ +#endif /* __TQMA6_CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 9b9f4150951..81f96ac91e8 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,9 +11,6 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H -#define CFG_FEC_MXC_PHYADDR 0x03 - #define CFG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" #endif /* __CONFIG_TQMA6_MBA6_H */ -- cgit v1.3.1 From 46de8729952a4cc702ecb730923c470dd21edc07 Mon Sep 17 00:00:00 2001 From: Max Merchel Date: Mon, 23 Mar 2026 14:47:35 +0100 Subject: configs: tqma6: change to include tqma6.h in baseboard headers The SoM (TQMa6) can be used on various baseboards. No modifications to the SoM files should be required to use the SoM on different baseboards. Therefore, include the SoM headers in the baseboard. Signed-off-by: Max Merchel --- board/tq/tqma6/Kconfig | 3 ++- include/configs/tqma6.h | 13 ------------- include/configs/tqma6_mba6.h | 2 ++ include/configs/tqma6_wru4.h | 2 ++ 4 files changed, 6 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/board/tq/tqma6/Kconfig b/board/tq/tqma6/Kconfig index e62228d73d0..9cb0c909aa9 100644 --- a/board/tq/tqma6/Kconfig +++ b/board/tq/tqma6/Kconfig @@ -7,7 +7,8 @@ config SYS_VENDOR default "tq" config SYS_CONFIG_NAME - default "tqma6" + default "tqma6_mba6" if MBA6 + default "tqma6_wru4" if WRU4 choice prompt "TQMa6 SoC variant" diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 3c6678aa2b8..00610e76869 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -38,17 +38,4 @@ #define TQMA6_SPI_UBOOT_START 0x400 #define TQMA6_SPI_UBOOT_SIZE 0xc0000 -/* - * All the defines above are for the TQMa6 SoM - * - * Now include the baseboard specific configuration - */ -#ifdef CONFIG_MBA6 -#include "tqma6_mba6.h" -#elif CONFIG_WRU4 -#include "tqma6_wru4.h" -#else -#error "No baseboard for the TQMa6 defined!" -#endif - #endif /* __TQMA6_CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h index 81f96ac91e8..c30aeae4f29 100644 --- a/include/configs/tqma6_mba6.h +++ b/include/configs/tqma6_mba6.h @@ -11,6 +11,8 @@ #ifndef __CONFIG_TQMA6_MBA6_H #define __CONFIG_TQMA6_MBA6_H +#include "tqma6.h" + #define CFG_MXC_UART_BASE UART2_BASE #endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h index 110bd895a8a..b35e471bd95 100644 --- a/include/configs/tqma6_wru4.h +++ b/include/configs/tqma6_wru4.h @@ -6,6 +6,8 @@ #ifndef __CONFIG_TQMA6_WRU4_H #define __CONFIG_TQMA6_WRU4_H +#include "tqma6.h" + /* Ethernet */ #define CFG_FEC_MXC_PHYADDR 0x01 -- cgit v1.3.1 From e2138cf1e6088f12ffa874e87cc8f4b198378635 Mon Sep 17 00:00:00 2001 From: Rasmus Villemoes Date: Mon, 23 Mar 2026 09:39:28 +0100 Subject: linker_lists.h: drop never used ll_start, ll_end macros These macros have AFAICT never been used at all. It's also far from clear what purpose it could serve - for one thing, what _type would one pass, other than void perhaps? The example using "struct my_sub_cmd" seems misplaced, as how could one know that the first linker list consists of those, and moreover, how would one know how many there are? The linker list concept is fragile enough on its own, there is no need to have unused functionality lying around that may or may not bitrot and certainly will confuse readers of linker_lists.h. Signed-off-by: Rasmus Villemoes Reviewed-by: Simon Glass --- include/linker_lists.h | 50 -------------------------------------------------- 1 file changed, 50 deletions(-) (limited to 'include') diff --git a/include/linker_lists.h b/include/linker_lists.h index 0f4a2d686e2..78ba937c8c3 100644 --- a/include/linker_lists.h +++ b/include/linker_lists.h @@ -288,56 +288,6 @@ #define ll_entry_ref(_type, _name, _list) \ ((_type *)&_u_boot_list_2_##_list##_2_##_name) -/** - * ll_start() - Point to first entry of first linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer to the very first entry of - * the very first linker-generated array. - * - * Since this macro defines the start of the linker-generated arrays, - * its leftmost index must be 1. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_start(struct my_sub_cmd); - */ -#define ll_start(_type) \ -({ \ - static char start[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_1"); \ - _type * tmp = (_type *)&start; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - -/** - * ll_end() - Point after last entry of last linker-generated array - * @_type: Data type of the entry - * - * This function returns ``(_type *)`` pointer after the very last entry of - * the very last linker-generated array. - * - * Since this macro defines the end of the linker-generated arrays, - * its leftmost index must be 3. - * - * Example: - * - * :: - * - * struct my_sub_cmd *msc = ll_end(struct my_sub_cmd); - */ -#define ll_end(_type) \ -({ \ - static char end[0] __aligned(4) __attribute__((unused)) \ - __section("__u_boot_list_3"); \ - _type * tmp = (_type *)&end; \ - asm("":"+r"(tmp)); \ - tmp; \ -}) - #endif /* __ASSEMBLY__ */ #endif /* __LINKER_LISTS_H__ */ -- cgit v1.3.1