From 3d7cf4192f045d9003c80bc937b18a6169eabbcf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:19 -0600 Subject: dm: core: Sort the uclasses Sort uclasses into alphabetical order and tidy up the comments. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/dm/uclass-id.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 08f1bad9385..b17528d207c 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -22,31 +22,31 @@ enum uclass_id { UCLASS_I2C_EMUL, /* sandbox I2C device emulator */ UCLASS_PCI_EMUL, /* sandbox PCI device emulator */ UCLASS_USB_EMUL, /* sandbox USB bus device emulator */ - UCLASS_SIMPLE_BUS, + UCLASS_SIMPLE_BUS, /* bus with child devices */ - /* U-Boot uclasses start here */ + /* U-Boot uclasses start here - in alphabetical order */ + UCLASS_CPU, /* CPU, typically part of an SoC */ + UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ - UCLASS_SERIAL, /* Serial UART */ - UCLASS_SPI, /* SPI bus */ - UCLASS_SPI_GENERIC, /* Generic SPI flash target */ - UCLASS_SPI_FLASH, /* SPI flash */ - UCLASS_CROS_EC, /* Chrome OS EC */ - UCLASS_THERMAL, /* Thermal sensor */ UCLASS_I2C, /* I2C bus */ - UCLASS_I2C_GENERIC, /* Generic I2C device */ UCLASS_I2C_EEPROM, /* I2C EEPROM device */ + UCLASS_I2C_GENERIC, /* Generic I2C device */ + UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_MASS_STORAGE, /* Mass storage device */ UCLASS_MOD_EXP, /* RSA Mod Exp device */ + UCLASS_PCH, /* x86 platform controller hub */ UCLASS_PCI, /* PCI bus */ UCLASS_PCI_GENERIC, /* Generic PCI bus device */ - UCLASS_PCH, /* x86 platform controller hub */ - UCLASS_ETH, /* Ethernet device */ - UCLASS_LPC, /* x86 'low pin count' interface */ + UCLASS_RTC, /* Real time clock device */ + UCLASS_SERIAL, /* Serial UART */ + UCLASS_SPI, /* SPI bus */ + UCLASS_SPI_GENERIC, /* Generic SPI flash target */ + UCLASS_SPI_FLASH, /* SPI flash */ + UCLASS_THERMAL, /* Thermal sensor */ UCLASS_USB, /* USB bus */ - UCLASS_USB_HUB, /* USB hub */ UCLASS_USB_DEV_GENERIC, /* USB generic device */ - UCLASS_MASS_STORAGE, /* Mass storage device */ - UCLASS_CPU, /* CPU, typically part of an SoC */ - UCLASS_RTC, /* Real time clock device */ + UCLASS_USB_HUB, /* USB hub */ UCLASS_COUNT, UCLASS_INVALID = -1, -- cgit v1.2.3 From 962f5caf600c54f4103bfa6b31fa2fb4e8aaacb9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:20 -0600 Subject: dm: gpio: Add error handling and a function to claim vector GPIOs gpio_get_values_as_int() should return an error if something goes wrong. Also provide gpio_claim_vector(), a function to request the GPIOs and set them to input mode. Otherwise callers have to do this themselves. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/asm-generic/gpio.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index 3b96b8209a1..4752ea4d823 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -336,15 +336,24 @@ int gpio_lookup_name(const char *name, struct udevice **devp, unsigned int *offsetp, unsigned int *gpiop); /** - * get_gpios() - Turn the values of a list of GPIOs into an integer + * gpio_get_values_as_int() - Turn the values of a list of GPIOs into an int * * This puts the value of the first GPIO into bit 0, the second into bit 1, * etc. then returns the resulting integer. * * @gpio_list: List of GPIOs to collect - * @return resulting integer value + * @return resulting integer value, or -ve on error */ -unsigned gpio_get_values_as_int(const int *gpio_list); +int gpio_get_values_as_int(const int *gpio_list); + +/** + * gpio_claim_vector() - claim a number of GPIOs for input + * + * @gpio_num_array: array of gpios to claim, terminated by -1 + * @fmt: format string for GPIO names, e.g. "board_id%d" + * @return 0 if OK, -ve on error + */ +int gpio_claim_vector(const int *gpio_num_array, const char *fmt); /** * gpio_request_by_name() - Locate and request a GPIO by name -- cgit v1.2.3 From 12e671142daa5d4dce5961e6f573a8b740b16f88 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:21 -0600 Subject: fdt: Add binding decode function for display-timings This is useful for display parameters. Add a simple decode function to read from this device tree node. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 77 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index f11475b5fdd..f304199e1df 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -802,6 +802,83 @@ int fdtdec_decode_memory_region(const void *blob, int node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep); +/* Display timings from linux include/video/display_timing.h */ +enum display_flags { + DISPLAY_FLAGS_HSYNC_LOW = 1 << 0, + DISPLAY_FLAGS_HSYNC_HIGH = 1 << 1, + DISPLAY_FLAGS_VSYNC_LOW = 1 << 2, + DISPLAY_FLAGS_VSYNC_HIGH = 1 << 3, + + /* data enable flag */ + DISPLAY_FLAGS_DE_LOW = 1 << 4, + DISPLAY_FLAGS_DE_HIGH = 1 << 5, + /* drive data on pos. edge */ + DISPLAY_FLAGS_PIXDATA_POSEDGE = 1 << 6, + /* drive data on neg. edge */ + DISPLAY_FLAGS_PIXDATA_NEGEDGE = 1 << 7, + DISPLAY_FLAGS_INTERLACED = 1 << 8, + DISPLAY_FLAGS_DOUBLESCAN = 1 << 9, + DISPLAY_FLAGS_DOUBLECLK = 1 << 10, +}; + +/* + * A single signal can be specified via a range of minimal and maximal values + * with a typical value, that lies somewhere inbetween. + */ +struct timing_entry { + u32 min; + u32 typ; + u32 max; +}; + +/* + * Single "mode" entry. This describes one set of signal timings a display can + * have in one setting. This struct can later be converted to struct videomode + * (see include/video/videomode.h). As each timing_entry can be defined as a + * range, one struct display_timing may become multiple struct videomodes. + * + * Example: hsync active high, vsync active low + * + * Active Video + * Video ______________________XXXXXXXXXXXXXXXXXXXXXX_____________________ + * |<- sync ->|<- back ->|<----- active ----->|<- front ->|<- sync.. + * | | porch | | porch | + * + * HSync _|¯¯¯¯¯¯¯¯¯¯|___________________________________________|¯¯¯¯¯¯¯¯¯ + * + * VSync ¯|__________|¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯|_________ + */ +struct display_timing { + struct timing_entry pixelclock; + + struct timing_entry hactive; /* hor. active video */ + struct timing_entry hfront_porch; /* hor. front porch */ + struct timing_entry hback_porch; /* hor. back porch */ + struct timing_entry hsync_len; /* hor. sync len */ + + struct timing_entry vactive; /* ver. active video */ + struct timing_entry vfront_porch; /* ver. front porch */ + struct timing_entry vback_porch; /* ver. back porch */ + struct timing_entry vsync_len; /* ver. sync len */ + + enum display_flags flags; /* display flags */ +}; + +/** + * fdtdec_decode_display_timing() - decode display timings + * + * Decode display timings from the supplied 'display-timings' node. + * See doc/device-tree-bindings/video/display-timing.txt for binding + * information. + * + * @param blob FDT blob + * @param node 'display-timing' node containing the timing subnodes + * @param index Index number to read (0=first timing subnode) + * @param config Place to put timings + * @return 0 if OK, -FDT_ERR_NOTFOUND if not found + */ +int fdtdec_decode_display_timing(const void *blob, int node, int index, + struct display_timing *config); /** * Set up the device tree ready for use */ -- cgit v1.2.3 From d55b7d4c53c78d4a4fbe28b65e8d50f184b53ce9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:26 -0600 Subject: power: Export register access functions from as3722 With the full PMIC framework we may be able to avoid this. But for now we need access to the PMIC. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/power/as3722.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/power/as3722.h b/include/power/as3722.h index aa966d2cca1..0f22482ff70 100644 --- a/include/power/as3722.h +++ b/include/power/as3722.h @@ -23,5 +23,8 @@ int as3722_gpio_configure(struct udevice *pmic, unsigned int gpio, unsigned long flags); int as3722_gpio_direction_output(struct udevice *pmic, unsigned int gpio, unsigned int level); +int as3722_read(struct udevice *pmic, u8 reg, u8 *value); +int as3722_write(struct udevice *pmic, u8 reg, u8 value); +int as3722_get(struct udevice **devp); #endif /* __POWER_AS3722_H__ */ -- cgit v1.2.3 From ec022efb8658cce75699afc3ce6ee8b2d9d0c273 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:31 -0600 Subject: tegra: config: Use CONFIG_LCD to detect LCD presence Instead of CONFIG_VIDEO_TEGRA, use CONFIG_LCD to determine whether an LCD is present. Tegra124 uses a different driver. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c3ad8beb903..46a155d4b80 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -34,7 +34,7 @@ #define STDIN_KBD_USB "" #endif -#ifdef CONFIG_VIDEO_TEGRA +#ifdef CONFIG_LCD #define STDOUT_LCD ",lcd" #else #define STDOUT_LCD "" -- cgit v1.2.3 From 490f5fd2388f0f7f18e1df22ff318393f8483ea4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:36 -0600 Subject: video: Add drm_dp_helper.h This file (from Linux 3.17) provides defines for display port. Use it so that our naming is consistent with Linux. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren --- include/linux/drm_dp_helper.h | 405 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 405 insertions(+) create mode 100644 include/linux/drm_dp_helper.h (limited to 'include') diff --git a/include/linux/drm_dp_helper.h b/include/linux/drm_dp_helper.h new file mode 100644 index 00000000000..86b06e11ccb --- /dev/null +++ b/include/linux/drm_dp_helper.h @@ -0,0 +1,405 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DRM_DP_HELPER_H_ +#define _DRM_DP_HELPER_H_ + +/* + * Unless otherwise noted, all values are from the DP 1.1a spec. Note that + * DP and DPCD versions are independent. Differences from 1.0 are not noted, + * 1.0 devices basically don't exist in the wild. + * + * Abbreviations, in chronological order: + * + * eDP: Embedded DisplayPort version 1 + * DPI: DisplayPort Interoperability Guideline v1.1a + * 1.2: DisplayPort 1.2 + * MST: Multistream Transport - part of DP 1.2a + * + * 1.2 formally includes both eDP and DPI definitions. + */ + +#define DP_AUX_I2C_WRITE 0x0 +#define DP_AUX_I2C_READ 0x1 +#define DP_AUX_I2C_STATUS 0x2 +#define DP_AUX_I2C_MOT 0x4 +#define DP_AUX_NATIVE_WRITE 0x8 +#define DP_AUX_NATIVE_READ 0x9 + +#define DP_AUX_NATIVE_REPLY_ACK (0x0 << 0) +#define DP_AUX_NATIVE_REPLY_NACK (0x1 << 0) +#define DP_AUX_NATIVE_REPLY_DEFER (0x2 << 0) +#define DP_AUX_NATIVE_REPLY_MASK (0x3 << 0) + +#define DP_AUX_I2C_REPLY_ACK (0x0 << 2) +#define DP_AUX_I2C_REPLY_NACK (0x1 << 2) +#define DP_AUX_I2C_REPLY_DEFER (0x2 << 2) +#define DP_AUX_I2C_REPLY_MASK (0x3 << 2) + +/* AUX CH addresses */ +/* DPCD */ +#define DP_DPCD_REV 0x000 + +#define DP_MAX_LINK_RATE 0x001 + +#define DP_MAX_LANE_COUNT 0x002 +# define DP_MAX_LANE_COUNT_MASK 0x1f +# define DP_TPS3_SUPPORTED (1 << 6) /* 1.2 */ +# define DP_ENHANCED_FRAME_CAP (1 << 7) + +#define DP_MAX_DOWNSPREAD 0x003 +# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6) + +#define DP_NORP 0x004 + +#define DP_DOWNSTREAMPORT_PRESENT 0x005 +# define DP_DWN_STRM_PORT_PRESENT (1 << 0) +# define DP_DWN_STRM_PORT_TYPE_MASK 0x06 +# define DP_DWN_STRM_PORT_TYPE_DP (0 << 1) +# define DP_DWN_STRM_PORT_TYPE_ANALOG (1 << 1) +# define DP_DWN_STRM_PORT_TYPE_TMDS (2 << 1) +# define DP_DWN_STRM_PORT_TYPE_OTHER (3 << 1) +# define DP_FORMAT_CONVERSION (1 << 3) +# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4) /* DPI */ + +#define DP_MAIN_LINK_CHANNEL_CODING 0x006 + +#define DP_DOWN_STREAM_PORT_COUNT 0x007 +# define DP_PORT_COUNT_MASK 0x0f +# define DP_MSA_TIMING_PAR_IGNORED (1 << 6) /* eDP */ +# define DP_OUI_SUPPORT (1 << 7) + +#define DP_I2C_SPEED_CAP 0x00c /* DPI */ +# define DP_I2C_SPEED_1K 0x01 +# define DP_I2C_SPEED_5K 0x02 +# define DP_I2C_SPEED_10K 0x04 +# define DP_I2C_SPEED_100K 0x08 +# define DP_I2C_SPEED_400K 0x10 +# define DP_I2C_SPEED_1M 0x20 + +#define DP_EDP_CONFIGURATION_CAP 0x00d /* XXX 1.2? */ +#define DP_TRAINING_AUX_RD_INTERVAL 0x00e /* XXX 1.2? */ + +/* Multiple stream transport */ +#define DP_FAUX_CAP 0x020 /* 1.2 */ +# define DP_FAUX_CAP_1 (1 << 0) + +#define DP_MSTM_CAP 0x021 /* 1.2 */ +# define DP_MST_CAP (1 << 0) + +#define DP_GUID 0x030 /* 1.2 */ + +#define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ +# define DP_PSR_IS_SUPPORTED 1 +#define DP_PSR_CAPS 0x071 /* XXX 1.2? */ +# define DP_PSR_NO_TRAIN_ON_EXIT 1 +# define DP_PSR_SETUP_TIME_330 (0 << 1) +# define DP_PSR_SETUP_TIME_275 (1 << 1) +# define DP_PSR_SETUP_TIME_220 (2 << 1) +# define DP_PSR_SETUP_TIME_165 (3 << 1) +# define DP_PSR_SETUP_TIME_110 (4 << 1) +# define DP_PSR_SETUP_TIME_55 (5 << 1) +# define DP_PSR_SETUP_TIME_0 (6 << 1) +# define DP_PSR_SETUP_TIME_MASK (7 << 1) +# define DP_PSR_SETUP_TIME_SHIFT 1 + +/* + * 0x80-0x8f describe downstream port capabilities, but there are two layouts + * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not, + * each port's descriptor is one byte wide. If it was set, each port's is + * four bytes wide, starting with the one byte from the base info. As of + * DP interop v1.1a only VGA defines additional detail. + */ + +/* offset 0 */ +#define DP_DOWNSTREAM_PORT_0 0x80 +# define DP_DS_PORT_TYPE_MASK (7 << 0) +# define DP_DS_PORT_TYPE_DP 0 +# define DP_DS_PORT_TYPE_VGA 1 +# define DP_DS_PORT_TYPE_DVI 2 +# define DP_DS_PORT_TYPE_HDMI 3 +# define DP_DS_PORT_TYPE_NON_EDID 4 +# define DP_DS_PORT_HPD (1 << 3) +/* offset 1 for VGA is maximum megapixels per second / 8 */ +/* offset 2 */ +# define DP_DS_VGA_MAX_BPC_MASK (3 << 0) +# define DP_DS_VGA_8BPC 0 +# define DP_DS_VGA_10BPC 1 +# define DP_DS_VGA_12BPC 2 +# define DP_DS_VGA_16BPC 3 + +/* link configuration */ +#define DP_LINK_BW_SET 0x100 +# define DP_LINK_BW_1_62 0x06 +# define DP_LINK_BW_2_7 0x0a +# define DP_LINK_BW_5_4 0x14 /* 1.2 */ + +#define DP_LANE_COUNT_SET 0x101 +# define DP_LANE_COUNT_MASK 0x0f +# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) + +#define DP_TRAINING_PATTERN_SET 0x102 +# define DP_TRAINING_PATTERN_DISABLE 0 +# define DP_TRAINING_PATTERN_1 1 +# define DP_TRAINING_PATTERN_2 2 +# define DP_TRAINING_PATTERN_3 3 /* 1.2 */ +# define DP_TRAINING_PATTERN_MASK 0x3 + +# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) +# define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) +# define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) +# define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) +# define DP_LINK_QUAL_PATTERN_MASK (3 << 2) + +# define DP_RECOVERED_CLOCK_OUT_EN (1 << 4) +# define DP_LINK_SCRAMBLING_DISABLE (1 << 5) + +# define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) +# define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) +# define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) +# define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) + +#define DP_TRAINING_LANE0_SET 0x103 +#define DP_TRAINING_LANE1_SET 0x104 +#define DP_TRAINING_LANE2_SET 0x105 +#define DP_TRAINING_LANE3_SET 0x106 + +# define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 +# define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 +# define DP_TRAIN_MAX_SWING_REACHED (1 << 2) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_0 (0 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_1 (1 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_2 (2 << 0) +# define DP_TRAIN_VOLTAGE_SWING_LEVEL_3 (3 << 0) + +# define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_0 (0 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_1 (1 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_2 (2 << 3) +# define DP_TRAIN_PRE_EMPH_LEVEL_3 (3 << 3) + +# define DP_TRAIN_PRE_EMPHASIS_SHIFT 3 +# define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) + +#define DP_DOWNSPREAD_CTRL 0x107 +# define DP_SPREAD_AMP_0_5 (1 << 4) +# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7) /* eDP */ + +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +# define DP_SET_ANSI_8B10B (1 << 0) + +#define DP_I2C_SPEED_CONTROL_STATUS 0x109 /* DPI */ +/* bitmask as for DP_I2C_SPEED_CAP */ + +#define DP_EDP_CONFIGURATION_SET 0x10a /* XXX 1.2? */ + +#define DP_MSTM_CTRL 0x111 /* 1.2 */ +# define DP_MST_EN (1 << 0) +# define DP_UP_REQ_EN (1 << 1) +# define DP_UPSTREAM_IS_SRC (1 << 2) + +#define DP_PSR_EN_CFG 0x170 /* XXX 1.2? */ +# define DP_PSR_ENABLE (1 << 0) +# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) +# define DP_PSR_CRC_VERIFICATION (1 << 2) +# define DP_PSR_FRAME_CAPTURE (1 << 3) + +#define DP_ADAPTER_CTRL 0x1a0 +# define DP_ADAPTER_CTRL_FORCE_LOAD_SENSE (1 << 0) + +#define DP_BRANCH_DEVICE_CTRL 0x1a1 +# define DP_BRANCH_DEVICE_IRQ_HPD (1 << 0) + +#define DP_PAYLOAD_ALLOCATE_SET 0x1c0 +#define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 +#define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 + +#define DP_SINK_COUNT 0x200 +/* prior to 1.2 bit 7 was reserved mbz */ +# define DP_GET_SINK_COUNT(x) ((((x) & 0x80) >> 1) | ((x) & 0x3f)) +# define DP_SINK_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 +# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) +# define DP_AUTOMATED_TEST_REQUEST (1 << 1) +# define DP_CP_IRQ (1 << 2) +# define DP_MCCS_IRQ (1 << 3) +# define DP_DOWN_REP_MSG_RDY (1 << 4) /* 1.2 MST */ +# define DP_UP_REQ_MSG_RDY (1 << 5) /* 1.2 MST */ +# define DP_SINK_SPECIFIC_IRQ (1 << 6) + +#define DP_LANE0_1_STATUS 0x202 +#define DP_LANE2_3_STATUS 0x203 +# define DP_LANE_CR_DONE (1 << 0) +# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) +# define DP_LANE_SYMBOL_LOCKED (1 << 2) + +#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \ + DP_LANE_CHANNEL_EQ_DONE | \ + DP_LANE_SYMBOL_LOCKED) + +#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 + +#define DP_INTERLANE_ALIGN_DONE (1 << 0) +#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6) +#define DP_LINK_STATUS_UPDATED (1 << 7) + +#define DP_SINK_STATUS 0x205 + +#define DP_RECEIVE_PORT_0_STATUS (1 << 0) +#define DP_RECEIVE_PORT_1_STATUS (1 << 1) + +#define DP_ADJUST_REQUEST_LANE0_1 0x206 +#define DP_ADJUST_REQUEST_LANE2_3 0x207 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 +# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 +# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c +# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 +# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 +# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 + +#define DP_TEST_REQUEST 0x218 +# define DP_TEST_LINK_TRAINING (1 << 0) +# define DP_TEST_LINK_VIDEO_PATTERN (1 << 1) +# define DP_TEST_LINK_EDID_READ (1 << 2) +# define DP_TEST_LINK_PHY_TEST_PATTERN (1 << 3) /* DPCD >= 1.1 */ +# define DP_TEST_LINK_FAUX_PATTERN (1 << 4) /* DPCD >= 1.2 */ + +#define DP_TEST_LINK_RATE 0x219 +# define DP_LINK_RATE_162 (0x6) +# define DP_LINK_RATE_27 (0xa) + +#define DP_TEST_LANE_COUNT 0x220 + +#define DP_TEST_PATTERN 0x221 + +#define DP_TEST_CRC_R_CR 0x240 +#define DP_TEST_CRC_G_Y 0x242 +#define DP_TEST_CRC_B_CB 0x244 + +#define DP_TEST_SINK_MISC 0x246 +#define DP_TEST_CRC_SUPPORTED (1 << 5) + +#define DP_TEST_RESPONSE 0x260 +# define DP_TEST_ACK (1 << 0) +# define DP_TEST_NAK (1 << 1) +# define DP_TEST_EDID_CHECKSUM_WRITE (1 << 2) + +#define DP_TEST_EDID_CHECKSUM 0x261 + +#define DP_TEST_SINK 0x270 +#define DP_TEST_SINK_START (1 << 0) + +#define DP_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0 /* 1.2 MST */ +# define DP_PAYLOAD_TABLE_UPDATED (1 << 0) +# define DP_PAYLOAD_ACT_HANDLED (1 << 1) + +#define DP_VC_PAYLOAD_ID_SLOT_1 0x2c1 /* 1.2 MST */ +/* up to ID_SLOT_63 at 0x2ff */ + +#define DP_SOURCE_OUI 0x300 +#define DP_SINK_OUI 0x400 +#define DP_BRANCH_OUI 0x500 + +#define DP_SET_POWER 0x600 +# define DP_SET_POWER_D0 0x1 +# define DP_SET_POWER_D3 0x2 +# define DP_SET_POWER_MASK 0x3 + +#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400 /* 1.2 MST */ +#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600 /* 1.2 MST */ + +#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */ +/* 0-5 sink count */ +# define DP_SINK_COUNT_CP_READY (1 << 6) + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */ + +#define DP_DEVICE_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */ + +#define DP_LINK_SERVICE_IRQ_VECTOR_ESI0 0x2005 /* 1.2 */ + +#define DP_PSR_ERROR_STATUS 0x2006 /* XXX 1.2? */ +# define DP_PSR_LINK_CRC_ERROR (1 << 0) +# define DP_PSR_RFB_STORAGE_ERROR (1 << 1) + +#define DP_PSR_ESI 0x2007 /* XXX 1.2? */ +# define DP_PSR_CAPS_CHANGE (1 << 0) + +#define DP_PSR_STATUS 0x2008 /* XXX 1.2? */ +# define DP_PSR_SINK_INACTIVE 0 +# define DP_PSR_SINK_ACTIVE_SRC_SYNCED 1 +# define DP_PSR_SINK_ACTIVE_RFB 2 +# define DP_PSR_SINK_ACTIVE_SINK_SYNCED 3 +# define DP_PSR_SINK_ACTIVE_RESYNC 4 +# define DP_PSR_SINK_INTERNAL_ERROR 7 +# define DP_PSR_SINK_STATE_MASK 0x07 + +/* DP 1.2 Sideband message defines */ +/* peer device type - DP 1.2a Table 2-92 */ +#define DP_PEER_DEVICE_NONE 0x0 +#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1 +#define DP_PEER_DEVICE_MST_BRANCHING 0x2 +#define DP_PEER_DEVICE_SST_SINK 0x3 +#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4 + +/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */ +#define DP_LINK_ADDRESS 0x01 +#define DP_CONNECTION_STATUS_NOTIFY 0x02 +#define DP_ENUM_PATH_RESOURCES 0x10 +#define DP_ALLOCATE_PAYLOAD 0x11 +#define DP_QUERY_PAYLOAD 0x12 +#define DP_RESOURCE_STATUS_NOTIFY 0x13 +#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14 +#define DP_REMOTE_DPCD_READ 0x20 +#define DP_REMOTE_DPCD_WRITE 0x21 +#define DP_REMOTE_I2C_READ 0x22 +#define DP_REMOTE_I2C_WRITE 0x23 +#define DP_POWER_UP_PHY 0x24 +#define DP_POWER_DOWN_PHY 0x25 +#define DP_SINK_EVENT_NOTIFY 0x30 +#define DP_QUERY_STREAM_ENC_STATUS 0x38 + +/* DP 1.2 MST sideband nak reasons - table 2.84 */ +#define DP_NAK_WRITE_FAILURE 0x01 +#define DP_NAK_INVALID_READ 0x02 +#define DP_NAK_CRC_FAILURE 0x03 +#define DP_NAK_BAD_PARAM 0x04 +#define DP_NAK_DEFER 0x05 +#define DP_NAK_LINK_FAILURE 0x06 +#define DP_NAK_NO_RESOURCES 0x07 +#define DP_NAK_DPCD_FAIL 0x08 +#define DP_NAK_I2C_NAK 0x09 +#define DP_NAK_ALLOCATE_FAIL 0x0a + +#define MODE_I2C_START 1 +#define MODE_I2C_WRITE 2 +#define MODE_I2C_READ 4 +#define MODE_I2C_STOP 8 + +/* Rest of file omitted as it is not used in U-Boot */ + +#endif /* _DRM_DP_HELPER_H_ */ -- cgit v1.2.3 From 00cf1167bb8f7c08825262ee83e77274ff034f0a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:37 -0600 Subject: edid: Add a function to read detailed monitor timings For digital displays (such as EDP LCDs) we would like to read the EDID information and use that to set display timings. Provide a function to do this. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/edid.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'include') diff --git a/include/edid.h b/include/edid.h index 18ec1d5ab0c..88b4b7d8542 100644 --- a/include/edid.h +++ b/include/edid.h @@ -15,6 +15,9 @@ #include +/* Size of the EDID data */ +#define EDID_SIZE 128 + #define GET_BIT(_x, _pos) \ (((_x) >> (_pos)) & 1) #define GET_BITS(_x, _pos_msb, _pos_lsb) \ @@ -287,4 +290,20 @@ int edid_get_ranges(struct edid1_info *edid, unsigned int *hmin, unsigned int *hmax, unsigned int *vmin, unsigned int *vmax); +struct display_timing; + +/** + * edid_get_timing() - Get basic digital display parameters + * + * @param buf Buffer containing EDID data + * @param buf_size Size of buffer in bytes + * @param timing Place to put preferring timing information + * @param panel_bits_per_colourp Place to put the number of bits per + * colour supported by the panel. This will be set to + * -1 if not available + * @return 0 if timings are OK, -ve on error + */ +int edid_get_timing(u8 *buf, int buf_size, struct display_timing *timing, + int *panel_bits_per_colourp); + #endif /* __EDID_H_ */ -- cgit v1.2.3 From 51f2c99e14b28b65b7f66a5cd392fa49c03537aa Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:38 -0600 Subject: dm: video: Add a uclass for display port eDP (Embedded DisplayPort) is a standard widely used in laptops to drive LCD panels. Add a uclass for this which supports a few simple operations. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren --- include/displayport.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/dm/uclass-id.h | 1 + 2 files changed, 61 insertions(+) create mode 100644 include/displayport.h (limited to 'include') diff --git a/include/displayport.h b/include/displayport.h new file mode 100644 index 00000000000..f7c7e252852 --- /dev/null +++ b/include/displayport.h @@ -0,0 +1,60 @@ +/* + * Copyright 2014 Google Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DISPLAYPORT_H +#define _DISPLAYPORT_H + +struct udevice; +struct display_timing; + +/** + * display_port_read_edid() - Read information from EDID + * + * @dev: Device to read from + * @buf: Buffer to read into (should be EDID_SIZE bytes) + * @buf_size: Buffer size (should be EDID_SIZE) + * @return number of bytes read, <=0 for error + */ +int display_port_read_edid(struct udevice *dev, u8 *buf, int buf_size); + +/** + * display_port_enable() - Enable a display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ +int display_port_enable(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); + +struct dm_display_port_ops { + /** + * read_edid() - Read information from EDID + * + * @dev: Device to read from + * @buf: Buffer to read into (should be EDID_SIZE bytes) + * @buf_size: Buffer size (should be EDID_SIZE) + * @return number of bytes read, <=0 for error + */ + int (*read_edid)(struct udevice *dev, u8 *buf, int buf_size); + + /** + * enable() - Enable the display port device + * + * @dev: Device to enable + * @panel_bpp: Number of bits per pixel for panel + * @timing: Display timings + * @return 0 if OK, -ve on error + */ + int (*enable)(struct udevice *dev, int panel_bpp, + const struct display_timing *timing); +}; + +#define display_port_get_ops(dev) \ + ((struct dm_display_port_ops *)(dev)->driver->ops) + +#endif diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index b17528d207c..095bcb22b93 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -27,6 +27,7 @@ enum uclass_id { /* U-Boot uclasses start here - in alphabetical order */ UCLASS_CPU, /* CPU, typically part of an SoC */ UCLASS_CROS_EC, /* Chrome OS EC */ + UCLASS_DISPLAY_PORT, /* Display port video */ UCLASS_ETH, /* Ethernet device */ UCLASS_GPIO, /* Bank of general-purpose I/O pins */ UCLASS_I2C, /* I2C bus */ -- cgit v1.2.3 From 00f37327524d51b46a601fb104e5d6cc0590979a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:40 -0600 Subject: tegra: video: Support serial output resource (SOR) on tegra124 The SOR is required for talking to eDP LCD panels. Add a driver for this which will be used by the DisplayPort driver. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren --- include/fdtdec.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index f304199e1df..6bf5f614e8b 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -130,6 +130,9 @@ enum fdt_compat_id { COMPAT_NVIDIA_TEGRA20_KBC, /* Tegra20 Keyboard */ COMPAT_NVIDIA_TEGRA20_NAND, /* Tegra2 NAND controller */ COMPAT_NVIDIA_TEGRA20_PWM, /* Tegra 2 PWM controller */ + COMPAT_NVIDIA_TEGRA124_DC, /* Tegra 124 Display controller */ + COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */ + COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */ COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */ COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */ COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */ -- cgit v1.2.3 From 531eaedc7a397b34979c6d35e5de7b78d2dddfde Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:43 -0600 Subject: tegra: config: nyan-big: Enable LCD Add the PMIC, LCD settings, PWM and also show the board info at the top of the LCD when starting up. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/nyan-big.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h index 53975999112..caca98b5a96 100644 --- a/include/configs/nyan-big.h +++ b/include/configs/nyan-big.h @@ -21,6 +21,8 @@ #define CONFIG_TEGRA_ENABLE_UARTA #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE +#define CONFIG_DISPLAY_BOARDINFO_LATE + /* I2C */ #define CONFIG_SYS_I2C_TEGRA #define CONFIG_CMD_I2C @@ -37,6 +39,18 @@ #define CONFIG_SYS_MMC_ENV_PART 2 #define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_I2C_EDID + +/* LCD support */ +#define CONFIG_LCD +#define CONFIG_PWM_TEGRA +#define CONFIG_AS3722_POWER +#define LCD_BPP LCD_COLOR16 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* Align LCD to 1MB boundary */ +#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE + /* SPI */ #define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */ #define CONFIG_TEGRA114_SPI_CTRLS 6 -- cgit v1.2.3 From dedc44b466ba24bd4f38840a79067d806d37d709 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 14 Apr 2015 21:03:44 -0600 Subject: tegra124: video: Add full link training for eDP Add full link training as a fallback in case the fast link training fails. Signed-off-by: Simon Glass Acked-by: Anatolij Gustschin Signed-off-by: Tom Warren --- include/linux/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/linux/drm_dp_helper.h b/include/linux/drm_dp_helper.h index 86b06e11ccb..758e4a4015a 100644 --- a/include/linux/drm_dp_helper.h +++ b/include/linux/drm_dp_helper.h @@ -264,6 +264,7 @@ #define DP_LINK_STATUS_UPDATED (1 << 7) #define DP_SINK_STATUS 0x205 +#define DP_SINK_STATUS_PORT0_IN_SYNC (1 << 0) #define DP_RECEIVE_PORT_0_STATUS (1 << 0) #define DP_RECEIVE_PORT_1_STATUS (1 << 1) -- cgit v1.2.3 From 48cfca240db06b2945f23b44e37b9a6018cd40fa Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Wed, 1 Apr 2015 15:40:53 -0600 Subject: ARM: tegra: CONFIG_{SYS_, }LOAD{_, }ADDR rationalization As best I can tell, CONFIG_SYS_LOAD_ADDR and CONFIG_LOADADDR/$loadaddr serve essentially the same purpose. Roughly, if a command takes a load address, then CONFIG_SYS_LOAD_ADDR or $loadaddr (or both) are the default if the command-line does not specify the address. Different U-Boot commands are inconsistent re: which of the two default values they use. As such, set the two to the same value, and move the logic that does this into tegra-common-post.h so it's not duplicated. A number of other non- Tegra boards do this too. The values chosen for these macros are no longer consistent with anything in MEM_LAYOUT_ENV_SETTINGS. Regain consistency by setting $kernel_addr_r to CONFIG_LOADADDR. Older scripts tend to use $loadaddr for the default kernel load address, whereas newer scripts and features tend to use $kernel_addr_r, along with other variables for other purposes such as DTBs and initrds. Hence, it's logical they should share the same value. I had originally thought to make the $kernel_addr_r and CONFIG_LOADADDR have different values. This would guarantee no interference if a script used the two variables for different purposes. However, that scenario is unlikely given the semantic meaning associated with the two variables. The lowest available value is 0x90200000; see comments for MEM_LAYOUT_ENV_SETTINGS in tegra30-common-post.h for details. However, that value would be problematic for a script that loaded a raw zImage to $loadaddr, since it's more than 128MB beyond the start of SDRAM, which would interfere with the kernel's CONFIG_AUTO_ZRELADDR. So, let's not do that. The only potential fallout I could foresee from this patch is if someone has a script that loads the kernel to $loadaddr, but some other file (DTB, initrd) to a hard-coded address that the new value of $loadaddr interferes with. This seems unlikely. A user should not do that; they should either hard-code all load addresses, or use U-Boot-supplied variables for all load addresses. Equally, any fallout due to this change is trivial to fix; simply modify the load addresses in that script. Cc: Paul Walmsley Signed-off-by: Stephen Warren Reviewed-by: Paul Walmsley Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common-post.h | 2 ++ include/configs/tegra114-common.h | 7 ++----- include/configs/tegra124-common.h | 7 ++----- include/configs/tegra20-common.h | 7 ++----- include/configs/tegra30-common.h | 7 ++----- 5 files changed, 10 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index 46a155d4b80..0cea795de1b 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -50,6 +50,8 @@ #define BOARD_EXTRA_ENV_SETTINGS #endif +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + #define CONFIG_EXTRA_ENV_SETTINGS \ TEGRA_DEVICE_SETTINGS \ MEM_LAYOUT_ENV_SETTINGS \ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h index 9eba5d517db..252e607d73f 100644 --- a/include/configs/tegra114-common.h +++ b/include/configs/tegra114-common.h @@ -26,13 +26,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -64,10 +60,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h index f2b3774da8f..1aee5c89f4c 100644 --- a/include/configs/tegra124-common.h +++ b/include/configs/tegra124-common.h @@ -18,13 +18,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -56,10 +52,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 6330281df71..0841f33bfc9 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -24,13 +24,9 @@ */ #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ #define CONFIG_STACKBASE 0x02800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -62,10 +58,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x01000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x10000000\0" \ "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=0x01000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x02000000\0" \ "ramdisk_addr_r=0x02100000\0" diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h index bfdbeb70d29..3e8e3c1e5bd 100644 --- a/include/configs/tegra30-common.h +++ b/include/configs/tegra30-common.h @@ -23,13 +23,9 @@ */ #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ -/* Environment information, boards can override if required */ -#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */ - /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */ #define CONFIG_STACKBASE 0x82800000 /* 40MB */ /*----------------------------------------------------------------------- @@ -61,10 +57,11 @@ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ +#define CONFIG_LOADADDR 0x81000000 #define MEM_LAYOUT_ENV_SETTINGS \ "scriptaddr=0x90000000\0" \ "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=0x81000000\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ "fdt_addr_r=0x82000000\0" \ "ramdisk_addr_r=0x82100000\0" -- cgit v1.2.3 From 86bd20b007daa32c1c20486ec9927ef6241c84bf Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Tue, 14 Apr 2015 08:41:14 -0600 Subject: ARM: tegra: enable STDIO deregistration At the very least when USB keyboard support is enabled, we need to enable CONFIG_SYS_STDIO_DEREGISTER, so the "usb reset" is able to re-scan USB ports and find new devices. Enable it everywhere per request from Simon Glass. Signed-off-by: Stephen Warren Reviewed-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 2cf1f68404b..7ae17923548 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -89,6 +89,9 @@ #define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#ifndef CONFIG_SPL_BUILD +#define CONFIG_SYS_STDIO_DEREGISTER +#endif /* * Miscellaneous configurable options -- cgit v1.2.3 From 21f0fd245e311fdb0d8a79747437595d9fab1536 Mon Sep 17 00:00:00 2001 From: Ian Campbell Date: Tue, 21 Apr 2015 07:18:40 +0200 Subject: jetson-tk1: Add PSCI configuration options and reserve secure code The secure world code is relocated to the MB just below the top of 4G, we reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is not protected in h/w. Signed-off-by: Ian Campbell Signed-off-by: Jan Kiszka Reviewed-by: Tom Rini Reviewed-by: Thierry Reding Tested-by: Thierry Reding Tested-by: Ian Campbell Signed-off-by: Tom Warren --- include/configs/jetson-tk1.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h index 8c016b79551..aeafbd5a6cd 100644 --- a/include/configs/jetson-tk1.h +++ b/include/configs/jetson-tk1.h @@ -79,4 +79,9 @@ #include "tegra-common-usb-gadget.h" #include "tegra-common-post.h" +#define CONFIG_ARMV7_PSCI 1 +/* Reserve top 1M for secure RAM */ +#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 +#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 + #endif /* __CONFIG_H */ -- cgit v1.2.3