From 70ed869ea5f6b1d13d7b140c83ec0dcd8a127ddc Mon Sep 17 00:00:00 2001 From: Vivek Mahajan Date: Tue, 27 Oct 2009 12:18:55 +0530 Subject: ppc/85xx/pci: fsl_pci_init: pcie agent mode support Originally written by Jason Jin and Mingkai Hu for mpc8536. When QorIQ based board is configured as a PCIe agent, then unlock/enable inbound PCI configuration cycles and init a 4K inbound memory window; so that a PCIe host can access the PCIe agents SDRAM at address 0x0 * Supported in fsl_pci_init_port() after adding pcie_ep as a param * Revamped copyright in drivers/pci/fsl_pci_init.c * Mods in 85xx based board specific pci init after this change Signed-off-by: Vivek Mahajan Signed-off-by: Kumar Gala --- include/asm-ppc/fsl_pci.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index 2790da7ed16..6b0c89bd3f3 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -62,6 +62,7 @@ typedef struct pci_inbound_window { #define PIWAR_LOCAL 0x00f00000 #define PIWAR_READ_SNOOP 0x00050000 #define PIWAR_WRITE_SNOOP 0x00005000 +#define PIWAR_IWS_4K 0x0000000b u32 res2[3]; } pit_t; @@ -171,7 +172,7 @@ struct fsl_pci_info { }; int fsl_pci_init_port(struct fsl_pci_info *pci_info, - struct pci_controller *hose, int busno); + struct pci_controller *hose, int busno, int pcie_ep); #define SET_STD_PCI_INFO(x, num) \ { \ -- cgit v1.2.3 From 5ccd29c3679b3669b0bde5c501c1aa0f325a7acb Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 23 Oct 2009 15:55:47 -0500 Subject: 85xx: MP Boot Page Translation update This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/asm-ppc/config.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index eba79010b15..af0853b0d7e 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -47,6 +47,16 @@ #define CONFIG_MAX_CPUS 1 #endif +/* + * Provide a default boot page translation virtual address that lines up with + * Freescale's default e500 reset page. + */ +#if (defined(CONFIG_E500) && defined(CONFIG_MP)) +#ifndef CONFIG_BPTR_VIRT_ADDR +#define CONFIG_BPTR_VIRT_ADDR 0xfffff000 +#endif +#endif + /* Relocation to SDRAM works on all PPC boards */ #define CONFIG_RELOC_FIXUP_WORKS -- cgit v1.2.3 From 48618126f78f05042dae428811809b594f747eb9 Mon Sep 17 00:00:00 2001 From: Peter Tyser Date: Fri, 23 Oct 2009 15:55:48 -0500 Subject: xpedite5370: Enable multi-core support Signed-off-by: Peter Tyser Signed-off-by: Kumar Gala --- include/configs/XPEDITE5370.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 26b798b4d8a..7782df36780 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -48,6 +48,13 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +/* + * Multicore config + */ +#define CONFIG_MP +#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ +#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ + /* * DDR config */ @@ -109,6 +116,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable + * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable -- cgit v1.2.3 From 7f52ed5ef1b490da282ace3316be381a6abf96a5 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 15 Oct 2009 17:47:06 +0400 Subject: mpc85xx: Add eSDHC support for MPC8569E-MDS boards eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 32e747efb35..3d07a5b5dc2 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -70,6 +70,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_ENABLE_36BIT_PHYS 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_HWCONFIG #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 @@ -206,6 +207,7 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 +#define CONFIG_SERIAL_MULTI 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -258,8 +260,10 @@ extern unsigned long get_clock_freq(void); #define PLPPAR1_I2C_BIT_MASK 0x0000000F #define PLPPAR1_I2C2_VAL 0x00000000 +#define PLPPAR1_ESDHC_VAL 0x0000000A #define PLPDIR1_I2C_BIT_MASK 0x0000000F #define PLPDIR1_I2C2_VAL 0x0000000F +#define PLPDIR1_ESDHC_VAL 0x00000006 /* * General PCI @@ -450,6 +454,18 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_MMC 1 + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + /* * Miscellaneous configurable options */ -- cgit v1.2.3 From a29155e12286cc5ec2df72c1cab28e3659bfdad5 Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Thu, 15 Oct 2009 17:47:08 +0400 Subject: mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND. Signed-off-by: Anton Vorontsov Signed-off-by: Kumar Gala --- include/configs/MPC8569MDS.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 3d07a5b5dc2..17ea3bb14ed 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -181,6 +181,29 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO +/* Chip select 3 - NAND */ +#define CONFIG_SYS_NAND_BASE 0xFC000000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ + | (2<