From 9427ba5c279700640419605afb61a13838ba5268 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Tue, 18 Dec 2012 17:23:19 +0000 Subject: boards/T4240qds:Fix IFC AMASK init as per FPGA register space T4240QDS's QIXIS FPGA has 4k register space size and IFC controller's Address Mask Registers is initialised 64K size. So Fix the Address Mask Register initilisation as 4K Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- include/configs/t4qds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index d58c24c4aa4..d93e0263f95 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -259,7 +259,7 @@ unsigned long get_board_ddr_clk(void); | CSPR_PORT_SIZE_8 \ | CSPR_MSEL_GPCM \ | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) #define CONFIG_SYS_CSOR3 0x0 /* QIXIS Timing parameters for IFC CS3 */ #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ -- cgit v1.3.1 From 9730b7bc11580a7fd7bdabbd76224eb1cc14d42a Mon Sep 17 00:00:00 2001 From: York Sun Date: Wed, 19 Dec 2012 17:23:05 +0000 Subject: powerpc/t4240qds: Update IFC timing for NOR flash Relax parameters to give address latching more time to setup. Tighten parameters to make it overall faster. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- include/configs/t4qds.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h index d93e0263f95..2c665b8a9dd 100644 --- a/include/configs/t4qds.h +++ b/include/configs/t4qds.h @@ -213,14 +213,14 @@ unsigned long get_board_ddr_clk(void); /* NOR Flash Timing Params */ #define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ - FTIM0_NOR_TEADC(0x01) | \ - FTIM0_NOR_TEAHC(0x20)) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ FTIM1_NOR_TRAD_NOR(0x1A) |\ FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ - FTIM2_NOR_TCH(0x0E) | \ +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ FTIM2_NOR_TWPH(0x0E) | \ FTIM2_NOR_TWP(0x1c)) #define CONFIG_SYS_NOR_FTIM3 0x0 -- cgit v1.3.1 From 238e14679157c972ccc4de909bfac83f46d0748d Mon Sep 17 00:00:00 2001 From: Hongtao Jia Date: Thu, 20 Dec 2012 19:36:12 +0000 Subject: powerpc/mpc8572ds: Enable bank interleaving to cs0+cs1 for dual-rank DIMMs The controller interleaving only takes the usable memory mapped to cs0. In the case of bank interleaving not enabled, only half of dual-rank DIMM will be used. For single-rank DIMM bank interleaving will be auto disabled. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Andy Fleming --- include/configs/MPC8572DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index a62b7d53a95..d233365b7d0 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -735,7 +735,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ -"hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \ +"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ -- cgit v1.3.1 From 86a194b73383d68ea66b182731c6ae4d884e27b4 Mon Sep 17 00:00:00 2001 From: Hongtao Jia Date: Thu, 20 Dec 2012 19:39:53 +0000 Subject: powerpc/mpc8544ds: Add USB controller support for MPC8544DS USB controller in uboot is a required feature for MPC8544DS. Without this support there is no 'usb' command in uboot. Signed-off-by: Jia Hongtao Signed-off-by: Li Yang Signed-off-by: Andy Fleming --- include/configs/MPC8544DS.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index 83b8668bac8..d5f3c5f56f2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -415,6 +415,18 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CMD_EXT2 #endif +/* + * USB + */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_EHCI_PCI +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_STORAGE +#define CONFIG_PCI_EHCI_DEVICE 0 +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ -- cgit v1.3.1 From b5b06fb7b04a93ea48638d4d2ba1932051a28f64 Mon Sep 17 00:00:00 2001 From: York Sun Date: Sun, 23 Dec 2012 19:25:27 +0000 Subject: powerpc/b4860qds: Added Support for B4860QDS B4860QDS is a high-performance computing evaluation, development and test platform supporting the B4860 QorIQ Power Architecture processor. B4860QDS Overview ------------------ - DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB of memory in two ranks of 2 GB. - DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank. - SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch VSC3316 - SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 - USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. - B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. - A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for AMC mode. - The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The RCW source is set by appropriate DIP-switches: - 16-bit NOR Flash / PROMJet - QIXIS 8-bit NOR Flash Emulator - 8-bit NAND Flash - 24-bit SPI Flash - Long address I2C EEPROM - Available debug interfaces are: - On-board eCWTAP controller with ETH and USB I/F - JTAG/COP 16-pin header for any external TAP controller - External JTAG source over AMC to support B2B configuration - 70-pin Aurora debug connector - QIXIS (FPGA) logic: - 2 KB internal memory space including - IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1, 2 and RTCCLK. - Two 8T49N222A SerDes ref clock devices support two SerDes port clocks - total four refclk, including CPRI clock scheme Signed-off-by: York Sun Signed-off-by: Prabhakar Kushwaha Signed-off-by: Shaveta Leekha Signed-off-by: Priyanka Jain Signed-off-by: Poonam Aggrwal Signed-off-by: Roy Zang Signed-off-by: Sandeep Singh Signed-off-by: Andy Fleming --- board/freescale/b4860qds/Makefile | 54 ++ board/freescale/b4860qds/b4860qds.c | 458 +++++++++++++ board/freescale/b4860qds/b4860qds.h | 26 + board/freescale/b4860qds/b4860qds_crossbar_con.h | 67 ++ board/freescale/b4860qds/b4860qds_qixis.h | 37 + board/freescale/b4860qds/ddr.c | 190 ++++++ board/freescale/b4860qds/eth_b4860qds.c | 338 ++++++++++ board/freescale/b4860qds/law.c | 44 ++ board/freescale/b4860qds/pci.c | 39 ++ board/freescale/b4860qds/tlb.c | 127 ++++ boards.cfg | 6 + doc/README.b4860qds | 330 +++++++++ include/configs/B4860QDS.h | 820 +++++++++++++++++++++++ 13 files changed, 2536 insertions(+) create mode 100644 board/freescale/b4860qds/Makefile create mode 100644 board/freescale/b4860qds/b4860qds.c create mode 100644 board/freescale/b4860qds/b4860qds.h create mode 100644 board/freescale/b4860qds/b4860qds_crossbar_con.h create mode 100644 board/freescale/b4860qds/b4860qds_qixis.h create mode 100644 board/freescale/b4860qds/ddr.c create mode 100644 board/freescale/b4860qds/eth_b4860qds.c create mode 100644 board/freescale/b4860qds/law.c create mode 100644 board/freescale/b4860qds/pci.c create mode 100644 board/freescale/b4860qds/tlb.c create mode 100644 doc/README.b4860qds create mode 100644 include/configs/B4860QDS.h (limited to 'include') diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile new file mode 100644 index 00000000000..06018f49c97 --- /dev/null +++ b/board/freescale/b4860qds/Makefile @@ -0,0 +1,54 @@ +# +# Copyright 2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o +COBJS-$(CONFIG_PCI) += pci.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c new file mode 100644 index 00000000000..88bdc1f65f1 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds.c @@ -0,0 +1,458 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/qixis.h" +#include "../common/vsc3316_3308.h" +#include "b4860qds.h" +#include "b4860qds_qixis.h" +#include "b4860qds_crossbar_con.h" + +#define CLK_MUX_SEL_MASK 0x4 +#define ETH_PHY_CLK_OUT 0x4 + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + char buf[64]; + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + static const char *const freq[] = {"100", "125", "156.25", "161.13", + "122.88", "122.88", "122.88"}; + int clock; + + printf("Board: %sQDS, ", cpu->name); + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ", + QIXIS_READ(id), QIXIS_READ(arch)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + if (sw < 0x8) + printf("vBank: %d\n", sw); + else if (sw >= 0x8 && sw <= 0xE) + puts("NAND\n"); + else + printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + + printf("FPGA: v%d (%s), build %d", + (int)QIXIS_READ(scver), qixis_read_tag(buf), + (int)qixis_read_minor()); + /* the timestamp string contains "\n" at the end */ + printf(" on %s", qixis_read_time(buf)); + + /* Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = QIXIS_READ(brdcfg[2]); + clock = (sw >> 5) & 7; + printf("Bank1=%sMHz ", freq[clock]); + sw = QIXIS_READ(brdcfg[4]); + clock = (sw >> 6) & 3; + printf("Bank2=%sMHz\n", freq[clock]); + + return 0; +} + +int select_i2c_ch_pca(u8 ch) +{ + int ret; + + /* Selecting proper channel via PCA*/ + ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1); + if (ret) { + printf("PCA: failed to select proper channel.\n"); + return ret; + } + + return 0; +} + +int configure_vsc3316_3308(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int num_vsc16_con, num_vsc08_con; + u32 serdes1_prtcl, serdes2_prtcl; + int ret; + + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return 0; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + printf("SERDES2 is not enabled\n"); + return 0; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + switch (serdes1_prtcl) { + case 0x2a: + case 0x2C: + case 0x2D: + case 0x2E: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B: SGMII + * Lanes: C,D,E,F,G,H: CPRI + */ + debug("Configuring crossbar to use onboard SGMII PHYs:" + "srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sgmii_lane_ab, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sgmii_lane_ab, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + +#ifdef CONFIG_PPC_B4420 + case 0x18: + /* + * Configuration: + * SERDES: 1 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F,G,H: CPRI + */ + debug("Configuring crossbar to use onboard SGMII PHYs:" + "srds_prctl:%x\n", serdes1_prtcl); + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sgmii_lane_cd, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sgmii_lane_cd, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; +#endif + + case 0x3E: + case 0x0D: + case 0x0E: + case 0x12: + num_vsc16_con = NUM_CON_VSC3316; + /* Configure VSC3316 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3316); + if (!ret) { + ret = vsc3316_config(VSC3316_TX_ADDRESS, + vsc16_tx_sfp, num_vsc16_con); + if (ret) + return ret; + ret = vsc3316_config(VSC3316_RX_ADDRESS, + vsc16_rx_sfp, num_vsc16_con); + if (ret) + return ret; + } else { + return ret; + } + break; + default: + printf("WARNING:VSC crossbars programming not supported for:%x" + " SerDes1 Protocol.\n", serdes1_prtcl); + return -1; + } + + switch (serdes2_prtcl) { + case 0x9E: + case 0x9A: + case 0x98: + case 0xb2: + case 0x49: + case 0x4E: + case 0x8D: + case 0x7A: + num_vsc08_con = NUM_CON_VSC3308; + /* Configure VSC3308 crossbar switch */ + ret = select_i2c_ch_pca(I2C_CH_VSC3308); + if (!ret) { + ret = vsc3308_config(VSC3308_TX_ADDRESS, + vsc08_tx_amc, num_vsc08_con); + if (ret) + return ret; + ret = vsc3308_config(VSC3308_RX_ADDRESS, + vsc08_rx_amc, num_vsc08_con); + if (ret) + return ret; + } else { + return ret; + } + break; + default: + printf("WARNING:VSC crossbars programming not supported for: %x" + " SerDes2 Protocol.\n", serdes2_prtcl); + return -1; + } + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_256M, 1); + + set_liodns(); +#ifdef CONFIG_SYS_DPAA_QBMAN + setup_portals(); +#endif + + /* Configure VSC3316 and VSC3308 crossbar switches */ + if (configure_vsc3316_3308()) + printf("VSC:failed to configure VSC3316/3308.\n"); + else + printf("VSC:VSC3316/3308 successfully configured.\n"); + + select_i2c_ch_pca(I2C_CH_DEFAULT); + + return 0; +} + +unsigned long get_board_sys_clk(void) +{ + u8 sysclk_conf = QIXIS_READ(brdcfg[1]); + + switch ((sysclk_conf & 0x0C) >> 2) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +unsigned long get_board_ddr_clk(void) +{ + u8 ddrclk_conf = QIXIS_READ(brdcfg[1]); + + switch (ddrclk_conf & 0x03) { + case QIXIS_CLK_100: + return 100000000; + case QIXIS_CLK_125: + return 125000000; + case QIXIS_CLK_133: + return 133333333; + } + return 66666666; +} + +static int serdes_refclock(u8 sw, u8 sdclk) +{ + unsigned int clock; + int ret = -1; + u8 brdcfg4; + + if (sdclk == 1) { + brdcfg4 = QIXIS_READ(brdcfg[4]); + if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT) + return SRDS_PLLCR0_RFCK_SEL_125; + else + clock = (sw >> 5) & 7; + } else + clock = (sw >> 6) & 3; + + switch (clock) { + case 0: + ret = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + ret = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + ret = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + case 3: + ret = SRDS_PLLCR0_RFCK_SEL_161_13; + break; + case 4: + case 5: + case 6: + ret = SRDS_PLLCR0_RFCK_SEL_122_88; + break; + default: + ret = -1; + break; + } + + return ret; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + case SRDS_PLLCR0_RFCK_SEL_161_13: + return "161.13"; + default: + return "122.88"; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + u8 sw; + serdes_corenet_t *srds_regs = + (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + int clock; + + sw = QIXIS_READ(brdcfg[2]); + clock = serdes_refclock(sw, 1); + if (clock >= 0) + actual[0] = clock; + else + printf("Warning: SDREFCLK1 switch setting is unsupported\n"); + + sw = QIXIS_READ(brdcfg[4]); + clock = serdes_refclock(sw, 2); + if (clock >= 0) + actual[1] = clock; + else + printf("Warning: SDREFCLK2 switch setting unsupported\n"); + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 pllcr0 = srds_regs->bank[i].pllcr0; + u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); + +#ifdef CONFIG_HAS_FSL_DR_USB + fdt_fixup_dr_usb(blob, bd); +#endif + +#ifdef CONFIG_SYS_DPAA_FMAN + fdt_fixup_fman_ethernet(blob); + fdt_fixup_board_enet(blob); +#endif +} diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h new file mode 100644 index 00000000000..f290f3ca169 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds.h @@ -0,0 +1,26 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CORENET_DS_H__ +#define __CORENET_DS_H__ + +void fdt_fixup_board_enet(void *blob); +void pci_of_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h new file mode 100644 index 00000000000..994dec570e2 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h @@ -0,0 +1,67 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CROSSBAR_CONNECTIONS_H__ +#define __CROSSBAR_CONNECTIONS_H__ + +#define NUM_CON_VSC3316 8 +#define NUM_CON_VSC3308 4 + +static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, + {5, 11}, {4, 5}, {2, 6}, {12, 9} }; + +static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1}, + {5, 15}, {4, 14}, {2, 12}, {12, 13} }; + +static const int8_t vsc16_tx_sgmii_lane_ab[8][2] = { {2, 14}, {12, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif +static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, + {11, 11}, {5, 10}, {6, 3}, {9, 12} }; + +static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc16_rx_sgmii_lane_ab[8][2] = { {14, 3}, {15, 12}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +#ifdef CONFIG_PPC_B4420 +static const int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; +#endif + +static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1}, + {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; + +static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; + +static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} }; + +static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; + +static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} }; + +#endif diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h new file mode 100644 index 00000000000..575b2ae7790 --- /dev/null +++ b/board/freescale/b4860qds/b4860qds_qixis.h @@ -0,0 +1,37 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __B4860QDS_QIXIS_H__ +#define __B4860QDS_QIXIS_H__ + +/* Definitions of QIXIS Registers for B4860QDS */ + +/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ +#define BRDCFG4_EMISEL_MASK 0xE0 +#define BRDCFG4_EMISEL_SHIFT 5 + +/* CLK */ +#define QIXIS_CLK_66 0x0 +#define QIXIS_CLK_100 0x1 +#define QIXIS_CLK_125 0x2 +#define QIXIS_CLK_133 0x3 + +#define QIXIS_SRDS1CLK_122 0x5a +#define QIXIS_SRDS1CLK_125 0x5e +#endif diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c new file mode 100644 index 00000000000..dd4c0f69e1d --- /dev/null +++ b/board/freescale/b4860qds/ddr.c @@ -0,0 +1,190 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 or later as published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +dimm_params_t ddr_raw_timing = { + .n_ranks = 2, + .rank_density = 2147483648u, + .capacity = 4294967296u, + .primary_sdram_width = 64, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 1, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, /* ECC */ + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1071, + .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */ + .tAA_ps = 13910, + .tWR_ps = 15000, + .tRCD_ps = 13910, + .tRRD_ps = 6000, + .tRP_ps = 13910, + .tRAS_ps = 34000, + .tRC_ps = 48910, + .tRFC_ps = 260000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 35000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "RAW timing DDR"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +struct board_specific_parameters { + u32 n_ranks; + u32 datarate_mhz_high; + u32 clk_adjust; + u32 wrlvl_start; + u32 wrlvl_ctl_2; + u32 wrlvl_ctl_3; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +}; + +/* + * This table contains all valid speeds we want to override with board + * specific parameters. datarate_mhz_high values need to be in ascending order + * for each n_ranks group. + */ +static const struct board_specific_parameters udimm0[] = { + /* + * memory controller 0 + * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T + * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay | + */ + {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, + {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, + {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, + {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0}, + {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0}, + {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0}, + {} +}; + +static const struct board_specific_parameters *udimms[] = { + udimm0, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; + ulong ddr_freq; + + if (ctrl_num > 2) { + printf("Not supported controller number %d\n", ctrl_num); + return; + } + if (!pdimm->n_ranks) + return; + + pbsp = udimms[0]; + + + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + while (pbsp->datarate_mhz_high) { + if (pbsp->n_ranks == pdimm->n_ranks) { + if (ddr_freq <= pbsp->datarate_mhz_high) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = + pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2; + popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3; + popts->twoT_en = pbsp->force_2T; + goto found; + } + pbsp_highest = pbsp; + } + pbsp++; + } + + if (pbsp_highest) { + printf("Error: board specific timing not found " + "for data rate %lu MT/s\n" + "Trying to use the highest speed (%u) parameters\n", + ddr_freq, pbsp_highest->datarate_mhz_high); + popts->cpo_override = pbsp_highest->cpo; + popts->write_data_delay = pbsp_highest->write_data_delay; + popts->clk_adjust = pbsp_highest->clk_adjust; + popts->wrlvl_start = pbsp_highest->wrlvl_start; + popts->twoT_en = pbsp_highest->force_2T; + } else { + panic("DIMM is not supported by this board"); + } +found: + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* + * Write leveling override + */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* + * Rtt and Rtt_WR override + */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 75 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm); + popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm); +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size; + + puts("Initializing....using SPD\n"); + + dram_size = fsl_ddr_sdram(); + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c new file mode 100644 index 00000000000..68e2725fce9 --- /dev/null +++ b/board/freescale/b4860qds/eth_b4860qds.c @@ -0,0 +1,338 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Author: Sandeep Kumar Singh + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII + * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board. + * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only + * one Fman device on B4860. The SERDES configuration is used to determine + * where the SGMII and XAUI cards exist, and also which Fman MACs are routed + * to which PHYs. So for a given Fman MAC, there is one and only PHY it + * connects to. MACs cannot be routed to PHYs dynamically. This configuration + * is done at boot time by reading SERDES protocol from RCW. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/ngpixis.h" +#include "../common/fman.h" +#include "../common/qixis.h" +#include "b4860qds_qixis.h" + +#define EMI_NONE 0xFFFFFFFF + +#ifdef CONFIG_FMAN_ENET + +/* + * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that + * lane at index is mapped to slot number n. A value of '0' will mean + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 0, 0, 0, 0, + 0, 0, 0, 0, + 1, 1, 1, 1, + 0, 0, 0, 0 +}; + +/* + * This function initializes the lane_to_slot[] array. It reads RCW to check + * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes + * lane_to_slot[] accordingly + */ +static void initialize_lane_to_slot(void) +{ + unsigned int serdes2_prtcl; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Initializing lane to slot: Serdes2 protocol: %x\n", + serdes2_prtcl); + + switch (serdes2_prtcl) { + case 0x18: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F: Aur + * Lanes: G,H: SRIO + */ + case 0x91: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: SGMII + * Lanes: C,D: SRIO2 + * Lanes: E,F,G,H: XAUI2 + */ + case 0x93: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: SGMII + * Lanes: E,F,G,H: XAUI2 + */ + case 0x98: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: XAUI2 + * Lanes: E,F,G,H: XAUI2 + */ + case 0x9a: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: PCI + * Lanes: C,D: SGMII + * Lanes: E,F,G,H: XAUI2 + */ + case 0x9e: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: PCI + * Lanes: E,F,G,H: XAUI2 + */ + case 0xb2: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B,C,D: PCI + * Lanes: E,F: SGMII 3&4 + * Lanes: G,H: XFI + */ + case 0xc2: + /* + * Configuration: + * SERDES: 2 + * Lanes: A,B: SGMII + * Lanes: C,D: SRIO2 + * Lanes: E,F,G,H: XAUI2 + */ + lane_to_slot[12] = 2; + lane_to_slot[13] = lane_to_slot[12]; + lane_to_slot[14] = lane_to_slot[12]; + lane_to_slot[15] = lane_to_slot[12]; + break; + + default: + printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + break; + } + return; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct memac_mdio_info memac_mdio_info; + struct memac_mdio_info tg_memac_mdio_info; + unsigned int i; + unsigned int serdes1_prtcl, serdes2_prtcl; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + serdes1_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS1_PRTCL; + if (!serdes1_prtcl) { + printf("SERDES1 is not enabled\n"); + return 0; + } + serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT; + debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl); + + serdes2_prtcl = in_be32(&gur->rcwsr[4]) & + FSL_CORENET2_RCWSR4_SRDS2_PRTCL; + if (!serdes2_prtcl) { + printf("SERDES2 is not enabled\n"); + return 0; + } + serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; + debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl); + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR; + memac_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fm_memac_mdio_init(bis, &memac_mdio_info); + + tg_memac_mdio_info.regs = + (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_memac_mdio_init(bis, &tg_memac_mdio_info); + + /* + * Program the two on board DTSEC PHY addresses assuming that they are + * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and + * 6 to on board SGMII phys + */ + fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + + switch (serdes1_prtcl) { + case 0x2a: + /* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */ + debug("Setting phy addresses for FM1_DTSEC5: %x and" + "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + /* Fixing Serdes clock by programming FPGA register */ + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + fm_info_set_phy_address(FM1_DTSEC5, + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC6, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + break; +#ifdef CONFIG_PPC_B4420 + case 0x18: + /* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */ + debug("Setting phy addresses for FM1_DTSEC3: %x and" + "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + /* Fixing Serdes clock by programming FPGA register */ + QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC5_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC6_PHY_ADDR); + break; +#endif + default: + printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n", + serdes1_prtcl); + break; + } + switch (serdes2_prtcl) { + case 0x18: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC1, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR); + break; + case 0x49: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC1, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR); + break; + case 0x8d: + case 0xb2: + debug("Setting phy addresses on SGMII Riser card for" + "FM1_DTSEC ports: \n"); + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR); + break; + default: + printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n", + serdes2_prtcl); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + fm_info_set_mdio(i, + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} + +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + int phy; + char alias[32]; + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + phy = fm_info_get_phy_address(port); + + sprintf(alias, "phy_sgmii_%x", phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + } +} + +void fdt_fixup_board_enet(void *fdt) +{ + int i; + char alias[32]; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_NONE: + sprintf(alias, "ethernet%u", i); + fdt_status_disabled_by_alias(fdt, alias); + break; + default: + break; + } + } +} diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c new file mode 100644 index 00000000000..4142e014d6f --- /dev/null +++ b/board/freescale/b4860qds/law.c @@ -0,0 +1,44 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN), +#endif + SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), +#endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c new file mode 100644 index 00000000000..b130d130374 --- /dev/null +++ b/board/freescale/b4860qds/pci.c @@ -0,0 +1,39 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c new file mode 100644 index 00000000000..373cb7848cb --- /dev/null +++ b/board/freescale/b4860qds/tlb.c @@ -0,0 +1,127 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_64K, 1), + + /* Bman/Qman */ +#ifdef CONFIG_SYS_BMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_QMAN_MEM_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_16M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_16M, 1), +#endif +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_4M, 1), +#endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 11, BOOKE_PAGESZ_64K, 1), +#endif + SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_4K, 1), + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 6d71f18ffe5..0a2ed40973f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -862,6 +862,12 @@ stxssa_4M powerpc mpc85xx stxssa stx T4240QDS powerpc mpc85xx t4qds freescale T4240QDS_SDCARD powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 T4240QDS_SPIFLASH powerpc mpc85xx t4qds freescale - T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +B4860QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860 +B4860QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +B4860QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4860,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +B4420QDS powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420 +B4420QDS_NAND powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 +B4420QDS_SPIFLASH powerpc mpc85xx b4860qds freescale - B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 xpedite520x powerpc mpc85xx - xes xpedite537x powerpc mpc85xx - xes xpedite550x powerpc mpc85xx - xes diff --git a/doc/README.b4860qds b/doc/README.b4860qds new file mode 100644 index 00000000000..f6c5ff8e9c8 --- /dev/null +++ b/doc/README.b4860qds @@ -0,0 +1,330 @@ +Overview +-------- +The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants). + +B4860 Overview +------------- +The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on +StarCore and Power Architecture® cores. It targets the broadband wireless +infrastructure and builds upon the proven success of the existing multicore +DSPs and Power CPUs. It is designed to bolster the rapidly changing and +expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS. + +The B4860 is a highly-integrated StarCore and Power Architecture processor that +contains: +. Six fully-programmable StarCore SC3900 FVP subsystems, divided into three +clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for +wireless base station applications +. Four dual-thread e6500 Power Architecture processors organized in one cluster-each +core runs up to 1.8 GHz +. Two DDR3/3L controllers for high-speed, industry-standard memory interface each +runs at up to 1866.67 MHz +. MAPLE-B3 hardware acceleration-for forward error correction schemes including +Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE +equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and +FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate +acceleration +. CoreNet fabric that fully supports coherency using MESI protocol between the + e6500 cores, SC3900 FVP cores, memories and external interfaces. + CoreNet fabric interconnect runs at 667 MHz and supports coherent and + non-coherent out of order transactions with prioritization and bandwidth + allocation amongst CoreNet endpoints. +. Data Path Acceleration Architecture, which includes the following: +. Frame Manager (FMan), which supports in-line packet parsing and general + classification to enable policing and QoS-based packet distribution +. Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading + of queue management, task management, load distribution, flow ordering, buffer + management, and allocation tasks from the cores +. Security engine (SEC 5.3)-crypto-acceleration for protocols such as IPsec, + SSL, and 802.16 +. RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound and + outbound). Supports types 5, 6 (outbound only) +. Large internal cache memory with snooping and stashing capabilities for + bandwidth saving and high utilization of processor elements. The 9856-Kbyte + internal memory space includes the following: +. 32 Kbyte L1 ICache per e6500/SC3900 core +. 32 Kbyte L1 DCache per e6500/SC3900 core +. 2048 Kbyte unified L2 cache for each SC3900 FVP cluster +. 2048 Kbyte unified L2 cache for the e6500 cluster +. Two 512 Kbyte shared L3 CoreNet platform caches (CPC) +. Sixteen 10-GHz SerDes lanes serving: +. Two Serial RapidIO interfaces. + - Each supports up to 4 lanes and a total of up to 8 lanes +. Up to 8-lanes Common Public Radio Interface (CPRI) controller for glue-less + antenna connection +. Two 10-Gbit Ethernet controllers (10GEC) +. Six 1G/2.5-Gbit Ethernet controllers for network communications +. PCI Express controller +. Debug (Aurora) +. Two OCeaN DMAs +. Various system peripherals +. 182 32-bit timers + +B4860QDS Overview +------------------ +- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 4 GB + of memory in two ranks of 2 GB. +- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB + of memory. Single rank. +- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point 16x16 switch + VSC3316 +- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point 8x8 switch VSC3308 +- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode. + B4860 UART port is available over USB-to-UART translator USB2SER or over RS232 flat cable. +- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper connectors + for Stand-alone mode and to the 1000Base-X over AMC MicroTCA connector ports 0 and 2 for + AMC mode. +- The B4860 configuration may be loaded from nine bits coded reset configuration reset source. The + RCW source is set by appropriate DIP-switches: +- 16-bit NOR Flash / PROMJet +- QIXIS 8-bit NOR Flash Emulator +- 8-bit NAND Flash +- 24-bit SPI Flash +- Long address I2C EEPROM +- Available debug interfaces are: + - On-board eCWTAP controller with ETH and USB I/F + - JTAG/COP 16-pin header for any external TAP controller + - External JTAG source over AMC to support B2B configuration + - 70-pin Aurora debug connector +- QIXIS (FPGA) logic: + - 2 KB internal memory space including +- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK, DDRCLK1,2 and + RTCCLK. +- Two 8T49N222A SerDes ref clock devices support two SerDes port clock frequency - total four + refclk, including CPRI clock scheme. + +B4420 Personality +-------------------- + +B4420 Personality +-------------------- +B4420 is a reduced personality of B4860 with less core/clusters(both SC3900 and e6500), less DDR +controllers, less serdes lanes, less SGMII interfaces and reduced target frequencies. + +Key differences between B4860 and B4420 +---------------------------------------- + +B4420 has: +1. Less e6500 cores: 1 cluster with 2 e6500 cores +2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster. +3. Single DDRC +4. 2X 4 lane serdes +5. 3 SGMII interfaces +6. no sRIO +7. no 10G + +B4860QDS Default Settings +------------------------- + +Switch Settings +---------------- + +SW1 OFF [0] OFF [1] OFF [1] OFF [0] OFF [1] OFF [0] OFF [1] OFF [1] +SW2 ON ON ON ON ON ON OFF OFF +SW3 OFF OFF OFF ON OFF OFF ON OFF +SW5 OFF OFF OFF OFF OFF OFF ON ON + +Note: PCIe slots modes: All the PCIe devices work as Root Complex. +Note: Boot location: NOR flash. + +SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple +66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz + +a) NAND boot + SW1 [1.1] = 0 + SW2 [1.1] = 1 + SW3 [1:4] = 0001 +b) NOR boot + SW1 [1.1] = 1 + SW2 [1.1] = 0 + SW3 [1:4] = 1000. + +B4420QDS Default Settings +------------------------- + +Switch Settings +---------------- +SW1 OFF[0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] OFF [0] +SW2 ON OFF ON OFF ON ON OFF OFF +SW3 OFF OFF OFF ON OFF OFF ON OFF +SW5 OFF OFF OFF OFF OFF OFF ON ON + +Note: PCIe slots modes: All the PCIe devices work as Root Complex. +Note: Boot location: NOR flash. + +SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple +66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz + +a) NAND boot + SW1 [1.1] = 0 + SW2 [1.1] = 1 + SW3 [1:4] = 0001 +b) NOR boot + SW1 [1.1] = 1 + SW2 [1.1] = 0 + SW3 [1:4] = 1000. + +Memory map on B4860QDS +---------------------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB +0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB +0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB +0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB +0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB +0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB +0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB +0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB +0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB +0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB +0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB +0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB +0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB +0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB +0xF_0000_0000 0xF_003F_FFFF DCSR 4 MB +0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB +0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB +0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB +0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB +0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB +0x0_8000_0000 0x0_FFFF_FFFF DDRC1 2 GB +0x0_0000_0000 0x0_7FFF_FFFF DDRC2 2 GB + +Memory map on B4420QDS +---------------------- +The addresses in brackets are physical addresses. + +Start Address End Address Description Size +0xF_FFDF_1000 0xF_FFFF_FFFF Free 2 MB +0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4 KB +0xF_FF81_0000 0xF_FFDE_FFFF Free 5 MB +0xF_FF80_0000 0xF_FF80_FFFF IFC NAND Flash 64 KB +0xF_FF00_0000 0xF_FF7F_FFFF Free 8 MB +0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16 MB +0xF_F801_0000 0xF_FDFF_FFFF Free 95 MB +0xF_F800_0000 0xF_F800_FFFF PCIe I/O Space 64 KB +0xF_F600_0000 0xF_F7FF_FFFF QMAN s/w portal 32 MB +0xF_F400_0000 0xF_F5FF_FFFF BMAN s/w portal 32 MB +0xF_F000_0000 0xF_F3FF_FFFF Free 64 MB +0xF_E800_0000 0xF_EFFF_FFFF IFC NOR Flash 128 MB +0xF_E000_0000 0xF_E7FF_FFFF Promjet 128 MB +0xF_A0C0_0000 0xF_DFFF_FFFF Free 1012 MB +0xF_A000_0000 0xF_A0BF_FFFF MAPLE0/1/2 12 MB +0xF_0040_0000 0xF_9FFF_FFFF Free 12 GB +0xF_0000_0000 0xF_003F_FFFF DCSR 4 MB +0xC_4000_0000 0xE_FFFF_FFFF Free 11 GB +0xC_3000_0000 0xC_3FFF_FFFF sRIO-2 I/O 256 MB +0xC_2000_0000 0xC_2FFF_FFFF sRIO-1 I/O 256 MB +0xC_0000_0000 0xC_1FFF_FFFF PCIe Mem Space 512 MB +0x1_0000_0000 0xB_FFFF_FFFF Free 44 GB +0x0_0000_0000 0x0_FFFF_FFFF DDRC1 4 GB + + +NOR Flash memory Map on B4860 and B4420QDS +------------------------------------------ + Start End Definition Size +0xEFF80000 0xEFFFFFFF u-boot (current bank) 512KB +0xEFF60000 0xEFF7FFFF u-boot env (current bank) 128KB +0xEFF40000 0xEFF5FFFF FMAN Ucode (current bank) 128KB +0xEF300000 0xEFF3FFFF rootfs (alternate bank) 12MB + 256KB +0xEE800000 0xEE8FFFFF device tree (alternate bank) 1MB +0xEE020000 0xEE6FFFFF Linux.uImage (alternate bank) 6MB+896KB +0xEE000000 0xEE01FFFF RCW (alternate bank) 128KB +0xEDF80000 0xEDFFFFFF u-boot (alternate bank) 512KB +0xEDF60000 0xEDF7FFFF u-boot env (alternate bank) 128KB +0xEDF40000 0xEDF5FFFF FMAN ucode (alternate bank) 128KB +0xED300000 0xEDF3FFFF rootfs (current bank) 12MB+256MB +0xEC800000 0xEC8FFFFF device tree (current bank) 1MB +0xEC020000 0xEC6FFFFF Linux.uImage (current bank) 6MB+896KB +0xEC000000 0xEC01FFFF RCW (current bank) 128KB + +Various Software configurations/environment variables/commands +-------------------------------------------------------------- +The below commands apply to both B4860QDS and B4420QDS. + +1. U-boot environment variable hwconfig + The default hwconfig is: + hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1: + dr_mode=host,phy_type=ulpi + Note: For USB gadget set "dr_mode=peripheral" + +2. FMAN Ucode versions + fsl_fman_ucode_B4860_106_3_6.bin + +3. Switching to alternate bank + Commands for switching to alternate bank. + + 1. To change from vbank0 to vbank2 + => qixis_reset altbank (it will boot using vbank2) + + 2.To change from vbank2 to vbank0 + => qixis reset (it will boot using vbank0) + +4. To change personality of board + For changing personality from B4860 to B4420 + 1)Boot from vbank0 + 2)Flash vbank2 with b4420 rcw and u-boot + 3)Give following commands to uboot prompt + => mw.b ffdf0040 0x30; + => mw.b ffdf0010 0x00; + => mw.b ffdf0062 0x02; + => mw.b ffdf0050 0x02; + => mw.b ffdf0010 0x30; + => reset + + Note: Power off cycle will lead to default switch settings. + Note: 0xffdf0000 is the address of the QIXIS FPGA. + +5. Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND) + + To change from NOR to NAND boot give following command on uboot prompt + => mw.b ffdf0040 0x30 + => mw.b ffdf0010 0x00 + => mw.b 0xffdf0050 0x08 + => mw.b 0xffdf0060 0x82 + => mw.b ffdf0061 0x00 + => mw.b ffdf0010 0x30 + => reset + + To change from NAND to NOR boot give following command on uboot prompt: + => mw.b ffdf0040 0x30 + => mw.b ffdf0010 0x00 + => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2) + => mw.b 0xffdf0060 0x12 + => mw.b ffdf0061 0x01 + => mw.b ffdf0010 0x30 + => reset + + Note: Power off cycle will lead to default switch settings. + Note: 0xffdf0000 is the address of the QIXIS FPGA. + +6. Ethernet interfaces for B4860QDS + Serdes protocosl tested: + 0x2a, 0x8d (serdes1, serdes2) [DEFAULT] + 0x2a, 0xb2 (serdes1, serdes2) + + When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G + SGMII on SGMII riser card. + Under U-boot these network interfaces are recognized as: + FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6. + + On Linux the interfaces are renamed as: + . eth2 -> fm1-gb2 + . eth3 -> fm1-gb3 + . eth4 -> fm1-gb4 + . eth5 -> fm1-gb5 + +7. RCW and Ethernet interfaces for B4420QDS + Serdes protocosl tested: + 0x18, 0x9e (serdes1, serdes2) + + Under U-boot these network interfaces are recognized as: + FM1@DTSEC3, FM1@DTSEC4 and e1000#0. + + On Linux the interfaces are renamed as: + . eth2 -> fm1-gb2 + . eth3 -> fm1-gb3 diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h new file mode 100644 index 00000000000..b09119a2f24 --- /dev/null +++ b/include/configs/B4860QDS.h @@ -0,0 +1,820 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * B4860 QDS board configuration file + */ +#define CONFIG_B4860QDS +#define CONFIG_PHYS_64BIT + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E6500 +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#ifndef CONFIG_PPC_B4420 +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +/* I2C bus multiplexer */ +#define I2C_MUX_PCA_ADDR 0x77 + +/* VSC Crossbar switches */ +#define CONFIG_VSC_CROSSBAR +#define I2C_CH_DEFAULT 0x8 +#define I2C_CH_VSC3316 0xc +#define I2C_CH_VSC3308 0xd + +#define VSC3316_TX_ADDRESS 0x70 +#define VSC3316_RX_ADDRESS 0x71 +#define VSC3308_TX_ADDRESS 0x02 +#define VSC3308_RX_ADDRESS 0x03 + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE +#endif + +#ifndef CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SPIFLASH) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET (512 * 1097) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE +#define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif +#else /* CONFIG_SYS_NO_FLASH */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#ifndef __ASSEMBLY__ +unsigned long get_board_sys_clk(void); +unsigned long get_board_ddr_clk(void); +#endif +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_DDR_ECC +#ifdef CONFIG_DDR_ECC +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef +#endif + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#if 0 +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#endif +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */ +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_FSL_DDR3 +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x51 +#define SPD_EEPROM_ADDRESS2 0x53 + +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 +#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) +#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) +/* NOR Flash Timing Params */ +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ + FTIM0_NOR_TEADC(0x01) | \ + FTIM0_NOR_TEAHC(0x20)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ + FTIM1_NOR_TRAD_NOR(0x1A) |\ + FTIM1_NOR_TSEQRAD_NOR(0x13)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ + FTIM2_NOR_TCH(0x0E) | \ + FTIM2_NOR_TWPH(0x0E) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ + + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_FSL_QIXIS /* use common QIXIS code */ +#define CONFIG_FSL_QIXIS_V2 +#define QIXIS_BASE 0xffdf0000 +#ifdef CONFIG_PHYS_64BIT +#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) +#else +#define QIXIS_BASE_PHYS QIXIS_BASE +#endif +#define QIXIS_LBMAP_SWITCH 0x01 +#define QIXIS_LBMAP_MASK 0x0f +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x02 +#define QIXIS_RST_CTL_RESET 0x31 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_CSPR3_EXT (0xf) +#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK3 IFC_AMASK(4 * 1024) +#define CONFIG_SYS_CSOR3 0x0 +/* QIXIS Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS3_FTIM3 0x0 + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_CSPR_EXT (0xf) +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* ONFI NAND Flash mode0 Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ + FTIM0_NAND_TWP(0x18) | \ + FTIM0_NAND_TWCHT(0x07) | \ + FTIM0_NAND_TWH(0x0a)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ + FTIM1_NAND_TWBE(0x39) | \ + FTIM1_NAND_TRR(0x0e) | \ + FTIM1_NAND_TRP(0x18)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x1e)) +#define CONFIG_SYS_NAND_FTIM3 0x0 + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#if defined(CONFIG_NAND) +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 +#else +#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT +#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 +#endif +#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000 +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe0ec000 /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed in Hz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x119000 + +/* + * RTC configuration + */ +#define RTC +#define CONFIG_RTC_DS3231 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * RapidIO + */ +#ifdef CONFIG_SYS_SRIO +#ifdef CONFIG_SRIO1 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ +#endif + +#ifdef CONFIG_SRIO2 +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +#endif +#endif + +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull +/* + * for slave UCODE and ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull +#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ + +/* slave core release by master*/ +#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ + +/* + * SRIO_PCIE_BOOT - SLAVE + */ +#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) +#endif + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#ifndef CONFIG_NOBQFMAN +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 25 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 25 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 + +#define CONFIG_SYS_DPAA_FMAN + +/* Default address of microcode for the Linux Fman driver */ +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 +#endif +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) +#endif /* CONFIG_NOBQFMAN */ + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS +#define SGMII_CARD_PORT1_PHY_ADDR 0x1C +#define SGMII_CARD_PORT2_PHY_ADDR 0x10 +#define SGMII_CARD_PORT3_PHY_ADDR 0x1E +#define SGMII_CARD_PORT4_PHY_ADDR 0x11 +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10 +#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11 +#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_HAS_FSL_DR_USB + +#ifdef CONFIG_HAS_FSL_DR_USB +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 +#endif +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks*/ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE ulpi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=null," \ + "bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=b4860qds/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=b4860qds/b4860qds.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +/* For emulation this causes u-boot to jump to the start of the proof point + app code automatically */ +#define CONFIG_PROOF_POINTS \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x29000000 - - -;" \ + "cpu 2 release 0x29000000 - - -;" \ + "cpu 3 release 0x29000000 - - -;" \ + "cpu 4 release 0x29000000 - - -;" \ + "cpu 5 release 0x29000000 - - -;" \ + "cpu 6 release 0x29000000 - - -;" \ + "cpu 7 release 0x29000000 - - -;" \ + "go 0x29000000" + +#define CONFIG_HVBOOT \ + "setenv bootargs config-addr=0x60000000; " \ + "bootm 0x01000000 - 0x00f00000" + +#define CONFIG_ALU \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "cpu 1 release 0x01000000 - - -;" \ + "cpu 2 release 0x01000000 - - -;" \ + "cpu 3 release 0x01000000 - - -;" \ + "cpu 4 release 0x01000000 - - -;" \ + "cpu 5 release 0x01000000 - - -;" \ + "cpu 6 release 0x01000000 - - -;" \ + "cpu 7 release 0x01000000 - - -;" \ + "go 0x01000000" + +#define CONFIG_LINUX \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "setenv ramdiskaddr 0x02000000;" \ + "setenv fdtaddr 0x00c00000;" \ + "setenv loadaddr 0x1000000;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_LINUX + +#ifdef CONFIG_SECURE_BOOT +#include +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From b38181fa833b123144752eca554888d8da7e27cf Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Fri, 4 Jan 2013 04:06:17 +0000 Subject: powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDB In order to be able to build a u-boot.pbl image, both the CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be defined. This patch sets these two files for the P2041RDB board. Signed-off-by: Valentin Longchamp Signed-off-by: Andy Fleming --- include/configs/P2041RDB.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8b9b0dbc221..bbc53ceafd2 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -34,6 +34,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -- cgit v1.3.1 From 41d910118cfd30c802e037bab70754fbe5f04c7e Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Mon, 14 Jan 2013 18:26:57 +0000 Subject: powerpc/85xx: Add BSC9132QDS support BSC9132QDS is a Freescale reference design board for BSC9132 SoC. BSC9132 SOC is an integrated device that targets the evolving Microcell, Picocell, and Enterprise-Femto base station market subsegments. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. BSC9132QDS Overview -------------------- 2Gbyte DDR3 (on board DDR), Dual Ranki 32Mbyte 16bit NOR flash 128Mbyte 2K page size NAND Flash 256 Kbit M24256 I2C EEPROM 128 Mbit SPI Flash memory SD slot USB-ULPI eTSEC1: Connected to SGMII PHY eTSEC2: Connected to SGMII PHY PCIe CPRI SerDes I2C RTC DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Naveen Burmi Signed-off-by: Poonam Aggrwal Signed-off-by: Prabhakar Kushwaha Signed-off-by: Andy Fleming --- MAINTAINERS | 4 + board/freescale/bsc9132qds/Makefile | 52 +++ board/freescale/bsc9132qds/README | 150 +++++++ board/freescale/bsc9132qds/bsc9132qds.c | 403 +++++++++++++++++++ board/freescale/bsc9132qds/ddr.c | 209 ++++++++++ board/freescale/bsc9132qds/law.c | 35 ++ board/freescale/bsc9132qds/tlb.c | 92 +++++ boards.cfg | 6 + include/configs/BSC9132QDS.h | 667 ++++++++++++++++++++++++++++++++ 9 files changed, 1618 insertions(+) create mode 100644 board/freescale/bsc9132qds/Makefile create mode 100644 board/freescale/bsc9132qds/README create mode 100644 board/freescale/bsc9132qds/bsc9132qds.c create mode 100644 board/freescale/bsc9132qds/ddr.c create mode 100644 board/freescale/bsc9132qds/law.c create mode 100644 board/freescale/bsc9132qds/tlb.c create mode 100644 include/configs/BSC9132QDS.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 28c052d7a0e..d3ed3905eac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27,6 +27,10 @@ Poonam Aggrwal BSC9131RDB BSC9131 +Naveen Burmi + + BSC9132QDS BSC9132 + Greg Allen UTX8245 MPC8245 diff --git a/board/freescale/bsc9132qds/Makefile b/board/freescale/bsc9132qds/Makefile new file mode 100644 index 00000000000..267400becb1 --- /dev/null +++ b/board/freescale/bsc9132qds/Makefile @@ -0,0 +1,52 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9132qds/README b/board/freescale/bsc9132qds/README new file mode 100644 index 00000000000..4a3dbfe5d4e --- /dev/null +++ b/board/freescale/bsc9132qds/README @@ -0,0 +1,150 @@ +Overview +-------- + The BSC9132 is a highly integrated device that targets the evolving + Microcell, Picocell, and Enterprise-Femto base station market subsegments. + + The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850 + core technologies with MAPLE-B2P baseband acceleration processing elements + to address the need for a high performance, low cost, integrated solution + that handles all required processing layers without the need for an + external device except for an RF transceiver or, in a Micro base station + configuration, a host device that handles the L3/L4 and handover between + sectors. + + The BSC9132 SoC includes the following function and features: + - Power Architecture subsystem including two e500 processors with + 512-Kbyte shared L2 cache + - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2 + cache + - 32 Kbyte of shared M3 memory + - The Multi Accelerator Platform Engine for Pico BaseStation Baseband + Processing (MAPLE-B2P) + - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including + ECC), up to 1333 MHz data rate + - Dedicated security engine featuring trusted boot + - Two DMA controllers + - OCNDMA with four bidirectional channels + - SysDMA with sixteen bidirectional channels + - Interfaces + - Four-lane SerDes PHY + - PCI Express controller complies with the PEX Specification-Rev 2.0 + - Two Common Public Radio Interface (CPRI) controller lanes + - High-speed USB 2.0 host and device controller with ULPI interface + - Enhanced secure digital (SD/MMC) host controller (eSDHC) + - Antenna interface controller (AIC), supporting four industry + standard JESD207/four custom ADI RF interfaces + - ADI lanes support both full duplex FDD support & half duplex TDD + - Universal Subscriber Identity Module (USIM) interface that + facilitates communication to SIM cards or Eurochip pre-paid phone + cards + - Two DUART, two eSPI, and two I2C controllers + - Integrated Flash memory controller (IFC) + - GPIO + - Sixteen 32-bit timers + +The SC3850 core subsystem consists of the following: + - 32 KB, 8-way, level 1 instruction cache (L1 ICache) + - 32 KB, 8-way, level 1 data cache (L1 DCache) + - 512 KB, 8-way, level 2 unified instruction/data cache (L2 cache/M2 memory) + - Memory management unit (MMU) + - Global interrupt controller ( GIC) + - Debug and profiling unit (DPU) + - Two 32-bit quad timers + +BSC9132QDS board Overview +------------------------- + 2Gbyte DDR3 (on board DDR), Dual Ranki + 32Mbyte 16bit NOR flash + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + SD slot + USB-ULPI + eTSEC1: Connected to SGMII PHY + eTSEC2: Connected to SGMII PHY + PCIe + CPRI + SerDes + I2C RTC + DUART interface: supports one UARTs up to 115200 bps for console display + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. CPU0/CPU1/CCB/DDR: 1000MHz/1000MHz/500MHz/800MHz + (SYSCLK = 100MHz, DDRCLK = 100MHz) +2. CPU0/CPU1/CCB/DDR: 1200MHz/1200MHz/600MHz/1330MHz + (SYSCLK = 100MHz, DDRCLK = 133MHz) + +Boot Methods Supported +----------------------- +1. NOR Flash +2. NAND Flash +3. SD Card +4. SPI flash + +Default Boot Method +-------------------- +NOR boot + +Building U-boot +-------------- +To build the u-boot for BSC9132QDS: +1. NOR Flash + make BSC9132QDS_NOR_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_NOR_DDRCLK133 : For 133MHZ DDR CLK +2. NAND Flash : It is currently not supported +3. SPI Flash + make BSC9132QDS_SPIFLASH_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_SPIFLASH_DDRCLK133 : For 133MHZ DDR CLK +4. SD Card + make BSC9132QDS_SDCARD_DDRCLK100 : For 100MHZ DDR CLK + make BSC9132QDS_SDCARD_DDRCLK133 : For 133MHZ DDR CLK + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 2G cacheable + 0x8000_0000 0x8FFF_FFFF NOR Flash 256M + 0x9000_0000 0x9FFF_FFFF PCIe Memory 256M + 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M + 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M + 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M + 0xC000_0000 0xC000_7FFF M3 Memory 32K + 0xC001_0000 0xC001_FFFF PCI Express I/O 64K + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F7_FFFF PA SRAM Region 0 512K + 0xC1F8_0000 0xC1FB_FFFF PA SRAM Region 1 512K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9132qds.dts > bsc9132qds.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9132qds.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9132qds.dtb + bootm 1000000 2000000 c00000 diff --git a/board/freescale/bsc9132qds/bsc9132qds.c b/board/freescale/bsc9132qds/bsc9132qds.c new file mode 100644 index 00000000000..bcac5c1ddb4 --- /dev/null +++ b/board/freescale/bsc9132qds/bsc9132qds.c @@ -0,0 +1,403 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_PCI +#include +#include +#endif + +#include "../common/qixis.h" +DECLARE_GLOBAL_DATA_PTR; + + +int board_early_init_f(void) +{ + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + return 0; +} + +void board_config_serdes_mux(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + + switch (srds_cfg) { + /* PEX(1) PEX(2) CPRI 2 CPRI 1 */ + case 1: + case 2: + case 3: + case 4: + case 5: + case 22: + case 23: + case 24: + case 25: + case 26: + QIXIS_WRITE_I2C(brdcfg[4], 0x03); + break; + + /* PEX(1) PEX(2) SGMII1 CPRI 1 */ + case 6: + case 7: + case 8: + case 9: + case 10: + case 27: + case 28: + case 29: + case 30: + case 31: + QIXIS_WRITE_I2C(brdcfg[4], 0x01); + break; + + /* PEX(1) PEX(2) SGMII1 SGMII2 */ + case 11: + case 32: + QIXIS_WRITE_I2C(brdcfg[4], 0x00); + break; + + /* PEX(1) SGMII2 CPRI 2 CPRI 1 */ + case 12: + case 13: + case 14: + case 15: + case 16: + case 33: + case 34: + case 35: + case 36: + case 37: + QIXIS_WRITE_I2C(brdcfg[4], 0x07); + break; + + /* PEX(1) SGMII2 SGMII1 CPRI 1 */ + case 17: + case 18: + case 19: + case 20: + case 21: + case 38: + case 39: + case 40: + case 41: + case 42: + QIXIS_WRITE_I2C(brdcfg[4], 0x05); + break; + + /* SGMII1 SGMII2 CPRI 2 CPRI 1 */ + case 43: + case 44: + case 45: + case 46: + case 47: + QIXIS_WRITE_I2C(brdcfg[4], 0x0F); + break; + + + default: + break; + } +} + +int board_early_init_r(void) +{ +#ifndef CONFIG_SYS_NO_FLASH + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_64M, 1); + + set_tlb(1, flashbase + 0x4000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel+1, BOOKE_PAGESZ_64M, 1); +#endif + board_config_serdes_mux(); + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +int checkboard(void) +{ + struct cpu_type *cpu; + u8 sw; + + cpu = gd->cpu; + printf("Board: %sQDS\n", cpu->name); + + printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x,\n", + QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver)); + + sw = QIXIS_READ(brdcfg[0]); + sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT; + + printf("IFC chip select:"); + switch (sw) { + case 0: + printf("NOR\n"); + break; + case 2: + printf("Promjet\n"); + break; + case 4: + printf("NAND\n"); + break; + default: + printf("Invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH); + break; + } + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[4]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; + +#endif + +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + tsec_eth_init(bis, tsec_info, num); + + #ifdef CONFIG_PCI + pci_eth_init(bis); + #endif + + return 0; +} +#endif + +#define USBMUX_SEL_MASK 0xc0 +#define USBMUX_SEL_UART2 0xc0 +#define USBMUX_SEL_USB 0x40 +#define SPIMUX_SEL_UART3 0x80 +#define GPS_MUX_SEL_GPS 0x40 + +#define TSEC_1588_CLKIN_MASK 0x03 +#define CON_XCVR_REF_CLK 0x00 + +int misc_init_r(void) +{ + u8 val; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 porbmsr = in_be32(&gur->porbmsr); + u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf; + + /*Configure 1588 clock-in source from RF Card*/ + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(TSEC_1588_CLKIN_MASK)) | CON_XCVR_REF_CLK); + + if (hwconfig("uart2") && hwconfig("usb1")) { + printf("UART2 and USB cannot work together on the board\n"); + printf("Remove one from hwconfig and reset\n"); + } else { + if (hwconfig("uart2")) { + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_UART2); + clrbits_be32(&gur->pmuxcr3, + MPC85xx_PMUXCR3_USB_SEL_MASK); + setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART2_SEL); + } else { + /* By default USB should be selected. + * Programming FPGA to select USB. */ + val = QIXIS_READ_I2C(brdcfg[5]); + QIXIS_WRITE_I2C(brdcfg[5], + (val & ~(USBMUX_SEL_MASK)) | USBMUX_SEL_USB); + } + + } + + if (hwconfig("sim")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SPI) { + + val = QIXIS_READ_I2C(brdcfg[3]); + QIXIS_WRITE_I2C(brdcfg[3], val|0x10); + clrbits_be32(&gur->pmuxcr, + MPC85xx_PMUXCR0_SIM_SEL_MASK); + setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR0_SIM_SEL); + } + } + + if (hwconfig("uart3")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SDHC) { + + /* UART3 and SPI1 (Flashes) are muxed together */ + val = QIXIS_READ_I2C(brdcfg[3]); + QIXIS_WRITE_I2C(brdcfg[3], (val | SPIMUX_SEL_UART3)); + clrbits_be32(&gur->pmuxcr3, + MPC85xx_PMUXCR3_UART3_SEL_MASK); + setbits_be32(&gur->pmuxcr3, MPC85xx_PMUXCR3_UART3_SEL); + + /* MUX to select UART3 connection to J24 header + * or to GPS */ + val = QIXIS_READ_I2C(brdcfg[6]); + if (hwconfig("gps")) + QIXIS_WRITE_I2C(brdcfg[6], + (val | GPS_MUX_SEL_GPS)); + else + QIXIS_WRITE_I2C(brdcfg[6], + (val & ~(GPS_MUX_SEL_GPS))); + } + } + return 0; +} + +void fdt_del_node_compat(void *blob, const char *compatible) +{ + int err; + int off = fdt_node_offset_by_compatible(blob, -1, compatible); + if (off < 0) { + printf("WARNING: could not find compatible node %s: %s.\n", + compatible, fdt_strerror(off)); + return; + } + err = fdt_del_node(blob, off); + if (err < 0) { + printf("WARNING: could not remove %s: %s.\n", + compatible, fdt_strerror(err)); + } +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + #if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; + #endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 porbmsr = in_be32(&gur->porbmsr); + u32 romloc = (porbmsr >> MPC85XX_PORBMSR_ROMLOC_SHIFT) & 0xf; + + if (!(hwconfig("uart2") && hwconfig("usb1"))) { + /* If uart2 is there in hwconfig remove usb node from + * device tree */ + + if (hwconfig("uart2")) { + /* remove dts usb node */ + fdt_del_node_compat(blob, "fsl-usb2-dr"); + } else { + fdt_fixup_dr_usb(blob, bd); + fdt_del_node_and_alias(blob, "serial2"); + } + } + + if (hwconfig("uart3")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SDHC) + /* Delete SPI node from the device tree */ + fdt_del_node_and_alias(blob, "spi1"); + } else + fdt_del_node_and_alias(blob, "serial3"); + + if (hwconfig("sim")) { + if (romloc == PORBMSR_ROMLOC_NAND_2K || + romloc == PORBMSR_ROMLOC_NOR || + romloc == PORBMSR_ROMLOC_SPI) { + + /* remove dts sdhc node */ + fdt_del_node_compat(blob, "fsl,esdhc"); + } else if (romloc == PORBMSR_ROMLOC_SDHC) { + + /* remove dts sim node */ + fdt_del_node_compat(blob, "fsl,sim-v1.0"); + printf("SIM & SDHC can't work together on the board"); + printf("\nRemove sim from hwconfig and reset\n"); + } + } +} +#endif diff --git a/board/freescale/bsc9132qds/ddr.c b/board/freescale/bsc9132qds/ddr.c new file mode 100644 index 00000000000..946ad190b07 --- /dev/null +++ b/board/freescale/bsc9132qds/ddr.c @@ -0,0 +1,209 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fsl_ddr_cfg_regs_t ddr_cfg_regs_1333 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_1333, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_1333, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_1333, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_1333, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_1333, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_1333, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_1333, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_1333, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {1060, 1333, &ddr_cfg_regs_1333}, + {0, 0, NULL} +}; + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J512M8_187E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9132qds/law.c b/board/freescale/bsc9132qds/law.c new file mode 100644 index 00000000000..dc2365851b4 --- /dev/null +++ b/board/freescale/bsc9132qds/law.c @@ -0,0 +1,35 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +struct law_entry law_table[] = { +#ifndef CONFIG_SYS_NO_FLASH + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), +#endif + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9132qds/tlb.c b/board/freescale/bsc9132qds/tlb.c new file mode 100644 index 00000000000..0e4545fb128 --- /dev/null +++ b/board/freescale/bsc9132qds/tlb.c @@ -0,0 +1,92 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 3, BOOKE_PAGESZ_64M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, + CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 4, BOOKE_PAGESZ_64M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_64K, 1), +#endif + + /* *I*G - Board FPGA */ + SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 9, BOOKE_PAGESZ_256K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_1M, 1), +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 0a2ed40973f..98f7a14d1e6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -856,6 +856,12 @@ P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 P5040DS powerpc mpc85xx corenet_ds freescale BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH +BSC9132QDS_NOR_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_100 +BSC9132QDS_NOR_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SYS_CLK_100_DDR_133 +BSC9132QDS_SDCARD_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_100 +BSC9132QDS_SDCARD_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SDCARD,SYS_CLK_100_DDR_133 +BSC9132QDS_SPIFLASH_DDRCLK100 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_100 +BSC9132QDS_SPIFLASH_DDRCLK133 powerpc mpc85xx bsc9132qds freescale - BSC9132QDS:BSC9132QDS,SPIFLASH,SYS_CLK_100_DDR_133 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h new file mode 100644 index 00000000000..431c6869678 --- /dev/null +++ b/include/configs/BSC9132QDS.h @@ -0,0 +1,667 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BSC9132 QDS board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_BSC9132QDS +#define CONFIG_BSC9132 +#endif + +#define CONFIG_MISC_INIT_R + +#ifdef CONFIG_SDCARD +#define CONFIG_RAMBOOT_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif +#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769 1 +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0x8ff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#if defined(CONFIG_PCI) +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI + +#define CONFIG_E1000 /* E1000 pci Ethernet card*/ + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "PCIe Slot" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_TSEC_ENET /* ethernet */ + +#if defined(CONFIG_SYS_CLK_100_DDR_100) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 +#elif defined(CONFIG_SYS_CLK_100_DDR_133) +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133000000 +#endif + +#define CONFIG_MP + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* enable branch predition */ + +#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01ffffff + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ +#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ +#define CONFIG_FSL_DDR_INTERACTIVE + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#define CONFIG_SYS_SDRAM_SIZE (1024) +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 + +/* DDR3 Controller Settings */ +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F +#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 +#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 +#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 +#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 +#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 +#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 + +#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 +#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 +#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 + +#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 +#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 +#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 +#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 +#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 +#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 +#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 +#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 + +/*FIXME: the following params are constant w.r.t diff freq +combinations. this should be removed later +*/ +#if CONFIG_DDR_CLK_FREQ == 100000000 +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 +#elif CONFIG_DDR_CLK_FREQ == 133000000 +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 +#else +#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 +#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 +#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 +#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 +#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 +#endif + + +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ +#define CONFIG_SYS_FLASH_BASE 0x88000000 +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE + +#define CONFIG_SYS_NOR_CSPR 0x88000101 +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) +/* NOR Flash Timing Params */ + +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ + | FTIM0_NOR_TEADC(0x03) \ + | FTIM0_NOR_TAVDS(0x00) \ + | FTIM0_NOR_TEAHC(0x0f)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ + | FTIM1_NOR_TRAD_NOR(0x09) \ + | FTIM1_NOR_TSEQRAD_NOR(0x09)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ + | FTIM2_NOR_TCH(0x4) \ + | FTIM2_NOR_TWPH(0x7) \ + | FTIM2_NOR_TWP(0x1e)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ + +#undef CONFIG_SYS_FLASH_CHECKSUM +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +/* CFI for NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ + | FTIM0_NAND_TWP(0x05) \ + | FTIM0_NAND_TWCHT(0x02) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ + | FTIM1_NAND_TWBE(0x1e) \ + | FTIM1_NAND_TRR(0x07) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x11)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* NAND */ +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND + +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_FSL_QIXIS +#ifdef CONFIG_FSL_QIXIS +#define CONFIG_SYS_FPGA_BASE 0xffb00000 +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 +#define QIXIS_BASE CONFIG_SYS_FPGA_BASE +#define QIXIS_LBMAP_SWITCH 9 +#define QIXIS_LBMAP_MASK 0x07 +#define QIXIS_LBMAP_SHIFT 0 +#define QIXIS_LBMAP_DFLTBANK 0x00 +#define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_RST_CTL_RESET 0x83 +#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 +#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 +#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 + +#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE + +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS3 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 +#endif + +/* Set up IFC registers for boot location NOR/NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER /* hush parser */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400800 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +#define CONFIG_ID_EEPROM +#ifdef CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#endif +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +/* I2C FPGA */ +#define CONFIG_I2C_FPGA +#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 + +#define CONFIG_RTC_DS3231 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* + * SPI interface will not be available in case of NAND boot SPI CS0 will be + * used for SLIC + */ +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI /* SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 1 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + +#endif /* CONFIG_TSEC_ENET */ + +#define CONFIG_MMC +#ifdef CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_DOS_PARTITION +#define CONFIG_FSL_ESDHC +#define CONFIG_GENERIC_MMC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#endif + +#define CONFIG_USB_EHCI /* USB */ +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq:1ms ticks */ + + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_HOSTNAME BSC9132qds +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" + +#define CONFIG_BAUDRATE 115200 + +#ifdef CONFIG_SDCARD +#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" +#else +#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=bsc9132qds.dtb\0" \ + "bdev=sda1\0" \ + CONFIG_DEF_HWCONFIG\ + "othbootargs=mem=880M ramdisk_size=600000 " \ + "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ + "isolcpus=0\0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + "debug_halt_off=mw ff7e0e30 0xf0000000;" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "usb start;" \ + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From d4ed6542788169b789c7eed142efc0a6fa5ca698 Mon Sep 17 00:00:00 2001 From: Andy Fleming Date: Thu, 24 Jan 2013 01:55:11 -0600 Subject: corenet: Disable video on P2020DS The P2020DS build had grown too large, and video support isn't enabled in almost any other Freescale board. Disabling it allows us to keep building, and provides options for reenabling it later. Signed-off-by: Andy Fleming --- include/configs/P2020DS.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 0cc57816927..a975ee10edb 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -490,7 +490,7 @@ #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT /* video */ -#define CONFIG_VIDEO +#undef CONFIG_VIDEO #if defined(CONFIG_VIDEO) #define CONFIG_BIOSEMU -- cgit v1.3.1 From 14d315b8b3e974a7f617a9b4454fc579161fb75b Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 23 Jan 2013 14:18:25 +0100 Subject: microblaze: Remove FSL support from generic board This code was targetting one specific Microblaze platform configuration which is obsolete and fsl bus isn't used in this way. Signed-off-by: Michal Simek --- board/xilinx/microblaze-generic/microblaze-generic.c | 20 -------------------- include/configs/microblaze-generic.h | 4 ---- 2 files changed, 24 deletions(-) (limited to 'include') diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index b75e62c715d..70f94c1a597 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -53,29 +53,9 @@ int gpio_init (void) return 0; } -#ifdef CONFIG_SYS_FSL_2 -void fsl_isr2 (void *arg) { - volatile int num; - *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) = - ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4))); - GET (num, 2); - NGET (num, 2); - puts("*"); -} - -int fsl_init2 (void) { - puts("fsl_init2\n"); - install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL); - return 0; -} -#endif - void board_init(void) { gpio_init(); -#ifdef CONFIG_SYS_FSL_2 - fsl_init2(); -#endif } int board_eth_init(bd_t *bis) diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index eed38c165f0..d172e56bcfc 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -120,10 +120,6 @@ # define CONFIG_SYS_TIMER_0_IRQ XILINX_TIMER_IRQ #endif -/* FSL */ -/* #define CONFIG_SYS_FSL_2 */ -/* #define FSL_INTR_2 1 */ - /* * memory layout - Example * CONFIG_SYS_TEXT_BASE = 0x1200_0000; defined in config.mk -- cgit v1.3.1 From 50b1fa399608652a47c1d2ae6d49754b86165ba8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 13 Dec 2012 20:49:12 +0000 Subject: Add generic global_data Add a generic global_data structure which all archs will eventually use. Signed-off-by: Simon Glass --- include/asm-generic/global_data.h | 102 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 102 insertions(+) create mode 100644 include/asm-generic/global_data.h (limited to 'include') diff --git a/include/asm-generic/global_data.h b/include/asm-generic/global_data.h new file mode 100644 index 00000000000..b8ac024045d --- /dev/null +++ b/include/asm-generic/global_data.h @@ -0,0 +1,102 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. + * (C) Copyright 2002-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_GENERIC_GBL_DATA_H +#define __ASM_GENERIC_GBL_DATA_H +/* + * The following data structure is placed in some memory which is + * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or + * some locked parts of the data cache) to allow for a minimum set of + * global variables during system initialization (until we have set + * up the memory controller so that we can use RAM). + * + * Keep it *SMALL* and remember to set GENERATED_GBL_DATA_SIZE > sizeof(gd_t) + * + * Each architecture has its own private fields. For now all are private + */ + +#ifndef __ASSEMBLY__ +typedef struct global_data { + bd_t *bd; + unsigned long flags; + unsigned long baudrate; + unsigned long cpu_clk; /* CPU clock in Hz! */ + unsigned long bus_clk; + /* We cannot bracket this with CONFIG_PCI due to mpc5xxx */ + unsigned long pci_clk; + unsigned long mem_clk; +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) + unsigned long fb_base; /* Base address of framebuffer mem */ +#endif +#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) + unsigned long post_log_word; /* Record POST activities */ + unsigned long post_log_res; /* success of POST test */ + unsigned long post_init_f_time; /* When post_init_f started */ +#endif +#ifdef CONFIG_BOARD_TYPES + unsigned long board_type; +#endif + unsigned long have_console; /* serial_init() was called */ +#ifdef CONFIG_PRE_CONSOLE_BUFFER + unsigned long precon_buf_idx; /* Pre-Console buffer index */ +#endif +#ifdef CONFIG_MODEM_SUPPORT + unsigned long do_mdm_init; + unsigned long be_quiet; +#endif + unsigned long env_addr; /* Address of Environment struct */ + unsigned long env_valid; /* Checksum of Environment valid? */ + + /* TODO: is this the same as relocaddr, or something else? */ + unsigned long dest_addr; /* Post-relocation address of U-Boot */ + unsigned long dest_addr_sp; + unsigned long ram_top; /* Top address of RAM used by U-Boot */ + + unsigned long relocaddr; /* Start address of U-Boot in RAM */ + phys_size_t ram_size; /* RAM size */ + unsigned long mon_len; /* monitor len */ + unsigned long irq_sp; /* irq stack pointer */ + unsigned long start_addr_sp; /* start_addr_stackpointer */ + unsigned long reloc_off; + struct global_data *new_gd; /* relocated global data */ + const void *fdt_blob; /* Our device tree, NULL if none */ + void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ + struct arch_global_data arch; /* architecture-specific data */ +} gd_t; +#endif + +/* + * Global Data Flags + */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Env. imported into hash table */ + +#endif /* __ASM_GENERIC_GBL_DATA_H */ -- cgit v1.3.1 From c7db645a6b0e6ed8ffa9c53a5c41430b95c20bcc Mon Sep 17 00:00:00 2001 From: Ashok Date: Wed, 7 Nov 2012 07:39:29 +0000 Subject: configs:Remove unused macro CONFIG_DISCOVER_PHY Remove unused macro CONFIG_DISCOVER_PHY from configs. Signed-off-by: Ashok Kumar Reddy Acked-by: Stefano Babic --- include/configs/apx4devkit.h | 1 - include/configs/sc_sps_1.h | 1 - 2 files changed, 2 deletions(-) (limited to 'include') diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 6764b4749c9..73c66af06d5 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -175,7 +175,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define IMX_FEC_BASE MXS_ENET0_BASE #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_XCV_TYPE RMII #endif diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index cb99d58644d..f807a61c73d 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -160,7 +160,6 @@ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_MULTI #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC -- cgit v1.3.1 From fb7e16cc1c1f5d5bb212118b89218b2e706226b2 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Thu, 13 Dec 2012 00:47:36 +0000 Subject: FAT: use toupper/tolower instead of recoding them toupper/tolower function are already declared, so use them. Signed-off-by: Richard Genoud Acked-by: Marek Vasut Acked-by: Stefano Babic --- fs/fat/fat.c | 3 ++- fs/fat/fat_write.c | 3 ++- include/fat.h | 3 --- 3 files changed, 4 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 25d3318cd0a..7bb5dba4e29 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -33,6 +33,7 @@ #include #include #include +#include /* * Convert a string to lowercase. @@ -40,7 +41,7 @@ static void downcase(char *str) { while (*str != '\0') { - TOLOWER(*str); + *str = tolower(*str); str++; } } diff --git a/fs/fat/fat_write.c b/fs/fat/fat_write.c index 4a1bda0a37e..819c33b1abd 100644 --- a/fs/fat/fat_write.c +++ b/fs/fat/fat_write.c @@ -28,6 +28,7 @@ #include #include #include +#include #include "fat.c" static void uppercase(char *str, int len) @@ -35,7 +36,7 @@ static void uppercase(char *str, int len) int i; for (i = 0; i < len; i++) { - TOUPPER(*str); + *str = toupper(*str); str++; } } diff --git a/include/fat.h b/include/fat.h index 706cd7a4bd3..b28c3fd6685 100644 --- a/include/fat.h +++ b/include/fat.h @@ -98,9 +98,6 @@ #endif #endif -#define TOLOWER(c) if((c) >= 'A' && (c) <= 'Z'){(c)+=('a' - 'A');} -#define TOUPPER(c) if ((c) >= 'a' && (c) <= 'z') \ - (c) -= ('a' - 'A'); #define START(dent) (FAT2CPU16((dent)->start) \ + (mydata->fatsize != 32 ? 0 : \ (FAT2CPU16((dent)->starthi) << 16))) -- cgit v1.3.1 From 34765e88532dfe0f8210baba9f9482de470d2202 Mon Sep 17 00:00:00 2001 From: Richard Genoud Date: Mon, 3 Dec 2012 06:28:28 +0000 Subject: cmd_time: merge run_command_and_time_it with cmd_process As far as every arch has a get_timer function, run_command_and_time_it code can now disappear. Signed-off-by: Richard Genoud Acked-By: Che-Liang Chiou [trini: s/ulong/unsigned long/ in command.h portion] Signed-off-by: Tom Rini --- common/cmd_time.c | 33 ++------------------------------- common/command.c | 6 +++++- common/hush.c | 2 +- common/main.c | 2 +- include/command.h | 4 +++- 5 files changed, 12 insertions(+), 35 deletions(-) (limited to 'include') diff --git a/common/cmd_time.c b/common/cmd_time.c index 6dbdbbfbe7a..9808cd66995 100644 --- a/common/cmd_time.c +++ b/common/cmd_time.c @@ -22,36 +22,6 @@ #include #include -/* - * TODO(clchiou): This function actually minics the bottom-half of the - * run_command() function. Since this function has ARM-dependent timer - * codes, we cannot merge it with the run_command() for now. - */ -static int run_command_and_time_it(int flag, int argc, char * const argv[], - ulong *cycles) -{ - cmd_tbl_t *cmdtp = find_cmd(argv[0]); - int retval = 0; - - if (!cmdtp) { - printf("%s: command not found\n", argv[0]); - return 1; - } - if (argc > cmdtp->maxargs) - return CMD_RET_USAGE; - - /* - * TODO(clchiou): get_timer_masked() is only defined in certain ARM - * boards. We could use the new timer API that Graeme is proposing - * so that this piece of code would be arch-independent. - */ - *cycles = get_timer_masked(); - retval = cmdtp->cmd(cmdtp, flag, argc, argv); - *cycles = get_timer_masked() - *cycles; - - return retval; -} - static void report_time(ulong cycles) { ulong minutes, seconds, milliseconds; @@ -75,11 +45,12 @@ static int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { ulong cycles = 0; int retval = 0; + int repeatable; if (argc == 1) return CMD_RET_USAGE; - retval = run_command_and_time_it(0, argc - 1, argv + 1, &cycles); + retval = cmd_process(0, argc - 1, argv + 1, &repeatable, &cycles); report_time(cycles); return retval; diff --git a/common/command.c b/common/command.c index 50c84292c16..305a236facc 100644 --- a/common/command.c +++ b/common/command.c @@ -513,7 +513,7 @@ static int cmd_call(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } enum command_ret_t cmd_process(int flag, int argc, char * const argv[], - int *repeatable) + int *repeatable, ulong *ticks) { enum command_ret_t rc = CMD_RET_SUCCESS; cmd_tbl_t *cmdtp; @@ -543,7 +543,11 @@ enum command_ret_t cmd_process(int flag, int argc, char * const argv[], /* If OK so far, then do the command */ if (!rc) { + if (ticks) + *ticks = get_timer(0); rc = cmd_call(cmdtp, flag, argc, argv); + if (ticks) + *ticks = get_timer(*ticks); *repeatable &= cmdtp->repeatable; } if (rc == CMD_RET_USAGE) diff --git a/common/hush.c b/common/hush.c index eb6c879c534..cc81c9c3e05 100644 --- a/common/hush.c +++ b/common/hush.c @@ -1665,7 +1665,7 @@ static int run_pipe_real(struct pipe *pi) } /* Process the command */ return cmd_process(flag, child->argc, child->argv, - &flag_repeat); + &flag_repeat, NULL); #endif } #ifndef __U_BOOT__ diff --git a/common/main.c b/common/main.c index 9e9268710de..e2d2e09bf9f 100644 --- a/common/main.c +++ b/common/main.c @@ -1452,7 +1452,7 @@ static int builtin_run_command(const char *cmd, int flag) continue; } - if (cmd_process(flag, argc, argv, &repeatable)) + if (cmd_process(flag, argc, argv, &repeatable, NULL)) rc = -1; /* Did the user stop this? */ diff --git a/include/command.h b/include/command.h index 476e7cffc28..3785eb987f4 100644 --- a/include/command.h +++ b/include/command.h @@ -139,10 +139,12 @@ enum command_ret_t { * @param repeatable This function sets this to 0 if the command is not * repeatable. If the command is repeatable, the value * is left unchanged. + * @param ticks If ticks is not null, this function set it to the + * number of ticks the command took to complete. * @return 0 if the command succeeded, 1 if it failed */ int cmd_process(int flag, int argc, char * const argv[], - int *repeatable); + int *repeatable, unsigned long *ticks); #endif /* __ASSEMBLY__ */ -- cgit v1.3.1 From e70fb539a634ab86153353aec8a9c1fede818eb0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 22 Jan 2013 23:40:06 +0000 Subject: serial: arm_dcc: Remove CONFIG_ARM_DCC_MULTI option CONFIG_ARM_DCC_MULTI should be also removed in the patch "serial: Remove CONFIG_SERIAL_MULTI from serial drivers" (sha1: a3827250606895ec2dd4b8d867342b7cabf3692f) Because the driver defines serial_* functions which cause conflict with serial.c (multiple definition of serial_*) Removing CONFIG_SERIAL_MULTI function also require to define default_serial_console for cases where another serial driver is not available in the system. Signed-off-by: Michal Simek Acked-by: Marek Vasut --- common/stdio.c | 2 +- drivers/serial/arm_dcc.c | 16 +++++----------- include/stdio_dev.h | 2 +- 3 files changed, 7 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/common/stdio.c b/common/stdio.c index 97ff9cf4a6a..5d5117c0ed8 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -207,7 +207,7 @@ int stdio_init (void) /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); -#ifdef CONFIG_ARM_DCC_MULTI +#ifdef CONFIG_ARM_DCC drv_arm_dcc_init (); #endif #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c index 7b5ecb5132d..812dcf0787c 100644 --- a/drivers/serial/arm_dcc.c +++ b/drivers/serial/arm_dcc.c @@ -89,15 +89,6 @@ #define TIMEOUT_COUNT 0x4000000 -#ifndef CONFIG_ARM_DCC_MULTI -#define arm_dcc_init serial_init -void serial_setbrg(void) {} -#define arm_dcc_getc serial_getc -#define arm_dcc_putc serial_putc -#define arm_dcc_puts serial_puts -#define arm_dcc_tstc serial_tstc -#endif - int arm_dcc_init(void) { return 0; @@ -147,7 +138,6 @@ int arm_dcc_tstc(void) return reg; } -#ifdef CONFIG_ARM_DCC_MULTI static struct stdio_dev arm_dcc_dev; int drv_arm_dcc_init(void) @@ -167,4 +157,8 @@ int drv_arm_dcc_init(void) return stdio_register(&arm_dcc_dev); } -#endif + +__weak struct serial_device *default_serial_console(void) +{ + return NULL; +} diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 932d093345e..9451740e8be 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -99,7 +99,7 @@ struct list_head* stdio_get_list(void); struct stdio_dev* stdio_get_by_name(const char* name); struct stdio_dev* stdio_clone(struct stdio_dev *dev); -#ifdef CONFIG_ARM_DCC_MULTI +#ifdef CONFIG_ARM_DCC int drv_arm_dcc_init(void); #endif #ifdef CONFIG_LCD -- cgit v1.3.1