From 9acb626fc145e7327f94fd77f927dce08dd978a8 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Thu, 20 Apr 2006 08:42:42 +0200 Subject: Add MCF5282 support (without preloader) relocate ichache_State to ram u-boot can run from internal flash Add EB+MCF-EV123 board support. Add m68k Boards to MAKEALL Patch from Jens Scharsig, 08 Aug 2005 --- include/asm-m68k/immap_5282.h | 82 ++++--- include/asm-m68k/m5282.h | 529 +++++++++++++++++++++++++++++++++++++++-- include/configs/EB+MCF-EV123.h | 223 +++++++++++++++++ 3 files changed, 783 insertions(+), 51 deletions(-) create mode 100644 include/configs/EB+MCF-EV123.h (limited to 'include') diff --git a/include/asm-m68k/immap_5282.h b/include/asm-m68k/immap_5282.h index f2b77db8711..a95912f9bad 100644 --- a/include/asm-m68k/immap_5282.h +++ b/include/asm-m68k/immap_5282.h @@ -25,39 +25,63 @@ #ifndef __IMMAP_5282__ #define __IMMAP_5282__ +struct sys_ctrl { + uint ipsbar; + char res1[4]; + uint rambar; + char res2[4]; + uchar crsr; + uchar cwcr; + uchar lpicr; + uchar cwsr; + uint dmareqc; + char res3[4]; + uint mpark; + + /* TODO: finish these */ +}; + + /* Fast ethernet controller registers */ typedef struct fec { - uint fec_ecntrl; /* ethernet control register */ - uint fec_ievent; /* interrupt event register */ - uint fec_imask; /* interrupt mask register */ - uint fec_ivec; /* interrupt level and vector status */ - uint fec_r_des_active; /* Rx ring updated flag */ - uint fec_x_des_active; /* Tx ring updated flag */ - uint res3[10]; /* reserved */ - uint fec_mii_data; /* MII data register */ - uint fec_mii_speed; /* MII speed control register */ - uint res4[17]; /* reserved */ - uint fec_r_bound; /* end of RAM (read-only) */ - uint fec_r_fstart; /* Rx FIFO start address */ - uint res5[6]; /* reserved */ - uint fec_x_fstart; /* Tx FIFO start address */ - uint res7[21]; /* reserved */ - uint fec_r_cntrl; /* Rx control register */ - uint fec_r_hash; /* Rx hash register */ - uint res8[14]; /* reserved */ - uint fec_x_cntrl; /* Tx control register */ - uint res9[0x9e]; /* reserved */ - uint fec_addr_low; /* lower 32 bits of station address */ - uint fec_addr_high; /* upper 16 bits of station address */ - uint fec_hash_table_high; /* upper 32-bits of hash table */ - uint fec_hash_table_low; /* lower 32-bits of hash table */ - uint fec_r_des_start; /* beginning of Rx descriptor ring */ - uint fec_x_des_start; /* beginning of Tx descriptor ring */ - uint fec_r_buff_size; /* Rx buffer size */ - uint res2[9]; /* reserved */ - uchar fec_fifo[960]; /* fifo RAM */ + uint res1; /* reserved 1000*/ + uint fec_ievent; /* interrupt event register 1004*/ /* EIR */ + uint fec_imask; /* interrupt mask register 1008*/ /* EIMR */ + uint res2; /* reserved 100c*/ + uint fec_r_des_active; /* Rx ring updated flag 1010*/ /* RDAR */ + uint fec_x_des_active; /* Tx ring updated flag 1014*/ /* XDAR */ + uint res3[3]; /* reserved 1018*/ + uint fec_ecntrl; /* ethernet control register 1024*/ /* ECR */ + uint res4[6]; /* reserved 1028*/ + uint fec_mii_data; /* MII data register 1040*/ /* MDATA */ + uint fec_mii_speed; /* MII speed control register 1044*/ /* MSCR */ + /*1044*/ + uint res5[7]; /* reserved 1048*/ + uint fec_mibc; /* MIB Control/Status register 1064*/ /* MIBC */ + uint res6[7]; /* reserved 1068*/ + uint fec_r_cntrl; /* Rx control register 1084*/ /* RCR */ + uint res7[15]; /* reserved 1088*/ + uint fec_x_cntrl; /* Tx control register 10C4*/ /* TCR */ + uint res8[7]; /* reserved 10C8*/ + uint fec_addr_low; /* lower 32 bits of station address */ /* PALR */ + uint fec_addr_high; /* upper 16 bits of station address */ /* PAUR */ + uint fec_opd; /* opcode + pause duration 10EC*/ /* OPD */ + uint res9[10]; /* reserved 10F0*/ + uint fec_ihash_table_high; /* upper 32-bits of individual hash *//* IAUR */ + uint fec_ihash_table_low; /* lower 32-bits of individual hash *//* IALR */ + uint fec_ghash_table_high; /* upper 32-bits of group hash *//* GAUR */ + uint fec_ghash_table_low; /* lower 32-bits of group hash *//* GALR */ + uint res10[7]; /* reserved 1128*/ + uint fec_tfwr; /* Transmit FIFO watermark 1144*/ /* TFWR */ + uint res11; /* reserved 1148*/ + uint fec_r_bound; /* FIFO Receive Bound Register = end of *//* FRBR */ + uint fec_r_fstart; /* FIFO Receive FIfo Start Registers = *//* FRSR */ + uint res12[11]; /* reserved 1154*/ + uint fec_r_des_start;/* beginning of Rx descriptor ring 1180*//* ERDSR */ + uint fec_x_des_start;/* beginning of Tx descriptor ring 1184*//* ETDSR */ + uint fec_r_buff_size;/* Rx buffer size 1188*/ /* EMRBR */ } fec_t; #endif /* __IMMAP_5282__ */ diff --git a/include/asm-m68k/m5282.h b/include/asm-m68k/m5282.h index 073b0bc790d..e5058a46aac 100644 --- a/include/asm-m68k/m5282.h +++ b/include/asm-m68k/m5282.h @@ -1,9 +1,6 @@ /* * mcf5282.h -- Definitions for Motorola Coldfire 5282 * - * Based on mcf5282sim.h of uCLinux distribution: - * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) - * * See file CREDITS for list of people who contributed to this * project. * @@ -34,27 +31,515 @@ #define INT_RAM_SIZE 65536 +/* General Purpose I/O Module GPIO */ -/* - * Define the 5282 SIM register set addresses. - */ -#define MCFICM_INTC0 0x0c00 /* Base for Interrupt Ctrl 0 */ -#define MCFICM_INTC1 0x0d00 /* Base for Interrupt Ctrl 0 */ -#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */ -#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */ -#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */ -#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */ -#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */ -#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */ -#define MCFINTC_IRLR 0x18 /* */ -#define MCFINTC_IACKL 0x19 /* */ -#define MCFINTC_ICR0 0x40 /* Base ICR register */ - -#define MCFINT_UART0 13 /* Interrupt number for UART0 */ -#define MCFINT_PIT1 55 /* Interrupt number for PIT1 */ - -#define MCF5282_GPIO_PUAPAR 0x10005C +#define MCFGPIO_PORTA (*(vu_char *) (CFG_MBAR+0x100000)) +#define MCFGPIO_PORTB (*(vu_char *) (CFG_MBAR+0x100001)) +#define MCFGPIO_PORTC (*(vu_char *) (CFG_MBAR+0x100002)) +#define MCFGPIO_PORTD (*(vu_char *) (CFG_MBAR+0x100003)) +#define MCFGPIO_PORTE (*(vu_char *) (CFG_MBAR+0x100004)) +#define MCFGPIO_PORTF (*(vu_char *) (CFG_MBAR+0x100005)) +#define MCFGPIO_PORTG (*(vu_char *) (CFG_MBAR+0x100006)) +#define MCFGPIO_PORTH (*(vu_char *) (CFG_MBAR+0x100007)) +#define MCFGPIO_PORTJ (*(vu_char *) (CFG_MBAR+0x100008)) +#define MCFGPIO_PORTDD (*(vu_char *) (CFG_MBAR+0x100009)) +#define MCFGPIO_PORTEH (*(vu_char *) (CFG_MBAR+0x10000A)) +#define MCFGPIO_PORTEL (*(vu_char *) (CFG_MBAR+0x10000B)) +#define MCFGPIO_PORTAS (*(vu_char *) (CFG_MBAR+0x10000C)) +#define MCFGPIO_PORTQS (*(vu_char *) (CFG_MBAR+0x10000D)) +#define MCFGPIO_PORTSD (*(vu_char *) (CFG_MBAR+0x10000E)) +#define MCFGPIO_PORTTC (*(vu_char *) (CFG_MBAR+0x10000F)) +#define MCFGPIO_PORTTD (*(vu_char *) (CFG_MBAR+0x100010)) +#define MCFGPIO_PORTUA (*(vu_char *) (CFG_MBAR+0x100011)) + +#define MCFGPIO_DDRA (*(vu_char *) (CFG_MBAR+0x100014)) +#define MCFGPIO_DDRB (*(vu_char *) (CFG_MBAR+0x100015)) +#define MCFGPIO_DDRC (*(vu_char *) (CFG_MBAR+0x100016)) +#define MCFGPIO_DDRD (*(vu_char *) (CFG_MBAR+0x100017)) +#define MCFGPIO_DDRE (*(vu_char *) (CFG_MBAR+0x100018)) +#define MCFGPIO_DDRF (*(vu_char *) (CFG_MBAR+0x100019)) +#define MCFGPIO_DDRG (*(vu_char *) (CFG_MBAR+0x10001A)) +#define MCFGPIO_DDRH (*(vu_char *) (CFG_MBAR+0x10001B)) +#define MCFGPIO_DDRJ (*(vu_char *) (CFG_MBAR+0x10001C)) +#define MCFGPIO_DDRDD (*(vu_char *) (CFG_MBAR+0x10001D)) +#define MCFGPIO_DDREH (*(vu_char *) (CFG_MBAR+0x10001E)) +#define MCFGPIO_DDREL (*(vu_char *) (CFG_MBAR+0x10001F)) +#define MCFGPIO_DDRAS (*(vu_char *) (CFG_MBAR+0x100020)) +#define MCFGPIO_DDRQS (*(vu_char *) (CFG_MBAR+0x100021)) +#define MCFGPIO_DDRSD (*(vu_char *) (CFG_MBAR+0x100022)) +#define MCFGPIO_DDRTC (*(vu_char *) (CFG_MBAR+0x100023)) +#define MCFGPIO_DDRTD (*(vu_char *) (CFG_MBAR+0x100024)) +#define MCFGPIO_DDRUA (*(vu_char *) (CFG_MBAR+0x100025)) + +#define MCFGPIO_PORTAP (*(vu_char *) (CFG_MBAR+0x100028)) +#define MCFGPIO_PORTBP (*(vu_char *) (CFG_MBAR+0x100029)) +#define MCFGPIO_PORTCP (*(vu_char *) (CFG_MBAR+0x10002A)) +#define MCFGPIO_PORTDP (*(vu_char *) (CFG_MBAR+0x10002B)) +#define MCFGPIO_PORTEP (*(vu_char *) (CFG_MBAR+0x10002C)) +#define MCFGPIO_PORTFP (*(vu_char *) (CFG_MBAR+0x10002D)) +#define MCFGPIO_PORTGP (*(vu_char *) (CFG_MBAR+0x10002E)) +#define MCFGPIO_PORTHP (*(vu_char *) (CFG_MBAR+0x10002F)) +#define MCFGPIO_PORTJP (*(vu_char *) (CFG_MBAR+0x100030)) +#define MCFGPIO_PORTDDP (*(vu_char *) (CFG_MBAR+0x100031)) +#define MCFGPIO_PORTEHP (*(vu_char *) (CFG_MBAR+0x100032)) +#define MCFGPIO_PORTELP (*(vu_char *) (CFG_MBAR+0x100033)) +#define MCFGPIO_PORTASP (*(vu_char *) (CFG_MBAR+0x100034)) +#define MCFGPIO_PORTQSP (*(vu_char *) (CFG_MBAR+0x100035)) +#define MCFGPIO_PORTSDP (*(vu_char *) (CFG_MBAR+0x100036)) +#define MCFGPIO_PORTTCP (*(vu_char *) (CFG_MBAR+0x100037)) +#define MCFGPIO_PORTTDP (*(vu_char *) (CFG_MBAR+0x100038)) +#define MCFGPIO_PORTUAP (*(vu_char *) (CFG_MBAR+0x100039)) + +#define MCFGPIO_SETA (*(vu_char *) (CFG_MBAR+0x100028)) +#define MCFGPIO_SETB (*(vu_char *) (CFG_MBAR+0x100029)) +#define MCFGPIO_SETC (*(vu_char *) (CFG_MBAR+0x10002A)) +#define MCFGPIO_SETD (*(vu_char *) (CFG_MBAR+0x10002B)) +#define MCFGPIO_SETE (*(vu_char *) (CFG_MBAR+0x10002C)) +#define MCFGPIO_SETF (*(vu_char *) (CFG_MBAR+0x10002D)) +#define MCFGPIO_SETG (*(vu_char *) (CFG_MBAR+0x10002E)) +#define MCFGPIO_SETH (*(vu_char *) (CFG_MBAR+0x10002F)) +#define MCFGPIO_SETJ (*(vu_char *) (CFG_MBAR+0x100030)) +#define MCFGPIO_SETDD (*(vu_char *) (CFG_MBAR+0x100031)) +#define MCFGPIO_SETEH (*(vu_char *) (CFG_MBAR+0x100032)) +#define MCFGPIO_SETEL (*(vu_char *) (CFG_MBAR+0x100033)) +#define MCFGPIO_SETAS (*(vu_char *) (CFG_MBAR+0x100034)) +#define MCFGPIO_SETQS (*(vu_char *) (CFG_MBAR+0x100035)) +#define MCFGPIO_SETSD (*(vu_char *) (CFG_MBAR+0x100036)) +#define MCFGPIO_SETTC (*(vu_char *) (CFG_MBAR+0x100037)) +#define MCFGPIO_SETTD (*(vu_char *) (CFG_MBAR+0x100038)) +#define MCFGPIO_SETUA (*(vu_char *) (CFG_MBAR+0x100039)) + +#define MCFGPIO_CLRA (*(vu_char *) (CFG_MBAR+0x10003C)) +#define MCFGPIO_CLRB (*(vu_char *) (CFG_MBAR+0x10003D)) +#define MCFGPIO_CLRC (*(vu_char *) (CFG_MBAR+0x10003E)) +#define MCFGPIO_CLRD (*(vu_char *) (CFG_MBAR+0x10003F)) +#define MCFGPIO_CLRE (*(vu_char *) (CFG_MBAR+0x100040)) +#define MCFGPIO_CLRF (*(vu_char *) (CFG_MBAR+0x100041)) +#define MCFGPIO_CLRG (*(vu_char *) (CFG_MBAR+0x100042)) +#define MCFGPIO_CLRH (*(vu_char *) (CFG_MBAR+0x100043)) +#define MCFGPIO_CLRJ (*(vu_char *) (CFG_MBAR+0x100044)) +#define MCFGPIO_CLRDD (*(vu_char *) (CFG_MBAR+0x100045)) +#define MCFGPIO_CLREH (*(vu_char *) (CFG_MBAR+0x100046)) +#define MCFGPIO_CLREL (*(vu_char *) (CFG_MBAR+0x100047)) +#define MCFGPIO_CLRAS (*(vu_char *) (CFG_MBAR+0x100048)) +#define MCFGPIO_CLRQS (*(vu_char *) (CFG_MBAR+0x100049)) +#define MCFGPIO_CLRSD (*(vu_char *) (CFG_MBAR+0x10004A)) +#define MCFGPIO_CLRTC (*(vu_char *) (CFG_MBAR+0x10004B)) +#define MCFGPIO_CLRTD (*(vu_char *) (CFG_MBAR+0x10004C)) +#define MCFGPIO_CLRUA (*(vu_char *) (CFG_MBAR+0x10004D)) + +#define MCFGPIO_PBCDPAR (*(vu_char *) (CFG_MBAR+0x100050)) +#define MCFGPIO_PFPAR (*(vu_char *) (CFG_MBAR+0x100051)) +#define MCFGPIO_PEPAR (*(vu_short *)(CFG_MBAR+0x100052)) +#define MCFGPIO_PJPAR (*(vu_char *) (CFG_MBAR+0x100054)) +#define MCFGPIO_PSDPAR (*(vu_char *) (CFG_MBAR+0x100055)) +#define MCFGPIO_PASPAR (*(vu_short *)(CFG_MBAR+0x100056)) +#define MCFGPIO_PEHLPAR (*(vu_char *) (CFG_MBAR+0x100058)) +#define MCFGPIO_PQSPAR (*(vu_char *) (CFG_MBAR+0x100059)) +#define MCFGPIO_PTCPAR (*(vu_char *) (CFG_MBAR+0x10005A)) +#define MCFGPIO_PTDPAR (*(vu_char *) (CFG_MBAR+0x10005B)) +#define MCFGPIO_PUAPAR (*(vu_char *) (CFG_MBAR+0x10005C)) + +/* Bit level definitions and macros */ +#define MCFGPIO_PORT7 (0x80) +#define MCFGPIO_PORT6 (0x40) +#define MCFGPIO_PORT5 (0x20) +#define MCFGPIO_PORT4 (0x10) +#define MCFGPIO_PORT3 (0x08) +#define MCFGPIO_PORT2 (0x04) +#define MCFGPIO_PORT1 (0x02) +#define MCFGPIO_PORT0 (0x01) +#define MCFGPIO_PORT(x) (0x01< + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _CONFIG_EB_MCF_EV123_H_ +#define _CONFIG_EB_MCF_EV123_H_ + +#define CONFIG_EB_MCF_EV123 + +#undef DEBUG +#undef CFG_HALT_BEFOR_RAM_JUMP +#undef ET_DEBUG + +/* + * High Level Configuration Options (easy to change) + */ + +#define CONFIG_MCF52x2 /* define processor family */ +#define CONFIG_M5282 /* define processor type */ + +#define CONFIG_MISC_INIT_R + +#define FEC_ENET +#define CONFIG_ETHADDR 00:CF:52:82:EB:01 + +#define CONFIG_BAUDRATE 9600 +#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } + +#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ + +#define CONFIG_BOOTCOMMAND "printenv" + +/* Configuration for environment + * Environment is embedded in u-boot in the second sector of the flash + */ +#ifndef CONFIG_MONITOR_IS_IN_RAM +#define CFG_ENV_ADDR 0xF003C000 /* End of 256K */ +#define CFG_ENV_SECT_SIZE 0x4000 +#define CFG_ENV_IS_IN_FLASH 1 +/* +#define CFG_ENV_IS_EMBEDDED 1 +#define CFG_ENV_ADDR_REDUND 0xF0018000 +#define CFG_ENV_SECT_SIZE_REDUND 0x4000 +*/ +#else +#define CFG_ENV_ADDR 0xFFE04000 +#define CFG_ENV_SECT_SIZE 0x2000 +#define CFG_ENV_IS_IN_FLASH 1 +#endif + +//#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADS | CFG_CMD_LOADB) ) +#define CONFIG_COMMANDS ( CONFIG_CMD_DFL & ~(CFG_CMD_LOADB)) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include + +#define CONFIG_BOOTDELAY 5 +#define CFG_PROMPT "\nEV123 U-Boot> " +#define CFG_LONGHELP /* undef to save memory */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_LOAD_ADDR 0x20000 + +#define CFG_MEMTEST_START 0x100000 +#define CFG_MEMTEST_END 0x400000 +/*#define CFG_DRAM_TEST 1 */ +#undef CFG_DRAM_TEST + +/* Clock and PLL Configuration */ +#define CFG_HZ 10000000 +#define CFG_CLK 58982400 /* 9,8304MHz * 6 */ + +/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ + +#define CFG_MFD 0x01 /* PLL Multiplication Factor Devider */ +#define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +#define CFG_MBAR 0x40000000 + +#define CFG_DISCOVER_PHY +/* #define CFG_ENET_BD_BASE 0x380000 */ + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR 0x20000000 +#define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE1 0x00000000 +#define CFG_SDRAM_SIZE1 16 /* SDRAM size in MB */ + +/* +#define CFG_SDRAM_BASE0 CFG_SDRAM_BASE1+CFG_SDRAM_SIZE1*1024*1024 +#define CFG_SDRAM_SIZE0 16 */ /* SDRAM size in MB */ + +#define CFG_SDRAM_BASE CFG_SDRAM_BASE1 +#define CFG_SDRAM_SIZE CFG_SDRAM_SIZE1 + +#define CFG_FLASH_BASE 0xFFE00000 +#define CFG_INT_FLASH_BASE 0xF0000000 + +/* If M5282 port is fully implemented the monitor base will be behind + * the vector table. */ +#if (TEXT_BASE != CFG_INT_FLASH_BASE) +#define CFG_MONITOR_BASE (TEXT_BASE + 0x400) +#else +#define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ +#endif + +#define CFG_MONITOR_LEN 0x20000 +#define CFG_MALLOC_LEN (256 << 10) +#define CFG_BOOTPARAMS_LEN 64*1024 + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization ?? + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ +#define CFG_MAX_FLASH_SECT 35 +#define CFG_MAX_FLASH_BANKS 2 +#define CFG_FLASH_ERASE_TOUT 10000000 +#define CFG_FLASH_PROTECTION + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 + +/*----------------------------------------------------------------------- + * Memory bank definitions + */ + +#define CFG_CS0_BASE CFG_FLASH_BASE +#define CFG_CS0_SIZE 2*1024*1024 +#define CFG_CS0_WIDTH 16 +#define CFG_CS0_RO 0 +#define CFG_CS0_WS 6 + +#define CFG_CS3_BASE 0xE0000000 +#define CFG_CS3_SIZE 1*1024*1024 +#define CFG_CS3_WIDTH 16 +#define CFG_CS3_RO 0 +#define CFG_CS3_WS 6 + +/*----------------------------------------------------------------------- + * Port configuration + */ +#define CFG_PACNT 0x0000000 /* Port A D[31:24] */ +#define CFG_PADDR 0x0000000 +#define CFG_PADAT 0x0000000 + +#define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ +#define CFG_PBDDR 0x0000000 +#define CFG_PBDAT 0x0000000 + +#define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ +#define CFG_PCDDR 0x0000000 +#define CFG_PCDAT 0x0000000 + +#define CFG_PEHLPAR 0xC0 +#define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ +#define CFG_DDRUA 0x05 +#define CFG_PJPAR 0xFF; + +/*----------------------------------------------------------------------- + * CCM configuration + */ + +#define CFG_CCM_SIZ 0 + +/*---------------------------------------------------------------------*/ +#endif /* _CONFIG_M5282EVB_H */ +/*---------------------------------------------------------------------*/ -- cgit v1.2.3