From 48cd7a1f6ccb7d971460e95a2b6c053d6e2a28d1 Mon Sep 17 00:00:00 2001 From: Vagrant Cascadian Date: Wed, 6 Apr 2022 13:42:03 -0700 Subject: rockchip: Enable SCSI in distro bootcmd for rk3399. Include SCSI in the list of boot targets if CONFIG_CMD_SCSI is enabled. Signed-off-by: Vagrant Cascadian Reviewed-by: Kever Yang --- include/configs/rockchip-common.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index ba7061a287c..0c08776ae26 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -29,6 +29,12 @@ #define BOOT_TARGET_NVME(func) #endif +#if CONFIG_IS_ENABLED(CMD_SCSI) + #define BOOT_TARGET_SCSI(func) func(SCSI, scsi, 0) +#else + #define BOOT_TARGET_SCSI(func) +#endif + #if CONFIG_IS_ENABLED(CMD_USB) #define BOOT_TARGET_USB(func) func(USB, usb, 0) #else @@ -57,6 +63,7 @@ #define BOOT_TARGET_DEVICES(func) \ BOOT_TARGET_MMC(func) \ BOOT_TARGET_NVME(func) \ + BOOT_TARGET_SCSI(func) \ BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) \ -- cgit v1.3.1 From 54562045e5937e724ae574f02bdb040338d258be Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 9 Apr 2022 18:55:02 +0200 Subject: rockchip: move ROCKCHIP_STIMER_BASE to Kconfig Move ROCKCHIP_STIMER_BASE to Kconfig. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/mach-rockchip/Kconfig | 10 ++++++++++ arch/arm/mach-rockchip/px30/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3036/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3128/Kconfig | 3 +++ arch/arm/mach-rockchip/rk322x/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3288/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3308/Kconfig | 10 ++++++---- arch/arm/mach-rockchip/rk3328/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3368/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3399/Kconfig | 3 +++ arch/arm/mach-rockchip/rk3568/Kconfig | 3 +++ configs/rock_defconfig | 1 + include/configs/px30_common.h | 1 - include/configs/rk3036_common.h | 1 - include/configs/rk3128_common.h | 1 - include/configs/rk322x_common.h | 1 - include/configs/rk3288_common.h | 1 - include/configs/rk3308_common.h | 1 - include/configs/rk3328_common.h | 1 - include/configs/rk3368_common.h | 1 - include/configs/rk3399_common.h | 1 - include/configs/rk3568_common.h | 1 - 22 files changed, 44 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 308dc09b038..811964973ae 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -339,6 +339,16 @@ config ROCKCHIP_BOOT_MODE_REG The Soc will enter to different boot mode(defined in asm/arch-rockchip/boot_mode.h) according to the value from this register. +config ROCKCHIP_STIMER + bool "Rockchip STIMER support" + default y + help + Enable Rockchip STIMER support. + +config ROCKCHIP_STIMER_BASE + hex + depends on ROCKCHIP_STIMER + config ROCKCHIP_SPL_RESERVE_IRAM hex "Size of IRAM reserved in SPL" default 0 diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 145bf3591ff..4886fe946e3 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -38,6 +38,9 @@ config TARGET_PX30_CORE config ROCKCHIP_BOOT_MODE_REG default 0xff010200 +config ROCKCHIP_STIMER_BASE + default 0xff220020 + config SYS_SOC default "px30" diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig index b746795d813..111531be1ef 100644 --- a/arch/arm/mach-rockchip/rk3036/Kconfig +++ b/arch/arm/mach-rockchip/rk3036/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x200081c8 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3036" diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig index b867401c7f5..9cc494eb409 100644 --- a/arch/arm/mach-rockchip/rk3128/Kconfig +++ b/arch/arm/mach-rockchip/rk3128/Kconfig @@ -16,6 +16,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0x100a0038 +config ROCKCHIP_STIMER_BASE + default 0x200440a0 + config SYS_SOC default "rk3128" diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 6458cd55814..058f848ddc7 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -8,6 +8,9 @@ config TARGET_EVB_RK3229 config ROCKCHIP_BOOT_MODE_REG default 0x110005c8 +config ROCKCHIP_STIMER_BASE + default 0x110d0020 + config SYS_SOC default "rk322x" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index f37b1bdfd50..dd8c7826fc1 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -148,6 +148,9 @@ config ROCKCHIP_FAST_SPL config ROCKCHIP_BOOT_MODE_REG default 0xff730094 +config ROCKCHIP_STIMER_BASE + default 0xff810020 + config SYS_SOC default "rk3288" diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index 8fa536e15dc..194353e4cd9 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -8,6 +8,12 @@ config TARGET_ROC_RK3308_CC bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT +config ROCKCHIP_BOOT_MODE_REG + default 0xff000500 + +config ROCKCHIP_STIMER_BASE + default 0xff1b00a0 + config SYS_SOC default "rk3308" @@ -17,10 +23,6 @@ config SYS_MALLOC_F_LEN config SPL_SERIAL default y -config ROCKCHIP_BOOT_MODE_REG - default 0xff000500 - - source "board/rockchip/evb_rk3308/Kconfig" source "board/firefly/firefly-rk3308/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig index d13a1690226..f6f1e06a83f 100644 --- a/arch/arm/mach-rockchip/rk3328/Kconfig +++ b/arch/arm/mach-rockchip/rk3328/Kconfig @@ -15,6 +15,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff1005c8 +config ROCKCHIP_STIMER_BASE + default 0xff1d0020 + config SYS_SOC default "rk3328" diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index 78eb96df3d1..104db36737b 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -45,6 +45,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff738200 +config ROCKCHIP_STIMER_BASE + default 0xff830020 + config SYS_SOC default "rk3368" diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 0833e083d9e..c1f251316cb 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -125,6 +125,9 @@ endchoice config ROCKCHIP_BOOT_MODE_REG default 0xff320300 +config ROCKCHIP_STIMER_BASE + default 0xff8680a0 + config SYS_SOC default "rk3399" diff --git a/arch/arm/mach-rockchip/rk3568/Kconfig b/arch/arm/mach-rockchip/rk3568/Kconfig index 201c63c2a9c..4e7c02cce06 100644 --- a/arch/arm/mach-rockchip/rk3568/Kconfig +++ b/arch/arm/mach-rockchip/rk3568/Kconfig @@ -9,6 +9,9 @@ config TARGET_EVB_RK3568 config ROCKCHIP_BOOT_MODE_REG default 0xfdc20200 +config ROCKCHIP_STIMER_BASE + default 0xfdd1c020 + config SYS_SOC default "rk3568" diff --git a/configs/rock_defconfig b/configs/rock_defconfig index 290f5afd787..4aa4608f904 100644 --- a/configs/rock_defconfig +++ b/configs/rock_defconfig @@ -11,6 +11,7 @@ CONFIG_ENV_OFFSET=0x3F8000 CONFIG_DEFAULT_DEVICE_TREE="rk3188-radxarock" CONFIG_SPL_TEXT_BASE=0x10080800 CONFIG_ROCKCHIP_RK3188=y +# CONFIG_ROCKCHIP_STIMER is not set CONFIG_TARGET_ROCK=y CONFIG_SPL_STACK_R_ADDR=0x60080000 CONFIG_DEBUG_UART_BASE=0x20064000 diff --git a/include/configs/px30_common.h b/include/configs/px30_common.h index 09923871571..dc609013f32 100644 --- a/include/configs/px30_common.h +++ b/include/configs/px30_common.h @@ -12,7 +12,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff220020 #define COUNTER_FREQUENCY 24000000 /* FIXME: ff020000 is pmu_mem (10k), while ff0e0000 is regular int_mem */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h index 00c453d739d..5905518edf1 100644 --- a/include/configs/rk3036_common.h +++ b/include/configs/rk3036_common.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h index 97caceacfe6..d77a7d7b098 100644 --- a/include/configs/rk3128_common.h +++ b/include/configs/rk3128_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h index ef55ef0a83b..3258820fcdc 100644 --- a/include/configs/rk322x_common.h +++ b/include/configs/rk322x_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ -#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index 490da7cb23b..e2e0f70a70c 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -13,7 +13,6 @@ #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_HZ_CLOCK 24000000 diff --git a/include/configs/rk3308_common.h b/include/configs/rk3308_common.h index 1664707ca65..9cda8d9c48b 100644 --- a/include/configs/rk3308_common.h +++ b/include/configs/rk3308_common.h @@ -15,7 +15,6 @@ #define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1b00a0 #define CONFIG_IRAM_BASE 0xfff80000 #define CONFIG_SYS_INIT_SP_ADDR 0x00800000 #define CONFIG_SPL_STACK 0x00400000 diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index c1e26a019b5..8a5f0c8999f 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -10,7 +10,6 @@ #define CONFIG_IRAM_BASE 0xff090000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_SYS_CBSIZE 1024 diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h index 8b239ca07da..239296c1d22 100644 --- a/include/configs/rk3368_common.h +++ b/include/configs/rk3368_common.h @@ -15,7 +15,6 @@ #define SDRAM_MAX_SIZE 0xff000000 #define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 #define COUNTER_FREQUENCY 24000000 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h index ed72c8bb6b1..4037dba58cc 100644 --- a/include/configs/rk3399_common.h +++ b/include/configs/rk3399_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 #define CONFIG_IRAM_BASE 0xff8c0000 diff --git a/include/configs/rk3568_common.h b/include/configs/rk3568_common.h index 25d7c5cc8ff..5649cd64e0e 100644 --- a/include/configs/rk3568_common.h +++ b/include/configs/rk3568_common.h @@ -11,7 +11,6 @@ #define CONFIG_SYS_CBSIZE 1024 #define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xfdd1c020 #define CONFIG_IRAM_BASE 0xfdcc0000 -- cgit v1.3.1 From 5e6ee6bde5dd8ef804665b6bf45237e30f45575b Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:37 +0200 Subject: rockchip: rk3066-power: sync power domain dt-binding header from Linux In order to update the DT for rk3066 sync the power domain dt-binding header. This is the state as of v5.12 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3066-power.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 include/dt-bindings/power/rk3066-power.h (limited to 'include') diff --git a/include/dt-bindings/power/rk3066-power.h b/include/dt-bindings/power/rk3066-power.h new file mode 100644 index 00000000000..acf9f310ac5 --- /dev/null +++ b/include/dt-bindings/power/rk3066-power.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__ +#define __DT_BINDINGS_POWER_RK3066_POWER_H__ + +/* VD_CORE */ +#define RK3066_PD_A9_0 0 +#define RK3066_PD_A9_1 1 +#define RK3066_PD_DBG 4 +#define RK3066_PD_SCU 5 + +/* VD_LOGIC */ +#define RK3066_PD_VIDEO 6 +#define RK3066_PD_VIO 7 +#define RK3066_PD_GPU 8 +#define RK3066_PD_PERI 9 +#define RK3066_PD_CPU 10 +#define RK3066_PD_ALIVE 11 + +/* VD_PMU */ +#define RK3066_PD_RTC 12 + +#endif -- cgit v1.3.1 From 33f4750783080302afd8f00bb07bd18d6e94f073 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Sat, 16 Apr 2022 17:09:47 +0200 Subject: rockchip: rk3066: add core support Add the core architecture code for the rk3066. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/include/asm/arch-rk3066/boot0.h | 8 ++++ arch/arm/include/asm/arch-rk3066/gpio.h | 8 ++++ arch/arm/include/asm/arch-rk3066/timer.h | 6 +++ arch/arm/mach-rockchip/Kconfig | 23 +++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3066/Kconfig | 30 +++++++++++++++ arch/arm/mach-rockchip/rk3066/Makefile | 5 +++ arch/arm/mach-rockchip/rk3066/clk_rk3066.c | 33 ++++++++++++++++ arch/arm/mach-rockchip/rk3066/rk3066.c | 49 ++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3066/syscon_rk3066.c | 55 +++++++++++++++++++++++++++ include/configs/mk808.h | 9 +++++ include/configs/rk3066_common.h | 47 +++++++++++++++++++++++ 12 files changed, 274 insertions(+) create mode 100644 arch/arm/include/asm/arch-rk3066/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3066/gpio.h create mode 100644 arch/arm/include/asm/arch-rk3066/timer.h create mode 100644 arch/arm/mach-rockchip/rk3066/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3066/Makefile create mode 100644 arch/arm/mach-rockchip/rk3066/clk_rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/rk3066.c create mode 100644 arch/arm/mach-rockchip/rk3066/syscon_rk3066.c create mode 100644 include/configs/mk808.h create mode 100644 include/configs/rk3066_common.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-rk3066/boot0.h b/arch/arm/include/asm/arch-rk3066/boot0.h new file mode 100644 index 00000000000..28c0fb9a4c6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/boot0.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/gpio.h b/arch/arm/include/asm/arch-rk3066/gpio.h new file mode 100644 index 00000000000..a4a3b3289c2 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include + +#endif diff --git a/arch/arm/include/asm/arch-rk3066/timer.h b/arch/arm/include/asm/arch-rk3066/timer.h new file mode 100644 index 00000000000..3bb39428cd6 --- /dev/null +++ b/arch/arm/include/asm/arch-rk3066/timer.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __ASM_ARCH_TIMER_H__ +#define __ASM_ARCH_TIMER_H__ + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 811964973ae..18aff5480ba 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -35,6 +35,28 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs. +config ROCKCHIP_RK3066 + bool "Support Rockchip RK3066" + select CPU_V7A + select SPL_BOARD_INIT if SPL + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select TPL_ROCKCHIP_BACK_TO_BROM + select TPL_ROCKCHIP_EARLYRETURN_TO_BROM + imply ROCKCHIP_COMMON_BOARD + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + help + The Rockchip RK3066 is a ARM-based SoC with a dual-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3128 bool "Support Rockchip RK3128" select CPU_V7A @@ -405,6 +427,7 @@ config LNX_KRNL_IMG_TEXT_OFFSET_BASE source "arch/arm/mach-rockchip/px30/Kconfig" source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3066/Kconfig" source "arch/arm/mach-rockchip/rk3128/Kconfig" source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk322x/Kconfig" diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 00aef0ecee6..6c1c7b8a108 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o obj-$(CONFIG_ROCKCHIP_PX30) += px30/ obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ +obj-$(CONFIG_ROCKCHIP_RK3066) += rk3066/ obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/ obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ obj-$(CONFIG_ROCKCHIP_RK322X) += rk322x/ diff --git a/arch/arm/mach-rockchip/rk3066/Kconfig b/arch/arm/mach-rockchip/rk3066/Kconfig new file mode 100644 index 00000000000..335f49bc557 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Kconfig @@ -0,0 +1,30 @@ +if ROCKCHIP_RK3066 + +config ROCKCHIP_BOOT_MODE_REG + default 0x20004040 + +config SYS_SOC + default "rk3066" + +config SYS_MALLOC_F_LEN + default 0x0800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL + default y + +config TPL_LIBCOMMON_SUPPORT + default y + +config TPL_LIBGENERIC_SUPPORT + default y + +config TPL_SERIAL + default y + +endif diff --git a/arch/arm/mach-rockchip/rk3066/Makefile b/arch/arm/mach-rockchip/rk3066/Makefile new file mode 100644 index 00000000000..9e2a9d4b0aa --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ + +obj-y += clk_rk3066.o +obj-y += rk3066.o +obj-y += syscon_rk3066.o diff --git a/arch/arm/mach-rockchip/rk3066/clk_rk3066.c b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c new file mode 100644 index 00000000000..c47526dca5d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/clk_rk3066.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include +#include + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rk3066a_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3066_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3066/rk3066.c b/arch/arm/mach-rockchip/rk3066/rk3066.c new file mode 100644 index 00000000000..78c7d894f90 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/rk3066.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include + +#define GRF_BASE 0x20008000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@1021c000", + [BROM_BOOTSOURCE_SD] = "/mmc@10214000", +}; + +void board_debug_uart_init(void) +{ + struct rk3066_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART on the RK3066 */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK | GPIO1B0_MASK, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); +} + +void spl_board_init(void) +{ + if (!IS_ENABLED(CONFIG_SPL_BUILD)) + return; + + if (IS_ENABLED(CONFIG_SPL_DM_MMC)) { + struct rk3066_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK | GPIO3B1_MASK | GPIO3B2_MASK | + GPIO3B3_MASK | GPIO3B4_MASK | GPIO3B5_MASK | + GPIO3B6_MASK, + GPIO3B0_SDMMC0_CLKOUT << GPIO3B0_SHIFT | + GPIO3B1_SDMMC0_CMD << GPIO3B1_SHIFT | + GPIO3B2_SDMMC0_DATA0 << GPIO3B2_SHIFT | + GPIO3B3_SDMMC0_DATA1 << GPIO3B3_SHIFT | + GPIO3B4_SDMMC0_DATA2 << GPIO3B4_SHIFT | + GPIO3B5_SDMMC0_DATA3 << GPIO3B5_SHIFT | + GPIO3B6_SDMMC0_DECTN << GPIO3B6_SHIFT); + } +} diff --git a/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c new file mode 100644 index 00000000000..a598f6400de --- /dev/null +++ b/arch/arm/mach-rockchip/rk3066/syscon_rk3066.c @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass + */ + +#include +#include +#include +#include +#include + +static const struct udevice_id rk3066_syscon_ids[] = { + { .compatible = "rockchip,rk3066-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3066-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3066-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3066) = { + .name = "rk3066_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3066_syscon_bind_of_plat(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3066_noc) = { + .name = "rockchip_rk3066_noc", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_grf) = { + .name = "rockchip_rk3066_grf", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 1, + .bind = rk3066_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rk3066_pmu) = { + .name = "rockchip_rk3066_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3066_syscon_ids + 2, + .bind = rk3066_syscon_bind_of_plat, +}; +#endif diff --git a/include/configs/mk808.h b/include/configs/mk808.h new file mode 100644 index 00000000000..e2ab2b512c8 --- /dev/null +++ b/include/configs/mk808.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS +#include + +#endif diff --git a/include/configs/rk3066_common.h b/include/configs/rk3066_common.h new file mode 100644 index 00000000000..be7d644e1e5 --- /dev/null +++ b/include/configs/rk3066_common.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2015 Google, Inc + */ + +#ifndef __CONFIG_RK3066_COMMON_H +#define __CONFIG_RK3066_COMMON_H + +#include +#include "rockchip-common.h" + +#define CONFIG_SYS_CBSIZE 256 + +#define CONFIG_SYS_INIT_SP_ADDR 0x78000000 + +#define CONFIG_IRAM_BASE 0x10080000 + +#define CONFIG_SPL_MAX_SIZE 0x32000 + +#define CONFIG_SPL_STACK 0x1008FFFF + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define SDRAM_BANK_SIZE (1024UL << 20UL) +#define SDRAM_MAX_SIZE CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE + +#ifndef CONFIG_SPL_BUILD + +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#endif -- cgit v1.3.1 From 3c48a6246027a06453cb6519ce7a4edbce499c9d Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:32 +0200 Subject: rockchip: rk3228-power: sync power domain dt-binding header from Linux In order to update the DT for rk3228 sync the power domain dt-binding header. This is the state as of v5.17 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/power/rk3228-power.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/power/rk3228-power.h (limited to 'include') diff --git a/include/dt-bindings/power/rk3228-power.h b/include/dt-bindings/power/rk3228-power.h new file mode 100644 index 00000000000..6a8dc1bf76c --- /dev/null +++ b/include/dt-bindings/power/rk3228-power.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3228_POWER_H__ +#define __DT_BINDINGS_POWER_RK3228_POWER_H__ + +/** + * RK3228 idle id Summary. + */ + +#define RK3228_PD_CORE 0 +#define RK3228_PD_MSCH 1 +#define RK3228_PD_BUS 2 +#define RK3228_PD_SYS 3 +#define RK3228_PD_VIO 4 +#define RK3228_PD_VOP 5 +#define RK3228_PD_VPU 6 +#define RK3228_PD_RKVDEC 7 +#define RK3228_PD_GPU 8 +#define RK3228_PD_PERI 9 +#define RK3228_PD_GMAC 10 + +#endif -- cgit v1.3.1 From 6914ef8e6773e490d4c6b412d21143b27bb00b02 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:33 +0200 Subject: rockchip: rk3228-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3228 sync the clock dt-binding header. This is the state as of v5.17 in Linux. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3228-cru.h | 54 ++++++++++++++++++++++++++++++++-- 1 file changed, 52 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 1217d5239f5..de550ea56ee 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -1,6 +1,7 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd. + * Copyright (c) 2015 Rockchip Electronics Co. Ltd. + * Author: Jeffy Chen */ #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H @@ -39,6 +40,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 +#define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 @@ -51,6 +53,18 @@ #define SCLK_MAC_TX 130 #define SCLK_MAC_PHY 131 #define SCLK_MAC_OUT 132 +#define SCLK_VDEC_CABAC 133 +#define SCLK_VDEC_CORE 134 +#define SCLK_RGA 135 +#define SCLK_HDCP 136 +#define SCLK_HDMI_CEC 137 +#define SCLK_CRYPTO 138 +#define SCLK_TSP 139 +#define SCLK_HSADC 140 +#define SCLK_WIFI 141 +#define SCLK_OTGPHY0 142 +#define SCLK_OTGPHY1 143 +#define SCLK_HDMI_PHY 144 /* dclk gates */ #define DCLK_VOP 190 @@ -58,15 +72,32 @@ /* aclk gates */ #define ACLK_DMAC 194 +#define ACLK_CPU 195 +#define ACLK_VPU_PRE 196 +#define ACLK_RKVDEC_PRE 197 +#define ACLK_RGA_PRE 198 +#define ACLK_IEP_PRE 199 +#define ACLK_HDCP_PRE 200 +#define ACLK_VOP_PRE 201 +#define ACLK_VPU 202 +#define ACLK_RKVDEC 203 +#define ACLK_IEP 204 +#define ACLK_RGA 205 +#define ACLK_HDCP 206 #define ACLK_PERI 210 #define ACLK_VOP 211 #define ACLK_GMAC 212 +#define ACLK_GPU 213 /* pclk gates */ #define PCLK_GPIO0 320 #define PCLK_GPIO1 321 #define PCLK_GPIO2 322 #define PCLK_GPIO3 323 +#define PCLK_VIO_H2P 324 +#define PCLK_HDCP 325 +#define PCLK_EFUSE_1024 326 +#define PCLK_EFUSE_256 327 #define PCLK_GRF 329 #define PCLK_I2C0 332 #define PCLK_I2C1 333 @@ -79,6 +110,7 @@ #define PCLK_TSADC 344 #define PCLK_PWM 350 #define PCLK_TIMER 353 +#define PCLK_CPU 354 #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 @@ -94,6 +126,24 @@ #define HCLK_SDMMC 456 #define HCLK_SDIO 457 #define HCLK_EMMC 459 +#define HCLK_CPU 460 +#define HCLK_VPU_PRE 461 +#define HCLK_RKVDEC_PRE 462 +#define HCLK_VIO_PRE 463 +#define HCLK_VPU 464 +#define HCLK_RKVDEC 465 +#define HCLK_VIO 466 +#define HCLK_RGA 467 +#define HCLK_IEP 468 +#define HCLK_VIO_H2P 469 +#define HCLK_HDCP_MMU 470 +#define HCLK_HOST0 471 +#define HCLK_HOST1 472 +#define HCLK_HOST2 473 +#define HCLK_OTG 474 +#define HCLK_TSP 475 +#define HCLK_M_CRYPTO 476 +#define HCLK_S_CRYPTO 477 #define HCLK_PERI 478 #define CLK_NR_CLKS (HCLK_PERI + 1) -- cgit v1.3.1 From 444311196e6e84c3e87f82bdc53b6510d0919e84 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:37 +0200 Subject: rockchip: rk3288-power: sync power domain dt-binding header from Linux In order to update the DT for rk3288 sync the power domain dt-binding header. This is the state as of v5.17 in Linux. Change location to be more in line with other SoCs. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/rk3288.dtsi | 2 +- include/dt-bindings/power-domain/rk3288.h | 11 ----------- include/dt-bindings/power/rk3288-power.h | 32 +++++++++++++++++++++++++++++++ 3 files changed, 33 insertions(+), 12 deletions(-) delete mode 100644 include/dt-bindings/power-domain/rk3288.h create mode 100644 include/dt-bindings/power/rk3288-power.h (limited to 'include') diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 22bb06cec5b..2086dbfda44 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include "skeleton.dtsi" diff --git a/include/dt-bindings/power-domain/rk3288.h b/include/dt-bindings/power-domain/rk3288.h deleted file mode 100644 index ca68c11475c..00000000000 --- a/include/dt-bindings/power-domain/rk3288.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ -#define __DT_BINDINGS_POWER_DOMAIN_RK3288_H__ - -/* RK3288 power domain index */ -#define RK3288_PD_GPU 0 -#define RK3288_PD_VIO 1 -#define RK3288_PD_VIDEO 2 -#define RK3288_PD_HEVC 3 -#define RK3288_PD_PERI 4 - -#endif diff --git a/include/dt-bindings/power/rk3288-power.h b/include/dt-bindings/power/rk3288-power.h new file mode 100644 index 00000000000..f710b56ccd8 --- /dev/null +++ b/include/dt-bindings/power/rk3288-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __DT_BINDINGS_POWER_RK3288_POWER_H__ +#define __DT_BINDINGS_POWER_RK3288_POWER_H__ + +/** + * RK3288 Power Domain and Voltage Domain Summary. + */ + +/* VD_CORE */ +#define RK3288_PD_A17_0 0 +#define RK3288_PD_A17_1 1 +#define RK3288_PD_A17_2 2 +#define RK3288_PD_A17_3 3 +#define RK3288_PD_SCU 4 +#define RK3288_PD_DEBUG 5 +#define RK3288_PD_MEM 6 + +/* VD_LOGIC */ +#define RK3288_PD_BUS 7 +#define RK3288_PD_PERI 8 +#define RK3288_PD_VIO 9 +#define RK3288_PD_ALIVE 10 +#define RK3288_PD_HEVC 11 +#define RK3288_PD_VIDEO 12 + +/* VD_GPU */ +#define RK3288_PD_GPU 13 + +/* VD_PMU */ +#define RK3288_PD_PMU 14 + +#endif -- cgit v1.3.1 From 334d519a13e4636dd454738510fc840467109b0e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Fri, 15 Apr 2022 23:21:38 +0200 Subject: rockchip: rk3288-cru: sync the clock dt-binding header from Linux In order to update the DT for rk3288 sync the clock dt-binding header. This is the state as of v5.17 in Linux. Keep SCLK_MAC_PLL in use for rk3288 clock driver. Signed-off-by: Johan Jonker Reviewed-by: Simon Glass Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3288-cru.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/dt-bindings/clock/rk3288-cru.h b/include/dt-bindings/clock/rk3288-cru.h index e368d767506..453f66718c6 100644 --- a/include/dt-bindings/clock/rk3288-cru.h +++ b/include/dt-bindings/clock/rk3288-cru.h @@ -1,9 +1,12 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Copyright (c) 2014 MundoReader S.L. * Author: Heiko Stuebner */ +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3288_H + /* core clocks */ #define PLL_APLL 1 #define PLL_DPLL 2 @@ -74,6 +77,9 @@ #define SCLK_USBPHY480M_SRC 122 #define SCLK_PVTM_CORE 123 #define SCLK_PVTM_GPU 124 +#define SCLK_CRYPTO 125 +#define SCLK_MIPIDSI_24M 126 +#define SCLK_VIP_OUT 127 #define SCLK_MAC_PLL 150 #define SCLK_MAC 151 @@ -153,6 +159,9 @@ #define PCLK_DDRUPCTL1 366 #define PCLK_PUBL1 367 #define PCLK_WDT 368 +#define PCLK_EFUSE256 369 +#define PCLK_EFUSE1024 370 +#define PCLK_ISP_IN 371 /* hclk gates */ #define HCLK_GPS 448 @@ -368,3 +377,5 @@ #define SRST_TSP_CLKIN0 189 #define SRST_TSP_CLKIN1 190 #define SRST_TSP_27M 191 + +#endif -- cgit v1.3.1