From 9729dc9565c9c1812efbb630e1db4d54f580363c Mon Sep 17 00:00:00 2001 From: Rajesh Bhagat Date: Tue, 7 Jun 2016 18:59:34 +0530 Subject: include: usb: Rename USB controller base address mapping Remove Soc specific defines and use generic chasis specific defines for USB controller base address mapping. Signed-off-by: Rajesh Bhagat Reviewed-by: York Sun --- include/linux/usb/xhci-fsl.h | 20 ++++++++------------ include/usb/ehci-ci.h | 2 +- 2 files changed, 9 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h index 253eddf1590..199f3667eb4 100644 --- a/include/linux/usb/xhci-fsl.h +++ b/include/linux/usb/xhci-fsl.h @@ -51,22 +51,18 @@ struct fsl_xhci { struct dwc3 *dwc3_reg; }; -#if defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR +#if defined(CONFIG_LS102XA) || defined(CONFIG_LS1012A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR #define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 #elif defined(CONFIG_LS2080A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 -#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR -#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR -#elif defined(CONFIG_LS1012A) -#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR -#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0 +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 +#elif defined(CONFIG_LS1043A) +#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB1_ADDR +#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB2_ADDR +#define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_XHCI_USB3_ADDR #endif #define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \ diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h index 586d32ab52d..882aed4a5f0 100644 --- a/include/usb/ehci-ci.h +++ b/include/usb/ehci-ci.h @@ -160,7 +160,7 @@ #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #elif defined(CONFIG_LS102XA) -#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR +#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR #define CONFIG_SYS_FSL_USB2_ADDR 0 #endif -- cgit v1.3.1 From 69d4b48c84b9c2b762066c5a68406a53e49ea2f3 Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Tue, 14 Jun 2016 13:52:39 -0400 Subject: SECURE_BOOT: Enable SD as a source for bootscript Add support for reading bootscript and bootscript header from SD. Also renamed macros *_FLASH to *_DEVICE to represent SD alongwith NAND and NOR flash. Reviewed-by: Aneesh Bansal Signed-off-by: Sumit Garg Reviewed-by: Simon Glass Reviewed-by: York Sun --- arch/arm/include/asm/fsl_secure_boot.h | 43 ++++++++++++++++++++---------- arch/powerpc/include/asm/fsl_secure_boot.h | 4 +-- include/config_fsl_chain_trust.h | 18 ++++++++----- 3 files changed, 42 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 3f76c9a1032..b35c271bba1 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -78,37 +78,52 @@ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" #else #define CONFIG_EXTRA_ENV \ - "setenv fdt_high 0xcfffffff;" \ - "setenv initrd_high 0xcfffffff;" \ + "setenv fdt_high 0xffffffff;" \ + "setenv initrd_high 0xffffffff;" \ "setenv hwconfig \'fsl_ddr:ctlr_intlv=null,bank_intlv=null\';" #endif /* Copying Bootscript and Header to DDR from NOR for LS2 and for rest, from * Non-XIP Memory (Nand/SD)*/ -#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_LS2080A) || \ + defined(CONFIG_SD_BOOT) #define CONFIG_BOOTSCRIPT_COPY_RAM #endif -/* The address needs to be modified according to NOR and DDR memory map */ +/* The address needs to be modified according to NOR, NAND, SD and + * DDR memory map + */ #ifdef CONFIG_LS2080A -#define CONFIG_BS_HDR_ADDR_FLASH 0x583920000 -#define CONFIG_BS_ADDR_FLASH 0x583900000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x583920000 +#define CONFIG_BS_ADDR_DEVICE 0x583900000 #define CONFIG_BS_HDR_ADDR_RAM 0xa3920000 #define CONFIG_BS_ADDR_RAM 0xa3900000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#else +#ifdef CONFIG_SD_BOOT +/* For SD boot address and size are assigned in terms of sector + * offset and no. of sectors respectively. + */ +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00000800 +#define CONFIG_BS_ADDR_DEVICE 0x00000840 +#define CONFIG_BS_HDR_SIZE 0x00000010 +#define CONFIG_BS_SIZE 0x00000008 #else -#define CONFIG_BS_HDR_ADDR_FLASH 0x600a0000 -#define CONFIG_BS_ADDR_FLASH 0x60060000 -#define CONFIG_BS_HDR_ADDR_RAM 0xa0060000 -#define CONFIG_BS_ADDR_RAM 0xa0060000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x600a0000 +#define CONFIG_BS_ADDR_DEVICE 0x60060000 +#define CONFIG_BS_HDR_SIZE 0x00002000 +#define CONFIG_BS_SIZE 0x00001000 +#endif /* #ifdef CONFIG_SD_BOOT */ +#define CONFIG_BS_HDR_ADDR_RAM 0x81000000 +#define CONFIG_BS_ADDR_RAM 0x81020000 #endif #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM -#define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BOOTSCRIPT_ADDR CONFIG_BS_ADDR_RAM -#define CONFIG_BS_SIZE 0x00001000 #else -#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_FLASH -/* BS_HDR_SIZE, BOOTSCRIPT_ADDR and BS_SIZE are not required */ +#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_DEVICE +/* BOOTSCRIPT_ADDR is not required */ #endif #include diff --git a/arch/powerpc/include/asm/fsl_secure_boot.h b/arch/powerpc/include/asm/fsl_secure_boot.h index 2e2d565ba43..2e937f0364b 100644 --- a/arch/powerpc/include/asm/fsl_secure_boot.h +++ b/arch/powerpc/include/asm/fsl_secure_boot.h @@ -128,10 +128,10 @@ /* If Boot Script is not on NOR and is required to be copied on RAM */ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_HDR_ADDR_RAM 0x00010000 -#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000 +#define CONFIG_BS_HDR_ADDR_DEVICE 0x00800000 #define CONFIG_BS_HDR_SIZE 0x00002000 #define CONFIG_BS_ADDR_RAM 0x00012000 -#define CONFIG_BS_ADDR_FLASH 0x00802000 +#define CONFIG_BS_ADDR_DEVICE 0x00802000 #define CONFIG_BS_SIZE 0x00001000 #define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h index 566fd80a05c..eb45e9851f0 100644 --- a/include/config_fsl_chain_trust.h +++ b/include/config_fsl_chain_trust.h @@ -74,23 +74,27 @@ #ifdef CONFIG_BOOTSCRIPT_COPY_RAM #define CONFIG_BS_COPY_ENV \ "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ - "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_device " __stringify(CONFIG_BS_HDR_ADDR_DEVICE)";" \ "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ - "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_device " __stringify(CONFIG_BS_ADDR_DEVICE)";" \ "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" /* For secure boot flow, default environment used will be used */ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_NAND) #define CONFIG_BS_COPY_CMD \ - "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ - "nand read $bs_ram $bs_flash $bs_size ;" + "nand read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "nand read $bs_ram $bs_device $bs_size ;" #endif /* CONFIG_RAMBOOT_NAND */ -#else +#elif defined(CONFIG_SD_BOOT) +#define CONFIG_BS_COPY_CMD \ + "mmc read $bs_hdr_ram $bs_hdr_device $bs_hdr_size ;" \ + "mmc read $bs_ram $bs_device $bs_size ;" +#else /* CONFIG_SD_BOOT */ #define CONFIG_BS_COPY_CMD \ - "cp.b $bs_hdr_flash $bs_hdr_ram $bs_hdr_size ;" \ - "cp.b $bs_flash $bs_ram $bs_size ;" + "cp.b $bs_hdr_device $bs_hdr_ram $bs_hdr_size ;" \ + "cp.b $bs_device $bs_ram $bs_size ;" #endif #endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ -- cgit v1.3.1 From e7e720c2cef046f67f23db0a54bd65f8b662531e Mon Sep 17 00:00:00 2001 From: Sumit Garg Date: Tue, 14 Jun 2016 13:52:40 -0400 Subject: arm: ls1021atwr: Add SD secure boot target Add SD secure boot target for ls1021atwr. Implement board specific spl_board_init() to setup CAAM stream ID and corresponding stream ID in SMMU. Change the u-boot size defined by a macro for copying the main U-Boot by SPL to also include the u-boot Secure Boot header size as header is appended to u-boot image. So header will also be copied from SD to DDR. Reviewed-by: Aneesh Bansal Signed-off-by: Sumit Garg Reviewed-by: Simon Glass Reviewed-by: York Sun --- board/freescale/ls1021atwr/ls1021atwr.c | 7 +++++ .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 31 ++++++++++++++++++++++ include/configs/ls1021atwr.h | 22 +++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig (limited to 'include') diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index c69c9cba42e..77482a947bf 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -503,6 +503,13 @@ int board_init(void) return 0; } +#if defined(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + ls102xa_smmu_stream_id_init(); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig new file mode 100644 index 00000000000..c735d6da5ea --- /dev/null +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATWR=y +CONFIG_SPL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SECURE_BOOT" +CONFIG_BOOTDELAY=0 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_I2C=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_FAT=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_OF_LIBFDT=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_RSA=y +CONFIG_DM=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 616aebb4e91..c588fdd34f0 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -124,7 +124,18 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. + */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS (0x400 + \ + (CONFIG_U_BOOT_HDR_SIZE / 512) +#else #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#endif /* ifdef CONFIG_SECURE_BOOT */ #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -137,7 +148,18 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x80000 + CONFIG_U_BOOT_HDR_SIZE) +#else #define CONFIG_SYS_MONITOR_LEN 0x80000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif #ifdef CONFIG_QSPI_BOOT -- cgit v1.3.1 From aeb901f2a6c19e399354345ad1acd67420401a10 Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Thu, 21 Jul 2016 18:09:38 +0800 Subject: ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention This patch implements PSCI functions for ls102xa SoC following PSCI v1.0, they are as the list: psci_version, psci_features, psci_cpu_suspend, psci_affinity_info, psci_system_reset, psci_system_off. Tested on LS1021aQDS, LS1021aTWR. Signed-off-by: Wang Dongsheng Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- arch/arm/cpu/armv7/ls102xa/psci.S | 103 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-ls102xa/config.h | 1 + board/freescale/ls1021aqds/Makefile | 1 + board/freescale/ls1021aqds/psci.S | 33 +++++++++ board/freescale/ls1021atwr/Makefile | 1 + board/freescale/ls1021atwr/psci.S | 25 +++++++ include/configs/ls1021aqds.h | 3 + include/configs/ls1021atwr.h | 1 + 8 files changed, 166 insertions(+), 2 deletions(-) create mode 100644 board/freescale/ls1021aqds/psci.S create mode 100644 board/freescale/ls1021atwr/psci.S (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index cba9c1e1aaf..8f386800f6c 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -12,19 +12,72 @@ #include #include +#define RCPM_TWAITSR 0x04C + #define SCFG_CORE0_SFT_RST 0x130 #define SCFG_CORESRENCR 0x204 -#define DCFG_CCSR_BRR 0x0E4 -#define DCFG_CCSR_SCRATCHRW1 0x200 +#define DCFG_CCSR_RSTCR 0x0B0 +#define DCFG_CCSR_RSTCR_RESET_REQ 0x2 +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + +#define PSCI_FN_PSCI_VERSION_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_SUSPEND_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_CPU_ON_FEATURE_MASK 0x0 +#define PSCI_FN_AFFINITY_INFO_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_OFF_FEATURE_MASK 0x0 +#define PSCI_FN_SYSTEM_RESET_FEATURE_MASK 0x0 .pushsection ._secure.text, "ax" .arch_extension sec + .align 5 + #define ONE_MS (GENERIC_TIMER_CLK / 1000) #define RESET_WAIT (30 * ONE_MS) +.globl psci_version +psci_version: + movw r0, #0 + movt r0, #1 + + bx lr + +_ls102x_psci_supported_table: + .word ARM_PSCI_0_2_FN_PSCI_VERSION + .word PSCI_FN_PSCI_VERSION_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_SUSPEND + .word PSCI_FN_CPU_SUSPEND_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_OFF + .word PSCI_FN_CPU_OFF_FEATURE_MASK + .word ARM_PSCI_0_2_FN_CPU_ON + .word PSCI_FN_CPU_ON_FEATURE_MASK + .word ARM_PSCI_0_2_FN_AFFINITY_INFO + .word PSCI_FN_AFFINITY_INFO_FEATURE_MASK + .word ARM_PSCI_0_2_FN_SYSTEM_OFF + .word PSCI_FN_SYSTEM_OFF_FEATURE_MASK + .word ARM_PSCI_0_2_FN_SYSTEM_RESET + .word PSCI_FN_SYSTEM_RESET_FEATURE_MASK + .word 0 + .word ARM_PSCI_RET_NI + +.globl psci_features +psci_features: + adr r2, _ls102x_psci_supported_table +1: ldr r3, [r2] + cmp r3, #0 + beq out_psci_features + cmp r1, r3 + addne r2, r2, #8 + bne 1b + +out_psci_features: + ldr r0, [r2, #4] + bx lr + @ r0: return value ARM_PSCI_RET_SUCCESS or ARM_PSCI_RET_INVAL @ r1: input target CPU ID in MPIDR format, original value in r1 may be dropped @ r4: output validated CPU ID if ARM_PSCI_RET_SUCCESS returns, meaningless for @@ -141,6 +194,52 @@ out_psci_cpu_on: psci_cpu_off: bl psci_cpu_off_common +1: wfi + b 1b + +.globl psci_affinity_info +psci_affinity_info: + push {lr} + + mov r0, #ARM_PSCI_RET_INVAL + + @ Verify Affinity level + cmp r2, #0 + bne out_affinity_info + + bl psci_check_target_cpu_id + cmp r0, #ARM_PSCI_RET_INVAL + beq out_affinity_info + mov r1, r4 + + @ Get RCPM base address + movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) + + mov r0, #PSCI_AFFINITY_LEVEL_ON + + @ Detect target CPU state + ldr r2, [r4, #RCPM_TWAITSR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq out_affinity_info + + mov r0, #PSCI_AFFINITY_LEVEL_OFF + +out_affinity_info: + pop {pc} + +.globl psci_system_reset +psci_system_reset: + @ Get DCFG base address + movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + + mov r2, #DCFG_CCSR_RSTCR_RESET_REQ + rev r2, r2 + str r2, [r1, #DCFG_CCSR_RSTCR] + 1: wfi b 1b diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 67a43117f90..e0b118537ed 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -32,6 +32,7 @@ #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) #define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000) diff --git a/board/freescale/ls1021aqds/Makefile b/board/freescale/ls1021aqds/Makefile index ab0234412cb..f0390c129f8 100644 --- a/board/freescale/ls1021aqds/Makefile +++ b/board/freescale/ls1021aqds/Makefile @@ -8,3 +8,4 @@ obj-y += ls1021aqds.o obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021aqds/psci.S b/board/freescale/ls1021aqds/psci.S new file mode 100644 index 00000000000..598168c7b07 --- /dev/null +++ b/board/freescale/ls1021aqds/psci.S @@ -0,0 +1,33 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: + @ Get QIXIS base address + movw r1, #(QIXIS_BASE & 0xffff) + movt r1, #(QIXIS_BASE >> 16) + + ldrb r2, [r1, #QIXIS_PWR_CTL] + orr r2, r2, #QIXIS_PWR_CTL_POWEROFF + strb r2, [r1, #QIXIS_PWR_CTL] + +1: wfi + b 1b + + .popsection diff --git a/board/freescale/ls1021atwr/Makefile b/board/freescale/ls1021atwr/Makefile index 01296c04b29..5238b158d7c 100644 --- a/board/freescale/ls1021atwr/Makefile +++ b/board/freescale/ls1021atwr/Makefile @@ -6,3 +6,4 @@ obj-y += ls1021atwr.o obj-$(CONFIG_FSL_DCU_FB) += dcu.o +obj-$(CONFIG_ARMV7_PSCI) += psci.o diff --git a/board/freescale/ls1021atwr/psci.S b/board/freescale/ls1021atwr/psci.S new file mode 100644 index 00000000000..bec73568d3c --- /dev/null +++ b/board/freescale/ls1021atwr/psci.S @@ -0,0 +1,25 @@ +/* + * Copyright 2016 NXP Semiconductor. + * Author: Wang Dongsheng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include + +#include +#include + + .pushsection ._secure.text, "ax" + + .arch_extension sec + + .align 5 + +.globl psci_system_off +psci_system_off: +1: wfi + b 1b + + .popsection diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index eb444ebd59e..ba3331f0a47 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,6 +10,7 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS #define CONFIG_SYS_FSL_CLK @@ -280,6 +281,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_PWR_CTL 0x21 +#define QIXIS_PWR_CTL_POWEROFF 0x80 #define QIXIS_RST_CTL_RESET 0x44 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index c588fdd34f0..5b6e0a55ae9 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -10,6 +10,7 @@ #define CONFIG_LS102XA #define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS #define CONFIG_SYS_FSL_CLK -- cgit v1.3.1 From 3288628a8d23681c865e91e65a341d48eb5fed73 Mon Sep 17 00:00:00 2001 From: Hongbo Zhang Date: Thu, 21 Jul 2016 18:09:39 +0800 Subject: ARMv7: PSCI: ls102xa: move secure text section into OCRAM LS1021 offers two secure OCRAM blocks for trustzone. This patch moves all the secure text sections into the OCRAM. Signed-off-by: Wang Dongsheng Signed-off-by: Hongbo Zhang Reviewed-by: York Sun --- arch/arm/include/asm/arch-ls102xa/config.h | 2 +- include/configs/ls1021aqds.h | 2 ++ include/configs/ls1021atwr.h | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index e0b118537ed..d408fe40561 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -10,7 +10,7 @@ #define CONFIG_SYS_CACHELINE_SIZE 64 #define OCRAM_BASE_ADDR 0x10000000 -#define OCRAM_SIZE 0x00020000 +#define OCRAM_SIZE 0x00010000 #define OCRAM_BASE_S_ADDR 0x10010000 #define OCRAM_S_SIZE 0x00010000 diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ba3331f0a47..47180f9ce8b 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -13,6 +13,8 @@ #define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 5b6e0a55ae9..2f19950dffe 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -13,6 +13,8 @@ #define CONFIG_ARMV7_PSCI_1_0 #define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + #define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO -- cgit v1.3.1 From 716d6677cbe96fa21438da6e6d2580a7093c99d9 Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Thu, 21 Jul 2016 18:31:23 +0800 Subject: ARMv8/ls1046a: Cleanup the environment variables Cleanup the variables: "kernel_addr","ramdisk_addr", "ramdisk_size","console". Signed-off-by: Wenbin Song Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index b0d4a8d10ac..a65113070ed 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -245,15 +245,12 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x61100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" + "console=ttyS0,115200\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ "earlycon=uart8250,mmio,0x21c0500" -- cgit v1.3.1 From dbe18f16d852216a45f632f0d3cf41f12b55d1ec Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Thu, 21 Jul 2016 18:55:16 +0800 Subject: armv8/ls1043a: Add MTD partition scheme Add and share the the MTD partition scheme with kernel by default bootargs. And add the "mtdparts" env. Signed-off-by: Wenbin Song Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index a65113070ed..0ad5261c567 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -241,6 +241,21 @@ #define CONFIG_HWCONFIG #define HWCONFIG_BUFFER_SIZE 128 +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#else +#define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \ + "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \ + "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \ + "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \ + "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \ + "40m(nor_bank4_fit);7e800000.flash:" \ + "1m(nand_uboot),1m(nand_uboot_env)," \ + "20m(nand_fit);spi0.0:1m(uboot)," \ + "5m(kernel),1m(dtb),9m(file_system)" +#endif + /* Initial environment variables */ #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ @@ -250,10 +265,13 @@ "kernel_start=0x61100000\0" \ "kernel_load=0xa0000000\0" \ "kernel_size=0x2800000\0" \ - "console=ttyS0,115200\0" + "console=ttyS0,115200\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ - "earlycon=uart8250,mmio,0x21c0500" + "earlycon=uart8250,mmio,0x21c0500 " \ + MTDPARTS_DEFAULT + #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ "e0000 f00000 && bootm $kernel_load" -- cgit v1.3.1