From 44b5c40be3dc4f063ec8bec1f3a71b1160e3788c Mon Sep 17 00:00:00 2001 From: Nicolas Ferre Date: Thu, 8 Aug 2019 07:48:26 +0000 Subject: board: atmel: add sama5d27_wlsom1_ek board Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP. Signed-off-by: Nicolas Ferre [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev --- include/configs/sama5d27_wlsom1_ek.h | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 include/configs/sama5d27_wlsom1_ek.h (limited to 'include') diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h new file mode 100644 index 00000000000..cc41560c1fd --- /dev/null +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D27 WLSOM1 EK Board. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif + +#endif -- cgit v1.3.1 From c721c22a031f59729bd3d53fd52739c87c561368 Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Thu, 8 Aug 2019 07:48:35 +0000 Subject: board: atmel: sama5d2_wlsom1_ek: add SPL support Add support for SPL for this board: DRAM initialization, PMC initialization, MMC boot. Signed-off-by: Eugen Hristev --- arch/arm/mach-at91/Kconfig | 1 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 147 +++++++++++++++++++++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 25 +++- include/configs/sama5d27_wlsom1_ek.h | 16 ++- 4 files changed, 185 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index ce0b1b4b33f..14343280793 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -189,6 +189,7 @@ config TARGET_SAMA5D27_WLSOM1_EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A + select SUPPORT_SPL help The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package), a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 483ec829001..3663ae4a7a8 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -78,3 +78,150 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ZQ_SHORT | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3); + + /* + * The AD220032D average time between REFRESH commands (Trefi): 3.9us + * 3.9us * 164MHz = 639.6 = 0x27F. + */ + ddrc->rtr = 0x27f; + /* Enable Adjust Refresh Rate */ + ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); + + ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15); + + /* + * According to the sama5d2 datasheet and the following values: + * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s + * Warning: note that the values T driftrate and V driftrate are dependent on + * the application environment. + * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s + * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize + * this timer to 0xFFFE. + */ + ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE); + + /* + * MR4 Read interval is dependent on the application environment. + * Here, we want to maximize this value as temperature is supposed + * to vary slowly in the application chosen. + * If Trefi is 3.9us, we have: + * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads. + */ + ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + ddrc_conf(&ddrc_config); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 6b11fcbc2b8..d7329a2a592 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -2,12 +2,20 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 -CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y @@ -15,9 +23,13 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DISPLAY_PRINT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -31,9 +43,15 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y CONFIG_AT91_H32MX=y @@ -56,6 +74,7 @@ CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ATMEL=y @@ -64,9 +83,11 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_W1=y CONFIG_W1_GPIO=y CONFIG_W1_EEPROM=y CONFIG_W1_EEPROM_DS24XXX=y CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index cc41560c1fd..6bcbc060208 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,16 +19,28 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000 +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -/* NAND flash */ -#undef CONFIG_CMD_NAND +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif #endif -- cgit v1.3.1 From 2a09eb6340e055be03008b75a7ca322a39482d3e Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Mon, 26 Aug 2019 06:47:07 +0000 Subject: board: atmel: sama5d2_wlsom1_ek: add qspi support and qspi boot config Add support for qspi memory on board. Created boot support for QSPI for both u-boot proper and SPL. Signed-off-by: Eugen Hristev --- board/atmel/sama5d27_wlsom1_ek/MAINTAINERS | 1 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 17 +++ configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 115 +++++++++++++++++++++ include/configs/sama5d27_wlsom1_ek.h | 4 + 4 files changed, 137 insertions(+) create mode 100644 configs/sama5d27_wlsom1_ek_qspiflash_defconfig (limited to 'include') diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS index 59671ac5401..ff68cf01a34 100644 --- a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/atmel/sama5d27_wlsom1_ek/ F: include/configs/sama5d27_wlsom1_ek.h F: configs/sama5d27_wlsom1_ek_mmc_defconfig +F: configs/sama5d27_wlsom1_ek_qspiflash_defconfig diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 3663ae4a7a8..19300483b5c 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -97,11 +97,28 @@ void spl_mmc_init(void) } #endif +#ifdef CONFIG_QSPI_BOOT +void spl_qspi_init(void) +{ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 5, 0); /* SCK */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 6, 0); /* CS */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 7, 0); /* IO0 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 8, 0); /* IO1 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 9, 0); /* IO2 */ + atmel_pio4_set_d_periph(AT91_PIO_PORTB, 10, 0); /* IO3 */ + + at91_periph_clk_enable(ATMEL_ID_QSPI1); +} +#endif + void spl_board_init(void) { #ifdef CONFIG_SD_BOOT spl_mmc_init(); #endif +#ifdef CONFIG_QSPI_BOOT + spl_qspi_init(); +#endif } void spl_display_print(void) diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig new file mode 100644 index 00000000000..56cca3ec418 --- /dev/null +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f00000 +CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_QSPI_BOOT=y +CONFIG_SPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DISPLAY_PRINT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=2 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=50000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=50000000 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 6bcbc060208..250eb7392e1 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -43,4 +43,8 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 +#endif + #endif -- cgit v1.3.1 From 37bd051e924aebefbdd9ef1b9e12256d6fcefcfe Mon Sep 17 00:00:00 2001 From: Eugen Hristev Date: Wed, 11 Sep 2019 13:02:28 +0000 Subject: board: atmel: sama5d27_wlsom1_ek: fix SPL OFFS on SPI Fixes redefinition of CONFIG_SYS_SPI_U_BOOT_OFFS This is now a Kconfig Fixes: e40a9ba6d2d5 ("board: atmel: sama5d2_wlsom1_ek: add qspi support and qspi boot config") Signed-off-by: Eugen Hristev --- configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 3 ++- include/configs/sama5d27_wlsom1_ek.h | 4 ---- 2 files changed, 2 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index ec05af13adc..82568e286d8 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -16,6 +16,7 @@ CONFIG_ENV_SECT_SIZE=0x1000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" @@ -26,12 +27,12 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0x200000 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y CONFIG_SPL_AT91_MCK_BYPASS=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 250eb7392e1..6bcbc060208 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -43,8 +43,4 @@ #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000 -#endif - #endif -- cgit v1.3.1 From 51422665de7c57a5e96a0c7b4fbc1a14804fa4b8 Mon Sep 17 00:00:00 2001 From: Sandeep Sheriker Mallikarjun Date: Fri, 27 Sep 2019 13:08:52 +0000 Subject: board: atmel: Add sam9x60ek board Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC. Signed-off-by: Sandeep Sheriker Mallikarjun [tudor.ambarus@microchip.com: - fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] - drop SPL related macros - drop memtest macros - drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros - drop inclusion of asm/arch/at91sam9_smc.h] Signed-off-by: Tudor Ambarus --- arch/arm/mach-at91/Kconfig | 7 +++++ board/atmel/sam9x60ek/Kconfig | 12 ++++++++ board/atmel/sam9x60ek/MAINTAINERS | 7 +++++ board/atmel/sam9x60ek/Makefile | 7 +++++ board/atmel/sam9x60ek/sam9x60ek.c | 59 ++++++++++++++++++++++++++++++++++++++ include/configs/sam9x60ek.h | 60 +++++++++++++++++++++++++++++++++++++++ 6 files changed, 152 insertions(+) create mode 100644 board/atmel/sam9x60ek/Kconfig create mode 100644 board/atmel/sam9x60ek/MAINTAINERS create mode 100644 board/atmel/sam9x60ek/Makefile create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c create mode 100644 include/configs/sam9x60ek.h (limited to 'include') diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 3cf13042b7b..85524004f9e 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -160,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM select BOARD_LATE_INIT select SUPPORT_SPL +config TARGET_SAM9X60EK + bool "SAM9X60-EK board" + select SAM9X60 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + config TARGET_SAMA5D2_PTC_EK bool "SAMA5D2 PTC EK board" select BOARD_EARLY_INIT_F @@ -316,6 +322,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig" source "board/atmel/at91sam9n12ek/Kconfig" source "board/atmel/at91sam9rlek/Kconfig" source "board/atmel/at91sam9x5ek/Kconfig" +source "board/atmel/sam9x60ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig new file mode 100644 index 00000000000..32fae2108e6 --- /dev/null +++ b/board/atmel/sam9x60ek/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SAM9X60EK + +config SYS_BOARD + default "sam9x60ek" + +config SYS_VENDOR + default "atmel" + +config SYS_CONFIG_NAME + default "sam9x60ek" + +endif diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS new file mode 100644 index 00000000000..e8c1346863a --- /dev/null +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -0,0 +1,7 @@ +SAM9X60EK BOARD +M: Sandeep Sheriker M +M: Eugen Hristev +S: Maintained +F: board/atmel/sam9x60ek/ +F: include/configs/sam9x60ek.h +F: configs/sam9x60ek_mmc_defconfig diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile new file mode 100644 index 00000000000..12a406a3bb5 --- /dev/null +++ b/board/atmel/sam9x60ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries +# +# Author: Sandeep Sheriker M + +obj-y += sam9x60ek.o diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c new file mode 100644 index 00000000000..62938741ddd --- /dev/null +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void at91_prepare_cpu_var(void); + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ + at91_prepare_cpu_var(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +void board_debug_uart_init(void) +{ + at91_seriald_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h new file mode 100644 index 00000000000..b778bd8e83e --- /dev/null +++ b/include/configs/sam9x60ek.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuation settings for the SAM9X60EK board. + * + * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries + * + * Author: Sandeep Sheriker M + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID 0 /* ignored in arm */ + +/* general purpose I/O */ +#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* + * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) + * NB: in this case, USB 1.1 devices won't be recognized. + */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#ifdef CONFIG_SD_BOOT +/* bootstrap + u-boot + env + linux in sd card */ +#define CONFIG_BOOTCOMMAND \ + "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ + "fatload mmc 0:1 0x22000000 zImage;" \ + "bootz 0x22000000 - 0x21000000" +#endif + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) + +#endif -- cgit v1.3.1 From 8ed15e4a3a0a1cfce08e97904887f7bd6c2fb27b Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 27 Sep 2019 13:09:07 +0000 Subject: board: sam9x60ek: Add NAND flash support - EBI Chip Select Register is now in SFR, - the pins are set to default values, - timings are matching MT29F4G08BABWP's nand flash requirements. Signed-off-by: Tudor Ambarus --- board/atmel/sam9x60ek/sam9x60ek.c | 61 +++++++++++++++++++++++++++++++++++++++ include/configs/sam9x60ek.h | 28 ++++++++++++++++++ 2 files changed, 89 insertions(+) (limited to 'include') diff --git a/board/atmel/sam9x60ek/sam9x60ek.c b/board/atmel/sam9x60ek/sam9x60ek.c index 62938741ddd..e352afc67ed 100644 --- a/board/atmel/sam9x60ek/sam9x60ek.c +++ b/board/atmel/sam9x60ek/sam9x60ek.c @@ -7,8 +7,10 @@ #include #include +#include #include #include +#include #include #include #include @@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR; void at91_prepare_cpu_var(void); +#ifdef CONFIG_CMD_NAND +static void sam9x60ek_nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + unsigned int csa; + + at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */ + at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */ + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1); + at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1); + + at91_periph_clk_enable(ATMEL_ID_PIOD); + + /* Enable CS3 */ + csa = readl(&sfr->ebicsa); + csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16; + + /* Configure IO drive */ + csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60; + + writel(csa, &sfr->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) | + AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_MODE_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_MODE_DBW_8 | +#endif + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15), + &smc->cs[3].mode); +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -48,6 +106,9 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; +#ifdef CONFIG_CMD_NAND + sam9x60ek_nand_hw_init(); +#endif return 0; } diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index b778bd8e83e..dbcbce3a2b8 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -42,6 +42,26 @@ #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_MASK_ALE BIT(21) +#define CONFIG_SYS_NAND_MASK_CLE BIT(22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 +#define CONFIG_SYS_NAND_ONFI_DETECTION + +#define CONFIG_MTD_DEVICE +#endif + +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#define CONFIG_PMECC_CAP 8 +#define CONFIG_PMECC_SECTOR_SIZE 512 + #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ #ifdef CONFIG_SD_BOOT @@ -50,6 +70,14 @@ "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ "fatload mmc 0:1 0x22000000 zImage;" \ "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_NAND_BOOT) +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_OFFSET_REDUND 0x100000 +#define CONFIG_BOOTCOMMAND "nand read " \ + "0x22000000 0x200000 0x600000; " \ + "nand read 0x21000000 0x180000 0x20000; " \ + "bootz 0x22000000 - 0x21000000" #endif /* -- cgit v1.3.1 From 8c04ea7cada44f393c435001bc466a82fde04fba Mon Sep 17 00:00:00 2001 From: Tudor Ambarus Date: Fri, 27 Sep 2019 13:09:15 +0000 Subject: configs: sam9x60ek: Add QSPI_BOOT defines Cope with the offsets defined at: https://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections/demo_nandflash_map_lnx4sam6x.png The environment starts at 0x140000 and it's of size 0x20000. The device tree starts at 0x180000 and it's of size 0x80000. The zImage starts at 0x200000 and it's of size 0x600000. Signed-off-by: Tudor Ambarus --- include/configs/sam9x60ek.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index dbcbce3a2b8..5f89ae4a511 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -78,6 +78,13 @@ "0x22000000 0x200000 0x600000; " \ "nand read 0x21000000 0x180000 0x20000; " \ "bootz 0x22000000 - 0x21000000" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x21000000 0x180000 0x80000; " \ + "sf read 0x22000000 0x200000 0x600000; " \ + "bootz 0x22000000 - 0x21000000" #endif /* -- cgit v1.3.1