From 3336e85b6a303663723436ca15dc5ea5ed5358e0 Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 7 May 2026 20:37:50 +0200 Subject: rockchip: Switch rk3128 boards to upstream devicetree Switch rk3128 boards to upstream devicetree. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- include/dt-bindings/clock/rk3128-cru.h | 273 --------------------------------- 1 file changed, 273 deletions(-) delete mode 100644 include/dt-bindings/clock/rk3128-cru.h (limited to 'include') diff --git a/include/dt-bindings/clock/rk3128-cru.h b/include/dt-bindings/clock/rk3128-cru.h deleted file mode 100644 index 6a47825dac5..00000000000 --- a/include/dt-bindings/clock/rk3128-cru.h +++ /dev/null @@ -1,273 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2017 Rockchip Electronics Co. Ltd. - * Author: Elaine - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 -#define PLL_GPLL_DIV2 6 -#define PLL_GPLL_DIV3 7 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_SARADC 91 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_HEVC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_DDRC 144 -#define SCLK_PVTM_FUNC 145 -#define SCLK_PVTM_CORE 146 -#define SCLK_PVTM_GPU 147 -#define SCLK_MIPI_24M 148 -#define SCLK_PVTM 149 -#define SCLK_CIF_SRC 150 -#define SCLK_CIF_OUT_SRC 151 -#define SCLK_CIF_OUT 152 -#define SCLK_SFC 153 -#define SCLK_USB480M 154 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_EBC 191 - -/* aclk gates */ -#define ACLK_VIO0 192 -#define ACLK_VIO1 193 -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VEPU 196 -#define ACLK_VDPU 197 -#define ACLK_CIF 198 -#define ACLK_IEP 199 -#define ACLK_LCDC0 204 -#define ACLK_RGA 205 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_SARADC 318 -#define PCLK_WDT 319 -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_MIPI 325 -#define PCLK_EFUSE 326 -#define PCLK_HDMI 327 -#define PCLK_ACODEC 328 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_GMAC 367 -#define PCLK_PMU_PRE 368 -#define PCLK_SIM_CARD 369 - -/* hclk gates */ -#define HCLK_SPDIF 440 -#define HCLK_GPS 441 -#define HCLK_USBHOST 442 -#define HCLK_I2S_8CH 443 -#define HCLK_I2S_2CH 444 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VEPU 461 -#define HCLK_VDPU 462 -#define HCLK_LCDC0 463 -#define HCLK_EBC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_CIF 470 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_CRYPTO 476 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_STRC_SYS_A 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_AHB2APBSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_PERI_NIU 23 -#define SRST_I2S_2CH 24 -#define SRST_I2S_8CH 25 -#define SRST_GPU_PVTM 26 -#define SRST_FUNC_PVTM 27 -#define SRST_CORE_PVTM 29 -#define SRST_EFUSE_P 30 -#define SRST_ACODEC_P 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_MIPIPHY_P 36 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 -#define SRST_SFC 47 - -#define SRST_PWM 48 -#define SRST_DAP_PO 50 -#define SRST_DAP 51 -#define SRST_DAP_SYS 52 -#define SRST_CRYPTO 53 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_SYS_A 57 -#define SRST_PERIPH_SYS_H 58 -#define SRST_PERIPH_SYS_P 59 -#define SRST_SMART_CARD 60 -#define SRST_CPU_PERI 61 -#define SRST_EMEM_PERI 62 -#define SRST_USB_PERI 63 - -#define SRST_DMA 64 -#define SRST_GPS 67 -#define SRST_NANDC 68 -#define SRST_USBOTG0 69 -#define SRST_OTGC0 71 -#define SRST_USBOTG1 72 -#define SRST_OTGC1 74 -#define SRST_DDRMSCH 79 - -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_WDT 86 -#define SRST_SARADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_TSP 92 -#define SRST_TSP_CLKIN 93 -#define SRST_HOST0_ECHI 94 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_VIO0_A 98 -#define SRST_VIO_BUS_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_USBPOR 105 -#define SRST_IEP_A 106 -#define SRST_IEP_H 107 -#define SRST_RGA_A 108 -#define SRST_RGA_H 109 -#define SRST_CIF0 110 -#define SRST_PMU 111 - -#define SRST_VCODEC_A 112 -#define SRST_VCODEC_H 113 -#define SRST_VIO1_A 114 -#define SRST_HEVC_CORE 115 -#define SRST_VCODEC_NIU_A 116 -#define SRST_PMU_NIU_P 117 -#define SRST_LCDC0_S 119 -#define SRST_GPU 120 -#define SRST_GPU_NIU_A 122 -#define SRST_EBC_A 123 -#define SRST_EBC_H 124 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_VIO_MIPI_DSI 137 - -#endif -- cgit v1.3.1 From 924f87b995fa6b451656df17f3b6be20a3cf9c4e Mon Sep 17 00:00:00 2001 From: Johan Jonker Date: Thu, 7 May 2026 20:38:03 +0200 Subject: rockchip: Switch rk3229 boards to upstream devicetree Switch rk3229 boards to upstream devicetree. Signed-off-by: Johan Jonker Reviewed-by: Kever Yang --- arch/arm/dts/Makefile | 3 - arch/arm/dts/rk3229-evb.dts | 256 ------- arch/arm/dts/rk3229.dtsi | 52 -- arch/arm/dts/rk322x.dtsi | 1293 -------------------------------- arch/arm/mach-rockchip/Kconfig | 1 + board/rockchip/evb_rk3229/MAINTAINERS | 1 - configs/evb-rk3229_defconfig | 4 +- include/dt-bindings/clock/rk3228-cru.h | 287 ------- 8 files changed, 3 insertions(+), 1894 deletions(-) delete mode 100644 arch/arm/dts/rk3229-evb.dts delete mode 100644 arch/arm/dts/rk3229.dtsi delete mode 100644 arch/arm/dts/rk322x.dtsi delete mode 100644 include/dt-bindings/clock/rk3228-cru.h (limited to 'include') diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 69824bf59b7..2b65cd9105c 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -45,9 +45,6 @@ dtb-$(CONFIG_MACH_S900) += \ dtb-$(CONFIG_MACH_S700) += \ s700-cubieboard7.dtb -dtb-$(CONFIG_ROCKCHIP_RK322X) += \ - rk3229-evb.dtb - dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-sheep.dtb \ rk3368-geekbox.dtb \ diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts deleted file mode 100644 index 797476e8bef..00000000000 --- a/arch/arm/dts/rk3229-evb.dts +++ /dev/null @@ -1,256 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -/dts-v1/; - -#include -#include "rk3229.dtsi" - -/ { - model = "Rockchip RK3229 Evaluation board"; - compatible = "rockchip,rk3229-evb", "rockchip,rk3229"; - - aliases { - mmc0 = &emmc; - }; - - memory@60000000 { - device_type = "memory"; - reg = <0x60000000 0x40000000>; - }; - - dc_12v: dc-12v-regulator { - compatible = "regulator-fixed"; - regulator-name = "dc_12v"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - - ext_gmac: ext_gmac { - compatible = "fixed-clock"; - clock-frequency = <125000000>; - clock-output-names = "ext_gmac"; - #clock-cells = <0>; - }; - - vcc_host: vcc-host-regulator { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&host_vbus_drv>; - regulator-name = "vcc_host"; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vcc_sys>; - }; - - vcc_phy: vcc-phy-regulator { - compatible = "regulator-fixed"; - enable-active-high; - regulator-name = "vcc_phy"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - regulator-boot-on; - vin-supply = <&vccio_1v8>; - }; - - vcc_sys: vcc-sys-regulator { - compatible = "regulator-fixed"; - regulator-name = "vcc_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&dc_12v>; - }; - - vccio_1v8: vccio-1v8-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vccio_3v3: vccio-3v3-regulator { - compatible = "regulator-fixed"; - regulator-name = "vccio_3v3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vcc_sys>; - }; - - vdd_arm: vdd-arm-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm1 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_arm"; - regulator-min-microvolt = <950000>; - regulator-max-microvolt = <1400000>; - regulator-always-on; - regulator-boot-on; - }; - - vdd_log: vdd-log-regulator { - compatible = "pwm-regulator"; - pwms = <&pwm2 0 25000 1>; - pwm-supply = <&vcc_sys>; - regulator-name = "vdd_log"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - regulator-boot-on; - }; - - gpio_keys { - compatible = "gpio-keys"; - autorepeat; - pinctrl-names = "default"; - pinctrl-0 = <&pwr_key>; - - power_key: power-key { - label = "GPIO Key Power"; - gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - }; -}; - -&cpu0 { - cpu-supply = <&vdd_arm>; -}; - -&cpu1 { - cpu-supply = <&vdd_arm>; -}; - -&cpu2 { - cpu-supply = <&vdd_arm>; -}; - -&cpu3 { - cpu-supply = <&vdd_arm>; -}; - -&emmc { - cap-mmc-highspeed; - non-removable; - status = "okay"; -}; - -&gmac { - assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>; - assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>; - clock_in_out = "input"; - phy-supply = <&vcc_phy>; - phy-mode = "rgmii"; - pinctrl-names = "default"; - pinctrl-0 = <&rgmii_pins>; - snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 10000 1000000>; - tx_delay = <0x30>; - rx_delay = <0x10>; - status = "okay"; -}; - -&io_domains { - status = "okay"; - - vccio1-supply = <&vccio_3v3>; - vccio2-supply = <&vccio_1v8>; - vccio4-supply = <&vccio_3v3>; -}; - -&pinctrl { - keys { - pwr_key: pwr-key { - rockchip,pins = <3 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; - }; - }; - - usb { - host_vbus_drv: host-vbus-drv { - rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; -}; - -&pwm1 { - status = "okay"; -}; - -&pwm2 { - status = "okay"; -}; - -&tsadc { - rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ - status = "okay"; -}; - -&uart2 { - status = "okay"; -}; - -&u2phy0 { - status = "okay"; - - u2phy0_otg: otg-port { - status = "okay"; - }; - - u2phy0_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&u2phy1 { - status = "okay"; - - u2phy1_otg: otg-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; - - u2phy1_host: host-port { - phy-supply = <&vcc_host>; - status = "okay"; - }; -}; - -&usb_host0_ehci { - status = "okay"; -}; - -&usb_host0_ohci { - status = "okay"; -}; - -&usb_host1_ehci { - status = "okay"; -}; - -&usb_host1_ohci { - status = "okay"; -}; - -&usb_host2_ehci { - status = "okay"; -}; - -&usb_host2_ohci { - status = "okay"; -}; - -&usb_otg { - status = "okay"; -}; diff --git a/arch/arm/dts/rk3229.dtsi b/arch/arm/dts/rk3229.dtsi deleted file mode 100644 index c340fb30e77..00000000000 --- a/arch/arm/dts/rk3229.dtsi +++ /dev/null @@ -1,52 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd - */ - -#include "rk322x.dtsi" - -/ { - compatible = "rockchip,rk3229"; - - /delete-node/ opp-table0; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - opp-1296000000 { - opp-hz = /bits/ 64 <1296000000>; - opp-microvolt = <1325000>; - }; - opp-1392000000 { - opp-hz = /bits/ 64 <1392000000>; - opp-microvolt = <1375000>; - }; - opp-1464000000 { - opp-hz = /bits/ 64 <1464000000>; - opp-microvolt = <1400000>; - }; - }; -}; diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi deleted file mode 100644 index 8eed9e3a92e..00000000000 --- a/arch/arm/dts/rk322x.dtsi +++ /dev/null @@ -1,1293 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - -#include -#include -#include -#include -#include -#include -#include - -/ { - #address-cells = <1>; - #size-cells = <1>; - - interrupt-parent = <&gic>; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - serial2 = &uart2; - spi0 = &spi0; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu0: cpu@f00 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf00>; - resets = <&cru SRST_CORE0>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - clock-latency = <40000>; - clocks = <&cru ARMCLK>; - enable-method = "psci"; - }; - - cpu1: cpu@f01 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf01>; - resets = <&cru SRST_CORE1>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu2: cpu@f02 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf02>; - resets = <&cru SRST_CORE2>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - - cpu3: cpu@f03 { - device_type = "cpu"; - compatible = "arm,cortex-a7"; - reg = <0xf03>; - resets = <&cru SRST_CORE3>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - enable-method = "psci"; - }; - }; - - cpu0_opp_table: opp-table-0 { - compatible = "operating-points-v2"; - opp-shared; - - opp-408000000 { - opp-hz = /bits/ 64 <408000000>; - opp-microvolt = <950000>; - clock-latency-ns = <40000>; - opp-suspend; - }; - opp-600000000 { - opp-hz = /bits/ 64 <600000000>; - opp-microvolt = <975000>; - }; - opp-816000000 { - opp-hz = /bits/ 64 <816000000>; - opp-microvolt = <1000000>; - }; - opp-1008000000 { - opp-hz = /bits/ 64 <1008000000>; - opp-microvolt = <1175000>; - }; - opp-1200000000 { - opp-hz = /bits/ 64 <1200000000>; - opp-microvolt = <1275000>; - }; - }; - - arm-pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = , - , - , - ; - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; - }; - - psci { - compatible = "arm,psci-1.0", "arm,psci-0.2"; - method = "smc"; - }; - - timer { - compatible = "arm,armv7-timer"; - arm,cpu-registers-not-fw-configured; - interrupts = , - , - , - ; - clock-frequency = <24000000>; - }; - - xin24m: oscillator { - compatible = "fixed-clock"; - clock-frequency = <24000000>; - clock-output-names = "xin24m"; - #clock-cells = <0>; - }; - - display_subsystem: display-subsystem { - compatible = "rockchip,display-subsystem"; - ports = <&vop_out>; - }; - - i2s1: i2s1@100b0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100b0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>; - dmas = <&pdma 14>, <&pdma 15>; - dma-names = "tx", "rx"; - pinctrl-names = "default"; - pinctrl-0 = <&i2s1_bus>; - status = "disabled"; - }; - - i2s0: i2s0@100c0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100c0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>; - dmas = <&pdma 11>, <&pdma 12>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - spdif: spdif@100d0000 { - compatible = "rockchip,rk3228-spdif"; - reg = <0x100d0000 0x1000>; - interrupts = ; - clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>; - clock-names = "mclk", "hclk"; - dmas = <&pdma 10>; - dma-names = "tx"; - pinctrl-names = "default"; - pinctrl-0 = <&spdif_tx>; - status = "disabled"; - }; - - i2s2: i2s2@100e0000 { - compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s"; - reg = <0x100e0000 0x4000>; - interrupts = ; - clock-names = "i2s_clk", "i2s_hclk"; - clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>; - dmas = <&pdma 0>, <&pdma 1>; - dma-names = "tx", "rx"; - status = "disabled"; - }; - - grf: syscon@11000000 { - compatible = "rockchip,rk3228-grf", "syscon", "simple-mfd"; - reg = <0x11000000 0x1000>; - #address-cells = <1>; - #size-cells = <1>; - - io_domains: io-domains { - compatible = "rockchip,rk3228-io-voltage-domain"; - status = "disabled"; - }; - - power: power-controller { - compatible = "rockchip,rk3228-power-controller"; - #power-domain-cells = <1>; - #address-cells = <1>; - #size-cells = <0>; - - power-domain@RK3228_PD_VIO { - reg = ; - clocks = <&cru ACLK_HDCP>, - <&cru SCLK_HDCP>, - <&cru ACLK_IEP>, - <&cru HCLK_IEP>, - <&cru ACLK_RGA>, - <&cru HCLK_RGA>, - <&cru SCLK_RGA>; - pm_qos = <&qos_hdcp>, - <&qos_iep>, - <&qos_rga_r>, - <&qos_rga_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VOP { - reg = ; - clocks =<&cru ACLK_VOP>, - <&cru DCLK_VOP>, - <&cru HCLK_VOP>; - pm_qos = <&qos_vop>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_VPU { - reg = ; - clocks = <&cru ACLK_VPU>, - <&cru HCLK_VPU>; - pm_qos = <&qos_vpu>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_RKVDEC { - reg = ; - clocks = <&cru ACLK_RKVDEC>, - <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, - <&cru SCLK_VDEC_CORE>; - pm_qos = <&qos_rkvdec_r>, - <&qos_rkvdec_w>; - #power-domain-cells = <0>; - }; - - power-domain@RK3228_PD_GPU { - reg = ; - clocks = <&cru ACLK_GPU>; - pm_qos = <&qos_gpu>; - #power-domain-cells = <0>; - }; - }; - - u2phy0: usb2phy@760 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0760 0x0c>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy0"; - #clock-cells = <0>; - status = "disabled"; - - u2phy0_otg: otg-port { - interrupts = , - , - ; - interrupt-names = "otg-bvalid", "otg-id", - "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy0_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - - u2phy1: usb2phy@800 { - compatible = "rockchip,rk3228-usb2phy"; - reg = <0x0800 0x0c>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - clock-output-names = "usb480m_phy1"; - #clock-cells = <0>; - status = "disabled"; - - u2phy1_otg: otg-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - - u2phy1_host: host-port { - interrupts = ; - interrupt-names = "linestate"; - #phy-cells = <0>; - status = "disabled"; - }; - }; - }; - - uart0: serial@11010000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11010000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@11020000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11020000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@11030000 { - compatible = "snps,dw-apb-uart"; - reg = <0x11030000 0x100>; - interrupts = ; - clock-frequency = <24000000>; - clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; - clock-names = "baudclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_xfer>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - efuse: efuse@11040000 { - compatible = "rockchip,rk3228-efuse"; - reg = <0x11040000 0x20>; - clocks = <&cru PCLK_EFUSE_256>; - clock-names = "pclk_efuse"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - efuse_id: id@7 { - reg = <0x7 0x10>; - }; - cpu_leakage: cpu_leakage@17 { - reg = <0x17 0x1>; - }; - }; - - i2c0: i2c@11050000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11050000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C0>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c0_xfer>; - status = "disabled"; - }; - - i2c1: i2c@11060000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11060000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C1>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c1_xfer>; - status = "disabled"; - }; - - i2c2: i2c@11070000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11070000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C2>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_xfer>; - status = "disabled"; - }; - - i2c3: i2c@11080000 { - compatible = "rockchip,rk3228-i2c"; - reg = <0x11080000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clock-names = "i2c"; - clocks = <&cru PCLK_I2C3>; - pinctrl-names = "default"; - pinctrl-0 = <&i2c3_xfer>; - status = "disabled"; - }; - - spi0: spi@11090000 { - compatible = "rockchip,rk3228-spi"; - reg = <0x11090000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; - clock-names = "spiclk", "apb_pclk"; - pinctrl-names = "default"; - pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>; - status = "disabled"; - }; - - wdt: watchdog@110a0000 { - compatible = "rockchip,rk3228-wdt", "snps,dw-wdt"; - reg = <0x110a0000 0x100>; - interrupts = ; - clocks = <&cru PCLK_CPU>; - status = "disabled"; - }; - - pwm0: pwm@110b0000 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0000 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm0_pin>; - status = "disabled"; - }; - - pwm1: pwm@110b0010 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0010 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm1_pin>; - status = "disabled"; - }; - - pwm2: pwm@110b0020 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0020 0x10>; - #pwm-cells = <3>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm2_pin>; - status = "disabled"; - }; - - pwm3: pwm@110b0030 { - compatible = "rockchip,rk3288-pwm"; - reg = <0x110b0030 0x10>; - #pwm-cells = <2>; - clocks = <&cru PCLK_PWM>; - pinctrl-names = "default"; - pinctrl-0 = <&pwm3_pin>; - status = "disabled"; - }; - - timer: timer@110c0000 { - compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer"; - reg = <0x110c0000 0x20>; - interrupts = ; - clocks = <&cru PCLK_TIMER>, <&xin24m>; - clock-names = "pclk", "timer"; - }; - - cru: clock-controller@110e0000 { - compatible = "rockchip,rk3228-cru"; - reg = <0x110e0000 0x1000>; - rockchip,grf = <&grf>; - #clock-cells = <1>; - #reset-cells = <1>; - assigned-clocks = - <&cru PLL_GPLL>, <&cru ARMCLK>, - <&cru PLL_CPLL>, <&cru ACLK_PERI>, - <&cru HCLK_PERI>, <&cru PCLK_PERI>, - <&cru ACLK_CPU>, <&cru HCLK_CPU>, - <&cru PCLK_CPU>; - assigned-clock-rates = - <594000000>, <816000000>, - <500000000>, <150000000>, - <150000000>, <75000000>, - <150000000>, <150000000>, - <75000000>; - }; - - pdma: pdma@110f0000 { - compatible = "arm,pl330", "arm,primecell"; - reg = <0x110f0000 0x4000>; - interrupts = , - ; - #dma-cells = <1>; - arm,pl330-periph-burst; - clocks = <&cru ACLK_DMAC>; - clock-names = "apb_pclk"; - }; - - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay-passive = <100>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&tsadc 0>; - - trips { - cpu_alert0: cpu_alert0 { - temperature = <70000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_alert1: cpu_alert1 { - temperature = <75000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "passive"; - }; - cpu_crit: cpu_crit { - temperature = <90000>; /* millicelsius */ - hysteresis = <2000>; /* millicelsius */ - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT 6>, - <&cpu1 THERMAL_NO_LIMIT 6>, - <&cpu2 THERMAL_NO_LIMIT 6>, - <&cpu3 THERMAL_NO_LIMIT 6>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = - <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - }; - - tsadc: tsadc@11150000 { - compatible = "rockchip,rk3228-tsadc"; - reg = <0x11150000 0x100>; - interrupts = ; - clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; - clock-names = "tsadc", "apb_pclk"; - assigned-clocks = <&cru SCLK_TSADC>; - assigned-clock-rates = <32768>; - resets = <&cru SRST_TSADC>; - reset-names = "tsadc-apb"; - pinctrl-names = "init", "default", "sleep"; - pinctrl-0 = <&otp_pin>; - pinctrl-1 = <&otp_out>; - pinctrl-2 = <&otp_pin>; - #thermal-sensor-cells = <1>; - rockchip,hw-tshut-temp = <95000>; - status = "disabled"; - }; - - hdmi_phy: hdmi-phy@12030000 { - compatible = "rockchip,rk3228-hdmi-phy"; - reg = <0x12030000 0x10000>; - clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMI_PHY>; - clock-names = "sysclk", "refoclk", "refpclk"; - #clock-cells = <0>; - clock-output-names = "hdmiphy_phy"; - #phy-cells = <0>; - status = "disabled"; - }; - - gpu: gpu@20000000 { - compatible = "rockchip,rk3228-mali", "arm,mali-400"; - reg = <0x20000000 0x10000>; - interrupts = , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1"; - clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>; - clock-names = "bus", "core"; - power-domains = <&power RK3228_PD_GPU>; - resets = <&cru SRST_GPU_A>; - status = "disabled"; - }; - - vpu: video-codec@20020000 { - compatible = "rockchip,rk3228-vpu", "rockchip,rk3399-vpu"; - reg = <0x20020000 0x800>; - interrupts = , - ; - interrupt-names = "vepu", "vdpu"; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "hclk"; - iommus = <&vpu_mmu>; - power-domains = <&power RK3228_PD_VPU>; - }; - - vpu_mmu: iommu@20020800 { - compatible = "rockchip,iommu"; - reg = <0x20020800 0x100>; - interrupts = ; - clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VPU>; - #iommu-cells = <0>; - }; - - vdec: video-codec@20030000 { - compatible = "rockchip,rk3228-vdec", "rockchip,rk3399-vdec"; - reg = <0x20030000 0x480>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, - <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - clock-names = "axi", "ahb", "cabac", "core"; - assigned-clocks = <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>; - assigned-clock-rates = <300000000>, <300000000>; - iommus = <&vdec_mmu>; - power-domains = <&power RK3228_PD_RKVDEC>; - }; - - vdec_mmu: iommu@20030480 { - compatible = "rockchip,iommu"; - reg = <0x20030480 0x40>, <0x200304c0 0x40>; - interrupts = ; - clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_RKVDEC>; - #iommu-cells = <0>; - }; - - vop: vop@20050000 { - compatible = "rockchip,rk3228-vop"; - reg = <0x20050000 0x1ffc>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; - resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>; - reset-names = "axi", "ahb", "dclk"; - iommus = <&vop_mmu>; - power-domains = <&power RK3228_PD_VOP>; - status = "disabled"; - - vop_out: port { - #address-cells = <1>; - #size-cells = <0>; - - vop_out_hdmi: endpoint@0 { - reg = <0>; - remote-endpoint = <&hdmi_in_vop>; - }; - }; - }; - - vop_mmu: iommu@20053f00 { - compatible = "rockchip,iommu"; - reg = <0x20053f00 0x100>; - interrupts = ; - clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VOP>; - #iommu-cells = <0>; - status = "disabled"; - }; - - rga: rga@20060000 { - compatible = "rockchip,rk3228-rga", "rockchip,rk3288-rga"; - reg = <0x20060000 0x1000>; - interrupts = ; - clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>; - clock-names = "aclk", "hclk", "sclk"; - power-domains = <&power RK3228_PD_VIO>; - resets = <&cru SRST_RGA>, <&cru SRST_RGA_A>, <&cru SRST_RGA_H>; - reset-names = "core", "axi", "ahb"; - }; - - iep_mmu: iommu@20070800 { - compatible = "rockchip,iommu"; - reg = <0x20070800 0x100>; - interrupts = ; - clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; - clock-names = "aclk", "iface"; - power-domains = <&power RK3228_PD_VIO>; - #iommu-cells = <0>; - status = "disabled"; - }; - - hdmi: hdmi@200a0000 { - compatible = "rockchip,rk3228-dw-hdmi"; - reg = <0x200a0000 0x20000>; - reg-io-width = <4>; - interrupts = ; - assigned-clocks = <&cru SCLK_HDMI_PHY>; - assigned-clock-parents = <&hdmi_phy>; - clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_CEC>; - clock-names = "isfr", "iahb", "cec"; - pinctrl-names = "default"; - pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; - resets = <&cru SRST_HDMI_P>; - reset-names = "hdmi"; - phys = <&hdmi_phy>; - phy-names = "hdmi"; - rockchip,grf = <&grf>; - status = "disabled"; - - ports { - hdmi_in: port { - #address-cells = <1>; - #size-cells = <0>; - hdmi_in_vop: endpoint@0 { - reg = <0>; - remote-endpoint = <&vop_out_hdmi>; - }; - }; - }; - }; - - sdmmc: mmc@30000000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30000000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, - <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>; - status = "disabled"; - }; - - sdio: mmc@30010000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30010000 0x4000>; - interrupts = ; - clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, - <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>; - status = "disabled"; - }; - - emmc: mmc@30020000 { - compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc"; - reg = <0x30020000 0x4000>; - interrupts = ; - clock-frequency = <37500000>; - max-frequency = <37500000>; - clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, - <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; - clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; - bus-width = <8>; - rockchip,default-sample-phase = <158>; - fifo-depth = <0x100>; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; - resets = <&cru SRST_EMMC>; - reset-names = "reset"; - status = "disabled"; - }; - - usb_otg: usb@30040000 { - compatible = "rockchip,rk3228-usb", "rockchip,rk3066-usb", - "snps,dwc2"; - reg = <0x30040000 0x40000>; - interrupts = ; - clocks = <&cru HCLK_OTG>; - clock-names = "otg"; - dr_mode = "otg"; - g-np-tx-fifo-size = <16>; - g-rx-fifo-size = <280>; - g-tx-fifo-size = <256 128 128 64 32 16>; - phys = <&u2phy0_otg>; - phy-names = "usb2-phy"; - status = "disabled"; - }; - - usb_host0_ehci: usb@30080000 { - compatible = "generic-ehci"; - reg = <0x30080000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host0_ohci: usb@300a0000 { - compatible = "generic-ohci"; - reg = <0x300a0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST0>, <&u2phy0>; - phys = <&u2phy0_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ehci: usb@300c0000 { - compatible = "generic-ehci"; - reg = <0x300c0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host1_ohci: usb@300e0000 { - compatible = "generic-ohci"; - reg = <0x300e0000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST1>, <&u2phy1>; - phys = <&u2phy1_otg>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ehci: usb@30100000 { - compatible = "generic-ehci"; - reg = <0x30100000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - usb_host2_ohci: usb@30120000 { - compatible = "generic-ohci"; - reg = <0x30120000 0x20000>; - interrupts = ; - clocks = <&cru HCLK_HOST2>, <&u2phy1>; - phys = <&u2phy1_host>; - phy-names = "usb"; - status = "disabled"; - }; - - gmac: ethernet@30200000 { - compatible = "rockchip,rk3228-gmac"; - reg = <0x30200000 0x10000>; - interrupts = ; - interrupt-names = "macirq"; - clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, - <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, - <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; - clock-names = "stmmaceth", "mac_clk_rx", - "mac_clk_tx", "clk_mac_ref", - "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; - rockchip,grf = <&grf>; - status = "disabled"; - }; - - qos_iep: qos@31030080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030080 0x20>; - }; - - qos_rga_w: qos@31030100 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030100 0x20>; - }; - - qos_hdcp: qos@31030180 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030180 0x20>; - }; - - qos_rga_r: qos@31030200 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31030200 0x20>; - }; - - qos_vpu: qos@31040000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31040000 0x20>; - }; - - qos_gpu: qos@31050000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31050000 0x20>; - }; - - qos_vop: qos@31060000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31060000 0x20>; - }; - - qos_rkvdec_r: qos@31070000 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070000 0x20>; - }; - - qos_rkvdec_w: qos@31070080 { - compatible = "rockchip,rk3228-qos", "syscon"; - reg = <0x31070080 0x20>; - }; - - gic: interrupt-controller@32010000 { - compatible = "arm,gic-400"; - interrupt-controller; - #interrupt-cells = <3>; - #address-cells = <0>; - - reg = <0x32011000 0x1000>, - <0x32012000 0x2000>, - <0x32014000 0x2000>, - <0x32016000 0x2000>; - interrupts = ; - }; - - pinctrl: pinctrl { - compatible = "rockchip,rk3228-pinctrl"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio0: gpio@11110000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11110000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO0>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio1: gpio@11120000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11120000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO1>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@11130000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11130000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO2>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio3: gpio@11140000 { - compatible = "rockchip,gpio-bank"; - reg = <0x11140000 0x100>; - interrupts = ; - clocks = <&cru PCLK_GPIO3>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; - - pcfg_pull_up: pcfg-pull-up { - bias-pull-up; - }; - - pcfg_pull_down: pcfg-pull-down { - bias-pull-down; - }; - - pcfg_pull_none: pcfg-pull-none { - bias-disable; - }; - - pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma { - drive-strength = <12>; - }; - - sdmmc { - sdmmc_clk: sdmmc-clk { - rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_cmd: sdmmc-cmd { - rockchip,pins = <1 RK_PB7 1 &pcfg_pull_none_drv_12ma>; - }; - - sdmmc_bus4: sdmmc-bus4 { - rockchip,pins = <1 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC4 1 &pcfg_pull_none_drv_12ma>, - <1 RK_PC5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - sdio { - sdio_clk: sdio-clk { - rockchip,pins = <3 RK_PA0 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_cmd: sdio-cmd { - rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none_drv_12ma>; - }; - - sdio_bus4: sdio-bus4 { - rockchip,pins = <3 RK_PA2 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA3 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA4 1 &pcfg_pull_none_drv_12ma>, - <3 RK_PA5 1 &pcfg_pull_none_drv_12ma>; - }; - }; - - emmc { - emmc_clk: emmc-clk { - rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; - }; - - emmc_cmd: emmc-cmd { - rockchip,pins = <1 RK_PC6 2 &pcfg_pull_none>; - }; - - emmc_bus8: emmc-bus8 { - rockchip,pins = <1 RK_PD0 2 &pcfg_pull_none>, - <1 RK_PD1 2 &pcfg_pull_none>, - <1 RK_PD2 2 &pcfg_pull_none>, - <1 RK_PD3 2 &pcfg_pull_none>, - <1 RK_PD4 2 &pcfg_pull_none>, - <1 RK_PD5 2 &pcfg_pull_none>, - <1 RK_PD6 2 &pcfg_pull_none>, - <1 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - gmac { - rgmii_pins: rgmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC6 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC7 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB1 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PC5 2 &pcfg_pull_none>, - <2 RK_PC4 2 &pcfg_pull_none>, - <2 RK_PB3 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>; - }; - - rmii_pins: rmii-pins { - rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none>, - <2 RK_PB4 1 &pcfg_pull_none>, - <2 RK_PD1 1 &pcfg_pull_none>, - <2 RK_PC3 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC2 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PB5 1 &pcfg_pull_none_drv_12ma>, - <2 RK_PC1 1 &pcfg_pull_none>, - <2 RK_PC0 1 &pcfg_pull_none>, - <2 RK_PB0 1 &pcfg_pull_none>, - <2 RK_PB7 1 &pcfg_pull_none>; - }; - - phy_pins: phy-pins { - rockchip,pins = <2 RK_PB6 2 &pcfg_pull_none>, - <2 RK_PB0 2 &pcfg_pull_none>; - }; - }; - - hdmi { - hdmi_hpd: hdmi-hpd { - rockchip,pins = <0 RK_PB7 1 &pcfg_pull_down>; - }; - - hdmii2c_xfer: hdmii2c-xfer { - rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, - <0 RK_PA7 2 &pcfg_pull_none>; - }; - - hdmi_cec: hdmi-cec { - rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; - }; - }; - - i2c0 { - i2c0_xfer: i2c0-xfer { - rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, - <0 RK_PA1 1 &pcfg_pull_none>; - }; - }; - - i2c1 { - i2c1_xfer: i2c1-xfer { - rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, - <0 RK_PA3 1 &pcfg_pull_none>; - }; - }; - - i2c2 { - i2c2_xfer: i2c2-xfer { - rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>, - <2 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - i2c3 { - i2c3_xfer: i2c3-xfer { - rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, - <0 RK_PA7 1 &pcfg_pull_none>; - }; - }; - - spi0 { - spi0_clk: spi0-clk { - rockchip,pins = <0 RK_PB1 2 &pcfg_pull_up>; - }; - spi0_cs0: spi0-cs0 { - rockchip,pins = <0 RK_PB6 2 &pcfg_pull_up>; - }; - spi0_tx: spi0-tx { - rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; - }; - spi0_rx: spi0-rx { - rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; - }; - spi0_cs1: spi0-cs1 { - rockchip,pins = <1 RK_PB4 1 &pcfg_pull_up>; - }; - }; - - spi1 { - spi1_clk: spi1-clk { - rockchip,pins = <0 RK_PC7 2 &pcfg_pull_up>; - }; - spi1_cs0: spi1-cs0 { - rockchip,pins = <2 RK_PA2 2 &pcfg_pull_up>; - }; - spi1_rx: spi1-rx { - rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up>; - }; - spi1_tx: spi1-tx { - rockchip,pins = <2 RK_PA1 2 &pcfg_pull_up>; - }; - spi1_cs1: spi1-cs1 { - rockchip,pins = <2 RK_PA3 2 &pcfg_pull_up>; - }; - }; - - i2s1 { - i2s1_bus: i2s1-bus { - rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, - <0 RK_PB1 1 &pcfg_pull_none>, - <0 RK_PB3 1 &pcfg_pull_none>, - <0 RK_PB4 1 &pcfg_pull_none>, - <0 RK_PB5 1 &pcfg_pull_none>, - <0 RK_PB6 1 &pcfg_pull_none>, - <1 RK_PA2 2 &pcfg_pull_none>, - <1 RK_PA4 2 &pcfg_pull_none>, - <1 RK_PA5 2 &pcfg_pull_none>; - }; - }; - - pwm0 { - pwm0_pin: pwm0-pin { - rockchip,pins = <3 RK_PC5 1 &pcfg_pull_none>; - }; - }; - - pwm1 { - pwm1_pin: pwm1-pin { - rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>; - }; - }; - - pwm2 { - pwm2_pin: pwm2-pin { - rockchip,pins = <1 RK_PB4 2 &pcfg_pull_none>; - }; - }; - - pwm3 { - pwm3_pin: pwm3-pin { - rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; - }; - }; - - spdif { - spdif_tx: spdif-tx { - rockchip,pins = <3 RK_PD7 2 &pcfg_pull_none>; - }; - }; - - tsadc { - otp_pin: otp-pin { - rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; - }; - - otp_out: otp-out { - rockchip,pins = <0 RK_PD0 2 &pcfg_pull_none>; - }; - }; - - uart0 { - uart0_xfer: uart0-xfer { - rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>, - <2 RK_PD3 1 &pcfg_pull_none>; - }; - - uart0_cts: uart0-cts { - rockchip,pins = <2 RK_PD5 1 &pcfg_pull_none>; - }; - - uart0_rts: uart0-rts { - rockchip,pins = <0 RK_PC1 1 &pcfg_pull_none>; - }; - }; - - uart1 { - uart1_xfer: uart1-xfer { - rockchip,pins = <1 RK_PB1 1 &pcfg_pull_none>, - <1 RK_PB2 1 &pcfg_pull_none>; - }; - - uart1_cts: uart1-cts { - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>; - }; - - uart1_rts: uart1-rts { - rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>; - }; - }; - - uart2 { - uart2_xfer: uart2-xfer { - rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, - <1 RK_PC3 2 &pcfg_pull_none>; - }; - - uart21_xfer: uart21-xfer { - rockchip,pins = <1 RK_PB2 2 &pcfg_pull_up>, - <1 RK_PB1 2 &pcfg_pull_none>; - }; - - uart2_cts: uart2-cts { - rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; - }; - - uart2_rts: uart2-rts { - rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; - }; - }; - }; -}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 02737c62df0..d92fcae2bb5 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,7 @@ config ROCKCHIP_RK322X select TPL_OF_LIBFDT select TPL_HAVE_INIT_STACK if TPL select SPL_DRIVERS_MISC + imply OF_UPSTREAM imply ROCKCHIP_COMMON_BOARD imply SPL_SERIAL imply SPL_ROCKCHIP_COMMON_BOARD diff --git a/board/rockchip/evb_rk3229/MAINTAINERS b/board/rockchip/evb_rk3229/MAINTAINERS index 4de97dbb0a4..7758ee9b930 100644 --- a/board/rockchip/evb_rk3229/MAINTAINERS +++ b/board/rockchip/evb_rk3229/MAINTAINERS @@ -1,7 +1,6 @@ EVB-RK3229 M: Kever Yang S: Maintained -F: arch/arm/dts/rk3229-evb.dts F: arch/arm/dts/rk3229-evb-u-boot.dtsi F: board/rockchip/evb_rk3229 F: include/configs/evb_rk3229.h diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 251ff4a0b6d..577b6580b3b 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x61100000 CONFIG_ENV_OFFSET=0x3F8000 -CONFIG_DEFAULT_DEVICE_TREE="rk3229-evb" +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3229-evb" CONFIG_ROCKCHIP_RK322X=y CONFIG_TARGET_EVB_RK3229=y CONFIG_SPL_STACK_R_ADDR=0x60600000 @@ -24,7 +24,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y CONFIG_USE_PREBOOT=y -CONFIG_DEFAULT_FDT_FILE="rk3229-evb.dtb" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3229-evb.dtb" # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_MAX_SIZE=0x100000 diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h deleted file mode 100644 index de550ea56ee..00000000000 --- a/include/dt-bindings/clock/rk3228-cru.h +++ /dev/null @@ -1,287 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ -/* - * Copyright (c) 2015 Rockchip Electronics Co. Ltd. - * Author: Jeffy Chen - */ - -#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H -#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H - -/* core clocks */ -#define PLL_APLL 1 -#define PLL_DPLL 2 -#define PLL_CPLL 3 -#define PLL_GPLL 4 -#define ARMCLK 5 - -/* sclk gates (special clocks) */ -#define SCLK_SPI0 65 -#define SCLK_NANDC 67 -#define SCLK_SDMMC 68 -#define SCLK_SDIO 69 -#define SCLK_EMMC 71 -#define SCLK_TSADC 72 -#define SCLK_UART0 77 -#define SCLK_UART1 78 -#define SCLK_UART2 79 -#define SCLK_I2S0 80 -#define SCLK_I2S1 81 -#define SCLK_I2S2 82 -#define SCLK_SPDIF 83 -#define SCLK_TIMER0 85 -#define SCLK_TIMER1 86 -#define SCLK_TIMER2 87 -#define SCLK_TIMER3 88 -#define SCLK_TIMER4 89 -#define SCLK_TIMER5 90 -#define SCLK_I2S_OUT 113 -#define SCLK_SDMMC_DRV 114 -#define SCLK_SDIO_DRV 115 -#define SCLK_EMMC_DRV 117 -#define SCLK_SDMMC_SAMPLE 118 -#define SCLK_SDIO_SAMPLE 119 -#define SCLK_SDIO_SRC 120 -#define SCLK_EMMC_SAMPLE 121 -#define SCLK_VOP 122 -#define SCLK_HDMI_HDCP 123 -#define SCLK_MAC_SRC 124 -#define SCLK_MAC_EXTCLK 125 -#define SCLK_MAC 126 -#define SCLK_MAC_REFOUT 127 -#define SCLK_MAC_REF 128 -#define SCLK_MAC_RX 129 -#define SCLK_MAC_TX 130 -#define SCLK_MAC_PHY 131 -#define SCLK_MAC_OUT 132 -#define SCLK_VDEC_CABAC 133 -#define SCLK_VDEC_CORE 134 -#define SCLK_RGA 135 -#define SCLK_HDCP 136 -#define SCLK_HDMI_CEC 137 -#define SCLK_CRYPTO 138 -#define SCLK_TSP 139 -#define SCLK_HSADC 140 -#define SCLK_WIFI 141 -#define SCLK_OTGPHY0 142 -#define SCLK_OTGPHY1 143 -#define SCLK_HDMI_PHY 144 - -/* dclk gates */ -#define DCLK_VOP 190 -#define DCLK_HDMI_PHY 191 - -/* aclk gates */ -#define ACLK_DMAC 194 -#define ACLK_CPU 195 -#define ACLK_VPU_PRE 196 -#define ACLK_RKVDEC_PRE 197 -#define ACLK_RGA_PRE 198 -#define ACLK_IEP_PRE 199 -#define ACLK_HDCP_PRE 200 -#define ACLK_VOP_PRE 201 -#define ACLK_VPU 202 -#define ACLK_RKVDEC 203 -#define ACLK_IEP 204 -#define ACLK_RGA 205 -#define ACLK_HDCP 206 -#define ACLK_PERI 210 -#define ACLK_VOP 211 -#define ACLK_GMAC 212 -#define ACLK_GPU 213 - -/* pclk gates */ -#define PCLK_GPIO0 320 -#define PCLK_GPIO1 321 -#define PCLK_GPIO2 322 -#define PCLK_GPIO3 323 -#define PCLK_VIO_H2P 324 -#define PCLK_HDCP 325 -#define PCLK_EFUSE_1024 326 -#define PCLK_EFUSE_256 327 -#define PCLK_GRF 329 -#define PCLK_I2C0 332 -#define PCLK_I2C1 333 -#define PCLK_I2C2 334 -#define PCLK_I2C3 335 -#define PCLK_SPI0 338 -#define PCLK_UART0 341 -#define PCLK_UART1 342 -#define PCLK_UART2 343 -#define PCLK_TSADC 344 -#define PCLK_PWM 350 -#define PCLK_TIMER 353 -#define PCLK_CPU 354 -#define PCLK_PERI 363 -#define PCLK_HDMI_CTRL 364 -#define PCLK_HDMI_PHY 365 -#define PCLK_GMAC 367 - -/* hclk gates */ -#define HCLK_I2S0_8CH 442 -#define HCLK_I2S1_8CH 443 -#define HCLK_I2S2_2CH 444 -#define HCLK_SPDIF_8CH 445 -#define HCLK_VOP 452 -#define HCLK_NANDC 453 -#define HCLK_SDMMC 456 -#define HCLK_SDIO 457 -#define HCLK_EMMC 459 -#define HCLK_CPU 460 -#define HCLK_VPU_PRE 461 -#define HCLK_RKVDEC_PRE 462 -#define HCLK_VIO_PRE 463 -#define HCLK_VPU 464 -#define HCLK_RKVDEC 465 -#define HCLK_VIO 466 -#define HCLK_RGA 467 -#define HCLK_IEP 468 -#define HCLK_VIO_H2P 469 -#define HCLK_HDCP_MMU 470 -#define HCLK_HOST0 471 -#define HCLK_HOST1 472 -#define HCLK_HOST2 473 -#define HCLK_OTG 474 -#define HCLK_TSP 475 -#define HCLK_M_CRYPTO 476 -#define HCLK_S_CRYPTO 477 -#define HCLK_PERI 478 - -#define CLK_NR_CLKS (HCLK_PERI + 1) - -/* soft-reset indices */ -#define SRST_CORE0_PO 0 -#define SRST_CORE1_PO 1 -#define SRST_CORE2_PO 2 -#define SRST_CORE3_PO 3 -#define SRST_CORE0 4 -#define SRST_CORE1 5 -#define SRST_CORE2 6 -#define SRST_CORE3 7 -#define SRST_CORE0_DBG 8 -#define SRST_CORE1_DBG 9 -#define SRST_CORE2_DBG 10 -#define SRST_CORE3_DBG 11 -#define SRST_TOPDBG 12 -#define SRST_ACLK_CORE 13 -#define SRST_NOC 14 -#define SRST_L2C 15 - -#define SRST_CPUSYS_H 18 -#define SRST_BUSSYS_H 19 -#define SRST_SPDIF 20 -#define SRST_INTMEM 21 -#define SRST_ROM 22 -#define SRST_OTG_ADP 23 -#define SRST_I2S0 24 -#define SRST_I2S1 25 -#define SRST_I2S2 26 -#define SRST_ACODEC_P 27 -#define SRST_DFIMON 28 -#define SRST_MSCH 29 -#define SRST_EFUSE1024 30 -#define SRST_EFUSE256 31 - -#define SRST_GPIO0 32 -#define SRST_GPIO1 33 -#define SRST_GPIO2 34 -#define SRST_GPIO3 35 -#define SRST_PERIPH_NOC_A 36 -#define SRST_PERIPH_NOC_BUS_H 37 -#define SRST_PERIPH_NOC_P 38 -#define SRST_UART0 39 -#define SRST_UART1 40 -#define SRST_UART2 41 -#define SRST_PHYNOC 42 -#define SRST_I2C0 43 -#define SRST_I2C1 44 -#define SRST_I2C2 45 -#define SRST_I2C3 46 - -#define SRST_PWM 48 -#define SRST_A53_GIC 49 -#define SRST_DAP 51 -#define SRST_DAP_NOC 52 -#define SRST_CRYPTO 53 -#define SRST_SGRF 54 -#define SRST_GRF 55 -#define SRST_GMAC 56 -#define SRST_PERIPH_NOC_H 58 -#define SRST_MACPHY 63 - -#define SRST_DMA 64 -#define SRST_NANDC 68 -#define SRST_USBOTG 69 -#define SRST_OTGC 70 -#define SRST_USBHOST0 71 -#define SRST_HOST_CTRL0 72 -#define SRST_USBHOST1 73 -#define SRST_HOST_CTRL1 74 -#define SRST_USBHOST2 75 -#define SRST_HOST_CTRL2 76 -#define SRST_USBPOR0 77 -#define SRST_USBPOR1 78 -#define SRST_DDRMSCH 79 - -#define SRST_SMART_CARD 80 -#define SRST_SDMMC 81 -#define SRST_SDIO 82 -#define SRST_EMMC 83 -#define SRST_SPI 84 -#define SRST_TSP_H 85 -#define SRST_TSP 86 -#define SRST_TSADC 87 -#define SRST_DDRPHY 88 -#define SRST_DDRPHY_P 89 -#define SRST_DDRCTRL 90 -#define SRST_DDRCTRL_P 91 -#define SRST_HOST0_ECHI 92 -#define SRST_HOST1_ECHI 93 -#define SRST_HOST2_ECHI 94 -#define SRST_VOP_NOC_A 95 - -#define SRST_HDMI_P 96 -#define SRST_VIO_ARBI_H 97 -#define SRST_IEP_NOC_A 98 -#define SRST_VIO_NOC_H 99 -#define SRST_VOP_A 100 -#define SRST_VOP_H 101 -#define SRST_VOP_D 102 -#define SRST_UTMI0 103 -#define SRST_UTMI1 104 -#define SRST_UTMI2 105 -#define SRST_UTMI3 106 -#define SRST_RGA 107 -#define SRST_RGA_NOC_A 108 -#define SRST_RGA_A 109 -#define SRST_RGA_H 110 -#define SRST_HDCP_A 111 - -#define SRST_VPU_A 112 -#define SRST_VPU_H 113 -#define SRST_VPU_NOC_A 116 -#define SRST_VPU_NOC_H 117 -#define SRST_RKVDEC_A 118 -#define SRST_RKVDEC_NOC_A 119 -#define SRST_RKVDEC_H 120 -#define SRST_RKVDEC_NOC_H 121 -#define SRST_RKVDEC_CORE 122 -#define SRST_RKVDEC_CABAC 123 -#define SRST_IEP_A 124 -#define SRST_IEP_H 125 -#define SRST_GPU_A 126 -#define SRST_GPU_NOC_A 127 - -#define SRST_CORE_DBG 128 -#define SRST_DBG_P 129 -#define SRST_TIMER0 130 -#define SRST_TIMER1 131 -#define SRST_TIMER2 132 -#define SRST_TIMER3 133 -#define SRST_TIMER4 134 -#define SRST_TIMER5 135 -#define SRST_VIO_H2P 136 -#define SRST_HDMIPHY 139 -#define SRST_VDAC 140 -#define SRST_TIMER_6CH_P 141 - -#endif -- cgit v1.3.1 From a06d8334e5f4cd31392e13a168b20a95139b2f18 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Jun 2026 20:20:58 +0200 Subject: ram: renesas: dbsc5: Add Renesas R-Car Gen5 DBSC5 driver Add Renesas R-Car Gen5 DBSC5 DRAM controller driver. This driver is currently capable of bringing LPDDR5X DRAM on Renesas R-Car X5H Ironhide board. Further boards can be supported by supplying board specific DRAM configuration data via dbsc5_get_board_data(). The driver reuses parts of previous DBSC5 driver, but due to hardware changes, can not be fully integrated into existing DBSC and DRAM driver, therefore the currentl DBSC and DRAM drivers are moved into R8A779G0 V4H specific files, and the R8A78000 X5H files are added in parallel. The Gen5 DBSC driver is meant to be used in RSIP context, while the Gen4 DBSC driver is meant to be used in SPL, therefore the Kconfig conditionals have been adjusted to match. Signed-off-by: Marek Vasut --- board/renesas/sparrowhawk/sparrowhawk.c | 2 +- drivers/ram/renesas/Kconfig | 6 +- drivers/ram/renesas/Makefile | 2 - drivers/ram/renesas/dbsc5/Makefile | 4 +- drivers/ram/renesas/dbsc5/dbsc5.c | 80 - drivers/ram/renesas/dbsc5/dbsc5.h | 29 - drivers/ram/renesas/dbsc5/dram.c | 4537 ----------------- drivers/ram/renesas/dbsc5/ecc.c | 168 + drivers/ram/renesas/dbsc5/qos.c | 2 +- drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c | 80 + drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h | 29 + drivers/ram/renesas/dbsc5/r8a779g0-dram.c | 4537 +++++++++++++++++ drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c | 76 + drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h | 17 + drivers/ram/renesas/dbsc5/r8a78000-dram.c | 2795 +++++++++++ drivers/ram/renesas/dbsc5/r8a78000-dram.h | 7385 ++++++++++++++++++++++++++++ include/dbsc5.h | 56 - include/r8a779g0-dbsc5.h | 56 + include/r8a78000-dbsc5.h | 63 + 19 files changed, 15214 insertions(+), 4710 deletions(-) delete mode 100644 drivers/ram/renesas/dbsc5/dbsc5.c delete mode 100644 drivers/ram/renesas/dbsc5/dbsc5.h delete mode 100644 drivers/ram/renesas/dbsc5/dram.c create mode 100644 drivers/ram/renesas/dbsc5/ecc.c create mode 100644 drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c create mode 100644 drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h create mode 100644 drivers/ram/renesas/dbsc5/r8a779g0-dram.c create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dram.c create mode 100644 drivers/ram/renesas/dbsc5/r8a78000-dram.h delete mode 100644 include/dbsc5.h create mode 100644 include/r8a779g0-dbsc5.h create mode 100644 include/r8a78000-dbsc5.h (limited to 'include') diff --git a/board/renesas/sparrowhawk/sparrowhawk.c b/board/renesas/sparrowhawk/sparrowhawk.c index f5b1a5614b1..a229542ba7e 100644 --- a/board/renesas/sparrowhawk/sparrowhawk.c +++ b/board/renesas/sparrowhawk/sparrowhawk.c @@ -5,7 +5,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/ram/renesas/Kconfig b/drivers/ram/renesas/Kconfig index 6a1ef2a0c63..8c3e5fab96f 100644 --- a/drivers/ram/renesas/Kconfig +++ b/drivers/ram/renesas/Kconfig @@ -1,7 +1,7 @@ config RAM_RENESAS_DBSC5 - bool "Renesas R-Car V4H/V4M DBSC5 controller driver" - depends on SPL && RAM && (R8A779G0 || R8A779H0) + bool "Renesas R-Car V4H/V4M/X5H DBSC5 controller driver" + depends on RAM && (R8A78000 || (SPL && (R8A779G0 || R8A779H0))) default n help Enable this to support the DBSC5 DRAM controller initialization - on Renesas R8A779G0/R8A779H0 SoCs. + on Renesas R8A779G0/R8A779H0/R8A78000 SoCs. diff --git a/drivers/ram/renesas/Makefile b/drivers/ram/renesas/Makefile index 578d05622d7..699b726972b 100644 --- a/drivers/ram/renesas/Makefile +++ b/drivers/ram/renesas/Makefile @@ -1,6 +1,4 @@ # SPDX-License-Identifier: GPL-2.0+ -ifdef CONFIG_XPL_BUILD obj-$(CONFIG_RAM_RENESAS_DBSC5) += dbsc5/ -endif obj-$(CONFIG_RZN1) += rzn1/ diff --git a/drivers/ram/renesas/dbsc5/Makefile b/drivers/ram/renesas/dbsc5/Makefile index 177be893e10..0ae2193e09b 100644 --- a/drivers/ram/renesas/dbsc5/Makefile +++ b/drivers/ram/renesas/dbsc5/Makefile @@ -1,3 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += dbsc5.o dram.o qos.o rtvram.o +obj-$(CONFIG_R8A779G0) += r8a779g0-dbsc5.o r8a779g0-dram.o qos.o +obj-$(CONFIG_R8A78000) += r8a78000-dbsc5.o r8a78000-dram.o ecc.o +obj-y += rtvram.o diff --git a/drivers/ram/renesas/dbsc5/dbsc5.c b/drivers/ram/renesas/dbsc5/dbsc5.c deleted file mode 100644 index 4cbc6aeda43..00000000000 --- a/drivers/ram/renesas/dbsc5/dbsc5.c +++ /dev/null @@ -1,80 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include "dbsc5.h" - -static int renesas_dbsc5_probe(struct udevice *dev) -{ - struct udevice *pdev; - int ret; - - ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &pdev); - if (ret) - return ret; - - ret = uclass_get_device_by_name(UCLASS_NOP, "dbsc5_qos", &pdev); - if (ret) - return ret; - - return 0; -} - -int renesas_dbsc5_bind(struct udevice *dev) -{ - struct udevice *ramdev, *qosdev; - struct driver *ramdrv, *qosdrv; - int ret; - - ramdrv = lists_driver_lookup_name("dbsc5_dram"); - if (!ramdrv) - return -ENOENT; - - - qosdrv = lists_driver_lookup_name("dbsc5_qos"); - if (!qosdrv) - return -ENOENT; - - ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", - dev_get_driver_data(dev), - dev_ofnode(dev), &ramdev); - if (ret) - return ret; - - ret = device_bind_with_driver_data(dev, qosdrv, "dbsc5_qos", 0, - dev_ofnode(dev), &qosdev); - if (ret) - device_unbind(ramdev); - - return ret; -} - -struct renesas_dbsc5_data r8a779g0_dbsc5_data = { - .clock_node = "renesas,r8a779g0-cpg-mssr", - .reset_node = "renesas,r8a779g0-rst", - .otp_node = "renesas,r8a779g0-otp", -}; - -static const struct udevice_id renesas_dbsc5_ids[] = { - { - .compatible = "renesas,r8a779g0-dbsc", - .data = (ulong)&r8a779g0_dbsc5_data - }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(renesas_dbsc5) = { - .name = "dbsc5", - .id = UCLASS_NOP, - .of_match = renesas_dbsc5_ids, - .bind = renesas_dbsc5_bind, - .probe = renesas_dbsc5_probe, -}; diff --git a/drivers/ram/renesas/dbsc5/dbsc5.h b/drivers/ram/renesas/dbsc5/dbsc5.h deleted file mode 100644 index bf22fcb8c11..00000000000 --- a/drivers/ram/renesas/dbsc5/dbsc5.h +++ /dev/null @@ -1,29 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -#ifndef __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ -#define __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ - -/* - * DBSC5 ... 0xe678_0000..0xe67fffff - * - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0 - * - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0 - * - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM - * - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0 - * - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB) - */ -#define DBSC5_AXMM_OFFSET 0x00000 -#define DBSC5_DBSC_A_OFFSET 0x10000 -#define DBSC5_CCI_OFFSET 0x20000 -#define DBSC5_DBSC_D_OFFSET 0x24000 -#define DBSC5_QOS_OFFSET 0x60000 - -struct renesas_dbsc5_data { - const char *clock_node; - const char *reset_node; - const char *otp_node; -}; - -#endif /* __DRIVERS_RAM_RENESAS_DBSC5_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/dram.c b/drivers/ram/renesas/dbsc5/dram.c deleted file mode 100644 index 3ed02e11f9e..00000000000 --- a/drivers/ram/renesas/dbsc5/dram.c +++ /dev/null @@ -1,4537 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2024 Renesas Electronics Corp. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "dbsc5.h" - -/* Number of array elements in Data Slice */ -#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 -/* Number of array elements in Data Slice */ -#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 -/* Number of array elements in Address Slice */ -#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 -/* Number of array elements in Address Control Slice */ -#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 -/* Number of array elements in PI Register */ -#define DDR_PI_REGSET_NUM_V4H 1381 - -/* Minimum value table for JS1 configuration table that can be taken */ -#define JS1_USABLEC_SPEC_LO 5 -/* Maximum value table for JS1 configuration table that can be taken */ -#define JS1_USABLEC_SPEC_HI 11 -/* The number of JS1 setting table */ -#define JS1_FREQ_TBL_NUM 12 -/* Macro to set the value of MR1 */ -#define JS1_MR1(f) (((f) << 4) | 0x00) /* CK mode = 0B */ -/* Macro to set the value of MR2 */ -#define JS1_MR2(f) (((f) << 4) | (f)) - -#define JS2_tSR 0 /* Element for self refresh */ -#define JS2_tXP 1 /* Exit power-down mode to first valid command */ -#define JS2_tRCD 2 /* Active to read or write delay */ -#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ -#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ -#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ -#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ -#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ -#define JS2_tRRD 8 /* Active bank a to active bank b command */ -#define JS2_tPPD 9 /* Precharge Power Down */ -#define JS2_tFAW 10 /* Four bank ACT window */ -#define JS2_tMRR 11 /* Mode Register Read */ -#define JS2_tMRW 12 /* Mode Register Write */ -#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ -#define JS2_tZQCALns 14 /* ZQ Calibration */ -#define JS2_tZQLAT 15 /* ZQ Latency */ -#define JS2_tODTon_min 16 /* Minimum time on die termination */ -#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ -#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ -#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ -#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ -#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ -#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ -#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ -#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ -#define JS2_tDQ72DQns 25 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ -#define JS2_tCAENTns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ -#define JS2_tCSCAL 27 /* Minimum CA Low Duration time */ -#define JS2_TBLCNT 28 /* The number of table */ - -#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ -#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ -#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ -#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ -#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ -#define JS2_tPDN (JS2_TBLCNT + 5) -#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) -#define JS2_CNT (JS2_TBLCNT + 7) - -struct jedec_spec1 { - u32 fx3; /* Frequency */ - u8 RLset1; /* setting value of Read Latency */ - u8 RLset2; /* setting value of Read Latency */ - u8 WLsetA; /* setting value of Write Latency */ - u8 WLsetB; /* setting value of Write Latency */ - u32 nWR; /* Write-Recovery for Auto-Precharge commands */ - u32 nRBTP; /* the minimum interval from a READ command to a PRE command */ - u32 ODTLon; /* On Die Termination */ - u8 MR1; /* Mode Register 1 */ - u8 MR2; /* Mode Register 2 */ - u32 WCKENLR; /* The setting time from CAS command to the Start-up of WCK in READ operation */ - u32 WCKENLW; /* The setting time from CAS command to the Start-up of WCK in WRITE operation */ - u32 WCKENLF; /* The setting time from CAS command to the Start-up of WCK in FAST-sync operation */ - u32 WCKPRESTA; /* The setting time from the Start-up of WCK to WCK Clocling Start */ - u32 WCKPRETGLR; /* The setting time from WCK Clocling Start to Reflecting frequency of WCK */ -}; - -static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { - /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ - { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ - { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ - { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ - { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ - { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ - { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ - { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ - { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ - { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ - { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ - { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ - { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ -}; - -struct jedec_spec2 { - u16 ps; /* Value in pico seconds */ - u16 cyc; /* Value in cycle count */ -}; - -static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { - { - { 15000, 2 }, /* tSR */ - { 7000, 3 }, /* tXP */ - { 18000, 2 }, /* tRCD */ - { 18000, 2 }, /* tRPpb */ - { 21000, 2 }, /* tRPab */ - { 42000, 3 }, /* tRAS */ - { 6250, 4 }, /* tWTR_S */ - { 12000, 4 }, /* tWTR_L */ - { 5000, 2 }, /* tRRD */ - { 0, 2 }, /* tPPD */ - { 20000, 0 }, /* tFAW */ - { 0, 4 }, /* tMRR */ - { 10000, 5 }, /* tMRW */ - { 14000, 5 }, /* tMRD */ - { 1500, 0 }, /* tZQCALns */ - { 30000, 4 }, /* tZQLAT */ - { 1500, 0 }, /* tODTon_min */ - { 4000, 0 }, /* tPDN_DSMus */ - { 200, 0 }, /* tXSR_DSMus */ - { 190, 0 }, /* tXDSM_XPus */ - { 700, 0 }, /* tWCK2DQI_HF */ - { 1600, 0 }, /* tWCK2DQO_HF */ - { 900, 0 }, /* tWCK2DQI_LF */ - { 1900, 0 }, /* tWCK2DQO_LF */ - { 40000, 8 }, /* tOSCODQI */ - { 125, 0 }, /* tDQ72DQns */ - { 250, 0 }, /* tCAENTns */ - { 1750, 0 } /* tCSCAL */ - }, { - { 15000, 2 }, /* tSR */ - { 7000, 3 }, /* tXP */ - { 19875, 2 }, /* tRCD */ - { 19875, 2 }, /* tRPpb */ - { 22875, 2 }, /* tRPab */ - { 43875, 3 }, /* tRAS */ - { 6250, 4 }, /* tWTR_S */ - { 12000, 4 }, /* tWTR_L */ - { 5000, 2 }, /* tRRD */ - { 0, 2 }, /* tPPD */ - { 20000, 0 }, /* tFAW */ - { 0, 4 }, /* tMRR */ - { 10000, 5 }, /* tMRW */ - { 14000, 5 }, /* tMRD */ - { 1500, 0 }, /* tZQCALns */ - { 30000, 4 }, /* tZQLAT */ - { 1500, 0 }, /* tODTon_min */ - { 4000, 0 }, /* tPDN_DSMus */ - { 200, 0 }, /* tXSR_DSMus */ - { 190, 0 }, /* tXDSM_XPus */ - { 715, 0 }, /* tWCK2DQI_HF */ - { 1635, 0 }, /* tWCK2DQO_HF */ - { 920, 0 }, /* tWCK2DQI_LF */ - { 1940, 0 }, /* tWCK2DQO_LF */ - { 40000, 8 }, /* tOSCODQI */ - { 125, 0 }, /* tDQ72DQns */ - { 250, 0 }, /* tCAENTns */ - { 1750, 0 } /* tCSCAL */ - } -}; - -static const u16 jedec_spec2_tRFC_ab[] = { - /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ - 130, 180, 180, 210, 210, 280, 280, 380, 380 -}; - -/* The address offsets of PI Register */ -#define DDR_PI_REGSET_OFS_V4H 0x0800 -/* The address offsets of Data Slice */ -#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 -/* The address offsets of Address Slice */ -#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 -/* The address offsets of Address Control Slice */ -#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 - -#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFF) -#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFF) -#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFF) - -#define DDR_REGDEF(lsb, len, adr) \ - (((lsb) << 24) | ((len) << 16) | (adr)) - -#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1000) -#define PHY_PER_CS_TRAINING_MULTICAST_EN DDR_REGDEF(0x10, 0x01, 0x1006) -#define PHY_PER_CS_TRAINING_INDEX DDR_REGDEF(0x18, 0x01, 0x1006) -#define PHY_VREF_INITIAL_STEPSIZE DDR_REGDEF(0x18, 0x08, 0x100D) -#define PHY_RDLVL_BEST_THRSHLD DDR_REGDEF(0x00, 0x04, 0x100E) -#define PHY_RDLVL_VREF_OUTLIER DDR_REGDEF(0x10, 0x03, 0x100E) -#define SC_PHY_WCK_CALC DDR_REGDEF(0x18, 0x01, 0x101A) -#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT DDR_REGDEF(0x10, 0x05, 0x102C) -#define PHY_CALVL_VREF_DRIVING_SLICE DDR_REGDEF(0x18, 0x01, 0x1030) -#define PHY_WRLVL_HARD0_DELAY_OBS DDR_REGDEF(0x00, 0x0A, 0x1038) -#define PHY_WRLVL_HARD1_DELAY_OBS DDR_REGDEF(0x10, 0x0A, 0x1038) -#define PHY_WRLVL_STATUS_OBS DDR_REGDEF(0x00, 0x1C, 0x1039) -#define PHY_WRLVL_ERROR_OBS DDR_REGDEF(0x00, 0x10, 0x103B) -#define PHY_GTLVL_STATUS_OBS DDR_REGDEF(0x00, 0x12, 0x103D) -#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS DDR_REGDEF(0x10, 0x09, 0x103E) -#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F) -#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043) -#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D) -#define PHY_SLV_DLY_CTRL_GATE_DISABLE DDR_REGDEF(0x10, 0x01, 0x104E) -#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050) -#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055) -#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055) -#define PHY_VREF_TRAINING_CTRL DDR_REGDEF(0x00, 0x02, 0x1056) -#define PHY_RDDQ0_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105D) -#define PHY_RDDQ1_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105D) -#define PHY_RDDQ2_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105E) -#define PHY_RDDQ3_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105E) -#define PHY_RDDQ4_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105F) -#define PHY_RDDQ5_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105F) -#define PHY_RDDQ6_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1060) -#define PHY_RDDQ7_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x1060) -#define PHY_RDDM_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1061) -#define PHY_RX_CAL_ALL_DLY DDR_REGDEF(0x18, 0x06, 0x1061) -#define PHY_RX_PCLK_CLK_SEL DDR_REGDEF(0x00, 0x03, 0x1062) -#define PHY_DATA_DC_CAL_CLK_SEL DDR_REGDEF(0x18, 0x03, 0x1063) -#define PHY_PAD_VREF_CTRL_DQ DDR_REGDEF(0x00, 0x0E, 0x1067) -#define PHY_PER_CS_TRAINING_EN DDR_REGDEF(0x00, 0x01, 0x1068) -#define PHY_RDDATA_EN_TSEL_DLY DDR_REGDEF(0x18, 0x05, 0x1069) -#define PHY_RDDATA_EN_OE_DLY DDR_REGDEF(0x00, 0x05, 0x106A) -#define PHY_RPTR_UPDATE DDR_REGDEF(0x10, 0x04, 0x106C) -#define PHY_WRLVL_RESP_WAIT_CNT DDR_REGDEF(0x08, 0x06, 0x106D) -#define PHY_RDLVL_DLY_STEP DDR_REGDEF(0x08, 0x04, 0x1070) -#define PHY_RDLVL_MAX_EDGE DDR_REGDEF(0x00, 0x09, 0x1071) -#define PHY_DATA_DC_WDQLVL_ENABLE DDR_REGDEF(0x08, 0x02, 0x1075) -#define PHY_RDDATA_EN_DLY DDR_REGDEF(0x10, 0x05, 0x1076) -#define PHY_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x08, 0x06, 0x1076) -#define PHY_DQ_DM_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1077) -#define PHY_DQ_DM_SWIZZLE1 DDR_REGDEF(0x00, 0x04, 0x1078) -#define PHY_CLK_WRDQS_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x107E) -#define PHY_WRITE_PATH_LAT_DEC DDR_REGDEF(0x10, 0x01, 0x107E) -#define PHY_RDDQS_GATE_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1088) -#define PHY_RDDQS_LATENCY_ADJUST DDR_REGDEF(0x10, 0x05, 0x1088) -#define PHY_WRITE_PATH_LAT_ADD DDR_REGDEF(0x18, 0x03, 0x1088) -#define PHY_WRITE_PATH_LAT_FRAC DDR_REGDEF(0x00, 0x08, 0x1089) -#define PHY_GTLVL_LAT_ADJ_START DDR_REGDEF(0x00, 0x05, 0x108A) -#define PHY_DATA_DC_DQS_CLK_ADJUST DDR_REGDEF(0x00, 0x08, 0x108C) -#define PHY_ADR_CALVL_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1202) -#define PHY_ADR_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x10, 0x01, 0x1203) -#define PHY_ADR_CALVL_RANK_CTRL DDR_REGDEF(0x18, 0x02, 0x1205) -#define PHY_ADR_CALVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x120A) -#define PHY_ADR_CALVL_OBS2 DDR_REGDEF(0x00, 0x20, 0x120B) -#define PHY_ADR_CALVL_DLY_STEP DDR_REGDEF(0x00, 0x04, 0x1210) -#define PHY_CS_ACS_ALLOCATION_BIT2_2 DDR_REGDEF(0x08, 0x02, 0x1215) -#define PHY_CS_ACS_ALLOCATION_BIT3_2 DDR_REGDEF(0x10, 0x02, 0x1215) -#define PHY_CSLVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x1221) -#define PHY_CLK_DC_CAL_CLK_SEL DDR_REGDEF(0x08, 0x03, 0x123A) -#define PHY_FREQ_SEL_MULTICAST_EN DDR_REGDEF(0x08, 0x01, 0x1301) -#define PHY_FREQ_SEL_INDEX DDR_REGDEF(0x10, 0x02, 0x1301) -#define SC_PHY_MANUAL_UPDATE DDR_REGDEF(0x18, 0x01, 0x1304) -#define PHY_SET_DFI_INPUT_RST_PAD DDR_REGDEF(0x18, 0x01, 0x1311) -#define PHY_CAL_MODE_0 DDR_REGDEF(0x00, 0x0D, 0x132C) -#define PHY_CAL_INTERVAL_COUNT_0 DDR_REGDEF(0x00, 0x20, 0x132D) -#define PHY_DATA_BYTE_ORDER_SEL DDR_REGDEF(0x00, 0x20, 0x133E) -#define PHY_PAD_ACS_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1348) -#define PHY_PLL_CTRL DDR_REGDEF(0x00, 0x0E, 0x134B) -#define PHY_PLL_CTRL_8X DDR_REGDEF(0x10, 0x0E, 0x134B) -#define PHY_CAL_CLK_SELECT_0 DDR_REGDEF(0x00, 0x03, 0x1360) - -#define PI_START DDR_REGDEF(0x00, 0x01, 0x0800) -#define PI_TRAIN_ALL_FREQ_REQ DDR_REGDEF(0x18, 0x01, 0x0802) -#define PI_CS_MAP DDR_REGDEF(0x08, 0x02, 0x0813) -#define PI_WRLVL_REQ DDR_REGDEF(0x10, 0x01, 0x081C) -#define PI_WRLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x081C) -#define PI_RDLVL_REQ DDR_REGDEF(0x18, 0x01, 0x0824) -#define PI_RDLVL_GATE_REQ DDR_REGDEF(0x00, 0x01, 0x0825) -#define PI_RDLVL_CS_SW DDR_REGDEF(0x08, 0x02, 0x0825) -#define PI_RDLVL_PERIODIC DDR_REGDEF(0x08, 0x01, 0x082E) -#define PI_RDLVL_INTERVAL DDR_REGDEF(0x08, 0x10, 0x0835) -#define PI_DRAMDCA_FLIP_MASK DDR_REGDEF(0x08, 0x02, 0x083B) -#define PI_DRAMDCA_LVL_REQ DDR_REGDEF(0x10, 0x01, 0x083D) -#define PI_DCMLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x083D) -#define PI_WRDCM_LVL_EN_F1 DDR_REGDEF(0x00, 0x02, 0x083F) -#define PI_DRAMDCA_LVL_EN_F1 DDR_REGDEF(0x08, 0x02, 0x083F) -#define PI_WRDCM_LVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x083F) -#define PI_DRAMDCA_LVL_EN_F2 DDR_REGDEF(0x00, 0x02, 0x0840) -#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0868) -#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0869) -#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x086A) -#define PI_TCKCKEL_F2 DDR_REGDEF(0x18, 0x04, 0x089D) -#define PI_WDQLVL_VREF_EN DDR_REGDEF(0x08, 0x04, 0x089E) -#define PI_WDQLVL_PERIODIC DDR_REGDEF(0x00, 0x01, 0x08A0) -#define PI_WDQLVL_INTERVAL DDR_REGDEF(0x00, 0x10, 0x08A4) -#define PI_INT_STATUS DDR_REGDEF(0x00, 0x20, 0x0900) -#define PI_INT_ACK_0 DDR_REGDEF(0x00, 0x20, 0x0902) -#define PI_INT_ACK_1 DDR_REGDEF(0x00, 0x03, 0x0903) -#define PI_LONG_COUNT_MASK DDR_REGDEF(0x10, 0x05, 0x090F) -#define PI_ADDR_MUX_0 DDR_REGDEF(0x00, 0x03, 0x0910) -#define PI_ADDR_MUX_1 DDR_REGDEF(0x08, 0x03, 0x0910) -#define PI_ADDR_MUX_2 DDR_REGDEF(0x10, 0x03, 0x0910) -#define PI_ADDR_MUX_3 DDR_REGDEF(0x18, 0x03, 0x0910) -#define PI_ADDR_MUX_4 DDR_REGDEF(0x00, 0x03, 0x0911) -#define PI_ADDR_MUX_5 DDR_REGDEF(0x08, 0x03, 0x0911) -#define PI_ADDR_MUX_6 DDR_REGDEF(0x10, 0x03, 0x0911) -#define PI_DATA_BYTE_SWAP_EN DDR_REGDEF(0x18, 0x01, 0x0911) -#define PI_DATA_BYTE_SWAP_SLICE0 DDR_REGDEF(0x00, 0x01, 0x0912) -#define PI_DATA_BYTE_SWAP_SLICE1 DDR_REGDEF(0x08, 0x01, 0x0912) -#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) -#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) -#define PI_DLL_RST DDR_REGDEF(0x00, 0x01, 0x0941) -#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 DDR_REGDEF(0x00, 0x08, 0x0964) -#define PI_WRLAT_F2 DDR_REGDEF(0x10, 0x07, 0x096A) -#define PI_TWCKENL_WR_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x096A) -#define PI_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096B) -#define PI_TWCKPRE_STATIC_F2 DDR_REGDEF(0x08, 0x06, 0x096B) -#define PI_TWCKPRE_TOGGLE_RD_F2 DDR_REGDEF(0x18, 0x06, 0x096B) -#define PI_TWCKENL_FS_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096C) -#define PI_CASLAT_F2 DDR_REGDEF(0x08, 0x07, 0x096C) -#define PI_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x0971) -#define PI_TREF_F2 DDR_REGDEF(0x00, 0x14, 0x0972) -#define PI_TDFI_WRLVL_WW_F0 DDR_REGDEF(0x00, 0x0A, 0x0974) -#define PI_TDFI_WRLVL_WW_F1 DDR_REGDEF(0x00, 0x0A, 0x0975) -#define PI_WRLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x0975) -#define PI_TDFI_WRLVL_WW_F2 DDR_REGDEF(0x00, 0x0A, 0x0976) -#define PI_WRLVL_WCKOFF_F2 DDR_REGDEF(0x10, 0x08, 0x0976) -#define PI_RDLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x097A) -#define PI_RDLVL_GATE_EN_F2 DDR_REGDEF(0x00, 0x02, 0x097B) -#define PI_RDLVL_VREF_EN_F0 DDR_REGDEF(0x10, 0x04, 0x097B) -#define PI_RDLVL_VREF_EN_F1 DDR_REGDEF(0x00, 0x04, 0x097D) -#define PI_RDLVL_VREF_EN_F2 DDR_REGDEF(0x10, 0x04, 0x097E) -#define PI_RDLAT_ADJ_F2 DDR_REGDEF(0x00, 0x09, 0x0981) -#define PI_WRLAT_ADJ_F2 DDR_REGDEF(0x00, 0x07, 0x0982) -#define PI_TDFI_CALVL_CC_F2 DDR_REGDEF(0x00, 0x0A, 0x0985) -#define PI_TDFI_CALVL_CAPTURE_F2 DDR_REGDEF(0x10, 0x0A, 0x0985) -#define PI_CALVL_EN_F2 DDR_REGDEF(0x10, 0x02, 0x0986) -#define PI_TCAENT_F2 DDR_REGDEF(0x00, 0x0E, 0x0989) -#define PI_TVREF_SHORT_F2 DDR_REGDEF(0x00, 0x0A, 0x098F) -#define PI_TVREF_LONG_F2 DDR_REGDEF(0x10, 0x0A, 0x098F) -#define PI_TVRCG_ENABLE_F2 DDR_REGDEF(0x00, 0x0A, 0x0990) -#define PI_TVRCG_DISABLE_F2 DDR_REGDEF(0x10, 0x0A, 0x0990) -#define PI_CALVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x00, 0x07, 0x0991) -#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x08, 0x07, 0x0991) -#define PI_CALVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x18, 0x07, 0x0991) -#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x0992) -#define PI_CALVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x10, 0x07, 0x0992) -#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x18, 0x07, 0x0992) -#define PI_TDFI_CALVL_STROBE_F2 DDR_REGDEF(0x08, 0x04, 0x0995) -#define PI_TXP_F2 DDR_REGDEF(0x10, 0x05, 0x0995) -#define PI_TMRWCKEL_F2 DDR_REGDEF(0x18, 0x08, 0x0995) -#define PI_TCKEHDQS_F2 DDR_REGDEF(0x10, 0x06, 0x099D) -#define PI_TFC_F2 DDR_REGDEF(0x00, 0x0A, 0x099E) -#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x10, 0x07, 0x09A0) -#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x18, 0x07, 0x09A0) -#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x09A4) -#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x08, 0x07, 0x09A4) -#define PI_TDFI_WDQLVL_WR_F2 DDR_REGDEF(0x00, 0x0A, 0x09A6) -#define PI_TDFI_WDQLVL_RW_F2 DDR_REGDEF(0x10, 0x0A, 0x09A6) -#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x00, 0x07, 0x09A7) -#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x08, 0x07, 0x09A7) -#define PI_WDQLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x09A7) -#define PI_MBIST_RDLAT_ADJ_F2 DDR_REGDEF(0x08, 0x09, 0x09A8) -#define PI_MBIST_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x09A8) -#define PI_TRTP_F2 DDR_REGDEF(0x18, 0x08, 0x09B3) -#define PI_TRP_F2 DDR_REGDEF(0x00, 0x08, 0x09B4) -#define PI_TRCD_F2 DDR_REGDEF(0x08, 0x08, 0x09B4) -#define PI_TWTR_S_F2 DDR_REGDEF(0x18, 0x06, 0x09B4) -#define PI_TWTR_L_F2 DDR_REGDEF(0x00, 0x06, 0x09B5) -#define PI_TWTR_F2 DDR_REGDEF(0x10, 0x06, 0x09B5) -#define PI_TWR_F2 DDR_REGDEF(0x18, 0x08, 0x09B5) -#define PI_TRAS_MIN_F2 DDR_REGDEF(0x10, 0x09, 0x09B6) -#define PI_TDQSCK_MAX_F2 DDR_REGDEF(0x00, 0x04, 0x09B7) -#define PI_TSR_F2 DDR_REGDEF(0x10, 0x08, 0x09B7) -#define PI_TMRD_F2 DDR_REGDEF(0x18, 0x08, 0x09B7) -#define PI_TDFI_CTRLUPD_MAX_F2 DDR_REGDEF(0x00, 0x15, 0x09BC) -#define PI_TDFI_CTRLUPD_INTERVAL_F2 DDR_REGDEF(0x00, 0x20, 0x09BD) -#define PI_TINIT_F2 DDR_REGDEF(0x00, 0x18, 0x09CC) -#define PI_TINIT1_F2 DDR_REGDEF(0x00, 0x18, 0x09CD) -#define PI_TINIT3_F2 DDR_REGDEF(0x00, 0x18, 0x09CE) -#define PI_TINIT4_F2 DDR_REGDEF(0x00, 0x18, 0x09CF) -#define PI_TINIT5_F2 DDR_REGDEF(0x00, 0x18, 0x09D0) -#define PI_TXSNR_F2 DDR_REGDEF(0x00, 0x10, 0x09D1) -#define PI_TZQCAL_F2 DDR_REGDEF(0x10, 0x0C, 0x09D6) -#define PI_TZQLAT_F2 DDR_REGDEF(0x00, 0x07, 0x09D7) -#define PI_ZQRESET_F2 DDR_REGDEF(0x10, 0x0C, 0x09D8) -#define PI_TDQ72DQ_F2 DDR_REGDEF(0x10, 0x0A, 0x09DD) -#define PI_TCBTRTW_F2 DDR_REGDEF(0x00, 0x06, 0x09DE) -#define PI_MC_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x09E1) -#define PI_CKE_MUX_0 DDR_REGDEF(0x00, 0x03, 0x09E6) -#define PI_CKE_MUX_1 DDR_REGDEF(0x08, 0x03, 0x09E6) -#define PI_SEQ_DEC_SW_CS DDR_REGDEF(0x00, 0x02, 0x0A4E) -#define PI_SW_SEQ_START DDR_REGDEF(0x10, 0x01, 0x0A4E) -#define PI_SW_SEQ_0 DDR_REGDEF(0x00, 0x1B, 0x0BF1) -#define PI_SW_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0BF2) -#define PI_DFS_ENTRY_SEQ_0 DDR_REGDEF(0x00, 0x1D, 0x0BFB) -#define PI_DFS_INITIALIZATION_SEQ_1 DDR_REGDEF(0x00, 0x1D, 0x0C24) -#define PI_DFS_INITIALIZATION_SEQ_9 DDR_REGDEF(0x00, 0x1D, 0x0C2C) -#define PI_DFS_INITIALIZATION_SEQ_10 DDR_REGDEF(0x00, 0x1D, 0x0C2D) -#define PI_RDLVL_TRAIN_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0C42) -#define PI_RDLVL_TRAIN_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0C43) -#define PI_RDLVL_TRAIN_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0C44) -#define PI_RDLVL_TRAIN_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x0C45) -#define PI_RDLVL_TRAIN_SEQ_5 DDR_REGDEF(0x00, 0x1B, 0x0C46) -#define PI_SEQ_WAIT_16_F2 DDR_REGDEF(0x00, 0x18, 0x0C77) -#define PI_SEQ_WAIT_17_F2 DDR_REGDEF(0x00, 0x18, 0x0C7A) -#define PI_SEQ_WAIT_18_F2 DDR_REGDEF(0x00, 0x18, 0x0C7D) -#define PI_SEQ_WAIT_19_F2 DDR_REGDEF(0x00, 0x18, 0x0C80) -#define PI_SEQ_WAIT_20_F2 DDR_REGDEF(0x00, 0x18, 0x0C83) -#define PI_SEQ_WAIT_21_F2 DDR_REGDEF(0x00, 0x18, 0x0C86) -#define PI_SEQ_WAIT_22_F2 DDR_REGDEF(0x00, 0x18, 0x0C89) -#define PI_SEQ_WAIT_23_F2 DDR_REGDEF(0x00, 0x18, 0x0C8C) -#define PI_SEQ_WAIT_24_F2 DDR_REGDEF(0x00, 0x18, 0x0C8F) -#define PI_SEQ_WAIT_25_F2 DDR_REGDEF(0x00, 0x18, 0x0C92) -#define PI_SEQ_WAIT_26_F2 DDR_REGDEF(0x00, 0x18, 0x0C95) -#define PI_SEQ_WAIT_30_F2 DDR_REGDEF(0x00, 0x18, 0x0CA1) -#define PI_DARRAY3_0_CS0_F0 DDR_REGDEF(0x00, 0x08, 0x0D0B) -#define PI_DARRAY3_1_CS0_F0 DDR_REGDEF(0x08, 0x08, 0x0D0B) -#define PI_DARRAY3_0_CS0_F1 DDR_REGDEF(0x00, 0x08, 0x0D15) -#define PI_DARRAY3_1_CS0_F1 DDR_REGDEF(0x08, 0x08, 0x0D15) -#define PI_DARRAY3_0_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D1F) -#define PI_DARRAY3_1_CS0_F2 DDR_REGDEF(0x08, 0x08, 0x0D1F) -#define PI_DARRAY3_4_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D20) -#define PI_DARRAY3_20_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D24) -#define PI_DARRAY3_0_CS1_F0 DDR_REGDEF(0x00, 0x08, 0x0D29) -#define PI_DARRAY3_1_CS1_F0 DDR_REGDEF(0x08, 0x08, 0x0D29) -#define PI_DARRAY3_0_CS1_F1 DDR_REGDEF(0x00, 0x08, 0x0D33) -#define PI_DARRAY3_1_CS1_F1 DDR_REGDEF(0x08, 0x08, 0x0D33) -#define PI_DARRAY3_0_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3D) -#define PI_DARRAY3_1_CS1_F2 DDR_REGDEF(0x08, 0x08, 0x0D3D) -#define PI_DARRAY3_4_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3E) -#define PI_DARRAY3_20_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D42) - -/* The setting table of Data Slice for V4H */ -static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { - 0x30020370, 0x00000000, 0x01000002, 0x00000000, - 0x00000000, 0x00000000, 0x00010300, 0x04000100, - 0x00010000, 0x01000000, 0x00000000, 0x00000000, - 0x00010000, 0x08010000, 0x00022003, 0x00000000, - 0x040F0100, 0x1404034F, 0x04040102, 0x04040404, - 0x00000100, 0x00000000, 0x00000000, 0x000800C0, - 0x000F18FF, 0x00000000, 0x00000001, 0x00070000, - 0x0000AAAA, 0x00005555, 0x0000B5B5, 0x00004A4A, - 0x00005656, 0x0000A9A9, 0x0000A9A9, 0x0000B5B5, - 0x00000000, 0xBFBF0000, 0xCCCCF7F7, 0x00000000, - 0x00000000, 0x00000000, 0x00080815, 0x08040000, - 0x00000004, 0x00103000, 0x000C0040, 0x00200200, - 0x01010000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000020, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000004, 0x001F07FF, 0x08000303, - 0x10200080, 0x00000006, 0x00000401, 0x00000000, - 0x20CEC201, 0x00000001, 0x00017706, 0x01007706, - 0x00000000, 0x008D006D, 0x00100001, 0x03FF0100, - 0x00006E01, 0x00000301, 0x00000000, 0x00000000, - 0x00000000, 0x00500050, 0x00500050, 0x00500050, - 0x00500050, 0x0D000050, 0x10100004, 0x06102010, - 0x61619041, 0x07097000, 0x00644180, 0x00803280, - 0x00808001, 0x13010101, 0x02000016, 0x10001003, - 0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140, - 0x00000100, 0x000001D1, 0x05000068, 0x00030402, - 0x01400000, 0x80800300, 0x00160010, 0x76543210, - 0x00000008, 0x03010301, 0x03010301, 0x03010301, - 0x03010301, 0x03010301, 0x00000000, 0x00500050, - 0x00500050, 0x00500050, 0x00500050, 0x00500050, - 0x00500050, 0x00500050, 0x00500050, 0x00500050, - 0x00070087, 0x00000000, 0x08010007, 0x00000000, - 0x20202020, 0x20202020, 0x20202020, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000 -}; - -/* The setting table of Address Slice for V4H */ -static const u32 DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { - 0x00200030, 0x00200002, 0x76543210, 0x00010001, - 0x06543210, 0x03070000, 0x00001000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x0000807F, - 0x00000001, 0x00000003, 0x00000000, 0x000F0000, - 0x030C000F, 0x00020103, 0x0000000F, 0x00000100, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x02000400, 0x0000002A, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00200101, - 0x10002C03, 0x00000003, 0x00030240, 0x00008008, - 0x00081020, 0x01200000, 0x00010001, 0x00000000, - 0x00100302, 0x003E4208, 0x01400140, 0x01400140, - 0x01400140, 0x01400140, 0x00000100, 0x00000100, - 0x00000100, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00020580, 0x03000040, - 0x00000000 -}; - -/* The setting table of Address Control Slice for V4H */ -static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { - 0x00000000, 0x00000100, 0x00000001, 0x23800000, - 0x00000000, 0x01000101, 0x00000000, 0x00000001, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00040101, 0x00000000, 0x00000000, 0x00000064, - 0x00000000, 0x00000000, 0x39421B42, 0x00010124, - 0x00520052, 0x00000052, 0x00000000, 0x00000000, - 0x00010001, 0x00000000, 0x00000000, 0x00010001, - 0x00000000, 0x00000000, 0x00010001, 0x07030102, - 0x01030307, 0x00000054, 0x00004096, 0x08200820, - 0x08200820, 0x08200820, 0x08200820, 0x00000820, - 0x004103B8, 0x0000003F, 0x000C0006, 0x00000000, - 0x000004C0, 0x00007A12, 0x00000208, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x03000000, 0x00000000, 0x00000000, 0x04102002, - 0x00041020, 0x01C98C98, 0x3F400000, 0x003F3F3F, - 0x00000000, 0x00000000, 0x76543210, 0x00010198, - 0x00000007, 0x00000000, 0x00000000, 0x00000000, - 0x00000002, 0x00000000, 0x00000000, 0x00000000, - 0x01032380, 0x00000100, 0x00000000, 0x31421342, - 0x00308000, 0x00000080, 0x00063F77, 0x00000006, - 0x0000033F, 0x00000000, 0x0000033F, 0x00000000, - 0x0000033F, 0x00000000, 0x00033F00, 0x00CC0000, - 0x00033F77, 0x00000000, 0x00033F00, 0x00EE0000, - 0x00033F00, 0x00EE0000, 0x00033F00, 0x00EE0000, - 0x00200106 -}; - -/* The setting table of PI Register for V4H */ -static const u32 DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { - 0x00000D00, 0x00010100, 0x00640004, 0x00000001, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0xFFFFFFFF, 0x02010000, 0x00000003, 0x00000005, - 0x00000002, 0x00000000, 0x00000101, 0x0012080E, - 0x00000000, 0x001E2C0E, 0x00000000, 0x00030300, - 0x01010700, 0x00000001, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x01000000, 0x00002807, 0x00000000, 0x32000300, - 0x00000000, 0x00000000, 0x04022004, 0x01040100, - 0x00010000, 0x00000100, 0x000000AA, 0x00000055, - 0x000000B5, 0x0000004A, 0x00000056, 0x000000A9, - 0x000000A9, 0x000000B5, 0x00000000, 0x01000000, - 0x00030300, 0x0000001A, 0x000007D0, 0x00000300, - 0x00000000, 0x00000000, 0x01000000, 0x00000101, - 0x00000000, 0x00000000, 0x00000000, 0x00000200, - 0x03030300, 0x01000000, 0x00000000, 0x00000100, - 0x00000003, 0x001100EF, 0x01A1120B, 0x00051400, - 0x001A0700, 0x001101FC, 0x00011A00, 0x00000000, - 0x001F0000, 0x00000000, 0x00000000, 0x00051500, - 0x001103FC, 0x00011A00, 0x00051500, 0x001102FC, - 0x00011A00, 0x00001A00, 0x00000000, 0x001F0000, - 0x001100FC, 0x00011A00, 0x01A1120B, 0x001A0701, - 0x00000000, 0x001F0000, 0x00000000, 0x00000000, - 0x001100EF, 0x01A1120B, 0x00051400, 0x01910480, - 0x01821009, 0x001F0000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x001A0700, 0x01A11E14, - 0x001101FC, 0x00211A00, 0x00051500, 0x001103FC, - 0x00011A00, 0x00051500, 0x001102FC, 0x00011A00, - 0x00031A00, 0x001A0701, 0x00000000, 0x001F0000, - 0x00000000, 0x00000000, 0x01A11E14, 0x01A1120B, - 0x00000000, 0x001F0000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x001100FD, 0x00012E00, - 0x00051700, 0x01A1120B, 0x001A0701, 0x001F0000, - 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, - 0x00051400, 0x001A0700, 0x001102FD, 0x00012E00, - 0x00000000, 0x001F0000, 0x00000000, 0x00000000, - 0x00070700, 0x00000000, 0x01000000, 0x00000300, - 0x17030000, 0x00000000, 0x00000000, 0x00000000, - 0x0A0A140A, 0x10020201, 0x332A0002, 0x01010000, - 0x0B000404, 0x04030308, 0x00010100, 0x02020301, - 0x01001000, 0x00000034, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x55AA55AA, 0x33CC33CC, - 0x0FF00FF0, 0x0F0FF0F0, 0x00008E38, 0x00000001, - 0x00000002, 0x00020001, 0x00020001, 0x02010201, - 0x0000000F, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0xAAAAA593, - 0xA5939999, 0x00000000, 0x00005555, 0x00003333, - 0x0000CCCC, 0x00000000, 0x0003FFFF, 0x00003333, - 0x0000CCCC, 0x00000000, 0x036DB6DB, 0x00249249, - 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x036DB6DB, 0x00249249, - 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x01000000, 0x00000100, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00010000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00010000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00080000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x01180400, - 0x03020100, 0x00060504, 0x00010100, 0x00000008, - 0x00080000, 0x00000001, 0x00000000, 0x0001AA00, - 0x00000100, 0x00000000, 0x00010000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00020000, 0x00000100, 0x00010000, 0x0000000B, - 0x0000001C, 0x00000100, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x03010000, 0x01000100, - 0x01020001, 0x00010300, 0x05000104, 0x01060001, - 0x00010700, 0x00000000, 0x00000000, 0x00010000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000301, 0x00000000, 0x00000000, 0x01010000, - 0x00000000, 0x00000200, 0x00000000, 0xB8000000, - 0x010000FF, 0x0000FFE8, 0x00FFA801, 0xFFD80100, - 0x00007F10, 0x00000000, 0x00000034, 0x0000003D, - 0x00020079, 0x02000200, 0x02000204, 0x06000C06, - 0x04040200, 0x04100804, 0x14090004, 0x1C081024, - 0x0000120C, 0x00000015, 0x000000CF, 0x00000026, - 0x0000017F, 0x00000130, 0x04000C2E, 0x00000404, - 0x01080032, 0x01080032, 0x000F0032, 0x00000000, - 0x00000000, 0x00000000, 0x00010300, 0x00010301, - 0x03030000, 0x00000001, 0x00010303, 0x00030000, - 0x0013000C, 0x0A060037, 0x03030526, 0x000C0032, - 0x0017003D, 0x0025004B, 0x00010101, 0x0000000E, - 0x00000019, 0x010000C8, 0x000F000F, 0x0007000C, - 0x001A0100, 0x0015001A, 0x0100000B, 0x00C900C9, - 0x005100A1, 0x29003329, 0x33290033, 0x0A070600, - 0x0A07060D, 0x0D09070D, 0x000C000D, 0x00001000, - 0x00000C00, 0x00001000, 0x00000C00, 0x02001000, - 0x0002000E, 0x00160019, 0x1E1A00C8, 0x00100004, - 0x361C0008, 0x00000000, 0x0000000C, 0x0006000C, - 0x0300361C, 0x04001300, 0x000D0019, 0x0000361C, - 0x20003300, 0x00000000, 0x02000000, 0x04040802, - 0x00060404, 0x0003C34F, 0x05022001, 0x0203000A, - 0x04040408, 0xC34F0604, 0x10010005, 0x040A0502, - 0x0A080F11, 0x1C0A040A, 0x0022C34F, 0x0C0C1002, - 0x00019E0A, 0x0000102C, 0x000002FE, 0x00001DEC, - 0x0000185C, 0x0000F398, 0x04000400, 0x03030400, - 0x002AF803, 0x00002AF8, 0x0000D6D7, 0x00000003, - 0x0000006E, 0x00000016, 0x00004E20, 0x00004E20, - 0x00030D40, 0x00000005, 0x000000C8, 0x00000027, - 0x00027100, 0x00027100, 0x00186A00, 0x00000028, - 0x00000640, 0x01000136, 0x00530040, 0x00010004, - 0x00960040, 0x00010004, 0x04B00040, 0x00000318, - 0x00280005, 0x05040404, 0x00070603, 0x06030503, - 0x0503000D, 0x00640603, 0x06040608, 0x00040604, - 0x00260015, 0x01050130, 0x01000100, 0x00020201, - 0x04040000, 0x01010104, 0x03020302, 0x00000100, - 0x02020101, 0x00000000, 0x09910260, 0x11911600, - 0x19A21009, 0x19A10100, 0x19A10201, 0x19A10302, - 0x19A10A03, 0x19A10B04, 0x19A10C05, 0x19A10E07, - 0x19A10F08, 0x19A1110A, 0x19A1120B, 0x19A1130C, - 0x19A1140D, 0x19A00C00, 0x199F0000, 0x199F0000, - 0x199F0000, 0x199F0000, 0x01910300, 0x01A21009, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x001140BF, 0x01811009, 0x01850400, 0x01A10C05, - 0x01850300, 0x01A10C11, 0x01850300, 0x001100BF, - 0x01811009, 0x01850500, 0x019F0000, 0x019F0000, - 0x01510001, 0x01D102A0, 0x01E21009, 0x00051900, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x01510001, - 0x01D10290, 0x01E21009, 0x01510001, 0x01D10000, - 0x01E21009, 0x00051800, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x0011008F, 0x00910000, - 0x01811009, 0x01910040, 0x01A21009, 0x019F0000, - 0x01911000, 0x01A21009, 0x01A10100, 0x01A10201, - 0x01A10302, 0x01A10A03, 0x01A10B04, 0x01A10C05, - 0x01A10E07, 0x01A10F08, 0x01A1110A, 0x01A1120B, - 0x01A1130C, 0x01A1140D, 0x01A00C00, 0x01910800, - 0x01A21009, 0x019F0000, 0x019F0000, 0x019F0000, - 0x0101017F, 0x00010101, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x01000000, 0x01000101, - 0x00000000, 0x00000000, 0x00050000, 0x00070100, - 0x000F0200, 0x00000000, 0x01A10100, 0x01A10201, - 0x01A10302, 0x01A00B04, 0x00210D06, 0x01A1110A, - 0x01A1140D, 0x00098000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, - 0x019F0000, 0x019F0000, 0x01A10100, 0x01A10201, - 0x01A10302, 0x01A10A03, 0x01A10B04, 0x00210D06, - 0x01A1110A, 0x00000000, 0x01A1140D, 0x00000000, - 0x00000000, 0x00000000, 0x01A1120B, 0x000A0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x000A0000, 0x01061300, - 0x00000000, 0x00000000, 0x00061180, 0x000612C0, - 0x00000000, 0x00000000, 0x001F0000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x01811009, 0x0011EFAF, - 0x01A1120B, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001100BF, - 0x01A1120B, 0x080D0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x080C0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0200, 0x001F0200, - 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, - 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, - 0x001F0200, 0x001F0200, 0x001100EF, 0x01A1120B, - 0x001F0000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x01A1120B, 0x001F0000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, - 0x001F0000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00211F14, 0x00212014, - 0x00212116, 0x00212217, 0x001F0000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x001A85FF, 0x00051E00, 0x001F0000, 0x00000000, - 0x00211F14, 0x00212015, 0x00212116, 0x00212217, - 0x01A1120B, 0x001F0000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x0031FFBF, 0x01A11009, - 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, - 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x0031FFBF, 0x01A11009, - 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, - 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x08084340, 0x0011FFFF, - 0x2011FFFB, 0x00012E00, 0x001100EF, 0x01A1120B, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x083E4340, 0x00212E00, - 0x01A1120B, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x003F0000, 0x08201020, - 0x28100020, 0x08083020, 0x08400020, 0x08402020, - 0x08483020, 0x10083020, 0x20180020, 0x30480020, - 0x78880020, 0x488010E0, 0x494B0000, 0x49089080, - 0x49080000, 0x490011C0, 0x0A000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x08000020, 0x08000020, 0x08000020, 0x08000020, - 0x001100FF, 0x01810302, 0x001100DF, 0x00010D06, - 0x001100EF, 0x01A1120B, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x00010D06, 0x01810302, 0x0181160E, 0x001F0000, - 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, - 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, - 0x00051B00, 0x001F13FF, 0x081A52FD, 0x001A12FF, - 0x00051A00, 0x001A13FF, 0x00051B00, 0x001F13FF, - 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, - 0x00051B00, 0x001F13FF, 0x00032300, 0x00032400, - 0x001F0000, 0x001F0000, 0x00800000, 0x0031FFBF, - 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, - 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x00800000, 0x0031FFBF, - 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, - 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, - 0x003F0000, 0x003F0000, 0x081100DF, 0x08010D06, - 0x0011000F, 0x0181160E, 0x001100EF, 0x01A1120B, - 0x001F0000, 0x001F0000, 0x001F0000, 0x009C0000, - 0x08010D06, 0x0181160E, 0x01A1120B, 0x001F0000, - 0x001F0000, 0x001F0000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x11910048, - 0x09910060, 0x19A21009, 0x19A10100, 0x19A10201, - 0x19A10302, 0x19A10A03, 0x19A10B04, 0x18051C00, - 0x19A1110A, 0x19A1120B, 0x19A1130C, 0x19A1140D, - 0x19A1160E, 0x181140BF, 0x19A11009, 0x19A10C05, - 0x19A00C00, 0x19A10E07, 0x19A10F08, 0x19910280, - 0x19A21009, 0x18051000, 0x18861101, 0x181F0000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18861100, - 0x19A11009, 0x101B0001, 0x181B0100, 0x18000500, - 0x181B0200, 0x00000000, 0x181B0600, 0x181B0C00, - 0x181B0100, 0x181B0200, 0x181B0300, 0x181B0400, - 0x181F0000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x18000000, 0x18000000, 0x18000000, - 0x18000000, 0x004B1040, 0x001011C0, 0x00089080, - 0x000811C0, 0x040811C0, 0x02000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x5F407FAA, - 0x007B776F, 0x4AB555AA, 0xB5A9A956, 0x9F80BFAA, - 0x00BBB7AF, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00002AF8, 0x0000D6D7, 0x0000006E, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x0000000E, 0x00000019, 0x000000C8, - 0x00000001, 0x00000001, 0x00000003, 0x00000007, - 0x00000007, 0x00000009, 0x00000001, 0x00000001, - 0x00000003, 0x00000001, 0x00000001, 0x00000003, - 0x0000006E, 0x000000C8, 0x00000640, 0x00000001, - 0x00000001, 0x00000003, 0x00000002, 0x00000004, - 0x0000001C, 0x00000007, 0x0000000B, 0x00000051, - 0x0000000C, 0x00000015, 0x000000A1, 0x00000003, - 0x00000000, 0x0000000C, 0x00000000, 0x00000000, - 0x00000000, 0x0000000F, 0x0000000F, 0x0000000F, - 0x00002AF9, 0x00002AF9, 0x00002AF9, 0x00000034, - 0x0000001E, 0x0000003C, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x000000C0, 0x00000000, 0x00000000, 0x55550000, - 0x00003C5A, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000, 0x00000000, 0x00000000, 0x00D60000, - 0x50005000, 0x803E0050, 0x00000200, 0x00000000, - 0x00000000, 0x00007800, 0x00000000, 0x00000000, - 0x00000000, 0x00C61110, 0x2C002834, 0x0C06002C, - 0x00000200, 0x00000000, 0x00000000, 0x00007800, - 0x00000000, 0x00000000, 0x00000000, 0x00C6BBB0, - 0x2C002834, 0x0C06002C, 0x00000200, 0x00000000, - 0x00000000, 0x00007800, 0x00000000, 0x00000000, - 0x00000000, 0x00D60000, 0x50005000, 0x803E0050, - 0x00000200, 0x00000000, 0x00000000, 0x00007800, - 0x00000000, 0x00000000, 0x00000000, 0x00C61110, - 0x2C002834, 0x082E002C, 0x00000200, 0x00000000, - 0x00000000, 0x00007800, 0x00000000, 0x00000000, - 0x00000000, 0x00C6BBB0, 0x2C002834, 0x082E002C, - 0x00000200, 0x00000000, 0x00000000, 0x00007800, - 0x00000000, 0x00000000, 0x00000000, 0x80808080, - 0x800D8080, 0x80808080, 0x17808080, 0x80808025, - 0x2221201F, 0x80808080, 0x80808080, 0x80808080, - 0x80808080, 0x80808080, 0x80808080, 0x80808080, - 0x80808080, 0x80808080, 0x80808080, 0x80808080, - 0x80808080, 0x80808080, 0x80808080, 0x0A030201, - 0x0E800C0B, 0x1211100F, 0x80161413, 0x08004C80, - 0x8080801E, 0x80804E80, 0x80808080, 0x80808080, - 0x80808080 -}; - -struct dbsc5_table_patch { - const u32 reg; - const u32 val; -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_3200[] = { - { PHY_REGULATOR_EN_CNT, 0x10 }, - { PHY_RX_CAL_ALL_DLY, 0x07 }, - { PHY_RDDATA_EN_TSEL_DLY, 0x08 }, - { PHY_RDDATA_EN_OE_DLY, 0x0B }, - { PHY_RPTR_UPDATE, 0x07 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x25 }, - { PHY_RDLVL_MAX_EDGE, 0x012D }, - { PHY_RDDATA_EN_DLY, 0x0B }, - { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0x05 }, - { PHY_GTLVL_LAT_ADJ_START, 0x03 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3200[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_3200[] = { - { PI_TCKCKEL_F2, 0x03 }, - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57 }, - { PI_TREF_F2, 0x613 }, - { PI_TDFI_WRLVL_WW_F0, 0x2B }, - { PI_TDFI_WRLVL_WW_F1, 0x2B }, - { PI_TDFI_WRLVL_WW_F2, 0x2B }, - { PI_RDLAT_ADJ_F2, 0x22 }, - { PI_TDFI_CALVL_CAPTURE_F2, 0x1D }, - { PI_TDFI_CALVL_CC_F2, 0x43 }, - { PI_TVRCG_ENABLE_F2, 0x51 }, - { PI_TVRCG_DISABLE_F2, 0x29 }, - { PI_TXP_F2, 0x07 }, - { PI_TMRWCKEL_F2, 0x0A }, - { PI_TDFI_CALVL_STROBE_F2, 0x06 }, - { PI_TFC_F2, 0x64 }, - { PI_TCKEHDQS_F2, 0x12 }, - { PI_TDFI_WDQLVL_RW_F2, 0x09 }, - { PI_TDFI_WDQLVL_WR_F2, 0x10 }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, - { PI_MBIST_RDLAT_ADJ_F2, 0x1E }, - { PI_TWTR_S_F2, 0x05 }, - { PI_TWTR_L_F2, 0x05 }, - { PI_TWTR_F2, 0x05 }, - { PI_TWR_F2, 0x0E }, - { PI_TDQSCK_MAX_F2, 0x01 }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x0C26 }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797C }, - { PI_TXSNR_F2, 0x9B }, - { PI_ZQRESET_F2, 0x0014 }, - { PI_TCBTRTW_F2, 0x04 }, - { PI_SEQ_WAIT_16_F2, 0x000064 }, - { PI_SEQ_WAIT_17_F2, 0x000002 }, - { PI_SEQ_WAIT_18_F2, 0x000007 }, - { PI_SEQ_WAIT_19_F2, 0x000002 }, - { PI_SEQ_WAIT_20_F2, 0x000002 }, - { PI_SEQ_WAIT_21_F2, 0x000320 }, - { PI_SEQ_WAIT_22_F2, 0x000002 }, - { PI_SEQ_WAIT_23_F2, 0x00000E }, - { PI_SEQ_WAIT_24_F2, 0x000029 }, - { PI_SEQ_WAIT_25_F2, 0x000051 }, - { PI_SEQ_WAIT_26_F2, 0x000003 }, - { PI_SEQ_WAIT_30_F2, 0x00002B }, - { PI_WRDCM_LVL_EN_F1, 0x00 }, - { PI_WRDCM_LVL_EN_F2, 0x00 }, - { PI_DRAMDCA_LVL_EN_F1, 0x00 }, - { PI_DRAMDCA_LVL_EN_F2, 0x00 }, - { PI_TINIT_F2, 0x013880 }, - { PI_TINIT1_F2, 0x013880 }, - { PI_TINIT3_F2, 0x0C3500 }, - { PI_TINIT4_F2, 0x000014 }, - { PI_TINIT5_F2, 0x000320 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_3733[] = { - { PHY_REGULATOR_EN_CNT, 0x13 }, - { PHY_RX_CAL_ALL_DLY, 0x08 }, - { PHY_RDDATA_EN_TSEL_DLY, 0x0A }, - { PHY_RDDATA_EN_OE_DLY, 0x0D }, - { PHY_RPTR_UPDATE, 0x08 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x2A }, - { PHY_RDLVL_MAX_EDGE, 0x0149 }, - { PHY_RDDATA_EN_DLY, 0x0D }, - { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0x9C }, - { PHY_GTLVL_LAT_ADJ_START, 0x04 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3733[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_3733[] = { - { PI_TCKCKEL_F2, 0x03 }, - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5B }, - { PI_TREF_F2, 0x717 }, - { PI_TDFI_WRLVL_WW_F0, 0x2C }, - { PI_TDFI_WRLVL_WW_F1, 0x2C }, - { PI_TDFI_WRLVL_WW_F2, 0x2C }, - { PI_RDLAT_ADJ_F2, 0x24 }, - { PI_TDFI_CALVL_CAPTURE_F2, 0x1F }, - { PI_TDFI_CALVL_CC_F2, 0x45 }, - { PI_TVRCG_ENABLE_F2, 0x5F }, - { PI_TVRCG_DISABLE_F2, 0x30 }, - { PI_TXP_F2, 0x07 }, - { PI_TMRWCKEL_F2, 0x0A }, - { PI_TDFI_CALVL_STROBE_F2, 0x06 }, - { PI_TFC_F2, 0x75 }, - { PI_TCKEHDQS_F2, 0x13 }, - { PI_TDFI_WDQLVL_RW_F2, 0x09 }, - { PI_TDFI_WDQLVL_WR_F2, 0x12 }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, - { PI_MBIST_RDLAT_ADJ_F2, 0x20 }, - { PI_TWTR_S_F2, 0x06 }, - { PI_TWTR_L_F2, 0x06 }, - { PI_TWTR_F2, 0x06 }, - { PI_TWR_F2, 0x10 }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x0E2E }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCC }, - { PI_TXSNR_F2, 0xB5 }, - { PI_ZQRESET_F2, 0x0018 }, - { PI_TCBTRTW_F2, 0x05 }, - { PI_SEQ_WAIT_16_F2, 0x000075 }, - { PI_SEQ_WAIT_17_F2, 0x000002 }, - { PI_SEQ_WAIT_18_F2, 0x000007 }, - { PI_SEQ_WAIT_19_F2, 0x000002 }, - { PI_SEQ_WAIT_20_F2, 0x000002 }, - { PI_SEQ_WAIT_21_F2, 0x0003A6 }, - { PI_SEQ_WAIT_22_F2, 0x000002 }, - { PI_SEQ_WAIT_23_F2, 0x000011 }, - { PI_SEQ_WAIT_24_F2, 0x000030 }, - { PI_SEQ_WAIT_25_F2, 0x00005F }, - { PI_SEQ_WAIT_26_F2, 0x000005 }, - { PI_SEQ_WAIT_30_F2, 0x00002D }, - { PI_TINIT_F2, 0x016C90 }, - { PI_TINIT1_F2, 0x016C90 }, - { PI_TINIT3_F2, 0x0E3D98 }, - { PI_TINIT4_F2, 0x000018 }, - { PI_TINIT5_F2, 0x0003A6 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_4266[] = { - { PHY_REGULATOR_EN_CNT, 0x16 }, - { PHY_RX_CAL_ALL_DLY, 0x09 }, - { PHY_RDDATA_EN_TSEL_DLY, 0x0B }, - { PHY_RDDATA_EN_OE_DLY, 0x0E }, - { PHY_RPTR_UPDATE, 0x08 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x2E }, - { PHY_RDLVL_MAX_EDGE, 0x0164 }, - { PHY_RDDATA_EN_DLY, 0x0E }, - { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0x30 }, - { PHY_GTLVL_LAT_ADJ_START, 0x04 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4266[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_4266[] = { - { PI_TCKCKEL_F2, 0x03 }, - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64 }, - { PI_TREF_F2, 0x81C }, - { PI_TDFI_WRLVL_WW_F0, 0x2D }, - { PI_TDFI_WRLVL_WW_F1, 0x2D }, - { PI_TDFI_WRLVL_WW_F2, 0x2D }, - { PI_RDLAT_ADJ_F2, 0x2B }, - { PI_TDFI_CALVL_CAPTURE_F2, 0x20 }, - { PI_TDFI_CALVL_CC_F2, 0x46 }, - { PI_TVRCG_ENABLE_F2, 0x6C }, - { PI_TVRCG_DISABLE_F2, 0x37 }, - { PI_TXP_F2, 0x07 }, - { PI_TMRWCKEL_F2, 0x0A }, - { PI_TFC_F2, 0x86 }, - { PI_TCKEHDQS_F2, 0x14 }, - { PI_TDFI_WDQLVL_RW_F2, 0x0B }, - { PI_TDFI_WDQLVL_WR_F2, 0x13 }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14 }, - { PI_MBIST_RDLAT_ADJ_F2, 0x27 }, - { PI_TWTR_S_F2, 0x07 }, - { PI_TWTR_L_F2, 0x07 }, - { PI_TWTR_F2, 0x07 }, - { PI_TWR_F2, 0x13 }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x1038 }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230 }, - { PI_TXSNR_F2, 0xCF }, - { PI_ZQRESET_F2, 0x001B }, - { PI_TCBTRTW_F2, 0x06 }, - { PI_SEQ_WAIT_16_F2, 0x000086 }, - { PI_SEQ_WAIT_17_F2, 0x000002 }, - { PI_SEQ_WAIT_18_F2, 0x000007 }, - { PI_SEQ_WAIT_19_F2, 0x000002 }, - { PI_SEQ_WAIT_20_F2, 0x000002 }, - { PI_SEQ_WAIT_21_F2, 0x00042B }, - { PI_SEQ_WAIT_22_F2, 0x000002 }, - { PI_SEQ_WAIT_23_F2, 0x000013 }, - { PI_SEQ_WAIT_24_F2, 0x000037 }, - { PI_SEQ_WAIT_25_F2, 0x00006C }, - { PI_SEQ_WAIT_26_F2, 0x000006 }, - { PI_SEQ_WAIT_30_F2, 0x000032 }, - { PI_TINIT_F2, 0x01A0AB }, - { PI_TINIT1_F2, 0x01A0AB }, - { PI_TINIT3_F2, 0x1046AB }, - { PI_TINIT4_F2, 0x00001B }, - { PI_TINIT5_F2, 0x00042B } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_4800[] = { - { PHY_REGULATOR_EN_CNT, 0x18 }, - { PHY_RX_CAL_ALL_DLY, 0x0A }, - { PHY_RDDATA_EN_TSEL_DLY, 0x0D }, - { PHY_RDDATA_EN_OE_DLY, 0x10 }, - { PHY_RPTR_UPDATE, 0x08 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x31 }, - { PHY_RDLVL_MAX_EDGE, 0x017F }, - { PHY_RDDATA_EN_DLY, 0x10 }, - { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6 }, - { PHY_GTLVL_LAT_ADJ_START, 0x05 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4800[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_4800[] = { - { PI_TCKCKEL_F2, 0x03 }, - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68 }, - { PI_RDLAT_ADJ_F2, 0x2D }, - { PI_TREF_F2, 0x920 }, - { PI_TDFI_WRLVL_WW_F0, 0x2E }, - { PI_TDFI_WRLVL_WW_F1, 0x2E }, - { PI_TDFI_WRLVL_WW_F2, 0x2E }, - { PI_TDFI_CALVL_CAPTURE_F2, 0x21 }, - { PI_TDFI_CALVL_CC_F2, 0x47 }, - { PI_TVRCG_DISABLE_F2, 0x3D }, - { PI_TVRCG_ENABLE_F2, 0x79 }, - { PI_TXP_F2, 0x08 }, - { PI_TMRWCKEL_F2, 0x0A }, - { PI_TCKEHDQS_F2, 0x14 }, - { PI_TFC_F2, 0x96 }, - { PI_TDFI_WDQLVL_RW_F2, 0x0B }, - { PI_TDFI_WDQLVL_WR_F2, 0x15 }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18 }, - { PI_MBIST_RDLAT_ADJ_F2, 0x29 }, - { PI_TWTR_S_F2, 0x08 }, - { PI_TWR_F2, 0x15 }, - { PI_TWTR_F2, 0x08 }, - { PI_TWTR_L_F2, 0x08 }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x1240 }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680 }, - { PI_TXSNR_F2, 0x0E9 }, - { PI_ZQRESET_F2, 0x001E }, - { PI_TCBTRTW_F2, 0x06 }, - { PI_SEQ_WAIT_16_F2, 0x000096 }, - { PI_SEQ_WAIT_17_F2, 0x000002 }, - { PI_SEQ_WAIT_18_F2, 0x000008 }, - { PI_SEQ_WAIT_19_F2, 0x000002 }, - { PI_SEQ_WAIT_20_F2, 0x000002 }, - { PI_SEQ_WAIT_21_F2, 0x0004B0 }, - { PI_SEQ_WAIT_22_F2, 0x000002 }, - { PI_SEQ_WAIT_23_F2, 0x000015 }, - { PI_SEQ_WAIT_24_F2, 0x00003D }, - { PI_SEQ_WAIT_25_F2, 0x000079 }, - { PI_SEQ_WAIT_26_F2, 0x000008 }, - { PI_SEQ_WAIT_30_F2, 0x000034 }, - { PI_TINIT_F2, 0x01D4A9 }, - { PI_TINIT1_F2, 0x01D4A9 }, - { PI_TINIT3_F2, 0x124E91 }, - { PI_TINIT4_F2, 0x00001E }, - { PI_TINIT5_F2, 0x0004B0 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_5500[] = { - { PHY_REGULATOR_EN_CNT, 0x1C }, - { PHY_RX_CAL_ALL_DLY, 0x0C }, - { PHY_RDDATA_EN_TSEL_DLY, 0x10 }, - { PHY_RDDATA_EN_OE_DLY, 0x13 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x37 }, - { PHY_RDLVL_MAX_EDGE, 0x01A3 }, - { PHY_RDDATA_EN_DLY, 0x13 }, - { PHY_RDDQS_LATENCY_ADJUST, 0x06 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0x8F }, - { PHY_GTLVL_LAT_ADJ_START, 0x06 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_5500[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_5500[] = { - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71 }, - { PI_RDLAT_ADJ_F2, 0x32 }, - { PI_TREF_F2, 0xA79 }, - { PI_TDFI_WRLVL_WW_F0, 0x30 }, - { PI_TDFI_WRLVL_WW_F1, 0x30 }, - { PI_TDFI_WRLVL_WW_F2, 0x30 }, - { PI_TDFI_CALVL_CAPTURE_F2, 0x23 }, - { PI_TDFI_CALVL_CC_F2, 0x49 }, - { PI_TVRCG_DISABLE_F2, 0x46 }, - { PI_TVRCG_ENABLE_F2, 0x8B }, - { PI_TMRWCKEL_F2, 0x0B }, - { PI_TCKEHDQS_F2, 0x15 }, - { PI_TFC_F2, 0xAD }, - { PI_TDFI_WDQLVL_RW_F2, 0x0C }, - { PI_TDFI_WDQLVL_WR_F2, 0x17 }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, - { PI_MBIST_RDLAT_ADJ_F2, 0x2E }, - { PI_TWTR_S_F2, 0x09 }, - { PI_TWR_F2, 0x18 }, - { PI_TWTR_F2, 0x09 }, - { PI_TWTR_L_F2, 0x09 }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x14F2 }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174 }, - { PI_TXSNR_F2, 0x10B }, - { PI_ZQRESET_F2, 0x0023 }, - { PI_TCBTRTW_F2, 0x07 }, - { PI_SEQ_WAIT_16_F2, 0x0000AD }, - { PI_SEQ_WAIT_21_F2, 0x000561 }, - { PI_SEQ_WAIT_23_F2, 0x000019 }, - { PI_SEQ_WAIT_24_F2, 0x000046 }, - { PI_SEQ_WAIT_25_F2, 0x00008B }, - { PI_SEQ_WAIT_26_F2, 0x00000A }, - { PI_SEQ_WAIT_30_F2, 0x000038 }, - { PI_TINIT_F2, 0x0219AF }, - { PI_TINIT1_F2, 0x0219AF }, - { PI_TINIT3_F2, 0x1500CF }, - { PI_TINIT4_F2, 0x000023 }, - { PI_TINIT5_F2, 0x000561 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_6000[] = { - { PHY_REGULATOR_EN_CNT, 0x1F }, - { PHY_RDDATA_EN_TSEL_DLY, 0x12 }, - { PHY_RDDATA_EN_OE_DLY, 0x15 }, - { PHY_WRLVL_RESP_WAIT_CNT, 0x3A }, - { PHY_RDLVL_MAX_EDGE, 0x01BD }, - { PHY_RDDATA_EN_DLY, 0x15 }, - { PHY_RDDQS_LATENCY_ADJUST, 0x07 }, - { PHY_RDDQS_GATE_SLAVE_DELAY, 0x1B }, - { PHY_GTLVL_LAT_ADJ_START, 0x06 }, - { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_6000[] = { - { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, - { PHY_ADR_CALVL_DLY_STEP, 0x02 } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_pi_6000[] = { - { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75 }, - { PI_RDLAT_ADJ_F2, 0x34 }, - { PI_TREF_F2, 0xB6B }, - { PI_TDFI_WRLVL_WW_F0, 0x31 }, - { PI_TDFI_WRLVL_WW_F1, 0x31 }, - { PI_TDFI_WRLVL_WW_F2, 0x31 }, - { PI_TVRCG_DISABLE_F2, 0x4D }, - { PI_TVRCG_ENABLE_F2, 0x98 }, - { PI_TMRWCKEL_F2, 0x0C }, - { PI_TFC_F2, 0xBC }, - { PI_TDFI_WDQLVL_RW_F2, 0x0C }, - { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, - { PI_MBIST_RDLAT_ADJ_F2, 0x30 }, - { PI_TWR_F2, 0x1A }, - { PI_TDFI_CTRLUPD_MAX_F2, 0x16D6 }, - { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45C }, - { PI_TXSNR_F2, 0x123 }, - { PI_ZQRESET_F2, 0x0026 }, - { PI_SEQ_WAIT_16_F2, 0x0000BC }, - { PI_SEQ_WAIT_21_F2, 0x0005DD }, - { PI_SEQ_WAIT_23_F2, 0x00001B }, - { PI_SEQ_WAIT_24_F2, 0x00004D }, - { PI_SEQ_WAIT_25_F2, 0x000098 }, - { PI_SEQ_WAIT_30_F2, 0x00003A }, - { PI_TINIT_F2, 0x024A16 }, - { PI_TINIT1_F2, 0x024A16 }, - { PI_TINIT3_F2, 0x16E4D8 }, - { PI_TINIT4_F2, 0x000026 }, - { PI_TINIT5_F2, 0x0005DD } -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_640 = { - PHY_DATA_DC_CAL_CLK_SEL, 0x05 -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_mbpsdiv_640 = { - PHY_CLK_DC_CAL_CLK_SEL, 0x04 -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_640 = { - PHY_CAL_CLK_SELECT_0, 0x05 -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = { - PHY_RX_PCLK_CLK_SEL, 0x3 -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = { - PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02 -}; - -static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = { - { PHY_PLL_CTRL, 0x1542 }, - { PHY_PLL_CTRL_8X, 0x3342 } -}; - -/* Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set */ -static const u32 PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = { - { PI_DARRAY3_0_CS0_F0, PI_DARRAY3_0_CS0_F1, PI_DARRAY3_0_CS0_F2 }, - { PI_DARRAY3_0_CS1_F0, PI_DARRAY3_0_CS1_F1, PI_DARRAY3_0_CS1_F2 } -}; - -/* Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set */ -static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = { - { PI_DARRAY3_1_CS0_F0, PI_DARRAY3_1_CS0_F1, PI_DARRAY3_1_CS0_F2 }, - { PI_DARRAY3_1_CS1_F0, PI_DARRAY3_1_CS1_F1, PI_DARRAY3_1_CS1_F2 } -}; - -/* DBSC registers */ -#define DBSC_DBSYSCONF0 0x0 -#define DBSC_DBSYSCONF1 0x0 -#define DBSC_DBSYSCONF1A 0x4 -#define DBSC_DBSYSCONF2 0x4 -#define DBSC_DBPHYCONF0 0x8 -#define DBSC_DBSYSCONF2A 0x8 -#define DBSC_DBMEMKIND 0x20 -#define DBSC_DBMEMKINDA 0x20 -#define DBSC_DBMEMCONF(ch, cs) (0x30 + (0x2000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) -#define DBSC_DBMEMCONFA(ch, cs) (0x30 + (0x4000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) -#define DBSC_DBSYSCNT0 0x100 -#define DBSC_DBSYSCNT0A 0x100 -#define DBSC_DBACEN 0x200 -#define DBSC_DBRFEN 0x204 -#define DBSC_DBCMD 0x208 -#define DBSC_DBCMD_CMD_OPCODE_PD 0x8 -#define DBSC_DBCMD_CMD_OPCODE_MRW 0xe -#define DBSC_DBCMD_CMD_OPCODE_MRR 0xf -#define DBSC_DBCMD_CMD_CHANNEL_ALL 0x8 -#define DBSC_DBCMD_CMD_RANK_ALL 0x4 -#define DBSC_DBWAIT 0x210 -#define DBSC_DBBL 0x400 -#define DBSC_DBBLA 0x400 -#define DBSC_DBRFCNF1 0x414 -#define DBSC_DBRFCNF2 0x418 -#define DBSC_DBCALCNF 0x424 -#define DBSC_DBDBICNT 0x518 -#define DBSC_DBDFIPMSTRCNF 0x520 -#define DBSC_DBDFICUPDCNF 0x540 -#define DBSC_DBBCAMDIS 0x9FC -#define DBSC_DBSCHRW1 0x1024 -#define DBSC_DBSCHTR0 0x1030 -#define DBSC_DBTR(x) (0x300 + (0x4 * (x))) -#define DBSC_DBRNK(x) (0x430 + (0x4 * (x))) -#define DBSC_DBDFISTAT(ch) (0x600 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBDFICNT(ch) (0x604 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDCNT2(ch) (0x618 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDLK(ch) (0x620 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDRGA(ch) (0x624 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDRGD(ch) (0x628 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDRGM(ch) (0x62C + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDSTAT0(ch) (0x630 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBPDSTAT1(ch) (0x634 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) -#define DBSC_DBSCHFCTST0 0x1040 -#define DBSC_DBSCHFCTST1 0x1044 - -/* CPG PLL3 registers */ -#define CPG_CPGWPR 0x0 -#define CPG_FRQCRD0 0x80C -#define CPG_PLLECR 0x820 -#define CPG_PLL3CR0 0x83C -#define CPG_PLL3CR1 0x8C0 -#define CPG_FSRCHKCLRR4 0x590 -#define CPG_FSRCHKSETR4 0x510 -#define CPG_FSRCHKRA4 0x410 -#define CPG_SRCR4 0x2C10 -#define CPG_SRSTCLR4 0x2C90 - -#define CPG_FRQCRD_KICK_BIT BIT(31) -#define CPG_PLL3CR0_KICK_BIT BIT(31) -#define CPG_PLLECR_PLL3ST_BIT BIT(11) - -#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) - -struct renesas_dbsc5_dram_priv { - void __iomem *regs; - void __iomem *cpg_regs; - - /* The board parameter structure of the board */ - const struct renesas_dbsc5_board_config *dbsc5_board_config; - - /* The board clock frequency */ - u32 brd_clk; - u32 brd_clkdiv; - u32 brd_clkdiva; - - /* The Mbps of Bus */ - u32 bus_clk; - u32 bus_clkdiv; - - /* The Mbps of DDR */ - u32 ddr_mbps; - u32 ddr_mbpsdiv; - - /* DDR memory multiplier setting value */ - u32 ddr_mul; - u32 ddr_mul_nf; - u32 ddr_mul_low; - u32 ddr_mul_reg; - - /* Value indicating the enabled channel */ - u32 ddr_phyvalid; - - /* The tccd value of DDR */ - u32 ddr_tccd; - - /* Memory capacity in each channel and each CS */ - u8 ddr_density[DRAM_CH_CNT][CS_CNT]; - /* Channels used for each memory rank */ - u32 ch_have_this_cs[CS_CNT]; - /* The maximum memory capacity */ - u32 max_density; - - /* Index of jedec spec1 setting table you use */ - u32 js1_ind; - /* Array of jedec spec2 setting table */ - u32 js2[JS2_CNT]; - /* Read latency */ - u32 RL; - /* Write latency */ - u32 WL; - - /* Array for DDR PI Slice settings */ - u32 DDR_PI_REGSET[DDR_PI_REGSET_NUM_V4H]; - /* Array for DDRPHY Slice settings */ - u32 DDR_PHY_SLICE_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; - /* Array for DDRPHY ADRRESS VALUE Slice settings */ - u32 DDR_PHY_ADR_V_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; - /* Array for DDRPHY ADRRESS CONTROL Slice settings */ - u32 DDR_PHY_ADR_G_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; -}; - -static const struct renesas_dbsc5_board_config renesas_v4h_dbsc5_board_config = { - /* RENESAS V4H White Hawk (64Gbit 1rank) */ - .bdcfg_phyvalid = 0xF, - .bdcfg_vref_r = 0x0, - .bdcfg_vref_w = 0x0, - .bdcfg_vref_ca = 0x0, - .bdcfg_rfm_chk = true, - .ch = { - [0] = { - .bdcfg_ddr_density = { 0x06, 0xFF }, - .bdcfg_ca_swap = 0x04506132, - .bdcfg_dqs_swap = 0x01, - .bdcfg_dq_swap = { 0x26147085, 0x12306845 }, - .bdcfg_dm_swap = { 0x03, 0x07 }, - .bdcfg_cs_swap = 0x10 - }, - [1] = { - .bdcfg_ddr_density = { 0x06, 0xFF }, - .bdcfg_ca_swap = 0x02341065, - .bdcfg_dqs_swap = 0x10, - .bdcfg_dq_swap = { 0x56782314, 0x71048365 }, - .bdcfg_dm_swap = { 0x00, 0x02 }, - .bdcfg_cs_swap = 0x10 - }, - [2] = { - .bdcfg_ddr_density = { 0x06, 0xFF }, - .bdcfg_ca_swap = 0x02150643, - .bdcfg_dqs_swap = 0x10, - .bdcfg_dq_swap = { 0x58264071, 0x41207536 }, - .bdcfg_dm_swap = { 0x03, 0x08 }, - .bdcfg_cs_swap = 0x10 - }, - [3] = { - .bdcfg_ddr_density = { 0x06, 0xFF }, - .bdcfg_ca_swap = 0x01546230, - .bdcfg_dqs_swap = 0x01, - .bdcfg_dq_swap = { 0x45761328, 0x62801745 }, - .bdcfg_dm_swap = { 0x00, 0x03 }, - .bdcfg_cs_swap = 0x10 - } - } -}; - -/** - * r_vch_nxt() - Macro for channel selection loop - * - * Return the ID of the channel to be used. Check for valid channels - * between the value of posn and the maximum number of CHs. If a valid - * channel is found, returns the value of that channel. - */ -static u32 r_vch_nxt(struct udevice *dev, u32 pos) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - int posn; - - for (posn = pos; posn < DRAM_CH_CNT; posn++) - if (priv->ddr_phyvalid & BIT(posn)) - break; - - return posn; -} - -/* Select only valid channels in all channels from CH0. */ -#define r_foreach_vch(dev, ch) \ -for ((ch) = r_vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = r_vch_nxt((dev), (ch) + 1)) - -/* All channels are selected. */ -#define r_foreach_ech(ch) \ -for (ch = 0; ch < DRAM_CH_CNT; ch++) - -/** - * dbsc5_clk_cpg_write_32() - Write clock control register - * - * Write the complement value of setting value to the CPG_CPGWPR register - * for releaseing the protect. Write setting value to destination address. - */ -static void dbsc5_clk_cpg_write_32(struct udevice *dev, void __iomem *a, u32 v) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - - writel(~v, priv->cpg_regs + CPG_CPGWPR); - writel(v, a); -} - -enum dbsc5_clk_pll3_mode { - PLL3_LOW_FREQUENCY_MODE = 0, - PLL3_HIGH_FREQUENCY_MODE, - PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER -}; - -/** - * dbsc5_clk_pll3_control() - Set PLL3 - * @dev: DBSC5 device - * @mode: PLL3 frequency mode - * - * Determine the set value according to the frequency mode of the argument. - * Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one. - * Reflect settings - */ -static void dbsc5_clk_pll3_control(struct udevice *dev, u32 mode) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - u32 data_div, data_mul, data_nf, ssmode, val; - int ret; - - /* - * PLL3VCO = EXTAL * priv->ddr_mul * 1/2 - * clk_ctlr_sync = PLL3VCO * pll3_div - * priv->ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 - */ - - switch (mode) { - case PLL3_LOW_FREQUENCY_MODE: - /* Low frequency mode (50MHz) */ - data_mul = (priv->ddr_mul_low / 2) - 1; /* PLL3VCO = 1600MHz */ - data_div = 0x9; /* div = 32 */ - data_nf = 0x0; - ssmode = 0x0; - break; - case PLL3_HIGH_FREQUENCY_MODE: - /* High frequency mode */ - data_mul = (priv->ddr_mul / 2) - 1; - data_div = 0x0; /* div = 2 */ - data_nf = priv->ddr_mul_nf; - ssmode = 0x4; - break; - case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: - /* High frequency mode for loading to DDRPHY registers */ - data_mul = (priv->ddr_mul_reg / 2) - 1; - data_div = 0x0; /* div = 2 */ - data_nf = 0x0; - ssmode = 0x4; - break; - default: - printf("%s Mode %d not supported\n", __func__, mode); - hang(); - } - - data_mul = (data_mul << 20) | (ssmode << 16); - data_nf = data_nf << 21; - - if (((readl(priv->cpg_regs + CPG_PLL3CR0) & 0x3FFFFF7F) != data_mul) || - (readl(priv->cpg_regs + CPG_PLL3CR1) != data_nf)) { - /* PLL3CR0 multiplie set */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, data_mul); - /* PLL3CR1 multiplie set */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR1, data_nf); - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, - readl(priv->cpg_regs + CPG_PLL3CR0) | - CPG_PLL3CR0_KICK_BIT); - - ret = readl_poll_timeout(priv->cpg_regs + CPG_PLLECR, val, - (val & CPG_PLLECR_PLL3ST_BIT), - 1000000); - if (ret < 0) { - printf("%s CPG_PLLECR bit CPG_PLLECR_PLL3ST_BIT timeout\n", __func__); - hang(); - } - } - - /* PLL3 DIV set(Target value) */ - ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, - ((val & CPG_FRQCRD_KICK_BIT) == 0), - 1000000); - if (ret < 0) { - printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT div set timeout\n", __func__); - hang(); - } - - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, - (readl(priv->cpg_regs + CPG_FRQCRD0) & 0xFFFFFFF0) | - data_div); - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, - readl(priv->cpg_regs + CPG_FRQCRD0) | - CPG_FRQCRD_KICK_BIT); - ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, - ((val & CPG_FRQCRD_KICK_BIT) == 0), - 1000000); - if (ret < 0) { - printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT timeout\n", __func__); - hang(); - } -} - -/** - * dbsc5_clk_wait_freqchgreq() - Training handshake functions - * - * Check the value of the argument req_assert. If req_assert is 1, wait until - * FREQCHGREQ of all channels is 1 before time expires. If req_assert is 0, - * wait until FREQCHGREQ of all channels is 0 before time expires. Return the - * result of whether time has expired or not as a return value. - */ -static u32 dbsc5_clk_wait_freqchgreq(struct udevice *dev, u32 req_assert) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 count = 0xFFFFFF; - u32 ch, reg; - - do { - reg = !!req_assert; - r_foreach_vch(dev, ch) - reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); - count = count - 1; - } while (((reg & 0x1) != !!req_assert) && (count != 0)); - - return count == 0x0; -} - -/** - * dbsc5_clk_set_freqchgack() - Training handshake functions - * @dev: DBSC5 device - * @ack_assert: Select DBSC_DBPDCNT2 content - * - * Check the value of the argument ackassert. If the value of ackassert - * is greater than or equal to 0, write 0xCF01 to DBSC_DBPDCNT2. - * If the value of ackassert is 0, write 0x0 to DBSC_DBPDCNT2. - */ -static void dbsc5_clk_set_freqchgack(struct udevice *dev, u32 ack_assert) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - const u32 reg = ack_assert ? 0xcf01 : 0x0; - u32 ch; - - r_foreach_vch(dev, ch) - writel(reg, regs_dbsc_d + DBSC_DBPDCNT2(ch)); -} - -/** - * dbsc5_clk_wait_dbpdstat1() - Wait for status register update - * @dev: DBSC5 device - * @status: Expected status - * - * Read value the DBSC_DBPDSTAT1(ch) register. Wait until the contents - * of the status register are the same as status. - */ -static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 i, ch, chk, reg; - - for (i = 0; i < 2; i++) { - do { - reg = status; - chk = 0; - r_foreach_vch(dev, ch) { - reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch)); - chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); - } - } while (reg != status && !(chk & BIT(0))); - } -} - -/** - * dbsc5_clk_pll3_freq() - Set up the pll3 frequency - * @dev: DBSC5 device - * - * Wait for frequency change request. DBSC_DBPDSTAT0 value determines whether - * dbsc5_clk_pll3_control is called in low frequency mode or high frequency - * mode. Call dbsc5_clk_set_freqchgack(1) function. Check update completion until - * timeout. Call dbsc5_clk_set_freqchgack(0) function. If timed out, return with - * error log Wait for status register update. - */ -static int dbsc5_clk_pll3_freq(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 fsel, timeout; - - dbsc5_clk_wait_freqchgreq(dev, 1); - - fsel = (readl(regs_dbsc_d + DBSC_DBPDSTAT0(0)) & 0x300) >> 8; - dbsc5_clk_pll3_control(dev, fsel ? PLL3_HIGH_FREQUENCY_MODE : - PLL3_LOW_FREQUENCY_MODE); - - dbsc5_clk_set_freqchgack(dev, 1); - timeout = dbsc5_clk_wait_freqchgreq(dev, 0); - dbsc5_clk_set_freqchgack(dev, 0); - - if (timeout) { - printf("Time out\n"); - return -ETIMEDOUT; - } - - dbsc5_clk_wait_dbpdstat1(dev, 0x7); - - return 0; -} - -/** - * dbsc5_reg_write() - Write DBSC register - * @addr: Destination address - * @data: Setting value to be written - * - * Write 32bit value @data to register at @addr . - */ -static void dbsc5_reg_write(void __iomem *addr, u32 data) -{ - writel(data, addr); - - if (((uintptr_t)addr & 0x000A0000) == 0x000A0000) - writel(data, addr + 0x4000); - else - writel(data, addr + 0x8000); -} - -/** - * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion - * @dev: DBSC5 device - * - * Wait for DRAM access completion. This is used before sending a command - * to the DRAM to assure no other command is in flight already, or while - * waiting for MRR command to complete. - */ -static void dbsc5_wait_dbwait(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 val; - int ret; - - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000); - if (ret < 0) { - printf("%s DBWAIT bit 0 timeout\n", __func__); - hang(); - } - - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000); - if (ret < 0) { - printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__); - hang(); - } -} - -/** - * dbsc5_send_dbcmd2() - DRAM Command Write Access - * @dev: DBSC5 device - * @opcode DRAM controller opcode - * @channel DRAM controller channel (0..3) - * @rank DRAM controller rank (0..1) - * @arg Command and argument bits (command specific encoding) - * - * First, execute the dummy read to DBSC_DBCMD. - * Confirm that no DBSC command operation is in progress 0. - * Write the contents of the command to be sent to DRAM. - */ -static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode, - const u8 channel, const u8 rank, - const u16 arg) -{ - const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg; - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - - /* dummy read */ - readl(regs_dbsc_d + DBSC_DBCMD); - - dbsc5_wait_dbwait(dev); - - dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd); -} - -/** - * dbsc5_reg_ddrphy_read() - Read setting from DDR PHY register - * @dev: DBSC5 device - * @ch: Target channel - * @regadd: Destination address - * - * Write matching values to DBPDRGA register and read value out of DBSC_DBPDRGD. - * Wait until the write process completed in each step. - */ -static u32 dbsc5_reg_ddrphy_read(struct udevice *dev, u32 ch, u32 regadd) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 val; - int ret; - - writel(regadd | BIT(14), regs_dbsc_d + DBSC_DBPDRGA(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15) | BIT(14))), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); - hang(); - } - - val = readl(regs_dbsc_d + DBSC_DBPDRGA(ch)); - - writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); - hang(); - } - - writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) again timeout\n", __func__); - hang(); - } - - return readl(regs_dbsc_d + DBSC_DBPDRGD(ch)); -} - -/** - * dbsc5_reg_ddrphy_write(dev, ) - Write setting to DDR PHY register - * @dev: DBSC5 device - * @ch: Target channel - * @regadd: Destination address - * @regdata: Value to be written - * - * Write matching values to DBPDRGA, DBPDRGD, DBPDRGA, DBPDRGA registers. - * Wait until the write process completed in each step. - */ -static void dbsc5_reg_ddrphy_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 val; - int ret; - - writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); - hang(); - } - - writel(regdata, regs_dbsc_d + DBSC_DBPDRGD(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15))), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGD timeout\n", __func__); - hang(); - } - - writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); - hang(); - } - - writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); -} - -/* - * dbsc5_reg_ddrphy_write_all() - Write setting from DDR PHY register for all channels - * @dev: DBSC5 device - * @regadd: Destination address - * @regdata: Value to be written - * - * Wrapper around dbsc5_reg_ddrphy_write() for all channels. - */ -static void dbsc5_reg_ddrphy_write_all(struct udevice *dev, u32 regadd, u32 regdata) -{ - u32 ch; - - r_foreach_vch(dev, ch) - dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); -} - -/** - * dbsc5_reg_ddrphy_masked_write() - Write setting to DDR PHY register with mask - * @dev: DBSC5 device - * @ch: Target channel - * @regadd: Destination address - * @regdata: Value to be written - * @msk: Register mask - * - * Wrapper around dbsc5_reg_ddrphy_write() with DBPDRGM set. - */ -static void dbsc5_reg_ddrphy_masked_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata, u32 msk) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 val; - int ret; - - writel(msk, regs_dbsc_d + DBSC_DBPDRGM(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == msk), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGM timeout\n", __func__); - hang(); - } - - dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); - - writel(0, regs_dbsc_d + DBSC_DBPDRGM(ch)); - ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == 0), 1000000); - if (ret < 0) { - printf("%s regs_dbsc_d + DBSC_DBPDRGM != 0 timeout\n", __func__); - hang(); - } -} - -/** - * dbsc5_ddr_setval_slice() - Write setting to DDR PHY hardware - * @dev: DBSC5 device - * @ch: Target channel - * @slice: Target slice - * @regdef: Encoded PHY/PI register and bitfield - * @val: Value to be written - * - * Calculate the bit field in which to write the setting value - * from encoded register and bitfield @regdef parameter. Call - * dbsc5_reg_ddrphy_masked_write() to write the value to hardware. - */ -static void dbsc5_ddr_setval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef, u32 val) -{ - const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); - const u32 len = DDR_REGDEF_LEN(regdef); - const u32 lsb = DDR_REGDEF_LSB(regdef); - const u32 msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); - const u32 dms = ~((!!(msk & BIT(24)) << 3) | (!!(msk & BIT(16)) << 2) | - (!!(msk & BIT(8)) << 1) | !!(msk & BIT(0))) & 0xf; - - dbsc5_reg_ddrphy_masked_write(dev, ch, adr, val << lsb, dms); -} - -/* - * dbsc5_ddr_setval() - Write setting from DDR PHY hardware slice 0 - * @dev: DBSC5 device - * @ch: Target channel - * @regdef: Encoded PHY/PI register and bitfield - * @val: Value to be written - * - * Wrapper around dbsc5_ddr_setval_slice() for slice 0. - */ -static void dbsc5_ddr_setval(struct udevice *dev, u32 ch, u32 regdef, u32 val) -{ - dbsc5_ddr_setval_slice(dev, ch, 0, regdef, val); -} - -/* - * dbsc5_ddr_setval_all_ch_slice() - Write setting from DDR PHY hardware for all channels and one slice - * @dev: DBSC5 device - * @slice: Target slice - * @regdef: Encoded PHY/PI register and bitfield - * @val: Value to be written - * - * Wrapper around dbsc5_ddr_setval_slice() for slice 0. - */ -static void dbsc5_ddr_setval_all_ch_slice(struct udevice *dev, u32 slice, u32 regdef, u32 val) -{ - u32 ch; - - r_foreach_vch(dev, ch) - dbsc5_ddr_setval_slice(dev, ch, slice, regdef, val); -} - -/* - * dbsc5_ddr_setval_all_ch() - Write setting from DDR PHY hardware for all channels and slice 0 - * @dev: DBSC5 device - * @regdef: Encoded PHY/PI register and bitfield - * @val: Value to be written - * - * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. - */ -static void dbsc5_ddr_setval_all_ch(struct udevice *dev, u32 regdef, u32 val) -{ - dbsc5_ddr_setval_all_ch_slice(dev, 0, regdef, val); -} - -/* - * dbsc5_ddr_setval_all_ch_all_slice() - Write setting from DDR PHY hardware for all channels and all slices - * @dev: DBSC5 device - * @regdef: Encoded PHY/PI register and bitfield - * @val: Value to be written - * - * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. - */ -static void dbsc5_ddr_setval_all_ch_all_slice(struct udevice *dev, u32 regdef, u32 val) -{ - u32 slice; - - for (slice = 0; slice < SLICE_CNT; slice++) - dbsc5_ddr_setval_all_ch_slice(dev, slice, regdef, val); -} - -/** - * dbsc5_ddr_getval_slice() - Read setting from DDR PHY/PI hardware - * @dev: DBSC5 device - * @ch: Target channel - * @slice: Target slice - * @regdef: Encoded PHY/PI register and bitfield - * - * Calculate the address and the bit-field from "regdef" value. - * Call dbsc5_reg_ddrphy_read() to read value from the target address. - */ -static u32 dbsc5_ddr_getval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef) -{ - const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); - const u32 len = DDR_REGDEF_LEN(regdef); - const u32 lsb = DDR_REGDEF_LSB(regdef); - const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); - - return (dbsc5_reg_ddrphy_read(dev, ch, adr) >> lsb) & msk; -} - -/** - * dbsc5_ddr_getval() - Read setting from DDR PHY/PI hardware slice 0 - * @dev: DBSC5 device - * @ch: Target channel - * @regdef: Encoded PHY/PI register and bitfield - * - * Wrapper around dbsc5_ddr_getval_slice() for slice 0. - */ -static u32 dbsc5_ddr_getval(struct udevice *dev, u32 ch, u32 regdef) -{ - return dbsc5_ddr_getval_slice(dev, ch, 0, regdef); -} - -/** - * dbsc5_table_patch_set() - Modify DDR PHY/PI settings table - * @tbl: DDR PHY/PI setting table pointer - * @adrmsk_pi: Use wider address mask for PI register - * @patch: List of modifications to the settings table - * @patchlen: Length of the list of modifications to the settings table - * - * Calculate the target index of settings table, calculate the bit-field - * to write the setting value, and write the setting value to the target - * bit-field in the index. - */ -static void dbsc5_table_patch_set(u32 *tbl, const bool adrmsk_pi, - const struct dbsc5_table_patch *patch, - int patchlen) -{ - const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; - u32 adr, len, lsb, msk; - int i; - - for (i = 0; i < patchlen; i++) { - adr = DDR_REGDEF_ADR(patch[i].reg); - len = DDR_REGDEF_LEN(patch[i].reg); - lsb = DDR_REGDEF_LSB(patch[i].reg); - msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); - - tbl[adr & adrmsk] &= ~msk; - tbl[adr & adrmsk] |= (patch[i].val << lsb) & msk; - } -} - -/** - * dbsc5_ddrtbl_getval() - Read setting from DDR PHY/PI settings table - * @tbl: DDR PHY/PI setting table pointer - * @regdef: Encoded PHY/PI register and bitfield - * @adrmsk_pi: Use wider address mask for PI register - * - * Calculate the target index of *tbl and the bit-field to read the - * setting value and read and return the setting value from the target - * bit-field in the index. - */ -static u32 dbsc5_ddrtbl_getval(const u32 *tbl, u32 regdef, bool adrmsk_pi) -{ - const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; - const u32 adr = DDR_REGDEF_ADR(regdef); - const u32 len = DDR_REGDEF_LEN(regdef); - const u32 lsb = DDR_REGDEF_LSB(regdef); - const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); - - return (tbl[adr & adrmsk] >> lsb) & msk; -} - -/** - * dbsc5_f_scale() - Calculate the best value for DBSC timing setting - * @priv: Driver private data - * @frac: Perform fractional rounding - * @ps Optimal setting value in pico second - * @cyc Optimal setting value in cycle count - * - * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, - * perform fractional rounding. Compare the value of the result of the conversion with the - * value of the argument @cyc and return the larger value. - */ -static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) -{ - const u32 mul = frac ? 8 : 800000; - const u32 tmp = DIV_ROUND_UP(ps, 10UL) * priv->ddr_mbps; - const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * priv->ddr_mbpsdiv); - - return (f_scale_div > cyc) ? f_scale_div : cyc; -} - -/** - * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 - * @priv: Driver private data - * - * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. - * Only the following array elements are calculated using different formulas from those - * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. - */ -static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv) -{ - const int derate = 0; - int i; - - for (i = 0; i < JS2_TBLCNT; i++) { - priv->js2[i] = dbsc5_f_scale(priv, false, - jedec_spec2[derate][i].ps, - jedec_spec2[derate][i].cyc); - } - - priv->js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, - jedec_spec2[derate][JS2_tZQCALns].ps * 1000UL, 0); - priv->js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, - jedec_spec2[derate][JS2_tDQ72DQns].ps * 1000UL, 0); - priv->js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, - jedec_spec2[derate][JS2_tCAENTns].ps * 1000UL, 0); - priv->js2[JS2_tRCpb] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPpb]; - priv->js2[JS2_tRCab] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPab]; - priv->js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, - jedec_spec2_tRFC_ab[priv->max_density] * 1000UL, 0); - - priv->js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; - priv->js2[JS2_tXSR] = priv->js2[JS2_tRFCab] + - dbsc5_f_scale(priv, false, 7500, 2); - priv->js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; - priv->js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, - jedec_spec2[derate][JS2_tPDN_DSM].ps * 10UL, 0); - priv->js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, - jedec_spec2[derate][JS2_tXSR_DSM].ps * 10UL, 0); - priv->js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, - jedec_spec2[derate][JS2_tXDSM_XP].ps * 10UL, 0); - priv->js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); -} - -/** - * dbsc5_ddrtbl_calc() - Calculate JS1/JS2 - * @priv: Driver private data - * - * Determine jedec_spec1 configuration table based on priv->ddr_mbps - * and priv->ddr_mbpsdiv. Calculate the value of the jedec_spec2 - * configuration table from priv->ddr_mbps and priv->ddr_mbpsdiv. - */ -static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv) -{ - int i; - - /* Search jedec_spec1 index */ - for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) - if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3) - break; - - priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI); - - priv->RL = js1[priv->js1_ind].RLset1; - priv->WL = js1[priv->js1_ind].WLsetA; - - /* Calculate jedec_spec2 */ - dbsc5_f_scale_js2(priv); -}; - -/** - * dbsc5_ddrtbl_load() Load table data into DDR registers - * @dev: DBSC5 device - * - * Copy the base configuration table to a local array. Change PI register table - * settings to match priv->ddr_mbps and priv->ddr_mbpsdiv. - * - * If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" - * setting in the configuration table. - * - * If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" - * setting in the configuration table. - * - * If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" - * setting in the configuration table. - * - * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 5120, - * change the contents of the PHY register setting table. - * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 4576, - * change the contents of the PHY register setting table. - * - * Reflect the contents of the configuration table in the register. - */ -static void dbsc5_ddrtbl_load(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbps = { - PHY_CAL_INTERVAL_COUNT_0, 10000 * priv->ddr_mbps / priv->ddr_mbpsdiv / 8 / 256, - }; - - const struct dbsc5_table_patch dbsc5_table_patch_pi_js[] = { - { PI_WRLAT_F2, priv->WL }, - { PI_TWCKENL_WR_ADJ_F2, (js1[priv->js1_ind].WCKENLW * 4) + 4 }, - { PI_TWCKENL_RD_ADJ_F2, (js1[priv->js1_ind].WCKENLR * 4) + 4 }, - { PI_TWCKPRE_STATIC_F2, (js1[priv->js1_ind].WCKPRESTA * 4) }, - { PI_TWCKPRE_TOGGLE_RD_F2, (js1[priv->js1_ind].WCKPRETGLR) * 4 }, - { PI_CASLAT_F2, priv->RL }, - { PI_TWCKENL_FS_ADJ_F2, (js1[priv->js1_ind].WCKENLF * 4) + 4 }, - { PI_TRFC_F2, priv->js2[JS2_tRFCab] }, - { PI_WRLVL_WCKOFF_F2, (priv->js2[JS2_tWLWCKOFF]) + 3 }, - { PI_WRLAT_ADJ_F2, (priv->WL * 4) + 2 }, - { PI_TCAENT_F2, priv->js2[JS2_tCAENTns] }, - { PI_TVREF_LONG_F2, (priv->js2[JS2_tCAENTns]) + 1 }, - { PI_TVREF_SHORT_F2, (priv->js2[JS2_tCAENTns]) + 1 }, - { PI_TRCD_F2, priv->js2[JS2_tRCD] }, - { PI_TRP_F2, priv->js2[JS2_tRPab] }, - { PI_TRTP_F2, js1[priv->js1_ind].nRBTP }, - { PI_TRAS_MIN_F2, priv->js2[JS2_tRAS] }, - { PI_TMRD_F2, (priv->js2[JS2_tMRD]) + 1 }, - { PI_TSR_F2, priv->js2[JS2_tSR] }, - { PI_TZQCAL_F2, priv->js2[JS2_tZQCALns] }, - { PI_TZQLAT_F2, priv->js2[JS2_tZQLAT] }, - { PI_TDQ72DQ_F2, priv->js2[JS2_tDQ72DQns] }, - { PI_MC_TRFC_F2, priv->js2[JS2_tRFCab] }, - }; - - const u32 vref_r = priv->dbsc5_board_config->bdcfg_vref_r; - const struct dbsc5_table_patch dbsc5_table_patch_slice_vref_r[] = { - { PHY_VREF_INITIAL_START_POINT, vref_r & 0xFF }, - { PHY_VREF_INITIAL_STOP_POINT, (vref_r & 0xFF00) >> 8 }, - { PHY_VREF_INITIAL_STEPSIZE, (vref_r & 0xFF0000) >> 16 } - }; - - const u32 vref_w = priv->dbsc5_board_config->bdcfg_vref_w; - const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_w[] = { - { PI_WDQLVL_VREF_INITIAL_START_POINT_F0, vref_w & 0xff }, - { PI_WDQLVL_VREF_INITIAL_START_POINT_F1, vref_w & 0xff }, - { PI_WDQLVL_VREF_INITIAL_START_POINT_F2, vref_w & 0xff }, - { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (vref_w & 0xff00) >> 8 }, - { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (vref_w & 0xff00) >> 8 }, - { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (vref_w & 0xff00) >> 8 } - }; - - const u32 vref_ca = priv->dbsc5_board_config->bdcfg_vref_ca; - const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_ca[] = { - { PI_CALVL_VREF_INITIAL_START_POINT_F0, vref_ca & 0xff }, - { PI_CALVL_VREF_INITIAL_START_POINT_F1, vref_ca & 0xff }, - { PI_CALVL_VREF_INITIAL_START_POINT_F2, vref_ca & 0xff }, - { PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (vref_ca & 0xff00) >> 8 }, - { PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (vref_ca & 0xff00) >> 8 }, - { PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (vref_ca & 0xff00) >> 8 } - }; - - int i, cs, slice; - u32 adr; - - /* Prepare register tables */ - memcpy(priv->DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_V4H, sizeof(DDR_PHY_SLICE_REGSET_V4H)); - memcpy(priv->DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_V4H, sizeof(DDR_PHY_ADR_V_REGSET_V4H)); - memcpy(priv->DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_V4H, sizeof(DDR_PHY_ADR_G_REGSET_V4H)); - memcpy(priv->DDR_PI_REGSET, DDR_PI_REGSET_V4H, sizeof(DDR_PI_REGSET_V4H)); - - /* Adjust PI parameters */ - dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, - &dbsc5_table_patch_adr_g_mbps, 1); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_js, - ARRAY_SIZE(dbsc5_table_patch_pi_js)); - - if (priv->ddr_mbps < (3201 * priv->ddr_mbpsdiv)) { - /* 2751-3200 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_3200, - ARRAY_SIZE(dbsc5_table_patch_slice_3200)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_3200, - ARRAY_SIZE(dbsc5_table_patch_adr_v_3200)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_3200, - ARRAY_SIZE(dbsc5_table_patch_pi_3200)); - } else if (priv->ddr_mbps < (3734 * priv->ddr_mbpsdiv)) { - /* 3201-3733 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_3733, - ARRAY_SIZE(dbsc5_table_patch_slice_3733)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_3733, - ARRAY_SIZE(dbsc5_table_patch_adr_v_3733)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_3733, - ARRAY_SIZE(dbsc5_table_patch_pi_3733)); - } else if (priv->ddr_mbps < (4268 * priv->ddr_mbpsdiv)) { - /* 3734-4267 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_4266, - ARRAY_SIZE(dbsc5_table_patch_slice_4266)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_4266, - ARRAY_SIZE(dbsc5_table_patch_adr_v_4266)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_4266, - ARRAY_SIZE(dbsc5_table_patch_pi_4266)); - } else if (priv->ddr_mbps < (4801 * priv->ddr_mbpsdiv)) { - /* 4269-4800 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_4800, - ARRAY_SIZE(dbsc5_table_patch_slice_4800)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_4800, - ARRAY_SIZE(dbsc5_table_patch_adr_v_4800)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_4800, - ARRAY_SIZE(dbsc5_table_patch_pi_4800)); - } else if (priv->ddr_mbps < (5501 * priv->ddr_mbpsdiv)) { - /* 4801 - 5500 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_5500, - ARRAY_SIZE(dbsc5_table_patch_slice_5500)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_5500, - ARRAY_SIZE(dbsc5_table_patch_adr_v_5500)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_5500, - ARRAY_SIZE(dbsc5_table_patch_pi_5500)); - } else if (priv->ddr_mbps < (6001 * priv->ddr_mbpsdiv)) { - /* 5501 - 6000 */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_6000, - ARRAY_SIZE(dbsc5_table_patch_slice_6000)); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - dbsc5_table_patch_adr_v_6000, - ARRAY_SIZE(dbsc5_table_patch_adr_v_6000)); - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_6000, - ARRAY_SIZE(dbsc5_table_patch_pi_6000)); - } - - for (cs = 0; cs < CS_CNT; cs++) { - struct dbsc5_table_patch dbsc5_table_patch_pi_mr12[] = { - { PI_DARRAY3_0_CSx_Fx[cs][2], js1[priv->js1_ind].MR1 }, - { PI_DARRAY3_1_CSx_Fx[cs][2], js1[priv->js1_ind].MR2 }, - }; - - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_mr12, - ARRAY_SIZE(dbsc5_table_patch_pi_mr12)); - } - - /* Read Vref (SoC side) Training range */ - if (priv->dbsc5_board_config->bdcfg_vref_r) { - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - dbsc5_table_patch_slice_vref_r, - ARRAY_SIZE(dbsc5_table_patch_slice_vref_r)); - } - - /* Write Vref (MR14, MR15) Training range */ - if (priv->dbsc5_board_config->bdcfg_vref_w) { - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_vref_w, - ARRAY_SIZE(dbsc5_table_patch_pi_vref_w)); - } - - /* CA Vref (MR12) Training range */ - if (priv->dbsc5_board_config->bdcfg_vref_ca) { - dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, - dbsc5_table_patch_pi_vref_ca, - ARRAY_SIZE(dbsc5_table_patch_pi_vref_ca)); - } - - /* Low Freq setting */ - if (priv->ddr_mbps < (8 * 640 * priv->ddr_mbpsdiv)) { - /* CAL_CLK(10-20MHz) */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - &dbsc5_table_patch_slice_mbpsdiv_640, 1); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, - &dbsc5_table_patch_adr_v_mbpsdiv_640, 1); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, - &dbsc5_table_patch_adr_g_mbpsdiv_640, 1); - } - - if (priv->ddr_mbps < (8 * 572 * priv->ddr_mbpsdiv)) { - /* CAL_CLK(10-20MHz) */ - dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, - &dbsc5_table_patch_slice_mbpsdiv_572, 1); - dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, - &dbsc5_table_patch_adr_g_mbpsdiv_572, 1); - } - - if (priv->ddr_mbps < (8 * 401 * priv->ddr_mbpsdiv)) { - dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, - dbsc5_table_patch_adr_g_mbpsdiv_400, - ARRAY_SIZE(dbsc5_table_patch_adr_g_mbpsdiv_400)); - } - - /* SET DATA SLICE TABLE */ - for (slice = 0; slice < SLICE_CNT; slice++) { - adr = DDR_PHY_SLICE_REGSET_OFS_V4H + (DDR_PHY_SLICE_REGSET_SIZE_V4H * slice); - for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM_V4H; i++) - dbsc5_reg_ddrphy_write_all(dev, adr + i, priv->DDR_PHY_SLICE_REGSET[i]); - } - - /* SET ADR SLICE TABLE */ - for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM_V4H; i++) - dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_V_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_V_REGSET[i]); - - /* SET ADRCTRL SLICE TABLE */ - for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM_V4H; i++) - dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_G_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_G_REGSET[i]); - - /* SET PI REGISTERS */ - for (i = 0; i < DDR_PI_REGSET_NUM_V4H; i++) - dbsc5_reg_ddrphy_write_all(dev, DDR_PI_REGSET_OFS_V4H + i, priv->DDR_PI_REGSET[i]); -} - -/** - * dbsc5_ddr_config() - Configure DDR registers - * @dev: DBSC5 device - * - * Set up wiring for DQ and DM pins and VREF_DRIVING. Set the CA pin wiring - * and ADR_CALVL_SWIZZLE settings. Make wiring settings for the CS pin. When - * memory rank is 1, set RANK setting to 1 to disable CS training. Configure - * the DATA_BYTE_SWAP setting. - */ -static void dbsc5_ddr_config(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - u32 ca_swap, cs_swap, dqs_swap; - u32 ch, slice; - - r_foreach_vch(dev, ch) { - /* Board settings (DQ, DM, VREF_DRIVING) */ - dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; - for (slice = 0; slice < SLICE_CNT; slice++) { - dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE0, - priv->dbsc5_board_config->ch[ch].bdcfg_dq_swap[slice]); - dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE1, - priv->dbsc5_board_config->ch[ch].bdcfg_dm_swap[slice]); - dbsc5_ddr_setval_slice(dev, ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, - !((dqs_swap >> (4 * slice)) & 1)); - } - dbsc5_ddr_setval(dev, ch, PHY_DATA_BYTE_ORDER_SEL, - priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap | 0x76543200); - - /* Board settings (CA, ADDR_MUX) */ - ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; - - /* ADDR_MUX */ - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_0, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_1, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_2, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_3, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_4, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_5, ca_swap & 0xf); - ca_swap >>= 4; - dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_6, ca_swap & 0xf); - ca_swap >>= 4; - - /* ADR_CALVL_SWIZZLE */ - ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; - dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_SWIZZLE0, ca_swap & 0x0fffffff); - - /* Board settings (CS) */ - /* CKE_MUX */ - /* SoC CKE -> DRAM CS */ - cs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_cs_swap; - dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_0, (cs_swap & 0xf) + 2); - dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_1, ((cs_swap >> 4) & 0xf) + 2); - dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT2_2, (cs_swap & 0xf) + 1); - dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((cs_swap >> 4) & 0xf) + 1); - - /* Mask CS_MAP if RANK1 is not found */ - if (!(priv->ch_have_this_cs[1] & BIT(ch))) { - dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_RANK_CTRL, 0x0); - for (slice = 0; slice < SLICE_CNT; slice++) - dbsc5_ddr_setval_slice(dev, ch, slice, PHY_PER_CS_TRAINING_EN, 0x0); - } - } - - r_foreach_vch(dev, ch) { - /* DATA_BYTE_SWAP */ - dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; - - dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_EN, 0x1); - dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE0, dqs_swap & 0xf); - dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE1, (dqs_swap >> 4) & 0xf); - - if (!(priv->ch_have_this_cs[1] & BIT(ch))) - dbsc5_ddr_setval(dev, ch, PI_CS_MAP, 0x1); - } -} - -/** - * dbsc5_dbsc_regset_pre() - Configure primary DDR registers - * @dev: DBSC5 device - * - * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. - * Write SDRAM configuration contents to registers. - */ -static void dbsc5_dbsc_regset_pre(struct udevice *dev) -{ -#define DBMEMCONF_REG(d3, row, bg, bank, col, dw) \ - (((d3) << 30) | ((row) << 24) | ((bg) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) -#define DBMEMCONF_REGD(density) /* 16bit */ \ - DBMEMCONF_REG(((density) % 2), ((((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1)), 2, 2, 10, 1) - - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 density; - u32 ch, cs; - - /* Primary settings */ - /* LPDDR5, BL=16, DFI interface */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBMEMKIND, 0xC); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBMEMKINDA, 0xC); - dbsc5_reg_write(regs_dbsc_d + DBSC_DBBL, 0x2); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBBLA, 0x2); - dbsc5_reg_write(regs_dbsc_d + DBSC_DBPHYCONF0, 0x1); - - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF0, 0x1); - - /* FREQRATIO=2 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF1, 0x20000); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF1A, 0x0); - - dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF2, 0x1); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF2A, 0x241); - - r_foreach_ech(ch) { - for (cs = 0; cs < CS_CNT; cs++) { - if (priv->ddr_density[ch][cs] == 0xFF) { - writel(0x00, regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); - writel(0x00, regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); - } else { - density = priv->ddr_density[ch][cs]; - writel(DBMEMCONF_REGD(density), - regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); - writel(DBMEMCONF_REGD(density), - regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); - } - } - } -} - -/** - * dbsc5_dbsc_regset() - Set DBSC timing parameters - * @dev: DBSC5 device - * - * Set the timing registers of the DBSC. - * Configure Scheduler settings. - */ -static void dbsc5_dbsc_regset(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 tmp[4]; - - /* DBTR0.CL : RL */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(0), priv->RL); - - /* DBTR1.CWL : WL */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(1), priv->WL); - - /* DBTR2.AL = 0 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(2), 0x0); - - /* DBTR3.TRCD: tRCD */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(3), priv->js2[JS2_tRCD]); - - /* DBTR4.TRPA,TRP: tRPab,tRPpb */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(4), (priv->js2[JS2_tRPab] << 16) | - priv->js2[JS2_tRPpb]); - - /* DBTR5.TRC : tRCpb */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(5), priv->js2[JS2_tRCpb]); - - /* DBTR6.TRAS : tRAS */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(6), priv->js2[JS2_tRAS]); - - /* DBTR7.TRRD : tRRD */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(7), ((priv->js2[JS2_tRRD] - 1) << 16) | - (priv->js2[JS2_tRRD] - 1)); - - /* DBTR8.TFAW : tFAW */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(8), priv->js2[JS2_tFAW] - 1); - - /* DBTR9.TRDPR: nRBTP */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); - - /* DBTR10.TWR : nWR */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(10), js1[priv->js1_ind].nWR); - - /* - * DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + - * RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature - */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11), - priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - - js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2); - - /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12), - ((priv->WL + 2 + priv->js2[JS2_tWTR_S]) << 16) | - (priv->WL + 4 + priv->js2[JS2_tWTR_L])); - - /* DBTR13.TRFCAB : tRFCab */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(13), priv->js2[JS2_tRFCab]); - - /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(14), (priv->js2[JS2_tCSCAL] << 24) | - (priv->js2[JS2_tXP] << 16) | - priv->js2[JS2_tXP]); - - /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(15), (0x02 << 24) | - (priv->js2[JS2_tSR] << 16) | - priv->js2[JS2_tSR]); - - /* DBTR16 */ - /* wdql(tphy_wrlat + tphy_wrdata) */ - tmp[0] = (priv->WL * 4) - 1 + 5; - /* dqenltcy(tphy_wrlat) */ - tmp[1] = (priv->WL * 4) - 2 - 2 + 5; - /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ - tmp[2] = (priv->RL * 4) + - dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, false) + - dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, false) + - 39; - /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ - tmp[3] = (priv->RL * 4) + 4 - - dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, false); - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(16), (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(17), (priv->js2[JS2_tMRR] << 24) | - (priv->js2[JS2_tMRW] << 16)); - - /* DBTR18. RODTL, RODTA = 0 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(18), 0x0); - - /* DBTR19. TZQCL, TZQCS = 0 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(19), 0x0); - - /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(20), ((priv->js2[JS2_tXSR]) << 16) | - priv->js2[JS2_tXSR]); - - /* DBTR21.TCCD */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(21), (priv->ddr_tccd << 16) | - (priv->ddr_tccd * 2)); - - /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(22), (priv->js2[JS2_tZQCALns] << 16) | priv->js2[JS2_tZQLAT]); - - /* DBTR23. RRSPC = 0 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(23), 0x0); - - /* DBTR24 */ - /* WRCSLAT(tphy_wrcslat) */ - tmp[0] = (priv->WL * 4) - 2; - /* WRCSGAP(tphy_wrcsgap) */ - tmp[1] = 0x0C; - /* RDCSLAT(tphy_rdcslat) */ - tmp[2] = priv->RL * 4; - /* RDCSGAP(tphy_rdcsgap) */ - tmp[3] = 0x0C; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* DBTR25. TWDQLVLDIS = 0 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(25), 0x0); - - /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(26), 0x0); - - /* DBTR27.TPDN : tPDN */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(27), priv->js2[JS2_tPDN]); - - /* DBTR28.txsrdsm : tXSR_DSM */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(28), priv->js2[JS2_tXSR_DSM]); - - /* DBTR29.tdsmxp : tXDSM_XP */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(29), priv->js2[JS2_tXDSM_XP]); - - /* DBTR30.TCMDPD : tCMDPD = 3 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(30), 0x3); - - /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(31), (priv->js2[JS2_tWCK2DQO_HF] << 4) | - priv->js2[JS2_tWCK2DQI_HF]); - - /* DBTR32 */ - /* twckenr */ - tmp[0] = (js1[priv->js1_ind].WCKENLR * 4) + 4 - 1; - /* twckenw */ - tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) + 4 - 1; - /* twckenlf */ - tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) + 4; - /* twckpresta */ - tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* DBTR33 */ - /* TWCKTGL */ - tmp[0] = 4; - /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ - tmp[1] = ((priv->RL + 4) * 4) + 3; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); - - /* DBTR34 */ - /* TWCKSUS = 4 */ - tmp[0] = 4; - /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ - tmp[1] = 1; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); - - /* DBTR35 */ - /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ - tmp[0] = priv->RL + 4 + 0 + 1; - /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ - tmp[1] = priv->WL + 4 + 0 + 1; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); - - /* DBTR36 */ - /* TWSSUSWRX : CAS(WCKSUS)WRX */ - tmp[0] = 3; - /* TWSOFFWRX : CAS(WS_OFF)WRX */ - tmp[1] = 3; - /* TWSFSWRX : CAS(WS_FS)WRX */ - tmp[2] = 2; - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); - - /* DBTR37 */ - /* tOSCO */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(37), priv->js2[JS2_tOSCODQI]); - - /* DBRNK2 */ - /* RNKRR = 12 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(2), 0xCC); - - /* DBRNK3 */ - /* RNKRW = 6 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(3), 0x66); - - /* DBRNK4 */ - /* RNKWR = 6 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(4), 0x66); - - /* DBRNK5 */ - /* RNKWW = 14 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(5), 0xEE); - - /* Timing registers for Scheduler */ - /* SCFCTST0 */ - /* SCPREACT */ - tmp[0] = priv->js2[JS2_tRPpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - /* SCACTRDWR */ - tmp[1] = (priv->WL + 2 + 1 + js1[priv->js1_ind].nWR + priv->js2[JS2_tRPpb]) * - priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - /* SCRDACRT */ - tmp[2] = ((js1[priv->js1_ind].nRBTP + 2) + priv->js2[JS2_tRPpb]) * - priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - /* SCACTACT */ - tmp[3] = priv->js2[JS2_tRCpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* SCFCTST1 */ - /* SCASYNCOFS */ - tmp[0] = 12; - /* SCACTRDWR */ - tmp[1] = priv->js2[JS2_tRCD] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - /* SCWRRD */ - tmp[2] = (readl(regs_dbsc_d + DBSC_DBTR(12)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - /* SCRDWR */ - tmp[3] = (readl(regs_dbsc_d + DBSC_DBTR(11)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* DBSCHRW1 */ - /* SCTRFCAB */ - tmp[0] = (priv->js2[JS2_tRFCab] + priv->js2[JS2_tZQLAT]) * - priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv; - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHRW1, tmp[0]); - - /* DBSCHTR0 */ - /* SCDT0 */ - tmp[0] = (4 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv) - 1; - /* SCDT1 */ - tmp[1] = (8 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv) - 1; - /* SCDT2 */ - tmp[2] = (12 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv) - 1; - /* SCDT3 */ - tmp[3] = (16 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / - priv->ddr_mbps / priv->bus_clkdiv) - 1; - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | - (tmp[1] << 8) | tmp[0]); - - /* QOS and CAM */ - dbsc5_reg_write(regs_dbsc_a + DBSC_DBBCAMDIS, 0x1); -} - -/** - * dbsc5_dbsc_regset_post() - Set DBSC registers - * @dev: DBSC5 device - * - * If memory rank is 2, CS_TRAINING_EN is set to the other side. - * Configure DBI read/write settings. Execute DRAM refresh settings. - * Set WTmode of DFI PHY to OFF. Set up PHY Periodic Write DQ training. - * Set WTmode of DFI PHY to ON. Calibration settings for PHY PAD. - * Set SDRAM calibration. Make DFI Control Update Setting settings. - * In the case of WARM_BOOT, cancel the self-refresh setting. - * Enable SDRAM auto refresh. Set up PHY Periodic Write DQ training. - * Enable access to SDRAM. - */ -static void dbsc5_dbsc_regset_post(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - /* Average periodic refresh interval/Average Refresh Interval [ns] */ - const u32 dbsc_refint = 1920; - /* 0: Average interval is REFINT, 1: Average interval is 1/2 REFINT */ - const u32 dbsc_refints = 0; - /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ - const u32 periodic_training_interval = 20000; - u32 phymster_req_interval; - u32 ch, slice; - u32 clk_count; - u32 refcycle; - u32 ctrl_clk; - u32 reg; - - if ((renesas_get_cpu_rev_integer() < 3) && priv->ch_have_this_cs[1]) { - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - dbsc5_ddr_setval_slice(dev, ch, slice, - PHY_PER_CS_TRAINING_EN, - 0x0); - } - } - } - - dbsc5_reg_write(regs_dbsc_d + DBSC_DBDBICNT, 0x3); - - /* set REFCYCLE */ - refcycle = dbsc_refint * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; - /* refpmax=8 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF1, (refcycle & 0xFFFF) | BIT(19)); - /* refpmin=1 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF2, dbsc_refints | BIT(16)); - - dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x0); - - /* Periodic-WriteDQ Training setting */ - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_VREF_EN, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_WDQLVL_ENABLE, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_PERIODIC, 0x1); - - /* Periodic-ReadDQ Training setting */ - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDLVL_DLY_STEP, 0x4); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_PERIODIC, 0x1); - - /* DFI_PHYMSTR_ACK , WTmode = b'01 */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x11); - - /* periodic SoC zqcal enable */ - reg = dbsc5_ddrtbl_getval(priv->DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0, false); - dbsc5_ddr_setval_all_ch(dev, PHY_CAL_MODE_0, reg | BIT(1)); - - /* Periodic dram zqcal enable */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBCALCNF, 0x1000010); - - /* Periodic phy ctrl update enable */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFICUPDCNF, 0x504C0001); - - /* Set Auto Refresh */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFEN, 0x1); - - /* Periodic-WriteDQ/ReadDQ Training Interval setting */ - phymster_req_interval = periodic_training_interval - 3000; - clk_count = 1024 - (dbsc5_ddrtbl_getval(priv->DDR_PI_REGSET, PI_LONG_COUNT_MASK, true) * 32); - ctrl_clk = priv->ddr_mbps / priv->ddr_mbpsdiv / 8; - reg = phymster_req_interval * ctrl_clk / clk_count; - - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_INTERVAL, reg); - - /* DRAM access enable */ - dbsc5_reg_write(regs_dbsc_a + DBSC_DBACEN, 0x1); -} - -/** - * dbsc5_pi_training() - Training by PI - * @dev: DBSC5 device - * - * Enable WCK signal training and read gate training. Start PI training. - * After DFI initialization for all channels is once turned off, turned - * on all chennels of it. Power down the DRAM device once and then release - * the power down mode. Perform training in low frequency mode and training - * in high frequency mode. Wait for the DFI training completion status - * bit to stand until the time limit. Turn off DFI initialization for all - * channels. Turn off WTMODE of DFI PHY. Check if CA/CS Training has failed. - * Check if Wrlvl training is in error. If an error can be confirmed from - * the check result, the result is returned as a return value. Clear the - * status register for PI training. - */ -static u32 dbsc5_pi_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - const int retry_max = 0x10000; - u32 ca_training_ng = 0; - u32 wr_training_ng = 0; - u32 phytrainingok = 0; - u32 complete_ng = 0; - bool frqchg_req; - u32 ch, reg; - int retry; - int ret; - - /* Init start */ - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_9, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_10, 0x0); - - /* PI_START */ - dbsc5_ddr_setval_all_ch(dev, PI_START, 0x1); - - r_foreach_vch(dev, ch) - writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); - - r_foreach_vch(dev, ch) - writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch)); - - /* Dummy PDE */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD, - DBSC_DBCMD_CMD_CHANNEL_ALL, - DBSC_DBCMD_CMD_RANK_ALL, 0); - - /* PDX */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD, - DBSC_DBCMD_CMD_CHANNEL_ALL, - DBSC_DBCMD_CMD_RANK_ALL, 1); - - /* Wait init_complete */ - for (retry = 0; retry < retry_max; retry++) { - frqchg_req = false; - for (ch = 0; ch < DRAM_CH_CNT; ch++) { - if (!((~phytrainingok & priv->ddr_phyvalid) & BIT(ch))) - continue; - - if (!(readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)) & BIT(0))) - continue; - - frqchg_req = true; - break; - } - - if (frqchg_req) { - ret = dbsc5_clk_pll3_freq(dev); - if (ret) - break; - } else { - r_foreach_vch(dev, ch) { - if (readl(regs_dbsc_d + DBSC_DBDFISTAT(ch)) & BIT(0)) - phytrainingok |= BIT(ch); - } - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - } - - /* - * dbdficnt0: - * dfi_dram_clk_disable=0 - * dfi_frequency = 0 - * freq_ratio = 10 (4:1) - * init_start =0 - */ - r_foreach_vch(dev, ch) - writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); - - /* DFI_PHYMSTR_ACK */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x1); - - /* Error check */ - r_foreach_vch(dev, ch) { - /* CA/CS Training Error Check */ - /* PI_CALVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(4); - /* Error on decrement/increment pass */ - reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS1) & (0x3 << 30); - /* Start outside of initial search range */ - reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS2) & (0x3 << 24); - /* CSlvl error */ - reg |= dbsc5_ddr_getval(dev, ch, PHY_CSLVL_OBS1) & (0xF << 28); - if (reg) { - ca_training_ng |= BIT(ch); - printf("%s pi_training_error:1\n", __func__); - } - - /* Wrlvl Error Check */ - /* PI_WRLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); - if (reg) { - wr_training_ng |= BIT(ch); - printf("%s pi_training_error:2\n", __func__); - } - } - - complete_ng = (wr_training_ng | ca_training_ng); - if (complete_ng) - return ~complete_ng; - - /* PI_INT_ACK assert */ - r_foreach_vch(dev, ch) { - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); - } - - return phytrainingok; -} - -/** - * dbsc5_write_leveling_adjust() - Write Leveling Cycle Adjust - * @dev: DBSC5 device - * - * Get delay value from the result write leveling of slice 0 and 1. - * Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask - * signals based on delay values. - */ -static void dbsc5_write_leveling_adjust(struct udevice *dev) -{ - u32 result_hard0, result_hard1; - u32 avg, avg_frac, avg_cycle; - u32 ch; - - r_foreach_vch(dev, ch) { - /* SLICE0 */ - result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD0_DELAY_OBS); - result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD1_DELAY_OBS); - - avg = result_hard0 + result_hard1; - if (result_hard0 > result_hard1) - avg += 0x400; - avg /= 2; - - avg_frac = avg & 0xFF; - avg_cycle = (avg >> 8) & 0x3; - - if (avg_cycle == 0x3) { - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x1); - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, 0x0); - } else { - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x0); - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, avg_cycle); - } - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_FRAC, avg_frac); - - /* SLICE1 */ - result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD0_DELAY_OBS); - result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD1_DELAY_OBS); - - avg = result_hard0 + result_hard1; - if (result_hard0 >= result_hard1) - avg += 0x400; - avg /= 2; - avg_frac = avg & 0xFF; - avg_cycle = (avg >> 8) & 0x3; - - if (avg_cycle == 0x3) { - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x1); - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, 0x0); - } else { - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x0); - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, avg_cycle); - } - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_FRAC, avg_frac); - } - - dbsc5_ddr_setval_all_ch_all_slice(dev, SC_PHY_WCK_CALC, 0x1); -} - -/** - * dbsc5_wl_gt_training() - Re-run Write Leveling & Read Gate Training - * @dev: DBSC5 device - * - * Set CA leveling OFF, read gate leveling ON, write gate leveling ON, - * PI dram wck training ON. Perform PI_DFS configuration. Start PI - * frequency training in manual mode. Perform training in high-frequency - * mode. Check for Write leveling Error and Gate leveling Error. If an - * error is identified, the resulting value is inverted and returned. - * Clear the PI status register. - */ -static u32 dbsc5_wl_gt_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const int retry_max = 0x10000; - u32 gt_training_ng = 0; - u32 wr_training_ng = 0; - u32 phytrainingok = 0; - u32 complete_ng = 0; - int retry, ret; - u32 ch, reg; - - dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); - - dbsc5_ddr_setval_all_ch(dev, PI_DFS_ENTRY_SEQ_0, 0x181F0000); - dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_1, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); - - /* Freq Change High to High*/ - ret = dbsc5_clk_pll3_freq(dev); - if (ret) - return ret; - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - /* Error Check */ - r_foreach_vch(dev, ch) { - /* Wrlvl Error Check */ - /* PI_WRLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); - if (reg) { - wr_training_ng |= BIT(ch); - printf("%s wl_gt_training_error:1\n", __func__); - } - - /* Gtlvl Error Check */ - /* PI_RDLVL_GATE_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2); - /* SLICE0 delay setup error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); - /* SLICE1 delay setup error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); - if (reg) { - gt_training_ng |= BIT(ch); - printf("%s wl_gt_training_error:2\n", __func__); - } - } - - complete_ng = (wr_training_ng | gt_training_ng); - if (complete_ng) - return ~complete_ng; - - /* PI_INT_ACK assert */ - r_foreach_vch(dev, ch) { - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); - } - - return phytrainingok; -} - -/** - * dbsc5_pi_int_ack_0_assert() - Training handshake functions - * @dev: DBSC5 device - * @bit: Status bit to poll - * - * Wait for the status bit specified in the argument to become 1 until the - * time limit. After checking status bits on all channels, clear the target - * status bits and returns the result of the check as the return value. - */ -static u32 dbsc5_pi_int_ack_0_assert(struct udevice *dev, u32 bit) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const int retry_max = 0x10000; - u32 ch, phytrainingok = 0; - int retry; - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(bit)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - if (phytrainingok != priv->ddr_phyvalid) - return phytrainingok; - - r_foreach_vch(dev, ch) - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, BIT(bit)); - - return phytrainingok; -} - -/** - * dbsc5_write_dca() - Write DCA Training - * @dev: DBSC5 device - * - * Get DCA Training CS0 Flip-0 training results for RANK0. - * Get DCA Training CS1 Flip-0 training results for RANK0. - * Calculate DRAMDCA settings from training results and write - * them to registers. Set DRAM DCA in MR30. Ensure that the - * training has been successfully completed. Clear CA status - * to 0. - */ -static void dbsc5_write_dca(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const int retry_max = 0x10000; - u32 phytrainingok = 0; - u32 ch, reg; - int retry; - - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_CAL_START, 0x1); - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) { - reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_DATA_DC_CAL_START) | - dbsc5_ddr_getval_slice(dev, ch, 1, PHY_DATA_DC_CAL_START); - if (!reg) - phytrainingok |= BIT(ch); - } - - if (phytrainingok == priv->ddr_phyvalid) - break; - } -} - -/** - * dbsc5_dramdca_training() - DRAM DCA Training and Calculations - * @dev: DBSC5 device - * - * Get DCA Training CS0 Flip-0 training results for RANK0. - * Get DCA Training CS1 Flip-0 training results for RANK0. - * Calculate DRAMDCA settings from training results and write - * them to registers. Set DRAM DCA in MR30. Ensure that the - * training has been successfully completed. Clear CA status - * to 0. - */ -static u32 dbsc5_dramdca_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; - const u32 mr30_conv[16] = { - 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, - 0x0, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF - }; - u32 dca_result_l_0[DRAM_CH_CNT][CS_CNT]; - u32 dca_result_u_0[DRAM_CH_CNT][CS_CNT]; - u32 dca_result_l_1[DRAM_CH_CNT][CS_CNT]; - u32 dca_result_u_1[DRAM_CH_CNT][CS_CNT]; - u32 ch, phytrainingok, reg; - u32 tempu, templ; - - /* Run DRAM DCA Training for Flip-0 */ - dbsc5_ddr_setval_all_ch(dev, PI_DCMLVL_CS_SW, rank); - - /* DRAMDCA go */ - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); - - /* PI_INT_ACK assert */ - phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); - if (phytrainingok != priv->ddr_phyvalid) - return phytrainingok; - - /* Result for DRAMDCA flip-0 */ - r_foreach_vch(dev, ch) { - reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); - dca_result_u_0[ch][0] = mr30_conv[reg >> 4]; - dca_result_l_0[ch][0] = mr30_conv[reg & 0xF]; - if (!(rank & 0x2)) - continue; - - reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); - dca_result_u_0[ch][1] = mr30_conv[reg >> 4]; - dca_result_l_0[ch][1] = mr30_conv[reg & 0xF]; - } - - /* Run DRAM DCA Training for Flip-1 */ - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x1); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x0); - - /* DRAMDCA go */ - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); - - /* PI_INT_ACK assert */ - phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); - if (phytrainingok != priv->ddr_phyvalid) - return phytrainingok; - - /* Result for DRAMDCA flip-1 */ - r_foreach_vch(dev, ch) { - reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); - dca_result_u_1[ch][0] = mr30_conv[reg >> 4]; - dca_result_l_1[ch][0] = mr30_conv[reg & 0xF]; - if (!(rank & 0x2)) - continue; - - reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); - dca_result_u_1[ch][1] = mr30_conv[reg >> 4]; - dca_result_l_1[ch][1] = mr30_conv[reg & 0xF]; - } - - /* Calculate and set DRAMDCA value */ - r_foreach_vch(dev, ch) { - /* CS0 */ - tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2; - templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2; - reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; - dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS0_F2, reg); - if (!(rank & 0x2)) - continue; - - /* CS1 */ - tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2; - templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2; - reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; - dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS1_F2, reg); - } - - /* Set DRAMDCA value in MR30 */ - dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_0, 0x1A11E14); - dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_1, 0x1F0000); - dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, rank); - dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_START, 0x1); - - /* PI_INT_ACK assert */ - phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 19); - if (phytrainingok != priv->ddr_phyvalid) - return phytrainingok; - - dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x2); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x1101FC); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x211A00); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x51500); - - return phytrainingok; -} - -/** - * dbsc5_write_leveling() - Re-run Write Leveling - * @dev: DBSC5 device - * - * CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA - * training is set to OFF. Set the memory rank for the Write leveling target - * and start leveling. Wait until leveling is complete. - * - * Check for Write leveling errors. If an error is confirmed to have occurred, - * the result is returned as a return value. Clear the PI status bit. - */ -static u32 dbsc5_write_leveling(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; - const int retry_max = 0x10000; - u32 wr_training_ng = 0; - u32 phytrainingok = 0; - u32 ch, reg; - int retry; - - dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_CS_SW, rank); - dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_REQ, 0x1); - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(29)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - /* Error check */ - r_foreach_vch(dev, ch) { - /* Wrlvl Error Check */ - /* PI_WRLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); - /* SLICE0 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); - /* SLICE1 wrlvl error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); - if (reg) { - wr_training_ng |= BIT(ch); - printf("%s write_leveling_error:1\n", __func__); - } - } - - if (wr_training_ng) - return ~wr_training_ng; - - /* PI_INT_ACK assert */ - r_foreach_vch(dev, ch) { - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); - } - - return phytrainingok; -} - -/** - * dbsc5_manual_write_dca() - Manual Write DCA Training - * @dev: DBSC5 device - * - * Write DCA training according to memory rank. - */ -static void dbsc5_manual_write_dca(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1; - u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; - u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; - u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; - u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; - u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; - u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; - u32 phy_dcc_code_mid; - const int retry_max = 0x10000; - const u8 ratio_min_div = 0xA; - const u8 ratio_max_div = 0x2; - const u8 ratio_min = 0x6; - const u8 ratio_max = 0x3; - u32 ch, cs, slice, tmp; - u32 complete = 0; - int i, retry; - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - phy_dcc_code_min[ch][slice] = 0x7F; - phy_dcc_code_max[ch][slice] = 0x0; - } - } - - for (cs = 0; cs < rank; cs++) { - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - phy_slv_dly[ch][cs][slice] = - dbsc5_ddr_getval_slice(dev, ch, slice, - PHY_CLK_WRDQS_SLAVE_DELAY); - } - } - } - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - if (rank == 0x2) { - /* Calculate average between ranks */ - phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + - phy_slv_dly[ch][1][slice]) / 2; - } else { - phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; - } - /* Determine the search range */ - slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div; - slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div; - if (slv_dly_max[ch][slice] > 0x7F) - slv_dly_max[ch][slice] = 0x7F; - } - } - - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1); - - for (i = 0; i <= 0x7F; i++) { - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) { - complete |= BIT(ch) << (8 * slice); - } else { - /* CS0/1 same setting, Need masked write */ - dbsc5_ddr_setval_slice(dev, ch, slice, - PHY_CLK_WRDQS_SLAVE_DELAY, - slv_dly_min[ch][slice] + i); - dbsc5_ddr_setval_slice(dev, ch, slice, SC_PHY_WCK_CALC, 0x1); - dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); - } - } - } - - if (complete == (priv->ddr_phyvalid | (priv->ddr_phyvalid << 8))) - break; - - /* Execute write dca */ - r_foreach_vch(dev, ch) - for (slice = 0; slice < SLICE_CNT; slice++) - if (!(((complete >> (8 * slice)) >> ch) & 0x1)) - dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DATA_DC_CAL_START, 0x1); - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - if (!(((complete >> (8 * slice)) >> ch) & 0x1)) { - for (retry = 0; retry < retry_max; retry++) { - tmp = dbsc5_ddr_getval_slice(dev, ch, slice, - PHY_DATA_DC_CAL_START); - if (!tmp) - break; - } - } - } - } - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - if ((slv_dly_min[ch][slice] + i) > slv_dly_max[ch][slice]) - continue; - - tmp = (dbsc5_ddr_getval_slice(dev, ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); - if ((tmp >> 6) == 0x1) - tmp = 0x0; - else if ((tmp >> 6) == 0x2) - tmp = 0x3F; - - if (tmp < phy_dcc_code_min[ch][slice]) - phy_dcc_code_min[ch][slice] = tmp; - - if (phy_dcc_code_max[ch][slice] < tmp) - phy_dcc_code_max[ch][slice] = tmp; - } - } - } - - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); - for (cs = 0; cs < rank; cs++) { - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - dbsc5_ddr_setval_slice(dev, ch, slice, - PHY_CLK_WRDQS_SLAVE_DELAY, - phy_slv_dly[ch][cs][slice]); - dbsc5_ddr_setval_slice(dev, ch, slice, - SC_PHY_WCK_CALC, 0x1); - dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); - } - } - } - - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0); - - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1); - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + - phy_dcc_code_max[ch][slice]) / 2; - dbsc5_ddr_setval_slice(dev, ch, slice, - PHY_DATA_DC_DQS_CLK_ADJUST, - phy_dcc_code_mid); - } - } -} - -/** - * dbsc5_read_gate_training() - Re-run read gate training by PI - * @dev: DBSC5 device - * - * Write leveling set to OFF, read gate leveling set to ON. Set memory rank - * for leveling target, turn on read gate leveling. Wait for leveling to be - * completed until the time limit. Check for errors during gate leveling. - * - * If an error is confirmed to have occurred, the result is returned as a - * return value. Clear the PI status register. - */ -static u32 dbsc5_read_gate_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; - const int retry_max = 0x10000; - u32 gt_training_ng = 0; - u32 phytrainingok = 0; - u32 ch, reg; - int retry; - - dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_REQ, 0x1); - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(24)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - /* Error Check */ - r_foreach_vch(dev, ch) { - /* Gtlvl Error Check */ - /* PI_RDLVL_GATE_ERROR_BIT */ - reg = (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2)); - /* SLICE0 delay setup error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); - /* SLICE1 delay setup error */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); - if (reg) { - gt_training_ng |= BIT(ch); - printf("%s read_gate_training_error\n", __func__); - } - } - - if (gt_training_ng) - return ~gt_training_ng; - - /* PI_INT_ACK assert */ - r_foreach_vch(dev, ch) { - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); - } - - return phytrainingok; -} - -/** - * dbsc5_read_vref_training() - Read Data Training with VREF Training - * @dev: DBSC5 device - * - * Set reading leveling to ON and Vref leveling of reading to OFF. - * Set Vref reading training to OFF. Get start value, end value and - * number of steps for Vref training. Determine the optimal VREFSEL - * value while increasing the Vref training setpoint by the starting - * value+step value. - */ -static u32 dbsc5_read_vref_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; - u32 best_dvw_min_byte0, best_dvw_min_byte1; - u32 dvw_min_byte0_table[DRAM_CH_CNT][128]; - u32 dvw_min_byte1_table[DRAM_CH_CNT][128]; - u32 dvw_min_byte0[DRAM_CH_CNT] = { 0 }; - u32 dvw_min_byte1[DRAM_CH_CNT] = { 0 }; - u32 best_lower_vref, best_upper_vref; - u32 best_vref_byte0, best_vref_byte1; - u32 vref_start, vref_stop, vref_step; - u32 best_vref_byte0_index = 0; - u32 best_vref_byte1_index = 0; - const int retry_max = 0x10000; - u32 win_byte0, win_byte1; - u32 phytrainingok = 0; - u32 vref_stop_index; - u32 temple, tempte; - u32 best_thrshld; - u32 vref_outlier; - u32 outlier_cnt; - u32 curr_rank; - int i, retry; - u32 obs_sel; - u32 ch, reg; - - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F0, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F1, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_VREF_TRAINING_CTRL, 0x0); - - /* ch0 vref_point */ - vref_start = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_START_POINT); - vref_stop = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STOP_POINT); - vref_step = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STEPSIZE); - vref_stop_index = (vref_stop - vref_start) / vref_step; - - if (vref_stop_index > 0x80) - return 0; - - for (i = 0; i < vref_stop_index; i++) { - r_foreach_vch(dev, ch) { - reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); - reg &= 0xF << 10; - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, - reg | BIT(9) | (vref_start + (vref_step * i))); - reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); - reg &= 0xF << 10; - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, - reg | BIT(9) | (vref_start + (vref_step * i))); - } - - for (curr_rank = 0; curr_rank < rank; curr_rank++) { - /* All ch Read Training Start */ - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, BIT(curr_rank)); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); - - phytrainingok = 0; - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(25)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - /* Read Training End */ - dbsc5_ddr_setval_all_ch(dev, PI_INT_ACK_0, BIT(25)); - - r_foreach_vch(dev, ch) { - /* minimum Data Valid Window for each VREF */ - dvw_min_byte0[ch] = 0xFFFFFFFF; - dvw_min_byte1[ch] = 0xFFFFFFFF; - for (obs_sel = 0x0; obs_sel < 0x19; obs_sel++) { - if (!((obs_sel < 0x11) || (obs_sel == 0x18))) - continue; - - dbsc5_ddr_setval_slice(dev, ch, 0, - PHY_RDLVL_RDDQS_DQ_OBS_SELECT, - obs_sel); - dbsc5_ddr_setval_slice(dev, ch, 1, - PHY_RDLVL_RDDQS_DQ_OBS_SELECT, - obs_sel); - - temple = dbsc5_ddr_getval_slice(dev, ch, 0, - PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); - tempte = dbsc5_ddr_getval_slice(dev, ch, 0, - PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); - if (tempte > temple) - win_byte0 = tempte - temple; - else - win_byte0 = 0; - - temple = dbsc5_ddr_getval_slice(dev, ch, 1, - PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); - tempte = dbsc5_ddr_getval_slice(dev, ch, 1, - PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); - if (tempte > temple) - win_byte1 = tempte - temple; - else - win_byte1 = 0; - - if (dvw_min_byte0[ch] > win_byte0) - dvw_min_byte0[ch] = win_byte0; - - if (dvw_min_byte1[ch] > win_byte1) - dvw_min_byte1[ch] = win_byte1; - } - } - } - - r_foreach_vch(dev, ch) { - dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; - dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; - } - } - - r_foreach_vch(dev, ch) { - /* Search best VREF byte0 */ - best_vref_byte0 = vref_start; - best_vref_byte0_index = 0; - best_dvw_min_byte0 = dvw_min_byte0_table[ch][0]; - - for (i = 0; i < vref_stop_index; i++) { - if (best_dvw_min_byte0 >= dvw_min_byte0_table[ch][i]) - continue; - - best_vref_byte0 = vref_start + (vref_step * i); - best_vref_byte0_index = i; - best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; - } - - /* Search best_lower VREF byte0 */ - reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_DLY_STEP); - if (reg == 0) - reg = 1; - best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_BEST_THRSHLD) * reg; - - vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); - best_lower_vref = best_vref_byte0; - outlier_cnt = vref_outlier; - for (i = best_vref_byte0_index; i >= 0; i--) { - if (dvw_min_byte0_table[ch][i] <= 0) - break; - - if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { - best_lower_vref = vref_start + (vref_step * i); - } else { - if (outlier_cnt > 0) - outlier_cnt--; - else - break; - } - - if (i == 0) - break; - } - - /* Search best_upper VREF byte0 */ - vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); - best_upper_vref = best_vref_byte0; - outlier_cnt = vref_outlier; - for (i = best_vref_byte0_index; i < vref_stop_index; i++) { - if (dvw_min_byte0_table[ch][i] <= 0) - break; - - if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { - best_upper_vref = vref_start + (vref_step * i); - } else { - if (outlier_cnt > 0) - outlier_cnt--; - else - break; - } - } - - /* Calculate center of best vref range byte0 */ - best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2; - - /* Search best VREF byte1 */ - best_vref_byte1 = vref_start; - best_vref_byte1_index = 0; - best_dvw_min_byte1 = dvw_min_byte1_table[ch][0]; - for (i = 0; i < vref_stop_index; i++) { - if (best_dvw_min_byte1 >= dvw_min_byte1_table[ch][i]) - continue; - - best_vref_byte1 = vref_start + (vref_step * i); - best_vref_byte1_index = i; - best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; - } - - /* Search best_lower VREF byte1 */ - reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_DLY_STEP); - if (reg == 0) - reg = 1; - best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_BEST_THRSHLD) * reg; - - vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); - best_lower_vref = best_vref_byte1; - outlier_cnt = vref_outlier; - for (i = best_vref_byte1_index; i >= 0; i--) { - if (dvw_min_byte1_table[ch][i] <= 0) - break; - - if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { - best_lower_vref = vref_start + (vref_step * i); - } else { - if (outlier_cnt > 0) - outlier_cnt--; - else - break; - } - - if (i == 0) - break; - } - - /* Search best_upper VREF byte1 */ - vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); - best_upper_vref = best_vref_byte1; - outlier_cnt = vref_outlier; - for (i = best_vref_byte1_index; i < vref_stop_index; i++) { - if (dvw_min_byte1_table[ch][i] <= 0) - break; - - if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { - best_upper_vref = vref_start + (vref_step * i); - } else { - if (outlier_cnt > 0) - outlier_cnt--; - else - break; - } - } - - /* Calculate center of best vref range byte1 */ - best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2; - - reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); - reg &= 0xF << 10; - dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, - reg | BIT(9) | best_vref_byte0); - reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); - reg &= 0xF << 10; - dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, - reg | BIT(9) | best_vref_byte1); - } - - return phytrainingok; -} - -/** - * dbsc5_read_write_training() - Read Data & RDDQ Training with best VREF & Write DQ VREF Training - * @dev: DBSC5 device - * - * Set read DQS/RDQS slave delay setting to 0. Write leveling set to OFF, - * read gate leveling set to OFF. Turn on read and write leveling. Start - * frequency training. Training in high-frequency mode. Wait until training - * is complete. Check for errors in write dq leveling and read leveling. - - * If an error is confirmed to have occurred, return the inverted result - * value. Clear the PI status register. - */ -static u32 dbsc5_read_write_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const int retry_max = 0x10000; - u32 wdq_training_ng = 0; - u32 rd_training_ng = 0; - u32 phytrainingok = 0; - u32 complete_ng = 0; - int retry, ret; - u32 ch, reg; - - /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ0_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ1_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ2_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ3_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ4_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ5_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ6_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ7_SLAVE_DELAY, 0x0); - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDM_SLAVE_DELAY, 0x0); - - dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); - dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); - - dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); - - /* Freq Change High to High*/ - ret = dbsc5_clk_pll3_freq(dev); - if (ret) - return ret; - - for (retry = 0; retry < retry_max; retry++) { - r_foreach_vch(dev, ch) - if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) - phytrainingok |= BIT(ch); - - if (phytrainingok == priv->ddr_phyvalid) - break; - } - - /* Error Check */ - r_foreach_vch(dev, ch) { - /* Rdlvl Error Check */ - /* PI_RDLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); - if (reg) { - rd_training_ng |= BIT(ch); - printf("%s read_write_training_error:1\n", __func__); - } - - /* Wdqlvl Error Check */ - /* PI_WDQLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(5); - /* SLICE0 wdqlvl_fail_dqZ */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); - /* SLICE1 wdqlvl_fail_dqZ */ - reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); - if (reg) { - wdq_training_ng |= BIT(ch); - printf("%s read_write_training_error:2\n", __func__); - } - } - - complete_ng = wdq_training_ng | rd_training_ng; - if (complete_ng) - return ~complete_ng; - - /* PI_INT_ACK assert */ - r_foreach_vch(dev, ch) { - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); - dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); - } - - return phytrainingok; -} - -/** - * dbsc5_read_training() - Correct RDDQ Training result & Re-Run Read Data Training - * @dev: DBSC5 device - * - * Set the Read DQ correction value and its upper limit from the board - * settings. Check DDR memory ranks. Add the offset value to the current - * Read DQ value and write it to the register. Write the setting value - * to PI_RDLVL_TRAIN_SEQ_x. Start the Read training. PI_INT_ACK assert. - * Execute the Rdlvl Error Check. Confirm that training has been successfully - * completed. Return the result of the confirmation as the return value. - */ -static u32 dbsc5_read_training(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; - const u32 rddq_delay_offset_ps = 0x19; - const u32 rddq_delay_max_ps = 0x67; - const u32 rddq_delay_addr[] = { - PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, - PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, - PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY - }; - const u32 rddq_delay_offset = rddq_delay_offset_ps * priv->ddr_mbps * 256 / - (priv->ddr_mbpsdiv * 2 * 1000000); - const u32 rddq_delay_max = rddq_delay_max_ps * priv->ddr_mbps * 256 / - (priv->ddr_mbpsdiv * 2 * 1000000); - u32 rd_training_ng = 0; - u32 ch, reg, slice; - u32 phytrainingok; - int i; - - r_foreach_vch(dev, ch) { - for (slice = 0; slice < SLICE_CNT; slice++) { - for (i = 0; i < 9; i++) { - reg = dbsc5_ddr_getval_slice(dev, ch, slice, - rddq_delay_addr[i]) + - rddq_delay_offset; - if (reg > rddq_delay_max) - reg = rddq_delay_max; - dbsc5_ddr_setval_slice(dev, ch, slice, rddq_delay_addr[i], reg); - } - } - } - - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_1, 0x89080); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_2, 0x811C0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_3, 0x40811C0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_4, 0x2000000); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_5, 0x0); - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); - - /* Read training go */ - dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); - - /* PI_INT_ACK assert */ - phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 25); - if (phytrainingok != priv->ddr_phyvalid) - return phytrainingok; - - /* Error Check */ - r_foreach_vch(dev, ch) { - /* Rdlvl Error Check */ - /* PI_RDLVL_ERROR_BIT */ - reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); - if (reg) { - rd_training_ng |= BIT(ch); - printf("%s read_training_error\n", __func__); - } - } - - if (rd_training_ng) - return ~rd_training_ng; - - return phytrainingok; -} - -/** - * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set - * @dev: DBSC5 device - * - * Set the mode register 28 of the SDRAM. - * ZQ Mode: Command-Based ZQ Calibration - * ZQ interval: Background Cal Interval < 64ms - */ -static void dbsc5_ddr_register_mr28_set(struct udevice *dev) -{ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRW, - DBSC_DBCMD_CMD_CHANNEL_ALL, - DBSC_DBCMD_CMD_RANK_ALL, (28 << 8) | 0x24); -} - -/** - * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read - * @dev: DBSC5 device - * - * Set the mode register 27 and 57 of the SDRAM. - */ -static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - - if (!priv->dbsc5_board_config->bdcfg_rfm_chk) - return; - - /* MR27 rank0 */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, - DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 27 << 8); - /* MR57 rank0 */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, - DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 57 << 8); - - if (!priv->ch_have_this_cs[1]) - return; - - /* MR27 rank1 */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, - DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 27 << 8); - /* MR57 rank1 */ - dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, - DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 57 << 8); -} - -/** - * dbsc5_init_ddr() - Initialize DDR - * @dev: DBSC5 device - * - * Status monitor and perform reset and software reset for DDR. - * Disable DDRPHY software reset. Unprotect the DDRPHY register. - * Perform pre-setting of DBSC registers. Configure the ddrphy - * registers. Process ddr backup. Set DBSC registers. - * - * Initialize DFI and perform PI training. Setup DDR mode registers - * pre-traning. Adjust number of write leveling cycles. Perform PI - * training in manual mode. Perform DRAM DCA training. Perform write - * leveling. Execute phydca training. Execute read gate training. - * - * Perform Vref training on read gate. Read DQ Write DQ Execute. - * Frequency selection change (F1->F2). Disable the FREQ_SEL_MULTICAST & - * PER_CS_TRAINING_MULTICAST. Start setting DDR mode registers. Set DBSC - * registers after training is completed. Set write protection for PHY - * registers. - */ -static u32 dbsc5_init_ddr(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - u32 phytrainingok; - u32 ch, val; - int ret; - - /* PLL3 initialization setting */ - /* Reset Status Monitor clear */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); - /* Reset Status Monitor set */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKSETR4, 0x600); - /* ddrphy soft reset assert */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRCR4, readl(priv->cpg_regs + CPG_SRCR4) | 0x600); - /* Wait reset FB */ - ret = readl_poll_timeout(priv->cpg_regs + CPG_FSRCHKRA4, val, ((val & 0x600) == 0), 1000000); - if (ret < 0) { - printf("%s CPG_FSRCHKRA4 Wait reset FB timeout\n", __func__); - hang(); - } - /* Reset Status Monitor clear */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); - - /* Initialize PLL3 setting */ - dbsc5_clk_pll3_control(dev, PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); - - /* DDRPHY soft reset negate */ - dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRSTCLR4, 0x600); - ret = readl_poll_timeout(priv->cpg_regs + CPG_SRCR4, val, ((val & 0x600) == 0), 1000000); - if (ret < 0) { - printf("%s CPG_SRCR4 DDRPHY soft reset negate timeout\n", __func__); - hang(); - } - - /* Unlock PHY */ - /* Unlock DDRPHY register */ - r_foreach_vch(dev, ch) - writel(0xA55A, regs_dbsc_d + DBSC_DBPDLK(ch)); - - /* DBSC register pre-setting */ - dbsc5_dbsc_regset_pre(dev); - - /* Load DDRPHY registers */ - dbsc5_ddrtbl_calc(priv); - dbsc5_ddrtbl_load(dev); - - /* Configure ddrphy registers */ - dbsc5_ddr_config(dev); - - /* DDR backupmode end */ - - /* DBSC register set */ - dbsc5_dbsc_regset(dev); - - /* Frequency selection change (F1->F2) */ - dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1); - dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0); - - /* dfi_init_start (start ddrphy) & execute pi_training */ - phytrainingok = dbsc5_pi_training(dev); - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:1\n", __func__); - return phytrainingok; - } - - /* Write leveling cycle adjust */ - dbsc5_write_leveling_adjust(dev); - - /* Execute write leveling & read gate training */ - phytrainingok = dbsc5_wl_gt_training(dev); - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:2\n", __func__); - return phytrainingok; - } - - /* Execute write dca training */ - dbsc5_write_dca(dev); - - /* Execute dram dca training */ - phytrainingok = dbsc5_dramdca_training(dev); - - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:3\n", __func__); - return phytrainingok; - } - - /* Execute write leveling */ - phytrainingok = dbsc5_write_leveling(dev); - - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:4\n", __func__); - return phytrainingok; - } - - /* Execute manual write dca training */ - dbsc5_manual_write_dca(dev); - - /* Execute read gate training */ - phytrainingok = dbsc5_read_gate_training(dev); - - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:5\n", __func__); - return phytrainingok; - } - - /* Execute read vref training */ - phytrainingok = dbsc5_read_vref_training(dev); - - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:6\n", __func__); - return phytrainingok; - } - - /* Execute read dq & write dq training with best vref */ - phytrainingok = dbsc5_read_write_training(dev); - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:7\n", __func__); - return phytrainingok; - } - - /* correct rddq training result & Execute read dq training */ - phytrainingok = dbsc5_read_training(dev); - - if (priv->ddr_phyvalid != phytrainingok) { - printf("%s init_ddr_error:8\n", __func__); - return phytrainingok; - } - - /* PER_CS_TRAINING_MULTICAST SET (disable) */ - dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); - - /* setup DDR mode registers */ - /* MRS */ - dbsc5_ddr_register_mr28_set(dev); - - /* MRR */ - dbsc5_ddr_register_mr27_mr57_read(dev); - - /* training complete, setup DBSC */ - dbsc5_dbsc_regset_post(dev); - - /* Lock PHY */ - /* Lock DDRPHY register */ - r_foreach_vch(dev, ch) - writel(0x0, regs_dbsc_d + DBSC_DBPDLK(ch)); - - return phytrainingok; -} - -/** - * dbsc5_get_board_data() - Obtain board specific DRAM configuration - * @dev: DBSC5 device - * @modemr0: MODEMR0 register content - * - * Return board specific DRAM configuration structure pointer. - */ -__weak const struct renesas_dbsc5_board_config * -dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) -{ - return &renesas_v4h_dbsc5_board_config; -} - -/** - * renesas_dbsc5_dram_probe() - DDR Initialize entry - * @dev: DBSC5 device - * - * Remove write protection on DBSC register. Read DDR configuration - * information from driver data. Calculate board clock frequency and - * operating frequency from DDR configuration information. Call the - * main function of DDR initialization. Perform DBSC write protection - * after initialization is complete. - */ -static int renesas_dbsc5_dram_probe(struct udevice *dev) -{ -#define RST_MODEMR0 0x0 -#define RST_MODEMR1 0x4 -#define OTP_MONITOR17 0x1144 - struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev); - ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node); - ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node); - ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node); - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; - void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; - phys_addr_t rregs = ofnode_get_addr(rnode); - const u32 modemr0 = readl(rregs + RST_MODEMR0); - const u32 modemr1 = readl(rregs + RST_MODEMR1); - phys_addr_t oregs = ofnode_get_addr(onode); - const u32 otpmon17 = readl(oregs + OTP_MONITOR17); - u32 breg, reg, md, sscg, product; - u32 ch, cs; - - /* Get board data */ - priv->dbsc5_board_config = dbsc5_get_board_data(dev, modemr0); - priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); - priv->max_density = 0; - priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode); - - for (cs = 0; cs < CS_CNT; cs++) - priv->ch_have_this_cs[cs] = 0; - - r_foreach_ech(ch) - for (cs = 0; cs < CS_CNT; cs++) - priv->ddr_density[ch][cs] = 0xFF; - - r_foreach_vch(dev, ch) { - for (cs = 0; cs < CS_CNT; cs++) { - priv->ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; - - if (priv->ddr_density[ch][cs] == 0xFF) - continue; - - if (priv->ddr_density[ch][cs] > priv->max_density) - priv->max_density = priv->ddr_density[ch][cs]; - - priv->ch_have_this_cs[cs] |= BIT(ch); - } - } - - /* Decode board clock frequency from MD[14:13] pins */ - priv->brd_clkdiv = 3; - - breg = (modemr0 >> 13) & 0x3; - if (breg == 0) { - priv->brd_clk = 50; /* 16.66 MHz */ - priv->bus_clk = priv->brd_clk * 0x18; - priv->bus_clkdiv = priv->brd_clkdiv; - } else if (breg == 1) { - priv->brd_clk = 60; /* 20 MHz */ - priv->bus_clk = priv->brd_clk * 0x14; - priv->bus_clkdiv = priv->brd_clkdiv; - } else if (breg == 3) { - priv->brd_clk = 100; /* 33.33 MHz */ - priv->bus_clk = priv->brd_clk * 0x18; - priv->bus_clkdiv = priv->brd_clkdiv * 2; - } else { - printf("MD[14:13] setting 0x%x not supported!", breg); - hang(); - } - - priv->brd_clkdiva = !!(modemr0 & BIT(14)); /* MD14 */ - - /* Decode DDR operating frequency from MD[37:36,19,17] pins */ - md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17); - product = otpmon17 & 0xff; - sscg = (modemr1 >> 4) & 0x03; - if (sscg == 2) { - printf("MD[37:36] setting 0x%x not supported!", sscg); - hang(); - } - - if (product == 0x2) { /* V4H-3 */ - priv->ddr_mbps = 4800; - priv->ddr_mbpsdiv = 1; - } else if (product == 0x1) { /* V4H-5 */ - if (md == 3) - priv->ddr_mbps = 4800; - else - priv->ddr_mbps = 5000; - priv->ddr_mbpsdiv = 1; - } else { /* V4H-7 */ - if (md == 0) { - if (sscg == 0) { - priv->ddr_mbps = 6400; - priv->ddr_mbpsdiv = 1; - } else { - priv->ddr_mbps = 19000; - priv->ddr_mbpsdiv = 3; - } - } else if (md == 1) { - priv->ddr_mbps = 6000; - priv->ddr_mbpsdiv = 1; - } else if (md == 2) { - priv->ddr_mbps = 5500; - priv->ddr_mbpsdiv = 1; - } else if (md == 3) { - priv->ddr_mbps = 4800; - priv->ddr_mbpsdiv = 1; - } - } - - priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, - priv->brd_clk, priv->brd_clkdiv * (priv->brd_clkdiva + 1)); - priv->ddr_mul_low = CLK_DIV(6400, 2, priv->brd_clk, - priv->brd_clkdiv * (priv->brd_clkdiva + 1)); - - priv->ddr_mul_reg = priv->ddr_mul_low; - if (sscg != 0) - priv->ddr_mul_reg -= 2; - - priv->ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1)) / - (priv->ddr_mbpsdiv * priv->brd_clk * 2)) - (8 * (priv->ddr_mul / 2) * 2); - - /* Adjust tccd */ - priv->ddr_tccd = 2; - - /* Initialize DDR */ - dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x1234); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x1234); - - reg = dbsc5_init_ddr(dev); - - dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x0); - dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x0); - - return reg != priv->ddr_phyvalid; -} - -/** - * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data - * @dev: DBSC5 device - * - * Extract DBSC5 address from DT and store it in driver data. - */ -static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) -{ - struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); - - priv->regs = dev_read_addr_ptr(dev); - if (!priv->regs) - return -EINVAL; - - return 0; -} - -/** - * renesas_dbsc5_dram_get_info() - Return RAM size - * @dev: DBSC5 device - * @info: Output RAM info - * - * Return size of the RAM managed by this RAM driver. - */ -static int renesas_dbsc5_dram_get_info(struct udevice *dev, - struct ram_info *info) -{ - info->base = 0x40000000; - info->size = 0; - - return 0; -} - -static const struct ram_ops renesas_dbsc5_dram_ops = { - .get_info = renesas_dbsc5_dram_get_info, -}; - -U_BOOT_DRIVER(renesas_dbsc5_dram) = { - .name = "dbsc5_dram", - .id = UCLASS_RAM, - .of_to_plat = renesas_dbsc5_dram_of_to_plat, - .ops = &renesas_dbsc5_dram_ops, - .probe = renesas_dbsc5_dram_probe, - .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), -}; diff --git a/drivers/ram/renesas/dbsc5/ecc.c b/drivers/ram/renesas/dbsc5/ecc.c new file mode 100644 index 00000000000..77295a696ab --- /dev/null +++ b/drivers/ram/renesas/dbsc5/ecc.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include + +#define DBSC5_DBSC_CNT 8 + +#define DBSC_D_BASE(n) (0xe9900000 + ((n) * 0x4000)) +#define DBSC_A_BASE(n) (0xe9800000 + ((n) * 0x8000)) +#define DBSYSCNT 0x100 +#define DBACEN 0x200 +#define DBFSINTENB02A 0x7088 +#define DBFSINTENB04A 0x7090 +#define DBFSCONFAXI0 0x7400 +#define DBFSDRAMECCAREA00 0x7450 +#define DBFSCTRL01A 0x7604 +#define DBFSCONF00A 0x7640 +#define DBFSCONF01A 0x7644 +#define DBFSCONF02A 0x7648 +#define DBFSSTAT00A 0x7680 +#define DBFSSTAT01A 0x7684 + +#define DBSYSCNT_ENABLE 0x1234 +#define DBSYSCNT_DISABLE 0x0 +#define DBACEN_ACCESS_DISABLE 0 +#define DBACEN_ACCESS_ENABLE 1 + +#define ECM_BASE 0xb89a0000 +#define ECMERRCTLR0 (ECM_BASE + 0x0) +#define ECMERRINCR0 (ECM_BASE + 0x200) +#define ECMERROMKR0 (ECM_BASE + 0x600) +#define ECMERRCTLR6 (ECM_BASE + (0x4 * 6)) +#define ECMERRINCR6 (ECM_BASE + 0x200U + (0x4 * 6)) +#define ECMERROMKR6 (ECM_BASE + 0x600U + (0x4 * 6)) +#define ECMWPCNTR (ECM_BASE + 0xa00) +#define ECMWACNTR (ECM_BASE + 0xa04) + +struct renesas_dbsc5_ecc_priv { + void __iomem *regs; +}; + +static void ecm_reg_unlock(void) +{ + writel(0xacce0001, ECMWPCNTR); +} + +static void ecm_reg_lock(void) +{ + writel(0xacce0000, ECMWPCNTR); +} + +static void ecm_reg_write(u32 adr, u32 val) +{ + writel(0xacce0000 | (adr & 0xffff), ECMWACNTR); + writel(val, adr); +} + +static int renesas_dbsc5_ecc_probe(struct udevice *dev) +{ + int i; + + ecm_reg_unlock(); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + writel(DBSYSCNT_ENABLE, DBSC_D_BASE(i) + DBSYSCNT); + writel(DBSYSCNT_ENABLE, DBSC_A_BASE(i) + DBSYSCNT); + } + + ecm_reg_write(ECMERRINCR0, readl(ECMERRINCR0) | 0xAAA); + ecm_reg_write(ECMERROMKR0, readl(ECMERROMKR0) | 0xAAA); + ecm_reg_write(ECMERRCTLR0, readl(ECMERRCTLR0) | 0xAAA); + ecm_reg_write(ECMERRINCR6, readl(ECMERRINCR6) | 0xA000); + ecm_reg_write(ECMERROMKR6, readl(ECMERROMKR6) | 0xA000); + ecm_reg_write(ECMERRCTLR6, readl(ECMERRCTLR6) | 0xA000); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xcccc, DBSC_A_BASE(i) + DBFSDRAMECCAREA00); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(DBACEN_ACCESS_DISABLE, DBSC_A_BASE(i) + DBACEN); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0, DBSC_A_BASE(i) + DBFSCONF00A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0, DBSC_A_BASE(i) + DBFSCONF01A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xcccb, DBSC_A_BASE(i) + DBFSCONF02A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0x1, DBSC_A_BASE(i) + DBFSCTRL01A); + + u32 fsstat; + do { + fsstat = 0x1; + for (i = 0; i < DBSC5_DBSC_CNT; i++) + fsstat &= readl(DBSC_A_BASE(i) + DBFSSTAT01A); + } while (!(fsstat & 0x1)); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(DBACEN_ACCESS_ENABLE, DBSC_A_BASE(i) + DBACEN); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + setbits_le32(DBSC_A_BASE(i) + DBFSCONFAXI0, 0x100); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xff00ff00, DBSC_A_BASE(i) + DBFSINTENB02A); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) + writel(0xffffffff, DBSC_A_BASE(i) + DBFSINTENB04A); + + ecm_reg_lock(); + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + writel(DBSYSCNT_DISABLE, DBSC_D_BASE(i) + DBSYSCNT); + writel(DBSYSCNT_DISABLE, DBSC_A_BASE(i) + DBSYSCNT); + } + + return 0; +} + +static int renesas_dbsc5_ecc_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +static int renesas_dbsc5_ecc_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct renesas_dbsc5_ecc_priv *priv = dev_get_priv(dev); + + info->base = (phys_addr_t)priv->regs; + info->size = 32 * SZ_1M; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_ecc_ops = { + .get_info = renesas_dbsc5_ecc_get_info, +}; + +static const struct udevice_id renesas_dbsc5_ecc_ids[] = { + { .compatible = "renesas,r8a78000-ecc" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5_ecc) = { + .name = "dbsc5_ecc", + .id = UCLASS_RAM, + .of_match = renesas_dbsc5_ecc_ids, + .of_to_plat = renesas_dbsc5_ecc_of_to_plat, + .ops = &renesas_dbsc5_ecc_ops, + .probe = renesas_dbsc5_ecc_probe, + .priv_auto = sizeof(struct renesas_dbsc5_ecc_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/qos.c b/drivers/ram/renesas/dbsc5/qos.c index 56a60b987af..a9fc0b1439a 100644 --- a/drivers/ram/renesas/dbsc5/qos.c +++ b/drivers/ram/renesas/dbsc5/qos.c @@ -9,7 +9,7 @@ #include #include #include -#include "dbsc5.h" +#include "r8a779g0-dbsc5.h" /* AXMM */ #define AXMM_ADSPLCR0 0x4008 diff --git a/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c new file mode 100644 index 00000000000..b57c885fc59 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "r8a779g0-dbsc5.h" + +static int renesas_dbsc5_probe(struct udevice *dev) +{ + struct udevice *pdev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &pdev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_NOP, "dbsc5_qos", &pdev); + if (ret) + return ret; + + return 0; +} + +int renesas_dbsc5_bind(struct udevice *dev) +{ + struct udevice *ramdev, *qosdev; + struct driver *ramdrv, *qosdrv; + int ret; + + ramdrv = lists_driver_lookup_name("dbsc5_dram"); + if (!ramdrv) + return -ENOENT; + + + qosdrv = lists_driver_lookup_name("dbsc5_qos"); + if (!qosdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", + dev_get_driver_data(dev), + dev_ofnode(dev), &ramdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(dev, qosdrv, "dbsc5_qos", 0, + dev_ofnode(dev), &qosdev); + if (ret) + device_unbind(ramdev); + + return ret; +} + +struct renesas_dbsc5_data r8a779g0_dbsc5_data = { + .clock_node = "renesas,r8a779g0-cpg-mssr", + .reset_node = "renesas,r8a779g0-rst", + .otp_node = "renesas,r8a779g0-otp", +}; + +static const struct udevice_id renesas_dbsc5_ids[] = { + { + .compatible = "renesas,r8a779g0-dbsc", + .data = (ulong)&r8a779g0_dbsc5_data + }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5) = { + .name = "dbsc5", + .id = UCLASS_NOP, + .of_match = renesas_dbsc5_ids, + .bind = renesas_dbsc5_bind, + .probe = renesas_dbsc5_probe, +}; diff --git a/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h new file mode 100644 index 00000000000..592c9badbd7 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dbsc5.h @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ + +/* + * DBSC5 ... 0xe678_0000..0xe67fffff + * - AXMM_BASE 0xe6780000 MM (DDR Hier) MM AXI Router - Region 0 + * - DBSC_A_BASE 0xe6790000 MM (DDR Hier) DBSC0A - Region 0 + * - CCI_BASE 0xe67A0000 MM (DDR Hier) FBA for MM + * - DBSC_D_BASE 0xE67A4000 MM (DDR Hier) DBSC0D - Region 0 + * - QOS_BASE 0xe67E0000 MM (DDR Hier) M-STATQ (64kiB) + */ +#define DBSC5_AXMM_OFFSET 0x00000 +#define DBSC5_DBSC_A_OFFSET 0x10000 +#define DBSC5_CCI_OFFSET 0x20000 +#define DBSC5_DBSC_D_OFFSET 0x24000 +#define DBSC5_QOS_OFFSET 0x60000 + +struct renesas_dbsc5_data { + const char *clock_node; + const char *reset_node; + const char *otp_node; +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A779G0_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/r8a779g0-dram.c b/drivers/ram/renesas/dbsc5/r8a779g0-dram.c new file mode 100644 index 00000000000..8dd4e321849 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a779g0-dram.c @@ -0,0 +1,4537 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "r8a779g0-dbsc5.h" + +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_SIZE_V4H 0x100 +/* Number of array elements in Data Slice */ +#define DDR_PHY_SLICE_REGSET_NUM_V4H 153 +/* Number of array elements in Address Slice */ +#define DDR_PHY_ADR_V_REGSET_NUM_V4H 61 +/* Number of array elements in Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_NUM_V4H 97 +/* Number of array elements in PI Register */ +#define DDR_PI_REGSET_NUM_V4H 1381 + +/* Minimum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_LO 5 +/* Maximum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_HI 11 +/* The number of JS1 setting table */ +#define JS1_FREQ_TBL_NUM 12 +/* Macro to set the value of MR1 */ +#define JS1_MR1(f) (((f) << 4) | 0x00) /* CK mode = 0B */ +/* Macro to set the value of MR2 */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +#define JS2_tSR 0 /* Element for self refresh */ +#define JS2_tXP 1 /* Exit power-down mode to first valid command */ +#define JS2_tRCD 2 /* Active to read or write delay */ +#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ +#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ +#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ +#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ +#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ +#define JS2_tRRD 8 /* Active bank a to active bank b command */ +#define JS2_tPPD 9 /* Precharge Power Down */ +#define JS2_tFAW 10 /* Four bank ACT window */ +#define JS2_tMRR 11 /* Mode Register Read */ +#define JS2_tMRW 12 /* Mode Register Write */ +#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ +#define JS2_tZQCALns 14 /* ZQ Calibration */ +#define JS2_tZQLAT 15 /* ZQ Latency */ +#define JS2_tODTon_min 16 /* Minimum time on die termination */ +#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ +#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ +#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ +#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ +#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ +#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ +#define JS2_tDQ72DQns 25 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ +#define JS2_tCAENTns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ +#define JS2_tCSCAL 27 /* Minimum CA Low Duration time */ +#define JS2_TBLCNT 28 /* The number of table */ + +#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ +#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ +#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ +#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ +#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ +#define JS2_tPDN (JS2_TBLCNT + 5) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) +#define JS2_CNT (JS2_TBLCNT + 7) + +struct jedec_spec1 { + u32 fx3; /* Frequency */ + u8 RLset1; /* setting value of Read Latency */ + u8 RLset2; /* setting value of Read Latency */ + u8 WLsetA; /* setting value of Write Latency */ + u8 WLsetB; /* setting value of Write Latency */ + u32 nWR; /* Write-Recovery for Auto-Precharge commands */ + u32 nRBTP; /* the minimum interval from a READ command to a PRE command */ + u32 ODTLon; /* On Die Termination */ + u8 MR1; /* Mode Register 1 */ + u8 MR2; /* Mode Register 2 */ + u32 WCKENLR; /* The setting time from CAS command to the Start-up of WCK in READ operation */ + u32 WCKENLW; /* The setting time from CAS command to the Start-up of WCK in WRITE operation */ + u32 WCKENLF; /* The setting time from CAS command to the Start-up of WCK in FAST-sync operation */ + u32 WCKPRESTA; /* The setting time from the Start-up of WCK to WCK Clocling Start */ + u32 WCKPRETGLR; /* The setting time from WCK Clocling Start to Reflecting frequency of WCK */ +}; + +static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* fx3, RL1, RL2, WLA.WLB.nWR.nRBTP, ODTLon */ + { 800, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 1, 3 }, /* 533.333Mbps*/ + { 1600, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 1, 4 }, /* 1066.666Mbps*/ + { 2400, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 4 }, /* 1600.000Mbps*/ + { 3200, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 2, 1, 1, 2, 4 }, /* 2133.333Mbps*/ + { 4000, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 1, 1, 2, 5 }, /* 2666.666Mbps*/ + { 4800, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 4, 2, 1, 2, 5 }, /* 3200.000Mbps*/ + { 5600, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 4, 2, 1, 3, 5 }, /* 3733.333Mbps*/ + { 6400, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 5, 2, 1, 3, 6 }, /* 4266.666Mbps*/ + { 7200, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 6, 3, 2, 3, 6 }, /* 4800.000Mbps*/ + { 8250, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 7, 3, 2, 4, 6 }, /* 5500.000Mbps*/ + { 9000, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 7, 4, 2, 4, 7 }, /* 6000.000Mbps*/ + { 9600, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 8, 4, 2, 4, 7 } /* 6400.000Mbps*/ +}; + +struct jedec_spec2 { + u16 ps; /* Value in pico seconds */ + u16 cyc; /* Value in cycle count */ +}; + +static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 18000, 2 }, /* tRCD */ + { 18000, 2 }, /* tRPpb */ + { 21000, 2 }, /* tRPab */ + { 42000, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 700, 0 }, /* tWCK2DQI_HF */ + { 1600, 0 }, /* tWCK2DQO_HF */ + { 900, 0 }, /* tWCK2DQI_LF */ + { 1900, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + }, { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 19875, 2 }, /* tRCD */ + { 19875, 2 }, /* tRPpb */ + { 22875, 2 }, /* tRPab */ + { 43875, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 5000, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 20000, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 715, 0 }, /* tWCK2DQI_HF */ + { 1635, 0 }, /* tWCK2DQO_HF */ + { 920, 0 }, /* tWCK2DQI_LF */ + { 1940, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 } /* tCSCAL */ + } +}; + +static const u16 jedec_spec2_tRFC_ab[] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +/* The address offsets of PI Register */ +#define DDR_PI_REGSET_OFS_V4H 0x0800 +/* The address offsets of Data Slice */ +#define DDR_PHY_SLICE_REGSET_OFS_V4H 0x1000 +/* The address offsets of Address Slice */ +#define DDR_PHY_ADR_V_REGSET_OFS_V4H 0x1200 +/* The address offsets of Address Control Slice */ +#define DDR_PHY_ADR_G_REGSET_OFS_V4H 0x1300 + +#define DDR_REGDEF_ADR(regdef) ((regdef) & 0xFFFF) +#define DDR_REGDEF_LEN(regdef) (((regdef) >> 16) & 0xFF) +#define DDR_REGDEF_LSB(regdef) (((regdef) >> 24) & 0xFF) + +#define DDR_REGDEF(lsb, len, adr) \ + (((lsb) << 24) | ((len) << 16) | (adr)) + +#define PHY_LP4_BOOT_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1000) +#define PHY_PER_CS_TRAINING_MULTICAST_EN DDR_REGDEF(0x10, 0x01, 0x1006) +#define PHY_PER_CS_TRAINING_INDEX DDR_REGDEF(0x18, 0x01, 0x1006) +#define PHY_VREF_INITIAL_STEPSIZE DDR_REGDEF(0x18, 0x08, 0x100D) +#define PHY_RDLVL_BEST_THRSHLD DDR_REGDEF(0x00, 0x04, 0x100E) +#define PHY_RDLVL_VREF_OUTLIER DDR_REGDEF(0x10, 0x03, 0x100E) +#define SC_PHY_WCK_CALC DDR_REGDEF(0x18, 0x01, 0x101A) +#define PHY_RDLVL_RDDQS_DQ_OBS_SELECT DDR_REGDEF(0x10, 0x05, 0x102C) +#define PHY_CALVL_VREF_DRIVING_SLICE DDR_REGDEF(0x18, 0x01, 0x1030) +#define PHY_WRLVL_HARD0_DELAY_OBS DDR_REGDEF(0x00, 0x0A, 0x1038) +#define PHY_WRLVL_HARD1_DELAY_OBS DDR_REGDEF(0x10, 0x0A, 0x1038) +#define PHY_WRLVL_STATUS_OBS DDR_REGDEF(0x00, 0x1C, 0x1039) +#define PHY_WRLVL_ERROR_OBS DDR_REGDEF(0x00, 0x10, 0x103B) +#define PHY_GTLVL_STATUS_OBS DDR_REGDEF(0x00, 0x12, 0x103D) +#define PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS DDR_REGDEF(0x10, 0x09, 0x103E) +#define PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS DDR_REGDEF(0x00, 0x09, 0x103F) +#define PHY_WDQLVL_STATUS_OBS DDR_REGDEF(0x00, 0x20, 0x1043) +#define PHY_DATA_DC_CAL_START DDR_REGDEF(0x18, 0x01, 0x104D) +#define PHY_SLV_DLY_CTRL_GATE_DISABLE DDR_REGDEF(0x10, 0x01, 0x104E) +#define PHY_REGULATOR_EN_CNT DDR_REGDEF(0x18, 0x06, 0x1050) +#define PHY_VREF_INITIAL_START_POINT DDR_REGDEF(0x00, 0x09, 0x1055) +#define PHY_VREF_INITIAL_STOP_POINT DDR_REGDEF(0x10, 0x09, 0x1055) +#define PHY_VREF_TRAINING_CTRL DDR_REGDEF(0x00, 0x02, 0x1056) +#define PHY_RDDQ0_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105D) +#define PHY_RDDQ1_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105D) +#define PHY_RDDQ2_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105E) +#define PHY_RDDQ3_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105E) +#define PHY_RDDQ4_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x105F) +#define PHY_RDDQ5_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x105F) +#define PHY_RDDQ6_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1060) +#define PHY_RDDQ7_SLAVE_DELAY DDR_REGDEF(0x10, 0x09, 0x1060) +#define PHY_RDDM_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1061) +#define PHY_RX_CAL_ALL_DLY DDR_REGDEF(0x18, 0x06, 0x1061) +#define PHY_RX_PCLK_CLK_SEL DDR_REGDEF(0x00, 0x03, 0x1062) +#define PHY_DATA_DC_CAL_CLK_SEL DDR_REGDEF(0x18, 0x03, 0x1063) +#define PHY_PAD_VREF_CTRL_DQ DDR_REGDEF(0x00, 0x0E, 0x1067) +#define PHY_PER_CS_TRAINING_EN DDR_REGDEF(0x00, 0x01, 0x1068) +#define PHY_RDDATA_EN_TSEL_DLY DDR_REGDEF(0x18, 0x05, 0x1069) +#define PHY_RDDATA_EN_OE_DLY DDR_REGDEF(0x00, 0x05, 0x106A) +#define PHY_RPTR_UPDATE DDR_REGDEF(0x10, 0x04, 0x106C) +#define PHY_WRLVL_RESP_WAIT_CNT DDR_REGDEF(0x08, 0x06, 0x106D) +#define PHY_RDLVL_DLY_STEP DDR_REGDEF(0x08, 0x04, 0x1070) +#define PHY_RDLVL_MAX_EDGE DDR_REGDEF(0x00, 0x09, 0x1071) +#define PHY_DATA_DC_WDQLVL_ENABLE DDR_REGDEF(0x08, 0x02, 0x1075) +#define PHY_RDDATA_EN_DLY DDR_REGDEF(0x10, 0x05, 0x1076) +#define PHY_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x08, 0x06, 0x1076) +#define PHY_DQ_DM_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1077) +#define PHY_DQ_DM_SWIZZLE1 DDR_REGDEF(0x00, 0x04, 0x1078) +#define PHY_CLK_WRDQS_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x107E) +#define PHY_WRITE_PATH_LAT_DEC DDR_REGDEF(0x10, 0x01, 0x107E) +#define PHY_RDDQS_GATE_SLAVE_DELAY DDR_REGDEF(0x00, 0x09, 0x1088) +#define PHY_RDDQS_LATENCY_ADJUST DDR_REGDEF(0x10, 0x05, 0x1088) +#define PHY_WRITE_PATH_LAT_ADD DDR_REGDEF(0x18, 0x03, 0x1088) +#define PHY_WRITE_PATH_LAT_FRAC DDR_REGDEF(0x00, 0x08, 0x1089) +#define PHY_GTLVL_LAT_ADJ_START DDR_REGDEF(0x00, 0x05, 0x108A) +#define PHY_DATA_DC_DQS_CLK_ADJUST DDR_REGDEF(0x00, 0x08, 0x108C) +#define PHY_ADR_CALVL_SWIZZLE0 DDR_REGDEF(0x00, 0x20, 0x1202) +#define PHY_ADR_MEAS_DLY_STEP_ENABLE DDR_REGDEF(0x10, 0x01, 0x1203) +#define PHY_ADR_CALVL_RANK_CTRL DDR_REGDEF(0x18, 0x02, 0x1205) +#define PHY_ADR_CALVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x120A) +#define PHY_ADR_CALVL_OBS2 DDR_REGDEF(0x00, 0x20, 0x120B) +#define PHY_ADR_CALVL_DLY_STEP DDR_REGDEF(0x00, 0x04, 0x1210) +#define PHY_CS_ACS_ALLOCATION_BIT2_2 DDR_REGDEF(0x08, 0x02, 0x1215) +#define PHY_CS_ACS_ALLOCATION_BIT3_2 DDR_REGDEF(0x10, 0x02, 0x1215) +#define PHY_CSLVL_OBS1 DDR_REGDEF(0x00, 0x20, 0x1221) +#define PHY_CLK_DC_CAL_CLK_SEL DDR_REGDEF(0x08, 0x03, 0x123A) +#define PHY_FREQ_SEL_MULTICAST_EN DDR_REGDEF(0x08, 0x01, 0x1301) +#define PHY_FREQ_SEL_INDEX DDR_REGDEF(0x10, 0x02, 0x1301) +#define SC_PHY_MANUAL_UPDATE DDR_REGDEF(0x18, 0x01, 0x1304) +#define PHY_SET_DFI_INPUT_RST_PAD DDR_REGDEF(0x18, 0x01, 0x1311) +#define PHY_CAL_MODE_0 DDR_REGDEF(0x00, 0x0D, 0x132C) +#define PHY_CAL_INTERVAL_COUNT_0 DDR_REGDEF(0x00, 0x20, 0x132D) +#define PHY_DATA_BYTE_ORDER_SEL DDR_REGDEF(0x00, 0x20, 0x133E) +#define PHY_PAD_ACS_RX_PCLK_CLK_SEL DDR_REGDEF(0x10, 0x03, 0x1348) +#define PHY_PLL_CTRL DDR_REGDEF(0x00, 0x0E, 0x134B) +#define PHY_PLL_CTRL_8X DDR_REGDEF(0x10, 0x0E, 0x134B) +#define PHY_CAL_CLK_SELECT_0 DDR_REGDEF(0x00, 0x03, 0x1360) + +#define PI_START DDR_REGDEF(0x00, 0x01, 0x0800) +#define PI_TRAIN_ALL_FREQ_REQ DDR_REGDEF(0x18, 0x01, 0x0802) +#define PI_CS_MAP DDR_REGDEF(0x08, 0x02, 0x0813) +#define PI_WRLVL_REQ DDR_REGDEF(0x10, 0x01, 0x081C) +#define PI_WRLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x081C) +#define PI_RDLVL_REQ DDR_REGDEF(0x18, 0x01, 0x0824) +#define PI_RDLVL_GATE_REQ DDR_REGDEF(0x00, 0x01, 0x0825) +#define PI_RDLVL_CS_SW DDR_REGDEF(0x08, 0x02, 0x0825) +#define PI_RDLVL_PERIODIC DDR_REGDEF(0x08, 0x01, 0x082E) +#define PI_RDLVL_INTERVAL DDR_REGDEF(0x08, 0x10, 0x0835) +#define PI_DRAMDCA_FLIP_MASK DDR_REGDEF(0x08, 0x02, 0x083B) +#define PI_DRAMDCA_LVL_REQ DDR_REGDEF(0x10, 0x01, 0x083D) +#define PI_DCMLVL_CS_SW DDR_REGDEF(0x18, 0x02, 0x083D) +#define PI_WRDCM_LVL_EN_F1 DDR_REGDEF(0x00, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F1 DDR_REGDEF(0x08, 0x02, 0x083F) +#define PI_WRDCM_LVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x083F) +#define PI_DRAMDCA_LVL_EN_F2 DDR_REGDEF(0x00, 0x02, 0x0840) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0868) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0869) +#define PI_DRAMDCA_LVL_ACTIVE_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x086A) +#define PI_TCKCKEL_F2 DDR_REGDEF(0x18, 0x04, 0x089D) +#define PI_WDQLVL_VREF_EN DDR_REGDEF(0x08, 0x04, 0x089E) +#define PI_WDQLVL_PERIODIC DDR_REGDEF(0x00, 0x01, 0x08A0) +#define PI_WDQLVL_INTERVAL DDR_REGDEF(0x00, 0x10, 0x08A4) +#define PI_INT_STATUS DDR_REGDEF(0x00, 0x20, 0x0900) +#define PI_INT_ACK_0 DDR_REGDEF(0x00, 0x20, 0x0902) +#define PI_INT_ACK_1 DDR_REGDEF(0x00, 0x03, 0x0903) +#define PI_LONG_COUNT_MASK DDR_REGDEF(0x10, 0x05, 0x090F) +#define PI_ADDR_MUX_0 DDR_REGDEF(0x00, 0x03, 0x0910) +#define PI_ADDR_MUX_1 DDR_REGDEF(0x08, 0x03, 0x0910) +#define PI_ADDR_MUX_2 DDR_REGDEF(0x10, 0x03, 0x0910) +#define PI_ADDR_MUX_3 DDR_REGDEF(0x18, 0x03, 0x0910) +#define PI_ADDR_MUX_4 DDR_REGDEF(0x00, 0x03, 0x0911) +#define PI_ADDR_MUX_5 DDR_REGDEF(0x08, 0x03, 0x0911) +#define PI_ADDR_MUX_6 DDR_REGDEF(0x10, 0x03, 0x0911) +#define PI_DATA_BYTE_SWAP_EN DDR_REGDEF(0x18, 0x01, 0x0911) +#define PI_DATA_BYTE_SWAP_SLICE0 DDR_REGDEF(0x00, 0x01, 0x0912) +#define PI_DATA_BYTE_SWAP_SLICE1 DDR_REGDEF(0x08, 0x01, 0x0912) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_PWRUP_SREFRESH_EXIT DDR_REGDEF(0x18, 0x01, 0x093D) +#define PI_DLL_RST DDR_REGDEF(0x00, 0x01, 0x0941) +#define PI_TDELAY_RDWR_2_BUS_IDLE_F2 DDR_REGDEF(0x00, 0x08, 0x0964) +#define PI_WRLAT_F2 DDR_REGDEF(0x10, 0x07, 0x096A) +#define PI_TWCKENL_WR_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x096A) +#define PI_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096B) +#define PI_TWCKPRE_STATIC_F2 DDR_REGDEF(0x08, 0x06, 0x096B) +#define PI_TWCKPRE_TOGGLE_RD_F2 DDR_REGDEF(0x18, 0x06, 0x096B) +#define PI_TWCKENL_FS_ADJ_F2 DDR_REGDEF(0x00, 0x06, 0x096C) +#define PI_CASLAT_F2 DDR_REGDEF(0x08, 0x07, 0x096C) +#define PI_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x0971) +#define PI_TREF_F2 DDR_REGDEF(0x00, 0x14, 0x0972) +#define PI_TDFI_WRLVL_WW_F0 DDR_REGDEF(0x00, 0x0A, 0x0974) +#define PI_TDFI_WRLVL_WW_F1 DDR_REGDEF(0x00, 0x0A, 0x0975) +#define PI_WRLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x0975) +#define PI_TDFI_WRLVL_WW_F2 DDR_REGDEF(0x00, 0x0A, 0x0976) +#define PI_WRLVL_WCKOFF_F2 DDR_REGDEF(0x10, 0x08, 0x0976) +#define PI_RDLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x097A) +#define PI_RDLVL_GATE_EN_F2 DDR_REGDEF(0x00, 0x02, 0x097B) +#define PI_RDLVL_VREF_EN_F0 DDR_REGDEF(0x10, 0x04, 0x097B) +#define PI_RDLVL_VREF_EN_F1 DDR_REGDEF(0x00, 0x04, 0x097D) +#define PI_RDLVL_VREF_EN_F2 DDR_REGDEF(0x10, 0x04, 0x097E) +#define PI_RDLAT_ADJ_F2 DDR_REGDEF(0x00, 0x09, 0x0981) +#define PI_WRLAT_ADJ_F2 DDR_REGDEF(0x00, 0x07, 0x0982) +#define PI_TDFI_CALVL_CC_F2 DDR_REGDEF(0x00, 0x0A, 0x0985) +#define PI_TDFI_CALVL_CAPTURE_F2 DDR_REGDEF(0x10, 0x0A, 0x0985) +#define PI_CALVL_EN_F2 DDR_REGDEF(0x10, 0x02, 0x0986) +#define PI_TCAENT_F2 DDR_REGDEF(0x00, 0x0E, 0x0989) +#define PI_TVREF_SHORT_F2 DDR_REGDEF(0x00, 0x0A, 0x098F) +#define PI_TVREF_LONG_F2 DDR_REGDEF(0x10, 0x0A, 0x098F) +#define PI_TVRCG_ENABLE_F2 DDR_REGDEF(0x00, 0x0A, 0x0990) +#define PI_TVRCG_DISABLE_F2 DDR_REGDEF(0x10, 0x0A, 0x0990) +#define PI_CALVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x00, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x08, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x18, 0x07, 0x0991) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x10, 0x07, 0x0992) +#define PI_CALVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x18, 0x07, 0x0992) +#define PI_TDFI_CALVL_STROBE_F2 DDR_REGDEF(0x08, 0x04, 0x0995) +#define PI_TXP_F2 DDR_REGDEF(0x10, 0x05, 0x0995) +#define PI_TMRWCKEL_F2 DDR_REGDEF(0x18, 0x08, 0x0995) +#define PI_TCKEHDQS_F2 DDR_REGDEF(0x10, 0x06, 0x099D) +#define PI_TFC_F2 DDR_REGDEF(0x00, 0x0A, 0x099E) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F0 DDR_REGDEF(0x10, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0 DDR_REGDEF(0x18, 0x07, 0x09A0) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F1 DDR_REGDEF(0x00, 0x07, 0x09A4) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1 DDR_REGDEF(0x08, 0x07, 0x09A4) +#define PI_TDFI_WDQLVL_WR_F2 DDR_REGDEF(0x00, 0x0A, 0x09A6) +#define PI_TDFI_WDQLVL_RW_F2 DDR_REGDEF(0x10, 0x0A, 0x09A6) +#define PI_WDQLVL_VREF_INITIAL_START_POINT_F2 DDR_REGDEF(0x00, 0x07, 0x09A7) +#define PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2 DDR_REGDEF(0x08, 0x07, 0x09A7) +#define PI_WDQLVL_EN_F2 DDR_REGDEF(0x18, 0x02, 0x09A7) +#define PI_MBIST_RDLAT_ADJ_F2 DDR_REGDEF(0x08, 0x09, 0x09A8) +#define PI_MBIST_TWCKENL_RD_ADJ_F2 DDR_REGDEF(0x18, 0x06, 0x09A8) +#define PI_TRTP_F2 DDR_REGDEF(0x18, 0x08, 0x09B3) +#define PI_TRP_F2 DDR_REGDEF(0x00, 0x08, 0x09B4) +#define PI_TRCD_F2 DDR_REGDEF(0x08, 0x08, 0x09B4) +#define PI_TWTR_S_F2 DDR_REGDEF(0x18, 0x06, 0x09B4) +#define PI_TWTR_L_F2 DDR_REGDEF(0x00, 0x06, 0x09B5) +#define PI_TWTR_F2 DDR_REGDEF(0x10, 0x06, 0x09B5) +#define PI_TWR_F2 DDR_REGDEF(0x18, 0x08, 0x09B5) +#define PI_TRAS_MIN_F2 DDR_REGDEF(0x10, 0x09, 0x09B6) +#define PI_TDQSCK_MAX_F2 DDR_REGDEF(0x00, 0x04, 0x09B7) +#define PI_TSR_F2 DDR_REGDEF(0x10, 0x08, 0x09B7) +#define PI_TMRD_F2 DDR_REGDEF(0x18, 0x08, 0x09B7) +#define PI_TDFI_CTRLUPD_MAX_F2 DDR_REGDEF(0x00, 0x15, 0x09BC) +#define PI_TDFI_CTRLUPD_INTERVAL_F2 DDR_REGDEF(0x00, 0x20, 0x09BD) +#define PI_TINIT_F2 DDR_REGDEF(0x00, 0x18, 0x09CC) +#define PI_TINIT1_F2 DDR_REGDEF(0x00, 0x18, 0x09CD) +#define PI_TINIT3_F2 DDR_REGDEF(0x00, 0x18, 0x09CE) +#define PI_TINIT4_F2 DDR_REGDEF(0x00, 0x18, 0x09CF) +#define PI_TINIT5_F2 DDR_REGDEF(0x00, 0x18, 0x09D0) +#define PI_TXSNR_F2 DDR_REGDEF(0x00, 0x10, 0x09D1) +#define PI_TZQCAL_F2 DDR_REGDEF(0x10, 0x0C, 0x09D6) +#define PI_TZQLAT_F2 DDR_REGDEF(0x00, 0x07, 0x09D7) +#define PI_ZQRESET_F2 DDR_REGDEF(0x10, 0x0C, 0x09D8) +#define PI_TDQ72DQ_F2 DDR_REGDEF(0x10, 0x0A, 0x09DD) +#define PI_TCBTRTW_F2 DDR_REGDEF(0x00, 0x06, 0x09DE) +#define PI_MC_TRFC_F2 DDR_REGDEF(0x00, 0x0A, 0x09E1) +#define PI_CKE_MUX_0 DDR_REGDEF(0x00, 0x03, 0x09E6) +#define PI_CKE_MUX_1 DDR_REGDEF(0x08, 0x03, 0x09E6) +#define PI_SEQ_DEC_SW_CS DDR_REGDEF(0x00, 0x02, 0x0A4E) +#define PI_SW_SEQ_START DDR_REGDEF(0x10, 0x01, 0x0A4E) +#define PI_SW_SEQ_0 DDR_REGDEF(0x00, 0x1B, 0x0BF1) +#define PI_SW_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0BF2) +#define PI_DFS_ENTRY_SEQ_0 DDR_REGDEF(0x00, 0x1D, 0x0BFB) +#define PI_DFS_INITIALIZATION_SEQ_1 DDR_REGDEF(0x00, 0x1D, 0x0C24) +#define PI_DFS_INITIALIZATION_SEQ_9 DDR_REGDEF(0x00, 0x1D, 0x0C2C) +#define PI_DFS_INITIALIZATION_SEQ_10 DDR_REGDEF(0x00, 0x1D, 0x0C2D) +#define PI_RDLVL_TRAIN_SEQ_1 DDR_REGDEF(0x00, 0x1B, 0x0C42) +#define PI_RDLVL_TRAIN_SEQ_2 DDR_REGDEF(0x00, 0x1B, 0x0C43) +#define PI_RDLVL_TRAIN_SEQ_3 DDR_REGDEF(0x00, 0x1B, 0x0C44) +#define PI_RDLVL_TRAIN_SEQ_4 DDR_REGDEF(0x00, 0x1B, 0x0C45) +#define PI_RDLVL_TRAIN_SEQ_5 DDR_REGDEF(0x00, 0x1B, 0x0C46) +#define PI_SEQ_WAIT_16_F2 DDR_REGDEF(0x00, 0x18, 0x0C77) +#define PI_SEQ_WAIT_17_F2 DDR_REGDEF(0x00, 0x18, 0x0C7A) +#define PI_SEQ_WAIT_18_F2 DDR_REGDEF(0x00, 0x18, 0x0C7D) +#define PI_SEQ_WAIT_19_F2 DDR_REGDEF(0x00, 0x18, 0x0C80) +#define PI_SEQ_WAIT_20_F2 DDR_REGDEF(0x00, 0x18, 0x0C83) +#define PI_SEQ_WAIT_21_F2 DDR_REGDEF(0x00, 0x18, 0x0C86) +#define PI_SEQ_WAIT_22_F2 DDR_REGDEF(0x00, 0x18, 0x0C89) +#define PI_SEQ_WAIT_23_F2 DDR_REGDEF(0x00, 0x18, 0x0C8C) +#define PI_SEQ_WAIT_24_F2 DDR_REGDEF(0x00, 0x18, 0x0C8F) +#define PI_SEQ_WAIT_25_F2 DDR_REGDEF(0x00, 0x18, 0x0C92) +#define PI_SEQ_WAIT_26_F2 DDR_REGDEF(0x00, 0x18, 0x0C95) +#define PI_SEQ_WAIT_30_F2 DDR_REGDEF(0x00, 0x18, 0x0CA1) +#define PI_DARRAY3_0_CS0_F0 DDR_REGDEF(0x00, 0x08, 0x0D0B) +#define PI_DARRAY3_1_CS0_F0 DDR_REGDEF(0x08, 0x08, 0x0D0B) +#define PI_DARRAY3_0_CS0_F1 DDR_REGDEF(0x00, 0x08, 0x0D15) +#define PI_DARRAY3_1_CS0_F1 DDR_REGDEF(0x08, 0x08, 0x0D15) +#define PI_DARRAY3_0_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D1F) +#define PI_DARRAY3_1_CS0_F2 DDR_REGDEF(0x08, 0x08, 0x0D1F) +#define PI_DARRAY3_4_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D20) +#define PI_DARRAY3_20_CS0_F2 DDR_REGDEF(0x00, 0x08, 0x0D24) +#define PI_DARRAY3_0_CS1_F0 DDR_REGDEF(0x00, 0x08, 0x0D29) +#define PI_DARRAY3_1_CS1_F0 DDR_REGDEF(0x08, 0x08, 0x0D29) +#define PI_DARRAY3_0_CS1_F1 DDR_REGDEF(0x00, 0x08, 0x0D33) +#define PI_DARRAY3_1_CS1_F1 DDR_REGDEF(0x08, 0x08, 0x0D33) +#define PI_DARRAY3_0_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3D) +#define PI_DARRAY3_1_CS1_F2 DDR_REGDEF(0x08, 0x08, 0x0D3D) +#define PI_DARRAY3_4_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D3E) +#define PI_DARRAY3_20_CS1_F2 DDR_REGDEF(0x00, 0x08, 0x0D42) + +/* The setting table of Data Slice for V4H */ +static const u32 DDR_PHY_SLICE_REGSET_V4H[DDR_PHY_SLICE_REGSET_NUM_V4H] = { + 0x30020370, 0x00000000, 0x01000002, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x04000100, + 0x00010000, 0x01000000, 0x00000000, 0x00000000, + 0x00010000, 0x08010000, 0x00022003, 0x00000000, + 0x040F0100, 0x1404034F, 0x04040102, 0x04040404, + 0x00000100, 0x00000000, 0x00000000, 0x000800C0, + 0x000F18FF, 0x00000000, 0x00000001, 0x00070000, + 0x0000AAAA, 0x00005555, 0x0000B5B5, 0x00004A4A, + 0x00005656, 0x0000A9A9, 0x0000A9A9, 0x0000B5B5, + 0x00000000, 0xBFBF0000, 0xCCCCF7F7, 0x00000000, + 0x00000000, 0x00000000, 0x00080815, 0x08040000, + 0x00000004, 0x00103000, 0x000C0040, 0x00200200, + 0x01010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000004, 0x001F07FF, 0x08000303, + 0x10200080, 0x00000006, 0x00000401, 0x00000000, + 0x20CEC201, 0x00000001, 0x00017706, 0x01007706, + 0x00000000, 0x008D006D, 0x00100001, 0x03FF0100, + 0x00006E01, 0x00000301, 0x00000000, 0x00000000, + 0x00000000, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x0D000050, 0x10100004, 0x06102010, + 0x61619041, 0x07097000, 0x00644180, 0x00803280, + 0x00808001, 0x13010101, 0x02000016, 0x10001003, + 0x06093E42, 0x0F063D01, 0x011700C8, 0x04100140, + 0x00000100, 0x000001D1, 0x05000068, 0x00030402, + 0x01400000, 0x80800300, 0x00160010, 0x76543210, + 0x00000008, 0x03010301, 0x03010301, 0x03010301, + 0x03010301, 0x03010301, 0x00000000, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00500050, 0x00500050, 0x00500050, 0x00500050, + 0x00070087, 0x00000000, 0x08010007, 0x00000000, + 0x20202020, 0x20202020, 0x20202020, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000 +}; + +/* The setting table of Address Slice for V4H */ +static const u32 DDR_PHY_ADR_V_REGSET_V4H[DDR_PHY_ADR_V_REGSET_NUM_V4H] = { + 0x00200030, 0x00200002, 0x76543210, 0x00010001, + 0x06543210, 0x03070000, 0x00001000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000807F, + 0x00000001, 0x00000003, 0x00000000, 0x000F0000, + 0x030C000F, 0x00020103, 0x0000000F, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x02000400, 0x0000002A, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00200101, + 0x10002C03, 0x00000003, 0x00030240, 0x00008008, + 0x00081020, 0x01200000, 0x00010001, 0x00000000, + 0x00100302, 0x003E4208, 0x01400140, 0x01400140, + 0x01400140, 0x01400140, 0x00000100, 0x00000100, + 0x00000100, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00020580, 0x03000040, + 0x00000000 +}; + +/* The setting table of Address Control Slice for V4H */ +static const u32 DDR_PHY_ADR_G_REGSET_V4H[DDR_PHY_ADR_G_REGSET_NUM_V4H] = { + 0x00000000, 0x00000100, 0x00000001, 0x23800000, + 0x00000000, 0x01000101, 0x00000000, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00040101, 0x00000000, 0x00000000, 0x00000064, + 0x00000000, 0x00000000, 0x39421B42, 0x00010124, + 0x00520052, 0x00000052, 0x00000000, 0x00000000, + 0x00010001, 0x00000000, 0x00000000, 0x00010001, + 0x00000000, 0x00000000, 0x00010001, 0x07030102, + 0x01030307, 0x00000054, 0x00004096, 0x08200820, + 0x08200820, 0x08200820, 0x08200820, 0x00000820, + 0x004103B8, 0x0000003F, 0x000C0006, 0x00000000, + 0x000004C0, 0x00007A12, 0x00000208, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x03000000, 0x00000000, 0x00000000, 0x04102002, + 0x00041020, 0x01C98C98, 0x3F400000, 0x003F3F3F, + 0x00000000, 0x00000000, 0x76543210, 0x00010198, + 0x00000007, 0x00000000, 0x00000000, 0x00000000, + 0x00000002, 0x00000000, 0x00000000, 0x00000000, + 0x01032380, 0x00000100, 0x00000000, 0x31421342, + 0x00308000, 0x00000080, 0x00063F77, 0x00000006, + 0x0000033F, 0x00000000, 0x0000033F, 0x00000000, + 0x0000033F, 0x00000000, 0x00033F00, 0x00CC0000, + 0x00033F77, 0x00000000, 0x00033F00, 0x00EE0000, + 0x00033F00, 0x00EE0000, 0x00033F00, 0x00EE0000, + 0x00200106 +}; + +/* The setting table of PI Register for V4H */ +static const u32 DDR_PI_REGSET_V4H[DDR_PI_REGSET_NUM_V4H] = { + 0x00000D00, 0x00010100, 0x00640004, 0x00000001, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xFFFFFFFF, 0x02010000, 0x00000003, 0x00000005, + 0x00000002, 0x00000000, 0x00000101, 0x0012080E, + 0x00000000, 0x001E2C0E, 0x00000000, 0x00030300, + 0x01010700, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x01000000, 0x00002807, 0x00000000, 0x32000300, + 0x00000000, 0x00000000, 0x04022004, 0x01040100, + 0x00010000, 0x00000100, 0x000000AA, 0x00000055, + 0x000000B5, 0x0000004A, 0x00000056, 0x000000A9, + 0x000000A9, 0x000000B5, 0x00000000, 0x01000000, + 0x00030300, 0x0000001A, 0x000007D0, 0x00000300, + 0x00000000, 0x00000000, 0x01000000, 0x00000101, + 0x00000000, 0x00000000, 0x00000000, 0x00000200, + 0x03030300, 0x01000000, 0x00000000, 0x00000100, + 0x00000003, 0x001100EF, 0x01A1120B, 0x00051400, + 0x001A0700, 0x001101FC, 0x00011A00, 0x00000000, + 0x001F0000, 0x00000000, 0x00000000, 0x00051500, + 0x001103FC, 0x00011A00, 0x00051500, 0x001102FC, + 0x00011A00, 0x00001A00, 0x00000000, 0x001F0000, + 0x001100FC, 0x00011A00, 0x01A1120B, 0x001A0701, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x001100EF, 0x01A1120B, 0x00051400, 0x01910480, + 0x01821009, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001A0700, 0x01A11E14, + 0x001101FC, 0x00211A00, 0x00051500, 0x001103FC, + 0x00011A00, 0x00051500, 0x001102FC, 0x00011A00, + 0x00031A00, 0x001A0701, 0x00000000, 0x001F0000, + 0x00000000, 0x00000000, 0x01A11E14, 0x01A1120B, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100FD, 0x00012E00, + 0x00051700, 0x01A1120B, 0x001A0701, 0x001F0000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x00051400, 0x001A0700, 0x001102FD, 0x00012E00, + 0x00000000, 0x001F0000, 0x00000000, 0x00000000, + 0x00070700, 0x00000000, 0x01000000, 0x00000300, + 0x17030000, 0x00000000, 0x00000000, 0x00000000, + 0x0A0A140A, 0x10020201, 0x332A0002, 0x01010000, + 0x0B000404, 0x04030308, 0x00010100, 0x02020301, + 0x01001000, 0x00000034, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x55AA55AA, 0x33CC33CC, + 0x0FF00FF0, 0x0F0FF0F0, 0x00008E38, 0x00000001, + 0x00000002, 0x00020001, 0x00020001, 0x02010201, + 0x0000000F, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0xAAAAA593, + 0xA5939999, 0x00000000, 0x00005555, 0x00003333, + 0x0000CCCC, 0x00000000, 0x0003FFFF, 0x00003333, + 0x0000CCCC, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x036DB6DB, 0x00249249, + 0x05B6DB6D, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x00000100, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00010000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00080000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x01180400, + 0x03020100, 0x00060504, 0x00010100, 0x00000008, + 0x00080000, 0x00000001, 0x00000000, 0x0001AA00, + 0x00000100, 0x00000000, 0x00010000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00020000, 0x00000100, 0x00010000, 0x0000000B, + 0x0000001C, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x03010000, 0x01000100, + 0x01020001, 0x00010300, 0x05000104, 0x01060001, + 0x00010700, 0x00000000, 0x00000000, 0x00010000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000301, 0x00000000, 0x00000000, 0x01010000, + 0x00000000, 0x00000200, 0x00000000, 0xB8000000, + 0x010000FF, 0x0000FFE8, 0x00FFA801, 0xFFD80100, + 0x00007F10, 0x00000000, 0x00000034, 0x0000003D, + 0x00020079, 0x02000200, 0x02000204, 0x06000C06, + 0x04040200, 0x04100804, 0x14090004, 0x1C081024, + 0x0000120C, 0x00000015, 0x000000CF, 0x00000026, + 0x0000017F, 0x00000130, 0x04000C2E, 0x00000404, + 0x01080032, 0x01080032, 0x000F0032, 0x00000000, + 0x00000000, 0x00000000, 0x00010300, 0x00010301, + 0x03030000, 0x00000001, 0x00010303, 0x00030000, + 0x0013000C, 0x0A060037, 0x03030526, 0x000C0032, + 0x0017003D, 0x0025004B, 0x00010101, 0x0000000E, + 0x00000019, 0x010000C8, 0x000F000F, 0x0007000C, + 0x001A0100, 0x0015001A, 0x0100000B, 0x00C900C9, + 0x005100A1, 0x29003329, 0x33290033, 0x0A070600, + 0x0A07060D, 0x0D09070D, 0x000C000D, 0x00001000, + 0x00000C00, 0x00001000, 0x00000C00, 0x02001000, + 0x0002000E, 0x00160019, 0x1E1A00C8, 0x00100004, + 0x361C0008, 0x00000000, 0x0000000C, 0x0006000C, + 0x0300361C, 0x04001300, 0x000D0019, 0x0000361C, + 0x20003300, 0x00000000, 0x02000000, 0x04040802, + 0x00060404, 0x0003C34F, 0x05022001, 0x0203000A, + 0x04040408, 0xC34F0604, 0x10010005, 0x040A0502, + 0x0A080F11, 0x1C0A040A, 0x0022C34F, 0x0C0C1002, + 0x00019E0A, 0x0000102C, 0x000002FE, 0x00001DEC, + 0x0000185C, 0x0000F398, 0x04000400, 0x03030400, + 0x002AF803, 0x00002AF8, 0x0000D6D7, 0x00000003, + 0x0000006E, 0x00000016, 0x00004E20, 0x00004E20, + 0x00030D40, 0x00000005, 0x000000C8, 0x00000027, + 0x00027100, 0x00027100, 0x00186A00, 0x00000028, + 0x00000640, 0x01000136, 0x00530040, 0x00010004, + 0x00960040, 0x00010004, 0x04B00040, 0x00000318, + 0x00280005, 0x05040404, 0x00070603, 0x06030503, + 0x0503000D, 0x00640603, 0x06040608, 0x00040604, + 0x00260015, 0x01050130, 0x01000100, 0x00020201, + 0x04040000, 0x01010104, 0x03020302, 0x00000100, + 0x02020101, 0x00000000, 0x09910260, 0x11911600, + 0x19A21009, 0x19A10100, 0x19A10201, 0x19A10302, + 0x19A10A03, 0x19A10B04, 0x19A10C05, 0x19A10E07, + 0x19A10F08, 0x19A1110A, 0x19A1120B, 0x19A1130C, + 0x19A1140D, 0x19A00C00, 0x199F0000, 0x199F0000, + 0x199F0000, 0x199F0000, 0x01910300, 0x01A21009, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x001140BF, 0x01811009, 0x01850400, 0x01A10C05, + 0x01850300, 0x01A10C11, 0x01850300, 0x001100BF, + 0x01811009, 0x01850500, 0x019F0000, 0x019F0000, + 0x01510001, 0x01D102A0, 0x01E21009, 0x00051900, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x01510001, + 0x01D10290, 0x01E21009, 0x01510001, 0x01D10000, + 0x01E21009, 0x00051800, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x0011008F, 0x00910000, + 0x01811009, 0x01910040, 0x01A21009, 0x019F0000, + 0x01911000, 0x01A21009, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x01A10C05, + 0x01A10E07, 0x01A10F08, 0x01A1110A, 0x01A1120B, + 0x01A1130C, 0x01A1140D, 0x01A00C00, 0x01910800, + 0x01A21009, 0x019F0000, 0x019F0000, 0x019F0000, + 0x0101017F, 0x00010101, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x01000101, + 0x00000000, 0x00000000, 0x00050000, 0x00070100, + 0x000F0200, 0x00000000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A00B04, 0x00210D06, 0x01A1110A, + 0x01A1140D, 0x00098000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x019F0000, 0x019F0000, + 0x019F0000, 0x019F0000, 0x01A10100, 0x01A10201, + 0x01A10302, 0x01A10A03, 0x01A10B04, 0x00210D06, + 0x01A1110A, 0x00000000, 0x01A1140D, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x000A0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x000A0000, 0x01061300, + 0x00000000, 0x00000000, 0x00061180, 0x000612C0, + 0x00000000, 0x00000000, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01811009, 0x0011EFAF, + 0x01A1120B, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001100BF, + 0x01A1120B, 0x080D0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x080C0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001F0200, 0x001F0200, + 0x001F0200, 0x001F0200, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01A1120B, 0x001F0000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00211F14, 0x00212014, + 0x00212116, 0x00212217, 0x001F0000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x001A85FF, 0x00051E00, 0x001F0000, 0x00000000, + 0x00211F14, 0x00212015, 0x00212116, 0x00212217, + 0x01A1120B, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x0031FFBF, 0x01A11009, + 0x01A10E07, 0x01A10F08, 0x003100BF, 0x01A11009, + 0x00051800, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x08084340, 0x0011FFFF, + 0x2011FFFB, 0x00012E00, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x083E4340, 0x00212E00, + 0x01A1120B, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x08201020, + 0x28100020, 0x08083020, 0x08400020, 0x08402020, + 0x08483020, 0x10083020, 0x20180020, 0x30480020, + 0x78880020, 0x488010E0, 0x494B0000, 0x49089080, + 0x49080000, 0x490011C0, 0x0A000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x08000020, 0x08000020, 0x08000020, 0x08000020, + 0x001100FF, 0x01810302, 0x001100DF, 0x00010D06, + 0x001100EF, 0x01A1120B, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x00010D06, 0x01810302, 0x0181160E, 0x001F0000, + 0x001F0000, 0x001F0000, 0x001F0000, 0x001F0000, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x081A52FD, 0x001A12FF, + 0x00051A00, 0x001A13FF, 0x00051B00, 0x001F13FF, + 0x081A52FD, 0x001A12FF, 0x00051A00, 0x001A13FF, + 0x00051B00, 0x001F13FF, 0x00032300, 0x00032400, + 0x001F0000, 0x001F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x00800000, 0x0031FFBF, + 0x01A11009, 0x01A10E07, 0x01A10F08, 0x003100BF, + 0x01A11009, 0x00051800, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x003F0000, 0x003F0000, + 0x003F0000, 0x003F0000, 0x081100DF, 0x08010D06, + 0x0011000F, 0x0181160E, 0x001100EF, 0x01A1120B, + 0x001F0000, 0x001F0000, 0x001F0000, 0x009C0000, + 0x08010D06, 0x0181160E, 0x01A1120B, 0x001F0000, + 0x001F0000, 0x001F0000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x11910048, + 0x09910060, 0x19A21009, 0x19A10100, 0x19A10201, + 0x19A10302, 0x19A10A03, 0x19A10B04, 0x18051C00, + 0x19A1110A, 0x19A1120B, 0x19A1130C, 0x19A1140D, + 0x19A1160E, 0x181140BF, 0x19A11009, 0x19A10C05, + 0x19A00C00, 0x19A10E07, 0x19A10F08, 0x19910280, + 0x19A21009, 0x18051000, 0x18861101, 0x181F0000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18861100, + 0x19A11009, 0x101B0001, 0x181B0100, 0x18000500, + 0x181B0200, 0x00000000, 0x181B0600, 0x181B0C00, + 0x181B0100, 0x181B0200, 0x181B0300, 0x181B0400, + 0x181F0000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x18000000, 0x18000000, 0x18000000, + 0x18000000, 0x004B1040, 0x001011C0, 0x00089080, + 0x000811C0, 0x040811C0, 0x02000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x5F407FAA, + 0x007B776F, 0x4AB555AA, 0xB5A9A956, 0x9F80BFAA, + 0x00BBB7AF, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00002AF8, 0x0000D6D7, 0x0000006E, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000000E, 0x00000019, 0x000000C8, + 0x00000001, 0x00000001, 0x00000003, 0x00000007, + 0x00000007, 0x00000009, 0x00000001, 0x00000001, + 0x00000003, 0x00000001, 0x00000001, 0x00000003, + 0x0000006E, 0x000000C8, 0x00000640, 0x00000001, + 0x00000001, 0x00000003, 0x00000002, 0x00000004, + 0x0000001C, 0x00000007, 0x0000000B, 0x00000051, + 0x0000000C, 0x00000015, 0x000000A1, 0x00000003, + 0x00000000, 0x0000000C, 0x00000000, 0x00000000, + 0x00000000, 0x0000000F, 0x0000000F, 0x0000000F, + 0x00002AF9, 0x00002AF9, 0x00002AF9, 0x00000034, + 0x0000001E, 0x0000003C, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x000000C0, 0x00000000, 0x00000000, 0x55550000, + 0x00003C5A, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00D60000, + 0x50005000, 0x803E0050, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C61110, 0x2C002834, 0x0C06002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C6BBB0, + 0x2C002834, 0x0C06002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00D60000, 0x50005000, 0x803E0050, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x00C61110, + 0x2C002834, 0x082E002C, 0x00000200, 0x00000000, + 0x00000000, 0x00007800, 0x00000000, 0x00000000, + 0x00000000, 0x00C6BBB0, 0x2C002834, 0x082E002C, + 0x00000200, 0x00000000, 0x00000000, 0x00007800, + 0x00000000, 0x00000000, 0x00000000, 0x80808080, + 0x800D8080, 0x80808080, 0x17808080, 0x80808025, + 0x2221201F, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x80808080, + 0x80808080, 0x80808080, 0x80808080, 0x0A030201, + 0x0E800C0B, 0x1211100F, 0x80161413, 0x08004C80, + 0x8080801E, 0x80804E80, 0x80808080, 0x80808080, + 0x80808080 +}; + +struct dbsc5_table_patch { + const u32 reg; + const u32 val; +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3200[] = { + { PHY_REGULATOR_EN_CNT, 0x10 }, + { PHY_RX_CAL_ALL_DLY, 0x07 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x08 }, + { PHY_RDDATA_EN_OE_DLY, 0x0B }, + { PHY_RPTR_UPDATE, 0x07 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x25 }, + { PHY_RDLVL_MAX_EDGE, 0x012D }, + { PHY_RDDATA_EN_DLY, 0x0B }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x05 }, + { PHY_GTLVL_LAT_ADJ_START, 0x03 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3200[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3200[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x57 }, + { PI_TREF_F2, 0x613 }, + { PI_TDFI_WRLVL_WW_F0, 0x2B }, + { PI_TDFI_WRLVL_WW_F1, 0x2B }, + { PI_TDFI_WRLVL_WW_F2, 0x2B }, + { PI_RDLAT_ADJ_F2, 0x22 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1D }, + { PI_TDFI_CALVL_CC_F2, 0x43 }, + { PI_TVRCG_ENABLE_F2, 0x51 }, + { PI_TVRCG_DISABLE_F2, 0x29 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x64 }, + { PI_TCKEHDQS_F2, 0x12 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x10 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x1E }, + { PI_TWTR_S_F2, 0x05 }, + { PI_TWTR_L_F2, 0x05 }, + { PI_TWTR_F2, 0x05 }, + { PI_TWR_F2, 0x0E }, + { PI_TDQSCK_MAX_F2, 0x01 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0C26 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x797C }, + { PI_TXSNR_F2, 0x9B }, + { PI_ZQRESET_F2, 0x0014 }, + { PI_TCBTRTW_F2, 0x04 }, + { PI_SEQ_WAIT_16_F2, 0x000064 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x000320 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x00000E }, + { PI_SEQ_WAIT_24_F2, 0x000029 }, + { PI_SEQ_WAIT_25_F2, 0x000051 }, + { PI_SEQ_WAIT_26_F2, 0x000003 }, + { PI_SEQ_WAIT_30_F2, 0x00002B }, + { PI_WRDCM_LVL_EN_F1, 0x00 }, + { PI_WRDCM_LVL_EN_F2, 0x00 }, + { PI_DRAMDCA_LVL_EN_F1, 0x00 }, + { PI_DRAMDCA_LVL_EN_F2, 0x00 }, + { PI_TINIT_F2, 0x013880 }, + { PI_TINIT1_F2, 0x013880 }, + { PI_TINIT3_F2, 0x0C3500 }, + { PI_TINIT4_F2, 0x000014 }, + { PI_TINIT5_F2, 0x000320 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_3733[] = { + { PHY_REGULATOR_EN_CNT, 0x13 }, + { PHY_RX_CAL_ALL_DLY, 0x08 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0A }, + { PHY_RDDATA_EN_OE_DLY, 0x0D }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2A }, + { PHY_RDLVL_MAX_EDGE, 0x0149 }, + { PHY_RDDATA_EN_DLY, 0x0D }, + { PHY_RDDQS_LATENCY_ADJUST, 0x04 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x9C }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_3733[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_3733[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x5B }, + { PI_TREF_F2, 0x717 }, + { PI_TDFI_WRLVL_WW_F0, 0x2C }, + { PI_TDFI_WRLVL_WW_F1, 0x2C }, + { PI_TDFI_WRLVL_WW_F2, 0x2C }, + { PI_RDLAT_ADJ_F2, 0x24 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x1F }, + { PI_TDFI_CALVL_CC_F2, 0x45 }, + { PI_TVRCG_ENABLE_F2, 0x5F }, + { PI_TVRCG_DISABLE_F2, 0x30 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TDFI_CALVL_STROBE_F2, 0x06 }, + { PI_TFC_F2, 0x75 }, + { PI_TCKEHDQS_F2, 0x13 }, + { PI_TDFI_WDQLVL_RW_F2, 0x09 }, + { PI_TDFI_WDQLVL_WR_F2, 0x12 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x10 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x20 }, + { PI_TWTR_S_F2, 0x06 }, + { PI_TWTR_L_F2, 0x06 }, + { PI_TWTR_F2, 0x06 }, + { PI_TWR_F2, 0x10 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x0E2E }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0x8DCC }, + { PI_TXSNR_F2, 0xB5 }, + { PI_ZQRESET_F2, 0x0018 }, + { PI_TCBTRTW_F2, 0x05 }, + { PI_SEQ_WAIT_16_F2, 0x000075 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0003A6 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000011 }, + { PI_SEQ_WAIT_24_F2, 0x000030 }, + { PI_SEQ_WAIT_25_F2, 0x00005F }, + { PI_SEQ_WAIT_26_F2, 0x000005 }, + { PI_SEQ_WAIT_30_F2, 0x00002D }, + { PI_TINIT_F2, 0x016C90 }, + { PI_TINIT1_F2, 0x016C90 }, + { PI_TINIT3_F2, 0x0E3D98 }, + { PI_TINIT4_F2, 0x000018 }, + { PI_TINIT5_F2, 0x0003A6 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4266[] = { + { PHY_REGULATOR_EN_CNT, 0x16 }, + { PHY_RX_CAL_ALL_DLY, 0x09 }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0B }, + { PHY_RDDATA_EN_OE_DLY, 0x0E }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x2E }, + { PHY_RDLVL_MAX_EDGE, 0x0164 }, + { PHY_RDDATA_EN_DLY, 0x0E }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x30 }, + { PHY_GTLVL_LAT_ADJ_START, 0x04 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4266[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4266[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x64 }, + { PI_TREF_F2, 0x81C }, + { PI_TDFI_WRLVL_WW_F0, 0x2D }, + { PI_TDFI_WRLVL_WW_F1, 0x2D }, + { PI_TDFI_WRLVL_WW_F2, 0x2D }, + { PI_RDLAT_ADJ_F2, 0x2B }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x20 }, + { PI_TDFI_CALVL_CC_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x6C }, + { PI_TVRCG_DISABLE_F2, 0x37 }, + { PI_TXP_F2, 0x07 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TFC_F2, 0x86 }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x13 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x14 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x27 }, + { PI_TWTR_S_F2, 0x07 }, + { PI_TWTR_L_F2, 0x07 }, + { PI_TWTR_F2, 0x07 }, + { PI_TWR_F2, 0x13 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1038 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xA230 }, + { PI_TXSNR_F2, 0xCF }, + { PI_ZQRESET_F2, 0x001B }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000086 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000007 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x00042B }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000013 }, + { PI_SEQ_WAIT_24_F2, 0x000037 }, + { PI_SEQ_WAIT_25_F2, 0x00006C }, + { PI_SEQ_WAIT_26_F2, 0x000006 }, + { PI_SEQ_WAIT_30_F2, 0x000032 }, + { PI_TINIT_F2, 0x01A0AB }, + { PI_TINIT1_F2, 0x01A0AB }, + { PI_TINIT3_F2, 0x1046AB }, + { PI_TINIT4_F2, 0x00001B }, + { PI_TINIT5_F2, 0x00042B } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_4800[] = { + { PHY_REGULATOR_EN_CNT, 0x18 }, + { PHY_RX_CAL_ALL_DLY, 0x0A }, + { PHY_RDDATA_EN_TSEL_DLY, 0x0D }, + { PHY_RDDATA_EN_OE_DLY, 0x10 }, + { PHY_RPTR_UPDATE, 0x08 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x31 }, + { PHY_RDLVL_MAX_EDGE, 0x017F }, + { PHY_RDDATA_EN_DLY, 0x10 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x05 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0xC6 }, + { PHY_GTLVL_LAT_ADJ_START, 0x05 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_4800[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_4800[] = { + { PI_TCKCKEL_F2, 0x03 }, + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x68 }, + { PI_RDLAT_ADJ_F2, 0x2D }, + { PI_TREF_F2, 0x920 }, + { PI_TDFI_WRLVL_WW_F0, 0x2E }, + { PI_TDFI_WRLVL_WW_F1, 0x2E }, + { PI_TDFI_WRLVL_WW_F2, 0x2E }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x21 }, + { PI_TDFI_CALVL_CC_F2, 0x47 }, + { PI_TVRCG_DISABLE_F2, 0x3D }, + { PI_TVRCG_ENABLE_F2, 0x79 }, + { PI_TXP_F2, 0x08 }, + { PI_TMRWCKEL_F2, 0x0A }, + { PI_TCKEHDQS_F2, 0x14 }, + { PI_TFC_F2, 0x96 }, + { PI_TDFI_WDQLVL_RW_F2, 0x0B }, + { PI_TDFI_WDQLVL_WR_F2, 0x15 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x18 }, + { PI_MBIST_RDLAT_ADJ_F2, 0x29 }, + { PI_TWTR_S_F2, 0x08 }, + { PI_TWR_F2, 0x15 }, + { PI_TWTR_F2, 0x08 }, + { PI_TWTR_L_F2, 0x08 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x1240 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xB680 }, + { PI_TXSNR_F2, 0x0E9 }, + { PI_ZQRESET_F2, 0x001E }, + { PI_TCBTRTW_F2, 0x06 }, + { PI_SEQ_WAIT_16_F2, 0x000096 }, + { PI_SEQ_WAIT_17_F2, 0x000002 }, + { PI_SEQ_WAIT_18_F2, 0x000008 }, + { PI_SEQ_WAIT_19_F2, 0x000002 }, + { PI_SEQ_WAIT_20_F2, 0x000002 }, + { PI_SEQ_WAIT_21_F2, 0x0004B0 }, + { PI_SEQ_WAIT_22_F2, 0x000002 }, + { PI_SEQ_WAIT_23_F2, 0x000015 }, + { PI_SEQ_WAIT_24_F2, 0x00003D }, + { PI_SEQ_WAIT_25_F2, 0x000079 }, + { PI_SEQ_WAIT_26_F2, 0x000008 }, + { PI_SEQ_WAIT_30_F2, 0x000034 }, + { PI_TINIT_F2, 0x01D4A9 }, + { PI_TINIT1_F2, 0x01D4A9 }, + { PI_TINIT3_F2, 0x124E91 }, + { PI_TINIT4_F2, 0x00001E }, + { PI_TINIT5_F2, 0x0004B0 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_5500[] = { + { PHY_REGULATOR_EN_CNT, 0x1C }, + { PHY_RX_CAL_ALL_DLY, 0x0C }, + { PHY_RDDATA_EN_TSEL_DLY, 0x10 }, + { PHY_RDDATA_EN_OE_DLY, 0x13 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x37 }, + { PHY_RDLVL_MAX_EDGE, 0x01A3 }, + { PHY_RDDATA_EN_DLY, 0x13 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x06 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x8F }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_5500[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_5500[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x71 }, + { PI_RDLAT_ADJ_F2, 0x32 }, + { PI_TREF_F2, 0xA79 }, + { PI_TDFI_WRLVL_WW_F0, 0x30 }, + { PI_TDFI_WRLVL_WW_F1, 0x30 }, + { PI_TDFI_WRLVL_WW_F2, 0x30 }, + { PI_TDFI_CALVL_CAPTURE_F2, 0x23 }, + { PI_TDFI_CALVL_CC_F2, 0x49 }, + { PI_TVRCG_DISABLE_F2, 0x46 }, + { PI_TVRCG_ENABLE_F2, 0x8B }, + { PI_TMRWCKEL_F2, 0x0B }, + { PI_TCKEHDQS_F2, 0x15 }, + { PI_TFC_F2, 0xAD }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_TDFI_WDQLVL_WR_F2, 0x17 }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x2E }, + { PI_TWTR_S_F2, 0x09 }, + { PI_TWR_F2, 0x18 }, + { PI_TWTR_F2, 0x09 }, + { PI_TWTR_L_F2, 0x09 }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x14F2 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xD174 }, + { PI_TXSNR_F2, 0x10B }, + { PI_ZQRESET_F2, 0x0023 }, + { PI_TCBTRTW_F2, 0x07 }, + { PI_SEQ_WAIT_16_F2, 0x0000AD }, + { PI_SEQ_WAIT_21_F2, 0x000561 }, + { PI_SEQ_WAIT_23_F2, 0x000019 }, + { PI_SEQ_WAIT_24_F2, 0x000046 }, + { PI_SEQ_WAIT_25_F2, 0x00008B }, + { PI_SEQ_WAIT_26_F2, 0x00000A }, + { PI_SEQ_WAIT_30_F2, 0x000038 }, + { PI_TINIT_F2, 0x0219AF }, + { PI_TINIT1_F2, 0x0219AF }, + { PI_TINIT3_F2, 0x1500CF }, + { PI_TINIT4_F2, 0x000023 }, + { PI_TINIT5_F2, 0x000561 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_6000[] = { + { PHY_REGULATOR_EN_CNT, 0x1F }, + { PHY_RDDATA_EN_TSEL_DLY, 0x12 }, + { PHY_RDDATA_EN_OE_DLY, 0x15 }, + { PHY_WRLVL_RESP_WAIT_CNT, 0x3A }, + { PHY_RDLVL_MAX_EDGE, 0x01BD }, + { PHY_RDDATA_EN_DLY, 0x15 }, + { PHY_RDDQS_LATENCY_ADJUST, 0x07 }, + { PHY_RDDQS_GATE_SLAVE_DELAY, 0x1B }, + { PHY_GTLVL_LAT_ADJ_START, 0x06 }, + { PHY_LP4_BOOT_RX_PCLK_CLK_SEL, 0x00 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_6000[] = { + { PHY_ADR_MEAS_DLY_STEP_ENABLE, 0x00 }, + { PHY_ADR_CALVL_DLY_STEP, 0x02 } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_pi_6000[] = { + { PI_TDELAY_RDWR_2_BUS_IDLE_F2, 0x75 }, + { PI_RDLAT_ADJ_F2, 0x34 }, + { PI_TREF_F2, 0xB6B }, + { PI_TDFI_WRLVL_WW_F0, 0x31 }, + { PI_TDFI_WRLVL_WW_F1, 0x31 }, + { PI_TDFI_WRLVL_WW_F2, 0x31 }, + { PI_TVRCG_DISABLE_F2, 0x4D }, + { PI_TVRCG_ENABLE_F2, 0x98 }, + { PI_TMRWCKEL_F2, 0x0C }, + { PI_TFC_F2, 0xBC }, + { PI_TDFI_WDQLVL_RW_F2, 0x0C }, + { PI_MBIST_TWCKENL_RD_ADJ_F2, 0x1C }, + { PI_MBIST_RDLAT_ADJ_F2, 0x30 }, + { PI_TWR_F2, 0x1A }, + { PI_TDFI_CTRLUPD_MAX_F2, 0x16D6 }, + { PI_TDFI_CTRLUPD_INTERVAL_F2, 0xE45C }, + { PI_TXSNR_F2, 0x123 }, + { PI_ZQRESET_F2, 0x0026 }, + { PI_SEQ_WAIT_16_F2, 0x0000BC }, + { PI_SEQ_WAIT_21_F2, 0x0005DD }, + { PI_SEQ_WAIT_23_F2, 0x00001B }, + { PI_SEQ_WAIT_24_F2, 0x00004D }, + { PI_SEQ_WAIT_25_F2, 0x000098 }, + { PI_SEQ_WAIT_30_F2, 0x00003A }, + { PI_TINIT_F2, 0x024A16 }, + { PI_TINIT1_F2, 0x024A16 }, + { PI_TINIT3_F2, 0x16E4D8 }, + { PI_TINIT4_F2, 0x000026 }, + { PI_TINIT5_F2, 0x0005DD } +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_640 = { + PHY_DATA_DC_CAL_CLK_SEL, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_v_mbpsdiv_640 = { + PHY_CLK_DC_CAL_CLK_SEL, 0x04 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_640 = { + PHY_CAL_CLK_SELECT_0, 0x05 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_slice_mbpsdiv_572 = { + PHY_RX_PCLK_CLK_SEL, 0x3 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_572 = { + PHY_PAD_ACS_RX_PCLK_CLK_SEL, 0x02 +}; + +static const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbpsdiv_400[] = { + { PHY_PLL_CTRL, 0x1542 }, + { PHY_PLL_CTRL_8X, 0x3342 } +}; + +/* Array of addresses for setting PI_DARRAY3_0 in each CS and frequency-set */ +static const u32 PI_DARRAY3_0_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_0_CS0_F0, PI_DARRAY3_0_CS0_F1, PI_DARRAY3_0_CS0_F2 }, + { PI_DARRAY3_0_CS1_F0, PI_DARRAY3_0_CS1_F1, PI_DARRAY3_0_CS1_F2 } +}; + +/* Array of addresses for setting PI_DARRAY3_1 in each CS and frequency-set */ +static const u32 PI_DARRAY3_1_CSx_Fx[CS_CNT][3] = { + { PI_DARRAY3_1_CS0_F0, PI_DARRAY3_1_CS0_F1, PI_DARRAY3_1_CS0_F2 }, + { PI_DARRAY3_1_CS1_F0, PI_DARRAY3_1_CS1_F1, PI_DARRAY3_1_CS1_F2 } +}; + +/* DBSC registers */ +#define DBSC_DBSYSCONF0 0x0 +#define DBSC_DBSYSCONF1 0x0 +#define DBSC_DBSYSCONF1A 0x4 +#define DBSC_DBSYSCONF2 0x4 +#define DBSC_DBPHYCONF0 0x8 +#define DBSC_DBSYSCONF2A 0x8 +#define DBSC_DBMEMKIND 0x20 +#define DBSC_DBMEMKINDA 0x20 +#define DBSC_DBMEMCONF(ch, cs) (0x30 + (0x2000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBMEMCONFA(ch, cs) (0x30 + (0x4000 * ((ch) & 0x2)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBSYSCNT0 0x100 +#define DBSC_DBSYSCNT0A 0x100 +#define DBSC_DBACEN 0x200 +#define DBSC_DBRFEN 0x204 +#define DBSC_DBCMD 0x208 +#define DBSC_DBCMD_CMD_OPCODE_PD 0x8 +#define DBSC_DBCMD_CMD_OPCODE_MRW 0xe +#define DBSC_DBCMD_CMD_OPCODE_MRR 0xf +#define DBSC_DBCMD_CMD_CHANNEL_ALL 0x8 +#define DBSC_DBCMD_CMD_RANK_ALL 0x4 +#define DBSC_DBWAIT 0x210 +#define DBSC_DBBL 0x400 +#define DBSC_DBBLA 0x400 +#define DBSC_DBRFCNF1 0x414 +#define DBSC_DBRFCNF2 0x418 +#define DBSC_DBCALCNF 0x424 +#define DBSC_DBDBICNT 0x518 +#define DBSC_DBDFIPMSTRCNF 0x520 +#define DBSC_DBDFICUPDCNF 0x540 +#define DBSC_DBBCAMDIS 0x9FC +#define DBSC_DBSCHRW1 0x1024 +#define DBSC_DBSCHTR0 0x1030 +#define DBSC_DBTR(x) (0x300 + (0x4 * (x))) +#define DBSC_DBRNK(x) (0x430 + (0x4 * (x))) +#define DBSC_DBDFISTAT(ch) (0x600 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBDFICNT(ch) (0x604 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDCNT2(ch) (0x618 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDLK(ch) (0x620 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGA(ch) (0x624 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGD(ch) (0x628 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDRGM(ch) (0x62C + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT0(ch) (0x630 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT1(ch) (0x634 + (0x2000 * ((ch) & 0x2)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBSCHFCTST0 0x1040 +#define DBSC_DBSCHFCTST1 0x1044 + +/* CPG PLL3 registers */ +#define CPG_CPGWPR 0x0 +#define CPG_FRQCRD0 0x80C +#define CPG_PLLECR 0x820 +#define CPG_PLL3CR0 0x83C +#define CPG_PLL3CR1 0x8C0 +#define CPG_FSRCHKCLRR4 0x590 +#define CPG_FSRCHKSETR4 0x510 +#define CPG_FSRCHKRA4 0x410 +#define CPG_SRCR4 0x2C10 +#define CPG_SRSTCLR4 0x2C90 + +#define CPG_FRQCRD_KICK_BIT BIT(31) +#define CPG_PLL3CR0_KICK_BIT BIT(31) +#define CPG_PLLECR_PLL3ST_BIT BIT(11) + +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +struct renesas_dbsc5_dram_priv { + void __iomem *regs; + void __iomem *cpg_regs; + + /* The board parameter structure of the board */ + const struct renesas_dbsc5_board_config *dbsc5_board_config; + + /* The board clock frequency */ + u32 brd_clk; + u32 brd_clkdiv; + u32 brd_clkdiva; + + /* The Mbps of Bus */ + u32 bus_clk; + u32 bus_clkdiv; + + /* The Mbps of DDR */ + u32 ddr_mbps; + u32 ddr_mbpsdiv; + + /* DDR memory multiplier setting value */ + u32 ddr_mul; + u32 ddr_mul_nf; + u32 ddr_mul_low; + u32 ddr_mul_reg; + + /* Value indicating the enabled channel */ + u32 ddr_phyvalid; + + /* The tccd value of DDR */ + u32 ddr_tccd; + + /* Memory capacity in each channel and each CS */ + u8 ddr_density[DRAM_CH_CNT][CS_CNT]; + /* Channels used for each memory rank */ + u32 ch_have_this_cs[CS_CNT]; + /* The maximum memory capacity */ + u32 max_density; + + /* Index of jedec spec1 setting table you use */ + u32 js1_ind; + /* Array of jedec spec2 setting table */ + u32 js2[JS2_CNT]; + /* Read latency */ + u32 RL; + /* Write latency */ + u32 WL; + + /* Array for DDR PI Slice settings */ + u32 DDR_PI_REGSET[DDR_PI_REGSET_NUM_V4H]; + /* Array for DDRPHY Slice settings */ + u32 DDR_PHY_SLICE_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS VALUE Slice settings */ + u32 DDR_PHY_ADR_V_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; + /* Array for DDRPHY ADRRESS CONTROL Slice settings */ + u32 DDR_PHY_ADR_G_REGSET[DDR_PHY_SLICE_REGSET_NUM_V4H]; +}; + +static const struct renesas_dbsc5_board_config renesas_v4h_dbsc5_board_config = { + /* RENESAS V4H White Hawk (64Gbit 1rank) */ + .bdcfg_phyvalid = 0xF, + .bdcfg_vref_r = 0x0, + .bdcfg_vref_w = 0x0, + .bdcfg_vref_ca = 0x0, + .bdcfg_rfm_chk = true, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x04506132, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x26147085, 0x12306845 }, + .bdcfg_dm_swap = { 0x03, 0x07 }, + .bdcfg_cs_swap = 0x10 + }, + [1] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02341065, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x56782314, 0x71048365 }, + .bdcfg_dm_swap = { 0x00, 0x02 }, + .bdcfg_cs_swap = 0x10 + }, + [2] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x02150643, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x58264071, 0x41207536 }, + .bdcfg_dm_swap = { 0x03, 0x08 }, + .bdcfg_cs_swap = 0x10 + }, + [3] = { + .bdcfg_ddr_density = { 0x06, 0xFF }, + .bdcfg_ca_swap = 0x01546230, + .bdcfg_dqs_swap = 0x01, + .bdcfg_dq_swap = { 0x45761328, 0x62801745 }, + .bdcfg_dm_swap = { 0x00, 0x03 }, + .bdcfg_cs_swap = 0x10 + } + } +}; + +/** + * r_vch_nxt() - Macro for channel selection loop + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 r_vch_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + int posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + if (priv->ddr_phyvalid & BIT(posn)) + break; + + return posn; +} + +/* Select only valid channels in all channels from CH0. */ +#define r_foreach_vch(dev, ch) \ +for ((ch) = r_vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = r_vch_nxt((dev), (ch) + 1)) + +/* All channels are selected. */ +#define r_foreach_ech(ch) \ +for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/** + * dbsc5_clk_cpg_write_32() - Write clock control register + * + * Write the complement value of setting value to the CPG_CPGWPR register + * for releaseing the protect. Write setting value to destination address. + */ +static void dbsc5_clk_cpg_write_32(struct udevice *dev, void __iomem *a, u32 v) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + writel(~v, priv->cpg_regs + CPG_CPGWPR); + writel(v, a); +} + +enum dbsc5_clk_pll3_mode { + PLL3_LOW_FREQUENCY_MODE = 0, + PLL3_HIGH_FREQUENCY_MODE, + PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER +}; + +/** + * dbsc5_clk_pll3_control() - Set PLL3 + * @dev: DBSC5 device + * @mode: PLL3 frequency mode + * + * Determine the set value according to the frequency mode of the argument. + * Write the set value to CPG_FRQCRD0 register and CPG_FRQCRD0 one. + * Reflect settings + */ +static void dbsc5_clk_pll3_control(struct udevice *dev, u32 mode) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 data_div, data_mul, data_nf, ssmode, val; + int ret; + + /* + * PLL3VCO = EXTAL * priv->ddr_mul * 1/2 + * clk_ctlr_sync = PLL3VCO * pll3_div + * priv->ddr_mul = (NI[7:0] + 1) * 2 + NF[24:0] / 2^24 + */ + + switch (mode) { + case PLL3_LOW_FREQUENCY_MODE: + /* Low frequency mode (50MHz) */ + data_mul = (priv->ddr_mul_low / 2) - 1; /* PLL3VCO = 1600MHz */ + data_div = 0x9; /* div = 32 */ + data_nf = 0x0; + ssmode = 0x0; + break; + case PLL3_HIGH_FREQUENCY_MODE: + /* High frequency mode */ + data_mul = (priv->ddr_mul / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = priv->ddr_mul_nf; + ssmode = 0x4; + break; + case PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER: + /* High frequency mode for loading to DDRPHY registers */ + data_mul = (priv->ddr_mul_reg / 2) - 1; + data_div = 0x0; /* div = 2 */ + data_nf = 0x0; + ssmode = 0x4; + break; + default: + printf("%s Mode %d not supported\n", __func__, mode); + hang(); + } + + data_mul = (data_mul << 20) | (ssmode << 16); + data_nf = data_nf << 21; + + if (((readl(priv->cpg_regs + CPG_PLL3CR0) & 0x3FFFFF7F) != data_mul) || + (readl(priv->cpg_regs + CPG_PLL3CR1) != data_nf)) { + /* PLL3CR0 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, data_mul); + /* PLL3CR1 multiplie set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR1, data_nf); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_PLL3CR0, + readl(priv->cpg_regs + CPG_PLL3CR0) | + CPG_PLL3CR0_KICK_BIT); + + ret = readl_poll_timeout(priv->cpg_regs + CPG_PLLECR, val, + (val & CPG_PLLECR_PLL3ST_BIT), + 1000000); + if (ret < 0) { + printf("%s CPG_PLLECR bit CPG_PLLECR_PLL3ST_BIT timeout\n", __func__); + hang(); + } + } + + /* PLL3 DIV set(Target value) */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT div set timeout\n", __func__); + hang(); + } + + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + (readl(priv->cpg_regs + CPG_FRQCRD0) & 0xFFFFFFF0) | + data_div); + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FRQCRD0, + readl(priv->cpg_regs + CPG_FRQCRD0) | + CPG_FRQCRD_KICK_BIT); + ret = readl_poll_timeout(priv->cpg_regs + CPG_FRQCRD0, val, + ((val & CPG_FRQCRD_KICK_BIT) == 0), + 1000000); + if (ret < 0) { + printf("%s CPG_FRQCRD0 bit CPG_FRQCRD_KICK_BIT timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_clk_wait_freqchgreq() - Training handshake functions + * + * Check the value of the argument req_assert. If req_assert is 1, wait until + * FREQCHGREQ of all channels is 1 before time expires. If req_assert is 0, + * wait until FREQCHGREQ of all channels is 0 before time expires. Return the + * result of whether time has expired or not as a return value. + */ +static u32 dbsc5_clk_wait_freqchgreq(struct udevice *dev, u32 req_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 count = 0xFFFFFF; + u32 ch, reg; + + do { + reg = !!req_assert; + r_foreach_vch(dev, ch) + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); + count = count - 1; + } while (((reg & 0x1) != !!req_assert) && (count != 0)); + + return count == 0x0; +} + +/** + * dbsc5_clk_set_freqchgack() - Training handshake functions + * @dev: DBSC5 device + * @ack_assert: Select DBSC_DBPDCNT2 content + * + * Check the value of the argument ackassert. If the value of ackassert + * is greater than or equal to 0, write 0xCF01 to DBSC_DBPDCNT2. + * If the value of ackassert is 0, write 0x0 to DBSC_DBPDCNT2. + */ +static void dbsc5_clk_set_freqchgack(struct udevice *dev, u32 ack_assert) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const u32 reg = ack_assert ? 0xcf01 : 0x0; + u32 ch; + + r_foreach_vch(dev, ch) + writel(reg, regs_dbsc_d + DBSC_DBPDCNT2(ch)); +} + +/** + * dbsc5_clk_wait_dbpdstat1() - Wait for status register update + * @dev: DBSC5 device + * @status: Expected status + * + * Read value the DBSC_DBPDSTAT1(ch) register. Wait until the contents + * of the status register are the same as status. + */ +static void dbsc5_clk_wait_dbpdstat1(struct udevice *dev, u32 status) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 i, ch, chk, reg; + + for (i = 0; i < 2; i++) { + do { + reg = status; + chk = 0; + r_foreach_vch(dev, ch) { + reg &= readl(regs_dbsc_d + DBSC_DBPDSTAT1(ch)); + chk |= readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)); + } + } while (reg != status && !(chk & BIT(0))); + } +} + +/** + * dbsc5_clk_pll3_freq() - Set up the pll3 frequency + * @dev: DBSC5 device + * + * Wait for frequency change request. DBSC_DBPDSTAT0 value determines whether + * dbsc5_clk_pll3_control is called in low frequency mode or high frequency + * mode. Call dbsc5_clk_set_freqchgack(1) function. Check update completion until + * timeout. Call dbsc5_clk_set_freqchgack(0) function. If timed out, return with + * error log Wait for status register update. + */ +static int dbsc5_clk_pll3_freq(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 fsel, timeout; + + dbsc5_clk_wait_freqchgreq(dev, 1); + + fsel = (readl(regs_dbsc_d + DBSC_DBPDSTAT0(0)) & 0x300) >> 8; + dbsc5_clk_pll3_control(dev, fsel ? PLL3_HIGH_FREQUENCY_MODE : + PLL3_LOW_FREQUENCY_MODE); + + dbsc5_clk_set_freqchgack(dev, 1); + timeout = dbsc5_clk_wait_freqchgreq(dev, 0); + dbsc5_clk_set_freqchgack(dev, 0); + + if (timeout) { + printf("Time out\n"); + return -ETIMEDOUT; + } + + dbsc5_clk_wait_dbpdstat1(dev, 0x7); + + return 0; +} + +/** + * dbsc5_reg_write() - Write DBSC register + * @addr: Destination address + * @data: Setting value to be written + * + * Write 32bit value @data to register at @addr . + */ +static void dbsc5_reg_write(void __iomem *addr, u32 data) +{ + writel(data, addr); + + if (((uintptr_t)addr & 0x000A0000) == 0x000A0000) + writel(data, addr + 0x4000); + else + writel(data, addr + 0x8000); +} + +/** + * dbsc5_wait_dbwait() - DRAM Command Wait Access Completion + * @dev: DBSC5 device + * + * Wait for DRAM access completion. This is used before sending a command + * to the DRAM to assure no other command is in flight already, or while + * waiting for MRR command to complete. + */ +static void dbsc5_wait_dbwait(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT bit 0 timeout\n", __func__); + hang(); + } + + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBWAIT + 0x4000, val, ((val & BIT(0)) == 0), 1000000); + if (ret < 0) { + printf("%s DBWAIT + 0x4000 bit 0 timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_send_dbcmd2() - DRAM Command Write Access + * @dev: DBSC5 device + * @opcode DRAM controller opcode + * @channel DRAM controller channel (0..3) + * @rank DRAM controller rank (0..1) + * @arg Command and argument bits (command specific encoding) + * + * First, execute the dummy read to DBSC_DBCMD. + * Confirm that no DBSC command operation is in progress 0. + * Write the contents of the command to be sent to DRAM. + */ +static void dbsc5_send_dbcmd2(struct udevice *dev, const u8 opcode, + const u8 channel, const u8 rank, + const u16 arg) +{ + const u32 cmd = (opcode << 24) | (channel << 20) | (rank << 16) | arg; + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + + /* dummy read */ + readl(regs_dbsc_d + DBSC_DBCMD); + + dbsc5_wait_dbwait(dev); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCMD, cmd); +} + +/** + * dbsc5_reg_ddrphy_read() - Read setting from DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * + * Write matching values to DBPDRGA register and read value out of DBSC_DBPDRGD. + * Wait until the write process completed in each step. + */ +static u32 dbsc5_reg_ddrphy_read(struct udevice *dev, u32 ch, u32 regadd) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd | BIT(14), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15) | BIT(14))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + val = readl(regs_dbsc_d + DBSC_DBPDRGA(ch)); + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) again timeout\n", __func__); + hang(); + } + + return readl(regs_dbsc_d + DBSC_DBPDRGD(ch)); +} + +/** + * dbsc5_reg_ddrphy_write(dev, ) - Write setting to DDR PHY register + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * + * Write matching values to DBPDRGA, DBPDRGD, DBPDRGA, DBPDRGA registers. + * Wait until the write process completed in each step. + */ +static void dbsc5_reg_ddrphy_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA timeout\n", __func__); + hang(); + } + + writel(regdata, regs_dbsc_d + DBSC_DBPDRGD(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == (regadd | BIT(15))), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGD timeout\n", __func__); + hang(); + } + + writel(regadd | BIT(15), regs_dbsc_d + DBSC_DBPDRGA(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGA(ch), val, (val == regadd), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGA | BIT(15) timeout\n", __func__); + hang(); + } + + writel(regadd, regs_dbsc_d + DBSC_DBPDRGA(ch)); +} + +/* + * dbsc5_reg_ddrphy_write_all() - Write setting from DDR PHY register for all channels + * @dev: DBSC5 device + * @regadd: Destination address + * @regdata: Value to be written + * + * Wrapper around dbsc5_reg_ddrphy_write() for all channels. + */ +static void dbsc5_reg_ddrphy_write_all(struct udevice *dev, u32 regadd, u32 regdata) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); +} + +/** + * dbsc5_reg_ddrphy_masked_write() - Write setting to DDR PHY register with mask + * @dev: DBSC5 device + * @ch: Target channel + * @regadd: Destination address + * @regdata: Value to be written + * @msk: Register mask + * + * Wrapper around dbsc5_reg_ddrphy_write() with DBPDRGM set. + */ +static void dbsc5_reg_ddrphy_masked_write(struct udevice *dev, u32 ch, u32 regadd, u32 regdata, u32 msk) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 val; + int ret; + + writel(msk, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == msk), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM timeout\n", __func__); + hang(); + } + + dbsc5_reg_ddrphy_write(dev, ch, regadd, regdata); + + writel(0, regs_dbsc_d + DBSC_DBPDRGM(ch)); + ret = readl_poll_timeout(regs_dbsc_d + DBSC_DBPDRGM(ch), val, (val == 0), 1000000); + if (ret < 0) { + printf("%s regs_dbsc_d + DBSC_DBPDRGM != 0 timeout\n", __func__); + hang(); + } +} + +/** + * dbsc5_ddr_setval_slice() - Write setting to DDR PHY hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Calculate the bit field in which to write the setting value + * from encoded register and bitfield @regdef parameter. Call + * dbsc5_reg_ddrphy_masked_write() to write the value to hardware. + */ +static void dbsc5_ddr_setval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef, u32 val) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + const u32 dms = ~((!!(msk & BIT(24)) << 3) | (!!(msk & BIT(16)) << 2) | + (!!(msk & BIT(8)) << 1) | !!(msk & BIT(0))) & 0xf; + + dbsc5_reg_ddrphy_masked_write(dev, ch, adr, val << lsb, dms); +} + +/* + * dbsc5_ddr_setval() - Write setting from DDR PHY hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval(struct udevice *dev, u32 ch, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_slice(dev, ch, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_slice() - Write setting from DDR PHY hardware for all channels and one slice + * @dev: DBSC5 device + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_slice(struct udevice *dev, u32 slice, u32 regdef, u32 val) +{ + u32 ch; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval_slice(dev, ch, slice, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch() - Write setting from DDR PHY hardware for all channels and slice 0 + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch(struct udevice *dev, u32 regdef, u32 val) +{ + dbsc5_ddr_setval_all_ch_slice(dev, 0, regdef, val); +} + +/* + * dbsc5_ddr_setval_all_ch_all_slice() - Write setting from DDR PHY hardware for all channels and all slices + * @dev: DBSC5 device + * @regdef: Encoded PHY/PI register and bitfield + * @val: Value to be written + * + * Wrapper around dbsc5_ddr_setval_all_ch_slice() for slice 0. + */ +static void dbsc5_ddr_setval_all_ch_all_slice(struct udevice *dev, u32 regdef, u32 val) +{ + u32 slice; + + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_all_ch_slice(dev, slice, regdef, val); +} + +/** + * dbsc5_ddr_getval_slice() - Read setting from DDR PHY/PI hardware + * @dev: DBSC5 device + * @ch: Target channel + * @slice: Target slice + * @regdef: Encoded PHY/PI register and bitfield + * + * Calculate the address and the bit-field from "regdef" value. + * Call dbsc5_reg_ddrphy_read() to read value from the target address. + */ +static u32 dbsc5_ddr_getval_slice(struct udevice *dev, u32 ch, u32 slice, u32 regdef) +{ + const u32 adr = DDR_REGDEF_ADR(regdef) + (0x100 * slice); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (dbsc5_reg_ddrphy_read(dev, ch, adr) >> lsb) & msk; +} + +/** + * dbsc5_ddr_getval() - Read setting from DDR PHY/PI hardware slice 0 + * @dev: DBSC5 device + * @ch: Target channel + * @regdef: Encoded PHY/PI register and bitfield + * + * Wrapper around dbsc5_ddr_getval_slice() for slice 0. + */ +static u32 dbsc5_ddr_getval(struct udevice *dev, u32 ch, u32 regdef) +{ + return dbsc5_ddr_getval_slice(dev, ch, 0, regdef); +} + +/** + * dbsc5_table_patch_set() - Modify DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @adrmsk_pi: Use wider address mask for PI register + * @patch: List of modifications to the settings table + * @patchlen: Length of the list of modifications to the settings table + * + * Calculate the target index of settings table, calculate the bit-field + * to write the setting value, and write the setting value to the target + * bit-field in the index. + */ +static void dbsc5_table_patch_set(u32 *tbl, const bool adrmsk_pi, + const struct dbsc5_table_patch *patch, + int patchlen) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + u32 adr, len, lsb, msk; + int i; + + for (i = 0; i < patchlen; i++) { + adr = DDR_REGDEF_ADR(patch[i].reg); + len = DDR_REGDEF_LEN(patch[i].reg); + lsb = DDR_REGDEF_LSB(patch[i].reg); + msk = (len == 32) ? 0xffffffff : ((BIT(len) - 1) << lsb); + + tbl[adr & adrmsk] &= ~msk; + tbl[adr & adrmsk] |= (patch[i].val << lsb) & msk; + } +} + +/** + * dbsc5_ddrtbl_getval() - Read setting from DDR PHY/PI settings table + * @tbl: DDR PHY/PI setting table pointer + * @regdef: Encoded PHY/PI register and bitfield + * @adrmsk_pi: Use wider address mask for PI register + * + * Calculate the target index of *tbl and the bit-field to read the + * setting value and read and return the setting value from the target + * bit-field in the index. + */ +static u32 dbsc5_ddrtbl_getval(const u32 *tbl, u32 regdef, bool adrmsk_pi) +{ + const u32 adrmsk = adrmsk_pi ? 0x7FF : 0xFF; + const u32 adr = DDR_REGDEF_ADR(regdef); + const u32 len = DDR_REGDEF_LEN(regdef); + const u32 lsb = DDR_REGDEF_LSB(regdef); + const u32 msk = (len == 32) ? 0xffffffff : (BIT(len) - 1); + + return (tbl[adr & adrmsk] >> lsb) & msk; +} + +/** + * dbsc5_f_scale() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ps Optimal setting value in pico second + * @cyc Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) +{ + const u32 mul = frac ? 8 : 800000; + const u32 tmp = DIV_ROUND_UP(ps, 10UL) * priv->ddr_mbps; + const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * priv->ddr_mbpsdiv); + + return (f_scale_div > cyc) ? f_scale_div : cyc; +} + +/** + * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 + * @priv: Driver private data + * + * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. + * Only the following array elements are calculated using different formulas from those + * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. + */ +static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv) +{ + const int derate = 0; + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + priv->js2[i] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][i].ps, + jedec_spec2[derate][i].cyc); + } + + priv->js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tZQCALns].ps * 1000UL, 0); + priv->js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tDQ72DQns].ps * 1000UL, 0); + priv->js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, + jedec_spec2[derate][JS2_tCAENTns].ps * 1000UL, 0); + priv->js2[JS2_tRCpb] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPpb]; + priv->js2[JS2_tRCab] = priv->js2[JS2_tRAS] + priv->js2[JS2_tRPab]; + priv->js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_ab[priv->max_density] * 1000UL, 0); + + priv->js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; + priv->js2[JS2_tXSR] = priv->js2[JS2_tRFCab] + + dbsc5_f_scale(priv, false, 7500, 2); + priv->js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; + priv->js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tPDN_DSM].ps * 10UL, 0); + priv->js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXSR_DSM].ps * 10UL, 0); + priv->js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, + jedec_spec2[derate][JS2_tXDSM_XP].ps * 10UL, 0); + priv->js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); +} + +/** + * dbsc5_ddrtbl_calc() - Calculate JS1/JS2 + * @priv: Driver private data + * + * Determine jedec_spec1 configuration table based on priv->ddr_mbps + * and priv->ddr_mbpsdiv. Calculate the value of the jedec_spec2 + * configuration table from priv->ddr_mbps and priv->ddr_mbpsdiv. + */ +static void dbsc5_ddrtbl_calc(struct renesas_dbsc5_dram_priv *priv) +{ + int i; + + /* Search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) + if (js1[i].fx3 * 2 * priv->ddr_mbpsdiv >= priv->ddr_mbps * 3) + break; + + priv->js1_ind = clamp(i, 0, JS1_USABLEC_SPEC_HI); + + priv->RL = js1[priv->js1_ind].RLset1; + priv->WL = js1[priv->js1_ind].WLsetA; + + /* Calculate jedec_spec2 */ + dbsc5_f_scale_js2(priv); +}; + +/** + * dbsc5_ddrtbl_load() Load table data into DDR registers + * @dev: DBSC5 device + * + * Copy the base configuration table to a local array. Change PI register table + * settings to match priv->ddr_mbps and priv->ddr_mbpsdiv. + * + * If the set value vref_r is not 0, change the "Read Vref (SoC side) Training range" + * setting in the configuration table. + * + * If the set value vref_w is not 0, change the "Write Vref (MR14, MR15) Training range" + * setting in the configuration table. + * + * If the set value vref_ca is not 0, change the "CA Vref (MR12) Training range" + * setting in the configuration table. + * + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 5120, + * change the contents of the PHY register setting table. + * If priv->ddr_mbps/priv->ddr_mbpsdiv is less than 4576, + * change the contents of the PHY register setting table. + * + * Reflect the contents of the configuration table in the register. + */ +static void dbsc5_ddrtbl_load(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const struct dbsc5_table_patch dbsc5_table_patch_adr_g_mbps = { + PHY_CAL_INTERVAL_COUNT_0, 10000 * priv->ddr_mbps / priv->ddr_mbpsdiv / 8 / 256, + }; + + const struct dbsc5_table_patch dbsc5_table_patch_pi_js[] = { + { PI_WRLAT_F2, priv->WL }, + { PI_TWCKENL_WR_ADJ_F2, (js1[priv->js1_ind].WCKENLW * 4) + 4 }, + { PI_TWCKENL_RD_ADJ_F2, (js1[priv->js1_ind].WCKENLR * 4) + 4 }, + { PI_TWCKPRE_STATIC_F2, (js1[priv->js1_ind].WCKPRESTA * 4) }, + { PI_TWCKPRE_TOGGLE_RD_F2, (js1[priv->js1_ind].WCKPRETGLR) * 4 }, + { PI_CASLAT_F2, priv->RL }, + { PI_TWCKENL_FS_ADJ_F2, (js1[priv->js1_ind].WCKENLF * 4) + 4 }, + { PI_TRFC_F2, priv->js2[JS2_tRFCab] }, + { PI_WRLVL_WCKOFF_F2, (priv->js2[JS2_tWLWCKOFF]) + 3 }, + { PI_WRLAT_ADJ_F2, (priv->WL * 4) + 2 }, + { PI_TCAENT_F2, priv->js2[JS2_tCAENTns] }, + { PI_TVREF_LONG_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TVREF_SHORT_F2, (priv->js2[JS2_tCAENTns]) + 1 }, + { PI_TRCD_F2, priv->js2[JS2_tRCD] }, + { PI_TRP_F2, priv->js2[JS2_tRPab] }, + { PI_TRTP_F2, js1[priv->js1_ind].nRBTP }, + { PI_TRAS_MIN_F2, priv->js2[JS2_tRAS] }, + { PI_TMRD_F2, (priv->js2[JS2_tMRD]) + 1 }, + { PI_TSR_F2, priv->js2[JS2_tSR] }, + { PI_TZQCAL_F2, priv->js2[JS2_tZQCALns] }, + { PI_TZQLAT_F2, priv->js2[JS2_tZQLAT] }, + { PI_TDQ72DQ_F2, priv->js2[JS2_tDQ72DQns] }, + { PI_MC_TRFC_F2, priv->js2[JS2_tRFCab] }, + }; + + const u32 vref_r = priv->dbsc5_board_config->bdcfg_vref_r; + const struct dbsc5_table_patch dbsc5_table_patch_slice_vref_r[] = { + { PHY_VREF_INITIAL_START_POINT, vref_r & 0xFF }, + { PHY_VREF_INITIAL_STOP_POINT, (vref_r & 0xFF00) >> 8 }, + { PHY_VREF_INITIAL_STEPSIZE, (vref_r & 0xFF0000) >> 16 } + }; + + const u32 vref_w = priv->dbsc5_board_config->bdcfg_vref_w; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_w[] = { + { PI_WDQLVL_VREF_INITIAL_START_POINT_F0, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F1, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_START_POINT_F2, vref_w & 0xff }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1, (vref_w & 0xff00) >> 8 }, + { PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2, (vref_w & 0xff00) >> 8 } + }; + + const u32 vref_ca = priv->dbsc5_board_config->bdcfg_vref_ca; + const struct dbsc5_table_patch dbsc5_table_patch_pi_vref_ca[] = { + { PI_CALVL_VREF_INITIAL_START_POINT_F0, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F1, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_START_POINT_F2, vref_ca & 0xff }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F0, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F1, (vref_ca & 0xff00) >> 8 }, + { PI_CALVL_VREF_INITIAL_STOP_POINT_F2, (vref_ca & 0xff00) >> 8 } + }; + + int i, cs, slice; + u32 adr; + + /* Prepare register tables */ + memcpy(priv->DDR_PHY_SLICE_REGSET, DDR_PHY_SLICE_REGSET_V4H, sizeof(DDR_PHY_SLICE_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_V_REGSET, DDR_PHY_ADR_V_REGSET_V4H, sizeof(DDR_PHY_ADR_V_REGSET_V4H)); + memcpy(priv->DDR_PHY_ADR_G_REGSET, DDR_PHY_ADR_G_REGSET_V4H, sizeof(DDR_PHY_ADR_G_REGSET_V4H)); + memcpy(priv->DDR_PI_REGSET, DDR_PI_REGSET_V4H, sizeof(DDR_PI_REGSET_V4H)); + + /* Adjust PI parameters */ + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbps, 1); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_js, + ARRAY_SIZE(dbsc5_table_patch_pi_js)); + + if (priv->ddr_mbps < (3201 * priv->ddr_mbpsdiv)) { + /* 2751-3200 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3200, + ARRAY_SIZE(dbsc5_table_patch_slice_3200)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3200, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3200)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3200, + ARRAY_SIZE(dbsc5_table_patch_pi_3200)); + } else if (priv->ddr_mbps < (3734 * priv->ddr_mbpsdiv)) { + /* 3201-3733 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_3733, + ARRAY_SIZE(dbsc5_table_patch_slice_3733)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_3733, + ARRAY_SIZE(dbsc5_table_patch_adr_v_3733)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_3733, + ARRAY_SIZE(dbsc5_table_patch_pi_3733)); + } else if (priv->ddr_mbps < (4268 * priv->ddr_mbpsdiv)) { + /* 3734-4267 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4266, + ARRAY_SIZE(dbsc5_table_patch_slice_4266)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4266, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4266)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4266, + ARRAY_SIZE(dbsc5_table_patch_pi_4266)); + } else if (priv->ddr_mbps < (4801 * priv->ddr_mbpsdiv)) { + /* 4269-4800 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_4800, + ARRAY_SIZE(dbsc5_table_patch_slice_4800)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_4800, + ARRAY_SIZE(dbsc5_table_patch_adr_v_4800)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_4800, + ARRAY_SIZE(dbsc5_table_patch_pi_4800)); + } else if (priv->ddr_mbps < (5501 * priv->ddr_mbpsdiv)) { + /* 4801 - 5500 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_5500, + ARRAY_SIZE(dbsc5_table_patch_slice_5500)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_5500, + ARRAY_SIZE(dbsc5_table_patch_adr_v_5500)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_5500, + ARRAY_SIZE(dbsc5_table_patch_pi_5500)); + } else if (priv->ddr_mbps < (6001 * priv->ddr_mbpsdiv)) { + /* 5501 - 6000 */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_6000, + ARRAY_SIZE(dbsc5_table_patch_slice_6000)); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + dbsc5_table_patch_adr_v_6000, + ARRAY_SIZE(dbsc5_table_patch_adr_v_6000)); + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_6000, + ARRAY_SIZE(dbsc5_table_patch_pi_6000)); + } + + for (cs = 0; cs < CS_CNT; cs++) { + struct dbsc5_table_patch dbsc5_table_patch_pi_mr12[] = { + { PI_DARRAY3_0_CSx_Fx[cs][2], js1[priv->js1_ind].MR1 }, + { PI_DARRAY3_1_CSx_Fx[cs][2], js1[priv->js1_ind].MR2 }, + }; + + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_mr12, + ARRAY_SIZE(dbsc5_table_patch_pi_mr12)); + } + + /* Read Vref (SoC side) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_r) { + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + dbsc5_table_patch_slice_vref_r, + ARRAY_SIZE(dbsc5_table_patch_slice_vref_r)); + } + + /* Write Vref (MR14, MR15) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_w) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_w, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_w)); + } + + /* CA Vref (MR12) Training range */ + if (priv->dbsc5_board_config->bdcfg_vref_ca) { + dbsc5_table_patch_set(priv->DDR_PI_REGSET, true, + dbsc5_table_patch_pi_vref_ca, + ARRAY_SIZE(dbsc5_table_patch_pi_vref_ca)); + } + + /* Low Freq setting */ + if (priv->ddr_mbps < (8 * 640 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_V_REGSET, false, + &dbsc5_table_patch_adr_v_mbpsdiv_640, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_640, 1); + } + + if (priv->ddr_mbps < (8 * 572 * priv->ddr_mbpsdiv)) { + /* CAL_CLK(10-20MHz) */ + dbsc5_table_patch_set(priv->DDR_PHY_SLICE_REGSET, false, + &dbsc5_table_patch_slice_mbpsdiv_572, 1); + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + &dbsc5_table_patch_adr_g_mbpsdiv_572, 1); + } + + if (priv->ddr_mbps < (8 * 401 * priv->ddr_mbpsdiv)) { + dbsc5_table_patch_set(priv->DDR_PHY_ADR_G_REGSET, false, + dbsc5_table_patch_adr_g_mbpsdiv_400, + ARRAY_SIZE(dbsc5_table_patch_adr_g_mbpsdiv_400)); + } + + /* SET DATA SLICE TABLE */ + for (slice = 0; slice < SLICE_CNT; slice++) { + adr = DDR_PHY_SLICE_REGSET_OFS_V4H + (DDR_PHY_SLICE_REGSET_SIZE_V4H * slice); + for (i = 0; i < DDR_PHY_SLICE_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, adr + i, priv->DDR_PHY_SLICE_REGSET[i]); + } + + /* SET ADR SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_V_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_V_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_V_REGSET[i]); + + /* SET ADRCTRL SLICE TABLE */ + for (i = 0; i < DDR_PHY_ADR_G_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PHY_ADR_G_REGSET_OFS_V4H + i, priv->DDR_PHY_ADR_G_REGSET[i]); + + /* SET PI REGISTERS */ + for (i = 0; i < DDR_PI_REGSET_NUM_V4H; i++) + dbsc5_reg_ddrphy_write_all(dev, DDR_PI_REGSET_OFS_V4H + i, priv->DDR_PI_REGSET[i]); +} + +/** + * dbsc5_ddr_config() - Configure DDR registers + * @dev: DBSC5 device + * + * Set up wiring for DQ and DM pins and VREF_DRIVING. Set the CA pin wiring + * and ADR_CALVL_SWIZZLE settings. Make wiring settings for the CS pin. When + * memory rank is 1, set RANK setting to 1 to disable CS training. Configure + * the DATA_BYTE_SWAP setting. + */ +static void dbsc5_ddr_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ca_swap, cs_swap, dqs_swap; + u32 ch, slice; + + r_foreach_vch(dev, ch) { + /* Board settings (DQ, DM, VREF_DRIVING) */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE0, + priv->dbsc5_board_config->ch[ch].bdcfg_dq_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DQ_DM_SWIZZLE1, + priv->dbsc5_board_config->ch[ch].bdcfg_dm_swap[slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_CALVL_VREF_DRIVING_SLICE, + !((dqs_swap >> (4 * slice)) & 1)); + } + dbsc5_ddr_setval(dev, ch, PHY_DATA_BYTE_ORDER_SEL, + priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap | 0x76543200); + + /* Board settings (CA, ADDR_MUX) */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + + /* ADDR_MUX */ + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_0, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_1, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_2, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_3, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_4, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_5, ca_swap & 0xf); + ca_swap >>= 4; + dbsc5_ddr_setval(dev, ch, PI_ADDR_MUX_6, ca_swap & 0xf); + ca_swap >>= 4; + + /* ADR_CALVL_SWIZZLE */ + ca_swap = priv->dbsc5_board_config->ch[ch].bdcfg_ca_swap; + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_SWIZZLE0, ca_swap & 0x0fffffff); + + /* Board settings (CS) */ + /* CKE_MUX */ + /* SoC CKE -> DRAM CS */ + cs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_cs_swap; + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_0, (cs_swap & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PI_CKE_MUX_1, ((cs_swap >> 4) & 0xf) + 2); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT2_2, (cs_swap & 0xf) + 1); + dbsc5_ddr_setval(dev, ch, PHY_CS_ACS_ALLOCATION_BIT3_2, ((cs_swap >> 4) & 0xf) + 1); + + /* Mask CS_MAP if RANK1 is not found */ + if (!(priv->ch_have_this_cs[1] & BIT(ch))) { + dbsc5_ddr_setval(dev, ch, PHY_ADR_CALVL_RANK_CTRL, 0x0); + for (slice = 0; slice < SLICE_CNT; slice++) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_PER_CS_TRAINING_EN, 0x0); + } + } + + r_foreach_vch(dev, ch) { + /* DATA_BYTE_SWAP */ + dqs_swap = priv->dbsc5_board_config->ch[ch].bdcfg_dqs_swap; + + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_EN, 0x1); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE0, dqs_swap & 0xf); + dbsc5_ddr_setval(dev, ch, PI_DATA_BYTE_SWAP_SLICE1, (dqs_swap >> 4) & 0xf); + + if (!(priv->ch_have_this_cs[1] & BIT(ch))) + dbsc5_ddr_setval(dev, ch, PI_CS_MAP, 0x1); + } +} + +/** + * dbsc5_dbsc_regset_pre() - Configure primary DDR registers + * @dev: DBSC5 device + * + * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. + * Write SDRAM configuration contents to registers. + */ +static void dbsc5_dbsc_regset_pre(struct udevice *dev) +{ +#define DBMEMCONF_REG(d3, row, bg, bank, col, dw) \ + (((d3) << 30) | ((row) << 24) | ((bg) << 20) | ((bank) << 16) | ((col) << 8) | (dw)) +#define DBMEMCONF_REGD(density) /* 16bit */ \ + DBMEMCONF_REG(((density) % 2), ((((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1)), 2, 2, 10, 1) + + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 density; + u32 ch, cs; + + /* Primary settings */ + /* LPDDR5, BL=16, DFI interface */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBMEMKIND, 0xC); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBMEMKINDA, 0xC); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBBL, 0x2); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBLA, 0x2); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBPHYCONF0, 0x1); + + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF0, 0x1); + + /* FREQRATIO=2 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF1, 0x20000); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF1A, 0x0); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCONF2, 0x1); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCONF2A, 0x241); + + r_foreach_ech(ch) { + for (cs = 0; cs < CS_CNT; cs++) { + if (priv->ddr_density[ch][cs] == 0xFF) { + writel(0x00, regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(0x00, regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } else { + density = priv->ddr_density[ch][cs]; + writel(DBMEMCONF_REGD(density), + regs_dbsc_d + DBSC_DBMEMCONF(ch, cs)); + writel(DBMEMCONF_REGD(density), + regs_dbsc_a + DBSC_DBMEMCONFA(ch, cs)); + } + } + } +} + +/** + * dbsc5_dbsc_regset() - Set DBSC timing parameters + * @dev: DBSC5 device + * + * Set the timing registers of the DBSC. + * Configure Scheduler settings. + */ +static void dbsc5_dbsc_regset(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 tmp[4]; + + /* DBTR0.CL : RL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(0), priv->RL); + + /* DBTR1.CWL : WL */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(1), priv->WL); + + /* DBTR2.AL = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(2), 0x0); + + /* DBTR3.TRCD: tRCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(3), priv->js2[JS2_tRCD]); + + /* DBTR4.TRPA,TRP: tRPab,tRPpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(4), (priv->js2[JS2_tRPab] << 16) | + priv->js2[JS2_tRPpb]); + + /* DBTR5.TRC : tRCpb */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(5), priv->js2[JS2_tRCpb]); + + /* DBTR6.TRAS : tRAS */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(6), priv->js2[JS2_tRAS]); + + /* DBTR7.TRRD : tRRD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(7), ((priv->js2[JS2_tRRD] - 1) << 16) | + (priv->js2[JS2_tRRD] - 1)); + + /* DBTR8.TFAW : tFAW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(8), priv->js2[JS2_tFAW] - 1); + + /* DBTR9.TRDPR: nRBTP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); + + /* DBTR10.TWR : nWR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(10), js1[priv->js1_ind].nWR); + + /* + * DBTR11.TRDWR : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + + * RD(tRPST/tCK) - ODTLon - RD(tODTon(min)/tCK) + 1 + feature + */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(11), + priv->RL + 4 + priv->js2[JS2_tWCK2DQO_HF] - + js1[priv->js1_ind].ODTLon - priv->js2[JS2_tODTon_min] + 2); + + /* DBTR12.TWRRD_S : WL + BL/2 + tWTR_S, TWRRD_L : WL + BL + tWTR_L */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(12), + ((priv->WL + 2 + priv->js2[JS2_tWTR_S]) << 16) | + (priv->WL + 4 + priv->js2[JS2_tWTR_L])); + + /* DBTR13.TRFCAB : tRFCab */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(13), priv->js2[JS2_tRFCab]); + + /* DBTR14.TCSCAL,TCKEHDLL,tCKEH : tCSCAL,tXP,tXP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(14), (priv->js2[JS2_tCSCAL] << 24) | + (priv->js2[JS2_tXP] << 16) | + priv->js2[JS2_tXP]); + + /* DBTR15.TESPD,TCKESR,TCKEL : tESPD = 2,tSR,tSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(15), (0x02 << 24) | + (priv->js2[JS2_tSR] << 16) | + priv->js2[JS2_tSR]); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (priv->WL * 4) - 1 + 5; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (priv->WL * 4) - 2 - 2 + 5; + /* dql(tphy_rdlat + trddata_en) RL * 4 + phy_rptr_update + phy_rddqs_latency_adjust + 39 */ + tmp[2] = (priv->RL * 4) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RPTR_UPDATE, false) + + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDQS_LATENCY_ADJUST, false) + + 39; + /* dqienltncy(trddata_en) RL * 4 - phy_rddata_en_dly_X + 4 * phy_wck_freq_ratio_X */ + tmp[3] = (priv->RL * 4) + 4 - + dbsc5_ddrtbl_getval(priv->DDR_PHY_SLICE_REGSET, PHY_RDDATA_EN_DLY, false); + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(16), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR17.TMODRD,TMOD: tMRR,tMRW */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(17), (priv->js2[JS2_tMRR] << 24) | + (priv->js2[JS2_tMRW] << 16)); + + /* DBTR18. RODTL, RODTA = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(18), 0x0); + + /* DBTR19. TZQCL, TZQCS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(19), 0x0); + + /* DBTR20.TXSDLL, TXS : tXSR,tXSR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(20), ((priv->js2[JS2_tXSR]) << 16) | + priv->js2[JS2_tXSR]); + + /* DBTR21.TCCD */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(21), (priv->ddr_tccd << 16) | + (priv->ddr_tccd * 2)); + + /* DBTR22.TZQCAL,TZQLAT : tZQCAL,tZQLAT */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(22), (priv->js2[JS2_tZQCALns] << 16) | priv->js2[JS2_tZQLAT]); + + /* DBTR23. RRSPC = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(23), 0x0); + + /* DBTR24 */ + /* WRCSLAT(tphy_wrcslat) */ + tmp[0] = (priv->WL * 4) - 2; + /* WRCSGAP(tphy_wrcsgap) */ + tmp[1] = 0x0C; + /* RDCSLAT(tphy_rdcslat) */ + tmp[2] = priv->RL * 4; + /* RDCSGAP(tphy_rdcsgap) */ + tmp[3] = 0x0C; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR25. TWDQLVLDIS = 0 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(25), 0x0); + + /* DBTR26. TWCK2DQOOSC,TDQSOSC : WCK2DQI interval timer run time, WCK2DQO interval timer run time */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(26), 0x0); + + /* DBTR27.TPDN : tPDN */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(27), priv->js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(28), priv->js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(29), priv->js2[JS2_tXDSM_XP]); + + /* DBTR30.TCMDPD : tCMDPD = 3 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(30), 0x3); + + /* DBTR31.TWCK2DQOMAX,TWCK2DQIMAX : tWCK2DQI/O_HF/LF */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(31), (priv->js2[JS2_tWCK2DQO_HF] << 4) | + priv->js2[JS2_tWCK2DQI_HF]); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (js1[priv->js1_ind].WCKENLR * 4) + 4 - 1; + /* twckenw */ + tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) + 4 - 1; + /* twckenlf */ + tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) + 4; + /* twckpresta */ + tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR33 */ + /* TWCKTGL */ + tmp[0] = 4; + /* TWCKDIS (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK) : tWCKPST = 2.5(MR10[3:2]) */ + tmp[1] = ((priv->RL + 4) * 4) + 3; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); + + /* DBTR34 */ + /* TWCKSUS = 4 */ + tmp[0] = 4; + /* TWCKPST RU(tWCKPST/tCK) : tWCKPST=2.5(MR10[3:2]) */ + tmp[1] = 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); + + /* DBTR35 */ + /* TRD2WCKOFF RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = priv->RL + 4 + 0 + 1; + /* TWR2WCKOFF WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = priv->WL + 4 + 0 + 1; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); + + /* DBTR36 */ + /* TWSSUSWRX : CAS(WCKSUS)WRX */ + tmp[0] = 3; + /* TWSOFFWRX : CAS(WS_OFF)WRX */ + tmp[1] = 3; + /* TWSFSWRX : CAS(WS_FS)WRX */ + tmp[2] = 2; + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR37 */ + /* tOSCO */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBTR(37), priv->js2[JS2_tOSCODQI]); + + /* DBRNK2 */ + /* RNKRR = 12 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(2), 0xCC); + + /* DBRNK3 */ + /* RNKRW = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(3), 0x66); + + /* DBRNK4 */ + /* RNKWR = 6 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(4), 0x66); + + /* DBRNK5 */ + /* RNKWW = 14 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRNK(5), 0xEE); + + /* Timing registers for Scheduler */ + /* SCFCTST0 */ + /* SCPREACT */ + tmp[0] = priv->js2[JS2_tRPpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTRDWR */ + tmp[1] = (priv->WL + 2 + 1 + js1[priv->js1_ind].nWR + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDACRT */ + tmp[2] = ((js1[priv->js1_ind].nRBTP + 2) + priv->js2[JS2_tRPpb]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCACTACT */ + tmp[3] = priv->js2[JS2_tRCpb] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* SCASYNCOFS */ + tmp[0] = 12; + /* SCACTRDWR */ + tmp[1] = priv->js2[JS2_tRCD] * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCWRRD */ + tmp[2] = (readl(regs_dbsc_d + DBSC_DBTR(12)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + /* SCRDWR */ + tmp[3] = (readl(regs_dbsc_d + DBSC_DBTR(11)) & 0xFF) * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHFCTST1, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* SCTRFCAB */ + tmp[0] = (priv->js2[JS2_tRFCab] + priv->js2[JS2_tZQLAT]) * + priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHRW1, tmp[0]); + + /* DBSCHTR0 */ + /* SCDT0 */ + tmp[0] = (4 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT1 */ + tmp[1] = (8 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT2 */ + tmp[2] = (12 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + /* SCDT3 */ + tmp[3] = (16 * priv->bus_clk * priv->ddr_mbpsdiv * 8UL / + priv->ddr_mbps / priv->bus_clkdiv) - 1; + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* QOS and CAM */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBBCAMDIS, 0x1); +} + +/** + * dbsc5_dbsc_regset_post() - Set DBSC registers + * @dev: DBSC5 device + * + * If memory rank is 2, CS_TRAINING_EN is set to the other side. + * Configure DBI read/write settings. Execute DRAM refresh settings. + * Set WTmode of DFI PHY to OFF. Set up PHY Periodic Write DQ training. + * Set WTmode of DFI PHY to ON. Calibration settings for PHY PAD. + * Set SDRAM calibration. Make DFI Control Update Setting settings. + * In the case of WARM_BOOT, cancel the self-refresh setting. + * Enable SDRAM auto refresh. Set up PHY Periodic Write DQ training. + * Enable access to SDRAM. + */ +static void dbsc5_dbsc_regset_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + /* Average periodic refresh interval/Average Refresh Interval [ns] */ + const u32 dbsc_refint = 1920; + /* 0: Average interval is REFINT, 1: Average interval is 1/2 REFINT */ + const u32 dbsc_refints = 0; + /* Periodic-WriteDQ/ReadDQ Training Interval [us] */ + const u32 periodic_training_interval = 20000; + u32 phymster_req_interval; + u32 ch, slice; + u32 clk_count; + u32 refcycle; + u32 ctrl_clk; + u32 reg; + + if ((renesas_get_cpu_rev_integer() < 3) && priv->ch_have_this_cs[1]) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_PER_CS_TRAINING_EN, + 0x0); + } + } + } + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDBICNT, 0x3); + + /* set REFCYCLE */ + refcycle = dbsc_refint * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; + /* refpmax=8 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF1, (refcycle & 0xFFFF) | BIT(19)); + /* refpmin=1 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFCNF2, dbsc_refints | BIT(16)); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x0); + + /* Periodic-WriteDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_VREF_EN, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_WDQLVL_ENABLE, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_PERIODIC, 0x1); + + /* Periodic-ReadDQ Training setting */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDLVL_DLY_STEP, 0x4); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_PERIODIC, 0x1); + + /* DFI_PHYMSTR_ACK , WTmode = b'01 */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x11); + + /* periodic SoC zqcal enable */ + reg = dbsc5_ddrtbl_getval(priv->DDR_PHY_ADR_G_REGSET, PHY_CAL_MODE_0, false); + dbsc5_ddr_setval_all_ch(dev, PHY_CAL_MODE_0, reg | BIT(1)); + + /* Periodic dram zqcal enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBCALCNF, 0x1000010); + + /* Periodic phy ctrl update enable */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFICUPDCNF, 0x504C0001); + + /* Set Auto Refresh */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBRFEN, 0x1); + + /* Periodic-WriteDQ/ReadDQ Training Interval setting */ + phymster_req_interval = periodic_training_interval - 3000; + clk_count = 1024 - (dbsc5_ddrtbl_getval(priv->DDR_PI_REGSET, PI_LONG_COUNT_MASK, true) * 32); + ctrl_clk = priv->ddr_mbps / priv->ddr_mbpsdiv / 8; + reg = phymster_req_interval * ctrl_clk / clk_count; + + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_INTERVAL, reg); + + /* DRAM access enable */ + dbsc5_reg_write(regs_dbsc_a + DBSC_DBACEN, 0x1); +} + +/** + * dbsc5_pi_training() - Training by PI + * @dev: DBSC5 device + * + * Enable WCK signal training and read gate training. Start PI training. + * After DFI initialization for all channels is once turned off, turned + * on all chennels of it. Power down the DRAM device once and then release + * the power down mode. Perform training in low frequency mode and training + * in high frequency mode. Wait for the DFI training completion status + * bit to stand until the time limit. Turn off DFI initialization for all + * channels. Turn off WTMODE of DFI PHY. Check if CA/CS Training has failed. + * Check if Wrlvl training is in error. If an error can be confirmed from + * the check result, the result is returned as a return value. Clear the + * status register for PI training. + */ +static u32 dbsc5_pi_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + const int retry_max = 0x10000; + u32 ca_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + bool frqchg_req; + u32 ch, reg; + int retry; + int ret; + + /* Init start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_9, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_10, 0x0); + + /* PI_START */ + dbsc5_ddr_setval_all_ch(dev, PI_START, 0x1); + + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + r_foreach_vch(dev, ch) + writel(0x21, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* Dummy PDE */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD, + DBSC_DBCMD_CMD_CHANNEL_ALL, + DBSC_DBCMD_CMD_RANK_ALL, 0); + + /* PDX */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_PD, + DBSC_DBCMD_CMD_CHANNEL_ALL, + DBSC_DBCMD_CMD_RANK_ALL, 1); + + /* Wait init_complete */ + for (retry = 0; retry < retry_max; retry++) { + frqchg_req = false; + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + if (!((~phytrainingok & priv->ddr_phyvalid) & BIT(ch))) + continue; + + if (!(readl(regs_dbsc_d + DBSC_DBPDSTAT0(ch)) & BIT(0))) + continue; + + frqchg_req = true; + break; + } + + if (frqchg_req) { + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + break; + } else { + r_foreach_vch(dev, ch) { + if (readl(regs_dbsc_d + DBSC_DBDFISTAT(ch)) & BIT(0)) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + } + + /* + * dbdficnt0: + * dfi_dram_clk_disable=0 + * dfi_frequency = 0 + * freq_ratio = 10 (4:1) + * init_start =0 + */ + r_foreach_vch(dev, ch) + writel(0x20, regs_dbsc_d + DBSC_DBDFICNT(ch)); + + /* DFI_PHYMSTR_ACK */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBDFIPMSTRCNF, 0x1); + + /* Error check */ + r_foreach_vch(dev, ch) { + /* CA/CS Training Error Check */ + /* PI_CALVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(4); + /* Error on decrement/increment pass */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS1) & (0x3 << 30); + /* Start outside of initial search range */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_ADR_CALVL_OBS2) & (0x3 << 24); + /* CSlvl error */ + reg |= dbsc5_ddr_getval(dev, ch, PHY_CSLVL_OBS1) & (0xF << 28); + if (reg) { + ca_training_ng |= BIT(ch); + printf("%s pi_training_error:1\n", __func__); + } + + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s pi_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | ca_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_write_leveling_adjust() - Write Leveling Cycle Adjust + * @dev: DBSC5 device + * + * Get delay value from the result write leveling of slice 0 and 1. + * Calculate latency of dfi_wrdata_en / dfi_wrdata / dfi_wrdata_mask + * signals based on delay values. + */ +static void dbsc5_write_leveling_adjust(struct udevice *dev) +{ + u32 result_hard0, result_hard1; + u32 avg, avg_frac, avg_cycle; + u32 ch; + + r_foreach_vch(dev, ch) { + /* SLICE0 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 > result_hard1) + avg += 0x400; + avg /= 2; + + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + + /* SLICE1 */ + result_hard0 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD0_DELAY_OBS); + result_hard1 = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_HARD1_DELAY_OBS); + + avg = result_hard0 + result_hard1; + if (result_hard0 >= result_hard1) + avg += 0x400; + avg /= 2; + avg_frac = avg & 0xFF; + avg_cycle = (avg >> 8) & 0x3; + + if (avg_cycle == 0x3) { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x1); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, 0x0); + } else { + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_DEC, 0x0); + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_ADD, avg_cycle); + } + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_WRITE_PATH_LAT_FRAC, avg_frac); + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, SC_PHY_WCK_CALC, 0x1); +} + +/** + * dbsc5_wl_gt_training() - Re-run Write Leveling & Read Gate Training + * @dev: DBSC5 device + * + * Set CA leveling OFF, read gate leveling ON, write gate leveling ON, + * PI dram wck training ON. Perform PI_DFS configuration. Start PI + * frequency training in manual mode. Perform training in high-frequency + * mode. Check for Write leveling Error and Gate leveling Error. If an + * error is identified, the resulting value is inverted and returned. + * Clear the PI status register. + */ +static u32 dbsc5_wl_gt_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + + dbsc5_ddr_setval_all_ch(dev, PI_DFS_ENTRY_SEQ_0, 0x181F0000); + dbsc5_ddr_setval_all_ch(dev, PI_DFS_INITIALIZATION_SEQ_1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:1\n", __func__); + } + + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s wl_gt_training_error:2\n", __func__); + } + } + + complete_ng = (wr_training_ng | gt_training_ng); + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_pi_int_ack_0_assert() - Training handshake functions + * @dev: DBSC5 device + * @bit: Status bit to poll + * + * Wait for the status bit specified in the argument to become 1 until the + * time limit. After checking status bits on all channels, clear the target + * status bits and returns the result of the check as the return value. + */ +static u32 dbsc5_pi_int_ack_0_assert(struct udevice *dev, u32 bit) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 ch, phytrainingok = 0; + int retry; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(bit)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + r_foreach_vch(dev, ch) + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, BIT(bit)); + + return phytrainingok; +} + +/** + * dbsc5_write_dca() - Write DCA Training + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static void dbsc5_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_DATA_DC_CAL_START, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_DATA_DC_CAL_START) | + dbsc5_ddr_getval_slice(dev, ch, 1, PHY_DATA_DC_CAL_START); + if (!reg) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_phyvalid) + break; + } +} + +/** + * dbsc5_dramdca_training() - DRAM DCA Training and Calculations + * @dev: DBSC5 device + * + * Get DCA Training CS0 Flip-0 training results for RANK0. + * Get DCA Training CS1 Flip-0 training results for RANK0. + * Calculate DRAMDCA settings from training results and write + * them to registers. Set DRAM DCA in MR30. Ensure that the + * training has been successfully completed. Clear CA status + * to 0. + */ +static u32 dbsc5_dramdca_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 mr30_conv[16] = { + 0x8, 0x7, 0x6, 0x5, 0x4, 0x3, 0x2, 0x1, + 0x0, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF + }; + u32 dca_result_l_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_0[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_l_1[DRAM_CH_CNT][CS_CNT]; + u32 dca_result_u_1[DRAM_CH_CNT][CS_CNT]; + u32 ch, phytrainingok, reg; + u32 tempu, templ; + + /* Run DRAM DCA Training for Flip-0 */ + dbsc5_ddr_setval_all_ch(dev, PI_DCMLVL_CS_SW, rank); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-0 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_0[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_0[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_0[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Run DRAM DCA Training for Flip-1 */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x0); + + /* DRAMDCA go */ + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 28); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Result for DRAMDCA flip-1 */ + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS0_F2); + dca_result_u_1[ch][0] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][0] = mr30_conv[reg & 0xF]; + if (!(rank & 0x2)) + continue; + + reg = dbsc5_ddr_getval(dev, ch, PI_DARRAY3_20_CS1_F2); + dca_result_u_1[ch][1] = mr30_conv[reg >> 4]; + dca_result_l_1[ch][1] = mr30_conv[reg & 0xF]; + } + + /* Calculate and set DRAMDCA value */ + r_foreach_vch(dev, ch) { + /* CS0 */ + tempu = (dca_result_u_0[ch][0] + dca_result_u_1[ch][0]) / 2; + templ = (dca_result_l_0[ch][0] + dca_result_l_1[ch][0]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS0_F2, reg); + if (!(rank & 0x2)) + continue; + + /* CS1 */ + tempu = (dca_result_u_0[ch][1] + dca_result_u_1[ch][1]) / 2; + templ = (dca_result_l_0[ch][1] + dca_result_l_1[ch][1]) / 2; + reg = (mr30_conv[tempu] << 4) | mr30_conv[templ]; + dbsc5_ddr_setval(dev, ch, PI_DARRAY3_20_CS1_F2, reg); + } + + /* Set DRAMDCA value in MR30 */ + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_0, 0x1A11E14); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_1, 0x1F0000); + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, rank); + dbsc5_ddr_setval_all_ch(dev, PI_SW_SEQ_START, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 19); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + dbsc5_ddr_setval_all_ch(dev, PI_SEQ_DEC_SW_CS, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_FLIP_MASK, 0x2); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_2, 0x1101FC); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_3, 0x211A00); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_ACTIVE_SEQ_4, 0x51500); + + return phytrainingok; +} + +/** + * dbsc5_write_leveling() - Re-run Write Leveling + * @dev: DBSC5 device + * + * CALVL training is set to OFF, WRDCM training is set to OFF, and DRAMDCA + * training is set to OFF. Set the memory rank for the Write leveling target + * and start leveling. Wait until leveling is complete. + * + * Check for Write leveling errors. If an error is confirmed to have occurred, + * the result is returned as a return value. Clear the PI status bit. + */ +static u32 dbsc5_write_leveling(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 wr_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_CALVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRDCM_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_DRAMDCA_LVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(29)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error check */ + r_foreach_vch(dev, ch) { + /* Wrlvl Error Check */ + /* PI_WRLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(3); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_STATUS_OBS) & BIT(12); + /* SLICE0 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WRLVL_ERROR_OBS); + /* SLICE1 wrlvl error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WRLVL_ERROR_OBS); + if (reg) { + wr_training_ng |= BIT(ch); + printf("%s write_leveling_error:1\n", __func__); + } + } + + if (wr_training_ng) + return ~wr_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_manual_write_dca() - Manual Write DCA Training + * @dev: DBSC5 device + * + * Write DCA training according to memory rank. + */ +static void dbsc5_manual_write_dca(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x2 : 0x1; + u32 phy_slv_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT]; + u32 phy_slv_dly_avg[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_min[DRAM_CH_CNT][SLICE_CNT]; + u32 slv_dly_max[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_min[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_max[DRAM_CH_CNT][SLICE_CNT]; + u32 phy_dcc_code_mid; + const int retry_max = 0x10000; + const u8 ratio_min_div = 0xA; + const u8 ratio_max_div = 0x2; + const u8 ratio_min = 0x6; + const u8 ratio_max = 0x3; + u32 ch, cs, slice, tmp; + u32 complete = 0; + int i, retry; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_min[ch][slice] = 0x7F; + phy_dcc_code_max[ch][slice] = 0x0; + } + } + + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_slv_dly[ch][cs][slice] = + dbsc5_ddr_getval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY); + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (rank == 0x2) { + /* Calculate average between ranks */ + phy_slv_dly_avg[ch][slice] = (phy_slv_dly[ch][0][slice] + + phy_slv_dly[ch][1][slice]) / 2; + } else { + phy_slv_dly_avg[ch][slice] = phy_slv_dly[ch][0][slice]; + } + /* Determine the search range */ + slv_dly_min[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_min / ratio_min_div; + slv_dly_max[ch][slice] = (phy_slv_dly_avg[ch][slice] & 0x07F) * ratio_max / ratio_max_div; + if (slv_dly_max[ch][slice] > 0x7F) + slv_dly_max[ch][slice] = 0x7F; + } + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x1); + + for (i = 0; i <= 0x7F; i++) { + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (slv_dly_max[ch][slice] < (slv_dly_min[ch][slice] + i)) { + complete |= BIT(ch) << (8 * slice); + } else { + /* CS0/1 same setting, Need masked write */ + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + slv_dly_min[ch][slice] + i); + dbsc5_ddr_setval_slice(dev, ch, slice, SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + + if (complete == (priv->ddr_phyvalid | (priv->ddr_phyvalid << 8))) + break; + + /* Execute write dca */ + r_foreach_vch(dev, ch) + for (slice = 0; slice < SLICE_CNT; slice++) + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) + dbsc5_ddr_setval_slice(dev, ch, slice, PHY_DATA_DC_CAL_START, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if (!(((complete >> (8 * slice)) >> ch) & 0x1)) { + for (retry = 0; retry < retry_max; retry++) { + tmp = dbsc5_ddr_getval_slice(dev, ch, slice, + PHY_DATA_DC_CAL_START); + if (!tmp) + break; + } + } + } + } + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + if ((slv_dly_min[ch][slice] + i) > slv_dly_max[ch][slice]) + continue; + + tmp = (dbsc5_ddr_getval_slice(dev, ch, slice, PHY_DATA_DC_DQS_CLK_ADJUST)); + if ((tmp >> 6) == 0x1) + tmp = 0x0; + else if ((tmp >> 6) == 0x2) + tmp = 0x3F; + + if (tmp < phy_dcc_code_min[ch][slice]) + phy_dcc_code_min[ch][slice] = tmp; + + if (phy_dcc_code_max[ch][slice] < tmp) + phy_dcc_code_max[ch][slice] = tmp; + } + } + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + for (cs = 0; cs < rank; cs++) { + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_INDEX, cs); + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_CLK_WRDQS_SLAVE_DELAY, + phy_slv_dly[ch][cs][slice]); + dbsc5_ddr_setval_slice(dev, ch, slice, + SC_PHY_WCK_CALC, 0x1); + dbsc5_ddr_setval(dev, ch, SC_PHY_MANUAL_UPDATE, 0x1); + } + } + } + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_SLV_DLY_CTRL_GATE_DISABLE, 0x0); + + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x1); + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + phy_dcc_code_mid = (phy_dcc_code_min[ch][slice] + + phy_dcc_code_max[ch][slice]) / 2; + dbsc5_ddr_setval_slice(dev, ch, slice, + PHY_DATA_DC_DQS_CLK_ADJUST, + phy_dcc_code_mid); + } + } +} + +/** + * dbsc5_read_gate_training() - Re-run read gate training by PI + * @dev: DBSC5 device + * + * Write leveling set to OFF, read gate leveling set to ON. Set memory rank + * for leveling target, turn on read gate leveling. Wait for leveling to be + * completed until the time limit. Check for errors during gate leveling. + * + * If an error is confirmed to have occurred, the result is returned as a + * return value. Clear the PI status register. + */ +static u32 dbsc5_read_gate_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const int retry_max = 0x10000; + u32 gt_training_ng = 0; + u32 phytrainingok = 0; + u32 ch, reg; + int retry; + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x1); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_REQ, 0x1); + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(24)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Gtlvl Error Check */ + /* PI_RDLVL_GATE_ERROR_BIT */ + reg = (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(2)); + /* SLICE0 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + /* SLICE1 delay setup error */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_GTLVL_STATUS_OBS) & (0x3 << 7); + if (reg) { + gt_training_ng |= BIT(ch); + printf("%s read_gate_training_error\n", __func__); + } + } + + if (gt_training_ng) + return ~gt_training_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_vref_training() - Read Data Training with VREF Training + * @dev: DBSC5 device + * + * Set reading leveling to ON and Vref leveling of reading to OFF. + * Set Vref reading training to OFF. Get start value, end value and + * number of steps for Vref training. Determine the optimal VREFSEL + * value while increasing the Vref training setpoint by the starting + * value+step value. + */ +static u32 dbsc5_read_vref_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + u32 best_dvw_min_byte0, best_dvw_min_byte1; + u32 dvw_min_byte0_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte1_table[DRAM_CH_CNT][128]; + u32 dvw_min_byte0[DRAM_CH_CNT] = { 0 }; + u32 dvw_min_byte1[DRAM_CH_CNT] = { 0 }; + u32 best_lower_vref, best_upper_vref; + u32 best_vref_byte0, best_vref_byte1; + u32 vref_start, vref_stop, vref_step; + u32 best_vref_byte0_index = 0; + u32 best_vref_byte1_index = 0; + const int retry_max = 0x10000; + u32 win_byte0, win_byte1; + u32 phytrainingok = 0; + u32 vref_stop_index; + u32 temple, tempte; + u32 best_thrshld; + u32 vref_outlier; + u32 outlier_cnt; + u32 curr_rank; + int i, retry; + u32 obs_sel; + u32 ch, reg; + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F0, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F1, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_VREF_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_VREF_TRAINING_CTRL, 0x0); + + /* ch0 vref_point */ + vref_start = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_START_POINT); + vref_stop = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STOP_POINT); + vref_step = dbsc5_ddr_getval(dev, 0, PHY_VREF_INITIAL_STEPSIZE); + vref_stop_index = (vref_stop - vref_start) / vref_step; + + if (vref_stop_index > 0x80) + return 0; + + for (i = 0; i < vref_stop_index; i++) { + r_foreach_vch(dev, ch) { + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | (vref_start + (vref_step * i))); + } + + for (curr_rank = 0; curr_rank < rank; curr_rank++) { + /* All ch Read Training Start */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, BIT(curr_rank)); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + phytrainingok = 0; + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(25)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Read Training End */ + dbsc5_ddr_setval_all_ch(dev, PI_INT_ACK_0, BIT(25)); + + r_foreach_vch(dev, ch) { + /* minimum Data Valid Window for each VREF */ + dvw_min_byte0[ch] = 0xFFFFFFFF; + dvw_min_byte1[ch] = 0xFFFFFFFF; + for (obs_sel = 0x0; obs_sel < 0x19; obs_sel++) { + if (!((obs_sel < 0x11) || (obs_sel == 0x18))) + continue; + + dbsc5_ddr_setval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + dbsc5_ddr_setval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_OBS_SELECT, + obs_sel); + + temple = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 0, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte0 = tempte - temple; + else + win_byte0 = 0; + + temple = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS); + tempte = dbsc5_ddr_getval_slice(dev, ch, 1, + PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS); + if (tempte > temple) + win_byte1 = tempte - temple; + else + win_byte1 = 0; + + if (dvw_min_byte0[ch] > win_byte0) + dvw_min_byte0[ch] = win_byte0; + + if (dvw_min_byte1[ch] > win_byte1) + dvw_min_byte1[ch] = win_byte1; + } + } + } + + r_foreach_vch(dev, ch) { + dvw_min_byte0_table[ch][i] = dvw_min_byte0[ch]; + dvw_min_byte1_table[ch][i] = dvw_min_byte1[ch]; + } + } + + r_foreach_vch(dev, ch) { + /* Search best VREF byte0 */ + best_vref_byte0 = vref_start; + best_vref_byte0_index = 0; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][0]; + + for (i = 0; i < vref_stop_index; i++) { + if (best_dvw_min_byte0 >= dvw_min_byte0_table[ch][i]) + continue; + + best_vref_byte0 = vref_start + (vref_step * i); + best_vref_byte0_index = i; + best_dvw_min_byte0 = dvw_min_byte0_table[ch][i]; + } + + /* Search best_lower VREF byte0 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i >= 0; i--) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte0 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte0; + outlier_cnt = vref_outlier; + for (i = best_vref_byte0_index; i < vref_stop_index; i++) { + if (dvw_min_byte0_table[ch][i] <= 0) + break; + + if (dvw_min_byte0_table[ch][i] >= (best_dvw_min_byte0 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte0 */ + best_vref_byte0 = (best_lower_vref + best_upper_vref) / 2; + + /* Search best VREF byte1 */ + best_vref_byte1 = vref_start; + best_vref_byte1_index = 0; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][0]; + for (i = 0; i < vref_stop_index; i++) { + if (best_dvw_min_byte1 >= dvw_min_byte1_table[ch][i]) + continue; + + best_vref_byte1 = vref_start + (vref_step * i); + best_vref_byte1_index = i; + best_dvw_min_byte1 = dvw_min_byte1_table[ch][i]; + } + + /* Search best_lower VREF byte1 */ + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_DLY_STEP); + if (reg == 0) + reg = 1; + best_thrshld = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_BEST_THRSHLD) * reg; + + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_lower_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i >= 0; i--) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_lower_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + + if (i == 0) + break; + } + + /* Search best_upper VREF byte1 */ + vref_outlier = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_RDLVL_VREF_OUTLIER); + best_upper_vref = best_vref_byte1; + outlier_cnt = vref_outlier; + for (i = best_vref_byte1_index; i < vref_stop_index; i++) { + if (dvw_min_byte1_table[ch][i] <= 0) + break; + + if (dvw_min_byte1_table[ch][i] >= (best_dvw_min_byte1 - best_thrshld)) { + best_upper_vref = vref_start + (vref_step * i); + } else { + if (outlier_cnt > 0) + outlier_cnt--; + else + break; + } + } + + /* Calculate center of best vref range byte1 */ + best_vref_byte1 = (best_lower_vref + best_upper_vref) / 2; + + reg = dbsc5_ddr_getval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 0, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte0); + reg = dbsc5_ddr_getval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ); + reg &= 0xF << 10; + dbsc5_ddr_setval_slice(dev, ch, 1, PHY_PAD_VREF_CTRL_DQ, + reg | BIT(9) | best_vref_byte1); + } + + return phytrainingok; +} + +/** + * dbsc5_read_write_training() - Read Data & RDDQ Training with best VREF & Write DQ VREF Training + * @dev: DBSC5 device + * + * Set read DQS/RDQS slave delay setting to 0. Write leveling set to OFF, + * read gate leveling set to OFF. Turn on read and write leveling. Start + * frequency training. Training in high-frequency mode. Wait until training + * is complete. Check for errors in write dq leveling and read leveling. + + * If an error is confirmed to have occurred, return the inverted result + * value. Clear the PI status register. + */ +static u32 dbsc5_read_write_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const int retry_max = 0x10000; + u32 wdq_training_ng = 0; + u32 rd_training_ng = 0; + u32 phytrainingok = 0; + u32 complete_ng = 0; + int retry, ret; + u32 ch, reg; + + /* RDDQ_SLAVE_DELAY Set 0x0050 -> 0x0000 */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ0_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ1_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ2_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ3_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ4_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ5_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ6_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDQ7_SLAVE_DELAY, 0x0); + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_RDDM_SLAVE_DELAY, 0x0); + + dbsc5_ddr_setval_all_ch(dev, PI_WRLVL_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_GATE_EN_F2, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_EN_F2, 0x3); + dbsc5_ddr_setval_all_ch(dev, PI_WDQLVL_EN_F2, 0x3); + + dbsc5_ddr_setval_all_ch(dev, PI_TRAIN_ALL_FREQ_REQ, 0x1); + + /* Freq Change High to High*/ + ret = dbsc5_clk_pll3_freq(dev); + if (ret) + return ret; + + for (retry = 0; retry < retry_max; retry++) { + r_foreach_vch(dev, ch) + if (dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(0)) + phytrainingok |= BIT(ch); + + if (phytrainingok == priv->ddr_phyvalid) + break; + } + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_write_training_error:1\n", __func__); + } + + /* Wdqlvl Error Check */ + /* PI_WDQLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(5); + /* SLICE0 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 0, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + /* SLICE1 wdqlvl_fail_dqZ */ + reg |= dbsc5_ddr_getval_slice(dev, ch, 1, PHY_WDQLVL_STATUS_OBS) & (0x1FF << 18); + if (reg) { + wdq_training_ng |= BIT(ch); + printf("%s read_write_training_error:2\n", __func__); + } + } + + complete_ng = wdq_training_ng | rd_training_ng; + if (complete_ng) + return ~complete_ng; + + /* PI_INT_ACK assert */ + r_foreach_vch(dev, ch) { + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_0, 0xFFFFFFFF); + dbsc5_ddr_setval(dev, ch, PI_INT_ACK_1, 0x7); + } + + return phytrainingok; +} + +/** + * dbsc5_read_training() - Correct RDDQ Training result & Re-Run Read Data Training + * @dev: DBSC5 device + * + * Set the Read DQ correction value and its upper limit from the board + * settings. Check DDR memory ranks. Add the offset value to the current + * Read DQ value and write it to the register. Write the setting value + * to PI_RDLVL_TRAIN_SEQ_x. Start the Read training. PI_INT_ACK assert. + * Execute the Rdlvl Error Check. Confirm that training has been successfully + * completed. Return the result of the confirmation as the return value. + */ +static u32 dbsc5_read_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + const u32 rank = priv->ch_have_this_cs[1] ? 0x3 : 0x1; + const u32 rddq_delay_offset_ps = 0x19; + const u32 rddq_delay_max_ps = 0x67; + const u32 rddq_delay_addr[] = { + PHY_RDDQ0_SLAVE_DELAY, PHY_RDDQ1_SLAVE_DELAY, PHY_RDDQ2_SLAVE_DELAY, + PHY_RDDQ3_SLAVE_DELAY, PHY_RDDQ4_SLAVE_DELAY, PHY_RDDQ5_SLAVE_DELAY, + PHY_RDDQ6_SLAVE_DELAY, PHY_RDDQ7_SLAVE_DELAY, PHY_RDDM_SLAVE_DELAY + }; + const u32 rddq_delay_offset = rddq_delay_offset_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + const u32 rddq_delay_max = rddq_delay_max_ps * priv->ddr_mbps * 256 / + (priv->ddr_mbpsdiv * 2 * 1000000); + u32 rd_training_ng = 0; + u32 ch, reg, slice; + u32 phytrainingok; + int i; + + r_foreach_vch(dev, ch) { + for (slice = 0; slice < SLICE_CNT; slice++) { + for (i = 0; i < 9; i++) { + reg = dbsc5_ddr_getval_slice(dev, ch, slice, + rddq_delay_addr[i]) + + rddq_delay_offset; + if (reg > rddq_delay_max) + reg = rddq_delay_max; + dbsc5_ddr_setval_slice(dev, ch, slice, rddq_delay_addr[i], reg); + } + } + } + + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_1, 0x89080); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_2, 0x811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_3, 0x40811C0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_4, 0x2000000); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_TRAIN_SEQ_5, 0x0); + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_CS_SW, rank); + + /* Read training go */ + dbsc5_ddr_setval_all_ch(dev, PI_RDLVL_REQ, 0x1); + + /* PI_INT_ACK assert */ + phytrainingok = dbsc5_pi_int_ack_0_assert(dev, 25); + if (phytrainingok != priv->ddr_phyvalid) + return phytrainingok; + + /* Error Check */ + r_foreach_vch(dev, ch) { + /* Rdlvl Error Check */ + /* PI_RDLVL_ERROR_BIT */ + reg = dbsc5_ddr_getval(dev, ch, PI_INT_STATUS) & BIT(1); + if (reg) { + rd_training_ng |= BIT(ch); + printf("%s read_training_error\n", __func__); + } + } + + if (rd_training_ng) + return ~rd_training_ng; + + return phytrainingok; +} + +/** + * dbsc5_ddr_register_mr28_set() - DDR mode register MR28 set + * @dev: DBSC5 device + * + * Set the mode register 28 of the SDRAM. + * ZQ Mode: Command-Based ZQ Calibration + * ZQ interval: Background Cal Interval < 64ms + */ +static void dbsc5_ddr_register_mr28_set(struct udevice *dev) +{ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRW, + DBSC_DBCMD_CMD_CHANNEL_ALL, + DBSC_DBCMD_CMD_RANK_ALL, (28 << 8) | 0x24); +} + +/** + * dbsc5_ddr_register_mr27_mr57_read() - DDR mode register MR27/MR57 read + * @dev: DBSC5 device + * + * Set the mode register 27 and 57 of the SDRAM. + */ +static void dbsc5_ddr_register_mr27_mr57_read(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + if (!priv->dbsc5_board_config->bdcfg_rfm_chk) + return; + + /* MR27 rank0 */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, + DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 27 << 8); + /* MR57 rank0 */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, + DBSC_DBCMD_CMD_CHANNEL_ALL, 0, 57 << 8); + + if (!priv->ch_have_this_cs[1]) + return; + + /* MR27 rank1 */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, + DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 27 << 8); + /* MR57 rank1 */ + dbsc5_send_dbcmd2(dev, DBSC_DBCMD_CMD_OPCODE_MRR, + DBSC_DBCMD_CMD_CHANNEL_ALL, 1, 57 << 8); +} + +/** + * dbsc5_init_ddr() - Initialize DDR + * @dev: DBSC5 device + * + * Status monitor and perform reset and software reset for DDR. + * Disable DDRPHY software reset. Unprotect the DDRPHY register. + * Perform pre-setting of DBSC registers. Configure the ddrphy + * registers. Process ddr backup. Set DBSC registers. + * + * Initialize DFI and perform PI training. Setup DDR mode registers + * pre-traning. Adjust number of write leveling cycles. Perform PI + * training in manual mode. Perform DRAM DCA training. Perform write + * leveling. Execute phydca training. Execute read gate training. + * + * Perform Vref training on read gate. Read DQ Write DQ Execute. + * Frequency selection change (F1->F2). Disable the FREQ_SEL_MULTICAST & + * PER_CS_TRAINING_MULTICAST. Start setting DDR mode registers. Set DBSC + * registers after training is completed. Set write protection for PHY + * registers. + */ +static u32 dbsc5_init_ddr(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + u32 phytrainingok; + u32 ch, val; + int ret; + + /* PLL3 initialization setting */ + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + /* Reset Status Monitor set */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKSETR4, 0x600); + /* ddrphy soft reset assert */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRCR4, readl(priv->cpg_regs + CPG_SRCR4) | 0x600); + /* Wait reset FB */ + ret = readl_poll_timeout(priv->cpg_regs + CPG_FSRCHKRA4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_FSRCHKRA4 Wait reset FB timeout\n", __func__); + hang(); + } + /* Reset Status Monitor clear */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_FSRCHKCLRR4, 0x600); + + /* Initialize PLL3 setting */ + dbsc5_clk_pll3_control(dev, PLL3_HIGH_FREQUENCY_MODE_LOAD_REGISTER); + + /* DDRPHY soft reset negate */ + dbsc5_clk_cpg_write_32(dev, priv->cpg_regs + CPG_SRSTCLR4, 0x600); + ret = readl_poll_timeout(priv->cpg_regs + CPG_SRCR4, val, ((val & 0x600) == 0), 1000000); + if (ret < 0) { + printf("%s CPG_SRCR4 DDRPHY soft reset negate timeout\n", __func__); + hang(); + } + + /* Unlock PHY */ + /* Unlock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0xA55A, regs_dbsc_d + DBSC_DBPDLK(ch)); + + /* DBSC register pre-setting */ + dbsc5_dbsc_regset_pre(dev); + + /* Load DDRPHY registers */ + dbsc5_ddrtbl_calc(priv); + dbsc5_ddrtbl_load(dev); + + /* Configure ddrphy registers */ + dbsc5_ddr_config(dev); + + /* DDR backupmode end */ + + /* DBSC register set */ + dbsc5_dbsc_regset(dev); + + /* Frequency selection change (F1->F2) */ + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_INDEX, 0x1); + dbsc5_ddr_setval_all_ch(dev, PHY_FREQ_SEL_MULTICAST_EN, 0x0); + + /* dfi_init_start (start ddrphy) & execute pi_training */ + phytrainingok = dbsc5_pi_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:1\n", __func__); + return phytrainingok; + } + + /* Write leveling cycle adjust */ + dbsc5_write_leveling_adjust(dev); + + /* Execute write leveling & read gate training */ + phytrainingok = dbsc5_wl_gt_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:2\n", __func__); + return phytrainingok; + } + + /* Execute write dca training */ + dbsc5_write_dca(dev); + + /* Execute dram dca training */ + phytrainingok = dbsc5_dramdca_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:3\n", __func__); + return phytrainingok; + } + + /* Execute write leveling */ + phytrainingok = dbsc5_write_leveling(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:4\n", __func__); + return phytrainingok; + } + + /* Execute manual write dca training */ + dbsc5_manual_write_dca(dev); + + /* Execute read gate training */ + phytrainingok = dbsc5_read_gate_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:5\n", __func__); + return phytrainingok; + } + + /* Execute read vref training */ + phytrainingok = dbsc5_read_vref_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:6\n", __func__); + return phytrainingok; + } + + /* Execute read dq & write dq training with best vref */ + phytrainingok = dbsc5_read_write_training(dev); + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:7\n", __func__); + return phytrainingok; + } + + /* correct rddq training result & Execute read dq training */ + phytrainingok = dbsc5_read_training(dev); + + if (priv->ddr_phyvalid != phytrainingok) { + printf("%s init_ddr_error:8\n", __func__); + return phytrainingok; + } + + /* PER_CS_TRAINING_MULTICAST SET (disable) */ + dbsc5_ddr_setval_all_ch_all_slice(dev, PHY_PER_CS_TRAINING_MULTICAST_EN, 0x0); + + /* setup DDR mode registers */ + /* MRS */ + dbsc5_ddr_register_mr28_set(dev); + + /* MRR */ + dbsc5_ddr_register_mr27_mr57_read(dev); + + /* training complete, setup DBSC */ + dbsc5_dbsc_regset_post(dev); + + /* Lock PHY */ + /* Lock DDRPHY register */ + r_foreach_vch(dev, ch) + writel(0x0, regs_dbsc_d + DBSC_DBPDLK(ch)); + + return phytrainingok; +} + +/** + * dbsc5_get_board_data() - Obtain board specific DRAM configuration + * @dev: DBSC5 device + * @modemr0: MODEMR0 register content + * + * Return board specific DRAM configuration structure pointer. + */ +__weak const struct renesas_dbsc5_board_config * +dbsc5_get_board_data(struct udevice *dev, const u32 modemr0) +{ + return &renesas_v4h_dbsc5_board_config; +} + +/** + * renesas_dbsc5_dram_probe() - DDR Initialize entry + * @dev: DBSC5 device + * + * Remove write protection on DBSC register. Read DDR configuration + * information from driver data. Calculate board clock frequency and + * operating frequency from DDR configuration information. Call the + * main function of DDR initialization. Perform DBSC write protection + * after initialization is complete. + */ +static int renesas_dbsc5_dram_probe(struct udevice *dev) +{ +#define RST_MODEMR0 0x0 +#define RST_MODEMR1 0x4 +#define OTP_MONITOR17 0x1144 + struct renesas_dbsc5_data *data = (struct renesas_dbsc5_data *)dev_get_driver_data(dev); + ofnode cnode = ofnode_by_compatible(ofnode_null(), data->clock_node); + ofnode rnode = ofnode_by_compatible(ofnode_null(), data->reset_node); + ofnode onode = ofnode_by_compatible(ofnode_null(), data->otp_node); + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + void __iomem *regs_dbsc_a = priv->regs + DBSC5_DBSC_A_OFFSET; + void __iomem *regs_dbsc_d = priv->regs + DBSC5_DBSC_D_OFFSET; + phys_addr_t rregs = ofnode_get_addr(rnode); + const u32 modemr0 = readl(rregs + RST_MODEMR0); + const u32 modemr1 = readl(rregs + RST_MODEMR1); + phys_addr_t oregs = ofnode_get_addr(onode); + const u32 otpmon17 = readl(oregs + OTP_MONITOR17); + u32 breg, reg, md, sscg, product; + u32 ch, cs; + + /* Get board data */ + priv->dbsc5_board_config = dbsc5_get_board_data(dev, modemr0); + priv->ddr_phyvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); + priv->max_density = 0; + priv->cpg_regs = (void __iomem *)ofnode_get_addr(cnode); + + for (cs = 0; cs < CS_CNT; cs++) + priv->ch_have_this_cs[cs] = 0; + + r_foreach_ech(ch) + for (cs = 0; cs < CS_CNT; cs++) + priv->ddr_density[ch][cs] = 0xFF; + + r_foreach_vch(dev, ch) { + for (cs = 0; cs < CS_CNT; cs++) { + priv->ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + + if (priv->ddr_density[ch][cs] == 0xFF) + continue; + + if (priv->ddr_density[ch][cs] > priv->max_density) + priv->max_density = priv->ddr_density[ch][cs]; + + priv->ch_have_this_cs[cs] |= BIT(ch); + } + } + + /* Decode board clock frequency from MD[14:13] pins */ + priv->brd_clkdiv = 3; + + breg = (modemr0 >> 13) & 0x3; + if (breg == 0) { + priv->brd_clk = 50; /* 16.66 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 1) { + priv->brd_clk = 60; /* 20 MHz */ + priv->bus_clk = priv->brd_clk * 0x14; + priv->bus_clkdiv = priv->brd_clkdiv; + } else if (breg == 3) { + priv->brd_clk = 100; /* 33.33 MHz */ + priv->bus_clk = priv->brd_clk * 0x18; + priv->bus_clkdiv = priv->brd_clkdiv * 2; + } else { + printf("MD[14:13] setting 0x%x not supported!", breg); + hang(); + } + + priv->brd_clkdiva = !!(modemr0 & BIT(14)); /* MD14 */ + + /* Decode DDR operating frequency from MD[37:36,19,17] pins */ + md = ((modemr0 & BIT(19)) >> 18) | ((modemr0 & BIT(17)) >> 17); + product = otpmon17 & 0xff; + sscg = (modemr1 >> 4) & 0x03; + if (sscg == 2) { + printf("MD[37:36] setting 0x%x not supported!", sscg); + hang(); + } + + if (product == 0x2) { /* V4H-3 */ + priv->ddr_mbps = 4800; + priv->ddr_mbpsdiv = 1; + } else if (product == 0x1) { /* V4H-5 */ + if (md == 3) + priv->ddr_mbps = 4800; + else + priv->ddr_mbps = 5000; + priv->ddr_mbpsdiv = 1; + } else { /* V4H-7 */ + if (md == 0) { + if (sscg == 0) { + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + } else { + priv->ddr_mbps = 19000; + priv->ddr_mbpsdiv = 3; + } + } else if (md == 1) { + priv->ddr_mbps = 6000; + priv->ddr_mbpsdiv = 1; + } else if (md == 2) { + priv->ddr_mbps = 5500; + priv->ddr_mbpsdiv = 1; + } else if (md == 3) { + priv->ddr_mbps = 4800; + priv->ddr_mbpsdiv = 1; + } + } + + priv->ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, + priv->brd_clk, priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + priv->ddr_mul_low = CLK_DIV(6400, 2, priv->brd_clk, + priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + priv->ddr_mul_reg = priv->ddr_mul_low; + if (sscg != 0) + priv->ddr_mul_reg -= 2; + + priv->ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1)) / + (priv->ddr_mbpsdiv * priv->brd_clk * 2)) - (8 * (priv->ddr_mul / 2) * 2); + + /* Adjust tccd */ + priv->ddr_tccd = 2; + + /* Initialize DDR */ + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x1234); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x1234); + + reg = dbsc5_init_ddr(dev); + + dbsc5_reg_write(regs_dbsc_d + DBSC_DBSYSCNT0, 0x0); + dbsc5_reg_write(regs_dbsc_a + DBSC_DBSYSCNT0A, 0x0); + + return reg != priv->ddr_phyvalid; +} + +/** + * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data + * @dev: DBSC5 device + * + * Extract DBSC5 address from DT and store it in driver data. + */ +static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +/** + * renesas_dbsc5_dram_get_info() - Return RAM size + * @dev: DBSC5 device + * @info: Output RAM info + * + * Return size of the RAM managed by this RAM driver. + */ +static int renesas_dbsc5_dram_get_info(struct udevice *dev, + struct ram_info *info) +{ + info->base = 0x40000000; + info->size = 0; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_dram_ops = { + .get_info = renesas_dbsc5_dram_get_info, +}; + +U_BOOT_DRIVER(renesas_dbsc5_dram) = { + .name = "dbsc5_dram", + .id = UCLASS_RAM, + .of_to_plat = renesas_dbsc5_dram_of_to_plat, + .ops = &renesas_dbsc5_dram_ops, + .probe = renesas_dbsc5_dram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c new file mode 100644 index 00000000000..b6b4ed8a5c0 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include "r8a78000-dbsc5.h" + +static int renesas_dbsc5_probe(struct udevice *dev) +{ + struct udevice *ddev, *vdev, *edev; + int ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_dram", &ddev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "ram@b8940000", &vdev); + if (ret) + return ret; + + ret = uclass_get_device_by_name(UCLASS_RAM, "dbsc5_ecc", &edev); + if (ret) + return ret; + + return 0; +} + +int renesas_dbsc5_bind(struct udevice *dev) +{ + struct udevice *ramdev, *eccdev; + struct driver *ramdrv, *eccdrv; + int ret; + + ramdrv = lists_driver_lookup_name("dbsc5_dram"); + if (!ramdrv) + return -ENOENT; + + eccdrv = lists_driver_lookup_name("dbsc5_ecc"); + if (!eccdrv) + return -ENOENT; + + ret = device_bind_with_driver_data(dev, ramdrv, "dbsc5_dram", + dev_get_driver_data(dev), + dev_ofnode(dev), &ramdev); + if (ret) + return ret; + + ret = device_bind_with_driver_data(dev, eccdrv, "dbsc5_ecc", 0, + dev_ofnode(dev), &eccdev); + if (ret) + device_unbind(ramdev); + + return ret; +} + +static const struct udevice_id renesas_dbsc5_ids[] = { + { .compatible = "renesas,r8a78000-dbsc", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(renesas_dbsc5) = { + .name = "dbsc5", + .id = UCLASS_NOP, + .of_match = renesas_dbsc5_ids, + .bind = renesas_dbsc5_bind, + .probe = renesas_dbsc5_probe, +}; diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h new file mode 100644 index 00000000000..b8c9a6f81fa --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dbsc5.h @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ + +struct renesas_dbsc5_data { + const char *clock_node; + const char *reset_node; + const char *otp_node; +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DBSC5_H__ */ diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dram.c b/drivers/ram/renesas/dbsc5/r8a78000-dram.c new file mode 100644 index 00000000000..f1c12901d52 --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dram.c @@ -0,0 +1,2795 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "r8a78000-dbsc5.h" +#include "r8a78000-dram.h" + +#define DBSC5_PHYNUM_CNT 8 +#define DBSC5_DBSC_CNT 8 +#define DBSC5_PLL3_CNT 4 + +/* Minimum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_LO 5 +/* Maximum value table for JS1 configuration table that can be taken */ +#define JS1_USABLEC_SPEC_HI 14 +/* The number of JS1 setting table */ +#define JS1_FREQ_TBL_NUM 15 +/* Macro to set the value of MR1 */ +#define JS1_MR1(f) ((f) << 4) /* CK mode = 0B */ +/* Macro to set the value of MR2 */ +#define JS1_MR2(f) (((f) << 4) | (f)) + +#define JS2_tSR 0 /* Element for self refresh */ +#define JS2_tXP 1 /* Exit power-down mode to first valid command */ +#define JS2_tRCD 2 /* Active to read or write delay */ +#define JS2_tRPpb 3 /* Minimum Row Precharge Delay Time */ +#define JS2_tRPab 4 /* Minimum Row Precharge Delay Time */ +#define JS2_tRAS 5 /* ACTIVE-to-PRECHARGE command */ +#define JS2_tWTR_S 6 /* Internal WRITE-to-READ command delay */ +#define JS2_tWTR_L 7 /* Internal WRITE-to-READ command delay */ +#define JS2_tRRD 8 /* Active bank a to active bank b command */ +#define JS2_tPPD 9 /* Precharge Power Down */ +#define JS2_tFAW 10 /* Four bank ACT window */ +#define JS2_tMRR 11 /* Mode Register Read */ +#define JS2_tMRW 12 /* Mode Register Write */ +#define JS2_tMRD 13 /* LOAD MODE REGISTER command cycle time */ +#define JS2_tZQCALns 14 /* ZQ Calibration */ +#define JS2_tZQLAT 15 /* ZQ Latency */ +#define JS2_tODTon_min 16 /* Minimum time on die termination */ +#define JS2_tPDN_DSM 17 /* Recommended minimum time for Deep Sleep Mode duration */ +#define JS2_tXSR_DSM 18 /* Required time to be fully re-powered up from Deep Sleep Mode */ +#define JS2_tXDSM_XP 19 /* Delay from Deep Sleep Mode Exit to Power-Down Exit */ +#define JS2_tWCK2DQI_HF 20 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_HF 21 /* Setting value of WCK to DQ output offset */ +#define JS2_tWCK2DQI_LF 22 /* Setting value of DQ to WCK input offset */ +#define JS2_tWCK2DQO_LF 23 /* Setting value of WCK to DQ output offset */ +#define JS2_tOSCODQI 24 /* Delay time from Stop WCK2DQI Interval Oscillator command to Mode Register Readout */ +#define JS2_tOSCODQO 25 +#define JS2_tDQ72DQns 26 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode2 */ +#define JS2_tCAENTns 27 /* Reception time to change the value fof REF(CA) for Command Bus Training Mode1 */ +#define JS2_tCSCAL 28 /* Minimum CA Low Duration time */ +#define JS2_tWCKSTOP 29 +#define JS2_tpbR2act 30 +#define JS2_TBLCNT 31 /* The number of table */ + +#define JS2_tRCpb JS2_TBLCNT /* ACTIVATE-to-ACTIVATE command period with per bank precharge */ +#define JS2_tRCab (JS2_TBLCNT + 1) /* ACTIVATE-to-ACTIVATE command period with all bank precharge */ +#define JS2_tRFCab (JS2_TBLCNT + 2) /* Refresh Cycle Time with All Banks */ +#define JS2_tRBTP (JS2_TBLCNT + 3) /* READ Burst end to PRECHARGE command delay */ +#define JS2_tXSR (JS2_TBLCNT + 4) /* Exit Self Refresh to Valid commands */ +#define JS2_tPDN (JS2_TBLCNT + 5) +#define JS2_tWLWCKOFF (JS2_TBLCNT + 6) +#define JS2_tRFCpb (JS2_TBLCNT + 7) +#define JS2_tpbR2pbR (JS2_TBLCNT + 8) +#define JS2_tRFMab (JS2_TBLCNT + 9) +#define JS2_tRFMpb (JS2_TBLCNT + 10) +#define JS2_CNT (JS2_TBLCNT + 11) + +#define JS2_DERATE 0 +#define DBSC_REFINT 1920 +#define PERIODIC_TRAINING_INTERVAL 20000 + +#define DBMEMCONF_REG(d3, row, BG, bank, col, dw) \ + (((d3) << 30) | ((row) << 24) | ((BG) << 20) | \ + ((bank) << 16) | ((col) << 8) | (dw)) + +#define DBMEMCONF_REGD(density) \ + (DBMEMCONF_REG(((density) % 2), (((density) + 1) / 2) + (28 - 2 - 2 - 10 - 1), \ + 2, 2, 10, 1)) + +struct jedec_spec1 { + u32 fx3; + u32 RLset0; + u32 RLset1; + u32 RLset2; + u32 WLsetA; + u32 WLsetB; + u32 nWR; + u32 nRBTP; + u32 ODTLon; + u32 MR1; + u32 MR2; + u32 WCKENLR0; + u32 WCKENLR1; + u32 WCKENLW; + u32 WCKENLF; + u32 WCKPRESTA; + u32 WCKPRETGLR; + u32 tRRD; + u32 tFAW; +}; + +static const struct jedec_spec1 js1[JS1_FREQ_TBL_NUM] = { + /* fx3,RL0,RL1,RL2,WLA.WLB.nWR.nRBTP,ODTLon */ + { 800, 3, 3, 3, 2, 2, 3, 0, 1, JS1_MR1(0), JS1_MR2(0), 0, 0, 0, 0, 1, 3, 3750, 15000 }, /* 533.333Mbps */ + { 1600, 4, 4, 4, 2, 3, 5, 0, 1, JS1_MR1(1), JS1_MR2(1), 0, 0, 0, 0, 1, 4, 3750, 15000 }, /* 1066.666Mbps */ + { 2400, 5, 5, 6, 3, 4, 7, 0, 2, JS1_MR1(2), JS1_MR2(2), 1, 1, 1, 1, 1, 4, 3750, 15000 }, /* 1600.000Mbps */ + { 3200, 6, 7, 7, 4, 5, 10, 0, 2, JS1_MR1(3), JS1_MR2(3), 1, 2, 1, 1, 2, 4, 3750, 15000 }, /* 2133.333Mbps */ + { 4000, 8, 8, 9, 4, 7, 12, 1, 2, JS1_MR1(4), JS1_MR2(4), 2, 2, 1, 1, 2, 5, 3750, 15000 }, /* 2666.666Mbps */ + { 4800, 9, 10, 10, 5, 8, 14, 1, 3, JS1_MR1(5), JS1_MR2(5), 3, 4, 2, 1, 2, 5, 3750, 15000 }, /* 3200.000Mbps */ + { 5600, 10, 11, 12, 6, 9, 16, 2, 4, JS1_MR1(6), JS1_MR2(6), 3, 4, 2, 1, 3, 5, 3750, 15000 }, /* 3733.333Mbps */ + { 6400, 12, 13, 14, 6, 11, 19, 2, 3, JS1_MR1(7), JS1_MR2(7), 4, 5, 2, 1, 3, 6, 3750, 15000 }, /* 4266.666Mbps */ + { 7200, 13, 14, 15, 7, 12, 21, 3, 4, JS1_MR1(8), JS1_MR2(8), 5, 6, 3, 2, 3, 6, 3750, 15000 }, /* 4800.000Mbps */ + { 8250, 15, 16, 17, 8, 14, 24, 4, 5, JS1_MR1(9), JS1_MR2(9), 6, 7, 3, 2, 4, 6, 3750, 15000 }, /* 5500.000Mbps */ + { 9000, 16, 17, 19, 9, 15, 26, 4, 6, JS1_MR1(10), JS1_MR2(10), 6, 7, 4, 2, 4, 7, 3750, 15000 }, /* 6000.000Mbps */ + { 9600, 17, 18, 20, 9, 16, 28, 4, 6, JS1_MR1(11), JS1_MR2(11), 7, 8, 4, 2, 4, 7, 3750, 15000 }, /* 6400.000Mbps */ + { 11250, 20, 22, 24, 11, 19, 32, 6, 7, JS1_MR1(12), JS1_MR2(12), 7, 9, 5, 3, 5, 9, 3750, 15000 }, /* 7500.000Mbps */ + { 12800, 23, 25, 26, 12, 22, 37, 6, 8, JS1_MR1(13), JS1_MR2(13), 8, 10, 5, 3, 6, 10, 3750, 15000 }, /* 8533.333Mbps */ + { 14400, 25, 28, 29, 14, 24, 41, 7, 9, JS1_MR1(14), JS1_MR2(14), 8, 11, 6, 3, 7, 11, 3330, 13320 } /* 9600.000Mbps */ +}; + +struct jedec_spec2 { + u32 ps; + u32 cyc; +}; + +static const struct jedec_spec2 jedec_spec2[2][JS2_TBLCNT] = { + { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 18000, 2 }, /* tRCD */ + { 18000, 2 }, /* tRPpb */ + { 21000, 2 }, /* tRPab */ + { 42000, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 0, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 0, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 700, 0 }, /* tWCK2DQI_HF */ + { 1600, 0 }, /* tWCK2DQO_HF */ + { 900, 0 }, /* tWCK2DQI_LF */ + { 1900, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 40000, 8 }, /* tOSCODQO */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 }, /* tCSCAL */ + { 6000, 2 }, /* tWCKSTOP */ + { 7500, 0 }, /* tpbR2act */ + }, { + { 15000, 2 }, /* tSR */ + { 7000, 3 }, /* tXP */ + { 19875, 2 }, /* tRCD */ + { 19875, 2 }, /* tRPpb */ + { 22875, 2 }, /* tRPab */ + { 43875, 3 }, /* tRAS */ + { 6250, 4 }, /* tWTR_S */ + { 12000, 4 }, /* tWTR_L */ + { 0, 2 }, /* tRRD */ + { 0, 2 }, /* tPPD */ + { 0, 0 }, /* tFAW */ + { 0, 4 }, /* tMRR */ + { 10000, 5 }, /* tMRW */ + { 14000, 5 }, /* tMRD */ + { 1500, 0 }, /* tZQCALns */ + { 30000, 4 }, /* tZQLAT */ + { 1500, 0 }, /* tODTon_min */ + { 4000, 0 }, /* tPDN_DSMus */ + { 200, 0 }, /* tXSR_DSMus */ + { 190, 0 }, /* tXDSM_XPus */ + { 715, 0 }, /* tWCK2DQI_HF */ + { 1635, 0 }, /* tWCK2DQO_HF */ + { 920, 0 }, /* tWCK2DQI_LF */ + { 1940, 0 }, /* tWCK2DQO_LF */ + { 40000, 8 }, /* tOSCODQI */ + { 40000, 8 }, /* tOSCODQO */ + { 125, 0 }, /* tDQ72DQns */ + { 250, 0 }, /* tCAENTns */ + { 1750, 0 }, /* tCSCAL */ + { 6000, 2 }, /* tWCKSTOP */ + { 7500, 0 }, /* tpbR2act */ + } +}; + +static const u32 jedec_spec2_tRFC_ab[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 130, 180, 180, 210, 210, 280, 280, 380, 380 +}; + +static const u32 jedec_spec2_tRFC_pb[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 60, 90, 90, 120, 120, 140, 140, 190, 190 +}; + +static const u32 jedec_spec2_tpbR2pbR[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 60, 90, 90, 90, 90, 90, 90, 90, 90 +}; + +static const u32 jedec_spec2_tRFM_ab[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 0, 0, 0, 0, 210, 280, 280, 380, 380 +}; + +static const u32 jedec_spec2_tRFM_pb[9] = { + /* 2Gb, 3Gb, 4Gb, 6Gb, 8Gb, 12Gb, 16Gb, 24Gb, 32Gb */ + 0, 0, 0, 0, 170, 190, 190, 260, 260 +}; + +/* System registers */ +#define SYSSS_TOP_BASE 0xc6480000 +#define SYSSS_ZB3CKCR0 (SYSSS_TOP_BASE + 0x10a0) +#define SYSSS_ZB3CKCR1 (SYSSS_TOP_BASE + 0x10a4) +#define SYSSS_ZB3CKCR_KICK BIT(31) +#define SYSSS_ZB3CKCR_PHYx(ch) ((0x7 * ((ch) & 0x1)) + (0x8 * ((ch) & 0x2))) +#define SYSSS_PLL1_1_CR0 (SYSSS_TOP_BASE + 0x1114) +#define SYSSS_PLL1_1DCR (SYSSS_TOP_BASE + 0x127c) +#define SYSSS_PLL3_x_CR0(ch) (SYSSS_TOP_BASE + 0x1180 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_CR1(ch) (SYSSS_TOP_BASE + 0x1184 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_CR2(ch) (SYSSS_TOP_BASE + 0x1188 + ((ch) * 0xc)) +#define SYSSS_PLL3_x_DCR(ch) (SYSSS_TOP_BASE + 0x12c4 + ((ch) * 0x8)) +#define SYSSS_PLL6_CR0 (SYSSS_TOP_BASE + 0x11c8) +#define SYSSS_PLL3_xSCR(ch) (SYSSS_TOP_BASE + 0x12c0 + ((ch) * 0x8)) +#define SYSSS_CLKTOPPKCPROT0 (SYSSS_TOP_BASE + 0x1370) +#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva))) + +/* MDLC registers */ +#define MODULE_CONTROL_DDRx_BASE(ch) (0xe8000000 + ((ch) * 0x80000)) +#define MODULE_CONTROL_DDRFI_BASE 0xc6480000 +#define MODULE_CONTROL_MDLC12PKCPROT1 (MODULE_CONTROL_DDRFI_BASE + 0xCF4) +#define MODULE_CONTROL_MDLC0xPKCPROT1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0xCF4) +#define MODULE_CONTROL_MDLC15MSRES8 (MODULE_CONTROL_DDRFI_BASE + 0x920) +#define MODULE_CONTROL_MDLC0xMSRES1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x904) +#define MODULE_CONTROL_MDLC0xMSRES3(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x90C) +#define MODULE_CONTROL_MDLC15MSRESS8 (MODULE_CONTROL_DDRFI_BASE + 0x980) +#define MODULE_CONTROL_MDLC0xMSRESS1(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x964) +#define MODULE_CONTROL_MDLC0xMSRESS3(ch) (MODULE_CONTROL_DDRx_BASE(ch) + 0x96C) +#define MODULE_STANDBY 0 +#define MODULE_RUN 3 + +/* DBSC5 registers */ +#define DBSC_A_BASE 0xE9800000 +#define DBSC_D_BASE 0xE9900000 + +#define DBSC_DBSYSCONF0 (DBSC_A_BASE + 0x0) +#define DBSC_DBSYSCONF1 (DBSC_D_BASE + 0x0) +#define DBSC_DBSYSCONF1A (DBSC_A_BASE + 0x4) +#define DBSC_DBSYSCONF2 (DBSC_D_BASE + 0x4) +#define DBSC_DBPHYCONF0 (DBSC_D_BASE + 0x8) +#define DBSC_DBSYSCONF2A (DBSC_A_BASE + 0x8) +#define DBSC_DBMEMKIND (DBSC_D_BASE + 0x20) +#define DBSC_DBMEMKINDA (DBSC_A_BASE + 0x20) +#define DBSC_DBMEMCONF(ch, cs) \ + (DBSC_D_BASE + 0x30 + (0x2000 * ((ch) & 0xE)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBMEMCONFA(ch, cs) \ + (DBSC_A_BASE + 0x30 + (0x4000 * ((ch) & 0xE)) + (0x10 * ((ch) & 0x1)) + (0x4 * (cs))) +#define DBSC_DBSYSCNT0 (DBSC_D_BASE + 0x100) +#define DBSC_DBSYSCNT0A (DBSC_A_BASE + 0x100) +#define DBSC_DBSYSCNT1A (DBSC_A_BASE + 0x104) +#define DBSC_DBACEN (DBSC_A_BASE + 0x200) +#define DBSC_DBRFEN (DBSC_D_BASE + 0x204) +#define DBSC_DBCMD (DBSC_D_BASE + 0x208) +#define DBSC_DBWAIT (DBSC_D_BASE + 0x210) +#define DBSC_DBTR(x) (DBSC_D_BASE + 0x300 + (0x4 * (x))) +#define DBSC_DBBL (DBSC_D_BASE + 0x400) +#define DBSC_DBBLA (DBSC_A_BASE + 0x400) +#define DBSC_DBRFCNF1 (DBSC_D_BASE + 0x414) +#define DBSC_DBRFCNF2 (DBSC_D_BASE + 0x418) +#define DBSC_DBCALCNF (DBSC_D_BASE + 0x424) +#define DBSC_DBSNOOPC (DBSC_D_BASE + 0x42C) +#define DBSC_DBRNK(x) (DBSC_D_BASE + 0x430 + (0x4 * (x))) +#define DBSC_DBDBICNT (DBSC_D_BASE + 0x518) +#define DBSC_DBDFIPMSTRCNF (DBSC_D_BASE + 0x520) +#define DBSC_DBDFICUPDCNF (DBSC_D_BASE + 0x540) +#define DBSC_DBDFISTAT(ch) \ + (DBSC_D_BASE + 0x600 + (0x2000 * ((ch) & 0xE)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBDFICNT(ch) \ + (DBSC_D_BASE + 0x604 + (0x2000 * ((ch) & 0xE)) + (0x40 * ((ch) & 0x1))) +#define DBSC_DBPDSTAT01(ch) (DBSC_D_BASE + 0x634 + (0x4000 * (ch))) +#define DBSC_DBBUS0CNF1 (DBSC_A_BASE + 0x804) +#define DBSC_DBBCAMDIS (DBSC_A_BASE + 0x9FC) +#define DBSC_DBSCHRW(x) (DBSC_A_BASE + 0x1020 + (0x4 * (x))) +#define DBSC_DBSCHTR0 (DBSC_A_BASE + 0x1030) +#define DBSC_DBSCHFCTST(x) (DBSC_A_BASE + 0x1040 + (0x4 * (x))) + +/* DDR PHY registers */ +#define DDR_PHY_BASE(ch) (0xA0000000 + (0x1000000 * (ch))) +#define DDR_PHY_DMA_TRANS_BASE(ch) (0xE0000000 + (0x1000000 * (ch))) + +#define PHY_HMAC_BASE(n) ((n) * 0x1000) +#define PHY_HMAC_TXSLEWAC(n) (PHY_HMAC_BASE(n) + 0x6d) +#define PHY_HMAC_TXIMPEDANCEAC(n) (PHY_HMAC_BASE(n) + 0x70) +#define PHY_HMAC_ODTIMPEDANCEAC(n) (PHY_HMAC_BASE(n) + 0x79) + +#define PHY_DBYTE_BASE(n) (0x10000 + ((n) * 0x1000)) +#define PHY_DBYTE_ENABLEWRITELINKECC(n) (PHY_DBYTE_BASE(n) + 0x01) +#define PHY_DBYTE_DQ0LNSEL(n) (PHY_DBYTE_BASE(n) + 0x80) +#define PHY_DBYTE_DQ1LNSEL(n) (PHY_DBYTE_BASE(n) + 0x81) +#define PHY_DBYTE_DQ2LNSEL(n) (PHY_DBYTE_BASE(n) + 0x82) +#define PHY_DBYTE_DQ3LNSEL(n) (PHY_DBYTE_BASE(n) + 0x83) +#define PHY_DBYTE_DQ4LNSEL(n) (PHY_DBYTE_BASE(n) + 0x84) +#define PHY_DBYTE_DQ5LNSEL(n) (PHY_DBYTE_BASE(n) + 0x85) +#define PHY_DBYTE_DQ6LNSEL(n) (PHY_DBYTE_BASE(n) + 0x86) +#define PHY_DBYTE_DQ7LNSEL(n) (PHY_DBYTE_BASE(n) + 0x87) +#define PHY_DBYTE_DQ8LNSEL(n) (PHY_DBYTE_BASE(n) + 0x88) +#define PHY_DBYTE_PPTCTLSTATIC(n) (PHY_DBYTE_BASE(n) + 0xa3) + +#define PHY_AC_BASE(n) (0x30000 + ((n) * 0x1000)) +#define PHY_AC_MAPCA0TODFI(n) (PHY_AC_BASE(n) + 0x90) +#define PHY_AC_MAPCA1TODFI(n) (PHY_AC_BASE(n) + 0x91) +#define PHY_AC_MAPCA2TODFI(n) (PHY_AC_BASE(n) + 0x92) +#define PHY_AC_MAPCA3TODFI(n) (PHY_AC_BASE(n) + 0x93) +#define PHY_AC_MAPCA4TODFI(n) (PHY_AC_BASE(n) + 0x94) +#define PHY_AC_MAPCA5TODFI(n) (PHY_AC_BASE(n) + 0x95) +#define PHY_AC_MAPCA6TODFI(n) (PHY_AC_BASE(n) + 0x96) +#define PHY_AC_ACLNDISABLE(n) (PHY_AC_BASE(n) + 0xac) +#define PHY_AC_DFICLKACLNDIS(n) (PHY_AC_BASE(n) + 0xad) +#define PHY_AC_PCLKACLNDIS(n) (PHY_AC_BASE(n) + 0xae) + +#define PHY_APB_BASE 0x58000 +#define PHY_APB_DRAMFREQ (PHY_APB_BASE + 0x01) +#define PHY_APB_DCAOPTS (PHY_APB_BASE + 0x02) +#define PHY_APB_SEQUENCECTRL (PHY_APB_BASE + 0x04) +#define PHY_APB_HDTCTRL (PHY_APB_BASE + 0x04) +#define PHY_APB_RXDFEOPT (PHY_APB_BASE + 0x07) +#define PHY_APB_CSPRESENTCHA (PHY_APB_BASE + 0x09) +#define PHY_APB_CSPRESENTCHB (PHY_APB_BASE + 0x10) +#define PHY_APB_MR1_A0 (PHY_APB_BASE + 0x16) +#define PHY_APB_MR1_A1 (PHY_APB_BASE + 0x16) +#define PHY_APB_MR1_B0 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR1_B1 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_A0 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_A1 (PHY_APB_BASE + 0x17) +#define PHY_APB_MR2_B0 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR2_B1 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_A0 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_A1 (PHY_APB_BASE + 0x18) +#define PHY_APB_MR3_B0 (PHY_APB_BASE + 0x19) +#define PHY_APB_MR3_B1 (PHY_APB_BASE + 0x19) +#define PHY_APB_MR11_A0 (PHY_APB_BASE + 0x1A) +#define PHY_APB_MR11_A1 (PHY_APB_BASE + 0x1A) +#define PHY_APB_MR11_B0 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR11_B1 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_A0 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_A1 (PHY_APB_BASE + 0x1B) +#define PHY_APB_MR12_B0 (PHY_APB_BASE + 0x1C) +#define PHY_APB_MR12_B1 (PHY_APB_BASE + 0x1C) +#define PHY_APB_MR22_A0 (PHY_APB_BASE + 0x25) +#define PHY_APB_MR22_A1 (PHY_APB_BASE + 0x25) +#define PHY_APB_MR22_B0 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR22_B1 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_A0 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_A1 (PHY_APB_BASE + 0x26) +#define PHY_APB_MR24_B0 (PHY_APB_BASE + 0x27) +#define PHY_APB_MR24_B1 (PHY_APB_BASE + 0x27) +#define PHY_APB_MR41_A0 (PHY_APB_BASE + 0x32) +#define PHY_APB_MR41_A1 (PHY_APB_BASE + 0x32) +#define PHY_APB_MR41_B0 (PHY_APB_BASE + 0x33) +#define PHY_APB_MR41_B1 (PHY_APB_BASE + 0x33) +#define PHY_APB_MR58_A0 (PHY_APB_BASE + 0x34) +#define PHY_APB_MR58_A1 (PHY_APB_BASE + 0x34) +#define PHY_APB_MR58_B0 (PHY_APB_BASE + 0x35) +#define PHY_APB_MR58_B1 (PHY_APB_BASE + 0x35) +#define PHY_APB_TXDFETRAINOPT (PHY_APB_BASE + 0x3E) +#define PHY_APB_UPPERLOWERBYTE (PHY_APB_BASE + 0x48) +#define PHY_APB_ALT_RL (PHY_APB_BASE + 0x48) +#define PHY_APB_MAIN_RL (PHY_APB_BASE + 0x49) +#define PHY_APB_RXVREFSTARTPAT (PHY_APB_BASE + 0x4E) +#define PHY_APB_RXVREFSTARTPRBS (PHY_APB_BASE + 0x4E) +#define PHY_APB_RXVREFENDPAT (PHY_APB_BASE + 0x4F) +#define PHY_APB_RXVREFENDPRBS (PHY_APB_BASE + 0x4F) +#define PHY_APB_RXVREFSTEPPAT (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFSTART (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFEND (PHY_APB_BASE + 0x50) +#define PHY_APB_TXVREFSTEP (PHY_APB_BASE + 0x51) +#define PHY_APB_RXVREFSTEPPRBS (PHY_APB_BASE + 0x51) +#define PHY_APB_RXDFEBITTIMECONTROL (PHY_APB_BASE + 0x59) + +#define PHY_HMMAS_BASE 0x60000 +#define PHY_HMMAS_CPLLCTRL1 (PHY_HMMAS_BASE + 0x05) +#define PHY_HMMAS_CPLLCTRL4 (PHY_HMMAS_BASE + 0x07) +#define PHY_HMMAS_CPLLCTRL5 (PHY_HMMAS_BASE + 0x08) +#define PHY_HMMAS_CPLLUPLLPROG0 (PHY_HMMAS_BASE + 0x0d) +#define PHY_HMMAS_CPLLUPLLPROG1 (PHY_HMMAS_BASE + 0x0e) +#define PHY_HMMAS_CPLLUPLLPROG2 (PHY_HMMAS_BASE + 0x0f) +#define PHY_HMMAS_CPLLUPLLPROG3 (PHY_HMMAS_BASE + 0x10) + +#define PHY_PPGC_BASE 0x70000 +#define PHY_PPGC_ACSMDONE (PHY_PPGC_BASE + 0x121) +#define PHY_PPGC_ACSMSTARTADDRXLATVAL0 (PHY_PPGC_BASE + 0x324) +#define PHY_PPGC_ACSMSTOPADDRXLATVAL0 (PHY_PPGC_BASE + 0x38b) +#define PHY_PPGC_HWTLPCSENA (PHY_PPGC_BASE + 0x072) +#define PHY_PPGC_HWTLPCSENB (PHY_PPGC_BASE + 0x073) +#define PHY_PPGC_HWTCONTROLVAL (PHY_PPGC_BASE + 0x07e) +#define PHY_PPGC_ACSMRPTCNTOVERRIDE (PHY_PPGC_BASE + 0x145) +#define PHY_PPGC_ACSMNOPADDR (PHY_PPGC_BASE + 0x18a) + +#define PHY_INITENG_BASE 0x90000 +#define PHY_INITENG_SEQ0BDISABLEFLAG0 (PHY_INITENG_BASE + 0x70c) +#define PHY_INITENG_SEQ0BGPR1 (PHY_INITENG_BASE + 0x801) +#define PHY_INITENG_SEQ0BDLY0 (PHY_INITENG_BASE + 0x8e0) +#define PHY_INITENG_SEQ0BGPR14 (PHY_INITENG_BASE + 0x80e) +#define PHY_INITENG_SEQ0BGPR15 (PHY_INITENG_BASE + 0x80f) + +#define PHY_DRTUB_BASE 0xc0000 +#define PHY_DRTUB_PIEINITVECSEL (PHY_DRTUB_BASE + 0x01) +#define PHY_DRTUB_UCCLKHCLKENABLES (PHY_DRTUB_BASE + 0x80) +#define PHY_DRTUB_STARTDCCMCLEAR (PHY_DRTUB_BASE + 0x88) + +#define PHY_APBONLY_BASE 0xd0000 +#define PHY_APBONLY_MICROCONTMUXSEL (PHY_APBONLY_BASE + 0x00) +#define PHY_APBONLY_UCTSHADOWREGS (PHY_APBONLY_BASE + 0x04) +#define PHY_APBONLY_DCTWRITEPROT (PHY_APBONLY_BASE + 0x31) +#define PHY_APBONLY_UCTWRITEONLYSHADOW (PHY_APBONLY_BASE + 0x32) +#define PHY_APBONLY_UCTDATWRITEONLYSHADOW (PHY_APBONLY_BASE + 0x34) +#define PHY_APBONLY_MICRORESET (PHY_APBONLY_BASE + 0x99) +#define PHY_APBONLY_SEQUENCEROVERRIDE (PHY_APBONLY_BASE + 0xe7) + +#define PHY_HMDBYTE_BASE(n) (0xe0000 + ((n) * 0x1000)) +#define PHY_HMDBYTE_VREGCTRL1DQ(n) (PHY_HMDBYTE_BASE(n) + 0x00) +#define PHY_HMDBYTE_TXDQSLEW(n) (PHY_HMDBYTE_BASE(n) + 0x1c) +#define PHY_HMDBYTE_TXIMPEDANCEDQ(n) (PHY_HMDBYTE_BASE(n) + 0x2c) +#define PHY_HMDBYTE_TXIMPEDANCEDQS(n) (PHY_HMDBYTE_BASE(n) + 0x2d) +#define PHY_HMDBYTE_ODTIMPEDANCEDQ(n) (PHY_HMDBYTE_BASE(n) + 0x2e) +#define PHY_HMDBYTE_ODTIMPEDANCEDQS(n) (PHY_HMDBYTE_BASE(n) + 0x2f) + +/* RENESAS X5H Board (64Gb 1rank x 4pcs) */ +static const struct renesas_dbsc5_board_config renesas_x5h_dbsc5_board_config = { + .bdcfg_phyvalid = 0xffff, + .bdcfg_tx_drv = 0x77777, + .bdcfg_tx_ffc = 0x30000000, + .bdcfg_rx_odt = 0x33333, + .bdcfg_rx_dfe = 0x0, + .bdcfg_tx_odt = 0x43, + .bdcfg_tx_ntodt = 0x3, + .bdcfg_tx_dfe = 0x0, + .bdcfg_rx_dca = 0x1, + .bdcfg_rx_drv = 0x6, + .bdcfg_rx_emphasis = 0x0, + .bdcfg_tx_dca = 0x1, + .bdcfg_ca_vref = 0x2e, + .bdcfg_rx_vref = 0xff001e, + .bdcfg_rx_vref_step = 0xf, + .bdcfg_tx_vref = 0x56e0a, + .bdcfg_rfm_chk = 0x1, + .ch = { + [0] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2641350, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x47583016, 0x85013247 }, + .bdcfg_dm_swap = { 0x2, 0x6 }, + }, + [1] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x3265410, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54263701, 0x84650312 }, + .bdcfg_dm_swap = { 0x8, 0x7 }, + }, + [2] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x1240635, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x56420713, 0x57802134 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [3] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5462301, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x74560128, 0x58760312 }, + .bdcfg_dm_swap = { 0x3, 0x4 }, + }, + [4] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4215306, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x45760138, 0x75803124 }, + .bdcfg_dm_swap = { 0x2, 0x6 }, + }, + [5] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4065321, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x65420371, 0x78560213 }, + .bdcfg_dm_swap = { 0x8, 0x4 }, + }, + [6] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4612035, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x25481730, 0x56703128 }, + .bdcfg_dm_swap = { 0x6, 0x4 }, + }, + [7] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5023416, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54783026, 0x41650238 }, + .bdcfg_dm_swap = { 0x1, 0x7 }, + }, + [8] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x521463, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x76453012, 0x85430127 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [9] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x5326041, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x43620781, 0x81653420 }, + .bdcfg_dm_swap = { 0x5, 0x7 }, + }, + [10] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2104635, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x54763210, 0x75831062 }, + .bdcfg_dm_swap = { 0x8, 0x4 }, + }, + [11] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x3654021, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x74561082, 0x56473012 }, + .bdcfg_dm_swap = { 0x3, 0x8 }, + }, + [12] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x514362, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x45761032, 0x74830126 }, + .bdcfg_dm_swap = { 0x8, 0x5 }, + }, + [13] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x4523016, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x54763021, 0x58470312 }, + .bdcfg_dm_swap = { 0x8, 0x6 }, + }, + [14] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x2315064, + .bdcfg_dqs_swap = 0x1, + .bdcfg_dq_swap = { 0x43620718, 0x68134207 }, + .bdcfg_dm_swap = { 0x5, 0x5 }, + }, + [15] = { + .bdcfg_ddr_density = { 0x6, 0xff }, + .bdcfg_ca_swap = 0x6315042, + .bdcfg_dqs_swap = 0x10, + .bdcfg_dq_swap = { 0x47653082, 0x64583012 }, + .bdcfg_dm_swap = { 0x1, 0x7 }, + } + } +}; + +struct renesas_dbsc5_dram_priv { + void __iomem *regs; + + /* The board parameter structure of the board */ + const struct renesas_dbsc5_board_config *dbsc5_board_config; + + /* The board clock frequency */ + u32 brd_clk; + u32 brd_clkdiv; + u32 brd_clkdiva; + /* The Mbps of DDR */ + u32 ddr_mbps; + u32 ddr_mbpsdiv; + /* Value indicating the enabled channel */ + u32 ddr_phyvalid; + u32 ddr_dramvalid; + /* Channels used for each memory rank */ + u32 ch_have_this_cs[CS_CNT]; + u32 upper_lower_byte[DBSC5_PHYNUM_CNT]; + u32 link_ecc_en; + /* The maximum memory capacity */ + u32 max_density; + /* Index of jedec spec1 setting table you use */ + u32 js1_ind; +}; + +/** + * vch_nxt() - Macro for channel selection loop + * @dev: DBSC5 device + * @pos: Iterator position + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 vch_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 posn; + + for (posn = pos; posn < DRAM_CH_CNT; posn++) + if (priv->ddr_dramvalid & BIT(posn)) + break; + + return posn; +} + +/** + * vphych_nxt() - Macro for PHY channel selection loop + * @dev: DBSC5 device + * @pos: Iterator position + * + * Return the ID of the channel to be used. Check for valid channels + * between the value of posn and the maximum number of CHs. If a valid + * channel is found, returns the value of that channel. + */ +static u32 vphych_nxt(struct udevice *dev, u32 pos) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 posn; + + for (posn = pos; posn < DBSC5_PHYNUM_CNT; posn++) + if (priv->ddr_phyvalid & BIT(posn)) + break; + + return posn; +} + +#define foreach_vch(dev, ch) \ + for ((ch) = vch_nxt((dev), 0); (ch) < DRAM_CH_CNT; (ch) = vch_nxt((dev), (ch) + 1)) + +#define foreach_vphych(dev, ch) \ + for ((ch) = vphych_nxt((dev), 0); (ch) < DBSC5_PHYNUM_CNT; (ch) = vphych_nxt((dev), (ch) + 1)) + +#define foreach_ech(ch) \ + for (ch = 0; ch < DRAM_CH_CNT; ch++) + +/** + * dbsc5_soft_delay() - Wait loop number of CPU cycles + * @loop: Number of cycles to wait + * + * This is a cycle counting approximate delay loop, used in very + * early code to wait for near future events. + */ +static void dbsc5_soft_delay(const int loop) +{ + int i; + + for (i = 0; i < loop; i++) + asm volatile("nop"); +} + +/** + * dbsc5_init_pll3() - Set PLL3 + * @dev: DBSC5 device + */ +static void dbsc5_init_pll3(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 data_cr0, data_cr1, data_div, data_dcr_1st, data_dcr_2nd, data_dcr_3rd; + u32 ddr_mul, ddr_mul_div, ddr_mul_ni, ddr_mul_nf; + const int pll3_frac_mode_threshold = 9000; + u32 ssmode, pll3vco, pll3_valid = 0; + u32 ddr_zb3ckcr[DBSC5_PHYNUM_CNT]; + u32 zb3ckcr0, zb3ckcr1; + u32 fvv, ch; + + /* Calculate valid PLL3 channel */ + for (ch = 0; ch < DBSC5_PHYNUM_CNT; ch++) { + pll3_valid |= (((priv->ddr_phyvalid >> (ch * 2)) | + (priv->ddr_phyvalid >> ((ch * 2) + 1))) & 0x1) << ch; + } + + /* Calculate PLL3 settings */ + if (priv->ddr_mbps < (pll3_frac_mode_threshold * priv->ddr_mbpsdiv)) + ssmode = 4; + else + ssmode = 0; + + ddr_mul = CLK_DIV(priv->ddr_mbps, priv->ddr_mbpsdiv * 2, priv->brd_clk, + priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + /* PLL3VCO = EXTAL * ddr_mul */ + pll3vco = ddr_mul * priv->brd_clk / (priv->brd_clkdiv * (priv->brd_clkdiva + 1)); + + if (pll3vco < 3000) { /* div = 4 */ + data_div = 2; + pll3vco = pll3vco * 2; + ddr_mul = ddr_mul * 2; + ddr_mul_div = 2; + } else { /* div = 2 */ + data_div = 0; + ddr_mul_div = 1; + } + + /* + * PLL3VCO FVV + * 3000 - 4000 0 + * 3750 - 4900 1 + * 4600 - 5800 2 + * 5450 - 6200 3 + */ + if (pll3vco > 5800) + fvv = 3; + else if (pll3vco > 4900) + fvv = 2; + else if (pll3vco > 4000) + fvv = 1; + else + fvv = 0; + + ddr_mul_ni = (ddr_mul / 2) - 1; + if (priv->ddr_mbps < (pll3_frac_mode_threshold * priv->ddr_mbpsdiv)) { + ddr_mul_nf = ((8 * priv->ddr_mbps * priv->brd_clkdiv * (priv->brd_clkdiva + 1) * ddr_mul_div) / + (priv->ddr_mbpsdiv * 2 * priv->brd_clk)) - (8 * (ddr_mul_ni + 1) * 2); + } else { + ddr_mul_nf = 0; + } + + data_cr0 = (ddr_mul_ni << 20) | (ssmode << 16); + data_cr1 = (fvv << 26) | ddr_mul_nf; + + /* Gradually frequency change settings */ + data_dcr_1st = 0x18; + data_dcr_2nd = 0x10; + data_dcr_3rd = 0; + + /* Disable write protection */ + writel(0xa5a5a501, SYSSS_CLKTOPPKCPROT0); + while (!((readl(SYSSS_CLKTOPPKCPROT0)) & BIT(0))) + ; + + /* Clock change & setting PLL3_x_CR0 and PLL3_x_CR1 */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* 1. Confirm that the PLL3_x are stable with PLLCLKSTAB */ + while (!(readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31))) + ; + + /* 2-1. Select PLL3_0SELID to CLK_IOSC1 */ + writel(0x1, SYSSS_PLL3_xSCR(ch)); + /* 2-2. Confirm PLL3_0SELACT register to ID equals CLK_IOSC1 */ + while (((readl(SYSSS_PLL3_xSCR(ch))) & 0x10001) != 0x10001) + ; + + /* 3. Stop the PLL3_x (PLLDISTRG = 1) */ + writel(0x20000000, SYSSS_PLL3_x_CR2(ch)); + /* 4. Confirm that the PLL3_0 has been stopped (PLLCLKSTAB = 0) */ + while (readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31)) + ; + + /* set PLL3_x_CR0 */ + clrsetbits_le32(SYSSS_PLL3_x_CR0(ch), 0x1ff70000, data_cr0); + /* set PLL3_x_CR1 */ + clrsetbits_le32(SYSSS_PLL3_x_CR1(ch), 0x0dffffff, data_cr1); + /* set PLL3_x_DCR */ + writel(data_dcr_1st, SYSSS_PLL3_x_DCR(ch)); + /* set PLL3_x_CR2 (PLLENTRG = 1) */ + writel(BIT(28), SYSSS_PLL3_x_CR2(ch)); + } + + /* Clock change */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* 1. Confirm that the PLL3_0 have been stable (PLLCLKSTAB = 1) */ + while (!(readl(SYSSS_PLL3_x_CR2(ch)) & BIT(31))) + ; + + /* 2-1. Select PLL input clock by PLLSELID register */ + writel(0, SYSSS_PLL3_xSCR(ch)); + /* 2-2. Confirm that PLL3_0SELACT register becomes same value with PLL3_0SELID */ + while (readl(SYSSS_PLL3_xSCR(ch)) & 0x10001) + ; + } + + /* Set PLL3_DCR gradually */ + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* Set PLL3_x_DCR */ + writel(data_dcr_2nd, SYSSS_PLL3_x_DCR(ch)); + /* Wait PLL3DIVSYNC is changed from 0 to 1 */ + while (!(readl(SYSSS_PLL3_x_DCR(ch)) & BIT(16))) + ; + } + + /* Wait until the current stabilizes */ + dbsc5_soft_delay(1000); + + for (ch = 0; ch < DBSC5_PLL3_CNT; ch++) { + if (!(pll3_valid & BIT(ch))) + continue; + + /* Set PLL3_x_DCR */ + writel(data_dcr_3rd, SYSSS_PLL3_x_DCR(ch)); + /* Wait PLL3DIVSYNC is changed from 0 to 1 */ + while (((readl(SYSSS_PLL3_x_DCR(ch))) & 0x10000) != 0x10000) + ; + } + + /* Wait until the current stabilizes */ + dbsc5_soft_delay(1000); + + /* Set PLL3 divider */ + zb3ckcr0 = readl(SYSSS_ZB3CKCR0); + zb3ckcr1 = readl(SYSSS_ZB3CKCR1); + for (ch = 0; ch < DBSC5_PHYNUM_CNT; ch++) { + if (priv->ddr_phyvalid & BIT(ch)) { + /* set FC[3:0] = data_div */ + ddr_zb3ckcr[ch] = data_div; + } else { + if (ch < 4) + ddr_zb3ckcr[ch] = (zb3ckcr0 >> SYSSS_ZB3CKCR_PHYx(ch)) & 0x1f; + else + ddr_zb3ckcr[ch] = (zb3ckcr1 >> SYSSS_ZB3CKCR_PHYx(ch)) & 0x1f; + } + } + + zb3ckcr0 = (ddr_zb3ckcr[3] << 23) | (ddr_zb3ckcr[2] << 16) | + (ddr_zb3ckcr[1] << 7) | ddr_zb3ckcr[0]; + zb3ckcr1 = (ddr_zb3ckcr[7] << 23) | (ddr_zb3ckcr[6] << 16) | + (ddr_zb3ckcr[5] << 7) | ddr_zb3ckcr[4]; + + /* Check ZB3CKCR0/1 KICK bit = 0 */ + while (readl(SYSSS_ZB3CKCR0) & SYSSS_ZB3CKCR_KICK) + ; + while (readl(SYSSS_ZB3CKCR1) & SYSSS_ZB3CKCR_KICK) + ; + + /* Set ZB3CKCR0/1 */ + writel(zb3ckcr0, SYSSS_ZB3CKCR0); + writel(zb3ckcr1, SYSSS_ZB3CKCR1); + + /* Set kickbit = 1 */ + setbits_le32(SYSSS_ZB3CKCR0, SYSSS_ZB3CKCR_KICK); + setbits_le32(SYSSS_ZB3CKCR1, SYSSS_ZB3CKCR_KICK); + + /* Wait ZB3CKCR0/1 KICK bit neg */ + while (readl(SYSSS_ZB3CKCR0) & SYSSS_ZB3CKCR_KICK) + ; + while (readl(SYSSS_ZB3CKCR1) & SYSSS_ZB3CKCR_KICK) + ; +} + +/** + * dbsc5_msres_sync_wait() - Wait for MSRES and MSRESS to synchronize + * @msres: MSRES register + * @msress: MSRESS register + */ +static void dbsc5_msres_sync_wait(u32 msres, u32 msress) +{ + while (readl(msres) != readl(msress)) + ; +} + +/** + * dbsc5_msres_status_set - Set DBSC5 into RUN or STANDBY mode + * @dev: DBSC5 device + * @status: RUN or STANDBY mode + */ +static void dbsc5_msres_status_set(struct udevice *dev, u32 status) +{ + u32 ch; + + foreach_vphych(dev, ch) { + /* + * Enable write access of protected registers + * dbq_reset / ddr_reset_apb / ddr_reset_hard / ddr_reset + */ + writel(0xa5a5a501, MODULE_CONTROL_MDLC0xPKCPROT1(ch)); + /* ddrfi */ + writel(0xa5a5a501, MODULE_CONTROL_MDLC12PKCPROT1); + + /* Check MDLCnMSRESS[i] = MDLCnMSRES[i] */ + /* dbq_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES1(ch), + MODULE_CONTROL_MDLC0xMSRESS1(ch)); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES3(ch), + MODULE_CONTROL_MDLC0xMSRESS3(ch)); + + /* ddrfi */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC15MSRES8, + MODULE_CONTROL_MDLC15MSRESS8); + + /* Set MDLCnMSRESx */ + /* dbq_reset */ + clrsetbits_le32(MODULE_CONTROL_MDLC0xMSRES1(ch), 0x3, status); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + clrsetbits_le32(MODULE_CONTROL_MDLC0xMSRES3(ch), 0x3f, + (status << 4) | (status << 2) | status); + + /* ddrfi */ + clrsetbits_le32(MODULE_CONTROL_MDLC15MSRES8, 0x3 << (ch * 2), + status << (ch * 2)); + + /* Check MDLCnMSRESS[i] = MDLCnMSRES[i] */ + /* dbq_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES1(ch), + MODULE_CONTROL_MDLC0xMSRESS1(ch)); + + /* ddr_reset_apb / ddr_reset_hard / ddr_reset */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC0xMSRES3(ch), + MODULE_CONTROL_MDLC0xMSRESS3(ch)); + + /* ddrfi */ + dbsc5_msres_sync_wait(MODULE_CONTROL_MDLC15MSRES8, + MODULE_CONTROL_MDLC15MSRESS8); + + /* Disables write access of protected registers */ + /* dbq_reset / ddr_reset_apb / ddr_reset_hard / ddr_reset */ + writel(0xa5a5a500, MODULE_CONTROL_MDLC0xPKCPROT1(ch)); + /* ddrfi */ + writel(0xa5a5a500, MODULE_CONTROL_MDLC12PKCPROT1); + } +} + +/** + * dbsc5_reg_write() - Write DBSC register + * @dev: DBSC5 device + * @addr: Destination address + * @data: Setting value to be written + * + * Write 32bit value @data to register at @addr . + */ +static void dbsc5_reg_write(struct udevice *dev, uintptr_t addr, u32 data) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + int i; + + for (i = 0; i < DBSC5_DBSC_CNT; i++) { + if (!(priv->ddr_phyvalid & BIT(i))) + continue; + + if ((addr & 0xFFF00000) == 0xE9900000) /* clk_dbsc region */ + writel(data, addr + (0x4000 * i)); + else /* clk_axim region */ + writel(data, addr + (0x8000 * i)); + } +} + +/** + * dbsc5_regset_unlock() - Unlock DBSC access + * @dev: DBSC5 device + */ +static void dbsc5_regset_unlock(struct udevice *dev) +{ + dbsc5_reg_write(dev, DBSC_DBSYSCNT0, 0x1234); + dbsc5_reg_write(dev, DBSC_DBSYSCNT0A, 0x1234); +} + +/** + * dbsc5_regset_lock() - Lock DBSC access + * @dev: DBSC5 device + */ +static void dbsc5_regset_lock(struct udevice *dev) +{ + dbsc5_reg_write(dev, DBSC_DBSYSCNT0, 0); + dbsc5_reg_write(dev, DBSC_DBSYSCNT0A, 0); +} + +/** + * dbsc5_send_dbcmd() - DRAM Command Write + * @dev: DBSC5 device + * @cmd: Command + */ +static void dbsc5_send_dbcmd(struct udevice *dev, u32 cmd) +{ + readl(DBSC_DBCMD); /* Dummy read */ + + while (readl(DBSC_DBWAIT) & BIT(0)) /* Wait for not busy */ + ; + + dbsc5_reg_write(dev, DBSC_DBCMD, cmd); +} + +/** + * dbsc5_send_dbcmd_ch() - DRAM Command Write on channel + * @ch: DBSC5 channel + * @cmd: Command + */ +static void dbsc5_send_dbcmd_ch(u32 ch, u32 cmd) +{ + readl(DBSC_DBCMD); /* Dummy read */ + + while (readl(DBSC_DBWAIT) & BIT(0)) /* Wait for not busy */ + ; + + writel(cmd, DBSC_DBCMD + (0x4000 * ch)); +} + +/** + * dbsc5_f_scale_rate() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ddr_mbps: DRAM Mbps + * @ddr_mbpsdiv: DRAM Mbps divider + * @ps: Optimal setting value in pico second + * @cyc: Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale_rate(struct renesas_dbsc5_dram_priv *priv, const bool frac, + u32 ddr_mbps, u32 ddr_mbpsdiv, u32 ps, u32 cyc) +{ + const u32 mul = frac ? 8 : 800000; + const u32 tmp = DIV_ROUND_UP(ps, 10UL) * ddr_mbps; + const u32 f_scale_div = DIV_ROUND_UP(tmp, mul * ddr_mbpsdiv); + + return (f_scale_div > cyc) ? f_scale_div : cyc; +} + +/** + * dbsc5_f_scale() - Calculate the best value for DBSC timing setting + * @priv: Driver private data + * @frac: Perform fractional rounding + * @ps: Optimal setting value in pico second + * @cyc: Optimal setting value in cycle count + * + * Convert the optimal value in pico second to in cycle count. Optionally, if @frac is true, + * perform fractional rounding. Compare the value of the result of the conversion with the + * value of the argument @cyc and return the larger value. + */ +static u32 dbsc5_f_scale(struct renesas_dbsc5_dram_priv *priv, const bool frac, u32 ps, u32 cyc) +{ + return dbsc5_f_scale_rate(priv, frac, priv->ddr_mbps, priv->ddr_mbpsdiv, ps, cyc); +} + +/** + * dbsc5_f_scale_js2() - Select optimal settings based on jedec_spec2 + * @priv: Driver private data + * @js2: Array of jedec spec2 setting table + * + * Calculate and assign each setting value of jedec_spec2 by "dbsc5_f_scale" function. + * Only the following array elements are calculated using different formulas from those + * described above -- JS2_tRRD/JS2_tFAW/JS2_tZQCALns/JS2_tRCpb/JS2_tRCab. + */ +static void dbsc5_f_scale_js2(struct renesas_dbsc5_dram_priv *priv, u32 *f_js2) +{ + int i; + + for (i = 0; i < JS2_TBLCNT; i++) { + f_js2[i] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][i].ps, + jedec_spec2[JS2_DERATE][i].cyc); + } + + f_js2[JS2_tRRD] = dbsc5_f_scale(priv, false, + js1[priv->js1_ind].tRRD + jedec_spec2[JS2_DERATE][JS2_tRRD].ps, + jedec_spec2[JS2_DERATE][JS2_tRRD].cyc); + f_js2[JS2_tFAW] = dbsc5_f_scale(priv, false, + js1[priv->js1_ind].tFAW + jedec_spec2[JS2_DERATE][JS2_tFAW].ps, + jedec_spec2[JS2_DERATE][JS2_tFAW].cyc); + f_js2[JS2_tZQCALns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tZQCALns].ps * 1000, 0); + f_js2[JS2_tDQ72DQns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tDQ72DQns].ps * 1000, 0); + f_js2[JS2_tCAENTns] = dbsc5_f_scale(priv, false, + jedec_spec2[JS2_DERATE][JS2_tCAENTns].ps * 1000, 0); + f_js2[JS2_tRCpb] = f_js2[JS2_tRAS] + f_js2[JS2_tRPpb]; + f_js2[JS2_tRCab] = f_js2[JS2_tRAS] + f_js2[JS2_tRPab]; + f_js2[JS2_tRFCab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_ab[priv->max_density] * 1000, 0); + f_js2[JS2_tRFCpb] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFC_pb[priv->max_density] * 1000, 0); + f_js2[JS2_tpbR2pbR] = dbsc5_f_scale(priv, false, + jedec_spec2_tpbR2pbR[priv->max_density] * 1000, 0); + f_js2[JS2_tRFMab] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFM_ab[priv->max_density] * 1000, 0); + f_js2[JS2_tRFMpb] = dbsc5_f_scale(priv, false, + jedec_spec2_tRFM_pb[priv->max_density] * 1000, 0); + + f_js2[JS2_tRBTP] = dbsc5_f_scale(priv, false, 7500, 2) - 2; + f_js2[JS2_tXSR] = f_js2[JS2_tRFCab] + dbsc5_f_scale(priv, false, 7500, 2); + f_js2[JS2_tPDN] = dbsc5_f_scale(priv, false, 10000, 0) + 1; + f_js2[JS2_tPDN_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tPDN_DSM].ps * 10, 0); + f_js2[JS2_tXSR_DSM] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tXSR_DSM].ps * 10, 0); + f_js2[JS2_tXDSM_XP] = dbsc5_f_scale(priv, true, + jedec_spec2[JS2_DERATE][JS2_tXDSM_XP].ps * 10, 0); + f_js2[JS2_tWLWCKOFF] = dbsc5_f_scale(priv, false, 14000, 5); +} + +/** + * dbsc5_dbsc_regset_pre() - Configure primary DDR registers + * @dev: DBSC5 device + * + * Set SDRAM type, Burst length, and PHY type. Frequency mode setting. + * Write SDRAM configuration contents to registers. + */ +static void dbsc5_dbsc_regset_pre(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ddr_density[DRAM_CH_CNT][CS_CNT]; + u32 RL, WL, WCKENLR; + u32 ch, cs, i, val; + u32 js2[JS2_CNT]; + u32 param_trdwr; + u32 tmp[4]; + + /* Determine DBSC clock frequency (in MHz) */ + const u32 ni = (readl(SYSSS_PLL1_1_CR0) >> 20) & 0x1FF; + const u32 cksel = (readl(SYSSS_PLL1_1_CR0) >> 7) & 0x1; + const u32 div = 0x20 - ((readl(SYSSS_PLL1_1DCR)) & 0x1F); + const u32 bus_clk = ((priv->brd_clk * (ni + 1) * 2) * div) / (cksel + 1) / 32 / 4; + + /* Determine board density */ + priv->max_density = 0; + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + for (cs = 0; cs < CS_CNT; cs++) { + ddr_density[ch][cs] = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] == 0xFF) + continue; + + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] > priv->max_density) + priv->max_density = priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs]; + } + } + + /* Search jedec_spec1 index */ + for (i = JS1_USABLEC_SPEC_LO; i < (JS1_FREQ_TBL_NUM - 1); i++) + if ((js1[i].fx3 * 2 * priv->ddr_mbpsdiv) >= (priv->ddr_mbps * 3)) + break; + + if (i > JS1_USABLEC_SPEC_HI) + priv->js1_ind = JS1_USABLEC_SPEC_HI; + else + priv->js1_ind = i; + + RL = js1[priv->js1_ind].RLset0; + WL = js1[priv->js1_ind].WLsetA; + WCKENLR = js1[priv->js1_ind].WCKENLR0; + + /* Calculate jedec_spec2 */ + dbsc5_f_scale_js2(priv, js2); + + /* LPDDR5, BL=16, DFI interface */ + dbsc5_reg_write(dev, DBSC_DBMEMKIND, 0xC); + dbsc5_reg_write(dev, DBSC_DBMEMKINDA, 0xC); + dbsc5_reg_write(dev, DBSC_DBBL, 0x2); + dbsc5_reg_write(dev, DBSC_DBBLA, 0x2); + + /* dcmpmd = 2 : bypass mode */ + dbsc5_reg_write(dev, DBSC_DBSYSCNT1A, 0x2); + dbsc5_reg_write(dev, DBSC_DBPHYCONF0, 0x1); + dbsc5_reg_write(dev, DBSC_DBSYSCONF0, 0x1); + + /* FREQRATIO=2 */ + dbsc5_reg_write(dev, DBSC_DBSYSCONF1, 0x20000); + dbsc5_reg_write(dev, DBSC_DBSYSCONF1A, 0); + dbsc5_reg_write(dev, DBSC_DBSYSCONF2, 0x1); + dbsc5_reg_write(dev, DBSC_DBSYSCONF2A, 0x241); + + for (ch = 0; ch < DRAM_CH_CNT; ch++) { + for (cs = 0; cs < CS_CNT; cs++) { + if (ddr_density[ch][cs] == 0xFF) { + writel(0, DBSC_DBMEMCONF(ch, cs)); + writel(0, DBSC_DBMEMCONFA(ch, cs)); + } else { + writel(DBMEMCONF_REGD(ddr_density[ch][cs]), + DBSC_DBMEMCONF(ch, cs)); + writel(DBMEMCONF_REGD(ddr_density[ch][cs]), + DBSC_DBMEMCONFA(ch, cs)); + } + } + } + + /* DBTR0.cl : RL */ + dbsc5_reg_write(dev, DBSC_DBTR(0), RL); + + /* DBTR1.cwl : WL */ + dbsc5_reg_write(dev, DBSC_DBTR(1), WL); + + /* DBTR2.al = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(2), 0); + + /* DBTR3.trcd : tRCD */ + dbsc5_reg_write(dev, DBSC_DBTR(3), js2[JS2_tRCD]); + + /* DBTR4.trpa,trp : tRPab,tRPpb */ + dbsc5_reg_write(dev, DBSC_DBTR(4), (js2[JS2_tRPab] << 16) | js2[JS2_tRPpb]); + + /* DBTR5.trc : tRCpb */ + dbsc5_reg_write(dev, DBSC_DBTR(5), js2[JS2_tRCpb]); + + /* DBTR6.tras : tRAS */ + dbsc5_reg_write(dev, DBSC_DBTR(6), js2[JS2_tRAS]); + + /* DBTR7.trrd : tRRD */ + dbsc5_reg_write(dev, DBSC_DBTR(7), (js2[JS2_tRRD] << 16) | js2[JS2_tRRD]); + + /* DBTR8.tfaw : tFAW */ + dbsc5_reg_write(dev, DBSC_DBTR(8), js2[JS2_tFAW]); + + /* DBTR9.trdpr : nRBTP */ + dbsc5_reg_write(dev, DBSC_DBTR(9), js1[priv->js1_ind].nRBTP); + + /* DBTR10.twr : nWR */ + dbsc5_reg_write(dev, DBSC_DBTR(10), js1[priv->js1_ind].nWR); + + /* + * DBTR11.trdwr : RL + BL/n_max + RU(tWCK2DQO(max)/tCK) + RD(tRPST/tCK) - + * ODTLon - RD(tODTon(min)/tCK) + 1 + feature + */ + param_trdwr = RL + 4 + js2[JS2_tWCK2DQO_HF] + 0 - js1[priv->js1_ind].ODTLon - + (js2[JS2_tODTon_min] - 1) + 1 + 0; + dbsc5_reg_write(dev, DBSC_DBTR(11), param_trdwr); + + /* DBTR12.twrrd_s,twrrd : WL + BL/2 + tWTR_S,WL + BL + tWTR_L */ + dbsc5_reg_write(dev, DBSC_DBTR(12), ((WL + 2 + js2[JS2_tWTR_S]) << 16) | + (WL + 4 + js2[JS2_tWTR_L])); + + /* DBTR13.trfcpb,trfc : tRFCpb,tRFCab */ + dbsc5_reg_write(dev, DBSC_DBTR(13), (js2[JS2_tRFCpb] << 16) | (js2[JS2_tRFCab])); + + /* DBTR14.tcscal,tckehdll,tckeh : tCSCAL,tXP,tXP */ + dbsc5_reg_write(dev, DBSC_DBTR(14), (js2[JS2_tCSCAL] << 24) | (js2[JS2_tXP] << 16) | + js2[JS2_tXP]); + + /* DBTR15 */ + /* tckel : tSR */ + tmp[0] = js2[JS2_tSR]; + /* tckesr : tSR */ + tmp[1] = js2[JS2_tSR]; + /* tespd : tESPD = 2 */ + tmp[2] = 0x2; + dbsc5_reg_write(dev, DBSC_DBTR(15), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR16 */ + /* wdql(tphy_wrlat + tphy_wrdata) */ + tmp[0] = (WL * 4) - 5 + 2; + /* dqenltcy(tphy_wrlat) */ + tmp[1] = (WL * 4) - 5; + /* dql(tphy_rdlat + trddata_en) : (6 + csrDFIMRL) * 4 + trddata_en */ + tmp[2] = ((6 + 7) * 4) + ((RL * 4) - 13); + /* dqienltncy(trddata_en) : RL * 4 - 13 */ + tmp[3] = (RL * 4) - 13; + dbsc5_reg_write(dev, DBSC_DBTR(16), (tmp[3] << 25) | (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR17.tmodrd,tmod : tMRR,tMRW */ + dbsc5_reg_write(dev, DBSC_DBTR(17), (js2[JS2_tMRR] << 24) | (js2[JS2_tMRW] << 16)); + + /* DBTR18.rodtl,rodta = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(18), 0); + + /* DBTR19.tzqcl,tzqcs = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(19), 0); + + /* DBTR20.txsdll,txs : tXSR,tXSR */ + dbsc5_reg_write(dev, DBSC_DBTR(20), (js2[JS2_tXSR] << 16) | js2[JS2_tXSR]); + + /* DBTR21.tccdmw, tccd */ + /* tccd(BL/2_max) */ + tmp[0] = 0x4; + /* tccd_s(BL/2_min) */ + tmp[1] = 0x2; + /* tccdmw */ + if ((priv->ddr_mbps * 3) > (25600 * priv->ddr_mbpsdiv)) + tmp[2] = 0x14; + else + tmp[2] = 0x10; + dbsc5_reg_write(dev, DBSC_DBTR(21), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR22.tzqcal,tzqlat : tZQCAL,tZQLAT */ + dbsc5_reg_write(dev, DBSC_DBTR(22), (js2[JS2_tZQCALns] << 16) | js2[JS2_tZQLAT]); + + /* DBTR23.rrspc = 0 */ + dbsc5_reg_write(dev, DBSC_DBTR(23), 0); + + /* DBTR24 */ + /* wrcslat(tphy_wrcslat) */ + tmp[0] = (WL * 4) - 5; + /* wrcsgap(tphy_wrcsgap) */ + tmp[1] = 0x4; + /* rdcslat(tphy_rdcslat) */ + tmp[2] = (RL * 4) - 13; + /* rdcsgap(tphy_rdcsgap) */ + tmp[3] = 0x4; + dbsc5_reg_write(dev, DBSC_DBTR(24), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR25 */ + dbsc5_reg_write(dev, DBSC_DBTR(25), 0); + + /* DBTR26 */ + dbsc5_reg_write(dev, DBSC_DBTR(26), 0); + + /* DBTR27.tpdn : tPDN */ + dbsc5_reg_write(dev, DBSC_DBTR(27), js2[JS2_tPDN]); + + /* DBTR28.txsrdsm : tXSR_DSM */ + dbsc5_reg_write(dev, DBSC_DBTR(28), js2[JS2_tXSR_DSM]); + + /* DBTR29.tdsmxp : tXDSM_XP */ + dbsc5_reg_write(dev, DBSC_DBTR(29), js2[JS2_tXDSM_XP]); + + /* DBTR30.tcmdpd : tCMDPD = 3 */ + dbsc5_reg_write(dev, DBSC_DBTR(30), 0x3); + + /* DBTR31.twck2dqomax,twck2dqimax : tWCK2DQO_HF/LF,tWCK2DQI_HF/LF */ + dbsc5_reg_write(dev, DBSC_DBTR(31), (js2[JS2_tWCK2DQO_HF] << 4) | js2[JS2_tWCK2DQI_HF]); + + /* DBTR32 */ + /* twckenr */ + tmp[0] = (WCKENLR * 4) - 4 - 1; + /* twckenw */ + tmp[1] = (js1[priv->js1_ind].WCKENLW * 4) - 4 - 1; + /* twckenlf */ + tmp[2] = (js1[priv->js1_ind].WCKENLF * 4) - 4; + /* twckpresta */ + tmp[3] = js1[priv->js1_ind].WCKPRESTA * 4; + dbsc5_reg_write(dev, DBSC_DBTR(32), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBTR33 */ + /* twcktgl */ + tmp[0] = 4; + /* twckdis : (RL+ bl/n_max) * 4 + RU(tWCKPST/tWCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = ((RL + 4) * 4) + 3; + dbsc5_reg_write(dev, DBSC_DBTR(33), (tmp[1] << 8) | tmp[0]); + + /* DBTR34 */ + /* twcksus = 4 */ + tmp[0] = 4; + /* twckpst : RU(tWCKPST/tCK),tWCKPST = MR10[3:2] = 2.5 */ + tmp[1] = 1; + dbsc5_reg_write(dev, DBSC_DBTR(34), (tmp[1] << 8) | tmp[0]); + + /* DBTR35 */ + /* trd2wckoff : RL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[0] = RL + 4 + 0 + 1; + /* twr2wckoff : WL + BL/n_max + RD(tWCKPST/tCK) + 1 */ + tmp[1] = WL + 4 + 0 + 1; + dbsc5_reg_write(dev, DBSC_DBTR(35), (tmp[1] << 16) | tmp[0]); + + /* DBTR36 */ + /* twssuswrx : CAS(WCKSUS)WRX */ + tmp[0] = 3; + /* twsoffwrx : CAS(WS_OFF)WRX */ + tmp[1] = 3; + /* twsfswrx : CAS(WS_FS)WRX */ + tmp[2] = 2; + dbsc5_reg_write(dev, DBSC_DBTR(36), (tmp[2] << 16) | (tmp[1] << 8) | tmp[0]); + + /* DBTR37 */ + /* tosco : tOSCODQI */ + tmp[0] = js2[JS2_tOSCODQI]; + /* toscodqi : tOSCODQI */ + tmp[1] = js2[JS2_tOSCODQI]; + /* toscodqo : tOSCODQO */ + tmp[2] = js2[JS2_tOSCODQO]; + dbsc5_reg_write(dev, DBSC_DBTR(37), (tmp[2] << 24) | (tmp[1] << 16) | tmp[0]); + + /* DBTR38.tpbr2act,tpbr2pbr : tpbR2act,tpbR2pbR */ + dbsc5_reg_write(dev, DBSC_DBTR(38), (js2[JS2_tpbR2act] << 8) | js2[JS2_tpbR2pbR]); + + /* DBTR39.trfmpb,trmbab : tRFMpb,tRFMab */ + dbsc5_reg_write(dev, DBSC_DBTR(39), (js2[JS2_tRFMpb] << 16) | js2[JS2_tRFMab]); + + /* DBRNK2 */ + /* rnkrr = tphy_wckcsgap + tWCK2DQO_rank2rank_HF/tWCK */ + val = dbsc5_f_scale_rate(priv, false, priv->ddr_mbps * 4, priv->ddr_mbpsdiv, 650, 0); + tmp[0] = (4 + val) / 4; + if ((tmp[0] * 4) == (4 + val)) + val = tmp[0]; + else + val = tmp[0] + 1; + dbsc5_reg_write(dev, DBSC_DBRNK(2), (val << 4) | val); + + /* DBRNK3 */ + /* rnkrw = tphy_wckcsgap + tWCK2DQO_rank2rank_HF/tWCK */ + val = dbsc5_f_scale_rate(priv, false, priv->ddr_mbps * 4, priv->ddr_mbpsdiv, 650, 0); + tmp[0] = (4 + val) / 4; + if ((tmp[0] * 4) == (4 + val)) + val = tmp[0]; + else + val = (tmp[0] + 1); + + /* trd2wckoff - trdwr */ + tmp[0] = (RL + 4 + 0 + 1) - param_trdwr; + if (tmp[0] > val) + val = tmp[0]; + dbsc5_reg_write(dev, DBSC_DBRNK(3), (val << 4) | val); + + /* DBRNK4 */ + /* rnkwr = tphy_wckcsgap */ + dbsc5_reg_write(dev, DBSC_DBRNK(4), 0x11); + + /* DBRNK5 */ + /* rnkww = tphy_wckcsgap */ + dbsc5_reg_write(dev, DBSC_DBRNK(5), 0x11); + + /* DBRNK6 */ + /* refmode = tphy_wckcsgap */ + /* per_bank_refresh */ + dbsc5_reg_write(dev, DBSC_DBRNK(6), 0x1); + + /* SCFCTST0 */ + /* scpreact */ + tmp[0] = 1UL * js2[JS2_tRPpb] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scactrdwr */ + tmp[1] = 1UL * (WL + 2 + 1 + js1[priv->js1_ind].nWR + js2[JS2_tRPpb]) * + bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv; + /* scrdacrt */ + tmp[2] = 1UL * ((js1[priv->js1_ind].nRBTP + 2) + js2[JS2_tRPpb]) * + bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv; + /* scactact */ + tmp[3] = 1UL * js2[JS2_tRCpb] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHFCTST(0), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* SCFCTST1 */ + /* scasyncofs */ + tmp[0] = 12; + /* scactrdwr */ + tmp[1] = 1UL * js2[JS2_tRCD] * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scwrrd */ + tmp[2] = 1UL * (WL + 4 + js2[JS2_tWTR_L]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* scrdwr */ + tmp[3] = 1UL * param_trdwr * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHFCTST(1), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW1 */ + /* sctrfcab */ + val = 1UL * (js2[JS2_tRFCab] + js2[JS2_tZQLAT]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* sctrfcab[7:0] = DBSCHRW1[7:0] */ + tmp[0] = val & 0xFF; + /* sctrfcab[8] = DBSCHRW1[24] */ + tmp[3] = val & 0x100; + /* sctrfcpb */ + tmp[1] = 1UL * (js2[JS2_tRFCpb]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + /* sctrfcpb */ + tmp[2] = 1UL * (js2[JS2_tpbR2pbR]) * bus_clk * priv->ddr_mbpsdiv * 8 / + priv->ddr_mbps / priv->brd_clkdiv; + dbsc5_reg_write(dev, DBSC_DBSCHRW(1), (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + /* DBSCHRW2 */ + /* scrfpben */ + tmp[0] = 1; + /* screfipb : tREFIpb */ + tmp[1] = DBSC_REFINT * bus_clk / priv->brd_clkdiv / 1000 / 8; + dbsc5_reg_write(dev, DBSC_DBSCHRW(2), (tmp[1] << 16) | tmp[0]); + + /* DBSCHTR0 */ + /* scdt0 */ + tmp[0] = (1UL * 4 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt1 */ + tmp[1] = (1UL * 8 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt2 */ + tmp[2] = (1UL * 12 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + /* scdt3 */ + tmp[3] = (1UL * 16 * bus_clk * priv->ddr_mbpsdiv * 8 / priv->ddr_mbps / priv->brd_clkdiv) - 1; + dbsc5_reg_write(dev, DBSC_DBSCHTR0, (tmp[3] << 24) | (tmp[2] << 16) | + (tmp[1] << 8) | tmp[0]); + + dbsc5_reg_write(dev, DBSC_DBBCAMDIS, 0x10); + + /* Dummy PDE */ + dbsc5_send_dbcmd(dev, 0x8840000); + /* Dummy PDX */ + dbsc5_send_dbcmd(dev, 0x8840001); +} + +/** + * dbsc5_dbsc_regset_post() - Set DBSC registers + * @dev: DBSC5 device + */ +static void dbsc5_dbsc_regset_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 val; + u32 tmp; + + dbsc5_reg_write(dev, DBSC_DBBUS0CNF1, 0); + + /* SRX */ + dbsc5_send_dbcmd(dev, 0xA840001); + + /* Write DBI ON */ + dbsc5_reg_write(dev, DBSC_DBDBICNT, 0x1); + + /* set REFCYCLE */ + val = DBSC_REFINT * priv->ddr_mbps / 8000 / priv->ddr_mbpsdiv; + /* refpmax=8 */ + dbsc5_reg_write(dev, DBSC_DBRFCNF1, 0x80000 | (val & 0xFFFF)); + /* refpmin=1 */ + dbsc5_reg_write(dev, DBSC_DBRFCNF2, 0x10000); + + /* periodic dram zqcal enable */ + dbsc5_reg_write(dev, DBSC_DBCALCNF, 0x1000010); + + /* wtmode = 1, pmstrmd = 2(WA for WS1), pmstren = 1 */ + dbsc5_reg_write(dev, DBSC_DBDFIPMSTRCNF, 0x15); + + /* periodic phy ctrl update enable */ + /* max = 80, min = 76, en = 1 */ + dbsc5_reg_write(dev, DBSC_DBDFICUPDCNF, 0x504C0001); + + /* set Auto Refresh */ + dbsc5_reg_write(dev, DBSC_DBRFEN, 0x1); + + /* dram access enable */ + dbsc5_reg_write(dev, DBSC_DBACEN, 0x1); + + tmp = (PERIODIC_TRAINING_INTERVAL * 1000) / DBSC_REFINT; + /* (ZQCalibration_interval + 1) / ZQCalibration_interval */ + val = (tmp * (0x10 + 1)) / 0x10; + /* snoopen=1 */ + dbsc5_reg_write(dev, DBSC_DBSNOOPC, BIT(24) | val); +} + +#define RTMMAC_BASE 0xb8900000 +#define RTDMAC_RDMSAR_0(ch) (RTMMAC_BASE + 0x0 + ((ch) * 0x1000)) +#define RTDMAC_RDMDAR_0(ch) (RTMMAC_BASE + 0x4 + ((ch) * 0x1000)) +#define RTDMAC_RDMTCR_0(ch) (RTMMAC_BASE + 0x8 + ((ch) * 0x1000)) +#define RTDMAC_RDMCHCR_0(ch) (RTMMAC_BASE + 0xc + ((ch) * 0x1000)) +#define RTDMAC_RDMCHCLR(ch) (RTMMAC_BASE + 0x100 + ((ch) * 0x1000)) +#define RTDMAC_RDMOR 0xb9438060 + +/** + * dbsc5_rtdmac_init() - Configure RTDMAC DMA controller + * @ch: DMA Channel + * @dst: Destination address + * @src: Source address + * @cnt: Byte count + */ +static void dbsc5_rtdmac_init(u32 ch, u32 dst, u32 src, u32 cnt) +{ + /* DMA Setting - 64Byte/AutoRequest mode */ + writel(src, RTDMAC_RDMSAR_0(ch)); + writel(dst, RTDMAC_RDMDAR_0(ch)); + writel(cnt, RTDMAC_RDMTCR_0(ch)); + writel(0x105409, RTDMAC_RDMCHCR_0(ch)); +} + +/** + * dbsc5_rtdmac_start() - Start RTDMAC DMA controller + */ +static void dbsc5_rtdmac_start(void) +{ + /* Start DMA */ + writew(0x1, RTDMAC_RDMOR); +} + +/** + * dbsc5_rtdmac_wait() - Wait for RTDMAC DMA completion + * @ch: DMA Channel + */ +static void dbsc5_rtdmac_wait(int ch) +{ + u32 val; + + /* Wait for DMA completion */ + for (;;) { + val = readl(RTDMAC_RDMCHCR_0(ch)); + if (val & BIT(1)) { /* Clear TE */ + writel(val & ~BIT(1), RTDMAC_RDMCHCR_0(ch)); + break; + } + + if (val & BIT(31)) { /* Clear CAE */ + writel(val & ~BIT(31), RTDMAC_RDMCHCR_0(ch)); + break; + } + } +} + +/** + * dbsc5_rtdmac_stop() - Stop RTDMAC DMA controller + */ +static void dbsc5_rtdmac_stop(void) +{ + u32 ch; + + /* Disable DMA */ + writew(0, RTDMAC_RDMOR); + for (ch = 0; ch < 16; ch++) + writel(readl(RTDMAC_RDMCHCR_0(ch)) | BIT(0), RTDMAC_RDMCHCLR(ch)); +} + +/** + * dbsc5_rtdmac_phyinit_trans_ach() - Load PHY using RTDMAC + * @dev: DBSC5 device + * @dst: Destination address + * @src: Source address + * @size: Transfer size + */ +static void dbsc5_rtdmac_phyinit_trans_ach(struct udevice *dev, u32 dst, u32 src, u32 size) +{ + u32 ch; + + foreach_vphych(dev, ch) { + dbsc5_rtdmac_init(ch, DDR_PHY_DMA_TRANS_BASE(ch) + (dst << 2), + src, (size + 0x3f) >> 6); + dbsc5_rtdmac_start(); + } + + foreach_vphych(dev, ch) + dbsc5_rtdmac_wait(ch); + + dbsc5_rtdmac_stop(); +} + +/** + * dbsc5_phy_apb_wr() - Write PHY register + * @ch: PHY channel + * @addr: Register address + * @data: Register value + */ +static void dbsc5_phy_apb_wr(u32 ch, u32 addr, u32 data) +{ + writel(data, DDR_PHY_BASE(ch) + (addr << 2)); +} + +/** + * dbsc5_phy_apb_wr_ach() - Write PHY register on all channels + * @addr: Register address + * @data: Register value + */ +static void dbsc5_phy_apb_wr_ach(struct udevice *dev, u32 addr, u32 data) +{ + u32 ch; + + foreach_vphych(dev, ch) + dbsc5_phy_apb_wr(ch, addr, data); +} + +/** + * dbsc5_phy_apb_rd() - Read PHY register + * @ch: PHY channel + * @addr: Register address + */ +static u32 dbsc5_phy_apb_rd(u32 ch, u32 addr) +{ + return readl(DDR_PHY_BASE(ch) + (addr << 2)); +} + +/** + * ddrphy_apb_rd_mod_wr() - Read-modify-Write PHY register + * @ch: PHY channel + * @addr: Register address + * @len: Clearing bitmask length + * @lsb: Clearing bitmask shift + * @data: Register value + */ +static void ddrphy_apb_rd_mod_wr(u32 ch, u32 addr, u32 len, u32 lsb, u32 data) +{ + u32 msk = 0xffffffff; + u32 val; + + if (len != 32) + msk = (BIT(len) - 1) << lsb; + + val = dbsc5_phy_apb_rd(ch, addr); + val &= ~msk; + val |= data << lsb; + dbsc5_phy_apb_wr(ch, addr, val); +} + +/** + * dbsc5_phy_apb_rd() - Read PHY message block + * @ch: PHY channel + */ +static u32 dbsc5_phy_apb_msg_rd(u32 ch) +{ + u32 ret; + + while (dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTSHADOWREGS) & BIT(0)) + ; + + ret = dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTWRITEONLYSHADOW); + dbsc5_phy_apb_wr(ch, PHY_APBONLY_DCTWRITEPROT, 0); + + while (!(dbsc5_phy_apb_rd(ch, PHY_APBONLY_UCTSHADOWREGS) & BIT(0))) + ; + + dbsc5_phy_apb_wr(ch, PHY_APBONLY_DCTWRITEPROT, BIT(0)); + + return ret; +} + +/** + * dbsc5_ddr_config_post() - Set DDR user configuration + * @dev: DBSC5 device + */ +static void dbsc5_ddr_config_post(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, tmp; + + foreach_vphych(dev, ch) { + /* 2-Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTCONTROLVAL, 0xc3); + + /* Configure IO parameters */ + /* DRAM Tx ODT for DQ */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 3, 7, + (priv->dbsc5_board_config->bdcfg_tx_odt >> 4) & 0x7); + + /* DRAM Tx ODT for CA */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 3, 11, + (priv->dbsc5_board_config->bdcfg_tx_odt) & 0x7); + + /* DRAM Tx NT DQ ODT */ + tmp = (priv->dbsc5_board_config->bdcfg_tx_ntodt) & 0x7; + if (tmp < 0x4) { + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 1, 6, 0x0); + tmp += 4; + } + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 3, 12, tmp); + + /* DRAM Tx NT ODT */ + ddrphy_apb_rd_mod_wr(ch, 0x41036, 1, 10, + ((priv->dbsc5_board_config->bdcfg_tx_ntodt) >> 4) & 0x1); + + /* DRAM Tx Per-pin DFE */ + ddrphy_apb_rd_mod_wr(ch, 0x4105A, 1, 7, + (priv->dbsc5_board_config->bdcfg_tx_dfe) & 0x1); + + /* DRAM Rx DRV */ + ddrphy_apb_rd_mod_wr(ch, 0x41026, 3, 7, + (priv->dbsc5_board_config->bdcfg_rx_drv) & 0x7); + + /* Link ECC setting */ + if (priv->link_ecc_en) { + ddrphy_apb_rd_mod_wr(ch, 0x41052, 1, 11, 0x1); + ddrphy_apb_rd_mod_wr(ch, 0x41052, 1, 13, 0x1); + } + } +} + +/** + * dbsc5_ddr_smb_config() - Set user configuration + * @dev: DBSC5 device + */ +static void dbsc5_ddr_smb_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, val; + + foreach_vphych(dev, ch) { + /* Frequency settings */ + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { + /* 5501 - 6400 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x1900); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xB0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xBB); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x3B); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x37); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { + /* 6401 - 7500 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x1D48); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xC0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xCC); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x4B); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x43); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { + /* 7501 - 8533 -- None */ + } else { + /* 8534 - 9600 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DRAMFREQ, 16, 16, 0x2580); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_DCAOPTS, 8, 8, 0x44); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A0, 8, 16, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_A1, 8, 24, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B0, 8, 0, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR1_B1, 8, 8, 0xE0); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A0, 8, 16, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_A1, 8, 24, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B0, 8, 0, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR2_B1, 8, 8, 0xEE); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, 0x63); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, 0x57); + } + + /* 2Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) { + ddrphy_apb_rd_mod_wr(ch, PHY_APB_CSPRESENTCHA, 2, 8, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_CSPRESENTCHB, 2, 0, 0x3); + } + + /* Board settings, data byte swap */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_UPPERLOWERBYTE, 4, 8, priv->upper_lower_byte[ch]); + + /* Configure Training settings */ + /* SOC Rx DFE function */ + if (!(priv->dbsc5_board_config->bdcfg_rx_dfe & BIT(0))) { + /* Rx DFE Disable */ + /* RxDFEBitTimeControl[4] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEBITTIMECONTROL, 1, 4, 0x1); + } else { + /* Rx DFE DQ 1tap */ + /* RxDFEOpt[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEOPT, 1, 30, 0); + /* RxClk scan skip */ + /* RxDFEBitTimeControl[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXDFEBITTIMECONTROL, 1, 6, 1); + } + + /* DRAM Tx DFE function */ + val = priv->dbsc5_board_config->bdcfg_tx_dfe & 0x7; + if (val == 0x0) { + /* Tx DFE Disable */ + /* PHY_APB_SEQUENCECTRL[10] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 10, 0x0); + } else { + /* Select Tx DFE step */ + /* DRAM Tx DFE for Upper */ + /* PHY_APB_MR24_A0, PHY_APB_MR24_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A0, 3, 20, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A1, 3, 28, val); + /* PHY_APB_MR24_B0, PHY_APB_MR24_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B0, 3, 4, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B1, 3, 12, val); + + /* DRAM Tx DFE for Lower */ + /* PHY_APB_MR24_A0, PHY_APB_MR24_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_A1, 3, 24, val); + /* PHY_APB_MR24_B0, PHY_APB_MR24_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR24_B1, 3, 8, val); + } + + /* DRAM Tx Per-pin DFE */ + val = (priv->dbsc5_board_config->bdcfg_tx_dfe >> 4) & 0x1; + /* PHY_APB_MR41_A0, PHY_APB_MR41_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A0, 1, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A1, 1, 24, val); + /* PHY_APB_MR41_B0, PHY_APB_MR41_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B0, 1, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B1, 1, 8, val); + /* TxDFETrainOpt[0] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXDFETRAINOPT, val, 1, 0); + + /* DRAM Rx DCA function */ + /* PHY_APB_SEQUENCECTRL[7] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 7, + priv->dbsc5_board_config->bdcfg_rx_dca & 0x1); + + /* DRAM Tx DCA function */ + /* PHY_APB_SEQUENCECTRL[6] */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_SEQUENCECTRL, 1, 6, + priv->dbsc5_board_config->bdcfg_tx_dca & 0x1); + + /* CA Vref training initial value */ + val = priv->dbsc5_board_config->bdcfg_ca_vref & 0x7F; + /* PHY_APB_MR12_A0, PHY_APB_MR12_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_A0, 7, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_A1, 7, 24, val); + /* PHY_APB_MR12_B0, PHY_APB_MR12_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_B0, 7, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR12_B1, 7, 8, val); + + /* Rx Vref training range */ + /* RxVrefStartPat, RxVrefStartPrbs */ + val = priv->dbsc5_board_config->bdcfg_rx_vref & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTARTPAT, 16, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTARTPRBS, 16, 16, val); + /* RxVrefEndPat, RxVrefEndPrbs */ + val = (priv->dbsc5_board_config->bdcfg_rx_vref >> 16) & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFENDPAT, 16, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFENDPRBS, 16, 16, val); + /* RxVrefStepPat, RxVrefStepPrbs */ + val = priv->dbsc5_board_config->bdcfg_rx_vref_step & 0xFFFF; + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTEPPAT, 16, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_RXVREFSTEPPRBS, 16, 0, val); + + /* Tx Vref training range */ + /* TxVrefStart */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFSTART, 8, 0, + priv->dbsc5_board_config->bdcfg_tx_vref & 0xFF); + /* TxVrefEnd */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFEND, 8, 8, + (priv->dbsc5_board_config->bdcfg_tx_vref >> 8) & 0xFF); + /* TxVrefStep */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_TXVREFSTEP, 8, 16, + (priv->dbsc5_board_config->bdcfg_tx_vref >> 16) & 0xFF); + + /* FW message setting */ + /* HdtCtrl */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_HDTCTRL, 8, 16, 0xff); + + /* Configure IO parameters */ + /* DRAM Tx ODT for DQ */ + val = (priv->dbsc5_board_config->bdcfg_tx_odt >> 4) & 0x7; + /* PHY_APB_MR11_A0, PHY_APB_MR11_B0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 3, 24, val); + /* PHY_APB_MR11_A1, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 3, 8, val); + + /* DRAM Tx ODT for CA */ + val = priv->dbsc5_board_config->bdcfg_tx_odt & 0x7; + /* PHY_APB_MR11_A0, PHY_APB_MR11_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 3, 20, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 3, 28, val); + /* PHY_APB_MR11_B0, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 3, 4, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 3, 12, val); + + /* DRAM Tx NT DQ ODT */ + val = priv->dbsc5_board_config->bdcfg_tx_ntodt & 0x7; + /* PHY_APB_MR41_A0, PHY_APB_MR41_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A0, 3, 21, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_A1, 3, 29, val); + /* PHY_APB_MR41_B0, PHY_APB_MR41_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B0, 3, 5, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR41_B1, 3, 13, val); + + /* DRAM Tx NT ODT */ + val = (priv->dbsc5_board_config->bdcfg_tx_ntodt >> 4) & 0x1; + /* PHY_APB_MR11_A0, PHY_APB_MR11_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A0, 1, 19, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_A1, 1, 27, val); + /* PHY_APB_MR11_B0, PHY_APB_MR11_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B0, 1, 3, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR11_B1, 1, 11, val); + + /* DRAM Rx DRV */ + val = priv->dbsc5_board_config->bdcfg_rx_drv & 0x7; + /* PHY_APB_MR3_A0, PHY_APB_MR3_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_A0, 3, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_A1, 3, 24, val); + /* PHY_APB_MR3_B0, PHY_APB_MR3_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_B0, 3, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR3_B1, 3, 8, val); + + /* DRAM Rx Pre-emphasis */ + val = ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 12) & 0x3); + val |= ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 8) & 0x3) << 2; + val |= ((priv->dbsc5_board_config->bdcfg_rx_emphasis >> 4) & 0x3) << 4; + val |= (priv->dbsc5_board_config->bdcfg_rx_emphasis & 0x3) << 6; + /* PHY_APB_MR58_A0, PHY_APB_MR58_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_A0, 8, 16, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_A1, 8, 24, val); + /* PHY_APB_MR58_B0, PHY_APB_MR58_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_B0, 8, 0, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR58_B1, 8, 8, val); + + /* Link ECC setting */ + if (priv->link_ecc_en) { + /* PHY_APB_MR22_A0, PHY_APB_MR22_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A0, 1, 20, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A1, 1, 28, 0x1); + /* PHY_APB_MR22_B0, PHY_APB_MR22_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B0, 1, 4, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B1, 1, 12, 0x1); + /* PHY_APB_MR22_A0, PHY_APB_MR22_A1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A0, 1, 22, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_A1, 1, 30, 0x1); + /* PHY_APB_MR22_B0, PHY_APB_MR22_B1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B0, 1, 6, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MR22_B1, 1, 14, 0x1); + /* PHY_APB_ALT_RL, PHY_APB_MAIN_RL */ + if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { + /* 6401 - 7500 */ + val = 0x5B; + } else { + /* 7501 - 8533 */ + val = 0x4F; + } + ddrphy_apb_rd_mod_wr(ch, PHY_APB_ALT_RL, 8, 24, val); + ddrphy_apb_rd_mod_wr(ch, PHY_APB_MAIN_RL, 8, 0, val); + } + } +} + +/** + * dbsc5_phy_data_load() - Load PHY data memory + * @dev: DBSC5 device + */ +static void dbsc5_phy_data_load(struct udevice *dev) +{ + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_STARTDCCMCLEAR, 0x0); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x0); + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_DCCM_OFS, + (uintptr_t)DMAC_TRANS_DCCM, + ARRAY_SIZE(DMAC_TRANS_DCCM) * 4); + dbsc5_ddr_smb_config(dev); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); +} + +/** + * dbsc5_phy_init_load() - Load PHY init memory + * @dev: DBSC5 device + */ +static void dbsc5_phy_init_load(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, i; + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab4); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab4[i].addr, cpu_trans_tab4[i].data); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2d56); + + foreach_vphych(dev, ch) { + if ((priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) != 0x0) { + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTLPCSENA, 0x3); + dbsc5_phy_apb_wr(ch, PHY_INITENG_SEQ0BGPR14, 0x3); + dbsc5_phy_apb_wr(ch, PHY_PPGC_HWTLPCSENB, 0x3); + dbsc5_phy_apb_wr(ch, PHY_INITENG_SEQ0BGPR15, 0x3); + } + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41000, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41001, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41002, 0); + dbsc5_phy_apb_wr_ach(dev, 0x41003, 0); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_ACSM_OFS, + (uintptr_t)DMAC_TRANS_ACSM, + ARRAY_SIZE(DMAC_TRANS_ACSM) * 4); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_PIE_OFS, + (uintptr_t)DMAC_TRANS_PIE, + ARRAY_SIZE(DMAC_TRANS_PIE) * 4); + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_SEQUENCEROVERRIDE, 0x600); + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMNOPADDR, 0x0); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMSTARTADDRXLATVAL0, + (uintptr_t)DATA_A, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab5); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab5[i].addr, cpu_trans_tab5[i].data); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMSTOPADDRXLATVAL0, + (uintptr_t)DATA_B, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab6); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab6[i].addr, cpu_trans_tab6[i].data); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x2); + else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) /* 6401 - 7500 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x3); + else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + } else /* 8534 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_PPGC_ACSMRPTCNTOVERRIDE, 0x5); + + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x41004, (uintptr_t)ACSM_0, 384); + + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { /* 5501 - 6400 */ + dbsc5_phy_apb_wr_ach(dev, 0x41009, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41011, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xD848); + dbsc5_phy_apb_wr_ach(dev, 0x41019, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xDDC8); + dbsc5_phy_apb_wr_ach(dev, 0x41021, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41029, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41031, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41039, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41045, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4104D, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41055, 0x4B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4105D, 0x4B000000); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { /* 6401 - 7500 */ + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xE048); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xE648); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + /* Nothing */ + } else { /* 8534 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, 0x41009, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41011, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41016, 0xF048); + dbsc5_phy_apb_wr_ach(dev, 0x41019, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4101E, 0xF748); + dbsc5_phy_apb_wr_ach(dev, 0x41021, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41029, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41031, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41039, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41045, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4104D, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x41055, 0x6B000000); + dbsc5_phy_apb_wr_ach(dev, 0x4105D, 0x6B000000); + } + + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x4110C, (uintptr_t)ACSM_123, 384); + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x41214, (uintptr_t)ACSM_123, 384); + dbsc5_rtdmac_phyinit_trans_ach(dev, 0x4131C, (uintptr_t)ACSM_123, 384); + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_SEQUENCEROVERRIDE, 0x400); + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_PIEINITVECSEL, 0x5821); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BDISABLEFLAG0, + (uintptr_t)DATA_C, 64); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab7); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab7[i].addr, cpu_trans_tab7[i].data); + + dbsc5_ddr_config_post(dev); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x6); + + if (priv->ddr_mbps < (6481 * priv->ddr_mbpsdiv)) { /* 5401 - 6480 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2D56); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else if (priv->ddr_mbps < (8537 * priv->ddr_mbpsdiv)) { /* 6481 - 8536 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1956); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else { /* 8537 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1956); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); +} + +/** + * dbsc5_phy_training() - Perform PHY training and read message block back + * @dev: DBSC5 device + */ +static u32 dbsc5_phy_training(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 phytrainingok = 0; + u32 fail_flag = 0; + u32 ch, val; + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0x1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x9); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 0x0); + + while ((phytrainingok != priv->ddr_phyvalid) && !fail_flag) { + foreach_vphych(dev, ch) { + val = dbsc5_phy_apb_msg_rd(ch); + if (val == 0x7) /* Training complete */ + phytrainingok |= BIT(ch); + else if (val == 0xFF) /* Training FAIL */ + fail_flag = 1; + } + } + + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICRORESET, 1); + dbsc5_phy_apb_wr_ach(dev, PHY_APBONLY_MICROCONTMUXSEL, 0); + + return phytrainingok; +} + +/** + * dbsc5_ddr_config() - Configure DBSC5 registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_config(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, ddr_ch, i, tmp, val; + + foreach_vphych(dev, ch) { + /* Frequency settings */ + if (priv->ddr_mbps < (6401 * priv->ddr_mbpsdiv)) { /* 5501 - 6400 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_6400); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_6400[i].addr, cpu_trans_tab3_6400[i].data); + } else if (priv->ddr_mbps < (7501 * priv->ddr_mbpsdiv)) { /* 6401 - 7500 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_7500); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_7500[i].addr, cpu_trans_tab3_7500[i].data); + } else if (priv->ddr_mbps < (8534 * priv->ddr_mbpsdiv)) { /* 7501 - 8533 */ + /* Nothing */ + } else { /* 8534 - 9600 */ + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3_9600); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3_9600[i].addr, cpu_trans_tab3_9600[i].data); + } + + /* 2-Rank settings */ + if (priv->ch_have_this_cs[1] & (0x3 << (ch * 2))) { + /* PHY_ACx_P0_PCLKACLNDIS[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_PCLKACLNDIS(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_PCLKACLNDIS(1), 1, 9, 0x0); + /* PHY_ACx_P0_DFICLKACLNDIS[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_DFICLKACLNDIS(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_DFICLKACLNDIS(1), 1, 9, 0x0); + /* PHY_ACx_P0_ACLNDISABLE[9] : Tx SEC lane1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_AC_ACLNDISABLE(0), 1, 9, 0x0); + ddrphy_apb_rd_mod_wr(ch, PHY_AC_ACLNDISABLE(1), 1, 9, 0x0); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[1] : PptEnDqs2DqTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 1, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 1, 0x1); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[5] : PptEnWck2DqoTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 5, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 5, 0x1); + /* PHY_DBYTEx_P0_PPTCTLSTATIC[9] : PptEnRxEnDlyTg1 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 1, 9, 0x1); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 1, 9, 0x1); + } + + /* BOARD SETTINGS (CA, DQ, DMI) */ + /* CA_SWAP_CHA */ + ddr_ch = (ch * 2); + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_ca_swap & 0xfffffff; + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA0TODFI(0), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA1TODFI(0), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA2TODFI(0), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA3TODFI(0), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA4TODFI(0), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA5TODFI(0), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA6TODFI(0), (val >> 24) & 0xf); + + /* DQ_SWAP_CHA_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[0] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(0), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(0), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(0), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(0), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(0), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(0), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(0), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(0), (val >> 28) & 0xf); + + /* DM_SWAP_CHA_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[0] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(0), val & 0xf); + + /* DQ_SWAP_CHA_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[1] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(1), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(1), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(1), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(1), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(1), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(1), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(1), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(1), (val >> 28) & 0xf); + + /* DM_SWAP_CHA_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[1] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(1), val & 0xf); + + /* CA_SWAP_CHB */ + ddr_ch = ((ch * 2) + 1); + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_ca_swap & 0xfffffff; + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA0TODFI(1), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA1TODFI(1), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA2TODFI(1), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA3TODFI(1), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA4TODFI(1), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA5TODFI(1), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_AC_MAPCA6TODFI(1), (val >> 24) & 0xf); + + /* DQ_SWAP_CHB_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[0] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(2), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(2), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(2), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(2), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(2), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(2), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(2), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(2), (val >> 28) & 0xf); + + /* DM_SWAP_CHB_SLICE0 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[0] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(2), val & 0xf); + + /* DQ_SWAP_CHB_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dq_swap[1] & 0xffffffff; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ0LNSEL(3), val & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ1LNSEL(3), (val >> 4) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ2LNSEL(3), (val >> 8) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ3LNSEL(3), (val >> 12) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ4LNSEL(3), (val >> 16) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ5LNSEL(3), (val >> 20) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ6LNSEL(3), (val >> 24) & 0xf); + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ7LNSEL(3), (val >> 28) & 0xf); + + /* DM_SWAP_CHB_SLICE1 */ + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dm_swap[1] & 0xf; + dbsc5_phy_apb_wr(ch, PHY_DBYTE_DQ8LNSEL(3), val & 0xf); + + /* BOARD SETTINGS (DATA_BYTE_SWAP) */ + priv->upper_lower_byte[ch] = 0x0; + ddr_ch = ch * 2; + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dqs_swap; + if ((val & 0xff) == 0x1) { + /* PHY_DBYTEx_P0_PPTCTLSTATIC[3][2] : DOCByteSelTg1/0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(0), 2, 2, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(1), 2, 2, 0x0); + priv->upper_lower_byte[ch] |= 0x3; + } + + ddr_ch = (ch * 2) + 1; + val = priv->dbsc5_board_config->ch[ddr_ch].bdcfg_dqs_swap; + if ((val & 0xFF) == 0x1) { + /* PHY_DBYTEx_P0_PPTCTLSTATIC[3][2] : DOCByteSelTg1/0 */ + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(2), 2, 2, 0x3); + ddrphy_apb_rd_mod_wr(ch, PHY_DBYTE_PPTCTLSTATIC(3), 2, 2, 0x0); + priv->upper_lower_byte[ch] |= 0xc; + } + } + + /* Configure IO parameters */ + /* SOC Tx DRV for DQ */ + val = priv->dbsc5_board_config->bdcfg_tx_drv & 0xf; + tmp = (val << 4) | val; + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQ(i), tmp); + + /* SOC Tx DRV for DQS */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 4) & 0xF; + tmp = (val << 8) | val; + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQS(i), tmp); + + /* SOC Tx DRV for WCK */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 8) & 0xF; + tmp = (val << 12) | (val << 8) | (val << 4) | val; + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXIMPEDANCEDQS(i + 1), tmp); + + /* SOC Tx DRV for CK */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 12) & 0xF; + tmp = (val << 4) | val; + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(12), tmp); + + /* SOC Tx DRV for AC */ + val = (priv->dbsc5_board_config->bdcfg_tx_drv >> 16) & 0xF; + tmp = (val << 4) | val; + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(i), tmp); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXIMPEDANCEAC(i + 7), tmp); + + /* SOC Tx FFC for DQ */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 28) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 24) & 0xF; + tmp |= (val << 4); + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_TXDQSLEW(i), tmp); + + /* SOC Tx FFC for CA */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 20) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 16) & 0xF; + tmp |= (val << 4); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(i), tmp); + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(i + 7), tmp); + + /* SOC Tx FFC for CK */ + /* Rise */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 12) & 0xF; + tmp = val; + /* Fall */ + val = (priv->dbsc5_board_config->bdcfg_tx_ffc >> 8) & 0xF; + tmp |= (val << 4); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_TXSLEWAC(12), tmp); + + /* SOC Rx ODT for DQ */ + val = priv->dbsc5_board_config->bdcfg_rx_odt & 0xF; + tmp = val << 4; + for (i = 0; i < 8; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQ(i), tmp); + + /* SOC Rx ODT for DQS */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 4) & 0xF; + tmp = (val << 12) | (val << 8); + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQS(i), tmp); + + /* SOC Rx ODT for WCK */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 8) & 0xF; + tmp = (val << 12) | (val << 8); + for (i = 0; i < 8; i += 2) + dbsc5_phy_apb_wr_ach(dev, PHY_HMDBYTE_ODTIMPEDANCEDQS(i + 1), tmp); + + /* SOC Rx ODT for CK */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 12) & 0xF; + tmp = val << 4; + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(5), tmp); + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(12), tmp); + + /* SOC Rx ODT for AC */ + val = (priv->dbsc5_board_config->bdcfg_rx_odt >> 16) & 0xF; + tmp = val << 4; + for (i = 0; i < 5; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(i), tmp); + for (i = 0; i < 5; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_HMAC_ODTIMPEDANCEAC(i + 7), tmp); + + /* Link ECC setting */ + if (priv->link_ecc_en) + for (i = 0; i < 4; i++) + dbsc5_phy_apb_wr_ach(dev, PHY_DBYTE_ENABLEWRITELINKECC(i), 0x1); +} + +/** + * dbsc5_phy_init() - Initialize DBSC5 PHY + * @dev: DBSC5 device + */ +static void dbsc5_phy_init(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, i; + + /* Initialize PHY Configuration */ + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab1); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab1[i].addr, cpu_trans_tab1[i].data); + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab2); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab2[i].addr, cpu_trans_tab2[i].data); + + if (priv->ddr_mbps < (6481 * priv->ddr_mbpsdiv)) { /* 5401 - 6480 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x808); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x1C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x2E9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else if (priv->ddr_mbps < (8537 * priv->ddr_mbpsdiv)) { /* 6481 - 8536 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1008); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1A9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } else { + /* 8537 - 9600 */ + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL1, 0x1008); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL4, 0x2C7F); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLCTRL5, 0x1A9A); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG0, 0x1009); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG1, 0x5060); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG2, 0x6B01); + dbsc5_phy_apb_wr_ach(dev, PHY_HMMAS_CPLLUPLLPROG3, 0x423); + } + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x5); + + dbsc5_rtdmac_phyinit_trans_ach(dev, DDR_PHY_ICCM_OFS, + (uintptr_t)DMAC_TRANS_ICCM, + ARRAY_SIZE(DMAC_TRANS_ICCM) * 4); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_UCCLKHCLKENABLES, 0x7); + + foreach_vphych(dev, ch) + for (i = 0; i < ARRAY_SIZE(cpu_trans_tab3); i++) + dbsc5_phy_apb_wr(ch, cpu_trans_tab3[i].addr, cpu_trans_tab3[i].data); + + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_PPGC_ACSMDONE, ((uintptr_t)DATA_3_1), 128); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BGPR1, ((uintptr_t)DATA_3_2), 128); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_INITENG_SEQ0BDLY0, ((uintptr_t)DATA_3_3), 64); + for (i = 0; i < 8; i += 2) { + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_HMDBYTE_VREGCTRL1DQ(i), + (uintptr_t)DATA_3_4, 256); + dbsc5_rtdmac_phyinit_trans_ach(dev, PHY_HMDBYTE_VREGCTRL1DQ(i + i), + (uintptr_t)DATA_3_5, 256); + } + + dbsc5_ddr_config(dev); + + dbsc5_phy_apb_wr_ach(dev, PHY_DRTUB_STARTDCCMCLEAR, 0x1); +} + +/** + * dbsc5_dfi_wait_init_complete() - Wait DFI init completion + * @dev: DBSC5 device + */ +static void dbsc5_dfi_wait_init_complete(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 retry = 0, phytrainingok = 0; + const u32 RETRY_MAX = 0x10000; + u32 ch, val; + + while (retry < RETRY_MAX) { + foreach_vch(dev, ch) { + val = readl(DBSC_DBDFISTAT(ch)); + if (val & 0x1) + phytrainingok |= BIT(ch); + } + + if (phytrainingok == priv->ddr_dramvalid) + break; + + retry++; + } +} + +/** + * dbsc5_dfi_init_start() - Start DFI initialization + * @dev: DBSC5 device + */ +static void dbsc5_dfi_init_start(struct udevice *dev) +{ + u32 ch; + + foreach_vch(dev, ch) + writel(0x21, DBSC_DBDFICNT(ch)); + + dbsc5_dfi_wait_init_complete(dev); + + foreach_vch(dev, ch) + writel(0x20, DBSC_DBDFICNT(ch)); +} + +/** + * dbsc5_ddr_mode_register_set() - Set DDR mode registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_mode_register_set(struct udevice *dev) +{ + dbsc5_send_dbcmd(dev, 0xE841C24); /* MR28 */ + dbsc5_send_dbcmd(dev, 0xE842540); + dbsc5_send_dbcmd(dev, 0xE842840); +} + +/** + * dbsc5_ddr_mode_register_read() - Read DDR mode registers + * @dev: DBSC5 device + */ +static void dbsc5_ddr_mode_register_read(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, val; + + val = priv->dbsc5_board_config->bdcfg_rfm_chk; + if (!val) + return; + + dbsc5_send_dbcmd(dev, 0xF801B00); /* MR27:0 */ + dbsc5_send_dbcmd(dev, 0xF803900); /* MR57:0 */ + + foreach_vphych(dev, ch) { + if ((priv->ch_have_this_cs[1] & (0x3 << (ch * 2)))) { + dbsc5_send_dbcmd_ch(ch, 0xF811B00); /* MR27:1 */ + dbsc5_send_dbcmd_ch(ch, 0xF813900); /* MR57:1 */ + } + } +} + +/** + * dbsc5_phy_pll_lock_status_read() - Read PHY PLL lock status + * @dev: DBSC5 device + */ +static u32 dbsc5_phy_pll_lock_status_read(struct udevice *dev) +{ + u32 ch, ret = 0; + + foreach_vphych(dev, ch) + ret |= (readl(DBSC_DBPDSTAT01(ch)) & BIT(0)) << ch; + + return ret; +} + +/** + * dbsc5_ddr_initialize() - Initialize DDR + * @dev: DBSC5 device + */ +static int dbsc5_ddr_initialize(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ddrphy_pll_lock_ok, phytrainingok; + + dbsc5_regset_unlock(dev); + dbsc5_msres_status_set(dev, MODULE_STANDBY); + dbsc5_init_pll3(dev); + dbsc5_msres_status_set(dev, MODULE_RUN); + dbsc5_phy_init(dev); + dbsc5_dbsc_regset_pre(dev); + dbsc5_phy_data_load(dev); + phytrainingok = dbsc5_phy_training(dev); + if (phytrainingok != priv->ddr_phyvalid) + return -EINVAL; + + dbsc5_phy_init_load(dev); + dbsc5_dfi_init_start(dev); + ddrphy_pll_lock_ok = dbsc5_phy_pll_lock_status_read(dev); + if (ddrphy_pll_lock_ok != priv->ddr_phyvalid) + return -EINVAL; + + dbsc5_ddr_mode_register_set(dev); + dbsc5_ddr_mode_register_read(dev); + + dbsc5_dbsc_regset_post(dev); + dbsc5_regset_lock(dev); + + return 0; +} + +/** + * dbsc5_get_board_data() - Obtain board specific DRAM configuration + * @dev: DBSC5 device + * + * Return board specific DRAM configuration structure pointer. + */ +__weak const struct renesas_dbsc5_board_config * +dbsc5_get_board_data(struct udevice *dev) +{ + return &renesas_x5h_dbsc5_board_config; +} + +/** + * renesas_dbsc5_dram_probe() - DDR Initialize entry + * @dev: DBSC5 device + * + * Remove write protection on DBSC register. Read DDR configuration + * information from driver data. Calculate board clock frequency and + * operating frequency from DDR configuration information. Call the + * main function of DDR initialization. Perform DBSC write protection + * after initialization is complete. + */ +static int renesas_dbsc5_dram_probe(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + u32 ch, cs, i; + + priv->dbsc5_board_config = dbsc5_get_board_data(dev); + + /* Link ECC only on SoC > 1.0 */ + if (renesas_get_cpu_rev_integer() == 1 && renesas_get_cpu_rev_fraction() == 0) + priv->link_ecc_en = 0; + else + priv->link_ecc_en = 1; + + priv->ddr_dramvalid = (u32)(priv->dbsc5_board_config->bdcfg_phyvalid); + priv->ddr_phyvalid = 0x0; + for (i = 0; i < DBSC5_PHYNUM_CNT; i++) { + priv->ddr_phyvalid |= ((((priv->ddr_dramvalid >> (i * 2)) | + (priv->ddr_dramvalid >> ((i * 2) + 1))) & 0x1) << i); + } + + for (cs = 0; cs < CS_CNT; cs++) + priv->ch_have_this_cs[cs] = 0; + + foreach_vch(dev, ch) + for (cs = 0; cs < CS_CNT; cs++) + if (priv->dbsc5_board_config->ch[ch].bdcfg_ddr_density[cs] != 0xff) + priv->ch_have_this_cs[cs] |= BIT(ch); + + /* Determine board clock frequency (in MHz) */ + priv->brd_clkdiv = 3; + switch (readl(SYSSS_PLL6_CR0)) { + case 0xa700000: /* 50 / 3 = 16.66MHz */ + priv->brd_clk = 50; + break; + case 0x8b00000: /* 60 / 3 = 20.00MHz */ + priv->brd_clk = 60; + break; + case 0xa700080: /* 100 / 3 = 33.33MHz */ + priv->brd_clk = 100; + break; + default: /* 50 / 3 = 16.66MHz */ + priv->brd_clk = 50; + break; + } + + priv->brd_clkdiva = !!(readl(SYSSS_PLL6_CR0) & BIT(7)); + + /* Determine DDR operating frequency clock (in Mbps) */ + priv->ddr_mbps = 6400; + priv->ddr_mbpsdiv = 1; + + /* Initialize DDR */ + return dbsc5_ddr_initialize(dev); +} + +/** + * renesas_dbsc5_dram_of_to_plat() - Convert OF data to plat data + * @dev: DBSC5 device + * + * Extract DBSC5 address from DT and store it in driver data. + */ +static int renesas_dbsc5_dram_of_to_plat(struct udevice *dev) +{ + struct renesas_dbsc5_dram_priv *priv = dev_get_priv(dev); + + priv->regs = dev_read_addr_ptr(dev); + if (!priv->regs) + return -EINVAL; + + return 0; +} + +/** + * renesas_dbsc5_dram_get_info() - Return RAM size + * @dev: DBSC5 device + * @info: Output RAM info + * + * Return size of the RAM managed by this RAM driver. + */ +static int renesas_dbsc5_dram_get_info(struct udevice *dev, + struct ram_info *info) +{ + info->base = 0x40000000; + info->size = 0; + + return 0; +} + +static const struct ram_ops renesas_dbsc5_dram_ops = { + .get_info = renesas_dbsc5_dram_get_info, +}; + +U_BOOT_DRIVER(renesas_dbsc5_dram) = { + .name = "dbsc5_dram", + .id = UCLASS_RAM, + .of_to_plat = renesas_dbsc5_dram_of_to_plat, + .ops = &renesas_dbsc5_dram_ops, + .probe = renesas_dbsc5_dram_probe, + .priv_auto = sizeof(struct renesas_dbsc5_dram_priv), +}; diff --git a/drivers/ram/renesas/dbsc5/r8a78000-dram.h b/drivers/ram/renesas/dbsc5/r8a78000-dram.h new file mode 100644 index 00000000000..ec810cd54bb --- /dev/null +++ b/drivers/ram/renesas/dbsc5/r8a78000-dram.h @@ -0,0 +1,7385 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ +#define __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ + +#define DDR_PHY_ICCM_OFS 0x00050000U +#define DDR_PHY_DCCM_OFS 0x00058000U +#define DDR_PHY_ACSM_OFS 0x00041454U +#define DDR_PHY_PIE_OFS 0x00044000U + +struct phyinitdata { + u32 addr; + u32 data; +}; + +static const struct phyinitdata cpu_trans_tab1[] = { + { 0x00030022, 0x00000002 }, + { 0x00031022, 0x00000002 }, + { 0x00004070, 0x000000FF }, + { 0x00005070, 0x00000077 }, + { 0x0000B070, 0x000000FF }, + { 0x0000C070, 0x00000077 }, + { 0x00104070, 0x000000FF }, + { 0x00105070, 0x00000077 }, + { 0x0010B070, 0x000000FF }, + { 0x0010C070, 0x00000077 }, + { 0x00204070, 0x000000FF }, + { 0x00205070, 0x00000077 }, + { 0x0020B070, 0x000000FF }, + { 0x0020C070, 0x00000077 }, + { 0x00304070, 0x000000FF }, + { 0x00305070, 0x00000077 }, + { 0x0030B070, 0x000000FF }, + { 0x0030C070, 0x00000077 }, + { 0x00000005, 0x00000003 }, + { 0x00001005, 0x00000003 }, + { 0x00002005, 0x00000003 }, + { 0x00003005, 0x00000003 }, + { 0x00004005, 0x00000003 }, + { 0x00005005, 0x00000003 }, + { 0x00007005, 0x00000003 }, + { 0x00008005, 0x00000003 }, + { 0x00009005, 0x00000003 }, + { 0x0000A005, 0x00000003 }, + { 0x0000B005, 0x00000003 }, + { 0x0000C005, 0x00000003 }, + { 0x000A0308, 0x00000002 }, + { 0x000A0002, 0x00000001 }, + { 0x000E0046, 0x00000006 }, + { 0x000E0047, 0x00000006 }, + { 0x000E0048, 0x00000006 }, + { 0x000E0049, 0x00000006 }, + { 0x000E1046, 0x00000006 }, + { 0x000E1047, 0x00000006 }, + { 0x000E1048, 0x00000006 }, + { 0x000E1049, 0x00000006 }, + { 0x000E104A, 0x00000006 }, + { 0x000E004B, 0x00000006 }, + { 0x000E104B, 0x00000006 }, + { 0x000E2046, 0x00000006 }, + { 0x000E2047, 0x00000006 }, + { 0x000E2048, 0x00000006 }, + { 0x000E2049, 0x00000006 }, + { 0x000E3046, 0x00000006 }, + { 0x000E3047, 0x00000006 }, + { 0x000E3048, 0x00000006 }, + { 0x000E3049, 0x00000006 }, + { 0x000E304A, 0x00000006 }, + { 0x000E204B, 0x00000006 }, + { 0x000E304B, 0x00000006 }, + { 0x000E4046, 0x00000006 }, + { 0x000E4047, 0x00000006 }, + { 0x000E4048, 0x00000006 }, + { 0x000E4049, 0x00000006 }, + { 0x000E5046, 0x00000006 }, + { 0x000E5047, 0x00000006 }, + { 0x000E5048, 0x00000006 }, + { 0x000E5049, 0x00000006 }, + { 0x000E504A, 0x00000006 }, + { 0x000E404B, 0x00000006 }, + { 0x000E504B, 0x00000006 }, + { 0x000E6046, 0x00000006 }, + { 0x000E6047, 0x00000006 }, + { 0x000E6048, 0x00000006 }, + { 0x000E6049, 0x00000006 }, + { 0x000E7046, 0x00000006 }, + { 0x000E7047, 0x00000006 }, + { 0x000E7048, 0x00000006 }, + { 0x000E7049, 0x00000006 }, + { 0x000E704A, 0x00000006 }, + { 0x000E604B, 0x00000006 }, + { 0x000E704B, 0x00000006 }, + { 0x00030020, 0x00000001 }, + { 0x00031020, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab2[] = { + { 0x00000005, 0x00000003 }, + { 0x00001005, 0x00000003 }, + { 0x00002005, 0x00000003 }, + { 0x00003005, 0x00000003 }, + { 0x00004005, 0x00000003 }, + { 0x00005005, 0x00000003 }, + { 0x00007005, 0x00000003 }, + { 0x00008005, 0x00000003 }, + { 0x00009005, 0x00000003 }, + { 0x0000A005, 0x00000003 }, + { 0x0000B005, 0x00000003 }, + { 0x0000C005, 0x00000003 }, + { 0x000A0308, 0x00000000 }, + { 0x000A0002, 0x00000001 }, + { 0x000E0046, 0x00000000 }, + { 0x000E0047, 0x00000000 }, + { 0x000E0048, 0x00000000 }, + { 0x000E0049, 0x00000000 }, + { 0x000E1046, 0x00000000 }, + { 0x000E1047, 0x00000000 }, + { 0x000E1048, 0x00000000 }, + { 0x000E1049, 0x00000000 }, + { 0x000E104A, 0x00000000 }, + { 0x000E004B, 0x00000002 }, + { 0x000E104B, 0x00000004 }, + { 0x000E2046, 0x00000000 }, + { 0x000E2047, 0x00000000 }, + { 0x000E2048, 0x00000000 }, + { 0x000E2049, 0x00000000 }, + { 0x000E3046, 0x00000000 }, + { 0x000E3047, 0x00000000 }, + { 0x000E3048, 0x00000000 }, + { 0x000E3049, 0x00000000 }, + { 0x000E304A, 0x00000000 }, + { 0x000E204B, 0x00000002 }, + { 0x000E304B, 0x00000004 }, + { 0x000E4046, 0x00000000 }, + { 0x000E4047, 0x00000000 }, + { 0x000E4048, 0x00000000 }, + { 0x000E4049, 0x00000000 }, + { 0x000E5046, 0x00000000 }, + { 0x000E5047, 0x00000000 }, + { 0x000E5048, 0x00000000 }, + { 0x000E5049, 0x00000000 }, + { 0x000E504A, 0x00000000 }, + { 0x000E404B, 0x00000002 }, + { 0x000E504B, 0x00000004 }, + { 0x000E6046, 0x00000000 }, + { 0x000E6047, 0x00000000 }, + { 0x000E6048, 0x00000000 }, + { 0x000E6049, 0x00000000 }, + { 0x000E7046, 0x00000000 }, + { 0x000E7047, 0x00000000 }, + { 0x000E7048, 0x00000000 }, + { 0x000E7049, 0x00000000 }, + { 0x000E704A, 0x00000000 }, + { 0x000E604B, 0x00000002 }, + { 0x000E704B, 0x00000004 }, + { 0x000200A5, 0x00000001 }, + { 0x00010097, 0x000007FF }, + { 0x00011097, 0x000007FF }, + { 0x00012097, 0x000007FF }, + { 0x00013097, 0x000007FF }, + { 0x0001003F, 0x00000001 }, + { 0x0001003F, 0x00000000 }, + { 0x0001103F, 0x00000001 }, + { 0x0001103F, 0x00000000 }, + { 0x0001203F, 0x00000001 }, + { 0x0001203F, 0x00000000 }, + { 0x0001303F, 0x00000001 }, + { 0x0001303F, 0x00000000 }, + { 0x000B0303, 0x00000009 }, + { 0x000A0302, 0x00000026 }, + { 0x000B0301, 0x00000000 }, + { 0x000B030F, 0x0000001D }, + { 0x00070067, 0x00000000 }, + { 0x000700E7, 0x00000000 }, + { 0x000300AE, 0x00001A80 }, + { 0x000300AD, 0x00001A80 }, + { 0x000300AC, 0x00001A80 }, + { 0x000310AE, 0x00001A80 }, + { 0x000310AD, 0x00001A80 }, + { 0x000310AC, 0x00001A80 }, + { 0x000100A3, 0x00000911 }, + { 0x000110A3, 0x0000091D }, + { 0x000120A3, 0x00000911 }, + { 0x000130A3, 0x0000091D }, + { 0x000C00F0, 0x00000001 }, + { 0x000C00F1, 0x00000002 }, + { 0x000C00F2, 0x00000007 }, + { 0x000C00F3, 0x00000034 }, + { 0x00090733, 0x0000002D }, + { 0x000C00F4, 0x00000005 }, + { 0x000C00F7, 0x0000F000 }, + { 0x00090737, 0x00000A00 }, + { 0x0009071F, 0x00000004 }, + { 0x00090829, 0x0000000F }, + { 0x00020007, 0x00000000 }, + { 0x000E007A, 0x00000000 }, + { 0x000E107A, 0x00000001 }, + { 0x000E207A, 0x00000000 }, + { 0x000E307A, 0x00000001 }, + { 0x000E407A, 0x00000000 }, + { 0x000E507A, 0x00000001 }, + { 0x000E607A, 0x00000000 }, + { 0x000E707A, 0x00000001 }, + { 0x0000061E, 0x00000000 }, + { 0x0000E61E, 0x00000000 }, + { 0x0000161E, 0x00000000 }, + { 0x0000261E, 0x00000000 }, + { 0x0000361E, 0x00000000 }, + { 0x0000461E, 0x00000000 }, + { 0x0000561E, 0x00000000 }, + { 0x0000761E, 0x00000000 }, + { 0x0000861E, 0x00000000 }, + { 0x0000961E, 0x00000000 }, + { 0x0000A61E, 0x00000000 }, + { 0x0000B61E, 0x00000000 }, + { 0x0000C61E, 0x00000000 }, + { 0x00010E1F, 0x00000000 }, + { 0x00011E1F, 0x00000000 }, + { 0x00012E1F, 0x00000000 }, + { 0x00013E1F, 0x00000000 }, + { 0x00030807, 0x0000EE66 }, + { 0x00031807, 0x0000EE66 }, + { 0x00010807, 0x0000EE66 }, + { 0x00011807, 0x0000EE66 }, + { 0x00012807, 0x0000EE66 }, + { 0x00013807, 0x0000EE66 }, + { 0x000300A0, 0x00003FFF }, + { 0x000310A0, 0x00003FFF }, + { 0x00010089, 0x00001FFF }, + { 0x0001008A, 0x000007FF }, + { 0x00011089, 0x00001FFF }, + { 0x0001108A, 0x000007FF }, + { 0x00012089, 0x00001FFF }, + { 0x0001208A, 0x000007FF }, + { 0x00013089, 0x00001FFF }, + { 0x0001308A, 0x000007FF }, + { 0x00020006, 0x0000000F }, + { 0x0002000C, 0x00000000 }, + { 0x000E000D, 0x00000001 }, + { 0x000E100D, 0x00000001 }, + { 0x000E200D, 0x00000001 }, + { 0x000E300D, 0x00000001 }, + { 0x000E400D, 0x00000001 }, + { 0x000E500D, 0x00000001 }, + { 0x000E600D, 0x00000001 }, + { 0x000E700D, 0x00000001 }, + { 0x00030027, 0x00000001 }, + { 0x0000003F, 0x00000001 }, + { 0x0000103F, 0x00000001 }, + { 0x0000203F, 0x00000001 }, + { 0x0000303F, 0x00000001 }, + { 0x0000403F, 0x00000001 }, + { 0x0000503F, 0x00000001 }, + { 0x00031027, 0x00000001 }, + { 0x0000703F, 0x00000001 }, + { 0x0000803F, 0x00000001 }, + { 0x0000903F, 0x00000001 }, + { 0x0000A03F, 0x00000001 }, + { 0x0000B03F, 0x00000001 }, + { 0x0000C03F, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab3[] = { + { 0x0002008B, 0x00000000 }, + { 0x000A03FF, 0x00004101 }, + { 0x000A030B, 0x00000000 }, + { 0x00060008, 0x00000E9A }, + { 0x00020002, 0x00000007 }, + { 0x00060040, 0x00000007 }, + { 0x00020000, 0x00000002 }, + { 0x000100FB, 0x00000000 }, + { 0x000110FB, 0x00000000 }, + { 0x000120FB, 0x00000000 }, + { 0x000130FB, 0x00000000 }, + { 0x00010024, 0x00000200 }, + { 0x00011024, 0x00000200 }, + { 0x00012024, 0x00000200 }, + { 0x00013024, 0x00000200 }, + { 0x00010025, 0x0000002C }, + { 0x00011025, 0x0000002C }, + { 0x00012025, 0x0000002C }, + { 0x00013025, 0x0000002C }, + { 0x00010004, 0x00000000 }, + { 0x00010003, 0x00000000 }, + { 0x00011004, 0x00000000 }, + { 0x00011003, 0x00000000 }, + { 0x00012004, 0x00000000 }, + { 0x00012003, 0x00000000 }, + { 0x00013004, 0x00000000 }, + { 0x00013003, 0x00000000 }, + { 0x000B0004, 0x0000042A }, + { 0x000A030C, 0x00000000 }, + { 0x0001003E, 0x00000005 }, + { 0x0001103E, 0x00000005 }, + { 0x0001203E, 0x00000005 }, + { 0x0001303E, 0x00000005 }, + { 0x00020003, 0x00000001 }, + { 0x0002000B, 0x00001111 }, + { 0x00010108, 0x00000000 }, + { 0x00011108, 0x00000000 }, + { 0x00012108, 0x00000000 }, + { 0x00013108, 0x00000000 }, + { 0x00070005, 0x00000003 }, + { 0x0007000F, 0x00000000 }, + { 0x0001000E, 0x00001301 }, + { 0x0001100E, 0x00001301 }, + { 0x0001200E, 0x00001301 }, + { 0x0001300E, 0x00001301 }, + { 0x00020019, 0x00000004 }, + { 0x00000070, 0x00000077 }, + { 0x00001070, 0x00000077 }, + { 0x00002070, 0x00000077 }, + { 0x00003070, 0x00000077 }, + { 0x00004070, 0x000000FF }, + { 0x00005070, 0x00000077 }, + { 0x00007070, 0x00000077 }, + { 0x00008070, 0x00000077 }, + { 0x00009070, 0x00000077 }, + { 0x0000A070, 0x00000077 }, + { 0x0000B070, 0x000000FF }, + { 0x0000C070, 0x00000077 }, + { 0x00000079, 0x00000030 }, + { 0x00001079, 0x00000030 }, + { 0x00002079, 0x00000030 }, + { 0x00003079, 0x00000030 }, + { 0x00004079, 0x00000030 }, + { 0x00005079, 0x00000030 }, + { 0x00007079, 0x00000030 }, + { 0x00008079, 0x00000030 }, + { 0x00009079, 0x00000030 }, + { 0x0000A079, 0x00000030 }, + { 0x0000B079, 0x00000030 }, + { 0x0000C079, 0x00000030 }, + { 0x0000006D, 0x00000000 }, + { 0x0000106D, 0x00000000 }, + { 0x0000206D, 0x00000000 }, + { 0x0000306D, 0x00000000 }, + { 0x0000406D, 0x00000000 }, + { 0x0000506D, 0x00000000 }, + { 0x0000706D, 0x00000000 }, + { 0x0000806D, 0x00000000 }, + { 0x0000906D, 0x00000000 }, + { 0x0000A06D, 0x00000000 }, + { 0x0000B06D, 0x00000000 }, + { 0x0000C06D, 0x00000000 }, + { 0x00010001, 0x00000000 }, + { 0x00011001, 0x00000000 }, + { 0x00012001, 0x00000000 }, + { 0x00013001, 0x00000000 }, + { 0x00070040, 0x00000050 }, + { 0x00070041, 0x0000000F }, + { 0x000100A5, 0x00000001 }, + { 0x000110A5, 0x00000001 }, + { 0x000120A5, 0x00000001 }, + { 0x000130A5, 0x00000001 }, + { 0x00010209, 0x00003232 }, + { 0x00011209, 0x00003232 }, + { 0x00012209, 0x00003232 }, + { 0x00013209, 0x00003232 }, + { 0x0001020F, 0x00000006 }, + { 0x0001120F, 0x00000006 }, + { 0x0001220F, 0x00000006 }, + { 0x0001320F, 0x00000006 }, + { 0x00020005, 0x00001111 }, + { 0x00010008, 0x00000001 }, + { 0x00011008, 0x00000001 }, + { 0x00012008, 0x00000001 }, + { 0x00013008, 0x00000001 }, + { 0x0007006B, 0x00000111 }, + { 0x00070066, 0x00000A10 }, + { 0x000700EB, 0x00000111 }, + { 0x000700E6, 0x00000A10 }, + { 0x00030008, 0x00000000 }, + { 0x00031008, 0x00000000 }, + { 0x000005E3, 0x00000004 }, + { 0x000015E3, 0x00000004 }, + { 0x000025E3, 0x00000004 }, + { 0x000035E3, 0x00000004 }, + { 0x000045E3, 0x00000004 }, + { 0x000055E3, 0x00000004 }, + { 0x000075E3, 0x00000004 }, + { 0x000085E3, 0x00000004 }, + { 0x000095E3, 0x00000004 }, + { 0x0000A5E3, 0x00000004 }, + { 0x0000B5E3, 0x00000004 }, + { 0x0000C5E3, 0x00000004 }, + { 0x000E05E3, 0x00000004 }, + { 0x000E15E3, 0x00000004 }, + { 0x000E25E3, 0x00000004 }, + { 0x000E35E3, 0x00000004 }, + { 0x000E45E3, 0x00000004 }, + { 0x000E55E3, 0x00000004 }, + { 0x000E65E3, 0x00000004 }, + { 0x000E75E3, 0x00000004 }, + { 0x0000050A, 0x00000001 }, + { 0x0000150A, 0x00000001 }, + { 0x0000250A, 0x00000001 }, + { 0x0000350A, 0x00000001 }, + { 0x0000450A, 0x00000001 }, + { 0x0000550A, 0x00000001 }, + { 0x0000750A, 0x00000001 }, + { 0x0000850A, 0x00000001 }, + { 0x0000950A, 0x00000001 }, + { 0x0000A50A, 0x00000001 }, + { 0x0000B50A, 0x00000001 }, + { 0x0000C50A, 0x00000001 }, + { 0x0001080B, 0x00000001 }, + { 0x0001180B, 0x00000001 }, + { 0x0001280B, 0x00000001 }, + { 0x0001380B, 0x00000001 }, + { 0x00030803, 0x0000108A }, + { 0x00031803, 0x0000108A }, + { 0x00010803, 0x0000108A }, + { 0x00011803, 0x0000108A }, + { 0x00012803, 0x0000108A }, + { 0x00013803, 0x0000108A }, + { 0x00000503, 0x0000002B }, + { 0x00001503, 0x0000002B }, + { 0x00002503, 0x0000002B }, + { 0x00003503, 0x0000002B }, + { 0x00004503, 0x0000002B }, + { 0x00005503, 0x0000002B }, + { 0x00007503, 0x0000002B }, + { 0x00008503, 0x0000002B }, + { 0x00009503, 0x0000002B }, + { 0x0000A503, 0x0000002B }, + { 0x0000B503, 0x0000002B }, + { 0x0000C503, 0x0000002B }, + { 0x00010C03, 0x0000002B }, + { 0x00011C03, 0x0000002B }, + { 0x00012C03, 0x0000002B }, + { 0x00013C03, 0x0000002B }, + { 0x00000110, 0x0000001F }, + { 0x00001110, 0x0000001F }, + { 0x00002110, 0x0000001F }, + { 0x00003110, 0x0000001F }, + { 0x00004110, 0x0000001F }, + { 0x00005110, 0x0000001F }, + { 0x00007110, 0x0000001F }, + { 0x00008110, 0x0000001F }, + { 0x00009110, 0x0000001F }, + { 0x0000A110, 0x0000001F }, + { 0x0000B110, 0x0000001F }, + { 0x0000C110, 0x0000001F }, + { 0x000E0110, 0x0000001F }, + { 0x000E1110, 0x0000001F }, + { 0x000E2110, 0x0000001F }, + { 0x000E3110, 0x0000001F }, + { 0x000E4110, 0x0000001F }, + { 0x000E5110, 0x0000001F }, + { 0x000E6110, 0x0000001F }, + { 0x000E7110, 0x0000001F }, + { 0x0001010B, 0x00000003 }, + { 0x0001110B, 0x00000003 }, + { 0x0001210B, 0x00000003 }, + { 0x0001310B, 0x00000003 }, + { 0x00000063, 0x0000004E }, + { 0x00001063, 0x0000004E }, + { 0x00002063, 0x0000004E }, + { 0x00003063, 0x0000004E }, + { 0x00004063, 0x0000004E }, + { 0x00005063, 0x0000004E }, + { 0x00007063, 0x0000004E }, + { 0x00008063, 0x0000004E }, + { 0x00009063, 0x0000004E }, + { 0x0000A063, 0x0000004E }, + { 0x0000B063, 0x0000004E }, + { 0x0000C063, 0x0000004E }, + { 0x000E0063, 0x0000004E }, + { 0x000E0064, 0x0000004E }, + { 0x000E0087, 0x0000004E }, + { 0x000E1063, 0x0000004E }, + { 0x000E1064, 0x0000004E }, + { 0x000E1087, 0x0000004E }, + { 0x000E2063, 0x0000004E }, + { 0x000E2064, 0x0000004E }, + { 0x000E2087, 0x0000004E }, + { 0x000E3063, 0x0000004E }, + { 0x000E3064, 0x0000004E }, + { 0x000E3087, 0x0000004E }, + { 0x000E4063, 0x0000004E }, + { 0x000E4064, 0x0000004E }, + { 0x000E4087, 0x0000004E }, + { 0x000E5063, 0x0000004E }, + { 0x000E5064, 0x0000004E }, + { 0x000E5087, 0x0000004E }, + { 0x000E6063, 0x0000004E }, + { 0x000E6064, 0x0000004E }, + { 0x000E6087, 0x0000004E }, + { 0x000E7063, 0x0000004E }, + { 0x000E7064, 0x0000004E }, + { 0x000E7087, 0x0000004E }, + { 0x000C0080, 0x00000007 }, + { 0x000300EB, 0x00000000 }, + { 0x000310EB, 0x00000000 } +}; + +static const struct phyinitdata cpu_trans_tab4[] = { + { 0x000B0310, 0x00000001 }, + { 0x000B0311, 0x00000001 }, + { 0x00060008, 0x00000D56 }, + { 0x00060006, 0x000003F0 }, + { 0x00010075, 0x00000001 }, + { 0x00011075, 0x00000001 }, + { 0x00012075, 0x00000001 }, + { 0x00013075, 0x00000001 }, + { 0x00030015, 0x00000000 }, + { 0x00031015, 0x00000000 }, + { 0x0001007C, 0x00000000 }, + { 0x0001107C, 0x00000000 }, + { 0x0001207C, 0x00000000 }, + { 0x0001307C, 0x00000000 }, + { 0x00070141, 0x00000000 }, + { 0x000B0001, 0x00000003 }, + { 0x0009080C, 0x00000003 }, + { 0x00010027, 0x00000001 }, + { 0x00011027, 0x00000001 }, + { 0x00012027, 0x00000001 }, + { 0x00013027, 0x00000001 }, + { 0x0001020F, 0x00000009 }, + { 0x0001120F, 0x00000009 }, + { 0x0001220F, 0x00000009 }, + { 0x0001320F, 0x00000009 }, + { 0x000E003F, 0x00000001 }, + { 0x000E008D, 0x00000001 }, + { 0x000E103F, 0x00000001 }, + { 0x000E108D, 0x00000001 }, + { 0x000E203F, 0x00000001 }, + { 0x000E208D, 0x00000001 }, + { 0x000E303F, 0x00000001 }, + { 0x000E308D, 0x00000001 }, + { 0x000E403F, 0x00000001 }, + { 0x000E408D, 0x00000001 }, + { 0x000E503F, 0x00000001 }, + { 0x000E508D, 0x00000001 }, + { 0x000E603F, 0x00000001 }, + { 0x000E608D, 0x00000001 }, + { 0x000E703F, 0x00000001 }, + { 0x000E708D, 0x00000001 }, + { 0x00090903, 0x00000000 }, + { 0x00070072, 0x00000001 }, + { 0x0009080E, 0x00000001 }, + { 0x00070073, 0x00000001 }, + { 0x0009080F, 0x00000001 } +}; + +static const struct phyinitdata cpu_trans_tab5[] = { + { 0x00070334, 0x0000011B }, + { 0x00070335, 0x0000011F }, + { 0x00070336, 0x00000121 }, + { 0x00070337, 0x00000122 }, + { 0x00070339, 0x00000123 }, + { 0x0007033A, 0x00000124 }, + { 0x0007033C, 0x00000125 }, + { 0x0007033D, 0x0000013E }, + { 0x0007033E, 0x00000148 }, + { 0x0007033F, 0x00000160 }, + { 0x00070350, 0x00000170 }, + { 0x00070351, 0x00000188 }, + { 0x00070352, 0x00000191 }, + { 0x00070353, 0x000001A3 } +}; + +static const struct phyinitdata cpu_trans_tab6[] = { + { 0x0007039B, 0x0000011E }, + { 0x0007039C, 0x00000120 }, + { 0x0007039D, 0x00000121 }, + { 0x0007039E, 0x00000122 }, + { 0x000703A0, 0x00000123 }, + { 0x000703A1, 0x00000124 }, + { 0x000703A3, 0x0000013D }, + { 0x000703A4, 0x00000147 }, + { 0x000703A5, 0x0000015F }, + { 0x000703A6, 0x0000016F }, + { 0x000703B7, 0x00000187 }, + { 0x000703B8, 0x00000190 }, + { 0x000703B9, 0x000001A2 }, + { 0x000703BA, 0x000001B3 }, + { 0x00070200, 0x0000040E }, + { 0x00070202, 0x0000044F }, + { 0x00070204, 0x000000C0 }, + { 0x00070205, 0x00000246 }, + { 0x00070206, 0x00000101 }, + { 0x00070207, 0x00000287 }, + { 0x00070208, 0x00000142 }, + { 0x00070209, 0x000002C8 }, + { 0x0007020A, 0x00000012 }, + { 0x0007020B, 0x0000034C }, + { 0x0007020C, 0x00000015 }, + { 0x0007020E, 0x00000016 }, + { 0x00070212, 0x0000002C }, + { 0x00070213, 0x00000018 }, + { 0x00070214, 0x0000002D }, + { 0x00070215, 0x00000019 }, + { 0x00070216, 0x0000002E }, + { 0x00070217, 0x0000001A }, + { 0x00070218, 0x0000002F }, + { 0x00070219, 0x0000001B }, + { 0x0007021A, 0x00000013 }, + { 0x0009001C, 0x00000267 }, + { 0x0009001D, 0x00000267 }, + { 0x0009001E, 0x00000267 }, + { 0x0009001F, 0x00000267 }, + { 0x00090020, 0x000002A0 }, + { 0x00090021, 0x00000267 }, + { 0x00090022, 0x00000000 }, + { 0x00090023, 0x00000000 }, + { 0x00090024, 0x00000000 }, + { 0x00090025, 0x00000000 }, + { 0x00090026, 0x00000000 }, + { 0x00090027, 0x00000000 }, + { 0x0009002B, 0x0000029D }, + { 0x00070145, 0x00000004 } +}; + +static const struct phyinitdata cpu_trans_tab7[] = { + { 0x000700F0, 0x00000B6D }, + { 0x000100B9, 0x00000001 }, + { 0x000100B1, 0x00000180 }, + { 0x000100BA, 0x00000001 }, + { 0x000100A2, 0x00000000 }, + { 0x000100B5, 0x00000001 }, + { 0x00010E2B, 0x00005A3C }, + { 0x00010E2A, 0x00005A3C }, + { 0x00010E20, 0x00000002 }, + { 0x000110B9, 0x00000001 }, + { 0x000110B1, 0x00000180 }, + { 0x000110BA, 0x00000001 }, + { 0x000110A2, 0x00000000 }, + { 0x000110B5, 0x00000001 }, + { 0x00011E2B, 0x00005A3C }, + { 0x00011E2A, 0x00005A3C }, + { 0x00011E20, 0x00000002 }, + { 0x000120B9, 0x00000001 }, + { 0x000120B1, 0x00000180 }, + { 0x000120BA, 0x00000001 }, + { 0x000120A2, 0x00000000 }, + { 0x000120B5, 0x00000001 }, + { 0x00012E2B, 0x00005A3C }, + { 0x00012E2A, 0x00005A3C }, + { 0x00012E20, 0x00000002 }, + { 0x000130B9, 0x00000001 }, + { 0x000130B1, 0x00000180 }, + { 0x000130BA, 0x00000001 }, + { 0x000130A2, 0x00000000 }, + { 0x000130B5, 0x00000001 }, + { 0x00013E2B, 0x00005A3C }, + { 0x00013E2A, 0x00005A3C }, + { 0x00013E20, 0x00000002 }, + { 0x0007001C, 0x00005A3C }, + { 0x0007001B, 0x00005A3C }, + { 0x00070010, 0x00000002 }, + { 0x0007007E, 0x00000041 }, + { 0x000701EF, 0x00007FFF }, + { 0x000300A6, 0x00000001 }, + { 0x000310A6, 0x00000001 }, + { 0x000701A8, 0x00000000 }, + { 0x00070128, 0x00000000 }, + { 0x00070131, 0x00000000 }, + { 0x00070132, 0x00000000 }, + { 0x00070133, 0x00000000 }, + { 0x00070134, 0x00000000 }, + { 0x00070142, 0x00000000 }, + { 0x00070144, 0x00000000 } +}; + +static const struct phyinitdata cpu_trans_tab3_7500[] = { + { 0x000908E0, 0x00000076 }, + { 0x000908E1, 0x00000160 }, + { 0x000908E2, 0x00000927 }, + { 0x000908E4, 0x00000018 }, + { 0x000908EA, 0x00000005 }, + { 0x000908EB, 0x00000005 }, + { 0x000908EC, 0x0000000C }, + { 0x000908ED, 0x0000005B }, + { 0x000B0004, 0x000003A9 }, + { 0x00070066, 0x00000910 }, + { 0x000700E6, 0x00000910 }, + { 0x00070135, 0x00001410 }, + { 0x00070136, 0x00001410 }, + { 0x00070137, 0x00000424 }, + { 0x00070138, 0x00001928 }, + { 0x00070139, 0x00001418 }, + { 0x0007013A, 0x00001418 }, + { 0x0007013B, 0x0000042C }, + { 0x0007013C, 0x00003530 }, + { 0x0007013D, 0x00001408 }, + { 0x0007013E, 0x00001408 }, + { 0x0007013F, 0x0000041C }, + { 0x00070140, 0x00001120 }, + { 0x0007012C, 0x00000843 }, + { 0x0007012D, 0x00000843 }, + { 0x00070130, 0x00000843 }, + { 0x0007012E, 0x00000827 }, + { 0x0007012F, 0x00000827 }, + { 0x00030803, 0x0000107A }, + { 0x00031803, 0x0000107A }, + { 0x00010803, 0x0000107A }, + { 0x00011803, 0x0000107A }, + { 0x00012803, 0x0000107A }, + { 0x00013803, 0x0000107A }, + { 0x00000503, 0x00000027 }, + { 0x00001503, 0x00000027 }, + { 0x00002503, 0x00000027 }, + { 0x00003503, 0x00000027 }, + { 0x00004503, 0x00000027 }, + { 0x00005503, 0x00000027 }, + { 0x00007503, 0x00000027 }, + { 0x00008503, 0x00000027 }, + { 0x00009503, 0x00000027 }, + { 0x0000A503, 0x00000027 }, + { 0x0000B503, 0x00000027 }, + { 0x0000C503, 0x00000027 }, + { 0x00010C03, 0x00000027 }, + { 0x00011C03, 0x00000027 }, + { 0x00012C03, 0x00000027 }, + { 0x00013C03, 0x00000027 }, + { 0x000908E8, 0x00000015 }, + { 0x000908E9, 0x00000048 }, + { 0x00000063, 0x00000058 }, + { 0x00001063, 0x00000058 }, + { 0x00002063, 0x00000058 }, + { 0x00003063, 0x00000058 }, + { 0x00004063, 0x00000058 }, + { 0x00005063, 0x00000058 }, + { 0x00007063, 0x00000058 }, + { 0x00008063, 0x00000058 }, + { 0x00009063, 0x00000058 }, + { 0x0000A063, 0x00000058 }, + { 0x0000B063, 0x00000058 }, + { 0x0000C063, 0x00000058 }, + { 0x0009080A, 0x00000258 }, + { 0x0009080B, 0x00000058 }, + { 0x00090815, 0x00000258 }, + { 0x00090816, 0x00000058 }, + { 0x000E0063, 0x00000058 }, + { 0x000E0064, 0x00000058 }, + { 0x000E0087, 0x00000058 }, + { 0x000E1063, 0x00000058 }, + { 0x000E1064, 0x00000058 }, + { 0x000E1087, 0x00000058 }, + { 0x000E2063, 0x00000058 }, + { 0x000E2064, 0x00000058 }, + { 0x000E2087, 0x00000058 }, + { 0x000E3063, 0x00000058 }, + { 0x000E3064, 0x00000058 }, + { 0x000E3087, 0x00000058 }, + { 0x000E4063, 0x00000058 }, + { 0x000E4064, 0x00000058 }, + { 0x000E4087, 0x00000058 }, + { 0x000E5063, 0x00000058 }, + { 0x000E5064, 0x00000058 }, + { 0x000E5087, 0x00000058 }, + { 0x000E6063, 0x00000058 }, + { 0x000E6064, 0x00000058 }, + { 0x000E6087, 0x00000058 }, + { 0x000E7063, 0x00000058 }, + { 0x000E7064, 0x00000058 }, + { 0x000E7087, 0x00000058 }, + { 0x00090817, 0x00000061 } +}; + +static const struct phyinitdata cpu_trans_tab3_9600[] = { + { 0x000908E0, 0x00000096 }, + { 0x000908E1, 0x000001C2 }, + { 0x000908E2, 0x00000BB8 }, + { 0x000908E4, 0x0000001E }, + { 0x000908EC, 0x0000000F }, + { 0x000908ED, 0x00000075 }, + { 0x000B0004, 0x000004B0 }, + { 0x00070066, 0x00000B10 }, + { 0x000700E6, 0x00000B10 }, + { 0x00070135, 0x00001C14 }, + { 0x00070136, 0x00001C14 }, + { 0x00070137, 0x00000430 }, + { 0x00070138, 0x00001934 }, + { 0x00070139, 0x00001C1C }, + { 0x0007013A, 0x00001C1C }, + { 0x0007013B, 0x00000438 }, + { 0x0007013C, 0x00003D3C }, + { 0x0007013D, 0x00001C08 }, + { 0x0007013E, 0x00001C08 }, + { 0x0007013F, 0x00000424 }, + { 0x00070140, 0x00001128 }, + { 0x0007012C, 0x00000857 }, + { 0x0007012D, 0x00000857 }, + { 0x00070130, 0x00000857 }, + { 0x0007012E, 0x00000833 }, + { 0x0007012F, 0x00000833 }, + { 0x00030803, 0x0000109A }, + { 0x00031803, 0x0000109A }, + { 0x00010803, 0x0000109A }, + { 0x00011803, 0x0000109A }, + { 0x00012803, 0x0000109A }, + { 0x00013803, 0x0000109A }, + { 0x00000503, 0x0000002F }, + { 0x00001503, 0x0000002F }, + { 0x00002503, 0x0000002F }, + { 0x00003503, 0x0000002F }, + { 0x00004503, 0x0000002F }, + { 0x00005503, 0x0000002F }, + { 0x00007503, 0x0000002F }, + { 0x00008503, 0x0000002F }, + { 0x00009503, 0x0000002F }, + { 0x0000A503, 0x0000002F }, + { 0x0000B503, 0x0000002F }, + { 0x0000C503, 0x0000002F }, + { 0x00010C03, 0x0000002F }, + { 0x00011C03, 0x0000002F }, + { 0x00012C03, 0x0000002F }, + { 0x00013C03, 0x0000002F }, + { 0x000908E8, 0x00000019 }, + { 0x000908E9, 0x00000056 }, + { 0x00000063, 0x00000045 }, + { 0x00001063, 0x00000045 }, + { 0x00002063, 0x00000045 }, + { 0x00003063, 0x00000045 }, + { 0x00004063, 0x00000045 }, + { 0x00005063, 0x00000045 }, + { 0x00007063, 0x00000045 }, + { 0x00008063, 0x00000045 }, + { 0x00009063, 0x00000045 }, + { 0x0000A063, 0x00000045 }, + { 0x0000B063, 0x00000045 }, + { 0x0000C063, 0x00000045 }, + { 0x0009080A, 0x00000245 }, + { 0x0009080B, 0x00000045 }, + { 0x00090815, 0x00000245 }, + { 0x00090816, 0x00000045 }, + { 0x000E0063, 0x00000045 }, + { 0x000E0064, 0x00000045 }, + { 0x000E0087, 0x00000045 }, + { 0x000E1063, 0x00000045 }, + { 0x000E1064, 0x00000045 }, + { 0x000E1087, 0x00000045 }, + { 0x000E2063, 0x00000045 }, + { 0x000E2064, 0x00000045 }, + { 0x000E2087, 0x00000045 }, + { 0x000E3063, 0x00000045 }, + { 0x000E3064, 0x00000045 }, + { 0x000E3087, 0x00000045 }, + { 0x000E4063, 0x00000045 }, + { 0x000E4064, 0x00000045 }, + { 0x000E4087, 0x00000045 }, + { 0x000E5063, 0x00000045 }, + { 0x000E5064, 0x00000045 }, + { 0x000E5087, 0x00000045 }, + { 0x000E6063, 0x00000045 }, + { 0x000E6064, 0x00000045 }, + { 0x000E6087, 0x00000045 }, + { 0x000E7063, 0x00000045 }, + { 0x000E7064, 0x00000045 }, + { 0x000E7087, 0x00000045 }, + { 0x00090817, 0x0000007D } +}; + +static const struct phyinitdata cpu_trans_tab3_6400[] = { + { 0x00060008, 0x00002E9A }, + { 0x000908E0, 0x00000064 }, + { 0x000908E1, 0x0000012C }, + { 0x000908E2, 0x000007D0 }, + { 0x000908E4, 0x00000014 }, + { 0x000908EA, 0x00000004 }, + { 0x000908EB, 0x00000004 }, + { 0x000908EC, 0x0000000A }, + { 0x000908ED, 0x0000004E }, + { 0x000B0004, 0x00000320 }, + { 0x00070066, 0x00000810 }, + { 0x000700E6, 0x00000810 }, + { 0x00070135, 0x0000100C }, + { 0x00070136, 0x0000100C }, + { 0x00070137, 0x0000041C }, + { 0x00070138, 0x00001920 }, + { 0x00070139, 0x00001018 }, + { 0x0007013A, 0x00001018 }, + { 0x0007013B, 0x00000428 }, + { 0x0007013C, 0x00002D2C }, + { 0x0007013D, 0x00001004 }, + { 0x0007013E, 0x00001004 }, + { 0x0007013F, 0x00000414 }, + { 0x00070140, 0x00001118 }, + { 0x0007012C, 0x00000837 }, + { 0x0007012D, 0x00000837 }, + { 0x00070130, 0x00000837 }, + { 0x0007012E, 0x0000081F }, + { 0x0007012F, 0x0000081F }, + { 0x00030803, 0x0000107A }, + { 0x00031803, 0x0000107A }, + { 0x00010803, 0x0000107A }, + { 0x00011803, 0x0000107A }, + { 0x00012803, 0x0000107A }, + { 0x00013803, 0x0000107A }, + { 0x00000503, 0x00000023 }, + { 0x00001503, 0x00000023 }, + { 0x00002503, 0x00000023 }, + { 0x00003503, 0x00000023 }, + { 0x00004503, 0x00000023 }, + { 0x00005503, 0x00000023 }, + { 0x00007503, 0x00000023 }, + { 0x00008503, 0x00000023 }, + { 0x00009503, 0x00000023 }, + { 0x0000A503, 0x00000023 }, + { 0x0000B503, 0x00000023 }, + { 0x0000C503, 0x00000023 }, + { 0x00010C03, 0x00000023 }, + { 0x00011C03, 0x00000023 }, + { 0x00012C03, 0x00000023 }, + { 0x00013C03, 0x00000023 }, + { 0x000908E8, 0x00000015 }, + { 0x000908E9, 0x00000048 }, + { 0x00000063, 0x00000068 }, + { 0x00001063, 0x00000068 }, + { 0x00002063, 0x00000068 }, + { 0x00003063, 0x00000068 }, + { 0x00004063, 0x00000068 }, + { 0x00005063, 0x00000068 }, + { 0x00007063, 0x00000068 }, + { 0x00008063, 0x00000068 }, + { 0x00009063, 0x00000068 }, + { 0x0000A063, 0x00000068 }, + { 0x0000B063, 0x00000068 }, + { 0x0000C063, 0x00000068 }, + { 0x0009080A, 0x00000268 }, + { 0x0009080B, 0x00000068 }, + { 0x00090815, 0x00000268 }, + { 0x00090816, 0x00000068 }, + { 0x000E0063, 0x00000068 }, + { 0x000E0064, 0x00000068 }, + { 0x000E0087, 0x00000068 }, + { 0x000E1063, 0x00000068 }, + { 0x000E1064, 0x00000068 }, + { 0x000E1087, 0x00000068 }, + { 0x000E2063, 0x00000068 }, + { 0x000E2064, 0x00000068 }, + { 0x000E2087, 0x00000068 }, + { 0x000E3063, 0x00000068 }, + { 0x000E3064, 0x00000068 }, + { 0x000E3087, 0x00000068 }, + { 0x000E4063, 0x00000068 }, + { 0x000E4064, 0x00000068 }, + { 0x000E4087, 0x00000068 }, + { 0x000E5063, 0x00000068 }, + { 0x000E5064, 0x00000068 }, + { 0x000E5087, 0x00000068 }, + { 0x000E6063, 0x00000068 }, + { 0x000E6064, 0x00000068 }, + { 0x000E6087, 0x00000068 }, + { 0x000E7063, 0x00000068 }, + { 0x000E7064, 0x00000068 }, + { 0x000E7087, 0x00000068 }, + { 0x00090817, 0x00000053 } +}; + +static const u32 DMAC_TRANS_ICCM[] = { + 0x0000058C, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000090, 0x00000090, 0x00000090, 0x00000090, + 0x00000050, 0x00000050, 0x00000050, 0x00000050, + 0x7000264A, 0x7000264A, 0x7000264A, 0x7000264A, + 0x00402069, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0xC0D1C0F1, 0x00007EE0, 0xC0D1C0F1, 0x00007EE0, + 0x0F80220A, 0x00008000, 0x0F80230A, 0xDEAD1234, + 0x00C01A00, 0x23AA7444, 0x1A000010, 0x744400C0, + 0x00D023AA, 0x00C01A00, 0x1A007444, 0x74440000, + 0x00401A00, 0x1A007444, 0x74440700, 0x06C01A00, + 0x230A7444, 0xABCD0F80, 0x1A00DEAD, 0x206900C0, + 0x78E00040, 0x803C2242, 0x42007CE0, 0x018020A8, + 0x04831101, 0x00D21A01, 0x78E07EE0, 0x803C2242, + 0x42007CE0, 0x010020A8, 0x00521A01, 0x78E07EE0, + 0xB6881CFC, 0xB6481CFC, 0xB6081CFC, 0xB5C81CFC, + 0xB5881CFC, 0xB5481CFC, 0xB5081CFC, 0xB4C81CFC, + 0xB4881CFC, 0xB4481CFC, 0xB4081CFC, 0xB3C81CFC, + 0xB3881CFC, 0x1CFC7FE0, 0x78E0B348, 0x78E07EE0, + 0xDD38748D, 0x78E0F038, 0xDD34748D, 0x78E0F036, + 0xDD30748D, 0x78E0F034, 0xDD2C748D, 0x78E0F032, + 0xDD28748D, 0x78E0F030, 0xDD24748D, 0x78E0F02E, + 0xDD20748D, 0x78E0F02C, 0xDD1C748D, 0x78E0F02A, + 0xDD18748D, 0x78E0F028, 0xDD14748D, 0x78E0F026, + 0xDD10748D, 0x78E0F024, 0xDD0C748D, 0x78E0F022, + 0xDD08748D, 0x78E0F01F, 0x74AD748D, 0x78E0F01C, + 0xF01C748D, 0x301A1434, 0x30191430, 0x3018142C, + 0x30171428, 0x30161424, 0x30151420, 0x3014141C, + 0x30131418, 0x30121414, 0x30111410, 0x3010140C, + 0xC601C702, 0x334D24B0, 0x331F24B0, 0x78E07EE0, + 0x1CFCC4C1, 0x1CFCB1C8, 0x1CFCB188, 0x1CFCB148, + 0xC3E1B108, 0xC1E1C2E1, 0xC4E1C0E1, 0xC0017FE0, + 0x0A11C2F0, 0x42300032, 0x0081292F, 0xF00369E1, + 0x280070ED, 0x274E03D1, 0x2A011800, 0x70F52000, + 0x03D02A00, 0x200921C5, 0x240E2841, 0x0AB24022, + 0x41C10020, 0x23C22A00, 0x000042D3, 0x4508FFFF, + 0xBA307F50, 0x2408232F, 0x20542240, 0x23640A13, + 0x04002940, 0x14C3251A, 0x080F6058, 0x61D900C5, + 0x852409ED, 0x294077A5, 0x251A2411, 0x72221400, + 0x0A6E4A10, 0x41C10020, 0x0A154300, 0x294020E4, + 0x231A0400, 0x60F804C2, 0x0085080D, 0x09EF61D9, + 0x77648524, 0x14002D40, 0x2000BD30, 0x254180C0, + 0xC6D09001, 0xEB884408, 0x00A5090D, 0x07554020, + 0x4181FFEF, 0x00200071, 0x78E04081, 0x4548C2E8, + 0x44084220, 0x41407034, 0x700CF646, 0x900C240E, + 0x80812003, 0x00330B11, 0x700C4668, 0x900D250E, + 0x80CE2003, 0x07CF2B41, 0x07D02A41, 0x0917EE8B, + 0x40200365, 0x42A14181, 0x2007FFC2, 0xF40EA3FE, + 0x4081C6C8, 0x082242A1, 0x43C10020, 0xA3FE2007, + 0x2505F3F8, 0xF3F693BE, 0x200E704C, 0x22038080, + 0xC6C88041, 0x00200031, 0x78E0708C, 0x00C42107, + 0xF040262F, 0x001270AC, 0x242F0026, 0x200E0104, + 0x25038140, 0x70740041, 0x0003000C, 0x8142220E, + 0x00C32503, 0x80852305, 0x00010116, 0x44484368, + 0x43204200, 0x82C0250A, 0x001A704D, 0x22C00004, + 0x25CA1821, 0x2F2F8301, 0x22C00141, 0x22C01063, + 0x70EC11C3, 0x80C0250A, 0x082127C0, 0x00040014, + 0x808125CA, 0x0141282F, 0x006327C0, 0x000327C0, + 0x8287270E, 0x002427CA, 0x45E071E4, 0x8800274C, + 0x0012702C, 0x700C0024, 0x42604140, 0x2742706C, + 0x240A8807, 0x002A7140, 0x274E0001, 0x007C880A, + 0x29000001, 0x29010280, 0x2A0001C1, 0x71A00285, + 0x01C22A01, 0x02852B00, 0x01C32B01, 0x224C72A0, + 0x00629800, 0x20A80009, 0x200005C0, 0x21018000, + 0x22018041, 0x23018082, 0x220200C3, 0x23038302, + 0x000E82C3, 0x22000006, 0x23018302, 0x20C082C3, + 0x70940066, 0x002270AC, 0x000E0001, 0x220E000A, + 0x25038142, 0x242F00C3, 0x000E8100, 0x200E0003, + 0x25038140, 0x7EE00041, 0x41404020, 0x706C4260, + 0x20A8F1CF, 0x20000380, 0x21018000, 0x22018041, + 0x72918082, 0x030622C2, 0x006620C5, 0x704CF1DB, + 0x706C6A09, 0x0002212F, 0x78E0F1E7, 0x81422253, + 0x224E7CE0, 0x00168803, 0x2801000C, 0x290000CC, + 0x28000081, 0x7FE00080, 0x234E7985, 0x28000003, + 0x7FE000C1, 0x78E07802, 0x81422253, 0x224E7CE0, + 0x00168803, 0x2900000C, 0x290100CC, 0x28010081, + 0x7FE00080, 0x234E7885, 0x29010003, 0x7FE000C0, + 0x78E07922, 0x00402069, 0xF1FE78E0, 0x0020001D, + 0x78E0700D, 0x87C82941, 0x002221CE, 0x87C32842, + 0x002220CE, 0x10C82007, 0x8040220A, 0x00210050, + 0x700C4100, 0x2D2F6869, 0x25CA8041, 0x2E2F00C4, + 0x26CA8081, 0x260200C4, 0x23CA8143, 0x23400024, + 0x2AC0007C, 0x20A800C3, 0x210202C0, 0x20CF8081, + 0x21C00F06, 0x222F0085, 0x202F0082, 0x202F9202, + 0x20CE0003, 0x7FE00025, 0x002221CE, 0x0F802020, + 0x05740000, 0xF000260A, 0x0FBF208A, 0x006420CA, + 0x202F7FE0, 0x7FE00003, 0x78E0770C, 0x704C702C, + 0x708C706C, 0x70CC70AC, 0x700D70EC, 0x704D702D, + 0x708D706D, 0x70CD70AD, 0x700E70ED, 0x704E702E, + 0x708E706E, 0x70CE70AE, 0x700F70EE, 0x706F702F, + 0x3000254A, 0x3000264A, 0x800144DB, 0x42DB8000, + 0x04008000, 0xFFCF0AB6, 0x05400E52, 0x0719D830, + 0xF1FEFFCF, 0x0C1EC0F1, 0xC1A1FFCF, 0x7487E805, + 0x7FE0C0D1, 0x40C3C0A8, 0x12218000, 0x206F8840, + 0xA84007C3, 0x208C8803, 0xF20D8FC3, 0xC040C084, + 0x08524020, 0xC18409A0, 0xD8FFD911, 0x02600AC2, + 0x0EF6B911, 0xD8FF0960, 0x20AB700C, 0x7FFF00C4, + 0x78E0F1FF, 0x47CBC2F8, 0x11DA8000, 0x10951746, + 0x23784310, 0x40580000, 0x4130781B, 0x2040704E, + 0x23140057, 0x19002556, 0x252F0001, 0x0FAF1487, + 0x72B52364, 0x2FC1208A, 0x20542244, 0x352E089B, + 0x202620CA, 0x70801600, 0x001B8000, 0x800146CB, + 0x08214D64, 0x40C3009E, 0x04868000, 0xE88A8800, + 0x20300B1F, 0x09E67EB4, 0x961200E0, 0xF00D961E, + 0x00E009DA, 0x134026F4, 0x96067EB4, 0x09CEF005, + 0x960C00E0, 0x09D69618, 0x700C00C0, 0x00A00D56, + 0x2C40712C, 0x70AD20CE, 0x23C02632, 0x10250D3B, + 0x21002D40, 0x04C02016, 0xE02460B8, 0x294060E9, + 0x20050380, 0x90040F80, 0x90000234, 0x02600AE6, + 0xB8C6B8C8, 0x200771A5, 0x40260401, 0x782579D8, + 0x20001900, 0x7146F1E2, 0xC6D8F1A9, 0xC1B4C3F6, + 0x16004110, 0x80007080, 0x4750000C, 0x800046CB, + 0x081B11DA, 0x4728003F, 0xF483B8E1, 0x41E14022, + 0x0F0642E2, 0x4380FFEF, 0x1F00C7D6, 0xC0801001, + 0x10951646, 0x800041C3, 0xDA4E0F12, 0xFFEF099A, + 0x700C708E, 0x704C702C, 0x04600B26, 0x42C3706C, + 0xFFFF0000, 0x722C700C, 0x44404340, 0x04600A8A, + 0xC0804540, 0x09E009F6, 0x2114D94E, 0x43D32552, + 0xF8049007, 0x21051B00, 0x208A7296, 0x24442FC1, + 0x0F8B2056, 0x20CA25AE, 0x45CB2026, 0x4D648001, + 0x07800AE2, 0x00E008D6, 0x150025F4, 0x15002514, + 0x00E008DA, 0x218A9006, 0x40C30FCF, 0xC2EC9007, + 0x712CB020, 0x00051800, 0x0C4A700C, 0x70AD00A0, + 0x23802232, 0x2E40E823, 0x2D4020D6, 0x20162100, + 0x60B80440, 0x60C9E024, 0x03802940, 0x0F802005, + 0x26FC9004, 0x208A9040, 0x09DA0FC7, 0x78460260, + 0x71A5B8C6, 0x04002007, 0x05812800, 0x78258700, + 0x2232A700, 0x0DC72380, 0x71869004, 0xA1140C6D, + 0x70051E00, 0x0004901C, 0x20051B00, 0x1F00C7D6, + 0x708E1001, 0x10931646, 0x24D22114, 0x208A7296, + 0x24442FC1, 0x0F692055, 0x20CA256E, 0x45CB2026, + 0x4D648001, 0x07800A2E, 0x00E00822, 0x150025F4, + 0x150D2514, 0x00E00826, 0x700C9506, 0x00A00BA6, + 0x2232712C, 0xE81C2380, 0x20D52D40, 0x2B4070AD, + 0x41222100, 0x04402016, 0xE02460B8, 0x076008DA, + 0xB8C660C8, 0x200771A5, 0x28000400, 0x87000541, + 0xA7007825, 0x23802232, 0x90040DD7, 0x0C917186, + 0xF144A114, 0x1CFCC2FA, 0x2482B6C8, 0x710C3E07, + 0x0FDF218A, 0x056008D6, 0xC808704C, 0x3643236F, + 0x685270AD, 0x0F802205, 0x00949004, 0xC0449000, + 0x30801300, 0x80BE2053, 0xC004F20B, 0x0F812205, + 0xC0949007, 0x0080206C, 0x00C02045, 0x2205B100, + 0x90080F80, 0x9040002C, 0x2443276F, 0x17004040, + 0x20842081, 0x217800CC, 0x20B80103, 0x41C30084, + 0x00020190, 0x40C37B04, 0x12DA8000, 0x0FB2A860, + 0x740C0220, 0x702CC08E, 0xFFAF0FC6, 0x0007228A, + 0xA08017F9, 0x019141C3, 0x20440000, 0x1C0C0200, + 0x20783344, 0xC5420000, 0xC540C541, 0xFFEF0C8A, + 0x1713C54B, 0x47CB2081, 0x04848000, 0x01002941, + 0x00DF0815, 0x009F0819, 0x007F081D, 0x1F00710C, + 0xF00D1043, 0x1F00D808, 0xF0091203, 0x1F00740C, + 0xF0051103, 0x1F00720C, 0xB9E21083, 0x800041C3, + 0x20CA0F0C, 0x764C0062, 0x0F3EAF01, 0xC08CFFAF, + 0x712CC08C, 0x07E00822, 0x0E1E714C, 0xC08003A0, + 0x050009A6, 0x46CB700E, 0x12208000, 0x30031C17, + 0x0408202F, 0x2440C187, 0x0B6E3AC2, 0x244003E0, + 0x08C535C3, 0x40C30011, 0x11388000, 0x00431800, + 0x30801417, 0x02E00A56, 0x0F2A4210, 0x142B0400, + 0x17133091, 0xB8E22080, 0x1F024022, 0xF42B1003, + 0x0C1A712C, 0xC28E0820, 0xC18B8E40, 0x3093141C, + 0x019645CB, 0x23140002, 0x61792083, 0xA9004362, + 0x0EAE740C, 0x41A10220, 0x0FFA4042, 0xC18E0260, + 0x702C4022, 0x08200BE6, 0x8E40C28E, 0x1401254F, + 0x0E8E740C, 0x43620220, 0x0FDA4042, 0xC18E0260, + 0xC18EF022, 0x706C714C, 0x0FC1248A, 0x00200C8E, + 0x8E2070AC, 0x2514C527, 0xC18B1042, 0xA9006159, + 0x088E4022, 0xC18E03A0, 0x740C8E40, 0x019441C3, + 0x0E4E0002, 0x43A10220, 0x0F9A4042, 0xC18E0260, + 0x10431F02, 0x202F7106, 0x08290408, 0xC8088114, + 0xDD07708D, 0x20057885, 0x00030F80, 0x0DB6F0D8, + 0x702C0960, 0x258DC808, 0x24561E3F, 0xB802180C, + 0x2005700F, 0x900F0F80, 0x0AF6C364, 0x18000720, + 0x14170604, 0x44D33080, 0x01668000, 0x30192440, + 0x1C00700E, 0x1CFF2FC3, 0xC046AFC3, 0x200CC006, + 0x02A2A000, 0xD9690026, 0x20801713, 0x00FF0821, + 0x0F52D840, 0x43000780, 0x41C3740C, 0x00020199, + 0x02200DBE, 0x228A4202, 0xF00E2001, 0x07A00F36, + 0x4300700C, 0x41C3740C, 0x00020198, 0x02200DA2, + 0x704E4202, 0x28152255, 0x2480260A, 0x203E2680, + 0x7676706E, 0x002D014A, 0x2FC3218A, 0x70AD70CD, + 0x708D706C, 0xC18E4002, 0x0803209A, 0x2B406038, + 0x61192141, 0x1F802604, 0xFFF80000, 0x610AB823, + 0x78C6D807, 0x7918712C, 0x0448202F, 0x8FC3208C, + 0x794BF408, 0xD8FF41A1, 0x41D170AD, 0xF02BF429, + 0xF224794B, 0x218C79D0, 0xF79D8042, 0x79707AB0, + 0x00850933, 0x07800EAE, 0x8F014300, 0x0EA64E10, + 0x781007A0, 0x0E9E4400, 0x404007A0, 0x740C4500, + 0x019B41C3, 0x0D0A0004, 0x42620220, 0x442A8F61, + 0x41A163BB, 0xF005D8FF, 0x40228F21, 0x452861B9, + 0x8F014110, 0x79D0661E, 0x8004218C, 0xFFC50768, + 0x262F7970, 0x2179F348, 0x651D0001, 0x006121C5, + 0x3082120B, 0x80412144, 0x78B0757C, 0x00A5081D, + 0x41C3D80A, 0x0001019F, 0x02000CB6, 0x702C7BAE, + 0x00832B44, 0xF01F710F, 0x70347BAE, 0x00832B44, + 0x144124CA, 0x23002600, 0x262F6078, 0x0016F006, + 0x704C0024, 0x0D137910, 0x25022065, 0x42A22001, + 0x4100F005, 0x702CF003, 0xC0874200, 0x04C02014, + 0x6179B040, 0x2048782E, 0x08170000, 0x780F2030, + 0x20811400, 0x00402009, 0x20021C00, 0x14FFF007, + 0x2009A081, 0x1CFF0040, 0x7166A002, 0x2840F15B, + 0x2440230D, 0xDE073713, 0x2640250A, 0x25001302, + 0x24831501, 0x07A00DAE, 0x44004610, 0x07A00DA6, + 0x45004042, 0x4202750C, 0x01A041C3, 0x0C120004, + 0x41700220, 0x22012940, 0x79A5C808, 0x20057825, + 0x00030F80, 0x0B8E00D8, 0x41C20960, 0x183F268D, + 0x3B112440, 0x24112114, 0x20C01100, 0x20487042, + 0x7E100000, 0x07A00D5E, 0x430040C1, 0x07A00D56, + 0x44004042, 0x41C3750C, 0x000301A1, 0x02200BC2, + 0xC8084202, 0x200578A5, 0x00030F80, 0x0B4608D8, + 0x41C10960, 0x20C01101, 0x20487042, 0x7E100000, + 0x07A00D22, 0x430040C1, 0x07A00D1A, 0x44004042, + 0x41C3750C, 0x000301A2, 0x02200B86, 0xC8084202, + 0x200578A5, 0x00030F80, 0x0B0A09D8, 0x41C10960, + 0x07A00CF2, 0x43004042, 0x41C3750C, 0x000201A3, + 0x02200B5E, 0xC8084202, 0x200578A5, 0x00030F80, + 0x0AE200D9, 0x41420960, 0x31D92140, 0xFFEF0561, + 0x20787106, 0x08423000, 0xB912FFEF, 0x07000822, + 0x07400CD2, 0x20801713, 0x003E0815, 0xB88D700C, + 0x70041E00, 0x00148000, 0x05000EBA, 0x30801300, + 0x80BE2053, 0x0CAEF20B, 0xC8080740, 0x2005B802, + 0x90070F81, 0xC004C094, 0xC08CB100, 0x0BEA712C, + 0x704C07A0, 0x702C700C, 0x05200BA2, 0x2480704C, + 0x14043E07, 0xC6DA341B, 0x47CBC2F4, 0x11DA8000, + 0x10921746, 0x46304550, 0x07600C6A, 0x40C24410, + 0x428241A2, 0x09A00B0A, 0x40C3706C, 0x27100000, + 0x05A00ED2, 0x2453702C, 0x702E2040, 0x00902078, + 0x201470CD, 0x70AD2493, 0x23C02332, 0x10250D4B, + 0x21002A40, 0x04002016, 0xE02460B8, 0x160060E9, + 0x80007080, 0x2053000C, 0xF20780BE, 0x0AFA4020, + 0x41020720, 0x2940F00B, 0x20050380, 0x90040F80, + 0x90000234, 0x02200B4E, 0x2053B8C8, 0x71A581BE, + 0x106226C5, 0x0BEEF1DA, 0x40C20740, 0x428241A2, + 0x09A00A8E, 0x2332DB7F, 0x094D23C0, 0x2A402025, + 0x20162100, 0x70220400, 0x60E9E024, 0x70801600, + 0x000C8000, 0x80BE2053, 0x4020F206, 0x07200A9A, + 0xF00C4102, 0x03802940, 0x0F802005, 0x02349004, + 0x0AF29000, 0xB8C80220, 0x7126B8C6, 0x0FC120B9, + 0xF1DB7E05, 0xC6D478CF, 0xC1A1C3FA, 0xD8404210, + 0x210AB89F, 0x250A3140, 0x47682100, 0x00901000, + 0x10E54350, 0x46308097, 0x800041D3, 0xEA081138, + 0x0F2A4042, 0x712C02A0, 0x20031900, 0x70801600, + 0x001B8000, 0x800045CB, 0x08291220, 0x708E007E, + 0x20300B21, 0x0A724042, 0x8D4004C0, 0x750C4410, + 0x018741C3, 0x43420003, 0x02200986, 0x0500240A, + 0x740C8D40, 0x41C34342, 0x0005018A, 0x04C0240A, + 0x260A45E1, 0x096A0540, 0x22530220, 0x46CB2058, + 0x04878000, 0xE8128E00, 0x201F0F09, 0x201E080B, + 0x04200E7A, 0x0F0B710C, 0x080D205F, 0x0E6E205E, + 0x720C0420, 0x10031E00, 0x41C37156, 0x08D80003, + 0x2078C808, 0x21D63097, 0x78250822, 0xB90C8D20, + 0x08B27825, 0xD9400960, 0x710E7076, 0x24A220CA, + 0x0DA57EF0, 0x740C23A4, 0x234A708D, 0xC80811C0, + 0x03012005, 0xB80C8D00, 0x20057825, 0x00030F80, + 0x088200D8, 0x41C10960, 0x1CFF238D, 0x180C2456, + 0x06C00DCE, 0xC18040E2, 0x716C734C, 0xFFAF0F02, + 0x1400718C, 0x26553009, 0xD8071801, 0x10C82E41, + 0x2006B923, 0x244A038B, 0x708D71C0, 0x088020A8, + 0x13002901, 0xB8C06C75, 0x02C62800, 0x209F8D00, + 0x70C20803, 0x70016078, 0x22058840, 0xA8400182, + 0x29014C18, 0x71851000, 0x2800B8C0, 0x8D0002C2, + 0x0803209F, 0x631B70C2, 0x88606338, 0xA8407A65, + 0xF1B07702, 0x43428D40, 0x018C41C3, 0x08620003, + 0x240A0220, 0x70AD04C0, 0xC808DC07, 0x200578A5, + 0x00030F80, 0x0FDEF0D8, 0x702C0920, 0x1DFF248D, + 0x180D2556, 0x06C00D2A, 0x30100915, 0x20310B11, + 0x702C4042, 0x02E00F1E, 0x20431900, 0xC7DA4082, + 0x41C3C2E2, 0x12208000, 0x89208941, 0x02C1229F, + 0x0582219F, 0x621A6038, 0xB8C38A02, 0x002009D6, + 0x068D205F, 0x00802079, 0x0186209F, 0x2534651D, + 0x80001F80, 0xC6C20A7C, 0x0AEEC0F1, 0x716C0100, + 0xDA62E89D, 0x800140C3, 0xBA9F4E77, 0x8A208800, + 0x262F7825, 0x0026F005, 0x12340004, 0x208B0080, + 0xF40D8401, 0x01000A7A, 0x0AA2E889, 0xE8870100, + 0x00801230, 0x04032044, 0xC0D1BB24, 0x40607FE0, + 0x4508C2EA, 0xD8FA4110, 0x46284748, 0x05200B1E, + 0x22C1219F, 0x0020096A, 0x40C34010, 0x12208000, + 0x762C8800, 0x0582209F, 0x244ADA22, 0x70CC0400, + 0x20327022, 0x80010F83, 0x710C4E84, 0xB80278B8, + 0x0340200F, 0x7D0FBB86, 0x0AB2700C, 0x45A10060, + 0x0402202F, 0x0F33E008, 0x202F103E, 0x700C2007, + 0x724CD907, 0x708C706C, 0x0A9270AC, 0x260A0060, + 0x700C0400, 0xDA22762C, 0x244A43C1, 0x45A10380, + 0x00600A7A, 0x0F2F70CC, 0x700C107E, 0x724CD907, + 0x708C706C, 0x0A6670AC, 0x260A0060, 0x700C0400, + 0xDA22762C, 0x244A43C1, 0x45A103C0, 0x00600A4E, + 0x700C70CC, 0x724CD907, 0x708C706C, 0x0A3E70AC, + 0x260A0060, 0x700C0400, 0x724CD907, 0x708C706C, + 0x0A2A70AC, 0x264A0060, 0x700C0A00, 0x006009CE, + 0xC6CA712C, 0x800040C3, 0x7FE00462, 0x00051800, + 0x1E00700C, 0x901C7004, 0x7EE00480, 0xE08E4100, + 0xF707710C, 0x704E0E0B, 0x40410000, 0xE1A87EE0, + 0x7FE07CE0, 0x78E0700C, 0x45CBC2E4, 0x1A108000, + 0xE8049511, 0x10451D28, 0x00200872, 0x460840A1, + 0x800040C3, 0xB0C00462, 0x702C40A1, 0xFF6F0E82, + 0x700CDA20, 0xB513B514, 0xB511B512, 0xC6C440C1, + 0x800041C3, 0x91030462, 0x71109120, 0x7CE0700C, + 0xFFCF07B9, 0x800040C3, 0x90000462, 0xB8227FE0, + 0x800040C3, 0x7FE0046E, 0x78E08800, 0x0DBEC0F1, + 0x700C0060, 0x00600DC6, 0x0C12700C, 0x700C0060, + 0xFFCF0F56, 0x7EE0C0D1, 0xC1A4C3F6, 0x800043C3, + 0x8B280462, 0xE90770CD, 0x71C56949, 0x80812104, + 0x904FF5FC, 0x100E8BA3, 0xB0B30115, 0x01171004, + 0x01161002, 0x1028BD0A, 0x1000010B, 0x10240109, + 0x10120108, 0x10140107, 0x2B400106, 0x101012CB, + 0x90910104, 0x01051020, 0x011E100A, 0x011F1006, + 0x01101008, 0x01131016, 0x0111101A, 0x0114100C, + 0x01121018, 0x226D902E, 0x1C0C0300, 0xB9C33004, + 0xDA7F6A14, 0x24537825, 0x1C0A20C1, 0x256D3004, + 0x1C042300, 0x2D403004, 0x78252100, 0x1C02BA07, + 0x2A403004, 0x235321C0, 0x78442181, 0x29407905, + 0x78252380, 0x31812753, 0x30041C08, 0x21C02840, + 0x93E37844, 0x2E407905, 0x78253380, 0x02012D40, + 0x30041C00, 0x21846C17, 0x2004000C, 0x00000F80, + 0x78257C00, 0x01012C40, 0x04012144, 0x7905BC0C, + 0x01402F40, 0x08012084, 0x79058B4A, 0x01C02E40, + 0x7825780F, 0x12012840, 0x30041C0E, 0x1F802404, + 0x70000000, 0x000C2184, 0x782578A5, 0x1F812304, + 0x08000000, 0x29407825, 0x21441101, 0x79050401, + 0x21402E40, 0x08012084, 0x2F407905, 0x780F21C0, + 0x79FD7825, 0x30041C06, 0x0A6DEA08, 0x7CCF0071, + 0x641C8B09, 0x12140C57, 0x244A6912, 0x20057100, + 0x00100F81, 0xC0804000, 0x03C020A8, 0x050B1002, + 0x0F8D2105, 0x00009000, 0x050C1002, 0xBC107424, + 0x12CC2405, 0x4F98A580, 0x907E2053, 0xB323B9A0, + 0x710CF205, 0x02002006, 0x40C3AB0B, 0x1A308000, + 0x00710A15, 0x00051800, 0x60D88B09, 0x00031B08, + 0xAB09B8C2, 0xC7D67830, 0x4350C2EE, 0x09D74130, + 0x47080030, 0x2FC3208A, 0x800045CB, 0x70CD1A10, + 0x2448222F, 0x21140A1D, 0x20300B19, 0x90BE2753, + 0x700CF219, 0xA5077726, 0xA505A506, 0xF02EA504, + 0x90BE2753, 0x0A69F21F, 0x74E52070, 0xA5C6A5C7, + 0x0D8AA5C5, 0xA5C4FFEF, 0x20B00A49, 0x77264708, + 0x40A1F1E0, 0x0C1A702C, 0xDA20FF6F, 0xA048228C, + 0x00250046, 0x1D22732C, 0x21801404, 0xB5322038, + 0x0A21F00C, 0x40A12070, 0x0BF6702C, 0xDA20FF6F, + 0x20B00A3B, 0x20912142, 0xFFCF0D42, 0xF1C24708, + 0x74E5A5C3, 0xA5C1A5C2, 0xF01DA5C0, 0xA5C6A5C7, + 0xA5C4A5C5, 0x2104F017, 0x00002F80, 0x781DFFFE, + 0x203F090F, 0xB5327704, 0xE708B511, 0xB532F00B, + 0xFFEF0D0A, 0x702CB511, 0xA52068E4, 0xA522A521, + 0x78F0A523, 0x78E0C6CE, 0x4508C2E2, 0x0060096E, + 0x080C208A, 0x752CD809, 0xDA0CB813, 0x0008238A, + 0x45A1708C, 0x00200EB6, 0x700C70CC, 0x724C762C, + 0x244A736C, 0x45A10680, 0x00200EA2, 0x0EF270CC, + 0x700C03C0, 0x724C762C, 0x244A716C, 0x45A10680, + 0x00200E8A, 0x0EDA70CC, 0x700C03C0, 0x724C762C, + 0x244A706C, 0x45A10680, 0x00200E72, 0x700C70CC, + 0x095ED922, 0x704C0060, 0x752C700C, 0x238A744C, + 0x708C000E, 0x0E5645A1, 0x70CC0020, 0xD907D880, + 0x744CB893, 0x708C706C, 0x0E4270AC, 0x70CC0020, + 0xFFCF0CA6, 0x78107704, 0x78E0C6C2, 0x4508C2EA, + 0x70801600, 0x00088000, 0x00B1080D, 0x2280204A, + 0xF00574CD, 0x2240204A, 0x0C9672CD, 0x08AEFFCF, + 0x208A0060, 0x08B2080C, 0x706C0040, 0x4768D907, + 0xBF8F724C, 0x40E1708C, 0x0DF270AC, 0x70CC0020, + 0xD907700C, 0x706C704C, 0x70AC708C, 0x00200DDE, + 0x6F1570CC, 0x704C752C, 0x708CDB80, 0x0DCE45A1, + 0x70CC0020, 0x12002F40, 0x42C1D929, 0x708C706C, + 0x70CC45A1, 0x00200DB6, 0x40224110, 0x42C1D929, + 0x708C706C, 0x0DA645A1, 0x70CC0020, 0x30821204, + 0xD907700C, 0x708C706C, 0x0D9270AC, 0x70CC0020, + 0xD907700C, 0x706C704C, 0x70AC708C, 0x00200D7E, + 0x6F1670CC, 0x704C752C, 0x0004238A, 0x45A1708C, + 0x00200D6A, 0xD80870CC, 0xB898D92A, 0x706C42C1, + 0x45A1708C, 0x00200D56, 0xD84170CC, 0xB812D92A, + 0x706C42C1, 0x45A1708C, 0x00200D42, 0x700C70CC, + 0x744CD907, 0x708C706C, 0x0D3270AC, 0x260A0020, + 0x0FBE0400, 0x700C0000, 0x704CD907, 0x708C706C, + 0x0D1A70AC, 0x70CC0020, 0xD907D880, 0x706C704C, + 0x70AC708C, 0x00200D06, 0x0B6E70CC, 0x7704FFCF, + 0xC6CA7810, 0x40C3C0F1, 0x61A80000, 0x0000080E, + 0xFFCF0AE2, 0x7EE0C0D1, 0x0072081D, 0x1600714C, + 0x901C7101, 0xE9850484, 0x71447210, 0x2179F6B9, + 0xF0030000, 0xD90B700C, 0xFF6F066D, 0x78E0B912, + 0x082DC2E2, 0x43200072, 0x800045CB, 0x8D420462, + 0x28057810, 0x0B110081, 0x9500027F, 0xEA848D4B, + 0xF003714C, 0x0CE6704C, 0xB500FFCF, 0x78E0C6C2, + 0x70ADC0E6, 0xB0A2E2B3, 0xB0A7B0A1, 0x0302B0A6, + 0xB0A0002D, 0x24AD4468, 0x20241203, 0x00F50080, + 0x01090000, 0x01310000, 0x015B0000, 0x01850000, + 0x01A50000, 0x01B30000, 0x00B70000, 0x00BB0000, + 0x02CF0000, 0x00BD0000, 0x01AB0000, 0x01B30000, + 0x02BF0000, 0x01AF0000, 0x01C10000, 0x01C70000, + 0x00A10000, 0x02AB0000, 0x02A70000, 0x02A30000, + 0x029F0000, 0x029B0000, 0x02970000, 0x02930000, + 0x01AD0000, 0x01BB0000, 0x006F0000, 0x01C10000, + 0x01E90000, 0x01E90000, 0x01EB0000, 0x006F0000, + 0x017D0000, 0x01E90000, 0x01E90000, 0x01F10000, + 0x01F30000, 0x00570000, 0x00370000, 0x01F30000, + 0x01F70000, 0x01F70000, 0x01F70000, 0x01F90000, + 0x01F90000, 0x01FD0000, 0x020B0000, 0x02210000, + 0x000F0000, 0x021D0000, 0x021D0000, 0xB0A40000, + 0x0020021F, 0xDB78B0A3, 0x2453B063, 0xF0A600C3, + 0xB063DB38, 0x00832453, 0x0203F0A0, 0xBBC60020, + 0x02F270D4, 0x23530021, 0xBB24018C, 0x0E012384, + 0x2345B084, 0xF0F400C3, 0x2C406BF3, 0x2453008C, + 0x274400C4, 0x24841C0E, 0x24051001, 0x24050384, + 0x7B7B110C, 0x2384B084, 0x27440C01, 0x7B85120C, + 0xF0DEBB80, 0x2C406BF3, 0x2453008C, 0x274400C4, + 0x24841C0E, 0x24051001, 0x24050384, 0x7B7B110C, + 0x2384B084, 0x27440C01, 0x7B85120C, 0x01432345, + 0x6BF3F0C6, 0x008C2C40, 0x00C42453, 0x1C0E2744, + 0x10012484, 0x03842405, 0x110C2405, 0xB0847B7B, + 0x0C012384, 0x120C2744, 0x23457B85, 0xF0B00183, + 0xBB037C7B, 0x1C012484, 0x0C032344, 0xB083BC82, + 0x008C2C40, 0x00C42453, 0x10012484, 0x01032305, + 0xF03C7B85, 0x2453BB23, 0x2384018C, 0xB0840C01, + 0x03032345, 0x0E25F094, 0x02370011, 0x18080020, + 0xBB050104, 0x2384DC68, 0xB0830801, 0xDB28F026, + 0x70D4F060, 0x00010218, 0x018C2353, 0x23847B7D, + 0xB0840001, 0xF07CBB83, 0x01041808, 0x06051806, + 0xDB38F077, 0x2453B063, 0xF00F0083, 0x018C2353, + 0x23847B7D, 0xB0840001, 0x0C032345, 0xDB78F068, + 0x2453B063, 0xBB8600C3, 0xF063B064, 0x2C406BF3, + 0x2453008C, 0x274400C4, 0x24841C0E, 0x24051001, + 0x24050384, 0x7B7B110C, 0x2384B084, 0x27440C01, + 0x7B85120C, 0xF04CBB81, 0xF049DB58, 0xB083B084, + 0x7B7DF047, 0x00012384, 0xF041BB83, 0xF041B084, + 0x2384BB23, 0x23450C01, 0xF0390303, 0x01832453, + 0x7B7DF035, 0x00012384, 0x0C032345, 0x70D4F02F, + 0xDB40F51F, 0xDB60F006, 0xDB20F004, 0xDB50F002, + 0xF026B0A4, 0xF023DB38, 0x00832453, 0xF01FBB86, + 0xBB037C7B, 0x1C012484, 0x02032344, 0xBB807B85, + 0xBB03F015, 0x008C2C40, 0x00C42453, 0x0C032344, + 0x10012484, 0x01032305, 0xF0097B85, 0xF007DB40, + 0xF005DB68, 0x2384BB05, 0xB0640801, 0x091DB063, + 0x0A19041F, 0x22780C70, 0x230B0A03, 0xF4068180, + 0x00432553, 0xF003B065, 0x0939B0A5, 0xDB0D053F, + 0x057F0937, 0x0939DBD0, 0xDB0D05BF, 0x05FF0937, + 0x0939DB08, 0xDB80063F, 0x067F09B3, 0x0010238A, + 0x06BF09D3, 0x0004238A, 0x06FF09D3, 0xF010706C, + 0x0345180E, 0xB067F00C, 0xF00ADBD0, 0xB067BB08, + 0x180EF006, 0xF0040205, 0xDB80B067, 0x0909BB8C, + 0xB06704DE, 0x07550A13, 0x708F0E21, 0x00181000, + 0x0B21766C, 0x2242008F, 0x0B190843, 0x0A150094, + 0xE2A90AF0, 0xF414704C, 0x180C744C, 0xF0100105, + 0x00832941, 0x7A66724C, 0x01032144, 0x21447074, + 0x0B0D0303, 0x22CF0330, 0xB0460021, 0x049E090B, + 0x00C22245, 0x262FB046, 0x000AF046, 0x18040003, + 0x090B0045, 0xBA83033E, 0x090DB046, 0x0D09019F, + 0xC4C6005F, 0x00451800, 0xB067C4C6, 0xBB0A756C, + 0x2B41F1BF, 0xBB2B01CC, 0x1C012484, 0x0E012384, + 0x110E2405, 0x01C32345, 0xF17AB0C4, 0xDB58B084, + 0xB067F176, 0xBB08DB11, 0x238AF1AB, 0xB0670008, + 0xBB09DB09, 0x78E0F1A5, 0x0C1AC2E2, 0x45280020, + 0x05600886, 0x0EB2760C, 0x7704FF8F, 0x00200C8E, + 0x0C6E7810, 0x70B50000, 0xFFC20B3C, 0x78E0C6C2, + 0x0BF2C2E2, 0x45280020, 0x0560085E, 0x0C52760C, + 0x70B50000, 0xFFC20B20, 0x78E0C6C2, 0x800040C3, + 0x7FE0046F, 0x00431800, 0x46CBC2F4, 0x04628000, + 0x8E4D4050, 0x2180260A, 0x2140240A, 0x2100250A, + 0x43304270, 0x01B1092D, 0xEA144110, 0x8E008EA2, + 0x80BE2053, 0x7DBBF402, 0x0487212F, 0x0A8640A2, + 0x42820020, 0x23402002, 0xFFEF0B0A, 0xF0C94122, + 0x081D8E0A, 0x40620071, 0xFFAF0DB6, 0x20788E68, + 0xBB240000, 0xB870B806, 0xAE086078, 0x47CB7054, + 0x1A108000, 0x223E090F, 0x206120C0, 0xB8819710, + 0x090DB710, 0x9710235E, 0xB710B880, 0x0E699620, + 0x21532030, 0x08190080, 0x700C0131, 0xA706A707, + 0xA704A705, 0x0D866904, 0xB600FFAF, 0x42628E23, + 0x43428E04, 0x41227825, 0x00002079, 0x0540240A, + 0x40E1AE03, 0x0500250A, 0x0ABA70CC, 0x70ADFFEF, + 0xFFAF0D3E, 0x08C54062, 0x4FA80030, 0x41224020, + 0x43424262, 0x0540240A, 0x0500250A, 0xFFEF0A96, + 0xF05871CC, 0x01110829, 0x225F0911, 0x8E438E04, + 0x00010A09, 0xE80C9712, 0xA704700C, 0xA706A705, + 0x6904A707, 0xFFAF0D16, 0x9620B600, 0x09CBB9C2, + 0x40620130, 0x003109C1, 0x8E23700C, 0x8E044262, + 0x78254342, 0x20794122, 0x240A0000, 0xAE030540, + 0x250A40E1, 0x0A3E0500, 0x70CCFFEF, 0x96008E22, + 0x090F7404, 0xB600227E, 0xB8819712, 0x4062B712, + 0xFFAF0CAE, 0x204D2002, 0x4F28E813, 0x42624122, + 0x240A4342, 0x250A0540, 0x0A0A0500, 0x71CCFFEF, + 0x74049600, 0xFFAF0CDE, 0x8E02B600, 0x40A17D02, + 0xFFEF09C2, 0xF0234122, 0xA1A2A1A3, 0xA1A0A1A1, + 0x96008EA2, 0xB600E008, 0x23402017, 0x0072082B, + 0x15841F22, 0x1F2460B8, 0x77041085, 0xFFAF0C6E, + 0x2F057F10, 0x96001341, 0xFFAF0E92, 0xB600704C, + 0x22D1214F, 0x1F24F003, 0x8E0410C5, 0x0E32AE03, + 0x40220620, 0x0C2AC6D4, 0x4308FF8F, 0x41224F28, + 0x43424262, 0x0540240A, 0x0500250A, 0xFFEF0986, + 0x960070CC, 0x0B357404, 0xB6001030, 0xFF8F0C1E, + 0x40E18EA2, 0x42624122, 0x240A4342, 0x250A0540, + 0x09620500, 0x71CCFFEF, 0x20029600, 0x74042341, + 0x8E02B600, 0xF10A4910, 0x20028E02, 0x0D13200D, + 0x0BEA1052, 0x40A1FF8F, 0xFFEF090A, 0x09934122, + 0x9712A2DE, 0xB712B880, 0x78E0F1C3, 0xC1ABC3E6, + 0x45284748, 0xC0804608, 0x0A66702C, 0xDA2AFF2F, + 0x41838E00, 0x8E01B103, 0x8E02B104, 0x8E03B10B, + 0x103E0F0B, 0x1C0AB10C, 0x0F0B3344, 0x1C1A105E, + 0x0C1A3344, 0xC080FFAF, 0x78E0C7C6, 0x800040C3, + 0x7FE00466, 0x00031800, 0x800041C3, 0xB1000462, + 0xB1037FE0, 0x800040C3, 0x7FE00466, 0x00431800, + 0x800043C3, 0xB30419E4, 0xB303D858, 0x01802153, + 0x2253B30C, 0xB30D0040, 0x800044CB, 0xB3050462, + 0xB308781D, 0x783DB300, 0x0140206C, 0xB8839440, + 0xB30BE208, 0x03B54060, 0xB440FFAF, 0xC1A4C3E8, + 0x800046CB, 0x47480462, 0x45289640, 0x00812253, + 0x700C4010, 0xC042C043, 0x091FC041, 0xC0400131, + 0x800041C3, 0xA1001A20, 0xA102A101, 0x6A04A103, + 0xFFAF0AFA, 0x8E02B600, 0x781B70F5, 0x080F780F, + 0x20CA2031, 0x0D090062, 0x45081005, 0x100E2D05, + 0x781078C9, 0x26C27510, 0x78D01061, 0x8004208C, + 0xD908F792, 0xB80AD81F, 0xB2074283, 0x08002059, + 0x0892B203, 0xC0800920, 0x107C2680, 0x208C78D0, + 0xF7328FC3, 0xF388262F, 0x2E40F212, 0x20041300, + 0x00000F80, 0xB8887000, 0xB88BB889, 0x30041C06, + 0x20046E17, 0x00000F80, 0xF0057C00, 0x1C06700C, + 0x1C0E3005, 0xC0803004, 0x0920084A, 0xC7C8D908, + 0x800041C3, 0x19020462, 0x7FE00043, 0x78E0A90C, + 0x70041E00, 0x049C901C, 0x78E07EE0, 0xC1A8C3E6, + 0x47284648, 0x24404508, 0x702C3080, 0xFF2F08E2, + 0x6E13DA1E, 0x2044BE0E, 0x42830400, 0xB203B20B, + 0x1F802605, 0x2C580000, 0x2753B200, 0x68371180, + 0xB20C7825, 0x11802553, 0x78256837, 0x78FDB204, + 0x0140206C, 0x2605B883, 0xB8071001, 0xC0807905, + 0x0FD2B228, 0xD91008E0, 0x78E0C7C6, 0x1E00710C, + 0x901C7004, 0x7EE00480, 0xB9025020, 0x0F812105, + 0x0488901C, 0xB1007FE0, 0xB9025020, 0x0F812105, + 0x048C901C, 0xB1007FE0, 0x4708C2E8, 0x20846A15, + 0x204F0001, 0x204F06D0, 0x2148068E, 0x77040040, + 0x68A17810, 0x400270F5, 0x038120CA, 0x704CD907, + 0x708C706C, 0x0B7670AC, 0x70CCFFEF, 0x1D3F258C, + 0x78E0C6C8, 0x256FC2E8, 0x46081743, 0x10D01500, + 0x20402040, 0x7314780F, 0x002500F0, 0x0D1E70ED, + 0x42C10880, 0x00842280, 0xE8188A60, 0x10C21500, + 0x780F6A01, 0x00F408D5, 0x2A446B01, 0xB8220081, + 0x0FC02049, 0x10002615, 0x0A999081, 0x242F00B2, + 0x90200045, 0xF0497180, 0x20B2082D, 0x20812844, + 0x170B1682, 0x240A6B01, 0x20A87000, 0x26150300, + 0x908110C0, 0x12C40C41, 0x0B3D9000, 0x77641004, + 0xF01B700C, 0x700CE3BF, 0x1682F717, 0xDC40170B, + 0x240A7C62, 0x20A87300, 0x261503C0, 0x94A110CC, + 0x12C40D15, 0x0B119480, 0xE3BF1324, 0x20CA7164, + 0xF0030FE1, 0x60384060, 0x7B0FAA00, 0x17021682, + 0xF749E3C0, 0x96017E75, 0x0084080B, 0x0A3D9600, + 0x242F0005, 0xD8C80045, 0x022041C3, 0xF0130003, + 0x792D7933, 0x1E824C31, 0x9000105C, 0x10240C0F, + 0x0C0B7A30, 0x0A151084, 0xD8C80005, 0x021F41C3, + 0x0F0E0003, 0xDF070140, 0xC6C840E1, 0x0DA2C2F2, + 0x451001A0, 0x704E4410, 0x800047CB, 0x0AA91222, + 0xD82520B5, 0x8820B89F, 0x7825881B, 0x048E0895, + 0x1A0D8FC0, 0x7DCF3482, 0x08898F01, 0x40C30344, + 0x12D98000, 0x08798800, 0x40A2036E, 0x085641A1, + 0x1A0B0760, 0x43103358, 0x0865700E, 0x0B5D2295, + 0x210A242E, 0x1A0C2500, 0x40C33418, 0x28F00000, + 0x221A7A1B, 0x211A2001, 0xB8222082, 0x623A78AA, + 0x40026219, 0x0184209A, 0x70C36038, 0x1A3C8000, + 0xFFEF0E76, 0x34581A0D, 0x3082120D, 0x00002078, + 0x3603120B, 0x021E41C3, 0x0B6E0003, 0x120CFF2F, + 0x71363604, 0xF5DB712E, 0xF1D17106, 0xF1BD71C5, + 0xF1AF7146, 0x78E0C6D2, 0x1CFCC2FA, 0xC1A8B6C8, + 0xD8254318, 0x1600B89F, 0x80007091, 0x44D31222, + 0x00489004, 0x24428820, 0x881B2210, 0x20787825, + 0x204000C0, 0x16000055, 0x80007080, 0x08E11223, + 0x40C30444, 0x12D98000, 0x08D18800, 0x212F046E, + 0x0F920447, 0x40630720, 0x23182940, 0x706E4118, + 0x34EE09B3, 0x22002B40, 0x200570AD, 0xC8080601, + 0x69127905, 0x20054230, 0x90040F96, 0x215A0320, + 0xC7802A00, 0x800041C3, 0x7FB4C004, 0x04C02015, + 0x603278B4, 0x11A06119, 0x20340101, 0x80000F80, + 0xB740BEC4, 0x1C08B722, 0x25053004, 0x68D21480, + 0x15002605, 0x00E009D6, 0xB7059000, 0x140E2605, + 0x00E009CA, 0xB7079600, 0x160071A5, 0x0DB32100, + 0x1C129564, 0x40A23004, 0x062009E6, 0x706CC180, + 0x2305C485, 0x14020480, 0xB8021501, 0x20057164, + 0xB2200502, 0x04012005, 0x0BEB9401, 0xB1008564, + 0x70801600, 0x00EE8000, 0x141CE885, 0x1E003100, + 0x71662004, 0xA2540B4D, 0xF18F7126, 0x1404C0A8, + 0xC6DA341B, 0xC1A3C3F8, 0xD8254018, 0x1600B89F, + 0x8000708D, 0x16001222, 0x80007092, 0x88200187, + 0x881B7056, 0x242122CA, 0x20787825, 0x204000C0, + 0x16000053, 0x80007080, 0x08DB1223, 0x40C30344, + 0x12D98000, 0x08CB8800, 0x79AF036E, 0x07200E76, + 0x2D404003, 0x47101316, 0x0FB1700E, 0x2840242E, + 0x702E2200, 0x05812005, 0x2105C808, 0x25050015, + 0xC1812440, 0x260568D2, 0x90041F8F, 0x0B960048, + 0x97000260, 0x1F8E2605, 0x00409004, 0x0B869600, + 0xC1820260, 0x30821409, 0x30811405, 0x0483223D, + 0x0480213D, 0xC022786B, 0xE810F410, 0x08022254, + 0x2154C321, 0x77040801, 0x1C097764, 0xC0623082, + 0x1C05C361, 0xF0033042, 0x792FC321, 0x0007252F, + 0x262FC140, 0x272F0087, 0x740C00C7, 0x41C34222, + 0x0007025A, 0x0C4A43A1, 0x240A0160, 0x0CF60400, + 0xC0810160, 0x0CEEB700, 0xC0820160, 0x2140B600, + 0x086F2040, 0x712E84E4, 0x08537106, 0x71A5A254, + 0xC7D8F191, 0x88606038, 0xA8607B44, 0x0083104B, + 0x184B7B44, 0x109600C2, 0x7B440083, 0x00C21896, + 0x008310E1, 0x7FE07A64, 0x008218E1, 0x2482C3F4, + 0x250A3306, 0x230A2180, 0x40702100, 0x45284650, + 0x248A4410, 0x24407001, 0x218A3011, 0xC0800FC7, + 0x014020A8, 0x1804B021, 0x18000015, 0xD8FF0005, + 0x301C1C82, 0x38002456, 0x000042D3, 0x47CB0A3C, + 0x1A3C8000, 0x00300D89, 0x07C31802, 0x1481251F, + 0x0184228A, 0x2F80241F, 0x28F00000, 0x2184209F, + 0x70026038, 0x0B9260F9, 0xC080FEEF, 0x088008AE, + 0x003008DB, 0x1600DD3F, 0x80007080, 0x080F0001, + 0x1600009F, 0x8000708D, 0x08920120, 0x24560880, + 0x24003843, 0x00003F81, 0xA901010C, 0x712C40A1, + 0x02E00EBE, 0x148A704C, 0x248A370D, 0x708D7001, + 0x20A8C080, 0x10020340, 0x10020503, 0x4A710502, + 0x71247270, 0x24C079AC, 0xF0501046, 0x20842180, + 0xA3440E9D, 0x20900B0F, 0x20510B13, 0x101F0D0B, + 0x0D0BF005, 0x71A5101F, 0x70CDF1F4, 0x94050EFB, + 0x20310D11, 0x16802500, 0x0080101C, 0x10000E4B, + 0x0880081A, 0x1482251A, 0x241F7014, 0x00002F81, + 0x708D28F0, 0x800040C3, 0x61591B3E, 0x229A42C1, + 0x623A0184, 0x6059F206, 0x14829161, 0x4B343701, + 0x620A62F9, 0x20801100, 0x0306242F, 0xC0804A13, + 0x00600F96, 0x71C5C280, 0x248AF1D2, 0x708D7001, + 0x20A8C080, 0x10020300, 0x10020502, 0x49530501, + 0x71647150, 0x10C624C0, 0xC7D47890, 0x4008C0E6, + 0x7001248A, 0x70CD70ED, 0x07C020A8, 0x000044CB, + 0x7D9B28F0, 0x1300201F, 0xBC227D6A, 0x60B87C2A, + 0x4448609D, 0x1184249F, 0x44CB659D, 0x1A3C8000, + 0x71E57DF5, 0x64BC6590, 0x4C159481, 0x25407410, + 0x26C0104B, 0x78D012C6, 0x78E0C4C6, 0x78E07EE0, + 0x70851E00, 0x0088900C, 0x78E07EE0, 0x0921C0F1, + 0x271400A5, 0x0ACE000C, 0x40A00160, 0x0AC6B40A, + 0x40C00160, 0x2740B40C, 0xF00C0200, 0x01600AB6, + 0xB40A4060, 0x01600AAE, 0xB40C4080, 0x04802740, + 0xC0D19000, 0x1F1C7FE0, 0x78E00004, 0x08EDC3F4, + 0xC1A40071, 0x47CB712E, 0x12228000, 0x20F509D3, + 0x0447202F, 0x00900813, 0x0051081B, 0x70811600, + 0x00258000, 0x1600F005, 0x80007081, 0x09AF0040, + 0x0D1A00D1, 0x0EEE01C0, 0x706E0600, 0x20B50B9F, + 0x0DB64062, 0x702C00A0, 0x20408FA0, 0x8F010A94, + 0x03440887, 0x13122D40, 0x2205C808, 0xC1802510, + 0x04002005, 0x04C22116, 0x46CBB802, 0x00009004, + 0x78C57AB4, 0x0B5F9000, 0xB2002071, 0x034021F4, + 0x422279B4, 0x9124716C, 0x603844A1, 0x042241C3, + 0x78100006, 0x0002252F, 0x01D62841, 0x01552553, + 0x260A740C, 0x093A0580, 0x270A0160, 0x2E400540, + 0x20052180, 0xC8080541, 0x04822005, 0x04002005, + 0xB802BA02, 0x22057E05, 0x90040F82, 0xB22000A8, + 0x71A5B620, 0x7166F1BD, 0x7126F1B2, 0x0E46F198, + 0x0C6A0600, 0x730C01E0, 0x78E0C7D4, 0x41C3C2F0, + 0x000001CF, 0x016008EA, 0x43D3740C, 0x12228000, + 0x208E1300, 0x800142D3, 0x22164D44, 0x1301238D, + 0x76102080, 0x002D0120, 0x23802216, 0xCC2290E0, + 0x702EE819, 0x40F144B1, 0x21041400, 0x42C1740C, + 0x01D041C3, 0x08AA0003, 0x43220160, 0x25001402, + 0x20087126, 0x27092010, 0xCC22100F, 0xA00409DD, + 0x40F1F002, 0x41C3740C, 0x000201D1, 0x088242E1, + 0x43020160, 0x740C7702, 0x41C37FFD, 0x000201D2, + 0x1310274E, 0x232F42E1, 0x08660408, 0x41700160, + 0x2E406F14, 0x20051343, 0x29402010, 0x20052100, + 0xC80803DF, 0x2300718C, 0x00000F8C, 0x726D1000, + 0x903842C3, 0x0C0F0000, 0x208A0031, 0x208A1C15, + 0x20051415, 0xB9021001, 0x1016218A, 0x0C0D7945, + 0x91200031, 0x1815218A, 0x000C2184, 0x2105708C, + 0x210507CF, 0xB9021001, 0x794572AC, 0x912070CC, + 0x000C2184, 0x20472005, 0x02012600, 0x001E2105, + 0x30C12605, 0x7945B902, 0x2605B1E0, 0xB9023301, + 0xB1E07945, 0x02412600, 0x00062105, 0x00C12605, + 0x7945B902, 0x01C41900, 0x03012605, 0x71CCB902, + 0x258D7945, 0x1900093F, 0x238C01C4, 0xE5081FFE, + 0xF16F71C5, 0x06000CEE, 0x78E0C6D0, 0x014422AA, + 0x010421AA, 0x800040C3, 0xA0410450, 0xA0207FE0, + 0x700026F4, 0x0F608000, 0x78E07EE0, 0x803C2042, + 0x012220E8, 0x0040212F, 0x7FE06909, 0x78E07810, + 0x4010C2E8, 0x4568730C, 0x0AD24648, 0x472801E0, + 0x800040C3, 0x88001138, 0x1600E810, 0x80007080, + 0x08190001, 0xD80F00FF, 0x42E14102, 0x708C43C1, + 0x08A00C16, 0xC6C845A1, 0x4102D80F, 0x43C142E1, + 0x08A00A6A, 0xC6C844A1, 0xEA06C0E6, 0x248A76AD, + 0xF005100F, 0x248ADD07, 0x2278100E, 0xBA060002, + 0x2204E23F, 0x7984004F, 0x7C0479B9, 0x2C0169D6, + 0x66FE1340, 0x0E176836, 0x61581064, 0x76107810, + 0x108D24C0, 0x6698F703, 0xC8084834, 0xB8027865, + 0x0F802005, 0x3C009004, 0xC4C6B080, 0x093EC2E2, + 0x099E02C0, 0x450802E0, 0x02A00D66, 0x609860BC, + 0x00412044, 0x780F6038, 0x07012089, 0x30021A04, + 0x78E0C6C2, 0x4008C2E6, 0x800040C3, 0x08151221, + 0x88401071, 0x70831600, 0x00408000, 0xF2957074, + 0x1030080D, 0x100C2078, 0xF0038865, 0xEC848863, + 0xF0038886, 0xC8088884, 0xDD787034, 0x0C0F706D, + 0x25CA10E5, 0x70CD1822, 0x2178F01F, 0x655D0001, + 0x70CDB903, 0x00462140, 0x03012B40, 0x7180240A, + 0x702D61B9, 0x69F27905, 0x030020A8, 0x13C12105, + 0x10102180, 0xB99CB992, 0x9120B99F, 0x038E2108, + 0x71647391, 0xB802F7AA, 0x0343236F, 0x0F802005, + 0x00209004, 0x730C9080, 0x05091302, 0x100C2479, + 0x210C8B20, 0x00009F80, 0x20CA0C7F, 0x723400AD, + 0x23CA7C9B, 0x718510E1, 0x2300DDFF, 0x7C3D130B, + 0x2E01E407, 0x7461130C, 0x208A641C, 0x20CA0FC7, + 0x78C40341, 0x00002079, 0x2356641C, 0x10000940, + 0x609800C0, 0x2048780E, 0xCA070003, 0x0813E80F, + 0x12210231, 0x0C17370C, 0x00001F80, 0x08176815, + 0x0C130251, 0x00001F81, 0x09177196, 0xBB620111, + 0x210CF007, 0x00009F80, 0x23C22156, 0x202F0066, + 0x242F0200, 0x785500C8, 0x007541C3, 0x70C30003, + 0x04588000, 0x6B09B060, 0x43017810, 0xFEEF0A7A, + 0x03C0207C, 0x40C3C6C6, 0x04588000, 0x90207855, + 0xC6C6B021, 0xC80843E3, 0x2005B802, 0x90080F80, + 0x90000014, 0x02A00F96, 0x2044B8C3, 0x781D0041, + 0x7B006038, 0x1CFCC2FA, 0x2482B6C8, 0xD98E3805, + 0xB99F70AD, 0xC551DA80, 0x11F88900, 0xC552808E, + 0x8908C047, 0xC553702C, 0xC044C554, 0xFEAF0D32, + 0x3E002455, 0x702CC098, 0x0D26DA80, 0xC557FEAF, + 0x14002644, 0xC54D720E, 0xC54FC54E, 0xC549C550, + 0xC54BC54A, 0xC556C54C, 0xC007C046, 0x807E2053, + 0x4DC8F212, 0x7825C808, 0x79B6C191, 0x06200BAE, + 0x1600714C, 0x8000708B, 0x16001223, 0x80007082, + 0xF02D1222, 0x708B1600, 0x12238000, 0x70821600, + 0x12228000, 0x10A40B47, 0x1F012554, 0x7825C808, + 0x68324448, 0x13832C40, 0x7200244A, 0x70CD7B25, + 0x048020A8, 0x24556D16, 0x671F3E0F, 0x671F6C14, + 0x12802E40, 0x7FD47865, 0x71C5B892, 0xB89FB89C, + 0xB7009000, 0x71857471, 0x0B47F7A6, 0x6D3610A4, + 0x611B6A14, 0x1F412554, 0x7825C808, 0x2A4068D2, + 0xC098038F, 0x244A7FC5, 0x60797200, 0x20A8700C, + 0x27050340, 0x2080100C, 0xBC920010, 0xBC9FBC9C, + 0x19029480, 0xE3100314, 0x71447271, 0xC006F7A9, + 0x4DDAE889, 0x7825C808, 0x79B6C189, 0x06200AEE, + 0xC004714C, 0x013E0815, 0xC8084DD8, 0xC18D7825, + 0x0ADA79B6, 0x714C0620, 0x227E208D, 0xC09871AD, + 0x3B1B2440, 0x08002054, 0xC042700F, 0x3E002455, + 0x30191408, 0x08002054, 0xC045C043, 0x30161408, + 0x140CC696, 0x24543013, 0x7EB43B92, 0x23522214, + 0x3B172440, 0x77B171ED, 0x1600F2F6, 0x80007085, + 0x16001223, 0x8000708C, 0xC0061222, 0x700DE8B8, + 0x03240D67, 0x2454702D, 0x25023B0B, 0x23140300, + 0x231413CB, 0x27143307, 0x20402304, 0x702D0046, + 0x1702700D, 0x762C0500, 0x01200C56, 0x4408DA40, + 0x1402B600, 0x762C0500, 0x01200C46, 0x1B00DA40, + 0x222F1004, 0x9E200206, 0x1B00B680, 0x780E1004, + 0x22087902, 0x9E200048, 0x212F4910, 0x268D0246, + 0x210808FF, 0x202F0009, 0xF0910206, 0xC0056C34, + 0x00482000, 0x2014C096, 0xC09703D0, 0x03DE2014, + 0x20442600, 0x30472100, 0x20462300, 0x702D706D, + 0x03240DF9, 0x11802B40, 0x2053C007, 0xF218807E, + 0x2016C091, 0x78F60341, 0x030121F4, 0x030020F4, + 0xB826B926, 0x20441A00, 0x30041E00, 0x21411200, + 0x212F4910, 0x210802C6, 0xF019000B, 0x7200244A, + 0x420143C0, 0x04C020A8, 0x05001202, 0x1A00B826, + 0x13022004, 0xB8260500, 0x30041E00, 0x21411200, + 0x212F4910, 0x210802C6, 0x214A000B, 0x250A2200, + 0x240A2100, 0x140221C0, 0x762C2500, 0x01200B72, + 0xB600DA40, 0x1502762C, 0x0B662500, 0xDA400120, + 0x20041800, 0x9E00790E, 0x212F7822, 0x218D0246, + 0x21082B7F, 0xC0040009, 0x013E083D, 0x3D112440, + 0x2116762C, 0xDA402340, 0x01200B36, 0x030020F4, + 0x2116B600, 0x762C23C0, 0x0B26DA40, 0x20F40120, + 0x18000300, 0x790E2004, 0x78229E00, 0x0246212F, + 0x00092108, 0x04042440, 0x04072740, 0x04062640, + 0x14082040, 0xF1867185, 0x0B66780E, 0x44000000, + 0x00200B5E, 0x0246202F, 0x202F4110, 0xC1880607, + 0x611942A1, 0x190043E1, 0xC1950442, 0x41C36038, + 0x0003038E, 0x01021800, 0x09E6740C, 0x40300120, + 0x2401204F, 0x42A1740C, 0x09D643E1, 0x240A0120, + 0x71070440, 0x203F2680, 0x203F2380, 0x22172742, + 0x77E570F5, 0xC005F501, 0x303F2180, 0x003F2080, + 0x321B2342, 0x77A570B5, 0xFFE205D4, 0xC135C045, + 0x70801600, 0x12208000, 0xD841E803, 0xD826F002, + 0x1408B89F, 0x700E3015, 0x1801712E, 0x14550052, + 0xA8203081, 0xA829C128, 0x30811421, 0xC006A82A, + 0x00172079, 0x34001C04, 0x34001C00, 0x30141408, + 0x3B182454, 0x3B962454, 0x34532014, 0x24562614, + 0x273971ED, 0x704E1440, 0x05C02006, 0xB8E070CD, + 0x1600F4CB, 0x8000708C, 0x16001222, 0x80007092, + 0x20141223, 0xC00333CE, 0x700D70AD, 0x25006C34, + 0x24002044, 0x20002049, 0x74520046, 0x002D015A, + 0xC00778AE, 0x807E2053, 0xC091F23F, 0x2016762C, + 0xDA400440, 0x012009DA, 0x030020F4, 0x43CB4700, + 0xFFFF0000, 0x3000264A, 0x0200254A, 0x20041E00, + 0xC1986F16, 0x6C146119, 0x762C6038, 0x078020F4, + 0x012009AE, 0x212FDA40, 0x264002C8, 0x258D305E, + 0x21090CBF, 0xB600000B, 0x081DC004, 0xC08D013E, + 0x78F6762C, 0x098ADA40, 0x20F40120, 0x23090300, + 0xB600100B, 0x02C6212F, 0x01C6202F, 0x79AE7822, + 0x000D2108, 0x274AF020, 0x260A0200, 0x250A3240, + 0x15020180, 0x762C0500, 0x01200956, 0x4308DA40, + 0x35001602, 0x094A762C, 0xDA400120, 0x02C6222F, + 0x4A31790E, 0x278D7AAE, 0x22080BFF, 0xB600004D, + 0x22C41E00, 0x14600F83, 0x1200234A, 0x0240250A, + 0x0100270A, 0x05001702, 0x0916762C, 0xDA400120, + 0x20041B00, 0x1502762C, 0x09060500, 0xDA400120, + 0x790EB600, 0x21401300, 0x212F7822, 0x238D0206, + 0x21081B3F, 0xC0040008, 0x013E083F, 0x3D0B2440, + 0x2316762C, 0xDA401440, 0x012008D6, 0x030020F4, + 0x13CB2316, 0x20041B00, 0xDA40762C, 0x012008C2, + 0x130023F4, 0x790EB600, 0x21401300, 0x212F7822, + 0x21080206, 0x24400008, 0x21400404, 0x26401409, + 0x71850406, 0x090AF153, 0x42100000, 0x00200902, + 0x0206202F, 0x202F4608, 0xC1800407, 0x45CB6119, + 0x00030392, 0xC181A9C0, 0x41A16038, 0x04821800, + 0x4222740C, 0x0F8A43E1, 0x240A00E0, 0x254F0480, + 0x740C1401, 0x43E14222, 0x00E00F76, 0x248044C1, + 0x7106203F, 0x77E570F5, 0xC003F50D, 0x203F2580, + 0x003F2080, 0x77267036, 0xFFE205F4, 0xC221C043, + 0x70801600, 0x12208000, 0xD943E803, 0xD928F002, + 0x1405B99F, 0x19013080, 0x19010092, 0x14060012, + 0x19013080, 0x19010012, 0xC0200492, 0x00121901, + 0x30801401, 0x1402A900, 0xA9013080, 0x2480A9C2, + 0x14043805, 0xC6DA341B, 0x40D3C2EA, 0x0C0C902C, + 0x21111000, 0x2D0D2040, 0x214F71ED, 0xB5E02100, + 0x180070CD, 0x40C32004, 0xA48007BF, 0x10151D04, + 0x1DF0702C, 0x1DF093C4, 0x0AFA9384, 0xB5E004A0, + 0xE8069502, 0x04A00A62, 0xF1FCD80A, 0xB5DEB5C0, + 0xB5DEB5FE, 0x24441800, 0x78E0C6CA, 0x70811600, + 0x00088000, 0x00720813, 0x7810B907, 0x77046038, + 0x00412804, 0x7813F006, 0x28057810, 0x79130040, + 0x782E7FE0, 0x0B32C2E6, 0x45080820, 0x16007014, + 0x80007080, 0x74CD0160, 0x11E226CA, 0x0EF2E805, + 0x712CFFAF, 0x1600F009, 0x80007080, 0xB8E20001, + 0x20CA700C, 0x7F1003E1, 0x40E141C1, 0x716C42A1, + 0x70AC708C, 0x00600A9E, 0x700C71CC, 0x42A1702C, + 0x0DCE716C, 0x708C08E0, 0x41C140E1, 0x706C42A1, + 0x70AC708C, 0x00600A7E, 0x710C71CC, 0x42A1702C, + 0x0DAE716C, 0x708C08E0, 0x78E0C6C6, 0x40D3C2F4, + 0x12228000, 0x20911000, 0x46304550, 0x0A942040, + 0x23122940, 0x20801001, 0x046408AF, 0x25132205, + 0x2005C808, 0x47CB04C0, 0x00009004, 0x41C3B802, + 0x000303EC, 0x422278E5, 0x740C90C0, 0x265343C1, + 0x0DCE1144, 0x23AD00E0, 0x0D230982, 0x740C2030, + 0x03ED41C3, 0x0DBA0000, 0x160000C0, 0x80007080, + 0xB8060008, 0x100D2E09, 0x0E0DF00B, 0x26402030, + 0xF007180D, 0x18340E0B, 0x264270AD, 0x2553180D, + 0x25AD114E, 0x0D111982, 0x740C2030, 0x03EE41C3, + 0xF00B0002, 0x20100E0D, 0x03EF41C3, 0xF0050002, + 0x03F041C3, 0x42A10002, 0x00E00D66, 0x6D1643C1, + 0x20082296, 0xC8087E05, 0x04C02005, 0xB8027126, + 0xB7C07F05, 0x0A8EF1A8, 0xC6D405C0, 0x800140C3, + 0x88204E81, 0x70801600, 0x00728000, 0x20447824, + 0x7FE00800, 0x00002078, 0x70801600, 0x008A8000, + 0x7FE0B8C1, 0x00402078, 0x800141C3, 0x89204E89, + 0x70801600, 0x00928000, 0x20447825, 0x7FE00800, + 0x78E0B825, 0x800141C3, 0x89204E77, 0x70801600, + 0x00628000, 0x20847825, 0x7FE00001, 0x78E0B826, + 0x70801600, 0x008E8000, 0x7FE0B8C1, 0x00002078, + 0x70801600, 0x00968000, 0x04002044, 0xB8247FE0, + 0xB7C81CF4, 0x087F4200, 0x1C040065, 0x78523001, + 0x6038700D, 0xB8224340, 0x71044140, 0x7000240A, + 0x20A84308, 0x810005C0, 0xC0427104, 0xC001C402, + 0xC0416098, 0x236FA160, 0x8100003F, 0x00210B0D, + 0xC002718D, 0xA1004409, 0x74247464, 0x240A4089, + 0x20A872C0, 0x82000340, 0xC102C042, 0x7822C001, + 0xC002C041, 0x1A047704, 0xEC0D0010, 0x031041C3, + 0x0C4E0001, 0xD80A00E0, 0x41C3700C, 0x00000311, + 0xC001F00E, 0xC201E810, 0x031241C3, 0x0C320001, + 0xD80A00E0, 0x41C3700C, 0x00000313, 0xFE8F092A, + 0xF008710C, 0xD80AD9C5, 0x00E00C16, 0x700CB912, + 0x341F140C, 0x78E07EE0, 0xB7C81CF4, 0x087F4200, + 0x1C040065, 0x78523001, 0x6038700D, 0xB8224340, + 0x71044140, 0x7000240A, 0x20A84308, 0x810005C0, + 0xC0427104, 0xC001C402, 0xC0416098, 0x236FA160, + 0x8100003F, 0x00210B0D, 0xC002718D, 0xA1004409, + 0x74247464, 0x240A4089, 0x20A872C0, 0x82000340, + 0xC102C042, 0x7822C001, 0xC002C041, 0x1A047704, + 0xEC0D0010, 0x031541C3, 0x0B960001, 0xD80A00E0, + 0x41C3700C, 0x00000316, 0xC001F00D, 0xC201E80F, + 0x031741C3, 0x0B7A0001, 0xD80A00E0, 0x700CD963, + 0x0876B913, 0x710CFE8F, 0x41C3F008, 0x00000319, + 0x00E00B5E, 0x700CD80A, 0x341F140C, 0x78E07EE0, + 0xE18F714C, 0x0FC7238A, 0x22CA7A38, 0xB80E00C1, + 0x0F812005, 0x02EC9004, 0x0240224F, 0x00051900, + 0xB100B140, 0x7FE0B140, 0x00051900, 0x7FE0720C, + 0x00C420AB, 0x2482C3EC, 0x41303204, 0x740C4210, + 0x021241C3, 0x45880000, 0x0B064668, 0x474800E0, + 0x3605120C, 0x120B740C, 0x41C33604, 0x00040213, + 0x3603120D, 0x00E00AEA, 0x3082120D, 0x71001600, + 0x000A8000, 0x007E0815, 0x41C3D8C8, 0x00020214, + 0x0ACE42C1, 0x43A100E0, 0x24407752, 0x27CC3010, + 0xF2039442, 0x0FE640F1, 0x701407C0, 0x7EC0706D, + 0x1FC7208A, 0x9FC0234C, 0x002D006C, 0xE0BF78D0, + 0x002D0052, 0x22C12215, 0xEC259181, 0x211578CE, + 0x90612000, 0x9000EB1F, 0x994078A2, 0x2048780E, + 0x79100000, 0x20157230, 0x20CA22C1, 0x4BB2008A, + 0x7B8E7A4E, 0x0FC72289, 0x2209B100, 0x781000C2, + 0x7A50B141, 0x00A4081B, 0x1902D8FF, 0xB1000005, + 0x2015F007, 0x180222C0, 0x18000005, 0x71650204, + 0xF1CA71C5, 0xA3C0200C, 0x7001248A, 0x02A220E8, + 0x25001002, 0x10141F02, 0x25001002, 0x10141F02, + 0xC7CC700C, 0x1CFCC2FA, 0xC1A8B6C8, 0x31401C04, + 0x41C34520, 0x28F00000, 0x42504078, 0x0042201F, + 0xC0177B3B, 0x009B2D41, 0x1C1C786C, 0x44C33100, + 0x1A3C8000, 0x00962440, 0x31C01C00, 0x31801C14, + 0x00972000, 0x30191460, 0x25802700, 0xC000C042, + 0xD8406849, 0x00952801, 0x800040C3, 0x10B71222, + 0x43500081, 0x00861000, 0x8821C143, 0x222FC144, + 0xC0040187, 0x01DC7210, 0xC003000D, 0x80802011, + 0x221FF2E6, 0x00000F90, 0x225F0A3C, 0xC0020281, + 0x029E265E, 0x2700700D, 0x20002414, 0xC0012010, + 0x21112400, 0xC0467834, 0x9240204C, 0x002D01A0, + 0x3787272F, 0x702D700C, 0x702C706C, 0x436870CD, + 0xF005262F, 0x800043C3, 0x0044C444, 0x44EB0024, + 0x100E249F, 0x092B641C, 0x646B1030, 0x68A9EB95, + 0x12C7242F, 0x4B977BAF, 0x7BCF7C2F, 0x7B7B7B82, + 0x03E50B17, 0x706C702D, 0x46A94161, 0xEB05F006, + 0x4300712D, 0x4361F002, 0xF1DB7104, 0x1030091F, + 0x7ECF782F, 0x12C7242F, 0x7E02DD7F, 0x7EDB7D82, + 0x20CA75D1, 0x21CA030D, 0x70A202CD, 0x8002208C, + 0x41A2F784, 0x0FC12187, 0x7D2F4709, 0x1184279A, + 0x7D0AC000, 0x308021F4, 0x7782702D, 0x03CC2400, + 0x1C8060B8, 0xC005101C, 0x248AE824, 0x27007001, + 0x80001F8B, 0x20A81B40, 0x40E30740, 0x14CC2901, + 0x000E209F, 0x7C8F643C, 0x609845A8, 0xB8816068, + 0x700C7314, 0x40A0F203, 0x271570AD, 0x7125124C, + 0x110E2400, 0xB60074C2, 0x1B00B4A0, 0xF05016C4, + 0x7001248A, 0x0400270A, 0x1440230A, 0x020120A8, + 0x290145EB, 0x259F14C0, 0x6038100E, 0x708D7F0F, + 0x606E65F8, 0xEE2540A0, 0x1180275F, 0x40C3651D, + 0xC1448000, 0x10B00E11, 0x0E1760BC, 0x444A1071, + 0xF0176510, 0x94816510, 0x160C2402, 0x60BEF011, + 0x96816515, 0x160C2402, 0x7F104CB0, 0x22029602, + 0x7ED0200E, 0x20CA76F1, 0x24CA034E, 0x7D90148D, + 0x10040D23, 0xED07C507, 0x25F4C506, 0x60B8120D, + 0x7E1064BC, 0x7DC27D90, 0x0D0B71A5, 0x708D1155, + 0x1B0440A0, 0x71251014, 0x03141F04, 0x21842180, + 0x21842080, 0x26407105, 0xF130305E, 0xF11171C4, + 0x1404C0A8, 0xC6DA341B, 0x4130C2EA, 0xFFEF0AE6, + 0x0D154508, 0x401011F5, 0x203278AD, 0x80000F89, + 0xF00A0D80, 0x41C3700C, 0x00010087, 0xFE6F0CAA, + 0x702D42A1, 0x900446CB, 0x6D0A02D4, 0x01750821, + 0x294096E0, 0x27041289, 0x00001F80, 0x2005C3FF, + 0x1E000240, 0x90077004, 0xC6CAFED4, 0x800040C3, + 0x10B71222, 0x21540086, 0x88612F08, 0x240B2140, + 0x45CB8880, 0x00009004, 0x36071208, 0x83040BDF, + 0x032E0E59, 0x13042C40, 0x7240244A, 0x20A870AC, + 0x25050980, 0x20050100, 0x220501C2, 0xB90202C1, + 0x912079A5, 0x20300817, 0x2205B927, 0xBA020202, + 0x92407AA5, 0x0182226D, 0xB9E06159, 0x21C74121, + 0xB90A03E2, 0x1F8F2704, 0xC3FFFFFF, 0x2556B802, + 0x7F250805, 0xB0E078C5, 0xF1D27185, 0x226FC2E2, + 0x44CB0443, 0x04988000, 0x8A6084A7, 0x7D6C8406, + 0x0001231C, 0x810212FE, 0x231A61B9, 0x219A000D, + 0x40A1041F, 0x141F259A, 0x041F209C, 0x61197BBD, + 0x20798C10, 0x2447004C, 0x799817C0, 0x00002B01, + 0x7905706C, 0xFE6F0892, 0x13002D00, 0x78E0C6C2, + 0xC1A1C3E6, 0x000F2315, 0x260A4008, 0x97013080, + 0x703070AD, 0x002E0120, 0x97204328, 0x21CC7171, + 0x01148005, 0x2B400026, 0x258A1407, 0x27050FC3, + 0x772D0207, 0x334E2616, 0x9E609E01, 0x00E2082B, + 0x0240260A, 0x7A7079AF, 0x40E07B10, 0x00E00C6A, + 0x30C42440, 0x210C4600, 0x14039000, 0x26CA3080, + 0x25090245, 0x9E030005, 0x082D9E62, 0x210A00E2, + 0x79AF1180, 0x7B107A70, 0x0C3E40E0, 0x244000E0, + 0x410830C4, 0x8000260C, 0x30801403, 0x118521CA, + 0x00052509, 0xE5C071A5, 0xFFC5079C, 0x45CB9720, + 0xFFFF0000, 0x02C5091B, 0x0B179701, 0x20021025, + 0x7A1002C0, 0x10402302, 0x20097810, 0xD840008D, + 0x3703121D, 0x02002002, 0x201A780C, 0x204000C1, + 0x780A1040, 0x2509786C, 0x210C0203, 0x20CA9000, + 0x70300245, 0x000521CA, 0x0008208A, 0x02C22002, + 0x7A4CCC1C, 0x71507A0C, 0x004522CA, 0x1FC1204E, + 0x2309792F, 0x16000043, 0x80007081, 0xB9E0000E, + 0xF409705C, 0x10412340, 0x782C792C, 0x20CA7210, + 0x41C30085, 0xFFFF00FF, 0x657D7030, 0x000521CA, + 0x7D25B908, 0xC7C640A1, 0x1200C0E6, 0x70AD3087, + 0x47CB706C, 0x113A8000, 0x0B69710D, 0x2B4001E5, + 0x235A0386, 0x702D0A0E, 0x704C706D, 0xB0A167D8, + 0x0A47B0A0, 0x26050255, 0x21050241, 0x90040F81, + 0x91200200, 0x0A157C2F, 0x28000321, 0x9020130C, + 0x0081210F, 0xF00DB020, 0x71249021, 0xB902B021, + 0x0F0F2184, 0x61F961D9, 0x02C41902, 0x7425B180, + 0x71447165, 0x9020F1DF, 0xB9897164, 0xF1CFB020, + 0x78E0C4C6, 0xC1A1C3E6, 0x16004608, 0x80007100, + 0x4528000A, 0x0980206D, 0x0817E808, 0x080D0050, + 0x1A0000D1, 0xF00700C3, 0x00831A00, 0x1A00F003, + 0x24400043, 0x244030C0, 0x0E123081, 0x42C101E0, + 0xC7C6E802, 0x30821402, 0x308C1403, 0x7B3D6459, + 0x10C12615, 0x91E0AD60, 0x61F99121, 0xB521793D, + 0x7C3D6399, 0x13012615, 0x91E0AD84, 0x61F99121, + 0xB523793D, 0x793D6359, 0xAD287E35, 0x96219640, + 0x793D6159, 0xC7C6B525, 0xC1A2C3E4, 0x45084628, + 0x30011C04, 0xFEAF0E3A, 0x30011C00, 0xD907D841, + 0xDA08B813, 0x708C706C, 0x0FA270AC, 0x70CCFEEF, + 0x742C700C, 0xFF2F0A8A, 0xC080714C, 0x09E241A1, + 0x734CFF2F, 0x700C4508, 0x0A76742C, 0x714CFF2F, + 0xD907706C, 0x744C4060, 0x708CB892, 0x0F6E70AC, + 0x70CCFEEF, 0xD907D880, 0xDA08B893, 0x708C706C, + 0x0F5A70AC, 0x70CCFEEF, 0xFE8F0DBE, 0xB600B802, + 0xC7C440A1, 0x2044781B, 0xD8E40181, 0x7FE07839, + 0x78E0B8C1, 0x01422053, 0x206DA941, 0x20AD0182, + 0x605801C1, 0xA9007FE0, 0x43E3C1A1, 0xFFEF0FEA, + 0xC020C180, 0x30811401, 0x6038B806, 0x74877B20, + 0x1CFCC2FA, 0x2482B6C8, 0x1CC83B06, 0x40383080, + 0x30001CC0, 0x1CC4700C, 0x1C403000, 0x1CFC3018, + 0x1CF83000, 0x1CF43000, 0x14C83000, 0x1CA03000, + 0x20843000, 0x1CA00004, 0x14A03000, 0x1C8C3010, + 0x148C30C0, 0x1CE43001, 0x28413180, 0x1CE02200, + 0x1CAC3140, 0x09AA3100, 0x401000E0, 0x70911600, + 0x000D8000, 0x30001CEC, 0x02A00FBA, 0x46084003, + 0x702CC808, 0x2005B802, 0x90380F80, 0x90E00008, + 0x3F802400, 0x01040000, 0xFE2F0B46, 0x148CDA50, + 0xB8A03000, 0x30001C98, 0x22002144, 0x000D2078, + 0x30001498, 0x00910811, 0xFF8F0E3A, 0x30001CC4, + 0xF004710C, 0x00C00986, 0x30001CBC, 0x40037DC4, + 0x02A00F62, 0x33401CD4, 0x30011498, 0x00B1092D, + 0x24012144, 0x71001600, 0x00148000, 0x04110819, + 0x07800F86, 0x0832E888, 0x701407C0, 0x1CA4710C, + 0xF40B3000, 0xF007700C, 0x00002052, 0x00012178, + 0x1CA47824, 0x148C3000, 0xBFC13000, 0x00002078, + 0x07A00F56, 0x30001C9C, 0x300214C0, 0x024541C3, + 0x148C0005, 0x240A3003, 0x1CD80600, 0x740C3000, + 0x300614AC, 0x00A00A7A, 0x0400250A, 0x300014D4, + 0x00102079, 0x30402042, 0x081B7D0F, 0x1CB001F5, + 0x14B03000, 0xB8C63000, 0x0050080B, 0x300014A0, + 0x1600E88A, 0x80007080, 0xB8E00107, 0x1C94700C, + 0xF2073000, 0x05800B96, 0x1C94710C, 0x27793000, + 0xDA7D1000, 0x30001CB4, 0x148C708E, 0x41DB3000, + 0xC1448000, 0x0080207C, 0x30001CB8, 0x20402040, + 0x30001CCC, 0x3000149C, 0x0F80201F, 0x51E00000, + 0x30001CF0, 0x800070C3, 0x1CD01B3C, 0x14B03000, + 0xB8C63000, 0x00012A01, 0x11C0257C, 0x1CE87824, + 0x2A013000, 0xB8C00340, 0x800045CB, 0x1CDC1221, + 0x14983000, 0x20783000, 0x1CA80080, 0x72963000, + 0x00260702, 0xB89FD825, 0x881B8820, 0x710C7905, + 0x05002800, 0x200FB802, 0x7E2B050E, 0x002106D4, + 0x0D0A730C, 0x1D000120, 0x148C1502, 0x24553001, + 0x14E03F42, 0x24553004, 0x14A43FC3, 0x202F3005, + 0x43180507, 0x01600CB2, 0x300614D4, 0x300014A0, + 0x00002079, 0x100115BB, 0x30001C90, 0x14904063, + 0x0A623002, 0x14900320, 0x14D83003, 0x7FCF3000, + 0x3003148C, 0x3F452455, 0x30061490, 0x14CCC182, + 0x42033007, 0x093E44E1, 0x43F10060, 0x300014AC, + 0x14A870AE, 0xC3823001, 0x35441C0A, 0x300214E8, + 0x02200C8E, 0x30431C0C, 0x300014A4, 0xC808E839, + 0x15B8700D, 0x15021086, 0x8DE11089, 0x78EF68D2, + 0x1004095F, 0x002E0E57, 0x038C2840, 0x7240244A, + 0x70EC7CC5, 0x20A8706C, 0x205F0600, 0x24000501, + 0x00003F82, 0x623A015C, 0x02812F40, 0x22147985, + 0x210501CB, 0x90040F81, 0x91200320, 0x633B71E4, + 0x10441B00, 0x3F812400, 0x01540000, 0x78707914, + 0x02402845, 0x02041A12, 0x71E5B100, 0x14B0F1D1, + 0x08173000, 0x14A801D5, 0x14DC3001, 0x20053000, + 0xF207807E, 0x1498F00D, 0x08173000, 0x16000090, + 0x80007080, 0x2044000B, 0x2D410815, 0x0C9B2155, + 0x0D972011, 0x70ED2030, 0x310B1412, 0x3108140E, + 0x12C02002, 0x31071410, 0x00072700, 0x15B8C808, + 0x15021085, 0x8DC11084, 0x00862840, 0x0C6B7BCF, + 0x0D6300C4, 0x2B4000EE, 0x704C0389, 0x11892105, + 0x0501235F, 0x3F802400, 0x015C0000, 0x02750A45, + 0x20146038, 0x2A400081, 0x20050280, 0x20050240, + 0x90040F80, 0x90000320, 0x02CC2000, 0x1325080D, + 0x1900B100, 0xF00C01C4, 0x710C1600, 0x013A8000, + 0x0325080B, 0xB1E07882, 0xB100F002, 0xF1DA7144, + 0x71C5B0E9, 0x14B8F1CC, 0x14B43001, 0x790B3000, + 0x8DE1F233, 0x8D027EEF, 0x0384085F, 0x800040C3, + 0x880012D9, 0x03AE084F, 0x094A41C1, 0x14C80660, + 0x43083000, 0x13002E40, 0x244AC107, 0x79057280, + 0x7825C808, 0x6872702C, 0x054020A8, 0x104E0B25, + 0x150C265F, 0x3F822400, 0x01040000, 0x2940645C, + 0x7A650282, 0xBA927C34, 0xBA9FBA9C, 0xB4409240, + 0x71E57124, 0xDA23F1D0, 0xBA0A4023, 0xFDEF0F82, + 0x14D8702C, 0xE8093000, 0x40C3702C, 0xBE248000, + 0xFDEF0F6E, 0x1412DAA0, 0x14103112, 0x0A4D310E, + 0x210A23A5, 0x140D2500, 0x70143080, 0x000102E4, + 0x108B15B8, 0x8D218D42, 0x31031410, 0x7050782F, + 0x000D03C2, 0x102E0B21, 0x7240244A, 0x0F80201F, + 0x0A3C0000, 0x020020A8, 0x300C14D0, 0x2080641C, + 0xB4600184, 0xF1EC7124, 0x31171414, 0x20162479, + 0x2E812185, 0x2A162640, 0x900740D3, 0x14ACC29C, + 0x08A13000, 0x14980010, 0x08133000, 0x79CF00B1, + 0x0F324063, 0x734CFE6F, 0xC808F044, 0x108815B8, + 0x108B1502, 0x8D016852, 0x0B55790F, 0x084D1044, + 0x2940106E, 0x0D3B038C, 0x7C452030, 0x0501215F, + 0x3F832400, 0x015C0000, 0x7240244A, 0x633B702D, + 0x038020A8, 0x12812940, 0x024F23F4, 0x67DF7985, + 0x21057125, 0x90040F81, 0xB1E00320, 0x2405F006, + 0x90041F81, 0xB1C03F20, 0xF1D87104, 0x000440C3, + 0x0A8293E0, 0x702C0420, 0x300114B8, 0x300014B4, + 0xF208790B, 0x70801600, 0x001D8000, 0xF4D0B8E0, + 0x1C0AC808, 0xB8023384, 0x0F802005, 0xC0049007, + 0x00051800, 0x7014C022, 0xF217C082, 0x3101140E, + 0x3F432455, 0x30051490, 0x3FC42455, 0x300614A8, + 0xC1404263, 0x3001148C, 0x4003C041, 0x02200ED2, + 0x3007149C, 0x148CF012, 0x24553001, 0x14C03F45, + 0x704C3003, 0x300414BC, 0x30061490, 0x30071494, + 0x09C6C040, 0x40030060, 0x300014C4, 0xF2917014, + 0x30001494, 0x0F247014, 0x1C1C0561, 0x710C3580, + 0x012009D6, 0x40034162, 0x0FC24162, 0x704C0020, + 0x08C1C022, 0xC0820030, 0x24051800, 0xE81CCA00, + 0x2940702C, 0x228A0380, 0x20050004, 0x90040F80, + 0xB04002F8, 0x7200244A, 0x0010228A, 0x020020A8, + 0x00832005, 0x00102280, 0x00051B00, 0xCA007124, + 0x800409D3, 0x3101140E, 0x1490C082, 0x24553005, + 0x14A83F43, 0x24553006, 0x149C3FC4, 0x42633007, + 0x4003C041, 0x0E1AC140, 0x732C0220, 0x43C3702C, + 0x4FA08001, 0x0945CA00, 0x29400025, 0x700D038B, + 0x0833700C, 0x71ED0255, 0x30021494, 0x70547F18, + 0x900442C3, 0xF20702F8, 0xBC0A630C, 0x12CC2405, + 0x2305F003, 0x7A85120C, 0x10102080, 0x7104B2E0, + 0xE309F1E9, 0xF1E07124, 0x1800D820, 0xF0102004, + 0x300314C0, 0x300414BC, 0x3F452455, 0x4003C040, + 0x704C732C, 0x08C270CC, 0x71EC0060, 0x30001494, + 0x0AB87014, 0x14EC05C1, 0x40033002, 0x00200ECE, + 0x700C4162, 0x012008D2, 0x1C1C4162, 0x76E23440, + 0x705278D0, 0xFFCE05CA, 0xFFCF056F, 0x108B15B8, + 0x8D827FD0, 0x796F8D61, 0x06587191, 0x0B41FFCD, + 0x2400104E, 0x00003F80, 0x20F40154, 0x16000042, + 0x80007080, 0x6058011B, 0xD81170F1, 0x1600F7CA, + 0x80007080, 0x4A10011C, 0xD89170F1, 0x006B20CA, + 0x2105B90E, 0x90040F81, 0xB1003ED4, 0xF1DD7164, + 0x08C1C022, 0x140E0030, 0x8DE13113, 0x8D0279EF, + 0x006408E3, 0x40C34030, 0x12D98000, 0x08A18800, + 0x70CD042E, 0x1291275E, 0x0447202F, 0x01A00DE2, + 0x205F4210, 0x14CC2502, 0xC182300C, 0x248A7C09, + 0x623A7001, 0x923A7AD4, 0x41C3643C, 0x28F00000, + 0x2043241A, 0x201FB922, 0x14F02041, 0x627A3002, + 0x41C1623A, 0x0184219A, 0x2300623B, 0x80000F81, + 0x43681B3C, 0x708DB180, 0x078020A8, 0x300114D4, + 0x43627A8F, 0x62197A39, 0x218C704C, 0xF74C8002, + 0x215A4242, 0x229F0181, 0x623A000E, 0x06432234, + 0x92417223, 0x13012315, 0x71C37185, 0x1A3C8000, + 0xB141B160, 0x0E7571C5, 0x712692B4, 0xF1A871E5, + 0x3FC02455, 0x916A4183, 0x41629149, 0x240AC041, + 0x149C0540, 0x24003000, 0x00003F85, 0x14CC015C, + 0xC0403007, 0x300014AC, 0x00062078, 0xFFAF094A, + 0x149C4063, 0x40633001, 0x30021490, 0x300314C4, + 0x01A00A06, 0x300414E4, 0x300114B8, 0x300014B4, + 0xF234790B, 0x7EEF8DE1, 0x08618D02, 0x40C30384, + 0x12D98000, 0x08518800, 0x41C103AE, 0x06200CB6, + 0x300014C8, 0x2E404408, 0xC1071300, 0x7280244A, + 0xC8087905, 0x700C7905, 0x20A86952, 0x0C270580, + 0x265F100E, 0x24001503, 0x00003F81, 0x61790104, + 0x000321F4, 0x02812840, 0xB9927945, 0xB99FB99C, + 0x7104B160, 0xF1D171E5, 0x0A9EC082, 0x702C0020, + 0x300014D0, 0x20967186, 0x01070794, 0x1CD0FFEF, + 0x14943000, 0x70143000, 0x05C208A0, 0x3B062480, + 0x341B1404, 0x78E0C6DA, 0x4110C2EA, 0x70801600, + 0x00088000, 0x08114548, 0x462800B1, 0x2280204A, + 0xF00574ED, 0x2240204A, 0x088272ED, 0x208AFEEF, + 0x0EC1080C, 0x208A1275, 0x08B90144, 0x0923038E, + 0x706C2030, 0xFECF0872, 0xD907706C, 0x724C4060, + 0x708CB88F, 0x0DB670AC, 0x70CCFEAF, 0xD907F00C, + 0xDA184060, 0x708CB88F, 0x0DA270AC, 0x70CCFEAF, + 0xFECF0846, 0xD907700C, 0x706C704C, 0x45A1708C, + 0xFEAF0D8A, 0x704C70CC, 0x4648752C, 0xBE94DB80, + 0x40C1708C, 0x0D7645A1, 0x70CCFEAF, 0xD9296E13, + 0x706C42E1, 0x45A1708C, 0xFEAF0D62, 0x01C0264A, + 0x30821204, 0xD907700C, 0x708C706C, 0x0D4E45A1, + 0x70CCFEAF, 0xD907700C, 0x706C704C, 0x45A1708C, + 0xFEAF0D3A, 0x78DB70CC, 0x704C752C, 0x0004238A, + 0x45A1708C, 0xFEAF0D26, 0xD84170CC, 0xF03CD92A, + 0x20300921, 0x0FC2706C, 0x706CFE8F, 0x4060D907, + 0xB88F724C, 0x70AC708C, 0xFEAF0D02, 0xF00D70CC, + 0x4060D907, 0xB88FDA28, 0x70AC708C, 0xFEAF0CEE, + 0x0F9670CC, 0x700CFE8F, 0xDA08D907, 0x708C706C, + 0x0CDA45A1, 0x70CCFEAF, 0xD907700C, 0x706C704C, + 0x45A1708C, 0xFEAF0CC6, 0x704C70CC, 0x4040752C, + 0x0004238A, 0x708CB895, 0x0CB245A1, 0x70CCFEAF, + 0xD92BD841, 0x42E1B812, 0x708C706C, 0x0C9E45A1, + 0x264AFEAF, 0x700C01C0, 0x744CD907, 0x708C706C, + 0x0C8A45A1, 0x260AFEAF, 0x0F160400, 0x700CFE8F, + 0x704CD907, 0x708C706C, 0x0C7270AC, 0x70CCFEAF, + 0xD907700C, 0x706C704C, 0x70AC708C, 0xFEAF0C5E, + 0x0AC670CC, 0x7704FE4F, 0x78E0C6CA, 0x88A0C0E6, + 0x900743C3, 0xED07C2CC, 0x00051B00, 0x00051B04, + 0x248AF005, 0xB3801FC7, 0x1600B382, 0x80007083, + 0x23780008, 0x6B920103, 0x900743C3, 0xED16C2C0, + 0x1B04B380, 0x09130085, 0xDB1000F5, 0x26F47B2D, + 0x800070C3, 0x908810BC, 0x23CF7295, 0x1E000361, + 0x900770C4, 0xF007C29C, 0x1C0C2445, 0x1B04B380, + 0x43C30045, 0x12228000, 0x008B13B7, 0x8BC08BE1, + 0x0F417BCF, 0x0B3910C4, 0x201410EE, 0x091300CC, + 0xDD0A0070, 0x1C24E988, 0x75AD1285, 0x1C24F007, + 0xF0051145, 0x1C24DD0F, 0x09151005, 0x221400B5, + 0x130000C3, 0x0B0900C3, 0xB4B20013, 0xF1E271C5, + 0x78E0C4C6, 0x702CC0F1, 0x900742C3, 0x1E00C2C0, + 0x90077044, 0xB220FED4, 0x1E00B222, 0x90087044, + 0x800801E4, 0x2005B802, 0x90070F80, 0xB020C000, + 0x002009E2, 0x80441ADC, 0x01800C2A, 0x7EE0C0D1, + 0x46C8C2F2, 0x47084528, 0x416040C1, 0x21C0250A, + 0x2140220A, 0x2100200A, 0x0E364170, 0x43500060, + 0x40E14410, 0x704C41A1, 0x240A4322, 0x250A0400, + 0x46C10480, 0x0020085E, 0x0540270A, 0xEF0870CD, + 0x000040C3, 0x0C32FFFF, 0x712C05E0, 0x4102D840, + 0x70041E00, 0x01E49008, 0x42828508, 0x2005B802, + 0x90070F80, 0x1800C000, 0x1E000045, 0x90077384, + 0x099AC29C, 0x40620020, 0x41628D00, 0xFFEF0CDE, + 0xA5074202, 0x412240A1, 0xFFEF0E86, 0xC6D24242, + 0xC1A1C3F0, 0xD8314608, 0x4528A108, 0x210AC808, + 0xA9C02180, 0xAD24702C, 0x2140230A, 0x200AA526, + 0xB8022100, 0x20054270, 0x90380F80, 0x90E00008, + 0xA522B521, 0x07600C66, 0x11C41D10, 0x20F00A2B, + 0x0A31AD05, 0x204B2070, 0x0A35A140, 0x204B20B0, + 0x0A33A140, 0x204B2031, 0xF21DA140, 0x14811D18, + 0x14011D14, 0x204BF025, 0xF21AA140, 0xF020D828, + 0x1D18F218, 0x1D141401, 0xF01B1481, 0xD87AF217, + 0x700CF016, 0x022541C3, 0x0BEE0001, 0x4242FDEF, + 0x1D18F00F, 0x1D1414C1, 0xF00B1441, 0xF008D829, + 0x14411D18, 0x14C11D14, 0xD87BF003, 0x0A91A505, + 0x275320B5, 0xF244907E, 0x10310E85, 0x20112179, + 0x800047CB, 0x8FC01222, 0x0402202F, 0x22112140, + 0x20522279, 0x00542044, 0x08658F01, 0x40C30384, + 0x12D98000, 0x08558800, 0x7ACF03AE, 0x41424022, + 0x01600EBA, 0x089E4382, 0xC18001A0, 0x23802314, + 0x00C11000, 0x09C2C080, 0x21BF0360, 0x0CEE0FFF, + 0xE80D0040, 0x30801401, 0xF789E0C0, 0x003F2080, + 0x30021C01, 0x7104C020, 0xC080C060, 0x00200EF6, + 0x13902514, 0x2004182C, 0xF1D071C5, 0x78E0C7D0, + 0x42C3700C, 0x0000901C, 0x900741C3, 0xB200F800, + 0x00151984, 0x00041A44, 0x80151980, 0x191CB202, + 0x19040015, 0x19040015, 0x19080015, 0xB1000015, + 0x7FE0B102, 0x78E0B104, 0x4050C2EA, 0x082D4130, + 0x45080275, 0x000046CB, 0x2025FFFF, 0xF0310340, + 0xF008F015, 0xF006F016, 0xF01CF018, 0xF026F01E, + 0x000046CB, 0xF025A536, 0x41C3700C, 0x00010224, + 0xFDEF0AC6, 0x70CD42A1, 0xDEFFF01B, 0xF019BE08, + 0x000046CB, 0xF015AAAA, 0x000046CB, 0xF011B2B2, + 0x000046CB, 0xF00D8241, 0x800040C3, 0x88C10104, + 0xBE088820, 0xF0057E25, 0x000046CB, 0x70165A3C, + 0x0A26DFAA, 0x27CA0760, 0xE8061021, 0x708F1600, + 0x01068000, 0x08E96D0B, 0x26040155, 0x00001F81, + 0xB928FF00, 0x42E178CF, 0x0B8A43E1, 0x240A05E0, + 0x16000440, 0x80007080, 0x72140008, 0x901C41C3, + 0x40C30000, 0xF8009007, 0x1900F406, 0x18000005, + 0xF0060005, 0x00451900, 0x00451800, 0x12300DA7, + 0x0D59D8FF, 0x0D551110, 0x0DF111D0, 0xD9441031, + 0x901C40C3, 0x45CB0044, 0xF8849007, 0x00851800, + 0x90951D80, 0x804418C0, 0x0EC64002, 0x1D0005E0, + 0x700C1105, 0x901F41C3, 0x7AD0C00C, 0xB518B516, + 0xB51A4340, 0xB1004440, 0xB1024540, 0xB504712C, + 0x02200DE6, 0xC6CAB506, 0x900745CB, 0x1D04F830, + 0x704C13D4, 0x0FC7208A, 0x0388242F, 0x722CB540, + 0x700CB502, 0x250A706C, 0x0DBE0100, 0x47480220, + 0x1C012542, 0x901F40C3, 0x1900C00C, 0x1D500085, + 0xB0E013C4, 0xB1E4B0E2, 0xC6CAB1E6, 0x90500D1F, + 0x45CBF199, 0xF8209007, 0x13D41D04, 0x10151D04, + 0x1D08700E, 0x7AD01014, 0x13D41D04, 0x901F47CB, + 0x1D00C004, 0x25421404, 0xB5021C11, 0xB700D844, + 0x722C700C, 0x44404340, 0x0D5E4540, 0x19000220, + 0x1D502105, 0x1F081404, 0x1F0C1404, 0x19081404, + 0x190C2404, 0xC6CA2404, 0x70051E00, 0xF8049007, + 0x78E0C6CA, 0x1CFCC2FA, 0xC1BFB6C8, 0x47084338, + 0xC08B70CE, 0xDA50702C, 0x31C01C00, 0x2140200A, + 0x31801C08, 0x31001C04, 0x1C28C348, 0x0C123580, + 0x1C24FDAF, 0xC8083580, 0x308D237C, 0x2005B802, + 0x90380F80, 0x90000008, 0x2079B8C1, 0x6F0B000E, + 0x039C7514, 0x71F50026, 0x00400A66, 0x25044610, + 0x0B0F1395, 0x712F3070, 0x21CA70D6, 0x47CB3541, + 0x12228000, 0x25802504, 0x300E14B8, 0x71148F60, + 0x202F8F41, 0x223C058A, 0x25CA00C1, 0x78252021, + 0x003F081B, 0x40614368, 0x7104790F, 0x10412614, + 0x00051924, 0x0AF5790F, 0x23788045, 0x737730C0, + 0x1618E009, 0xC0431017, 0xC044700C, 0x026120CA, + 0x8605C044, 0x9608C045, 0x30300969, 0xC808C047, + 0x12C0200A, 0x108717B7, 0x05C02005, 0x10861701, + 0x212F6892, 0x0E4D0207, 0x0F450044, 0x2940006E, + 0x215F0383, 0x7B850289, 0xC203700C, 0x00850831, + 0xEA88C202, 0x06822100, 0x0082121C, 0x0080081D, + 0x02422000, 0x7D54C58B, 0x02822840, 0xBA927A65, + 0xBA9FBA9C, 0xB5409240, 0xF1E97104, 0xF1DB7105, + 0x40CB7377, 0x0F000000, 0x20002552, 0x102120CA, + 0x800040DB, 0xC04612D9, 0x02C7222F, 0x08678F01, + 0x10000084, 0x085B3080, 0x2A4000AE, 0xC0050303, + 0x02012305, 0x900444CB, 0x79050000, 0x7905C808, + 0x208D20F4, 0x7985B902, 0xC106B1A0, 0xB040210B, + 0x2305F20B, 0x210505C1, 0x78250201, 0x7C05B802, + 0x208020F4, 0x0D1BB400, 0x26142030, 0x23051080, + 0x903605C3, 0x208020F4, 0xFEEF0B52, 0x7165C201, + 0x0C12F1CC, 0x8F610540, 0x0B458F20, 0x7A2F0044, + 0x2A407124, 0x2614038B, 0x2305108C, 0x90041F80, + 0x900002D4, 0x20849492, 0xBC0A040E, 0x204F7885, + 0x2305000C, 0x90041F80, 0xB0803ED4, 0x7854C089, + 0x208220F4, 0x782FB040, 0x80050BC7, 0xFEAF09BE, + 0x09CAD8C8, 0x960EFEAF, 0x248A702E, 0xC0082002, + 0xFE6F0D42, 0x1700712C, 0x8F211093, 0x24C7202F, + 0xA040200C, 0x002D0152, 0x0FCF228A, 0x30801000, + 0x84002011, 0x2440F29F, 0xC507390B, 0x140123F4, + 0x140B2314, 0x30B50B37, 0xB9C6653D, 0x6038C007, + 0x8002208C, 0x2555F796, 0x0D2D180D, 0x1B002030, + 0x26141344, 0xC2011400, 0x23032840, 0x23059036, + 0x0A8A05C3, 0x78B0FEEF, 0x1B00F006, 0xF0351344, + 0x13441B00, 0x119E0D63, 0xE82FC001, 0x180D2554, + 0x20300D1F, 0x13441B00, 0x14002614, 0x23032840, + 0x05C32305, 0x9036714C, 0xFEEF0A52, 0x0E3B78B0, + 0x28402031, 0xD90F238C, 0x1F802405, 0x02D49004, + 0x26149060, 0x90521400, 0xB0327946, 0x0F802304, + 0xC3FF0000, 0x7905B90A, 0x1F802405, 0x3ED49004, + 0x1300B020, 0x2840110D, 0xC8082302, 0xC0057A05, + 0x41C37845, 0x3C009004, 0x7825B802, 0xC006B0A0, + 0xB000210B, 0x2205F208, 0x6A1205C2, 0x13007825, + 0xB0201101, 0x23802840, 0x0F802005, 0x26FC9004, + 0x01121000, 0xC002C504, 0xE88E7AAF, 0x02110A09, + 0xE89CC000, 0xE888C000, 0x26802000, 0x0080101C, + 0x00000A29, 0xE8098E04, 0x11041602, 0x0447232F, + 0x4102C000, 0xC000F006, 0x0448242F, 0x706C4102, + 0x04A00C7A, 0x0480250A, 0xC00371A5, 0x09BB79AF, + 0x71668004, 0x40C3F153, 0xC2EC9007, 0xB0407126, + 0x21FD248D, 0x00051800, 0x3010095D, 0x108B17B7, + 0x7C4F8F40, 0x03040951, 0x132E0B49, 0x13002C40, + 0x128D245F, 0x05C32005, 0x7865C808, 0x68D2706C, + 0x0B31C003, 0xC0020005, 0x2400E887, 0x101C1680, + 0x0B1D0080, 0x63BF0000, 0x20F4C08B, 0x2B4003CF, + 0x78C50280, 0xB89CB892, 0xB0E0B89F, 0xF1EA7164, + 0xF1D97144, 0x1404C0BF, 0xC6DA341B, 0xFFC1046C, + 0xFFCF046F, 0x0F812032, 0x0E9C8000, 0x02150809, + 0xF0037933, 0x7FE0B9C2, 0x78E0782D, 0x78E07EE0, + 0x70C51E00, 0x0088900C, 0x78E07EE0, 0x0926C0F1, + 0x0862FD8F, 0x4608FD8F, 0x4528CA09, 0x09807014, + 0xC1A10361, 0xC040C086, 0x70801600, 0x00128000, + 0x10240E0D, 0x0D5E40A1, 0xC1000720, 0x7014CA09, + 0x07010A10, 0xDC247487, 0xFD8F009B, 0xC1A2C3E8, + 0x45284050, 0x41C34200, 0x00010361, 0xFFEF0FB2, + 0xED23750C, 0x70CD704C, 0x7100244A, 0x4040702C, + 0x024020A8, 0x20F4C380, 0x7B34200C, 0x712460B8, + 0x1406B380, 0x750C3106, 0x31041402, 0x036241C3, + 0x14040005, 0x0F7A3105, 0x1400FFEF, 0x71C53103, + 0x0AC97AD0, 0xC7C88344, 0x02550A15, 0x215FE808, + 0x621A0240, 0x0F822232, 0x4FA08001, 0x40407FE0, + 0x88008821, 0x7FE0B807, 0x78E06038, 0x88008821, + 0x7FE0B806, 0x78E06038, 0x216C791D, 0x20530142, + 0x20840141, 0x60380001, 0x60587FE0, 0x00432801, + 0x2B007A69, 0x78220041, 0x7FE0621A, 0x78E07850, + 0x215FC0E4, 0x44CB0A03, 0x113A8000, 0x647970CD, + 0x639291A1, 0x0E257A04, 0x23151365, 0x61990381, + 0x790B9122, 0x79DBF208, 0x00412314, 0x91236199, + 0x0042220F, 0xF1F171C5, 0xC4C47850, 0xC1A4C3F2, + 0x70931600, 0x00048000, 0x02E341C3, 0x0EC20000, + 0x740CFFEF, 0x800145CB, 0x6DCB4E77, 0x19152554, + 0x02200CC6, 0x40C140C1, 0x05600F66, 0x40C1D90B, + 0x05600F5E, 0x40C1D911, 0x0A7ED912, 0xDAEFFEAF, + 0x0F4E40C1, 0xD9120560, 0x0F4640C1, 0xD9290560, + 0x05600BEA, 0x0BE640C1, 0x40A20560, 0x800140C3, + 0x0BDA4F0A, 0x42100560, 0x800140C3, 0x0BCE4F55, + 0x41100560, 0x10C01603, 0x8E3670ED, 0x800040D3, + 0x8E4D1220, 0x23C218B8, 0x23C41800, 0x017E0A11, + 0x238018BC, 0x00120809, 0x011E0933, 0x092F7905, + 0xB88601BF, 0x154BAD00, 0xB8861080, 0x10021D4B, + 0x10801596, 0x1D96B886, 0x15E11002, 0xB8861080, + 0x10021DE1, 0x07200862, 0xC808710C, 0x40C36832, + 0x0504901C, 0xB1E07905, 0x10C3276F, 0x804518A4, + 0x773541C3, 0x8F009400, 0x80822044, 0x001E40C3, + 0x45088480, 0x104125CA, 0xE9098F38, 0x02E541C3, + 0x0DCE0000, 0xD80AFFEF, 0x7054F047, 0x0BEB41C3, + 0x20CAC200, 0x09DE0041, 0x702C03A0, 0x70801600, + 0x000D8000, 0x00BE080B, 0x09DED840, 0x0D960700, + 0x40C3FFCF, 0x019B8000, 0x10FF8820, 0x20058080, + 0xF21A807E, 0x201A782A, 0x000F0F80, 0x09CA4240, + 0x702C03A0, 0xC8094200, 0x010421AA, 0x09237912, + 0x23AA0085, 0x08FF0104, 0x20AA80C4, 0x50320144, + 0xF0097A22, 0x097E40A1, 0x702C03A0, 0x621AF00D, + 0x21AAC80A, 0x090F0104, 0x23AA00A5, 0x08F70144, + 0x20AA80C0, 0x16000104, 0x80007080, 0xB8E0000D, + 0x06C20F78, 0x03C008CE, 0x800045CB, 0x8D001138, + 0x0010088B, 0x08878F00, 0x0DE200DF, 0x0EF20080, + 0x8D00FDCF, 0x704C708E, 0x8F00E806, 0x02002044, + 0x00022078, 0x0B4A700C, 0xD908FE6F, 0x081F8D01, + 0x704C00B4, 0xE8078D00, 0x20448F00, 0x20780200, + 0x700C0002, 0xFE6F0B2A, 0x8D00702C, 0xE807704C, + 0x20448F00, 0x20780200, 0x700C0002, 0xFE6F0B12, + 0x8D00D90A, 0x8F00E806, 0x02002044, 0x00142078, + 0x702CD808, 0xFE6F0AFA, 0x8D004282, 0x8F00E80E, + 0x02002044, 0x00022078, 0x40C3F009, 0x8480001E, + 0x03A008B2, 0xF00F702C, 0x700C704C, 0xFE6F0AD2, + 0x0C42D996, 0x700C0580, 0xFE2F0F82, 0x0CC2712C, + 0x160000C0, 0x80007080, 0x081502FE, 0xD95D003E, + 0x0C5ED80A, 0xB913FFEF, 0x07400AFA, 0x0BE2C080, + 0x235305A0, 0xC08020D3, 0x00A008BE, 0x40C1D91C, + 0xC280702C, 0x708CDBFF, 0x07600BD2, 0x0B5A70AD, + 0x0BBE0000, 0xC08005A0, 0x089EC080, 0xD91000A0, + 0x0896C080, 0xD91C00A0, 0x712C40C1, 0xDBFFC280, + 0x07600BAA, 0x40C1708C, 0x04E00E4E, 0x40C1D90B, + 0x04E00E46, 0x40C1D911, 0x04E00E3E, 0x40C1D912, + 0x04E00E36, 0xCA0ED929, 0x10050D2F, 0x2B02235F, + 0x1F812532, 0x04788000, 0x7AB561CB, 0x720271A5, + 0x2132AA68, 0xAA6A0483, 0x05432132, 0x04412132, + 0xAA2BAA69, 0x0CEAF1EA, 0xD96EFE8F, 0x11C5B99F, + 0x19018480, 0x21400012, 0x21400EC2, 0x12010683, + 0xA9000480, 0x04801201, 0x00121B01, 0x04801205, + 0x1201AB00, 0xA9010480, 0x04801201, 0x1201A902, + 0xAB010480, 0x04801201, 0x1276AB02, 0x1A8B0480, + 0x12018012, 0x43400480, 0x000A1B79, 0x04801201, + 0xAC006B85, 0x121D6C25, 0x19010480, 0x12010012, + 0x1A560480, 0x12010002, 0xAB010480, 0x04801201, + 0x1211AC01, 0x19010480, 0x12010012, 0x1A430480, + 0x8A000002, 0x8A01AB02, 0x8A02AC02, 0x197CE227, + 0x12010012, 0x19010480, 0x12010012, 0x19010480, + 0x12010012, 0x19010480, 0x12010012, 0x19E70480, + 0x12018012, 0x19050480, 0x12010012, 0x19050480, + 0x12010012, 0x19050480, 0x12010012, 0x19010480, + 0x12010012, 0x21420480, 0xAB0003C3, 0x028C2142, + 0x04801201, 0xAC0069AD, 0x04801201, 0x1201AD00, + 0x19010480, 0x12010012, 0xAB010480, 0x04801201, + 0x1201AC01, 0xAD010480, 0x04801201, 0x1201A900, + 0xAB020480, 0x04801201, 0x1201AC02, 0xAD020480, + 0x04801201, 0x1201A901, 0x19F30480, 0x8A008002, + 0x800219F8, 0x19FD8A01, 0x8A028002, 0x1600A902, + 0x90387101, 0x12260034, 0x080D8080, 0x704C01BF, + 0xF011B9A0, 0x70801600, 0x01648000, 0x013F0817, + 0x1600B980, 0x80007080, 0xB8E6001F, 0x22CA724C, + 0x1E000061, 0x903B7044, 0xC808C034, 0x2005B802, + 0x903B0F80, 0xB040C008, 0x78E0C7D2, 0x40C3C5E1, + 0x12228000, 0x706C88A1, 0x704C8880, 0xCA00702C, + 0x00050921, 0x03040909, 0x10450D0F, 0x0F802205, + 0x3ED49004, 0x7124B060, 0x000072C3, 0xF1F14000, + 0x78E0C4C2, 0x1C00DC3F, 0x7C0F0302, 0x080DB830, + 0x4C3100A5, 0xF00A4852, 0x00250B09, 0xF0064872, + 0x704C7831, 0x00021C00, 0xCC1D792C, 0x0003211A, + 0x221ACC1C, 0x782C0081, 0x60787FE0, 0x44CBC0F1, + 0x01078000, 0x42008C60, 0x003F0B2D, 0x0B29710C, + 0x700C007F, 0x7234B9A0, 0xFEC20C9C, 0x40C3F40B, + 0x4E778001, 0x9081145B, 0x78258800, 0x207A780D, + 0x78440000, 0x7EE0C0D1, 0x71001600, 0x00068000, + 0x0F80203C, 0x0C800000, 0x78E07EE0, 0x06C3216F, + 0xB8E68900, 0x7CE0700C, 0x20448907, 0x7FE00200, + 0x78E0B823, 0x4528C2E4, 0xFDEF0B26, 0xEE1E4608, + 0x05800926, 0xD925700C, 0xDB86704C, 0x45A1708C, + 0xFE2F0C8A, 0x700C70CC, 0x704CD926, 0x708CDB86, + 0x0C7A70AC, 0x70CCFE2F, 0xD910700C, 0xFE2F0F62, + 0x08D2714C, 0xF00C0580, 0x10452553, 0xD919D880, + 0xDB86744C, 0x0C56708C, 0x70CCFE2F, 0x0BFE700C, + 0x712CFE2F, 0x40C3EE87, 0x75300000, 0x03600D06, + 0xC6C4D91E, 0x0C46C0F1, 0x730C0060, 0x800040C3, + 0x88001138, 0x1600E810, 0x80007080, 0x08190001, + 0x098A00DF, 0x710C0080, 0xFFEF0F6E, 0x0902D90F, + 0xF00600C0, 0x0F62700C, 0xD90FFFEF, 0x7EE0C0D1, + 0x4430C2F0, 0xFEEF0BA2, 0x46CB4110, 0x12DC8000, + 0x43108620, 0x800140C3, 0x88E04E77, 0x0442202F, + 0x70901600, 0x00628000, 0x704CB8C0, 0x0976706C, + 0x42100260, 0x900745CB, 0x0A0AC17C, 0x1D000520, + 0x0A3E1005, 0x708CFDCF, 0x4080752C, 0xB895714C, + 0x0004238A, 0x0440250A, 0xFE2F0BA2, 0xD88070CC, + 0xB892D90F, 0x706CDA20, 0x0500240A, 0x0440250A, + 0xFE2F0B8A, 0x700C70CC, 0xFE2F0B32, 0x2705712C, + 0x78ED140F, 0x20310B0F, 0x10451D00, 0x00120807, + 0x8620C6D0, 0x00022084, 0x01C32841, 0x09064042, + 0x42620260, 0x78E0C6D0, 0x0B62C2E6, 0x730C0060, + 0x72ED70CD, 0xB89FD825, 0x881B8820, 0x710C7905, + 0xB80278D8, 0x0380200F, 0xF259782B, 0x712C7D0F, + 0x056009EE, 0x09AA40A1, 0x0AF2FDCF, 0xE00C0140, + 0x7A0F752C, 0xB813D809, 0x0008238A, 0x45A1708C, + 0xFE2F0B0A, 0x269F70CC, 0x700C12C1, 0xDA22762C, + 0x03C0244A, 0x70CC45A1, 0x1F8E2632, 0x4E838001, + 0xFE2F0AEA, 0x11C3264F, 0x002D40C3, 0x0BB6C6C0, + 0x712C0360, 0x700C7910, 0xFE2F0DC6, 0x700C704C, + 0xDA22762C, 0x244A43C1, 0x45A103C0, 0xFE2F0ABE, + 0x700C70CC, 0xDA08752C, 0x000E238A, 0x45A1708C, + 0xFE2F0AAA, 0xD88070CC, 0xB893D907, 0x706C744C, + 0x70AC708C, 0xFE2F0A96, 0x700C70CC, 0xFE2F0A3E, + 0x40A1712C, 0x0560094A, 0x278D702C, 0x71CD17BE, + 0x78E0C6C6, 0xB7C81CF4, 0xC181C808, 0x1C08714C, + 0x0DEA3001, 0x1C0404A0, 0x41C33001, 0x0000036B, + 0xFFAF0EFE, 0x700C750C, 0x0F36712C, 0xC281FFAF, + 0x341F140C, 0x78E07EE0, 0xB7C81CF4, 0x70C3C181, + 0x00400100, 0x1C08714C, 0x0DB23001, 0x1C0404A0, + 0x41C33001, 0x0000036A, 0xFFAF0EC6, 0x700C750C, + 0x0EFE712C, 0xC281FFAF, 0x341F140C, 0x78E07EE0, + 0x4030C2EA, 0x70AD4110, 0x00FA76B5, 0x097B000D, + 0x740C203E, 0x00E541C3, 0x0E960001, 0x42A1FFAF, + 0xDF0770CD, 0x800040C3, 0x88600485, 0x800040C3, + 0x10001220, 0x244A008B, 0x708D7200, 0x20A8DA07, + 0x40610540, 0x209F6D35, 0x27060803, 0x70021388, + 0x2E416119, 0x667E10C0, 0x28016108, 0xB8C00200, + 0x77447858, 0x7A8F7C05, 0x00E641C3, 0x0E420001, + 0x740CFFAF, 0x9004268C, 0xFFC507AC, 0x740CD9E7, + 0xFFAF0E2E, 0x097BB910, 0x740C207E, 0x00E841C3, + 0x0E1E0001, 0x42A1FFAF, 0xDF0770CD, 0x800040C3, + 0x88600485, 0x800040C3, 0x10001220, 0x244A008B, + 0xDA077200, 0x20A8708D, 0x40610540, 0x209F6D35, + 0x27060803, 0x70021388, 0x2E416119, 0x667E10C0, + 0x28016108, 0xB8C00200, 0x77447858, 0x7A8F7C05, + 0x00E941C3, 0x0DCA0001, 0x740CFFAF, 0x9004268C, + 0xFFC507AC, 0x740CD975, 0xFFAF0DB6, 0x71A5B911, + 0xC6CAF184, 0xC1A2C3F6, 0x46504170, 0xC1814730, + 0x30C22440, 0x01600A82, 0x30832440, 0x000040C3, + 0x211A28F0, 0x14022011, 0x232F3094, 0x46CB2000, + 0x1B3C8000, 0x308D1403, 0x23640C9F, 0x0F0679AF, + 0x40E20560, 0x704E4510, 0x24AE0D85, 0x261F474A, + 0x251A24C1, 0x00001F80, 0x279A0A3C, 0x71221184, + 0x671F6038, 0x06E00A76, 0x13D02600, 0x20851002, + 0x13842734, 0x21061004, 0x2D41E808, 0x740C0085, + 0x00A741C3, 0xF0060005, 0x41C3740C, 0x000500A8, + 0x0D1E42A1, 0x4342FFAF, 0x18002659, 0x1600671F, + 0x80007080, 0x0819000B, 0x40E1007F, 0x00200BCA, + 0x40E1712C, 0x00200BC2, 0xF00A702C, 0x090240E1, + 0x712C0020, 0x08FA40E1, 0x702C0020, 0x0A7D7146, + 0x71A5A294, 0xC7D6F1B2, 0xC1BFC3EA, 0x47084548, + 0x702CC08B, 0x0CEADA50, 0x4668FD2F, 0x10B10F29, + 0x41C3750C, 0x00010365, 0xFFAF0CB6, 0xC08B42C1, + 0x0D9E702C, 0x704C04A0, 0xD909700C, 0xFFAF0CE2, + 0xC7CAC28B, 0xC046700C, 0xC044C045, 0x30041C28, + 0x750CC049, 0x41C3EF12, 0x00010368, 0xFFAF0C82, + 0x255442C1, 0x25001F42, 0x01001F8C, 0x25400020, + 0x4D5A1A03, 0xF00F712C, 0x036641C3, 0x0C620001, + 0x42C1FFAF, 0x148C2540, 0x14022540, 0xD9094D48, + 0xC040DBC8, 0x000940C3, 0x70AD0001, 0x37102440, + 0x30112440, 0xC047C241, 0x4083C442, 0xC343B030, + 0xC08BB031, 0x0C4A702C, 0xDA50FD2F, 0x24011104, + 0x1002C808, 0x7825250E, 0x0AF2C18B, 0x42C104A0, + 0x41C140A1, 0xFFAF0C4A, 0x71A5C28B, 0x91140DD7, + 0x90110F63, 0x00000CF2, 0x78E0C7CA, 0x1CFCC2FA, + 0x2482B6C8, 0x20143F05, 0x22550042, 0x922A0800, + 0x30401CE8, 0x1CEC9228, 0x92263040, 0x30401CF0, + 0x1CF49224, 0x92223040, 0x30401CF8, 0x1CFC9220, + 0x922C3040, 0x30581C40, 0x1C41922E, 0x92303058, + 0x30581C42, 0x1C439232, 0x92343058, 0x30581C44, + 0x1C459236, 0x92383058, 0x30581C46, 0x1C47923A, + 0x923C3058, 0x30581C48, 0x1C49923E, 0x12403058, + 0x1C4A0101, 0x12443058, 0x1C4B0101, 0x12483058, + 0x1C4C0101, 0x124C3058, 0x1C4D0101, 0x12503058, + 0x1C4E0101, 0x12543058, 0x1C4F0101, 0x12583058, + 0x1C500101, 0x125C3058, 0x1C510101, 0x12603058, + 0x1C520101, 0x12643058, 0x1C530101, 0x12683058, + 0x1C540101, 0x126C3058, 0x1C550101, 0x12703058, + 0x1C560101, 0x12743058, 0x1C570101, 0x12783058, + 0x1C580101, 0x127C3058, 0x1C590101, 0x90203058, + 0x30581C5A, 0x1C5B9022, 0x90243058, 0x30581C5C, + 0x1C5D9026, 0x90283058, 0x30581C5E, 0x01061014, + 0x01091018, 0x0108101C, 0x010B1020, 0x90F490D2, + 0x909890B6, 0x905C907A, 0x1040903E, 0x10440119, + 0x10480118, 0x104C0117, 0x10500116, 0x10540115, + 0x10580114, 0x105C0113, 0x10600112, 0x10640111, + 0x10680110, 0x106C011F, 0x1070011E, 0x10740105, + 0x10780104, 0x107C0107, 0x2455011B, 0x18643800, + 0x186006C0, 0x185C01C0, 0x18580100, 0x18540140, + 0x18500780, 0x184C07C0, 0x18480400, 0x18440440, + 0x18400480, 0x183C04C0, 0x18380500, 0x18340540, + 0x18300580, 0x182C05C0, 0x18280600, 0xA0290640, + 0x00A541C3, 0xA0480040, 0xA086A067, 0xA0E4A0A5, + 0x1808A0C3, 0x180402C0, 0x18000200, 0x145E0240, + 0x1C7C3600, 0x14FC3180, 0xC05E3002, 0x3600145D, + 0x300314F8, 0x300414F4, 0x145CC05D, 0x14EC3600, + 0x14F03006, 0xC05C3005, 0x3600145B, 0x300714E8, + 0x145AC05B, 0xC05A3600, 0x36001459, 0x1458C059, + 0xC0583600, 0x36001457, 0x1456C057, 0xC0563600, + 0x36001455, 0x1454C055, 0xC0543600, 0x36001453, + 0x1452C053, 0xC0523600, 0x36001451, 0x1450C051, + 0xC0503600, 0x3600144F, 0x144EC04F, 0xC04E3600, + 0x3600144D, 0x144CC04D, 0xC04C3600, 0x3600144B, + 0x144AC04B, 0xC04A3600, 0x36001449, 0x1448C049, + 0xC0483600, 0x36001447, 0x1446C047, 0xC0463600, + 0x36001445, 0x1444C045, 0xC0443600, 0x36001443, + 0x1442C043, 0xC0423600, 0x36001441, 0x1440C041, + 0xC0403600, 0xFFAF094A, 0x2480740C, 0x14043F05, + 0xC6DA341B, 0x1CFCC2FA, 0xC1BCB6C8, 0x20557834, + 0x90580801, 0x01051158, 0x01071160, 0x9054C259, + 0x01061168, 0x01041018, 0x9050C25A, 0x01161010, + 0x01171008, 0x1038C25B, 0x10400108, 0x10480119, + 0x10500118, 0x10580115, 0x10600114, 0x10680113, + 0x10700112, 0x10780111, 0x1100011B, 0x9164010B, + 0x91EC9148, 0x91B491D0, 0x911C9198, 0x01101140, + 0x011F1148, 0x011E1150, 0x01091170, 0x01011178, + 0x31801C58, 0x31C01C54, 0x31401C50, 0x3005146C, + 0x30061468, 0x30071464, 0x41C3C158, 0x001F00A6, + 0x740CC050, 0x42E2C24B, 0x43C2C34A, 0x32401C5C, + 0x37801C4C, 0x37C01C48, 0x34001C44, 0xC54EC44F, + 0xC74CC64D, 0x32C01C24, 0x36C01C20, 0x34401C1C, + 0x34801C18, 0x34C01C14, 0x35001C10, 0x35401C0C, + 0x36001C08, 0x36401C04, 0xFFAF0856, 0x32001C00, + 0x1404C0BC, 0xC6DA341B, 0xC1A2C2F2, 0x70901600, + 0x00048000, 0x20D02053, 0x710C702E, 0x70AE724E, + 0x1600E807, 0x80007080, 0xE8890025, 0x1600F040, + 0x80007080, 0x08810040, 0x251F0010, 0x00002F8D, + 0x706E7000, 0x23002B40, 0x60BE70AC, 0xC808728E, + 0x03812005, 0x0300255F, 0x0F802030, 0x05B88000, + 0xB8027825, 0xB89FB89C, 0x20539000, 0x205300C6, + 0x274C0107, 0x26CE8400, 0xB8250026, 0x00C12053, + 0x02340909, 0x7813B8C2, 0x41C3C141, 0x0008006A, + 0x750CC040, 0x43A24202, 0xFF6F0FB6, 0x04C0240A, + 0x25FF248D, 0x716671AC, 0xA1940B9D, 0x228D700C, + 0x71AE2EBE, 0x800040C3, 0x880012D9, 0x046E087D, + 0x724E708E, 0x2414710C, 0x2800244E, 0xBE0C050F, + 0x45CB706E, 0x05D08000, 0x7F0B8D04, 0xC808F227, + 0x03812005, 0x78258500, 0xB89CB802, 0x9000B89F, + 0x00C62053, 0x01072053, 0x8400274C, 0x002626CE, + 0x2053B825, 0x090B00C1, 0xB8C20234, 0xC1417813, + 0x006B41C3, 0xC0400008, 0x4202750C, 0x240A4322, + 0x0F2E0500, 0x250AFF6F, 0x716604C0, 0xA1B40BAD, + 0x228DE50C, 0x718E22BF, 0x097D7126, 0xC0A2A114, + 0x78E0C6D2, 0xC1B7C3EC, 0x41C3D840, 0x0000036D, + 0x88A0B89F, 0x809110E5, 0xFF6F0EF6, 0x2105750C, + 0x700E2351, 0xE58770AD, 0x00260162, 0x20C02178, + 0x10B50D0D, 0x1208704E, 0xF009360E, 0x0D0F704E, + 0x70CD10B0, 0x360E1208, 0xC083744E, 0x0EE2702C, + 0xDA50FCEF, 0x800041C3, 0x89011222, 0x08E38980, + 0x742C0324, 0x29007882, 0x732C048F, 0x049F2900, + 0x2900722C, 0x712C049E, 0x04852900, 0x40C36821, + 0x12D98000, 0x00841000, 0x7040240A, 0x903843C3, + 0x20A80000, 0x0CA905C1, 0x2C40032E, 0x26F01347, + 0x8000734B, 0x270510F8, 0xC2830387, 0x11C02305, + 0x03012215, 0x2300B802, 0x78651146, 0x17892300, + 0x23009000, 0xB10017C8, 0x01C02605, 0x7865B802, + 0xB1089000, 0x11C02105, 0x7865B802, 0xB1109000, + 0x11C02005, 0x7865B802, 0xB1189000, 0x7894710C, + 0x00012214, 0x2005B80C, 0x23050382, 0x23001080, + 0xB80213CB, 0x90007865, 0x2605B100, 0xB8020080, + 0x90007865, 0x2105B108, 0xB8021080, 0x90007865, + 0x2005B110, 0xB8021080, 0x02C22205, 0x90007865, + 0x6A12B118, 0x90007865, 0x00041940, 0x750C7185, + 0x036E41C3, 0x42A10001, 0xFF6F0DC6, 0x6E3470CD, + 0x6038C083, 0x01071008, 0x01061006, 0x01041002, + 0x01051004, 0x90459060, 0x90079026, 0x42C1C240, + 0x41C3C141, 0x0009036F, 0x0D96C042, 0x750CFF6F, + 0x0ECF71C5, 0x71A59154, 0x68C1F14F, 0x41C3750C, + 0x00010370, 0xFF6F0D7A, 0x70AD4202, 0x209F4002, + 0x20140401, 0x40C30341, 0xBF648000, 0x6113603A, + 0x123C750C, 0x41C30106, 0x00050371, 0x01051228, + 0x01041214, 0xFF6F0D4A, 0x71A542A1, 0x92540DD1, + 0x20402040, 0x83A408B9, 0xC7CC710E, 0x094AC2E6, + 0x702CFEEF, 0x800046CB, 0x8EE01222, 0x09418E21, + 0x204003E4, 0xC8080A8D, 0x78A57AEF, 0x2A406832, + 0x78250380, 0x03F141C3, 0xB8920004, 0xB89FB89C, + 0x750C9060, 0x23534460, 0x0CF60145, 0x24ADFF6F, + 0x71E50982, 0x79EF8E01, 0x804508CF, 0x78E0C6C6, + 0xC1B4C3E2, 0x360D1208, 0x702CC080, 0xFCEF0CF2, + 0xD9DBDA50, 0x0CCA750C, 0xB912FF6F, 0x12032585, + 0x40A1C180, 0x04600B96, 0x700CDA09, 0x0CF2D909, + 0xC280FF6F, 0x78E0C7C2, 0x78E07EE0, 0xA023702C, + 0xA021A022, 0xA0207FE0, 0x4200C2E8, 0x780F7704, + 0x004C41C3, 0x207C0001, 0x098E00C0, 0x4050FD2F, + 0x901C41C3, 0x42C301C8, 0x12228000, 0x20B00821, + 0xDC25706C, 0x0831BC9F, 0x8C002071, 0xB162B100, + 0x9201B178, 0xD83FB200, 0xF00CB806, 0x1600B160, + 0x80007080, 0xB1020040, 0x9202B178, 0xD83FB200, + 0xF011B110, 0x8C1BB100, 0xB178B102, 0x20049110, + 0x00000F80, 0xB110FFBE, 0xAA008A02, 0xAA018A05, + 0x0F16B170, 0x400204E0, 0x78E0C6C8, 0x40C37014, + 0x048A8000, 0x1600F207, 0x90387101, 0xB9800030, + 0x9020F003, 0x1E00B9A0, 0x903B7044, 0x7FE0C030, + 0x78E0B020, 0x4528C2E4, 0xFD6F0DC6, 0xEE154608, + 0x762CC808, 0x746CDA22, 0x0B80244A, 0x70CC45A1, + 0x2005B802, 0x90070F80, 0x1800C004, 0x0F1E0045, + 0x700CFDAF, 0x700CF013, 0xDA22762C, 0x244A706C, + 0x45A10B80, 0xFDAF0F06, 0xC80870CC, 0x2005B802, + 0x90070F80, 0x1800C004, 0x700C0005, 0xFDAF0E9E, + 0xC6C4712C, 0x4628C2E4, 0x21534508, 0x710C0142, + 0xFCEF0F3E, 0xBE23702C, 0x16022644, 0x8540655D, + 0x85017A06, 0xA5407826, 0xC6C4A501, 0x70801600, + 0x00018000, 0x7CE0B8E0, 0x900F41C3, 0x704CC068, + 0x04C02150, 0xB040B140, 0x900840C3, 0xB0400068, + 0x804519D8, 0x804518A8, 0x18007FE0, 0x78E000C5, + 0x03C32841, 0x03C12840, 0x28417B25, 0x21440341, + 0x28410081, 0x7B2500C2, 0x02C12841, 0x01012144, + 0x00012284, 0x28417B25, 0x21440241, 0x7B250201, + 0x01C12841, 0x04012144, 0x28417B25, 0x21440141, + 0x79650801, 0x79456875, 0x22847A1D, 0x23840002, + 0x79450010, 0x22847A1B, 0x79450004, 0x22846853, + 0x79450008, 0x7B25704C, 0xBA8B6837, 0x23057944, + 0x2840004C, 0x795B0243, 0x28407964, 0x7C2502C3, + 0x79646A32, 0x10432405, 0x03412840, 0x78246A13, + 0x7FE07B05, 0x78E07870, 0xC1A4C3FA, 0x00582053, + 0x800045CB, 0x207811DA, 0x4138308F, 0x15464510, + 0x40E11081, 0x219F4030, 0x42D30582, 0x4E748001, + 0x02C1209F, 0x140E2714, 0x46D3706E, 0x02249004, + 0x2FC7248A, 0x41C36038, 0x0504901C, 0x100C7042, + 0xC8080097, 0x2005B802, 0x1A000042, 0x19A40045, + 0x20058045, 0x90070F81, 0x2005C090, 0x90040F80, + 0x90000090, 0xB100B888, 0x0B3F66A8, 0x28402025, + 0x78F62100, 0xE0247062, 0x294060A9, 0x21050391, + 0x18002580, 0x0E060504, 0x740C02E0, 0x22012640, + 0x21057166, 0x18002040, 0x69040504, 0x04402005, + 0x00051800, 0x2D40F1E2, 0xD9102080, 0x05512005, + 0x303009AF, 0x0A9A4042, 0x404204C0, 0x0FA6D910, + 0xDA410260, 0xD9104042, 0xFDEF0DAE, 0x0FBEDAF3, + 0x208AFDAF, 0x0D820C12, 0x700C0160, 0xFD4F0B7A, + 0x40C36829, 0x04888000, 0x0520099A, 0x40C3B020, + 0x13880000, 0x02E00DBE, 0x09C2D90C, 0x40420500, + 0x0F62D90D, 0xDA400260, 0x05200916, 0xC080C080, + 0xFFEF0DF6, 0xC080D910, 0xFFEF0DEE, 0x41E1D90D, + 0x219F4002, 0x704C02C1, 0x0582209F, 0x708CC380, + 0x611970AC, 0x0447202F, 0x06A00E2E, 0x40427142, + 0x0D36D910, 0xDAF3FDEF, 0xD9104042, 0x02600F16, + 0x4042DA61, 0x0D22D910, 0xDA7FFDEF, 0x0D1AF00E, + 0xDAF3FDEF, 0xD9104042, 0x02600EFA, 0x4042DA61, + 0x0EF2D910, 0xDA800260, 0x70451E00, 0x04C4901C, + 0x800040C3, 0x88001220, 0xDA40E803, 0xDA25F002, + 0x209F41E1, 0x219F0582, 0xBA9F02C1, 0x00931200, + 0x70426038, 0xFD6F0ACA, 0x00941010, 0x000009AE, + 0x050008C6, 0x0447222F, 0x0806D810, 0x4182FDEF, + 0x742C700C, 0xFDAF0F1A, 0x0B27714C, 0x710C20F1, + 0x30812079, 0x24847838, 0xB8022282, 0x21412485, + 0x0040200F, 0x7A0F4182, 0xFDAF0FD6, 0x700CD810, + 0x0EEED920, 0x714CFDAF, 0x0BA2700C, 0x712CFDAF, + 0xFD4F0A6E, 0x01600C52, 0x084A700C, 0x700C0500, + 0xFDAF0B8A, 0xD914702C, 0x000040C3, 0x0C961388, + 0x441002E0, 0xE81866A8, 0x2840706E, 0x78F62100, + 0xE0247062, 0xD88060A9, 0x052009EA, 0x29404130, + 0x71662391, 0x2F812105, 0x02309004, 0x66A8B100, + 0xA0040BDB, 0x0C5E4082, 0xD90C02E0, 0x00400882, + 0x0500085A, 0x000340C3, 0x0C4AD090, 0x702C02E0, + 0x05200812, 0x21D5274F, 0xE81866A8, 0x2840706E, + 0x78F62100, 0xE0247062, 0x40A260A9, 0x05200996, + 0x29404130, 0x71662391, 0x2F812105, 0x02309004, + 0x66A8B100, 0xA0040BDB, 0x40C3D90C, 0x13880000, + 0x02E00C02, 0x66A84410, 0x254FE819, 0x706E2215, + 0x21002840, 0x706278F6, 0x60A9E024, 0x095640A2, + 0x41300520, 0x23912940, 0x21057166, 0x90042F81, + 0xB1000230, 0x0BDD66A8, 0x4082A004, 0x02E00BC6, + 0x66A8D90C, 0x702EE825, 0x21002840, 0x702278F6, + 0x60A9E024, 0x0006208A, 0x0520091A, 0x2B404330, + 0x24052394, 0x90042F81, 0xB1000224, 0x02E00B6E, + 0x208A740C, 0x08FE0006, 0x41620520, 0x2F812405, + 0x022C9004, 0x7126B100, 0x09C166A8, 0x40C3A004, + 0xD0900003, 0x02E00B6E, 0x4042702C, 0x0460098A, + 0x0F6AD910, 0xC7DA04C0, 0x40D3C2F8, 0x01E8901C, + 0x000040C3, 0x10000FFF, 0x10102112, 0x18102111, + 0x18002005, 0xC8082004, 0x2005B802, 0x900C0F80, + 0x90400020, 0x800040C3, 0x8800121E, 0x0201204F, + 0x1E006058, 0x901C7044, 0x20420508, 0x160000D5, + 0x80007080, 0x70140114, 0xD93DF281, 0xB910750C, + 0xFF2F0EDE, 0x47CB70CD, 0x01188000, 0x45CB8F40, + 0x0001003E, 0x0ECA750C, 0x41A1FF2F, 0x10562740, + 0x1401254F, 0x20821600, 0xFF2F0EB6, 0x2640750C, + 0x71AD2057, 0x20821700, 0x750CBD96, 0xFF2F0EA2, + 0x274241A1, 0x254F10D4, 0x14001401, 0x0E922082, + 0x750CFF2F, 0x20532440, 0x1441254F, 0x20821300, + 0x0E7E750C, 0x4038FF2F, 0x204F6FA9, 0x8D403401, + 0xFF2F0E6E, 0x710C750C, 0xE808722D, 0x70801600, + 0x00258000, 0xF037E887, 0x70801600, 0x00408000, + 0xC808E835, 0x13812E40, 0x7180244A, 0x008B2840, + 0x0A4020A8, 0x03DE208A, 0x201143E2, 0x40A18380, + 0x4062F40F, 0x11300E1B, 0x0E1343C2, 0x40621330, + 0x12F00E0F, 0x0E2743C2, 0x40821151, 0x210543E1, + 0x884002C8, 0x20058B00, 0x90001F8C, 0xB40001C0, + 0x1F802005, 0x01B49000, 0x71C5B040, 0x000071C3, + 0xDE074000, 0x10FF218D, 0x45CB700C, 0x11388000, + 0x108015E6, 0x27C12D42, 0x7824B802, 0x1E0070A2, + 0x901C7004, 0x40C30510, 0x2AF80000, 0x02E009E6, + 0x1800702C, 0x18102484, 0x15E62444, 0x781D1080, + 0x7704B8A0, 0xC6D8AD01, 0x0AC2C2E8, 0x40100640, + 0x700C71ED, 0x900F45CB, 0xD940C298, 0x73C41E00, + 0xC028900F, 0x02E009AE, 0x1E00B5E0, 0x902F73C4, + 0x0A62CC40, 0x700C03A0, 0x02E0090E, 0x1D00D810, + 0x16001005, 0x9018710E, 0x08150018, 0x26842030, + 0x1E001C07, 0x901B73C4, 0xF02EC000, 0x901B45CB, + 0x264FC018, 0x702C1280, 0x096AB500, 0x208A02E0, + 0x702C0A0F, 0x000F40C3, 0x095A4240, 0x1DEC02E0, + 0x160093C4, 0x90187101, 0x1DE8004C, 0xB9C493C4, + 0x90051DEC, 0x70801600, 0x00048000, 0x08002044, + 0x78C5B804, 0xC808B500, 0x2005B802, 0x90180F80, + 0xB0200024, 0x800041C3, 0x89001220, 0x0582209F, + 0x000111BC, 0x88216038, 0x00DF090D, 0x21538834, + 0xF20480FE, 0x04C00E2A, 0x70451E00, 0xC0B49027, + 0x78E0C6C8, 0xC1A3C3FA, 0x2140260A, 0x3100210A, + 0x40584770, 0x71344530, 0x002D0136, 0xC8084210, + 0x800047CB, 0xB8021222, 0x0F802005, 0x01909038, + 0x08159000, 0x1600025E, 0x80007080, 0x701400F3, + 0x0001024E, 0x208A70D4, 0x218A003E, 0x0C9E2001, + 0x21CAFD2F, 0x8FA02002, 0x00132079, 0x22132340, + 0x75308F21, 0x000D01A6, 0x800040C3, 0x880012D9, + 0x036E08CB, 0x0E137AAF, 0x40622030, 0x0C8E41A2, + 0x43420060, 0x0A92F004, 0x40400020, 0x234E2714, + 0x20700A25, 0x0A4FB600, 0x212F2031, 0xF2138348, + 0x0050099F, 0x009009A3, 0x00D1093B, 0x800041C3, + 0xF01C014A, 0x8348222F, 0x41C3F209, 0x014C8000, + 0x41C3F008, 0x01478000, 0x41C3F010, 0x014B8000, + 0x0083227C, 0x21CA7074, 0x80000F81, 0x0A0D014D, + 0x41C300D4, 0x014E8000, 0x00901100, 0x70811600, + 0x000D8000, 0x017E0937, 0x0DFAC182, 0x22140040, + 0x20002340, 0x80000F94, 0x0D6A0470, 0x140904A0, + 0x08133080, 0xC1220874, 0x001E090F, 0x20431C00, + 0x09FDF005, 0x1C00801E, 0x96202003, 0x24402000, + 0x2108780F, 0x49100001, 0x71A5B600, 0x41C3F192, + 0x01488000, 0x41C3F1D2, 0x01498000, 0x2550F1CE, + 0x08BF2000, 0x708D00B1, 0x800045CB, 0x0EC31222, + 0x73B62030, 0x20C82578, 0x126124CA, 0x12482040, + 0xFD2F0B7A, 0x12892C40, 0x108615B7, 0x15014700, + 0x8D60108B, 0x018C7371, 0x0E7F000D, 0x2B4000EE, + 0xC8080301, 0x47CB7905, 0xFFFF0000, 0x04812105, + 0x69B270CD, 0x42814021, 0x02050A43, 0x00310F11, + 0x06812300, 0x0081111C, 0x00400A2B, 0x20B10D13, + 0x03412005, 0x0F812105, 0x01E89004, 0x2505F005, + 0x90041F81, 0x912000A8, 0x210871F1, 0x27CA038E, + 0x20801045, 0x71440010, 0x66FEF1E0, 0x20C22714, + 0x268C79DD, 0x21809002, 0x21CA003F, 0xB2200025, + 0x30C22014, 0x7164B220, 0x8FA0F1BE, 0x700CF080, + 0x03A341C3, 0x0FC20001, 0x42A2FCAF, 0x4042F07A, + 0x714CC180, 0xC441716C, 0x00A009EA, 0x4042C440, + 0x714CC180, 0x00A009DE, 0x8D01706C, 0x08D58D40, + 0x784200A4, 0x2A922240, 0xC8086821, 0x7040240A, + 0x078020A8, 0x03012A40, 0x79057142, 0xB992B902, + 0xB99FB99C, 0xC1809180, 0x008321F4, 0x6479BCC5, + 0x08032142, 0x7930E120, 0x2714E1C0, 0x23CA2081, + 0xB1600025, 0x30812014, 0xB1607144, 0x8F21F042, + 0x097D8FA0, 0x49B00364, 0x40C36841, 0x12D98000, + 0x240A8880, 0x40A17080, 0x20A8DAC1, 0x0C0D0240, + 0x2714102E, 0xB3402003, 0xF02A7104, 0x800040C3, + 0x880012D9, 0x034E0847, 0x234027F4, 0x00600C26, + 0xCA05C182, 0xC082E805, 0x02200D4E, 0x16004123, + 0x80007080, 0x0819000D, 0x2214017E, 0x20322340, + 0x80000F81, 0x0D320470, 0xC0820220, 0x0A86C082, + 0x2014FF2F, 0x8F21334E, 0x71A5B600, 0x834509B1, + 0x78E0C7DA, 0x2840C2E2, 0x4200038C, 0x1F812405, + 0x0AB09004, 0x70EC9100, 0x0003204F, 0xB8A0B160, + 0x2A40B100, 0xC8080301, 0x69127905, 0x0F802005, + 0x0AB49004, 0x0B1D9060, 0x46600175, 0x208040C0, + 0x7825080A, 0xB892B802, 0xB89FB89C, 0x01071000, + 0x1F802405, 0x03549004, 0x16009000, 0x80007101, + 0x090D0006, 0x00000F84, 0x781D0A6B, 0x211F7910, + 0x20020180, 0xB80601C0, 0x00402805, 0x0804218A, + 0x0008252F, 0x7D104910, 0x01442053, 0x11832D41, + 0x039D41C3, 0x092A0006, 0x740CFF2F, 0xC6C240A1, + 0x01822053, 0x01C120AD, 0x7FE0A941, 0x78E0A900, + 0xC1A4C3F0, 0x40C34410, 0x12208000, 0x202F8820, + 0x41300502, 0xD940E903, 0xD925F002, 0x2044B99F, + 0x89000053, 0x00F1080F, 0x20002352, 0x04E0092E, + 0x09AA712C, 0x40C3FFCF, 0xC3500000, 0x02A00CF6, + 0x46CB732C, 0x11DA8000, 0x04E008BA, 0x244F2314, + 0x21122940, 0x67C870AD, 0x10250D2B, 0x24C02216, + 0xE02460B8, 0x208A60C9, 0x0A3A0004, 0x403004E0, + 0x23902840, 0x200571A5, 0x90042F81, 0xB1000230, + 0x45CBF1EB, 0x13880000, 0x0CAA40A1, 0xD90C02A0, + 0x04C008AA, 0x702CC808, 0xB802700E, 0x0F802005, + 0x0504901C, 0x00051800, 0x02A00C8A, 0x45CB40A1, + 0x4E748001, 0x091A40A1, 0xD91004A0, 0xD91040A1, + 0xFDAF0C36, 0x40A1DACF, 0x0C2ED910, 0xDAFFFDAF, + 0x04A00FCE, 0xC080C080, 0xFFAF0CAE, 0x4062D910, + 0x2582219F, 0x02C1209F, 0xC380704C, 0x70AC718C, + 0x60B97022, 0x06600CF2, 0x40C34082, 0x36B00000, + 0x02A00C32, 0x67C8D90A, 0x2216E812, 0x700224C0, + 0xE0247106, 0xB80E60C8, 0x0F812005, 0x02309004, + 0xB88C700C, 0x67C8B100, 0xA00408E3, 0x0A2A40A1, + 0xD9100420, 0x6832C808, 0x0F802105, 0xC0909007, + 0x0F812105, 0x00909004, 0x21049120, 0x00000F81, + 0xB020FEFF, 0x02A00B52, 0xC7D0D814, 0x46CBC2E8, + 0x01E8901C, 0x96A89620, 0x25464030, 0xB6081C00, + 0x0F802105, 0x0C300000, 0x1600B600, 0x80007080, + 0xE8360114, 0x750CD945, 0xFEEF0F86, 0xC808B910, + 0x726D702C, 0x710C68F2, 0x1600E807, 0x80007080, + 0xE8880025, 0x1600F020, 0x80007080, 0xE8200040, + 0x7180244A, 0x060020A8, 0x03802940, 0x800042C3, + 0x78E519AC, 0x004C22F4, 0x0F832005, 0x01C09000, + 0xE21CB380, 0x0F832005, 0x01B49000, 0x004022F4, + 0xB3007124, 0x238DD907, 0x700C16BF, 0x901C40C3, + 0x18000508, 0x18080005, 0x40C30005, 0x2AF80000, + 0x02A00B32, 0x1E00702C, 0xB6A81404, 0x78E0C6C8, + 0x1CFCC2FA, 0xC1A7B6C8, 0xD9894528, 0x4608B910, + 0xC344D8C8, 0xFEEF0EEA, 0xD8C8C243, 0xD98BED04, + 0xF004B910, 0xB911D945, 0xFECF0ED6, 0xC18640A1, + 0x35C22440, 0x00A00BB2, 0x35832440, 0xEE05D8C8, + 0xB910D98D, 0xD923F003, 0x0EB6B912, 0xC006FECF, + 0x008E45CB, 0x41A10001, 0xD8C8C041, 0xFEEF0EA2, + 0x1417C201, 0x254F3080, 0xC0401401, 0x0E92D8C8, + 0xC200FEEF, 0x30801416, 0x009046CB, 0x41C10001, + 0xD8C8C042, 0xFEEF0E7A, 0xC203C202, 0x1401264F, + 0xFEEF0E6E, 0xDD20D8C8, 0x144F264F, 0xD8C8BD9F, + 0x0E5E41E1, 0x1501FEEF, 0x8D401482, 0x1401274F, + 0xFEEF0E4E, 0x15F6D8C8, 0x264F9082, 0xD8C8148F, + 0xFEEF0E3E, 0x15F741E1, 0x274F9082, 0x0E321401, + 0xD8C8FEEF, 0xBF918D44, 0x0E26D8C8, 0x41E1FEEF, + 0x274F8D5F, 0x0E1A1401, 0xD8C8FEEF, 0xD8C8BE93, + 0x0E0E41C1, 0xDA0AFEEF, 0x1401264F, 0x0E02D8C8, + 0x744CFEEF, 0xD8C8D94D, 0xFEEF0DF6, 0xC001B911, + 0x01427014, 0x704E002C, 0x47D3C000, 0x0A3C0000, + 0x05C2201F, 0x20C12F40, 0x46D3C004, 0x1A3C8000, + 0x0059201F, 0x20902640, 0x22007223, 0x20000595, + 0xC1002090, 0x7110C002, 0x002D00F0, 0x2540230A, + 0x240AC600, 0xC0032400, 0x04A00F3A, 0x431879CF, + 0x0BC1702E, 0xD8C8346E, 0x4342C204, 0x009B41C3, + 0x44C10004, 0xFEEF0D8A, 0x0440250A, 0xD8C8D927, + 0xFEEF0D7E, 0x70ADB912, 0x34C0200A, 0x1704478A, + 0xD8C81503, 0x35021004, 0x009D41C3, 0x0D620003, + 0x44A1FEEF, 0xE5C071A5, 0xDD4FF7B3, 0xBD11D8C8, + 0xFEEF0D4E, 0x254F41A1, 0x0D461401, 0xD8C8FEEF, + 0xD8C8752C, 0xFEEF0D3A, 0x221AB915, 0x00002F81, + 0x261A28F0, 0x452A15C0, 0x1184259A, 0x800047CB, + 0x71231B3E, 0x0A466038, 0x651D0620, 0x260065EB, + 0x65FD2341, 0x07021180, 0x11041502, 0xBB22E807, + 0x41C3D8C8, 0x000300A1, 0xD8C8F005, 0x00A241C3, + 0x0CEE0003, 0xD9A3FECF, 0x0CE6D8C8, 0xB910FEEF, + 0x23807126, 0x093F2184, 0x2480A2B4, 0xC0022184, + 0x07267610, 0x71C5FFE5, 0x000040C3, 0x250028F0, + 0x20002015, 0x71462010, 0x220CC001, 0x06F6A000, + 0xD929FFCB, 0x0CAAD8C8, 0xB912FEEF, 0x1404C0A7, + 0xC6DA341B, 0xC1A2C3F0, 0x40C34310, 0x12258000, + 0x800041D3, 0x88000025, 0x11004748, 0x4628208C, + 0x30021C03, 0xC181710C, 0x30C22440, 0x00A0095A, + 0x30C32440, 0x30121404, 0x10C02478, 0x20087104, + 0x084F0490, 0x44102072, 0x0B1170AD, 0x740C2030, + 0x00AA41C3, 0xF0050003, 0x00A941C3, 0x42A10003, + 0x0C3E43A1, 0x44C1FEEF, 0x15250D11, 0x41C1700C, + 0x0E8642E1, 0x43A1FF2F, 0x14A30D11, 0x41C1710C, + 0x0E7642E1, 0x43A1FF2F, 0x0DC371A5, 0x11E59404, + 0x081FA080, 0x4062003E, 0x42C1702C, 0xFFEF0D06, + 0x406243E1, 0x42C1712C, 0xFFEF0CFA, 0xC7D043E1, + 0x2482C3F2, 0x42203608, 0x740C4210, 0x021741C3, + 0x0BDE0001, 0x4450FEEF, 0xC1804042, 0xFE2F0EEA, + 0x35C22440, 0x003108B5, 0xC0864708, 0x00200902, + 0xC0204142, 0xC2864182, 0x0D1A4342, 0x4110FE2F, + 0x70CD4510, 0x70ED454A, 0x200A706E, 0xE7C02440, + 0x9500F755, 0x0505081F, 0x0C1B9501, 0x78CF2025, + 0xC2864182, 0xFE2F0CEE, 0x0B0B4342, 0x43102005, + 0xE60840D1, 0xE708E520, 0x74EDF1EB, 0x2000740C, + 0x4508200E, 0xE0BF78CF, 0x4182F70A, 0x0CC6C286, + 0x4342FE2F, 0x20050B09, 0x40D14310, 0x234E2002, + 0xE0BF78CF, 0x4182F70A, 0x0CAAC286, 0x4342FE2F, + 0x20050B09, 0x40D14310, 0x91350DC7, 0x0B1D78BD, + 0x230C2030, 0x1A82A540, 0x21CA251C, 0x22802402, + 0x70ED2084, 0x24421A00, 0xC7D240E1, 0x4010C2E8, + 0xB8226901, 0x20494528, 0x46CB0FCF, 0x00020218, + 0x41C1740C, 0x0AFA42A1, 0x43E1FEEF, 0x23C02015, + 0x90419060, 0x00E50A13, 0x1401264F, 0x0AE2740C, + 0x74ADFEEF, 0x4002F00A, 0x2080627A, 0xA8A00084, + 0x70AD785D, 0x201C1882, 0xC6C840A1, 0x2155C0E6, + 0x248A0F8E, 0x708D7001, 0x238A704C, 0x20A80FC7, + 0x20160280, 0x7144008F, 0xB762B783, 0xB760B781, + 0x2115716D, 0x234002CC, 0x94401048, 0x0D3794A1, + 0x211510A5, 0x93A00203, 0x0A119341, 0x20160364, + 0xB2A002C2, 0xB2619361, 0x910214FC, 0x910314FE, + 0x00A40B65, 0x02C32016, 0x14FEB340, 0xB3419102, + 0x2016F02A, 0x774402CD, 0x9340B541, 0x232F7144, + 0x14FC1088, 0x71449102, 0x22097A50, 0xB54002C2, + 0x1086232F, 0x23099C40, 0x77441082, 0x9441B540, + 0xB5427144, 0x77449341, 0x14FE7B50, 0x77449102, + 0x22087A50, 0xB54300C2, 0x9C417B4E, 0x00822308, + 0xB5437144, 0x9FF4086F, 0x1200230A, 0x91619140, + 0x00A50B17, 0x91427744, 0x0B3B9163, 0xB0400084, + 0xB0419143, 0xB041F017, 0x71449142, 0x7B4EB040, + 0x23099940, 0x77440082, 0x9141B040, 0xB0427144, + 0x77449143, 0x7B4EB043, 0x23089941, 0x71440082, + 0x9642B043, 0x010311FE, 0x00A50B1B, 0x96407744, + 0x010311FA, 0x00840B41, 0x11FAB740, 0xB7210101, + 0xB741F01A, 0x71449640, 0x7B4EB740, 0x23099E42, + 0x77440082, 0x11FEB740, 0x71440102, 0x11FAB742, + 0x77440102, 0x7A4EB743, 0x014111FE, 0x00412208, + 0xB7237124, 0x7F80244A, 0x034020A8, 0x09159024, + 0x00000F81, 0x218AFFFF, 0x180A0FC7, 0xB0240005, + 0xC4C6E008, 0x1CFCC2FA, 0x1600B6C8, 0x8000708F, + 0x46CB1222, 0x1A3E8000, 0x2100270A, 0x41584078, + 0x46104338, 0x10912642, 0x70801600, 0x12238000, + 0x01507710, 0x40C3000D, 0x12D98000, 0x20118800, + 0xF29E83C0, 0x091370AD, 0x27003031, 0x101C1680, + 0x75100080, 0x0D0BF290, 0x70171271, 0x248AF28C, + 0x70EC7001, 0x706D700D, 0x70CC702D, 0x20A8706C, + 0x40C30D00, 0x28F00000, 0x261F791B, 0x231F2002, + 0xB8223041, 0x615978EC, 0x40A1611A, 0x0184209A, + 0x20156058, 0x213401C0, 0x60D0200C, 0x03250829, + 0xEB174050, 0x02C7222F, 0x0207212F, 0x222F4953, + 0x212F0187, 0x79420247, 0x23CA7170, 0x20CA1189, + 0xF0071249, 0x26CA7074, 0x210A01C1, 0x203D11C0, + 0x71E40303, 0x02C7212F, 0x0207202F, 0x212F4832, + 0x202F0187, 0x78220247, 0x23CA7050, 0x20CA118A, + 0x222F124A, 0x232F22C7, 0x23002207, 0x0F472480, + 0x242F2030, 0x0D762002, 0xE80D05C0, 0x209A40A1, + 0x70020184, 0x05002015, 0x20012134, 0x782260D0, + 0x2302F003, 0x120B2480, 0x252F3086, 0x253F0006, + 0x41C30180, 0x00050237, 0x43E142C2, 0xFC6F0D1A, + 0x40A144A1, 0x0184209A, 0x20102000, 0x18002656, + 0x0D2A7002, 0x180005E0, 0xE80E0502, 0x25002015, + 0x213460D1, 0x60382000, 0x2000791D, 0x80002F80, + 0xB0201B40, 0xE58A71A5, 0xFFC506CE, 0xF15671E5, + 0x341B1404, 0x78E0C6DA, 0x7034C2E6, 0x03012A40, + 0x79654608, 0x47CBC808, 0x00409004, 0x27C07825, + 0x28401222, 0xE688008B, 0x404846C1, 0x026126CA, + 0x000045CB, 0x702DFFFF, 0x706C708D, 0x01A50B37, + 0x0E137890, 0x20001275, 0x101C1680, 0x0B1F0080, + 0x21050000, 0x78E512C0, 0xFEEF0842, 0x79B09000, + 0x004D2009, 0x20087990, 0x2180004C, 0x71641010, + 0x79B0F1E6, 0x781D6038, 0x78E0C6C6, 0x44CBC0E6, + 0x12228000, 0x108814B7, 0x14008CE1, 0x0F9B1086, + 0x08931184, 0x244A11AE, 0x265A7280, 0x20A8028B, + 0x446900C1, 0x800045CB, 0x249AC144, 0x2432100E, + 0x80001F89, 0x0927C444, 0x659E10F0, 0x10B00915, + 0x7135659E, 0x702D70EC, 0x2434F417, 0xF0131347, + 0x13472434, 0x11091602, 0x2434F00F, 0x16021347, + 0xDD801109, 0x21029682, 0x7D8211C4, 0x03450C0B, + 0x218A4781, 0x21001002, 0x211411CC, 0x7E9D02CD, + 0x018C20F4, 0xB58064DC, 0x02CD2214, 0x018C20F4, + 0xB58074E0, 0x02CD2314, 0x018C20F4, 0x74217165, + 0x71C4B580, 0xC4C6F1B5, 0x706CC0F1, 0x2240DC3F, + 0x248A008B, 0x18007001, 0xA9800003, 0x01C020A8, + 0x15081304, 0x10110809, 0xF0037164, 0x2280A860, + 0x248A0F83, 0x20A87001, 0x12FC01C0, 0xEB858503, + 0x89807785, 0xA980F002, 0x7B8F8840, 0xCA0B4B51, + 0x44207110, 0xF649700C, 0x021D41C3, 0x0E520003, + 0xD8C9FEAF, 0xC0D1760C, 0x78E07EE0, 0x7002248A, + 0x20A8706C, 0x41000480, 0x0182235A, 0x000E219A, + 0x41C3623A, 0xC1448000, 0x61596234, 0x090D9121, + 0x71640305, 0xD8807FE0, 0x786F7FE0, 0xF717E1FF, + 0x7A22DA80, 0x7080240A, 0x044020A8, 0x215A4200, + 0x229A0183, 0x635B000E, 0x800042C3, 0x6354C144, + 0x9241627A, 0x03040A09, 0xD9807124, 0x78307FE0, + 0x01422053, 0xA941B826, 0xA9007FE0, 0xC1A3C3EC, + 0x700C4210, 0x458B4130, 0xB504B505, 0x018D41C3, + 0xB5030000, 0x0DBAB502, 0x740CFEAF, 0x4122710C, + 0x32822440, 0x00200F26, 0x31832440, 0x4122700C, + 0x0F1AC282, 0xC3810020, 0x3140140A, 0x2042D980, + 0x40C38443, 0x12208000, 0x23CA9582, 0x8840002C, + 0xE411E4EE, 0x24CA95E4, 0x1406104D, 0x7E703110, + 0x740C7D90, 0x018E41C3, 0x43420007, 0x45C1718C, + 0x0400260A, 0x0D5A47E1, 0xC540FEAF, 0x13840D1B, + 0x23E40817, 0x27CC7512, 0xF7599385, 0x41224042, + 0x43E1704C, 0x4042F00D, 0x704C4122, 0x44A143E1, + 0xFCAF0B4A, 0x404270AC, 0x704C4122, 0x240A43C1, + 0x0B3A0400, 0x71ACFCAF, 0x0E15C7CC, 0x0DEB13C5, + 0x40429424, 0x704C4122, 0xF00F43C1, 0x14250D13, + 0x41C3740C, 0x0000018F, 0xFE8F0CF6, 0x4042C7CC, + 0x704C4122, 0x44A143E1, 0x78E0F1E5, 0x800042C3, + 0x24AA0450, 0x21AA1144, 0x82610104, 0x200E8200, + 0xA2008040, 0x90C12403, 0xA2217FE0, 0x1CFCC2FA, + 0xC1B6B6C8, 0x800046CB, 0x8EA01222, 0x780F4310, + 0x714CC180, 0x1C04706C, 0x24403001, 0x0BE63019, + 0x1C000020, 0x23403001, 0x23402A18, 0x09D62A9B, + 0x255F03A0, 0x16001251, 0x272F1092, 0x8E011487, + 0x03E40885, 0x2F412354, 0x33CD21F4, 0x41C3740C, + 0x000103EA, 0xFEAF0C6A, 0x2F4042A1, 0xC8081315, + 0x26C12505, 0x900447CB, 0x78250000, 0xB802708E, + 0x2440270A, 0x902078E5, 0x01502153, 0xE5207502, + 0x2348262F, 0x05C7222F, 0x7854C082, 0x03EB41C3, + 0x43020004, 0xB0A04440, 0x0C26740C, 0x250AFEAF, + 0x71860580, 0x0507202F, 0x827408DD, 0x250571E6, + 0xC8082601, 0x21007825, 0xB8022511, 0x78E57146, + 0xF1BDB0A0, 0x7825C808, 0x714CC182, 0x708C706C, + 0x06200D7E, 0xC0B670AC, 0x341B1404, 0x78E0C6DA, + 0xD820C2E2, 0x900745CB, 0x1D00C40C, 0x0F6A1045, + 0x1D000220, 0xD8201005, 0x02200F5E, 0x10451D00, + 0x10051D00, 0x78E0C6C2, 0x803C2042, 0x42C3F208, + 0x12EA8000, 0x010020A8, 0x00521A14, 0x06200475, + 0x78E0712C, 0x2482C3EA, 0x45083212, 0x38802455, + 0x0BAE702C, 0x228AFC2F, 0x710C0010, 0xB80278B8, + 0x00200E42, 0x0350200F, 0x00200E46, 0x07912040, + 0x8E82208C, 0xDEFE70ED, 0x0E36F705, 0x20540000, + 0x740C088E, 0x040841C3, 0x714C0002, 0xFEAF0B52, + 0x120843A1, 0xC084360D, 0x800041C3, 0x0B4A1042, + 0xDA78FC2F, 0x0BC6C084, 0xD9780620, 0x1E00D80F, + 0x900773C4, 0x0FDEC29C, 0xD90FFDAF, 0x212F78CF, + 0x0FA60447, 0x222F0160, 0x25050407, 0x00011F90, + 0x45CB002A, 0x12228000, 0x8D208D01, 0x00640829, + 0xB90E7822, 0x28407104, 0x240A2082, 0x20A87000, + 0x22050300, 0x71C30040, 0x40000000, 0xB89FB89C, + 0x00051800, 0xD80F70CD, 0xFDAF0F8A, 0x700CD90F, + 0xFCEF0DDA, 0x8D01712C, 0x77108DE0, 0x002D006C, + 0x106D26C0, 0x712C78E2, 0x26046861, 0x00001F82, + 0x2653FFF8, 0xBA231080, 0x71C57918, 0x70C0240A, + 0x090020A8, 0x13032F40, 0x73C026F4, 0x048C8000, + 0x2F407865, 0xB802120C, 0x0F802005, 0x02DC9004, + 0x010B1000, 0x38802455, 0x70756098, 0x8C00605C, + 0x004220C5, 0x7826F402, 0x04032305, 0x6B12AC00, + 0xB89C71E5, 0xB0C0B89F, 0x03400F9A, 0x087B78D0, + 0x00008F84, 0x8DC00800, 0x8D01700E, 0x03A408DD, + 0x41C3740C, 0x00010409, 0xFEAF0A36, 0x702E42C1, + 0xAFDF218C, 0x002D00B6, 0x218B740C, 0x1C0CA803, + 0x1C083400, 0xF4123400, 0x28002156, 0x21822941, + 0x0F802004, 0xFFC00000, 0x41C3B826, 0x0002040A, + 0x09FE6869, 0x740CFEAF, 0x70CCDF08, 0xC282706C, + 0x627A708D, 0x00892653, 0x7100244A, 0x200A736D, + 0x1A001440, 0x20A80003, 0x2E400500, 0x24551200, + 0x61193881, 0x10C02841, 0x61087105, 0x02402801, + 0xB8C07125, 0x02C02800, 0x7C057765, 0x00862652, + 0x71647426, 0x177F278D, 0x140DAA80, 0x140B3087, + 0x140C3085, 0x140A3086, 0xC2223084, 0x30831409, + 0x3081140E, 0x3080140F, 0x41C3C140, 0x0008040B, + 0x097EC041, 0x740CFEAF, 0x41C3F1A4, 0x0000040C, + 0xFE8F096E, 0xF19371C5, 0x78E0C7CA, 0x082E43E3, + 0x20780000, 0x16000001, 0x80007080, 0x08110008, + 0x217800B1, 0xB8020000, 0x7B007404, 0x00002178, + 0x7204781B, 0x78E07B00, 0x800040C3, 0x88201220, + 0x219F8841, 0x229F0582, 0x10BC02C1, 0x60380000, + 0x8A03621A, 0x86002044, 0x02002078, 0x20CA7FE0, + 0x78E000A1, 0x244AC5E1, 0x706C71C0, 0x702C704C, + 0x900C44CB, 0x20A80240, 0x21050280, 0x7424030D, + 0x651D95A0, 0x7144AD40, 0x70811600, 0x00408000, + 0x244AE90E, 0x704C71C0, 0x028020A8, 0x1381244F, + 0x74447945, 0x61199120, 0x7164A967, 0x78E0C4C2, + 0x4310C2F2, 0x4570710C, 0x42304450, 0xFCAF0A92, + 0x04CD2800, 0x10512553, 0xD90B700C, 0x706C704C, + 0x250A708C, 0x0BF60440, 0x70CCFCEF, 0xD9FF700C, + 0xFCEF0EDE, 0x6D12704C, 0x200F762C, 0xDA2204C0, + 0x700C7E0F, 0x20300D1D, 0x244ADB40, 0x45C10A00, + 0xFCEF0BCA, 0xD88070CC, 0x744CD919, 0xF00CDB83, + 0x0940244A, 0x0BB645C1, 0x70CCFCEF, 0xD919D880, + 0xDB81744C, 0x250A708C, 0x0BA20440, 0x70CCFCEF, + 0x0B4A700C, 0x712CFCEF, 0x0BCE700C, 0xB88B0220, + 0x000040C3, 0x0C4E9C40, 0xD9080220, 0x20300D0B, + 0xD92640C1, 0xD923F002, 0xFE8F0F7A, 0x800047CB, + 0x8FA01222, 0x082B8F01, 0x79AF0344, 0x0C4E4062, + 0x403000A0, 0x4002E809, 0x0F9A742C, 0x42620360, + 0x23412214, 0x8F01B100, 0x71A57510, 0x0D0DF7AF, + 0x40C12030, 0xF003D927, 0x0F3AD924, 0x8FA0FE8F, + 0x0B7D8F61, 0x7EAF0364, 0x0C124062, 0x41C100A0, + 0x40C1E834, 0x0F5E742C, 0x42620360, 0x22F4B808, + 0x22142341, 0x78252342, 0x1600B200, 0x80007101, + 0x218C0006, 0xF70581C3, 0x00451A00, 0x7810F004, + 0x0095080D, 0x000040C3, 0xF009FFFF, 0x70811600, + 0x00088000, 0x2905B911, 0xB2000000, 0x0D117B10, + 0x740C2030, 0x035941C3, 0xF0050002, 0x035A41C3, + 0x0F5E0002, 0x42A1FE6F, 0xF1C471A5, 0x0B298FA0, + 0x79AF0364, 0x00A00B96, 0xE88B4062, 0x103F0D0D, + 0x23402214, 0xF0049021, 0x810110FE, 0x8F61B020, + 0xF1EF71A5, 0x0B438F40, 0x0C3F0084, 0x23782030, + 0x0D0F2000, 0x20782030, 0x48AC0000, 0x489CF002, + 0x68614B50, 0x7825C808, 0x70C0240A, 0x20A86892, + 0x2A400340, 0x22F40380, 0x78852081, 0xB8927144, + 0xB89FB89C, 0x08CAB020, 0x700CFC8F, 0x744CD90C, + 0x708C706C, 0x0440250A, 0xFCEF0A32, 0x700C70CC, + 0x764CD907, 0x708C706C, 0x0A2270AC, 0x268AFCEF, + 0x700C0FC3, 0x744CD910, 0x708C706C, 0x0440250A, + 0xFCEF0A0A, 0xD88070CC, 0x764CD907, 0x708C706C, + 0x09FA70AC, 0x268AFCEF, 0x700C0FC3, 0xFCEF099E, + 0x0832712C, 0xC6D203C0, 0xC1A4C3EA, 0x45484668, + 0x41104030, 0x0F9770ED, 0x244A11F5, 0x40C37200, + 0x12208000, 0x20300935, 0x704C8820, 0x20A8706C, + 0x40200540, 0x209F6F95, 0x70020803, 0x2B41641C, + 0x640C00C0, 0x01802344, 0x01C02047, 0x102E0C3B, + 0xE212C080, 0xF029E312, 0xDA7EDBFE, 0x050020A8, + 0x6F954020, 0x0803209F, 0x641C7002, 0x00C02B41, + 0x2344640C, 0x20470180, 0x0C1901C0, 0xC080102E, + 0xBB72BA72, 0x41C3F011, 0x00020183, 0xF00878F4, + 0x003E2380, 0x41C378F4, 0x00020184, 0x740CB040, + 0xFE6F0DEE, 0x71E542E1, 0x1400F1B7, 0x244A3100, + 0xC28071C0, 0xB600B500, 0x038020A8, 0x05011202, + 0x090B9560, 0xB52000C5, 0x080B9600, 0x40200045, + 0x78E0B620, 0x78E0C7CA, 0xE808702C, 0x8002222F, + 0x6119B8C0, 0xF5FC4040, 0x78307FE0, 0x71001600, + 0x02909008, 0x78E07EE0, 0x0872C2E2, 0x08C6FD8F, + 0x4508FDAF, 0x70811600, 0x001C8000, 0xE80CE906, + 0xD87DED8B, 0xF019B807, 0xED8CE80B, 0x000040C3, + 0xF0134650, 0x40C3ED0A, 0x4A380000, 0xED0AF00D, + 0x000040C3, 0xF0095208, 0x000040C3, 0xF0052EE0, + 0x000040C3, 0x097E36B0, 0x742C0220, 0xC6C2780F, + 0x800040C3, 0x051D12DC, 0x8000FC6F, 0x45CBC2E4, + 0x12208000, 0x8D218D00, 0x0582209F, 0x02C1219F, + 0x100215BC, 0x60386058, 0xB8248801, 0xFC6F0EE6, + 0x058E205F, 0x00832079, 0x8D418D00, 0x0582209F, + 0x02C1229F, 0x100115BC, 0x0285239F, 0x60586038, + 0x63DB8803, 0xD80AB8E5, 0x022120CA, 0x2332631B, + 0x80000F80, 0xC6C407E0, 0x40C3C2E2, 0x12208000, + 0x88418820, 0x0582219F, 0x02C1229F, 0x000010BC, + 0x621A6038, 0xB8C38A02, 0xFC6F0E8A, 0x038D205F, + 0x00812079, 0x800040C3, 0x219F0646, 0x61B90483, + 0x60386112, 0x621A9001, 0xC6C27850, 0x4568C2E8, + 0x4050DB7F, 0x44604220, 0x248AE983, 0x8D850FC7, + 0x11041D06, 0xEA14E80E, 0x70811600, 0x01468000, + 0x40C3E91E, 0x01408000, 0xB5268861, 0xF0158820, + 0x1D08710C, 0xB8901001, 0xC6C8A503, 0x20100831, + 0x71011600, 0x01428000, 0x40C3E92E, 0x01388000, + 0xB5269062, 0xB5249020, 0xF031B565, 0x11041D0A, + 0x10051D08, 0x1D0CEC2A, 0xF0291085, 0x71011600, + 0x01448000, 0x40C3E918, 0x013E8000, 0x10FC9060, + 0xB5268100, 0xB504B565, 0x70801600, 0x000B8000, + 0x017E082B, 0x8008238C, 0x10051D08, 0x238AF78F, + 0xF1DC0FC7, 0x0FC7238A, 0x11041D0A, 0x10051D08, + 0x1D0CEC04, 0xF0031205, 0x41C3B506, 0x00030227, + 0xFC2F08D6, 0x00C0243D, 0x1104150C, 0x0400250A, + 0x95059544, 0x1D0E4851, 0x29081104, 0x78220101, + 0x022841C3, 0xB5050004, 0x0BA67B10, 0x740CFE6F, + 0x78E0C6C8, 0x084BC5E1, 0x712D00B5, 0x2078DD25, + 0xBD9F0008, 0x8D8D700C, 0x10F00C0F, 0x2444716D, + 0x20521040, 0x7015000B, 0x20CA8D80, 0xA90002C1, + 0x10002900, 0x7C0BAA00, 0x700C712C, 0xAB20F207, + 0x800041C3, 0x702D1220, 0x4021A900, 0xDD40C4C2, + 0x00882078, 0x700CBD9F, 0x0C118D8D, 0x716D10F0, + 0x10402444, 0x000B2052, 0x8D807015, 0x02C120CA, + 0x2900A900, 0xAA001000, 0x722C7C0B, 0xF5E1710C, + 0x78E0F1E5, 0x00700821, 0x7DE07014, 0x70801600, + 0x00258000, 0x00C02078, 0xA1007104, 0x800040C3, + 0xF0151224, 0x70801600, 0x00408000, 0x0050080F, + 0x00D10811, 0x00811900, 0x1900F006, 0xF0040041, + 0x00011900, 0x800040C3, 0x88201226, 0x8801AA20, + 0xAB007FE0, 0x0883C2E2, 0x45080030, 0x71021600, + 0x00148000, 0x00CF41C3, 0x0AB60001, 0xD8FFFE6F, + 0x08676D09, 0x120D01D5, 0x120B3083, 0x120C3604, + 0x20253605, 0xF0080000, 0xF010F00B, 0xF018F013, + 0xF024F01B, 0x41C3700C, 0x000300D0, 0x700CF022, + 0x00D141C3, 0xF01E0003, 0x41C3700C, 0x000300D2, + 0x700CF018, 0x00D341C3, 0xF0140003, 0x41C3700C, + 0x000300D4, 0x120BF00E, 0x41C33082, 0x000400D5, + 0xFBEF0F56, 0xC6C2700C, 0x41C3700C, 0x000300D6, + 0x43804260, 0xFBEF0F42, 0x0140240A, 0x78E0C6C2, + 0x000043CB, 0x242F28F0, 0x201F12C0, 0x7B8A02C0, + 0x108B2B41, 0x02C1211F, 0x0184229F, 0x60386078, + 0x42C36058, 0x1A3E8000, 0x08012256, 0x78356029, + 0x61116A2A, 0x48326050, 0x71447030, 0x002522CA, + 0x78507FE0, 0x1CFCC2FA, 0xC1A6B6C8, 0x16004608, + 0x80007100, 0x4528000A, 0xC3414358, 0x781DC043, + 0x87812044, 0xC045710C, 0xC042D810, 0x090DF207, + 0x700C00B1, 0xF003C045, 0x208AC142, 0xB6010004, + 0xAE00D820, 0x081FC003, 0xD8C8007E, 0x8D409561, + 0x021A41C3, 0x121C0004, 0x09963705, 0x121DFE6F, + 0x8D003704, 0xC2014363, 0x95E14210, 0x0AE641E1, + 0x41F1FDAF, 0xC0034010, 0x007E081D, 0x9561D8C8, + 0x41C38D40, 0x0004021B, 0x0400240A, 0xFE6F0962, + 0x0400250A, 0x7014C002, 0x7216F2BC, 0x00250174, + 0xC002746E, 0x70CE8DE0, 0xB82295A1, 0x1410C044, + 0x22003015, 0x240A24C0, 0x210A2440, 0x20533400, + 0x22020150, 0x0D1124C0, 0x20531521, 0x0F1B0151, + 0x70EE1460, 0x4022C201, 0x0A7A4182, 0x4363FDAF, + 0x15210D0B, 0x0F254710, 0xC2011400, 0x41824002, + 0xFDAF0A62, 0x0F154363, 0x081F2005, 0x47100664, + 0x220A474A, 0xF00B2400, 0xA640270C, 0x148627CA, + 0x244622CA, 0x270AF743, 0x24002640, 0x240224C0, + 0x205324D1, 0x21530218, 0x77522211, 0x944125CC, + 0x0D21F405, 0x700E1621, 0xC201F01B, 0x41224042, + 0xFDAF0A12, 0x40104363, 0x25CC7752, 0xF2119601, + 0x4042C201, 0x09FE4103, 0x4363FDAF, 0x20050813, + 0x05E40819, 0x2600210A, 0x4010458A, 0x200CF00A, + 0x25CAA5C0, 0xF7461506, 0x2500210A, 0x25C0200A, + 0x26610817, 0x30141410, 0xF547262F, 0x2542F204, + 0xF0032054, 0xC003708E, 0x007E082D, 0x2507252F, + 0x41C3D8C8, 0x0007021C, 0x434242C2, 0x0440240A, + 0x0400250A, 0x0400260A, 0x04C0270A, 0xFE6F0832, + 0x35401C00, 0x08178E00, 0x0D170481, 0x96012010, + 0x0440080F, 0x2500250A, 0x0DFDF012, 0x1410A011, + 0x202F3015, 0x431084C2, 0x716EF404, 0x2500250A, + 0x00012079, 0x2005C005, 0xF20C807E, 0xC00271C6, + 0xA000260C, 0x14441E02, 0xFFE506AA, 0x14821E00, + 0xC0A64002, 0x341B1404, 0x78E0C6DA, 0x44CBC0E6, + 0x12D98000, 0x8C204028, 0x7100244A, 0x70AD70CD, + 0x20A8708D, 0x091B0240, 0x7185030F, 0x000075C3, + 0x702C8000, 0x900345CB, 0x706DC000, 0x6892F015, + 0x10812800, 0x79647D85, 0x1F8C2505, 0x00009038, + 0x25059480, 0x903B1F8D, 0x2406C000, 0x7C6410CF, + 0x2C0179E5, 0x0C43108B, 0xB5200031, 0x708C1600, + 0x00258000, 0x1600EC88, 0x8000708C, 0xEC140040, + 0xBE0CDE07, 0x28007E05, 0x6E52108C, 0x22057C64, + 0x90000F81, 0x91200000, 0x0F8D2205, 0xC0009003, + 0x79857966, 0x4061B520, 0x78E0C4C6, 0x1CFCC2FA, + 0xC1ADB6C8, 0x4210C71D, 0x70801600, 0x00148000, + 0x21C0200A, 0x41384150, 0x700F70EE, 0x31801C2C, + 0x31401C04, 0x31001C28, 0x013E081B, 0x1600C349, + 0x80007080, 0x080F001E, 0x710F003F, 0x05400C5A, + 0x97C44018, 0x20C02242, 0x0175082F, 0x0D8297A1, + 0xE815FE4F, 0x800040C3, 0x88411222, 0x0A1F8800, + 0x790F0004, 0x27147104, 0x19241041, 0x790F05C4, + 0x80450AF3, 0x0ADBF003, 0x2178A050, 0xD80930D2, + 0x30F10911, 0xD80AC040, 0x3240234A, 0xF003C040, + 0x0842706F, 0x0E360380, 0xD8C8FCAF, 0xFCAF0E3E, + 0x7056970E, 0x900446D3, 0x40C33DD0, 0x01D09004, + 0x200226CA, 0x3031080D, 0x2004258A, 0x2002258A, + 0x2538C01C, 0x704E1393, 0x800044D3, 0xC04C1222, + 0x30002150, 0x40C3C045, 0x28F00000, 0x2001211F, + 0x201F781B, 0x60382000, 0x4063C043, 0x0184209F, + 0x6038C103, 0x0F812000, 0x1A3C8000, 0x800070C3, + 0xC0481A3E, 0xC042720C, 0x30802178, 0xC1477204, + 0x710CC046, 0x45CBC044, 0xC2CC9007, 0x20300A1D, + 0x0FC7208A, 0x732EB500, 0x15C41D04, 0x0819C005, + 0x97C800B1, 0xF009BE07, 0x712E70CD, 0x15C41D00, + 0xF003B502, 0x1400BE08, 0x14012090, 0x202F208B, + 0x0B930407, 0x43A21024, 0x70811600, 0x12D98000, + 0x002E097F, 0x10012714, 0x038B2840, 0x1F822305, + 0x3ED49004, 0xB90A9132, 0x04412105, 0xC109B220, + 0x000021F4, 0x30300829, 0x0A1960D8, 0x79102030, + 0x08002155, 0x0FCF218A, 0x8FCF208C, 0xF009F7C8, + 0x8002218C, 0xF785702C, 0x003E2080, 0x23054100, + 0xB0201580, 0xE815CC20, 0x712CD840, 0x15C41D00, + 0x03E009E6, 0x15C41D04, 0x70801600, 0x00088000, + 0xD8407414, 0x20CAD944, 0x1DF40041, 0x71069004, + 0xCC20F1B5, 0xC106E827, 0x20032D01, 0x00412800, + 0x1400633B, 0x0B3F2081, 0x16001044, 0x80007088, + 0x782F12D9, 0x102E0827, 0x2005B80E, 0x90040F82, + 0x9200029C, 0x05C41A00, 0x0F8C2004, 0x1FFE0000, + 0xB80DCC20, 0xBC807C05, 0x7124B280, 0x0BD7782F, + 0x78709005, 0xFCAF082E, 0x7076702C, 0x14B7F26F, + 0x14012088, 0x8F05208B, 0x208E1400, 0x268AE82E, + 0x7BCF0FC7, 0x10C40BC5, 0x10CE084D, 0x0F82231F, + 0x0A3C0000, 0xC008C407, 0x621A645C, 0xC1004063, + 0x00450835, 0xE988C101, 0x06812300, 0x0081111C, + 0x00400819, 0x7001248A, 0x41404189, 0x018020A8, + 0x00151904, 0x11941904, 0x11842480, 0x01842280, + 0xF1E77104, 0xF1D771C5, 0x128D265F, 0x7ACF7563, + 0x10840B69, 0x10AE085F, 0x416344A9, 0x0957C000, + 0xC0010005, 0x2200E887, 0x101C0680, 0x09410080, + 0x788F0000, 0x7002248A, 0x000E209F, 0x0F832000, + 0xC1448000, 0x20A8C00C, 0x1B0201C0, 0x1B040014, + 0x225F0015, 0x60F80500, 0x3030080D, 0x18347834, + 0xF0060FC5, 0x23F4C30A, 0xB07A0083, 0x71247185, + 0xE50AF1D6, 0xF1CD71C5, 0x0A7E706E, 0x1400FC4F, + 0x14012090, 0x262F2080, 0x08771407, 0x714E03A4, + 0x70801600, 0x12D98000, 0x03AE0863, 0x13912E40, + 0xC000456B, 0x10050D57, 0xE888C001, 0x16802600, + 0x0080101C, 0x10000D43, 0x12802D40, 0x20CA7337, + 0x20050021, 0x20050440, 0x90040F80, 0xC10B01D0, + 0x0FF87034, 0x9000FD61, 0x1502265F, 0x7034C104, + 0x800041C3, 0x7AB4BE24, 0x6159F204, 0xF005B100, + 0x19506159, 0x71A50004, 0x7106F1D5, 0xC102F1C3, + 0xC1427724, 0x702C7034, 0xFFE2056E, 0x1400C144, + 0x202F2091, 0x200C2447, 0x012EA000, 0x1600000D, + 0x80007081, 0x211112D9, 0xF28D8400, 0x2295215E, + 0xC000466B, 0x010A7610, 0xC0010006, 0x2000E887, + 0x101C2680, 0x0EA10080, 0x205F1000, 0x40C32501, + 0xBE248000, 0x03832114, 0x6315607A, 0x01121250, + 0xE82E8F05, 0xDB3F9724, 0x48319701, 0x29049707, + 0x78300001, 0x023E41C3, 0x42000002, 0x000120BC, + 0xFBEF0816, 0x201F4350, 0x00002F81, 0xC0030A3C, + 0x40C16119, 0x0184209A, 0x21156119, 0x200004C0, + 0x80000F81, 0x70C31A3C, 0x1A3E8000, 0x23650A33, + 0x0FC7228A, 0x05C41800, 0xF016B140, 0x23640A29, + 0x79D461F9, 0x082D911A, 0x00000F81, 0x2200FFFF, + 0xE0FF2340, 0x1934F70A, 0x700C05C4, 0xB1A0F00A, + 0x04841800, 0xF1A771C5, 0x2080781D, 0xB11A003F, + 0x78109728, 0x75104D12, 0x0480200E, 0x23832500, + 0x004B2A04, 0x28047C6F, 0x23CA0040, 0x7A101025, + 0x02C8212F, 0x80640AD1, 0x215F4081, 0x209F0181, + 0x6119000E, 0x800040C3, 0x6038C144, 0xB0219721, + 0x90609721, 0x00C50907, 0x7165B020, 0x1401F1EA, + 0x71262080, 0xC0ADF167, 0x341B1404, 0x78E0C6DA, + 0x47CBC2FA, 0x12228000, 0x240A8FC0, 0x250A2180, + 0x260A2140, 0x47702100, 0x41384058, 0x8F014110, + 0x03840899, 0x800040C3, 0x880012D9, 0x03AE0889, + 0x1105704E, 0x700E2080, 0x27F4E883, 0x265A2390, + 0x11051293, 0xE81D2080, 0x000040C3, 0x791B28F0, + 0x3002211F, 0x3041201F, 0x78CCB822, 0x611A6159, + 0x209A4042, 0x621A0184, 0x800040C3, 0x60591A3C, + 0x91016215, 0x0345081B, 0x700C70AD, 0x0B82F009, + 0x4062FF6F, 0x40624508, 0xFF6F0BA6, 0x60B941A1, + 0x24C22614, 0x7502793D, 0x71467102, 0x2514B220, + 0xB1A024C1, 0x04012000, 0x24C02414, 0x0A977166, + 0xB020A2B4, 0xF1B571C5, 0x78E0C6DA, 0x800041C3, + 0x89011222, 0x71108920, 0x07CD20E0, 0x29407822, + 0x71040382, 0x7000240A, 0x030020A8, 0x0F812205, + 0x01D09004, 0x72C39100, 0x40000000, 0xB100E020, + 0x78E07EE0, 0x0343236F, 0x800041C3, 0x93000458, + 0x208CDA08, 0xD8088059, 0x02A520CA, 0x9300B100, + 0x8059208C, 0x20CAD808, 0xB10102A5, 0x208C9300, + 0xD8088059, 0x02A520CA, 0x9300B102, 0x8059208C, + 0x02A522CA, 0xB1437FE0, 0xC1A2C3EE, 0x42104728, + 0x0C0D2055, 0x0D124020, 0x702CFD6F, 0x40424010, + 0x090E702C, 0xDACAFBAF, 0x208A71CD, 0xB5C20016, + 0x20041AC2, 0x0C15208A, 0x1600B500, 0x80007080, + 0x20440009, 0x710C8091, 0x00A120CA, 0x22431AC6, + 0x03200A1A, 0x20021AC9, 0x22408D24, 0xADC82403, + 0x200D2178, 0x424240E1, 0x71AC708C, 0xFEEF0BDA, + 0x12C546A1, 0x22402081, 0x22402202, 0x40E12603, + 0x71AC708C, 0xFEEF0BC2, 0x47CB46A1, 0x12228000, + 0x8F018FC0, 0x03840841, 0x238D2214, 0x0C9AC180, + 0x9500FD6F, 0x0C929504, 0xC181FD6F, 0x0BBAC080, + 0x712C0120, 0xFE2F090E, 0xB500C080, 0x0BAAC081, + 0x712C0120, 0xFE2F08FE, 0xB504C081, 0x76108F01, + 0xF7A471C5, 0x05000CE2, 0x70148FC0, 0x2040740C, + 0x20CA2413, 0x204001E2, 0x1AC72491, 0x8F012002, + 0x03A4085F, 0x13102E40, 0x265A70AD, 0x2D401503, + 0x22051202, 0xC8080402, 0x41C37A05, 0x00009004, + 0x04402205, 0x04C22205, 0xB8027342, 0x78257BB4, + 0x01051000, 0x1B206A12, 0x78250144, 0x01041000, + 0x1B70740C, 0x41C30104, 0x000401C7, 0x0FD242C1, + 0x43A1FDEF, 0x0DB771A5, 0x71C59254, 0xC7CEF1D1, + 0x40C3C0F1, 0x12208000, 0xC8088880, 0x7885BC0C, + 0x0F802005, 0x0FD80003, 0x05200F3A, 0xC808702C, + 0x6C127C05, 0x0F802005, 0x0364900C, 0x7FE0C0D1, + 0x00051800, 0xD9FFD838, 0x1803B89F, 0x18FC0052, + 0x18018042, 0x18160052, 0x18010052, 0xA8200052, + 0x7FE0A823, 0x78E0A824, 0xD9FFD83A, 0x1803B89F, + 0x18FC0052, 0x18018042, 0x18160052, 0x18010052, + 0xA8200052, 0x7FE0A823, 0x78E0A824, 0x200AC2E8, + 0x47682100, 0x45284648, 0x0135080B, 0xBA0E4200, + 0x0A0FF00D, 0x700C03F1, 0xBA0EDA1F, 0x41C3F008, + 0x00010030, 0xFB8F0C22, 0xBA92704C, 0x900040C3, + 0x22053A90, 0x74040001, 0x2205B1A0, 0x74040001, + 0x2205B1C0, 0x74040001, 0xB1E07845, 0x04041800, + 0x78E0C6C8, 0x4110C2EE, 0x230A4040, 0x220A2140, + 0x45682100, 0xFEAF0BAE, 0x46084030, 0xFEAF0BA6, + 0x470840A1, 0xFEAF0B9E, 0x45084042, 0xFEAF0B96, + 0x09214062, 0x092D2090, 0x09472050, 0x42222031, + 0x901C42C3, 0x41C3006C, 0xF8A89007, 0xF011B2C0, + 0x901C42C3, 0xB2C000EC, 0x900741C3, 0xF009F928, + 0x901C42C3, 0xB2C000AC, 0x900741C3, 0xB2E2F8E8, + 0xB102B1A0, 0x84041AD4, 0x840419D8, 0x41C3C6CE, + 0x0001002F, 0xFBAF0B72, 0xC6CE700C, 0x45CBC5E1, + 0x006C901C, 0x10141D04, 0x900744CB, 0x1D3CF8A8, + 0x1C041054, 0x1C3C1094, 0x1D0410D4, 0xB5201014, + 0x10941C04, 0xB51EB460, 0x10441D40, 0x1C40B45E, + 0xC4C210C4, 0x1600C2E2, 0x90307100, 0x45CB0200, + 0x4FC48001, 0x1A11DAB0, 0x206D3003, 0x40C30081, + 0x04A88000, 0x40A1A820, 0xFB6F0E26, 0x42C3702C, + 0xFFFC7FFF, 0x10802504, 0x2000B822, 0x00050F81, + 0x12688000, 0x20790600, 0x1A680000, 0x1A090058, + 0xC6C23002, 0x0FBAC3EC, 0xC1A1FBEF, 0x800040D3, + 0x205410D4, 0x70CD280F, 0x254270AD, 0x08111700, + 0x160001D5, 0x80007080, 0xE8130131, 0x14032532, + 0x1700700C, 0x762C1084, 0x254A704C, 0x08FE03C0, + 0x70CCFC6F, 0xD922700C, 0xFC6F0BE6, 0x71A5704C, + 0x98F40DCB, 0x700C71E5, 0xFC6F0892, 0xDD25712C, + 0xBD9F714E, 0x702C722E, 0x8D40720E, 0x7A058D1B, + 0x20402A00, 0x200FB802, 0x7F4B004F, 0x0E6AF21B, + 0x40C10060, 0x0F3AE817, 0x252FFBCF, 0x700C03C7, + 0x704C762C, 0x244ADBD0, 0x08A20300, 0x70CCFC6F, + 0xD922700C, 0xFC6F0B8A, 0x700C704C, 0xFC6F083E, + 0x208D712C, 0x712C277F, 0x25FF218D, 0xD98271CD, + 0xB99F70CD, 0x800047CB, 0x712E1220, 0x04801101, + 0x0140206C, 0x0E002045, 0x8900C060, 0x0140206C, + 0x0E002045, 0x30021C01, 0x206C8901, 0x20450140, + 0x1C020E00, 0x89023002, 0x0140206C, 0x0E002045, + 0x30021C03, 0x790F700C, 0x00B50979, 0xE906AF00, + 0xE8888D1B, 0xF034710C, 0x70148D00, 0xF230700C, + 0x20402900, 0xFEAF0826, 0x0E96780F, 0x702CFBCF, + 0x8D60720E, 0x7B058D1B, 0x20402900, 0x200FB802, + 0x7A6B0042, 0x8F60F20F, 0x252FC080, 0x704C0087, + 0x0440244A, 0x787470CC, 0x700C602B, 0xFC2F0FDE, + 0x208D762C, 0x712C2A7F, 0xD922700C, 0xFC6F0AC2, + 0x700C704C, 0xFC2F0F76, 0x8F00712C, 0xF1C57104, + 0xFE6F0FCA, 0xB7C0730C, 0x78E0C7CC, 0x0FDEC0F1, + 0x208A00E0, 0x7910041F, 0x0A96700C, 0x704CFC6F, + 0x7EE0C0D1, 0x4508C2E2, 0xB813D841, 0x744CD907, + 0x708C706C, 0x0F8670AC, 0x70CCFC2F, 0xFC4F0A2A, + 0xD90740A1, 0x706C744C, 0x70AC708C, 0xFC2F0F6E, + 0x09FE70CC, 0x40A1FC4F, 0x744CD907, 0x708C706C, + 0x0F5A70AC, 0x70CCFC2F, 0xD907D880, 0x744CB893, + 0x708C706C, 0x0F4670AC, 0x70CCFC2F, 0x78E0C6C2, + 0x800042C3, 0x8A401225, 0x0042223C, 0x16007854, + 0x80007082, 0x22110121, 0x21448000, 0x20F90040, + 0x7FE00022, 0x002120F8, 0x4608C2E4, 0x800040C3, + 0x88001225, 0x203C4528, 0x0CAE0040, 0x41C10060, + 0x710C7014, 0x038120CA, 0xFFE10FB8, 0xC6C441A1, + 0x0927682B, 0x71140175, 0x71011600, 0x00148000, + 0x210B710C, 0x00008F80, 0xF2034008, 0x782D7EE0, + 0x207A7FE0, 0x700C0000, 0xF1FAF3F0, 0x4220C0F1, + 0x2144B923, 0xBAC50601, 0x81006119, 0xFB6F0F3E, + 0xB8C08121, 0x7FE0C0D1, 0x00002078, 0x2482C3EC, + 0x45083708, 0x087AC087, 0x41A1FF2F, 0xC18240A1, + 0xFD2F0E46, 0x31C22440, 0xC7CCE802, 0x30801407, + 0x00B00811, 0x080F72CD, 0x704E00F0, 0xF00370CD, + 0x702E714E, 0xC080C182, 0x42A179D5, 0xFFAF091A, + 0x080FC387, 0xC7200444, 0x14024110, 0x76523110, + 0xF63277C5, 0xA03009C7, 0x1D82750C, 0x2580141C, + 0x700C1084, 0xC7CCADE0, 0xC1A2C3E6, 0x70AD4708, + 0x800146CB, 0xC5414D7C, 0x0071080D, 0xD864C540, + 0xF066B600, 0xB606D8C8, 0x080FF062, 0xE8890050, + 0xB808D87F, 0xD87FF003, 0xC040B810, 0xD9FFF006, + 0x0FA6700C, 0xB910FB6F, 0x10710F0D, 0x26F44E1C, + 0xF0041340, 0x034020F4, 0x0882B802, 0x7810FC6F, + 0xD907D841, 0xDA08B813, 0x708C706C, 0x0DCE70AC, + 0x70CCFC2F, 0x742C700C, 0xFC6F08B6, 0xC080714C, + 0x080E41E1, 0x724CFC6F, 0xD914700C, 0xFC6F08A2, + 0x706C714C, 0x4060D907, 0xB892744C, 0x70AC708C, + 0xFC2F0D9A, 0x160070CC, 0x80007080, 0x0811000C, + 0x700C003E, 0x087AD914, 0x714CFC6F, 0xD907D880, + 0xDA08B893, 0x708C706C, 0x0D7270AC, 0x70CCFC2F, + 0xFBCF0BD6, 0x13412614, 0x10710F0F, 0xB1016849, + 0xB14C71A5, 0xB107F004, 0xB15271A5, 0x90B40D3F, + 0xC7C678B0, 0x702CC2E4, 0x4508DA4B, 0xFB6F0A02, + 0x090E2055, 0x704CD95A, 0x1104B99F, 0xAD010480, + 0x04801104, 0x1104AD02, 0xAD030480, 0x04801104, + 0x1104AD0A, 0xAD0B0480, 0x04801104, 0x1104AD0C, + 0xAD0D0480, 0x04801104, 0x1104AD0E, 0xAD0F0480, + 0x04801104, 0x1104AD10, 0xAD110480, 0x04801104, + 0x1104AD12, 0xAD130480, 0x04801104, 0x1104AD14, + 0xAD150480, 0x04801104, 0x1104AD16, 0xAD180480, + 0x04801104, 0x1104AD19, 0xAD1A0480, 0x04801104, + 0x1104AD1B, 0xAD1C0480, 0x04801104, 0x1104AD1E, + 0xAD1F0480, 0x04801104, 0x10021D20, 0x04801104, + 0x10021D21, 0x04801104, 0x10021D22, 0x04801104, + 0x10021D25, 0x04801104, 0x10021D28, 0x04801108, + 0x10021D29, 0x10821D2E, 0x04801104, 0x10021D3A, + 0x04801104, 0x10021D45, 0x04801104, 0x10021D46, + 0x04801104, 0x10021D47, 0x84801179, 0x10021D48, + 0x0080118B, 0x10021D49, 0x0080118F, 0x10021D4A, + 0x04801104, 0x10021D4C, 0x04801104, 0x10021D4D, + 0x04801104, 0x10021D4E, 0x04801104, 0x10021D55, + 0x04801104, 0x10021D56, 0x04801104, 0x10021D57, + 0x04801104, 0x10021D58, 0x04801104, 0x10021D59, + 0x04801104, 0x10021D5A, 0x04801104, 0x10021D5B, + 0x04801104, 0x10021D5C, 0x04801104, 0x10021D5D, + 0x04801104, 0x10021D5E, 0x04801104, 0x10021D5F, + 0x04801104, 0x10021D60, 0x04801104, 0x10021D61, + 0x04801104, 0x10021D63, 0x04801104, 0x10021D64, + 0x04801104, 0x10021D65, 0x04801104, 0x10021D66, + 0x04801104, 0x10021D67, 0x04801104, 0x10021D69, + 0x04801104, 0x10021D6A, 0x04801104, 0x10021D6B, + 0x04801104, 0x10021D6C, 0x04801104, 0x10021D6D, + 0x04801104, 0x10021D70, 0x04801104, 0x10021D73, + 0x04801108, 0x10021D74, 0x10821D79, 0x04801104, + 0x10021D85, 0x04801104, 0x1104AE00, 0x1D910480, + 0x11041002, 0x1D920480, 0x11791002, 0x1D938480, + 0x118B1002, 0xAE040080, 0x0080118F, 0x10021D95, + 0x04801104, 0x10021D97, 0x04801104, 0x1104AE08, + 0x1D990480, 0x11041002, 0xAE100480, 0x04801104, + 0x10021DA1, 0x04801104, 0x10021DA2, 0x04801104, + 0x10021DA3, 0x04801104, 0x1104AE14, 0x1DA50480, + 0x11041002, 0x1DA60480, 0x11041002, 0x1DA70480, + 0x11041002, 0xAE180480, 0x04801104, 0x10021DA9, + 0x04801104, 0x10021DAA, 0x04801104, 0x10021DAB, + 0x04801104, 0x1104AE1C, 0x1DAE0480, 0x11041002, + 0x1DAF0480, 0x11041002, 0x1E200480, 0x11041002, + 0x1DB10480, 0x11041002, 0x1DB20480, 0x11041002, + 0x1E240480, 0x11041002, 0x1DB50480, 0x11041002, + 0x1DB60480, 0x11041002, 0x1DB70480, 0x11041002, + 0x1E280480, 0x11041002, 0x1DBB0480, 0x11041002, + 0x1DBE0480, 0x11081002, 0x1DBF0480, 0x1E341002, + 0x11041082, 0x1E400480, 0x11041002, 0x1DDB0480, + 0x11041002, 0x1E4C0480, 0x11041002, 0x1DDD0480, + 0x11791002, 0x1DDE8480, 0x118B1002, 0x1DDF0080, + 0x118F1002, 0x1E500080, 0x11041002, 0x1DE20480, + 0x11041002, 0x1DE30480, 0x11041002, 0x1E540480, + 0x11041002, 0x1DEB0480, 0x11041002, 0x1E5C0480, + 0x11041002, 0x1DED0480, 0x11041002, 0x1DEE0480, + 0x11041002, 0x1DEF0480, 0x11041002, 0x1E600480, + 0x11041002, 0x1DF10480, 0x11041002, 0x1DF20480, + 0x11041002, 0x1DF30480, 0x11041002, 0x1E640480, + 0x11041002, 0x1DF50480, 0x11041002, 0x1DF60480, + 0x11041002, 0x1DF70480, 0x11041002, 0x1DF90480, + 0x11041002, 0x1DFA0480, 0x11041002, 0x1DFB0480, + 0x11041002, 0x1E6C0480, 0x11041002, 0x1DFD0480, + 0x11041002, 0x1DFF0480, 0x25561002, 0x11041800, + 0xA8600483, 0x238043A1, 0x11040044, 0xAB000480, + 0x04801104, 0x1104AB01, 0xAB020480, 0x04801104, + 0x1104AB05, 0xAB080480, 0x04801108, 0xAB4EAB09, + 0x04801104, 0x1104AB1A, 0x1B250480, 0x11040002, + 0x1B260480, 0x25560002, 0x11041940, 0xA8400482, + 0x1B288900, 0x89040002, 0x00021B29, 0x1B2A8908, + 0xC6C40002, 0x1CFCC2FA, 0x256FB6C8, 0x8D001243, + 0x017E084F, 0x42C3C1AE, 0x00349018, 0x05001204, + 0x800041C3, 0x1902018C, 0x12040014, 0x19020500, + 0x12040014, 0x19020500, 0x12E00014, 0xB1008500, + 0x6872C808, 0x00802305, 0xB1039000, 0x03002242, + 0x90007865, 0x6A0CB101, 0x90007865, 0xC08CB102, + 0x800041C3, 0x0D320635, 0x764CFB2F, 0x0DAEC08C, + 0x762C0520, 0xD9258D00, 0xB99FB8C3, 0x70041E00, + 0x022C9008, 0x42C38900, 0x01C8901C, 0x891BB200, + 0x11F4B202, 0xE8968080, 0x03000C56, 0x2042C805, + 0xF210803C, 0x20A8700C, 0x20050380, 0x90040F82, + 0x9220028C, 0x000070C3, 0x21444000, 0xB2200301, + 0x902C41C3, 0x91000C98, 0x78259122, 0x001E0815, + 0x71001600, 0x00068000, 0x0F84080D, 0x0C810000, + 0xFC8F0DAA, 0x00000BB6, 0x70801600, 0x011D8000, + 0x0AFAE807, 0xC0AE0300, 0x341B1404, 0x1600C6DA, + 0x80007080, 0x701400F3, 0x00010370, 0x702E700C, + 0x1E00B88C, 0x90077444, 0x43DBC3E8, 0xC83C9007, + 0x70041E00, 0xC3649007, 0x40DBC808, 0x00009000, + 0x20056892, 0x00010F80, 0x24050027, 0x90041F83, + 0x9340083C, 0x16C12405, 0x0F822204, 0xFF780000, + 0x01822285, 0x2405B140, 0x90071F82, 0xC04BC09C, + 0x2005B802, 0xC2450600, 0x9040C048, 0xBAA0C005, + 0x1600B040, 0x90047100, 0xB8A00AB0, 0x70041E00, + 0xCAB09007, 0x20459300, 0xB1A0014D, 0x70801600, + 0x00088000, 0x01002079, 0x2040B802, 0x2B40030B, + 0x0F861240, 0x20960120, 0xC8080208, 0x47CBBDA0, + 0x12228000, 0x22056852, 0xB1A006C1, 0xB7209721, + 0x0F812205, 0x08249004, 0x34401C0C, 0x34401C08, + 0x34401C04, 0x793B9120, 0x0F872184, 0x231F7124, + 0x21551041, 0xC1460DC1, 0x0F812205, 0x01909038, + 0xC14A9120, 0xB962C181, 0x702CC149, 0x202FC144, + 0x28402447, 0x20052312, 0x68520480, 0x900440C3, + 0x22050A80, 0x74040001, 0x43839120, 0x2205B322, + 0x91200001, 0xB3237404, 0x00012205, 0x74049120, + 0x2205B324, 0x91200001, 0xB3257404, 0x208A7A05, + 0x92200FCF, 0x2840B307, 0xB3262380, 0x0F8E2005, + 0x0AB09004, 0x9600C047, 0x0001204F, 0xB8A0B620, + 0xC007B600, 0x0F802005, 0x03549004, 0x090BC10A, + 0x9000027F, 0x140C781D, 0x7D103107, 0x3106140A, + 0x1404740C, 0x41C33103, 0x0007005A, 0x31051408, + 0x14064202, 0x240A3117, 0x0AF605C0, 0xC540FDAF, + 0x16D5255F, 0x30141424, 0x702F706E, 0x29012D85, + 0x15562502, 0x23552500, 0x21001402, 0x71021600, + 0x00068000, 0x0A11791B, 0x00000F85, 0x0D2D0C80, + 0xF0201045, 0x03440925, 0x30100915, 0x21011400, + 0x0D197822, 0x08152002, 0xF0140582, 0x05C0200E, + 0x20020D09, 0x058308EF, 0x2179D95D, 0x0F9A3100, + 0xB910FB2F, 0x72867127, 0xB17409B1, 0x756E7166, + 0x2205C808, 0x00012F86, 0x2005020F, 0x20050481, + 0xB9020180, 0x2105B802, 0x90040F81, 0x19000AB4, + 0xD99C04C4, 0x70441E00, 0xC3649007, 0x2005C10B, + 0x21050600, 0xB9020481, 0x060B2105, 0x11091300, + 0x1001214F, 0x10441B00, 0x256C90A0, 0xB9801041, + 0x0DC6B020, 0xC0060120, 0x10002150, 0x1B00BDA0, + 0xC8081004, 0x01812005, 0x2105B902, 0xB1A00601, + 0x214F9620, 0xB6400002, 0xB620B9A0, 0x04812005, + 0x2105B902, 0x90040F82, 0xC1070ABC, 0x0F812105, + 0x03589004, 0xB2209120, 0x080D8F23, 0x218C2065, + 0xF4118FC3, 0x20610815, 0x8F258F44, 0x72304150, + 0x21CAC104, 0xF00A006D, 0x2084080F, 0x080B8F25, + 0x71262045, 0x712CF003, 0xC104C144, 0xF3117034, + 0x706EF003, 0xC108F196, 0x91A0B802, 0x254FC105, + 0xB1401002, 0x06C12005, 0x0F802005, 0x083C9004, + 0x266C90C0, 0xB8801040, 0x0D1EB100, 0xC0060120, + 0xBDA0C005, 0xB0A0BEA0, 0xB802C808, 0x06C12005, + 0x8FA0B1C0, 0x8F017AAF, 0x04CA7210, 0x40C3FFCD, + 0x12D98000, 0x08418800, 0x2A4000AE, 0x2405038C, + 0x90041F80, 0x90600354, 0x2353C808, 0xB8020201, + 0x20057885, 0x90380F8C, 0x9400021C, 0x0F802004, + 0xFE000000, 0x41C37825, 0x00020062, 0x0922B400, + 0x740CFDAF, 0xF1D871A5, 0x800041C3, 0x9100018A, + 0x8701113E, 0xF7877110, 0xFC8F0C2A, 0x04807014, + 0x0463FFC1, 0x78E0FFCF, 0xC808C2E6, 0x21056832, + 0x90070F80, 0x2105C83C, 0x90040F81, 0x9120083C, + 0x0F812104, 0xFF780000, 0x01812145, 0x1600B020, + 0x80007087, 0x0E5A0005, 0x710C0320, 0x47CB712D, + 0x0084900C, 0x0F9574CC, 0x1F000030, 0x700C1244, + 0x01200CD2, 0x702C742C, 0x901840C3, 0xB7200008, + 0x02441800, 0x824418FC, 0x70441E00, 0x0C40902C, + 0x804418F8, 0x009840C3, 0x0CAA9680, 0x46280120, + 0x47CBD833, 0x08009008, 0x45CBB700, 0x02889008, + 0x0C06D820, 0xB5C00120, 0x900743CB, 0x1D58C11C, + 0x208A9244, 0x1B000010, 0x1B001145, 0x234F1184, + 0x1B0014CB, 0x1B001145, 0x1D001184, 0x0BDA1085, + 0x1D580120, 0x700C9384, 0xB5C0D920, 0x01200C56, + 0x1B0CB7C0, 0xF0659244, 0x01200BBE, 0x46CB740C, + 0x00189018, 0x950016F0, 0x2004702C, 0x00000F80, + 0x1E00FDFF, 0x901B7004, 0x40C3C018, 0x4240000F, + 0xB7204528, 0x4708B620, 0x70441E00, 0x0C40902C, + 0x90441EFC, 0x90441EF8, 0x01200C0A, 0x10C51E04, + 0x78FD720D, 0x0BFE702C, 0x1E040120, 0x702C1204, + 0x009840C3, 0x0BEE9680, 0xB6A20120, 0x900843CB, + 0x47C301E0, 0xC11C9007, 0x12441B00, 0x1F00D833, + 0x47CB0145, 0x08009008, 0x01841F00, 0x04C7274F, + 0x1A8E2355, 0x01451F00, 0x01841F00, 0x760CB700, + 0x01200B26, 0x700CB6A0, 0x000041C3, 0x1B002710, + 0x0BA21204, 0x1E000120, 0x700C1204, 0x1B00D920, + 0xB6A01344, 0x01200B8E, 0x1F0CB7A0, 0x0CB68244, + 0x710C01E0, 0x01200AF2, 0x46CBD878, 0xC11C900F, + 0x14CF2650, 0x1E00710C, 0x1E001185, 0x1F001105, + 0x08D61185, 0x1F0000E0, 0x0EF21105, 0x208AFDCF, + 0x45CB0D07, 0x03E09008, 0x0B4AD920, 0x1D000120, + 0x700C1045, 0x1EB2B88C, 0xD820101C, 0x101D1F84, + 0x01200AA6, 0x10051D00, 0x78E0C6C6, 0x78E07EE0, + 0x78E07EE0, 0x16007A1B, 0x80007080, 0x7859001C, + 0x7FE07839, 0x78E0B8C0, 0x2079C2F0, 0x43500050, + 0x45CB4728, 0x11DA8000, 0x03200ECA, 0x204E2014, + 0x66A8704E, 0x20250A2B, 0x20166F14, 0x70420400, + 0x60A9E024, 0x084ED880, 0x41300360, 0x23912940, + 0x21057146, 0x90042F81, 0xB1000230, 0x40C3F1EB, + 0x4E200000, 0x01200ABE, 0x66A8702C, 0x21D3234F, + 0x702EE82B, 0x20166F14, 0x70220400, 0x60A9E024, + 0x08124062, 0x42300360, 0x23942A40, 0x2F812405, + 0x02309004, 0x0A66B100, 0x740C0120, 0x2FC7228A, + 0x2F802405, 0x02249004, 0x04841800, 0x01200A4E, + 0x2405740C, 0x90042F80, 0x1800022C, 0x71260484, + 0x09B566A8, 0xD90CA004, 0x000040C3, 0x0A561388, + 0x44100120, 0xE81A66A8, 0x2213234F, 0x6F14704E, + 0x04002016, 0xE0247042, 0x406260A9, 0x03200FA6, + 0x29404130, 0x71462391, 0x2F812105, 0x02309004, + 0x66A8B100, 0xA0040ADB, 0x0A1A4082, 0xD90C0120, + 0xE82666A8, 0x6F14702E, 0x04002016, 0xE0247022, + 0x208A60A9, 0x0F6E0006, 0x42300320, 0x23932A40, + 0x2F812305, 0x02249004, 0x09C2B100, 0x740C0120, + 0x0006208A, 0x03200F4E, 0x23054142, 0x90042F81, + 0xB100022C, 0x66A87126, 0xA00409BF, 0x000340C3, + 0x09C2D090, 0x702C0120, 0x03000DC2, 0x78E0C6D0, + 0x1CFCC2FA, 0x2482B6C8, 0x702C3211, 0xFCEF099A, + 0x1207C045, 0xC0443091, 0xC051700C, 0xC04FC050, + 0xC04DC04E, 0xFF2F082E, 0x47CBC04C, 0x12228000, + 0x40108F61, 0x0B338F20, 0x750C0064, 0x70801600, + 0x000C8000, 0x700CB8E3, 0x2100F208, 0x101C0680, + 0x20780080, 0xB8080000, 0x70422614, 0x048C8000, + 0xB2007124, 0xC205F1E9, 0x03F246CB, 0x0D220001, + 0x41C1FD6F, 0xFDEF0FEA, 0x45CBC005, 0x01268000, + 0x264F8D40, 0x0D0A1401, 0x740CFD6F, 0x214A7036, + 0x8D003480, 0x33E121CA, 0xF491B8E0, 0x712EC005, + 0x41C3C204, 0x000103F5, 0x20002900, 0x0CE268D2, + 0x740CFD6F, 0x712CC004, 0xFC6F0EC6, 0x0D9E704C, + 0x0EAEFE0F, 0x0CB2FB4F, 0x0C8A0300, 0x700C0300, + 0xFBAF0FCA, 0x1600712C, 0x80007082, 0x22780008, + 0x68210080, 0x71001600, 0x0510901C, 0x2044C047, + 0x20002040, 0x1E002003, 0x901C7044, 0x0A0F0510, + 0x218A00B0, 0x218A0048, 0xC0050090, 0x1010260F, + 0x2340C808, 0xB802078E, 0x0F822005, 0x04F8901C, + 0x0F802005, 0x04F4901C, 0x714CB220, 0x712CB020, + 0x71001600, 0x0508901C, 0xB887C048, 0x70041E00, + 0x0508901C, 0xFC6F0E3A, 0x0C62C004, 0x4210FB4F, + 0x000040C3, 0x08B2FFFF, 0x41000320, 0x208A7056, + 0xD9FF0FC7, 0x0EA6711C, 0x710C02E0, 0x70801600, + 0x000C8000, 0x00DF080D, 0x74441E00, 0xC2D49007, + 0x1E00D80F, 0x901F7085, 0x1E00C040, 0x90077085, + 0x08B2F880, 0xD90FFCAF, 0x0240093A, 0x0A9278CF, + 0x212F0060, 0x8D000407, 0x00FF0821, 0x1410C092, + 0x0205301B, 0x23400020, 0xD9FD3A9B, 0x0BD2D80A, + 0xB912FD6F, 0x00000425, 0x0BE6702C, 0x228AFAEF, + 0xC3050010, 0x714C740C, 0x03F941C3, 0x1C2C0002, + 0x0BAE3FC1, 0x1C28FD6F, 0x8FA03FC1, 0x1410700E, + 0x2340301B, 0x232F3A9B, 0x238C0408, 0x00A68FDF, + 0xC808000D, 0x20058FC1, 0x689206C0, 0x13640E23, + 0x13802D40, 0xB8927885, 0xB89FB89C, 0xC28AEB85, + 0x7AB49020, 0x1800B220, 0x71A50404, 0x08A6F1F0, + 0xD80F0240, 0xFCAF080E, 0x700CD90F, 0xFBAF0E5E, + 0x8F01712C, 0x085B8FA0, 0x78A20364, 0x6821714C, + 0x2F832004, 0xFFF80000, 0x20802053, 0x7A18BB23, + 0x7040240A, 0x20A843A9, 0x26F40740, 0x800072C0, + 0x6832048C, 0x13802B40, 0x2B407825, 0x20051201, + 0x90040F80, 0x908002DC, 0x6038C092, 0x60797095, + 0x20C58900, 0xF4030082, 0x71657846, 0x7106A900, + 0x700EF1AB, 0x08DD8F01, 0x42A10364, 0x03FA41C3, + 0x0ADE0001, 0x740CFD6F, 0x09B9702E, 0x00002F85, + 0x218B0800, 0x1C0CA803, 0x1C083400, 0xF4123400, + 0x28002156, 0x21822941, 0x0F802004, 0xFFC00000, + 0x41C3B826, 0x000203FB, 0x0AA66869, 0x740CFD6F, + 0x70CCDB08, 0xC48270CD, 0x64DC700C, 0x00892653, + 0x7100244A, 0x200A736D, 0x1C001440, 0x20A81003, + 0x2D4004C0, 0xC2921201, 0x2841623A, 0x710510C1, + 0x29016229, 0x71250241, 0x2900B9C0, 0x776502C1, + 0x26527825, 0x74260086, 0x238D71C5, 0xAC0007FF, + 0x3087140D, 0x3085140B, 0x3086140C, 0x3084140A, + 0x1409C222, 0x140E3083, 0x140F3081, 0xC1403080, + 0x03FC41C3, 0xC0410008, 0xFD6F0A26, 0xF1A7740C, + 0x03FD41C3, 0x0A1A0000, 0x740CFD6F, 0xF19471A5, + 0x08318F20, 0x78220064, 0xC8086861, 0x06C02005, + 0x70C0240A, 0x20A86852, 0xC08A0380, 0x004320F4, + 0x03802940, 0x71247845, 0xB89CB892, 0xB060B89F, + 0x02000F22, 0x03FE41C3, 0x09D60000, 0x740CFD6F, + 0x42D3700C, 0x00009000, 0x202FC046, 0xC0498648, + 0x1600F2F2, 0x80007080, 0x0817000C, 0x700C00FE, + 0xFBAF0CBA, 0xD80F712C, 0xFC6F0E5A, 0x700CD90F, + 0xFBAF0CAA, 0x8FC0712C, 0x76108F01, 0x002D01AA, + 0x2440D80F, 0x27143C17, 0x17002397, 0x70142100, + 0x2614F4C9, 0x80007395, 0x2E40048C, 0x24401301, + 0x15003E11, 0x21052100, 0x00010F98, 0x200500B7, + 0x21050600, 0xB80206C1, 0x23912114, 0x04802005, + 0x2490224F, 0xC8089040, 0x78254350, 0x20841900, + 0x2005B802, 0xC0902010, 0x21141000, 0x03962014, + 0x21001600, 0x0B3FE80E, 0x740C2031, 0x03FF41C3, + 0x42C10002, 0x091A4382, 0x1F00FD6F, 0xF0932045, + 0x20110B23, 0x7014CA07, 0x20CAD812, 0xC10903E1, + 0x00610813, 0x740C702C, 0xFD6F08F6, 0x710CB99A, + 0x2453C046, 0x24AD214D, 0x740C2982, 0x040141C3, + 0x42C10004, 0x44A14382, 0xFD6F08D6, 0x04C0250A, + 0x20812440, 0x20056916, 0xCA070353, 0xD8227014, + 0x072120CA, 0x004508C3, 0x08B3C006, 0x16000010, + 0x80007080, 0x29090008, 0xF2518014, 0x040241C3, + 0x089E0000, 0x740CFD6F, 0xD90FD80F, 0xFC6F0D46, + 0x23441800, 0x02000DCE, 0x41C3740C, 0x00030403, + 0x706C42C1, 0xFD6F087A, 0x160044A1, 0x80007080, + 0x0817000C, 0x700C00FE, 0xFBAF0B72, 0xD80F712C, + 0xFC6F0D12, 0x700CD90F, 0xFBAF0B62, 0x1500712C, + 0x20052100, 0xB8020600, 0x04802005, 0x19009000, + 0xE8132004, 0x21842C40, 0x2405740C, 0x41C30344, + 0x00030404, 0x438242C1, 0xFD6F0826, 0x21041800, + 0x20451F00, 0x740CF017, 0x040541C3, 0x42C10003, + 0x080E706C, 0x44A1FD6F, 0x41C343B1, 0x00000406, + 0xFAEF0D06, 0x1800700C, 0x110024C4, 0x1E002100, + 0x71C52004, 0x0C9EF12A, 0xD90FFC6F, 0x02200D26, + 0xF10D7727, 0x1E00C007, 0x901C7004, 0xC0080510, + 0x70041E00, 0x0508901C, 0xFE4F0816, 0x702CC004, + 0xFC6F09AE, 0x41C3704C, 0x00000407, 0xFD2F0FB2, + 0x0A7E750C, 0xC005FDEF, 0x32112480, 0x341B1404, + 0x78E0C6DA, 0xC1A4C3E8, 0x800046CB, 0x8EA11220, + 0x40D371ED, 0x4E748001, 0x40027014, 0x7FB8D912, + 0x083EF209, 0x400202C0, 0x0D4AD912, 0xDA800060, + 0x09B6F003, 0x0EFA0240, 0xC08002E0, 0x0BDAC080, + 0xD912FDEF, 0x259F8E00, 0x209F12C1, 0x704C0582, + 0x708CC380, 0x6F12651D, 0x250078E5, 0x0A7E1401, + 0x780F04A0, 0x000040C3, 0x0B5A4E20, 0x702C00E0, + 0x78E0C7C8, 0x2482C3F2, 0x44103104, 0x702CC081, + 0xFAAF0F3E, 0x0004228A, 0x800045CB, 0x8D401220, + 0x20502479, 0x22102040, 0xA0432442, 0x41C3750C, + 0x00030150, 0xFD2F0EFA, 0x0400240A, 0x24408DA0, + 0xC8083081, 0x7D05BD0C, 0xFCAF0A82, 0x46084082, + 0x1F802505, 0x00D90003, 0x0E6AD940, 0x43100460, + 0x02200BBE, 0x1402BE68, 0x7FD03102, 0x41E14082, + 0x0BEA41F1, 0x4250FB2F, 0xD955E806, 0x0BBA700C, + 0xB912FAEF, 0x22002840, 0x7D0570CD, 0x800047CB, + 0x25050484, 0x00031F95, 0x7DD000D8, 0x9FC3258C, + 0x40A2F712, 0x04600E1E, 0x0B7641A1, 0x40820200, + 0x0BAA4122, 0x4242FB2F, 0x61B9C181, 0x8F00A900, + 0xF1ED661E, 0x0DFE40A2, 0x702C0460, 0x20802B40, + 0xB89C70AD, 0x0B4AB89F, 0xB0A00220, 0x015741C3, + 0x0E4E0000, 0x740CFD2F, 0x21C22042, 0x41C3740C, + 0x00020158, 0xFD2F0E3A, 0x8F804302, 0x7200244A, + 0x706C704C, 0x030020A8, 0x659EC081, 0x224E60A9, + 0x714401C0, 0x290045C9, 0x7B050000, 0x41C37A6F, + 0x00010159, 0xFD2F0E0A, 0x268C740C, 0x45C99004, + 0xD9ADF6A5, 0x0DFA740C, 0xB911FD2F, 0x700C8F40, + 0x8FC3208C, 0xC181F707, 0x70346109, 0x008120C0, + 0x2080F3F8, 0x7E0E003F, 0x9004268C, 0x41C3F688, + 0x0000015B, 0xFAEF0AD2, 0xF009700C, 0x41C3740C, + 0x0001015C, 0xFD2F0DBA, 0x40C342C1, 0x01258000, + 0x6D2988A0, 0x0114090B, 0x180074AD, 0x740C0103, + 0x015D41C3, 0x0D9A0001, 0x42A1FD2F, 0x740CBD05, + 0x015E41C3, 0x0D8A0001, 0x42A1FD2F, 0x780E4EB0, + 0x78E0C7D2, 0xC1A4C3E2, 0x800145CB, 0x40A14E74, + 0x02A00E2E, 0x40A1D910, 0x0B3AD910, 0xDA410060, + 0xD91040A1, 0xFBEF0942, 0x40A1DAF3, 0x02A00E12, + 0x40A1D929, 0x0932D929, 0xDA1FFBEF, 0x0E0240A1, + 0xD90B02A0, 0xD90B40A1, 0xFBEF091E, 0x40A1DAF0, + 0x02A00DEE, 0x40A1D912, 0x0AFAD912, 0xDA080060, + 0xD91240A1, 0xFBEF0902, 0x0CA6DAF8, 0xC08002E0, + 0x0986C080, 0xD910FDEF, 0x097EC080, 0xD929FDEF, + 0x0976C080, 0xD90BFDEF, 0x096EC080, 0xD912FDEF, + 0x0966C080, 0x732CFDEF, 0x095EC080, 0xD911FDEF, + 0x0956C080, 0xD912FDEF, 0x70801600, 0x01318000, + 0x0071080D, 0x0942C080, 0xD913FDEF, 0x702C40A1, + 0xDBFFC280, 0x04A00C56, 0x40C3708C, 0x4E200000, + 0x00E008D2, 0x40A1702C, 0x02200EEE, 0x40A1D929, + 0x02200EE6, 0x40A1D90B, 0x02200EDE, 0xC7C2D912, + 0xC1A2C3EC, 0x800145CB, 0x41304D64, 0xD8644010, + 0x254070CD, 0xB5001312, 0xC640C641, 0x731478CF, + 0x000D00F0, 0x20100919, 0x00D00829, 0x0050081F, + 0x00900829, 0xD87FE896, 0xF01EB808, 0x00D0082D, + 0x00500831, 0x0090080D, 0xD87FE898, 0xF014B810, + 0x7F0040C3, 0xF0107F7F, 0x7F7F40C3, 0xF00C007F, + 0x700CD989, 0xF00EB911, 0x007F40C3, 0xF0047F7F, + 0xB818D87F, 0xF008C040, 0x41C3700C, 0x00000119, + 0xFACF0916, 0x15001502, 0x0A02B802, 0x7810FBAF, + 0xD907D841, 0xDA08B813, 0x708C706C, 0x0F4E70AC, + 0x70CCFB6F, 0x742C700C, 0xFBAF0A36, 0xC080714C, + 0x098E4102, 0x724CFBAF, 0xD914700C, 0xFBAF0A22, + 0x706C714C, 0x4060D907, 0xB892744C, 0x70AC708C, + 0xFB6F0F1A, 0x160070CC, 0x80007080, 0x0811000C, + 0x700C003E, 0x09FAD914, 0x714CFBAF, 0xD907D880, + 0xDA08B893, 0x708C706C, 0x0EF270AC, 0x70CCFB6F, + 0xFB0F0D56, 0x7704B500, 0x20141A02, 0xF18871C5, + 0x78E0C7CC, 0x4608C2E8, 0x70801600, 0x000C8000, + 0x47284050, 0x8E00204B, 0x40C3F2B7, 0x12208000, + 0x20812078, 0x219F8800, 0x209F02C1, 0x61190582, + 0x0F8F2132, 0x4E868001, 0xFB0F0D26, 0xD907706C, + 0x744C4568, 0x708CBD9A, 0x70AC40A1, 0xFB6F0E8E, + 0x43E170CC, 0x238540A1, 0x762C0201, 0x244A744C, + 0x250A0480, 0x0E760400, 0x70CCFB6F, 0xD90740A1, + 0x706C744C, 0x70AC708C, 0xFB6F0E62, 0x0FC1268A, + 0xFB8F0906, 0x13C0254F, 0x744CD907, 0x708C706C, + 0x0E4A70AC, 0x70CCFB6F, 0xD90740A1, 0x706C744C, + 0x70AC708C, 0xFB6F0E36, 0x03C0264A, 0xD9077EBD, + 0x744C40C1, 0x708C706C, 0x0E2270AC, 0x70CCFB6F, + 0xD90740A1, 0x706C744C, 0x70AC708C, 0xFB6F0E0E, + 0x0FC3268A, 0xD90740C1, 0x706C744C, 0x70AC708C, + 0xFB6F0DFA, 0x40A170CC, 0x744CD907, 0x708C706C, + 0x0DEA70AC, 0x268AFB6F, 0x40C10FC3, 0x744CD907, + 0x708C706C, 0x0DD670AC, 0x70CCFB6F, 0xD90740A1, + 0x706C744C, 0x70AC708C, 0xFB6F0DC2, 0x0FC3268A, + 0x1480254F, 0x744CD907, 0x708C706C, 0x0DAE70AC, + 0x71CCFB6F, 0xFB8F083A, 0xD90740A1, 0x706C744C, + 0x70AC708C, 0xFB6F0D96, 0x40A173CC, 0x744CD907, + 0x708C706C, 0x0D8670AC, 0x268AFB6F, 0x40A10FC1, + 0x744C762C, 0x244A43E1, 0x250A0480, 0x0D6E0400, + 0x70CCFB6F, 0xD90740A1, 0x706C744C, 0x70AC708C, + 0x0FC0264A, 0x0BDAF03F, 0x700CFB0F, 0x744CD907, + 0x708C706C, 0x0D4670AC, 0x70CCFB6F, 0xFB4F0FEA, + 0xD907706C, 0x724C4568, 0x708CBD99, 0x70AC40A1, + 0xFB6F0D2A, 0x700C70CC, 0x42C1D907, 0x708C706C, + 0x0D1A70AC, 0x70CCFB6F, 0xBD2D740C, 0x712CB892, + 0x43A142E1, 0x70AC708C, 0xFB6F0D02, 0x6D1370CC, + 0xDA0CD907, 0x708C706C, 0x0CF270AC, 0x71CCFB6F, + 0xFB4F0F7E, 0xD907700C, 0x706CDA10, 0x70AC708C, + 0x0CDA70CC, 0xD880FB4F, 0x744CD907, 0x708C706C, + 0x0CCA70AC, 0x70CCFB6F, 0x78E0C6C8, 0x4510C2F4, + 0x71001600, 0x0508901C, 0x20534330, 0xF4098196, + 0x03E641C3, 0x094A0000, 0x740CFD2F, 0x265F71CE, + 0x2E4020CF, 0x710C2094, 0x200E241F, 0x93A50FFD, + 0x0B0E7104, 0x740CFB0F, 0x03E741C3, 0x09220001, + 0x42C2FD2F, 0xFB4F0F22, 0x2280265F, 0x704CD907, + 0x708C706C, 0x770470AC, 0x2007212F, 0x0C5E700C, + 0x260AFB6F, 0x6F010440, 0x7B0F702C, 0x0986D807, + 0x704C0020, 0x000045CB, 0x232F12C8, 0xD81D0580, + 0x426241A1, 0x0020096E, 0xD81E4270, 0x426241A1, + 0x00200962, 0xD81F4342, 0x426241A1, 0x00200956, + 0xD8204342, 0x704C41A1, 0x0020094A, 0x78F24342, + 0x661E702C, 0x7BCFD807, 0x093A704C, 0x40700020, + 0xD907700C, 0x706C704C, 0x70AC708C, 0xFB6F0BEE, + 0x0440260A, 0x20402242, 0x262FD907, 0x700C0007, + 0x706C744C, 0x0BD6708C, 0x70ACFB6F, 0x710CDD08, + 0x082A41C2, 0x4262FBAF, 0x41C2700C, 0xFBAF081E, + 0x258C4262, 0x700C1DFF, 0xDA5CD907, 0x708C706C, + 0x70CC70AC, 0xFB6F0BA6, 0x708C71CE, 0x458874CD, + 0xBD8CBE92, 0xD92E40C1, 0x43A142A2, 0x0B8E70AC, + 0x70CCFB6F, 0xD92F40C1, 0x43A142A2, 0x70AC708C, + 0xFB6F0B7A, 0x6D1370CC, 0x744CD907, 0x708C706C, + 0x0B6A70AC, 0x71CCFB6F, 0x0540202F, 0x0C8D2054, + 0x2580241F, 0x08FD46CA, 0x71C68364, 0xD907700C, + 0x706C704C, 0x70AC708C, 0xFB6F0B42, 0x0440260A, + 0x1500261E, 0x704C702C, 0x671F78A2, 0x7B0F6F01, + 0x00200862, 0xDD25D807, 0xBD07D81D, 0x41A14262, + 0x00200852, 0xD81E4342, 0x426241A1, 0x00200846, + 0xD81F4342, 0x426241A1, 0x0020083A, 0xD8204342, + 0x704C41A1, 0x0020082E, 0xD8074342, 0x704C702C, + 0x00200822, 0x700C4302, 0x704CD907, 0x708C706C, + 0x0ADA70AC, 0x260AFB6F, 0x0D660440, 0xC6D4FB4F, + 0x4648C2E8, 0x40104728, 0x6B09EB0F, 0x68A1780F, + 0x4102700C, 0x43E1704C, 0x45C1708C, 0xFB6F0AAE, + 0x258C70CC, 0xC6C81E3F, 0x4050C2E8, 0x47CB4528, + 0x04988000, 0x8703E81B, 0xE8877104, 0x71001600, + 0x025C9004, 0x720CA703, 0x900746CB, 0x0B1EC25C, + 0x1E0000A0, 0x16001005, 0x80007080, 0x2053000C, + 0xF223817E, 0x90051ECC, 0xC808F021, 0x46CB70AD, + 0xC3EC9007, 0x21056832, 0x903B0F80, 0xB0A0C02C, + 0x268079C5, 0xD8141939, 0x0A7EB1A0, 0xB6A000A0, + 0x90451E2C, 0x93441ED8, 0x93441ED4, 0xB6068703, + 0x93441EE0, 0x1ECCC6C8, 0x740C9344, 0x900746CB, + 0x0ABAC224, 0xB6A000A0, 0x10051E08, 0x20300819, + 0x90051E58, 0x20710823, 0x1E00700C, 0x90077285, + 0xF010C254, 0xB802C808, 0x0F802005, 0xC3EC9007, + 0x00451800, 0x41C3F006, 0x0000034D, 0xFA8F0B8A, + 0x74041E00, 0xC2509007, 0xB802C808, 0x0F802005, + 0xC02C903B, 0x00851800, 0x78E0C6C8, 0xC1A2C3F2, + 0xB99FD925, 0x1C068900, 0x891B3002, 0x30021C07, + 0x800040C3, 0x88201224, 0x8822C161, 0x30421C05, + 0x88038821, 0x30421C02, 0xFEAF0896, 0x30021C03, + 0x70ED4110, 0x218121AD, 0x0FA9714E, 0x2A001465, + 0x70CD23D5, 0x0E99C806, 0x24401005, 0x60C83180, + 0xA000250B, 0x2714F242, 0x700E1380, 0x20142A00, + 0x30802440, 0x03932032, 0x60CDC081, 0x0B6D78AF, + 0x78CF2024, 0xFF6F0EF2, 0x6E3479EF, 0x800042C3, + 0xE81311DE, 0x20402040, 0x03C32116, 0x6D817910, + 0x61596179, 0x03021920, 0x0408212F, 0x61596179, + 0x03421920, 0x232FF016, 0x79F60408, 0x16006179, + 0x80007080, 0x240B0121, 0x6D01A000, 0xF2066159, + 0x00021920, 0xF005A9A0, 0x1920A900, 0x40020342, + 0x204072A5, 0xF1CC0050, 0xF1B671C5, 0xF1AF71E5, + 0x78E0C7D2, 0xDB24C2E6, 0x800042C3, 0xBB9F1224, + 0x00031A00, 0xE0078B00, 0x00C12841, 0x69898B1C, + 0xE80FAA81, 0x791DC805, 0x70801600, 0x003F8000, + 0xB9C6E007, 0xAA22B823, 0x68C96038, 0x4689F003, + 0x12B5AA22, 0x788F008D, 0xAAC37104, 0x7000240A, + 0x20A8770C, 0x71040180, 0x100D250F, 0x42C378CF, + 0x12D98000, 0x0064081B, 0x7822AAA0, 0x240A7104, + 0x20A87000, 0x250F0180, 0x7124104D, 0x70ADAAA0, + 0x800044CB, 0x0D4311DA, 0x408910B5, 0x706D70CD, + 0x0B3179AF, 0x70751095, 0x20CA4060, 0x80000F82, + 0x88E0003F, 0xFF6F0DE2, 0xE80578CF, 0xB8236F07, + 0x4F1FF003, 0x1802B824, 0x71C51012, 0xF1EB7165, + 0x71A57185, 0xC6C6F1E1, 0x0A22C0F1, 0xC0D10100, + 0x700C7FE0, 0xE9058840, 0x001F0A0B, 0xBAE07EE0, + 0x88217DE0, 0xF78AE1C0, 0x20E07354, 0x218007CD, + 0xA821003F, 0xF0086A21, 0x7CE07054, 0x08012154, + 0x6A29A821, 0xA8207FE0, 0x0443216F, 0x11FE8940, + 0x229F8101, 0x790C041F, 0x00802905, 0x71047FE0, + 0x2482C3F4, 0x16003302, 0x80007080, 0xB8C30004, + 0x800047CB, 0x205F1220, 0x41C30B16, 0x0000013F, + 0x2700702E, 0x18081580, 0x0C360001, 0xD80AFCEF, + 0xFF8F0EB6, 0x800042D3, 0x202F1138, 0x24400448, + 0x24403181, 0x08823142, 0x2440FEAF, 0x701431C3, + 0x1407F4E3, 0x0F763080, 0x1A00FD6F, 0x14052043, + 0x712C3080, 0xFDAF0966, 0x70AD4310, 0x712C4062, + 0x0F62704C, 0x1A00FFAF, 0x14062342, 0xC1823080, + 0x716C724C, 0x0A0A708C, 0x4010FAAF, 0x702CC083, + 0xFA6F0BEE, 0x258ADA80, 0x708E2002, 0x8F2070CD, + 0x0507222F, 0x0CD64062, 0xC540FF6F, 0xC1804002, + 0x716C724C, 0xFAAF09DA, 0x1401708C, 0x20533080, + 0xF20681BE, 0x60D8C083, 0x00431800, 0x258D7186, + 0x71C52A7F, 0x740C8F60, 0x014141C3, 0x0B820002, + 0x4202FCEF, 0xDE8070AD, 0x41C3C083, 0x00010142, + 0x0B6E60AA, 0x740CFCEF, 0x1E3F268D, 0x41C371A5, + 0x00000143, 0xFCEF0B5A, 0x248A740C, 0x77AD7002, + 0x776D700C, 0x20A8776C, 0xC1830740, 0x610977B5, + 0xE0FFF207, 0xE914F202, 0x6829E906, 0xE98FF005, + 0xF00E4508, 0x2302D97F, 0x49B210CC, 0x25CA7291, + 0x21CA10CC, 0x43A102CC, 0x77AD4328, 0x77747104, + 0x77B5F404, 0xF404DE7F, 0x46694568, 0x41A18F60, + 0x21B94EB0, 0x207F0FFF, 0x78240100, 0x014541C3, + 0x0FF60002, 0x4202FA6F, 0x41C366B8, 0x00030146, + 0x00942844, 0x42A1740C, 0x0AD643C1, 0x240AFCEF, + 0x8F200500, 0x843E2105, 0x26144620, 0x70022040, + 0x180860F8, 0xF20B0502, 0x2011081D, 0x00510E19, + 0x75021E00, 0x004E8000, 0x1E00F013, 0x80007502, + 0xF00F0033, 0x20510813, 0x00110E0F, 0x75021E00, + 0x00348000, 0x1E00F005, 0x80007502, 0x242F004F, + 0x250A0507, 0x245F0400, 0x20540140, 0x78300C81, + 0x02822845, 0x209E4040, 0x60380DBF, 0x014741C3, + 0x7B100005, 0xFCEF0A5A, 0x4062750C, 0x0946702C, + 0x1A00FDEF, 0x71262043, 0x0448202F, 0x061E7414, + 0x40C3FFC5, 0x12D88000, 0x00431800, 0x78E0C7D4, + 0x88606038, 0xA8607B45, 0x0083104B, 0x184B7B45, + 0x109600C2, 0x7B450083, 0x00C21896, 0x008310E1, + 0x7FE07A65, 0x008218E1, 0x2482C3EA, 0x266F3206, + 0xC0801243, 0xFF2F0812, 0x10901600, 0x800140C3, + 0x88404E77, 0x7A058813, 0x30811403, 0x30801416, + 0x78477825, 0x01BE080B, 0x0C2E700C, 0x256F03C0, + 0x150016C3, 0x081110C0, 0xC0800032, 0x0DAAD913, + 0xDAF3FB6F, 0x3BC02456, 0xFD6F0D16, 0x20D02053, + 0x3BC02456, 0x02A00946, 0xC080D90B, 0xDA45D910, + 0xFFEF0F72, 0x30112440, 0x3BC02456, 0x02A0092E, + 0x2456D946, 0x09263BC0, 0xD94702A0, 0x3BC02456, + 0x02A0091A, 0x2456D948, 0x09123BC0, 0xD94902A0, + 0x3BC02456, 0x02A00906, 0xCA0ED94A, 0x47CB704C, + 0x12208000, 0x00050A31, 0x2B01205F, 0x0F832232, + 0x04788000, 0x79557322, 0x673F7144, 0xAB208F28, + 0x1B968F2A, 0x8F290042, 0x00421B4B, 0x1BE18F2B, + 0xF1E70042, 0x3BC22456, 0x712CC080, 0x08BEDBFF, + 0x708C0460, 0xD910C080, 0xFB6F0CFE, 0x8D00DABC, + 0x005E0815, 0x08118E00, 0xC080017F, 0x0ED6D910, + 0xDA40FFEF, 0x02A0088A, 0x3BC02456, 0x3BC02456, + 0xFD6F0D66, 0xC027D910, 0x017F0819, 0xD91CC080, + 0xFFEF0EB2, 0x2456724C, 0x0D4E3BC0, 0xD91CFD6F, + 0x3BC22456, 0x702CC080, 0x0862DBFF, 0x708C0460, + 0x080F8D00, 0x8E00005E, 0x0ADCB8E5, 0x08A2FEC1, + 0x0A8EFCCF, 0x8D00FACF, 0xF29EB8E1, 0xB8E58E00, + 0x096AF49A, 0x0882FD8F, 0xD8100280, 0x0FC2D940, + 0xDA0FFB2F, 0x762C700C, 0xFB2F0ED6, 0x8F20714C, + 0x0582219F, 0x100017BC, 0x88216038, 0x00DF090D, + 0x20538814, 0xF23580FE, 0x2400702C, 0x00003F80, + 0x087E012C, 0xDA4BFA6F, 0x3A002456, 0x02A00816, + 0x00831800, 0x0B56700C, 0x712CFB2F, 0xFACF0A22, + 0x02800826, 0x752C700C, 0xFB2F0E86, 0x40C3714C, + 0x3A980000, 0x00600C4E, 0x0D0A742C, 0x710C0120, + 0x3F802400, 0x012C0000, 0x02800966, 0x000340C3, + 0x0C320D40, 0xD9080060, 0x01200D5A, 0xD810710C, + 0x0F2E702C, 0xDA0FFB2F, 0x762C700C, 0xFB2F0E42, + 0x700C714C, 0x704CD932, 0x708C706C, 0x0B3E73AC, + 0x70CCFB2F, 0xD933700C, 0x706CDA20, 0x73AC708C, + 0xFB2F0B2A, 0x700C70CC, 0x0E16762C, 0x714CFB2F, + 0xD938D811, 0xFB2F0EEA, 0x700CDA0F, 0x0E02D907, + 0x714CFB2F, 0xD930700C, 0x706C704C, 0x73AC708C, + 0xFB2F0AFA, 0x700C70CC, 0x704CD931, 0x708C706C, + 0x0AEA73AC, 0x70CCFB2F, 0x762C700C, 0xFB2F0DD2, + 0x0F42714C, 0x700C0240, 0xFB2F0A82, 0x0FC2712C, + 0xF027FD8F, 0xDA20D825, 0x706CB89F, 0x70CC708C, + 0x881B8820, 0xD90B7825, 0x00452053, 0xFB2F0AAE, + 0x700C700C, 0x724CD928, 0x708C706C, 0x0A9E73AC, + 0x70CCFB2F, 0xD907700C, 0x706CDA1E, 0x70AC708C, + 0xFB2F0A8A, 0x700C70CC, 0xFB2F0A32, 0x702C712C, + 0x70441E00, 0xC200901F, 0x70801600, 0x00968000, + 0x011E0815, 0xB802C808, 0x0F802005, 0xC0049007, + 0x00451800, 0x900840C3, 0xB02001B8, 0x1CC3266F, + 0x8E00B036, 0xF01AE89E, 0x1600E908, 0x80007080, + 0xE88B0040, 0xF011710C, 0x70801600, 0x00258000, + 0x700C7014, 0x710CF209, 0x0A327838, 0x780FFD6F, + 0xFB8F0986, 0x68218F00, 0x792FAF20, 0x809409CD, + 0xFD6F0A1A, 0x70AD730C, 0x8E20B7A0, 0x0C82E984, + 0x8E200240, 0x900740C3, 0xB0A0C2CC, 0xE989B0A2, + 0x71001600, 0x00108000, 0x09F07114, 0x0F820242, + 0x08DAFF0F, 0xC7CAFD8F, 0x78E07EE0, 0x7FE0700C, + 0x00C420AB, 0x1CFCC2FA, 0xC1A2B6C8, 0xC8084608, + 0x006E41C3, 0xB8020002, 0x0F802005, 0x200C900C, + 0x78BD90A0, 0x70901600, 0x00048000, 0x004F2044, + 0x10432544, 0x42E1D80A, 0xFCAF0E36, 0x20534078, + 0xC04020C0, 0xC200EF8A, 0x006F41C3, 0x0E220001, + 0xD80AFCAF, 0x000003E5, 0xB802C808, 0x0F802005, + 0x140C9000, 0x30310821, 0x01131000, 0x10C02D41, + 0x1AC125AD, 0x0F832084, 0x60B8742C, 0x0380205A, + 0xF004E038, 0x732CD870, 0x6038710E, 0x1E007017, + 0x90037404, 0x1E00D878, 0x90077404, 0x02F4F87C, + 0xC0410022, 0x02EC70D5, 0x710C0021, 0x01000AA6, + 0x45CBC808, 0xC400900F, 0x14CE2550, 0xB802726D, + 0x03412005, 0x190078C5, 0x180002C4, 0x099E02C4, + 0xD81E0060, 0x36091208, 0x702E700D, 0x70CC71EC, + 0x00100F11, 0x70801600, 0x00258000, 0xF053E888, + 0x70801600, 0x00408000, 0x001008A7, 0x00052752, + 0x3000264A, 0x33002E40, 0x70C0704C, 0x200572EF, + 0x0E090244, 0xEAB830D1, 0x31310E17, 0x8080270B, + 0x1600F207, 0x80007081, 0x095D0025, 0x0E1B0050, + 0x220B3131, 0xF2098140, 0x70811600, 0x00408000, + 0x0051090F, 0x2678F020, 0x794B3141, 0x215AF41C, + 0x41C32503, 0x12E08000, 0x71266A94, 0x43C36179, + 0x0FF10000, 0x43C3B166, 0x05248000, 0x1908639A, + 0x82E30003, 0x22058241, 0xA1E40102, 0x6462A141, + 0xA1407A05, 0x31FF278D, 0x2640714C, 0x0E79305E, + 0x46C3B194, 0x70000000, 0x193E238D, 0x40C370EC, + 0x12D98000, 0x00841000, 0x43C371CC, 0x05448000, + 0x022E0C6B, 0x72AC700C, 0x00072E00, 0x02002014, + 0x244AB80C, 0x20057180, 0x4308025F, 0x3000264A, + 0x088020A8, 0x310C2E40, 0x89086399, 0x8000270B, + 0x215AF218, 0x40C32502, 0x12E08000, 0x60587126, + 0x000042C3, 0xB0460FF1, 0x81218143, 0x07C12105, + 0x01821808, 0x6461A021, 0x02C12105, 0xA020A044, + 0x305E2640, 0x04BF258D, 0x7105710C, 0x91140895, + 0x41C34022, 0x00010069, 0x024120BC, 0xFA6F094A, + 0x21424222, 0x42D3A03C, 0x12E48000, 0x2344F20B, + 0x22402042, 0xD9F12140, 0x014020A8, 0x1814A822, + 0x706D0092, 0x79EDDFF1, 0xFE2F0862, 0x71654022, + 0x14310B11, 0x702C4022, 0x01A00A56, 0x706DDA10, + 0x7F0D6F01, 0x94120FE3, 0x702C4022, 0x01A00A42, + 0x21424261, 0xF20DA03C, 0x2006710C, 0x224004C1, + 0x20A82140, 0x180201C0, 0x181403C3, 0x706D0052, + 0x4022DF0F, 0xFE2F0816, 0x716541E1, 0x14310B11, + 0x712C4022, 0x01A00A0A, 0x706DDA10, 0x7F0D6F09, + 0x9C3F278C, 0x4022F62F, 0x09F6712C, 0x426101A0, + 0x2030098F, 0x230A708E, 0x702F3440, 0x350F215A, + 0x23D32200, 0x20D51308, 0x23F10D1F, 0x20D61309, + 0x14822730, 0xDB0F740C, 0x006441C3, 0x0B720003, + 0x240AFCAF, 0x268C0580, 0xF40DAC7F, 0x14822730, + 0x43A2740C, 0x006541C3, 0x0B560003, 0x248AFCAF, + 0x26000C7F, 0x27302540, 0x28441482, 0x13040097, + 0x252F2080, 0xE80705C5, 0x41C3740C, 0x00040066, + 0x740CF005, 0x006741C3, 0x43A20004, 0xFCAF0B22, + 0x0580240A, 0x238D7127, 0x1B06313F, 0x402225C2, + 0x04200BE2, 0xC808702C, 0x2005B802, 0x78C50341, + 0x05041900, 0x05041800, 0x0120084A, 0xC808710C, + 0x7D05B802, 0x1D007E05, 0x1E001045, 0xF0061045, + 0x74041E00, 0xC02C9003, 0x0260083E, 0x4008710C, + 0x00200ECA, 0x45CBD80D, 0xE008900F, 0x255070CD, + 0xB5C014CB, 0x13841B00, 0x00200E4E, 0x1D00C001, + 0x08231404, 0x1B003031, 0xC8081404, 0x40C36832, + 0xC400900F, 0x00022105, 0x7825B8B3, 0xB0C0B2C0, + 0x40C3F00C, 0xC02C9003, 0xB8AFB0C0, 0x70451E00, + 0x802C9001, 0x00451800, 0x1E0070CD, 0x90037384, + 0x1E00D878, 0x90077384, 0x0FCEF87C, 0x40010220, + 0x45CBD820, 0x03E09008, 0x00200DEE, 0x10451D00, + 0x0DE6D820, 0xB5C00020, 0xD80AC200, 0x007041C3, + 0x0A3E0002, 0x4303FCAF, 0x1404C0A2, 0xC6DA341B, + 0x1CFCC2F8, 0x2482B6C8, 0x44303902, 0xB910D9AB, + 0x30001C84, 0x4670740C, 0xFCAF0A16, 0xD9204550, + 0x89A0B99F, 0x11002553, 0x8961A900, 0x01002353, + 0xA9017BA5, 0x813E2353, 0x808C11F7, 0x11002453, + 0x800219F7, 0x808211F8, 0x01002253, 0x800219F8, + 0x1901F405, 0x19000043, 0x7A850043, 0x813E2253, + 0x19F8F405, 0x19F78043, 0x0E1D8043, 0x740C2030, + 0x20710E23, 0x09BAD92B, 0xB912FCAF, 0x712E700F, + 0xF01070EE, 0x09AAD9AD, 0xB910FCAF, 0x710F70EE, + 0xD957F007, 0xFCAF099A, 0x71EEB911, 0x722E700F, + 0xBD9FDDEE, 0x15328DC0, 0x70D5109B, 0x0ECA40D1, + 0x23CA03A0, 0x1C8C3022, 0xE8123000, 0x740CD9AF, + 0xFCAF096E, 0xD825B910, 0x8840B89F, 0x00412244, + 0xA8204250, 0x274488FB, 0xA83B1041, 0x740CD90B, + 0xFCAF094E, 0x8D00B914, 0x120C4182, 0x20793085, + 0x14840006, 0x42A23000, 0x0D8A43C2, 0x240AFBEF, + 0x160006C0, 0x80007080, 0x081B000B, 0xD9B1003E, + 0x091E740C, 0xB910FCAF, 0x41A240E2, 0xFDAF0C7A, + 0x20054203, 0x148C35C0, 0x1C883001, 0x78253000, + 0x0051085F, 0xE8AD8D00, 0x740CD959, 0xFCAF08F2, + 0x2479B911, 0x40E22003, 0x42A2702C, 0x0440240A, + 0x01200EBE, 0x46084370, 0x40E2E88A, 0x42A2712C, + 0x0EAE4362, 0x240A0120, 0x46080440, 0x740CD9B3, + 0xFCAF08BE, 0x40E2B910, 0x0C1E41A2, 0x4203FDAF, + 0xFE2F0DE6, 0x709640C1, 0xFB2209A4, 0x0F1740A2, + 0x740C2030, 0x089AD92D, 0xB912FCAF, 0x04800AE6, + 0xD9B5F057, 0xFCAF088A, 0x120CB910, 0x24793081, + 0x20782003, 0x40032004, 0x04A00806, 0xCA0C42A2, + 0x060A212F, 0x00002078, 0x084D7825, 0xD840003F, + 0xB89F700E, 0x88C0722E, 0x808010E5, 0x0E237E05, + 0x4002142E, 0x70931600, 0x00048000, 0xFBEF0C5A, + 0x4200712C, 0x4162700C, 0xFCEF0B62, 0x218D4302, + 0x710E2C7F, 0x740CD95B, 0xFCAF0826, 0x09DEB911, + 0x40A2FB2F, 0x0343206F, 0x10C29020, 0x09330700, + 0x0C2F0004, 0x16002011, 0x80007100, 0x09230188, + 0x0E9E0005, 0x2005FC8F, 0x08170600, 0xD9B70071, + 0x0FEE740C, 0xB910FC6F, 0xFB2F0ABE, 0x8D0040A2, + 0xF47C7114, 0x7014CA06, 0x700CF278, 0x20300C15, + 0x30001C90, 0xFC8F0E6A, 0x710CE804, 0x30001C90, + 0x708E1600, 0x12228000, 0x16007DCF, 0x80007080, + 0x08C51223, 0x40C30344, 0x12D98000, 0x08B58800, + 0x40A2036E, 0x0260092E, 0x702E41A1, 0x30001CA0, + 0x300014A0, 0x046E0897, 0x706E720C, 0x30001C94, + 0xB89FD825, 0x881B8820, 0x710C7905, 0x04C02800, + 0x200FB802, 0x782B04C0, 0x1490F231, 0x40C33010, + 0x28F00000, 0x231F791B, 0x201F2002, 0xB8222041, + 0x436278AA, 0x6219623A, 0x209A4022, 0x704C0184, + 0x41E26038, 0x800070C3, 0x1C981A3C, 0x24793000, + 0x1C9C2000, 0x14983000, 0x0B623000, 0x149C0460, + 0x14983004, 0x41E23000, 0x3004149C, 0x0B4E714C, + 0x43620460, 0x710E7016, 0x1494F3D3, 0x716E3000, + 0x08817704, 0x1C948031, 0x71263000, 0xA2940965, + 0xF19C71C5, 0x0100099A, 0x3000148C, 0x026E7014, + 0x0C0A0001, 0x24790380, 0x1C05200E, 0x40633002, + 0x42C141E2, 0xFE2F0A3A, 0xD917C380, 0x0EC2740C, + 0xB913FC6F, 0x30001488, 0x256FE81A, 0x700C1243, + 0x10901500, 0xFBEF0AC2, 0x4200712C, 0x4102700C, + 0xFCEF09CA, 0x8DA0706C, 0x0AAE710C, 0x712CFBEF, + 0x700C4200, 0x09B641A1, 0x716CFCEF, 0x2744DD40, + 0xBD9F1080, 0xAD0070F6, 0x20802244, 0x90021DE5, + 0x09DAF27E, 0x710CFD2F, 0x800046CB, 0x8E221B3C, + 0x140C714C, 0x782A3100, 0x61199620, 0x0EB6710C, + 0x21ADFA6F, 0x40C30883, 0x25788000, 0x140C8842, + 0x7A2A3101, 0x710C9020, 0x724C6159, 0xFA6F0E96, + 0x088321AD, 0xFD2F0996, 0x40C3720C, 0x2FB48000, + 0x140C8842, 0x7A2A3101, 0x710C9020, 0x714C6159, + 0xFA6F0E72, 0x088321AD, 0x800040C3, 0x884239F0, + 0x3101140C, 0x90207A2A, 0x6159710C, 0x0E56724C, + 0x21ADFA6F, 0x09560883, 0x730CFD2F, 0x3085120C, + 0x14844182, 0x42A23000, 0x708C43C2, 0xFBEF0A26, + 0xD9B971CC, 0xB910740C, 0x0DC6ADE0, 0x1DE5FC6F, + 0x40C39482, 0x12228000, 0x008810B7, 0x88608841, + 0x01007350, 0x0835000D, 0x244A10EE, 0x700C7280, + 0x050020A8, 0x209A68A1, 0x231A0184, 0x00000F81, + 0x60380A3C, 0x800041C3, 0x603C442C, 0x60D860D1, + 0x8802B420, 0x40A1AC02, 0xF1E47164, 0x3085120C, + 0x14844182, 0x42A23000, 0x708C43C2, 0x09B671CC, + 0x700EFBEF, 0x740CD95D, 0xADE0B911, 0xFC6F0D52, + 0x94821DE5, 0x3081120C, 0x42A24003, 0x0CD243C1, + 0x708C0460, 0x212FCA0C, 0x2078060A, 0x78250000, + 0x001F0845, 0x15E58DE0, 0x72AD9080, 0x0F237F05, + 0x4002142E, 0x708E1600, 0x00048000, 0xFBEF092A, + 0x4200712C, 0x41C1700C, 0xFCEF0832, 0x258D4302, + 0x710E1C7F, 0x740CD9BB, 0xFC6F0CF6, 0x0EAEB910, + 0x40A2FAEF, 0x0343206F, 0x10C29020, 0x09390700, + 0x0C350004, 0x16002011, 0x80007100, 0x09290188, + 0x0B6E0005, 0x2005FC8F, 0x081D0600, 0xD92F0071, + 0x0CBE740C, 0xB912FC6F, 0xFAEF0F8E, 0xF00440A2, + 0x04400F02, 0x30001488, 0x256FE819, 0x700C1243, + 0x08B68DC0, 0x712CFBEF, 0x710C4200, 0x0FBE41C1, + 0x706CFCAF, 0x710C8DA0, 0xFBEF089E, 0x4200712C, + 0x41A1710C, 0xFCAF0FA6, 0x2480716C, 0x14043902, + 0xC6D8341B, 0x68614200, 0x7054CA08, 0x20AA7B19, + 0x081700C4, 0x23CA003F, 0x720C0021, 0x00C420AB, + 0x20AB710C, 0x0B1100C4, 0x16000415, 0x901C7100, + 0xF01B0490, 0x010420AA, 0x0A1B7A12, 0x24AA00E5, + 0x21AA1144, 0x08FF0104, 0x4B508044, 0x114424AA, + 0x6078F002, 0x010421AA, 0x20E17110, 0x22AA07C6, + 0x0CF50144, 0x7EE09080, 0x0443226F, 0x8A004300, + 0x0A0F239A, 0x00802079, 0x12FE6822, 0x78398100, + 0x70002E05, 0x4240000F, 0xFFEF077D, 0x00002B05, + 0x0826C0F1, 0x0F720000, 0xC0D1FFCF, 0x78E07EE0, + 0x4328C0F1, 0x00200812, 0x7071702C, 0x7FE0C0D1, + 0x02C520CA, 0x0343226F, 0x000370D3, 0x92600D41, + 0x0F8628C5, 0x86A00001, 0x00C620DA, 0x052628C5, + 0x00C520DA, 0x0F8528C5, 0x8480001E, 0x69818A62, + 0x71046078, 0x00C02805, 0x800043C3, 0x8B601138, + 0x12FBEB0D, 0x0A178082, 0x43C300DF, 0x121E8000, + 0xEA058B40, 0x8B817A2C, 0x74107C4C, 0x20CA7FE0, + 0x78E0030D, 0x0DBAC2EE, 0x2053FDCF, 0x206D00C1, + 0x50160900, 0x43D3782A, 0x003F8000, 0x13005015, + 0x13012080, 0xE9112081, 0x029741C3, 0x083A0000, + 0x2079FA2F, 0xCA140000, 0x20811300, 0x206CB802, + 0x61190080, 0xD953F011, 0x00002078, 0xFA2F081A, + 0x1600B913, 0x80007081, 0xC8060024, 0x0091080B, + 0x781DC805, 0x7A2F5015, 0x807E2153, 0x00832A41, + 0x23C0BA23, 0x21530062, 0x1A028080, 0x22C03002, + 0xD80A0062, 0x029941C3, 0x1A010002, 0x0AD230C2, + 0x1A00FC6F, 0x226F3082, 0x41C320C3, 0x0006029B, + 0x20801200, 0xD87FB8E2, 0x01E220CA, 0x30021A03, + 0x1205D80A, 0x12002486, 0x120C2107, 0x120A2085, + 0x13012104, 0x0A9A2083, 0x121FFC6F, 0x121F2082, + 0xB8E02080, 0xDE66F2AB, 0x02A447CB, 0xBE9F0005, + 0x41E1D80A, 0x948616FC, 0x948516FC, 0x10841600, + 0x908316FC, 0x908216A6, 0xFC6F0A66, 0x2640BAC3, + 0x8E6C160D, 0x10861500, 0x1401274F, 0x908515FC, + 0x15F8D80A, 0x16A69084, 0x0A469082, 0xBAC3FC6F, + 0x14102540, 0x10008D64, 0x274F2086, 0x10FC144D, + 0xD80AA085, 0xA08410F8, 0x16A641A1, 0x0A229082, + 0xBAC3FC6F, 0x240F2040, 0x20831004, 0x14861710, + 0x1401254F, 0x908517EC, 0x17E8D80A, 0x16A69084, + 0x09FE9082, 0xBAC3FC6F, 0x948617FC, 0x1700D80A, + 0x41C31085, 0x000502A8, 0x908417FC, 0x17F84030, + 0x16A69083, 0x09DA9082, 0xBAC3FC6F, 0x150D2740, + 0x15008F68, 0x204F1086, 0x15FC2401, 0xD80A9085, + 0x908415F8, 0x908216A6, 0xFC6F09B6, 0x2540BAC3, + 0x8D64140F, 0x10861700, 0x2441204F, 0x908517FC, + 0x17F8D80A, 0x16A69084, 0x09969082, 0xBAC3FC6F, + 0x120D2740, 0x15008F64, 0xD80A1084, 0x908216A6, + 0x02AB41C3, 0x097A0003, 0xBAC3FC6F, 0x10861510, + 0x2481204F, 0x1085150C, 0x1508D80A, 0x8D641084, + 0x908216A6, 0xFC6F095A, 0x151CBAC3, 0xD80A1085, + 0x10841518, 0x02AD41C3, 0x8D740004, 0x908216A6, + 0xFC6F093E, 0x121FBAC3, 0xB8E12080, 0xDE67F2A8, + 0x02AE45CB, 0xBE9F0005, 0x41A1D80A, 0x948616FC, + 0x948516FC, 0x14841618, 0x908316E4, 0x9082168D, + 0xFC6F090E, 0x16FCBAC3, 0x254F9486, 0x16001401, + 0xD80A1085, 0x908416FC, 0x908316F8, 0x90821691, + 0xFC6F08EE, 0x2640BAC3, 0x8E68150D, 0x10861500, + 0x15FCD80A, 0x41C39085, 0x000502B0, 0x908415F8, + 0x16914030, 0x08CA9082, 0xBAC3FC6F, 0x140F2540, + 0x17008D64, 0x204F1086, 0x17FC2401, 0xD80A9085, + 0x908417F8, 0x90821691, 0xFC6F08A6, 0x2740BAC3, + 0x8F64140D, 0x10861500, 0x2441204F, 0x908515FC, + 0x15F8D80A, 0x41309084, 0x90821691, 0xFC6F0882, + 0x2540BAC3, 0x8D64140F, 0x10861700, 0x2401214F, + 0x908517FC, 0x17F8D80A, 0x16919084, 0x08629082, + 0xBAC3FC6F, 0x140D2740, 0x15088F64, 0x204F1486, + 0x15F4248F, 0xD80A9085, 0x908415F0, 0x169141E1, + 0x083E9082, 0xBAC3FC6F, 0x10841500, 0x15FCD80A, + 0x41C39083, 0x000302B5, 0x90821691, 0xFC6F0822, + 0x1510BAC3, 0x274F1086, 0x150C1441, 0xD80A1085, + 0x10841508, 0x16918D64, 0x08069082, 0xBAC3FC6F, + 0x1085151C, 0x1518D80A, 0x41C31084, 0x000402B7, + 0x16918D74, 0x0FEA9082, 0xBAC3FC2F, 0x20801301, + 0xF2ABB8E0, 0xD80ADE68, 0x41C3BE9F, 0x000502B8, + 0x16FC4030, 0x16FC9486, 0x16009485, 0x16FC1084, + 0x16A49083, 0x0FBA9082, 0xBAC3FC2F, 0x160F2640, + 0x17008E6C, 0x204F1086, 0x17FC2401, 0xD80A9085, + 0x908417F8, 0x908216A4, 0xFC2F0F96, 0x2740BAC3, + 0x8F64140D, 0x10861500, 0x2441204F, 0x908515FC, + 0x15F8D80A, 0x41309084, 0x908216A4, 0xFC2F0F72, + 0x2540BAC3, 0x8D64140F, 0x14861710, 0x2401214F, + 0x908517EC, 0x17E8D80A, 0x16A49084, 0x0F529082, + 0xBAC3FC2F, 0x948617FC, 0x2481204F, 0x10851700, + 0x17FCD80A, 0x40309084, 0x908317F8, 0x908216A4, + 0xFC2F0F2E, 0x2740BAC3, 0x8F68150D, 0x10861500, + 0x2401204F, 0x908515FC, 0x15F8D80A, 0x16A49084, + 0x0F0E9082, 0xBAC3FC2F, 0x140F2540, 0x17008D64, + 0x204F1086, 0x17FC2441, 0xD80A9085, 0x908417F8, + 0x908216A4, 0xFC2F0EEA, 0x2740BAC3, 0x8F64120D, + 0x10841500, 0x16A4D80A, 0x41C39082, 0x000302BF, + 0xFC2F0ECE, 0x1510BAC3, 0xD80A1086, 0x1085150C, + 0x02C041C3, 0x15080005, 0x8D641084, 0x908216A4, + 0xFC2F0EAE, 0x151CBAC3, 0xD80A1085, 0x10841518, + 0x02C141C3, 0x8D740004, 0x908216A4, 0xFC2F0E92, + 0x1301BAC3, 0xB8E12080, 0xDE69F2AA, 0x02C245CB, + 0xBE9F0005, 0x41A1D80A, 0x948616FC, 0x948516FC, + 0x14841618, 0x908316E4, 0x9082168B, 0xFC2F0E62, + 0x16FCBAC3, 0x254F9486, 0x16001401, 0xD80A1085, + 0x908416FC, 0x908316F8, 0x9082168F, 0xFC2F0E42, + 0x2640BAC3, 0x8E68150D, 0x10861500, 0x02C447CB, + 0x15FC0005, 0xD80A9085, 0x908415F8, 0x168F41E1, + 0x0E1E9082, 0xBAC3FC2F, 0x14102540, 0x10008D64, + 0x274F2086, 0x10FC1401, 0xD80AA085, 0xA08410F8, + 0x9082168F, 0xFC2F0DFA, 0x2040BAC3, 0x10042411, + 0x11002083, 0xBF912086, 0xA08511FC, 0x11F8D80A, + 0x41E1A084, 0x9082168F, 0xFC2F0DD6, 0x2140BAC3, + 0x1104240D, 0x15002083, 0x274F1086, 0x15FC1401, + 0xD80A9085, 0x908415F8, 0x9082168F, 0xFC2F0DB2, + 0x2540BAC3, 0x8D64140F, 0x14861708, 0x02C845CB, + 0x17F40005, 0xD80A9085, 0x908417F0, 0x168F41A1, + 0x0D8E9082, 0xBAC3FC2F, 0x10841700, 0x17FCD80A, + 0x41C39083, 0x000302C9, 0x9082168F, 0xFC2F0D72, + 0x1710BAC3, 0x254F1086, 0x170C1441, 0xD80A1085, + 0x10841708, 0x168F8F64, 0x0D569082, 0xBAC3FC2F, + 0x1085171C, 0x1718D80A, 0x41C31084, 0x000402CB, + 0x168F8F74, 0x0D3A9082, 0xBAC3FC2F, 0x71001600, + 0x02009030, 0xB82271ED, 0x10002706, 0x30021A08, + 0x21001200, 0x0F85082B, 0x0A6B0000, 0x244AC808, + 0x68527200, 0x20A8700C, 0x22050340, 0x70C30001, + 0x40000000, 0x0F812105, 0x004C9038, 0x0BAAB1E0, + 0x46CBFE0F, 0xC1DC901F, 0x1443256F, 0x73C41E00, + 0x04A0901C, 0x73C41E00, 0xC294900B, 0x10051E00, + 0x41C3740C, 0x000102CE, 0xFC2F0CC6, 0x0BD68D40, + 0x8D00FAAF, 0x02CF41C3, 0x0CB60000, 0x750CFC2F, + 0x120AB6F2, 0x08152100, 0x16000050, 0x80007080, + 0xB8E40004, 0x010109F4, 0x70801600, 0x01148000, + 0x0CEC7014, 0x16000182, 0x80007080, 0x205300F4, + 0xF20B80FE, 0x813E206C, 0x208CF207, 0xF7068FC2, + 0x1A20B825, 0xC6CE301C, 0x301D1A20, 0x78E0C6CE, + 0x0E3EC2E2, 0x40C3FA0F, 0x0BB80000, 0xFFEF0886, + 0x252F702C, 0xF20D9007, 0xD907700C, 0x706C704C, + 0x73AC708C, 0xFA6F0F96, 0x258C70CC, 0xD8801E3F, + 0x704CD907, 0x708C706C, 0x0F8273AC, 0x70CCFA6F, + 0x0F2A700C, 0x712CFA6F, 0x78E0C6C2, 0x1CFCC2FA, + 0x2482B6C8, 0xC0413C09, 0x70C01600, 0x001F8000, + 0x00320817, 0x0E06DE51, 0xC0010020, 0x3C092480, + 0x341B1404, 0x740CC6DA, 0x0BE6BE13, 0x41C1FC2F, + 0x3F002456, 0x70901600, 0x12238000, 0x708D1600, + 0x12228000, 0x0BEA702C, 0xDA90F9AF, 0x3A802456, + 0x0BDE702C, 0xDA90F9AF, 0x70921600, 0x001F8000, + 0x21402244, 0x1401264F, 0xF9EF08AE, 0x01402079, + 0x20402244, 0x20912244, 0x2244C044, 0xC0432100, + 0x0442242F, 0x740CC303, 0x41C3C204, 0x0003028A, + 0xFC2F0B7E, 0xC808BB22, 0x2005B802, 0x90380F80, + 0x90000008, 0xB8C2C049, 0x0050080D, 0x80B10871, + 0xF003720C, 0xC045710C, 0xC04278BB, 0x2014710C, + 0x226D0400, 0x41C32902, 0x0001028B, 0x740CC048, + 0x0B3E70ED, 0x4450FC2F, 0x01A00B2E, 0xC001C001, + 0x01E00CC2, 0x2F4079EF, 0x45101310, 0x0DCB70AD, + 0x2D40236E, 0x275A120E, 0x26051500, 0x726E140E, + 0x78B4704E, 0x800170C3, 0x18004DAC, 0x43420405, + 0x238C2200, 0x0201239F, 0xC8084CAA, 0x1488275A, + 0x42C37905, 0x00009004, 0x2455B902, 0x79453C0B, + 0x10CB2300, 0x01061100, 0x2300C18C, 0x6179120B, + 0x14032440, 0x134B2314, 0x71017865, 0x1B00B802, + 0x78451184, 0x100079B4, 0x740C0105, 0x01441900, + 0x028C41C3, 0x42420005, 0x0AA643E1, 0x44A1FC2F, + 0x20510C41, 0x000040C3, 0x271A0A3C, 0xB8021001, + 0x2000221F, 0x40A16119, 0x0184209A, 0xC8086119, + 0x210078C5, 0x80000F82, 0xB8021B40, 0x800071C3, + 0x20056D20, 0x90040F80, 0x90000320, 0xB100B200, + 0x2BFE238D, 0x71A5714E, 0x92540D37, 0x0F2371E5, + 0x244A9114, 0xD8987140, 0x903B43DB, 0x20A8C000, + 0x20050200, 0x740406C1, 0x00C51900, 0x20B10C11, + 0x20412478, 0x000047CB, 0xF00586B0, 0x000047CB, + 0x2940265C, 0xE90520C0, 0x000147CB, 0x20523694, + 0xC04A0100, 0xFCAF0DFA, 0xDE25700C, 0xBE9F716E, + 0x029040DB, 0xC8080005, 0x2005B802, 0x903B0F80, + 0x0B11C008, 0x228A2071, 0x18002802, 0xF0060045, + 0x2902228A, 0x01451800, 0x30171428, 0xC808708E, + 0x7140244A, 0x20A84242, 0x22050440, 0xE2100001, + 0x2105B902, 0x210506C3, 0x903B0F81, 0x1B00C004, + 0x190005C4, 0x160005C4, 0x80007080, 0x08110001, + 0xDD6400BF, 0x708D1600, 0x01208000, 0xE88BC003, + 0xD80FC201, 0x716C742C, 0x70AC44A1, 0xFB6F0DD6, + 0xC00470CC, 0xC201E88A, 0x742CD80F, 0x44A1706C, + 0x0DC270AC, 0x70CCFB6F, 0x70AE720C, 0xC047C046, + 0x8E3B8E00, 0x710C7905, 0x05402800, 0x200FB802, + 0x782B0540, 0x740CF2A6, 0x028D41C3, 0x42620003, + 0x093E43E2, 0x240AFC2F, 0x16000540, 0x80007091, + 0x16001222, 0x80007080, 0x210C1223, 0x0124A000, + 0x40C3000D, 0x12D98000, 0x20118800, 0xF2888440, + 0x0AA2C001, 0x212F01E0, 0x700E0447, 0x2448262F, + 0xC00BC04B, 0x042E08F3, 0x1408252F, 0xE8ABC004, + 0xE8B4C003, 0x41C240A2, 0x7F6042A1, 0x4118706C, + 0x4103740C, 0x43A24222, 0x0400240A, 0x05C0250A, + 0xFC2F08CE, 0x0640260A, 0x41C240A2, 0x7F6042A1, + 0x4508716C, 0x3401204F, 0x4222740C, 0x240A43A2, + 0x250A0400, 0x08AA05C0, 0x46A1FC2F, 0x164D2509, + 0x40A2F01F, 0x42A141C2, 0x706C7F60, 0x740C4508, + 0x028E41C3, 0xF00C0005, 0x41C240A2, 0x7F6042A1, + 0x4508716C, 0x41C3740C, 0x0005028F, 0x43A24222, + 0x0400240A, 0x05C0250A, 0xFC2F0866, 0x43A246A1, + 0x248C215A, 0x0201239F, 0x3A802456, 0x60986078, + 0x04012014, 0x3F002456, 0x91406078, 0x03650A17, + 0x20146098, 0x42A10400, 0x1800B1A0, 0x40E205C4, + 0x20F4F003, 0xC2400400, 0x0008272F, 0x41C3740C, + 0x00070292, 0x432242A2, 0x0400240A, 0x05C0250A, + 0xFC2F080E, 0x710646A1, 0xA254080B, 0xF16B7126, + 0x71AEC007, 0x70147704, 0xF54CC047, 0x274C71E6, + 0x061EA800, 0x8E00FFC5, 0x79058E3B, 0x2800710C, + 0xB8020500, 0x0500200F, 0xF24C782B, 0x70901600, + 0x12228000, 0x70801600, 0x12238000, 0x04240877, + 0x40C34082, 0x12D98000, 0x08678800, 0x212F042E, + 0x09420407, 0xC00101E0, 0x2495205A, 0x70AD4610, + 0x236E0E49, 0x2500210A, 0x3A802456, 0x2201219F, + 0x70A27022, 0x034020F4, 0x700CE88A, 0x029341C3, + 0x42820003, 0x0C824302, 0x44A1F9AF, 0x2500205A, + 0x200078B4, 0x80010F81, 0x24564DAC, 0x70223F00, + 0x20F470A2, 0xB1000340, 0x0DB971A5, 0x71069254, + 0xC301F1C2, 0x000042C3, 0x0D9EBA68, 0x414203E0, + 0x718EC006, 0x08537704, 0xC0468031, 0x230CC005, + 0x0536A000, 0x7166FFE5, 0xC00170CD, 0x01E008B6, + 0x2E4079CF, 0x43101311, 0x0B7970AD, 0x2D40236E, + 0x704C1210, 0x24502005, 0x4340724E, 0x148C265A, + 0x0201239F, 0x3C002455, 0x04082200, 0x900447CB, + 0x20400000, 0x44A11481, 0x20006078, 0xC808030B, + 0x23F47905, 0xB9021349, 0x190079E5, 0x20400244, + 0x78251401, 0x029441C3, 0xB8020005, 0xC08C7F05, + 0x43C16078, 0x24F4641C, 0xB7001340, 0x24F4740C, + 0x0EAE1345, 0x23F4FBEF, 0x228D1346, 0x714C247F, + 0x0D8B71A5, 0x71C59254, 0x91140E73, 0x0882C001, + 0x712C03A0, 0x7A0FC008, 0x780FC002, 0x00040A29, + 0x6832C808, 0xB8C4C002, 0x7825B80E, 0x0F832005, + 0x00089038, 0xB300C009, 0x7104C002, 0x780FC042, + 0x80050AE5, 0x70801600, 0x01648000, 0xF42BB8E6, + 0x70801600, 0x001F8000, 0x00FF0839, 0x41C3740C, + 0x00000295, 0xFBCF0E3A, 0x256FC201, 0xD80F1A43, + 0x716C742C, 0xFF6F0BFE, 0x12051D00, 0xD80FC201, + 0x0BF2742C, 0x706CFF6F, 0xB88FD808, 0xF00BB500, + 0x029641C3, 0x0E0A0000, 0x740CFBEF, 0xFAEF0F7A, + 0x020DC001, 0x78E0FFCF, 0x1CFCC2FA, 0xC1BFB6C8, + 0xC8084410, 0x2005B802, 0x90380F80, 0x90000008, + 0x1600C043, 0x80007080, 0xC1030164, 0xC046B9C2, + 0x800040C3, 0x88601222, 0x00700911, 0x72348841, + 0x00220320, 0xF003720C, 0xC044710C, 0xC00671AD, + 0x780D7D54, 0xC0497F7B, 0x88002044, 0xF40EC047, + 0x7140244A, 0x20A8D898, 0x20050280, 0x903B0F81, + 0x7404C000, 0x00C51900, 0x01600D7E, 0xD8254082, + 0x33C7232F, 0x712FB89F, 0x881B8820, 0x20787825, + 0x710400C0, 0x78AFC048, 0x202FC041, 0xC0043647, + 0x02347013, 0x40820025, 0x752CC808, 0x2005B802, + 0x903B0F80, 0x0815C008, 0xC1453071, 0xDEA0712C, + 0x730CB020, 0xF009C040, 0x01451800, 0xDEA4740C, + 0x760CC040, 0x70ADC045, 0x7510C008, 0x000601F2, + 0x2578C007, 0x20791017, 0x27040000, 0x20782017, + 0x27043040, 0x0F1F2017, 0x244A2071, 0xD8987140, + 0x024020A8, 0x0F812005, 0xC000903B, 0x19007404, + 0x08DE0005, 0x710CFCAF, 0x30041400, 0x2347262F, + 0x218AD8C8, 0x43820004, 0x000042C3, 0x250ABA68, + 0x70CC0580, 0x02A0083E, 0xC0064250, 0x800140D3, + 0x08434DAC, 0x244000FF, 0x74AE3B13, 0x2400210A, + 0x41224062, 0xF96F0CB2, 0x2340DA14, 0x258D2513, + 0x21402EBF, 0x14142511, 0xD8C83004, 0x0004218A, + 0x43824242, 0x0580250A, 0x02600FFA, 0xC28B70CC, + 0x42C3F004, 0xBF648000, 0x244A746C, 0x20A87280, + 0x100002C0, 0x12022101, 0x60380500, 0x1802781D, + 0x238C2014, 0x084A0D7F, 0x700CFCAF, 0x0E424082, + 0x702C0360, 0x706E70F6, 0xF28570AE, 0x7140244A, + 0x20A8D998, 0x21050280, 0x903B0F80, 0x7424C000, + 0x04C41800, 0xF07773AE, 0x244AC808, 0x20057140, + 0x41C10342, 0x038020A8, 0x00402205, 0xB802E110, + 0x0F832005, 0xC000903B, 0xC042700C, 0x00051B00, + 0x30041400, 0x142440C1, 0xD9103006, 0x0FFF26BF, + 0x000042C3, 0x43822950, 0x02600F5A, 0x0580250A, + 0x2540203C, 0x26C0200A, 0xC001C04A, 0x04040895, + 0x212FC002, 0x20790402, 0xB9C60000, 0x00922840, + 0x0D524082, 0x702E01A0, 0x230C2840, 0x24055020, + 0x43C11342, 0x00482205, 0x20412044, 0x010B2140, + 0x22C50955, 0x04AE0849, 0x10C12005, 0x903842C3, + 0xB9020000, 0x00892105, 0x11061100, 0x270BC10A, + 0xF216A040, 0x29812140, 0xB9027985, 0x26537A25, + 0x091D00C1, 0x120003F1, 0x0F150107, 0x274000F0, + 0x19000041, 0xB2201184, 0x10051900, 0x7126E310, + 0xF1D87146, 0x7106C002, 0x00002052, 0xF1B7C042, + 0x202F7166, 0x0D1524C7, 0x71A5A405, 0x05CFF106, + 0x7127FFEF, 0x03600D1A, 0xC001712C, 0x06C40827, + 0x6852C808, 0x11002753, 0xB80E71E5, 0x20057845, + 0x90380F81, 0xC0030008, 0x79EFB100, 0x08E9C001, + 0x16008045, 0x80007080, 0x08590164, 0x1600019F, + 0x80007080, 0x083B001F, 0x740C00FF, 0x028641C3, + 0x0ADE0000, 0x256FFBCF, 0xD80F1A43, 0x4282742C, + 0x08A2716C, 0x1D00FF6F, 0xD80F1205, 0x4282742C, + 0xFF6F0892, 0xD808706C, 0xB500B88F, 0x41C3F00A, + 0x00000287, 0xFBEF0AAA, 0x0C1E740C, 0x4082FAEF, + 0x1404C0BF, 0xC6DA341B, 0x200AC2F6, 0x80010F80, + 0x20A78000, 0x200A0849, 0x80010F80, 0x20A78000, + 0x200A0949, 0x80010F80, 0x20A77000, 0x200A0809, + 0x80010F80, 0x20A77000, 0x200A0909, 0x00080F80, + 0x20296000, 0x206F0000, 0x100020C3, 0x701420C0, + 0x000B072C, 0x800047CB, 0x8F00019A, 0x1600E886, + 0x80007080, 0xE812019B, 0x00C420AA, 0x003F0811, + 0x20AB720C, 0x710C00C4, 0x00C420AB, 0x010420AA, + 0x20AA5031, 0x50320144, 0x19C3266F, 0x70451E00, + 0x0080900C, 0x903045CB, 0x16EF03B8, 0x0D4E9481, + 0x950002E0, 0x000041D3, 0x0E962503, 0x1E00FC6F, + 0x0E961444, 0x41C30080, 0x00000325, 0xFBEF09E2, + 0x0D2ED80A, 0x40C3FA0F, 0xA6350000, 0x902446CB, + 0xB60020A8, 0x0304208A, 0xD80AB602, 0x032741C3, + 0x09BE0001, 0x4222FBEF, 0xD80A9542, 0x41C39560, + 0x00050328, 0x910415FC, 0x71051600, 0x03B89008, + 0xFBEF099E, 0x910615F8, 0xFDCF0B6E, 0xB802C808, + 0x0F802005, 0x002C9008, 0xCA079020, 0x01B5081B, + 0x00CC2184, 0x8084218C, 0x41C3F407, 0x00000329, + 0xF96F0E76, 0xCC1E700C, 0x08139620, 0x700C0060, + 0x032A41C3, 0x0E620000, 0xCC1FF94F, 0x08139622, + 0x700C0060, 0x032B41C3, 0x0E4E0000, 0x1600F94F, + 0x80007080, 0xB8E00185, 0x00C20C54, 0x1243256F, + 0x800042D3, 0x8D001138, 0x9566B8C3, 0x1A00B814, + 0x0B1A2043, 0x50300160, 0xFDCF098E, 0xFDCF09AE, + 0xBBE0C808, 0xB8024170, 0x0F802005, 0x003C900C, + 0x01141000, 0x1E00F28D, 0x90087045, 0x0DD60288, + 0x710C0020, 0x70801600, 0x00198000, 0x1600E893, + 0x80007080, 0x080D000D, 0x8D00005E, 0x011E0817, + 0xE8898F00, 0x70801600, 0x019B8000, 0x0E947014, + 0x0D66FA41, 0x0B42FF4F, 0xD933FECF, 0x08B2740C, + 0xB914FBEF, 0xFE0F0B22, 0xF9CF0A86, 0x742C700C, + 0xFA2F0EEE, 0x700C704C, 0xFA2F0BA2, 0x0DE6712C, + 0x700C0020, 0x70801600, 0x000D8000, 0x005E080D, + 0xB8E48D00, 0x01410F30, 0x1A43266F, 0xFBEF09A2, + 0x10451E00, 0xFB0F0B06, 0xFECF0A06, 0x01000E4E, + 0x233E0939, 0xD80A70ED, 0x033341C3, 0x08520000, + 0xBF8CFBEF, 0x70801600, 0x01848000, 0x20CA7014, + 0x1A0B0321, 0x08123002, 0xB6E0F9AF, 0xB80CD809, + 0x0DCAB600, 0xD80D0020, 0x03400C2E, 0xF9CF0A02, + 0x000040C3, 0x0C4E3A98, 0x702CFF6F, 0xD907780F, + 0x02022048, 0x706C700C, 0x70AC708C, 0xFA2F0B5E, + 0x700C70CC, 0xFA2F0B06, 0x0DC6712C, 0x710CFA4F, + 0x20031A00, 0xB600B88F, 0x00200D82, 0x0B3E700C, + 0x710CFC6F, 0x207E092B, 0x41C3D80A, 0x000002F1, + 0xFB8F0FCE, 0x1A43266F, 0x0A2E710C, 0x1E0001A0, + 0x720C1085, 0xB600B88F, 0x00200D52, 0x095D710C, + 0xD9BB20BE, 0x0FAAD80A, 0xB912FBAF, 0xFBCF0FAE, + 0x1A43266F, 0xFAEF0ABE, 0x11051E00, 0x41C3E80F, + 0x000002ED, 0xFBAF0F8A, 0x09EED80A, 0xD80901A0, + 0xB88F740C, 0x750CB600, 0x41C3F00E, 0x000002EE, + 0xFBAF0F6E, 0x09D2D80A, 0x700C01A0, 0xB88F740C, + 0x720CB600, 0x00000CF6, 0x000042D3, 0x21044000, + 0xF215A495, 0x02EF41C3, 0x0F460000, 0xD80AFBAF, + 0x1A43266F, 0x09A2D80C, 0x1E0001A0, 0x730C1484, + 0xB600B80E, 0x00200CC6, 0x2144D814, 0xF205A216, + 0x02E008EA, 0x0939710C, 0xD80A21BE, 0x02F741C3, + 0x0F0E0000, 0xDF40FBAF, 0xFD8F0FA2, 0x1A43266F, + 0xB6E0D80B, 0x01A00962, 0x30431A06, 0xB88FD840, + 0x0C8AB600, 0x760C0020, 0x30031A06, 0xF445262F, + 0x00030096, 0xF98F0EF6, 0xFAEF09FA, 0xE8094710, + 0x02F941C3, 0x0ECA0000, 0xD80AFBAF, 0x266FF03D, + 0xD95F14C3, 0x10931600, 0x0EB6B913, 0xD80AFBAF, + 0x12CF2640, 0xB700D880, 0xA0002351, 0x090AD80D, + 0x20CA01A0, 0x8E0002A1, 0x00BF0843, 0x218A70F6, + 0xD8FF0FC7, 0xFAEF0802, 0xCA0A703C, 0xD825E897, + 0xB89F706E, 0x88C072EE, 0x7E05881B, 0x14EE0E19, + 0x0A864062, 0x712CFB2F, 0x42008D20, 0x098E700C, + 0x4362FC2F, 0x2D3F278D, 0xD880716E, 0xB700B88F, + 0x00200BEA, 0x0D67D80A, 0x16002010, 0x80007080, + 0x08510164, 0xD92F013F, 0x0E36D80A, 0xB914FBAF, + 0x1A43266F, 0xF9AF0E46, 0x14841E00, 0x218A7014, + 0xD8FF0FC7, 0xFFAF0A0A, 0x730C703C, 0xB600B80E, + 0x00200BAA, 0x8D20D814, 0x704C700C, 0xFC2F092E, + 0x8D20706C, 0x714C700C, 0xFC2F0922, 0xF007716C, + 0xD80AD9CD, 0xFBAF0DEA, 0x096DB912, 0xD80A22BE, + 0x02FA41C3, 0x0DDA0000, 0x278AFBAF, 0x0DEE1010, + 0x4210F98F, 0x70801600, 0x01638000, 0xFA6F0E42, + 0x266F712C, 0x41421A43, 0x02600EFA, 0xD821B6E0, + 0xB600B80A, 0xE895CA0A, 0x70EDD825, 0x724EB89F, + 0x88DB8820, 0x0E157E25, 0x40E113EE, 0xFB2F09AA, + 0x0EAA712C, 0x41E1FBEF, 0x2DFF228D, 0x0B1E71ED, + 0xD80E0020, 0x2051092D, 0x70801600, 0x00198000, + 0x1600E897, 0x80007080, 0xE893011D, 0x033541C3, + 0x0D5E0000, 0xD80AFBAF, 0x01600FBE, 0xF009D808, + 0x213F0909, 0xF003710C, 0x0F3E700C, 0x09710140, + 0x704E213E, 0x20801000, 0x370E1223, 0x0D4EB8E2, + 0x22CAF9AF, 0x278A23E1, 0xE8831FC7, 0x0E51DFFF, + 0xD80A117E, 0x02FD41C3, 0x0D160000, 0x208AFB8F, + 0x266F0404, 0xB6001A43, 0x4142720C, 0x00200AEA, + 0x083242E1, 0xE80DFACF, 0x02FE41C3, 0x0CF20000, + 0x740CFBAF, 0x4142730C, 0x00200ACE, 0x40C342E1, + 0x81100000, 0x0A76B600, 0xD8160020, 0x20300EAD, + 0x40C3704E, 0x01888000, 0x103F9020, 0x70308700, + 0xF786700C, 0x00000F5A, 0x00002052, 0x30021A05, + 0x0E7A700C, 0x1A0C02A0, 0xCA053482, 0x700CE806, + 0x02A00E6A, 0x30431A0C, 0x20801000, 0x370E1223, + 0x0CAAB8E2, 0x22CAF9AF, 0x278A23E1, 0xE8831FC7, + 0x0E0DDFFF, 0x0F9E119E, 0xE808FA8F, 0xD80A732C, + 0xFBAF0C6E, 0xF022B918, 0x02FF41C3, 0x0C620000, + 0xD80AFBAF, 0x0204208A, 0x1A43266F, 0x710CB600, + 0x0A364142, 0x42E10020, 0x000040C3, 0xB6000908, + 0x4142700C, 0x00200A22, 0x40C342E1, 0x81080000, + 0x09CAB600, 0xD8180020, 0x227E0951, 0x41C3D80A, + 0x00000301, 0xFBAF0C1A, 0x2008228A, 0xF9AF0C2E, + 0x208F1000, 0x0F764010, 0x730CFC2F, 0x700CBFE2, + 0x1A43266F, 0x03E120CA, 0x0CE24102, 0x1E000220, + 0xD8411484, 0xB600B809, 0xE885CA0A, 0xFBEF0CCA, + 0x097A8D00, 0xD8090020, 0xE829CA0A, 0x70EDD825, + 0x720EB89F, 0x88DB8820, 0x0E297E25, 0x40E113EE, + 0xFAEF0FD6, 0x8D20712C, 0x710C4200, 0x0EDE43E1, + 0x4250FBEF, 0x700C8D20, 0x0ED24242, 0x43E1FBEF, + 0x2B7F208D, 0x0C8271ED, 0x8D00FBEF, 0x70801600, + 0x00008000, 0x0EACB8E5, 0x0982FC02, 0x0923FECF, + 0x8D002050, 0x0C012044, 0x0C100913, 0x017F0809, + 0xF003700C, 0x0C4A710C, 0x0ED202C0, 0x0CBE0100, + 0xC8080080, 0x2005B802, 0x900F0F80, 0x1800C03C, + 0x08DE0504, 0x700C0160, 0x00000DF6, 0xD80AD967, + 0xFBAF0B3E, 0x0E96B913, 0x700CFC2F, 0x02A00F6A, + 0x700CD807, 0x00C420AB, 0xF0007FFF, 0x02800C82, + 0x4308C2E6, 0x730C71AD, 0x900F46CB, 0x0EAAC028, + 0xB6A0FF2F, 0x900847CB, 0x97000288, 0x0B3DB8A1, + 0xB7001031, 0x900F41C3, 0x40C3C298, 0x3FFF0000, + 0x19E8B1A0, 0x20508004, 0x40C30341, 0xC2249007, + 0x1600B020, 0x80007082, 0x2253000C, 0xF205817E, + 0x00051804, 0xB022F002, 0xFF2F0E5E, 0xD81FD80D, + 0x135C1FAC, 0xFF2F0E52, 0x10051E00, 0x78E0C6C6, + 0x4308C2E4, 0xFF2F0E42, 0x70ADD81F, 0x900846CB, + 0x740C03E0, 0xFF2F0E32, 0x1654B6A0, 0x206C9700, + 0xB8810040, 0x10300B0B, 0x901C1E54, 0x700CC6C4, + 0x900F41C3, 0xB88CC280, 0x40C3B100, 0xC2249007, + 0xB0A2B0A0, 0xC6C4B1AC, 0x4608C2E4, 0x70801600, + 0x00128000, 0x8203208C, 0x02AE0E8C, 0x0EFA40C1, + 0x0BDE0040, 0x0B26FECF, 0xCA110080, 0x800145CB, + 0x25164FC4, 0x0B4A1000, 0xB0C0FAEF, 0x30821211, + 0xA5017D56, 0x0F0A6A01, 0x1A11FAAF, 0x0C663002, + 0xC6C40280, 0x1CFCC2FA, 0x2482B6C8, 0x41583304, + 0x4310C141, 0x702CC08E, 0xF92F0A26, 0x708EDA50, + 0x35001C34, 0x35001C30, 0x35001C2C, 0xFBEF087E, + 0x35001C28, 0x21350B27, 0x2353C042, 0x730C20C1, + 0x21787839, 0xB8C000DB, 0x202FC043, 0x26F004C5, + 0x80007000, 0xC04410C4, 0x700CF007, 0xB890706F, + 0x4063C044, 0x2350C043, 0x21842000, 0xC0473004, + 0x46D3720C, 0x12218000, 0x800047D3, 0xC045C144, + 0x458AD825, 0x718EB89F, 0x881B8820, 0x2C007905, + 0xB8022340, 0x0350200F, 0xA040200B, 0x00210408, + 0x0CEA730C, 0x1E00FC2F, 0xC0042342, 0x0E2A78A5, + 0xC04602A0, 0xC8084110, 0x7825C106, 0x208916B8, + 0x20881602, 0x008B2840, 0x20811601, 0x1064086D, + 0x096540A1, 0x2940106E, 0x215A0380, 0x2005050C, + 0xC78E02C0, 0x7280244A, 0x0F832005, 0x00009000, + 0x679F700C, 0x080020A8, 0x30310911, 0x06822100, + 0x0082121C, 0x0080082F, 0x30300B0B, 0x02422079, + 0x2078F003, 0xEA8F0242, 0x0271080D, 0x9340C68E, + 0xF009B749, 0x02822840, 0x7A65669E, 0x92407E14, + 0x7104B640, 0xF1CC7124, 0x3005140C, 0xC28C4162, + 0x708CC38A, 0xFC6F0C12, 0x40C370CC, 0x12DC8000, + 0x21798020, 0x40A13002, 0x09CA4340, 0x4250FE2F, + 0x30300B73, 0x1407262F, 0x0CCE710C, 0x41C1FC2F, + 0x00800A0A, 0x38812455, 0xDA084022, 0x44C14362, + 0x3C052440, 0x0480260A, 0x089A71EC, 0x2455FB6F, + 0xDA23388F, 0xBA0A40E2, 0xF92F08A6, 0xC301702C, + 0x1408D808, 0x41623004, 0x2440704C, 0x260A3C05, + 0x70EC0480, 0xFB6F0C52, 0x2455C740, 0x082A3880, + 0x702CFB6F, 0x0C72700C, 0x41C1FC2F, 0x00C00E3E, + 0x2455F029, 0x40223881, 0x4362DA08, 0x244044C1, + 0x260A3C05, 0x71EC0480, 0xFB6F083A, 0x388F2455, + 0x40E2DA23, 0x084ABA0A, 0x702CF92F, 0xD808C301, + 0x30041408, 0x704C4162, 0x3C052440, 0x0480260A, + 0x0BF670EC, 0xC740FB6F, 0x38802455, 0xFB2F0FCA, + 0x1601702C, 0x16022091, 0x210C2080, 0x025CA000, + 0x40C3000D, 0x12D98000, 0x20118800, 0x02468440, + 0x29400021, 0xC0062315, 0x05402005, 0xC049700E, + 0x2280215A, 0x0917C048, 0x21003031, 0x101C2680, + 0x200C0080, 0x0214A000, 0x0B0D0001, 0x20793030, + 0xF0042240, 0x22402078, 0x02007014, 0xC2080002, + 0x229A7202, 0x2232000E, 0x80000F83, 0xEB14C444, + 0x00700B2B, 0x05C02234, 0x0B1772E2, 0x922100F1, + 0xDE809282, 0x4E924913, 0x00A20B17, 0x42104291, + 0xF0074628, 0x70CD704E, 0xDE80F003, 0x215A4210, + 0xC08E2501, 0xC007603A, 0x040F22F4, 0x00B1080F, + 0xC08C4058, 0x044020F4, 0x0812F00A, 0x40E1FBAF, + 0xC08C4708, 0xFBAF0806, 0x044020F4, 0x4F10661E, + 0x20024EF1, 0x72760480, 0x20CA4608, 0x26CA0045, + 0x0B411046, 0x12082030, 0x0BB73609, 0x28402071, + 0x47CB220B, 0x00009000, 0x154B2305, 0x124B2305, + 0x1F812305, 0x006A0001, 0xB90261B9, 0x03C82105, + 0x1F812305, 0x00680001, 0xB90261B9, 0xF0787F25, + 0x220B2840, 0x900042C3, 0x23050000, 0x7BD0154B, + 0x124B2305, 0x23057810, 0x00011F81, 0x61B90068, + 0x7F4569F2, 0x21099720, 0x230500CE, 0x00011F81, + 0x61B9006A, 0x2105B902, 0x10000088, 0x21091101, + 0x23050000, 0xB9021341, 0x0F822105, 0x00489004, + 0x0F812105, 0x00409004, 0x16009240, 0x80007083, + 0x0B8D00EF, 0x91200030, 0xB9C6BAC6, 0x21CC72D1, + 0x005E838D, 0x0A59000D, 0x4A760065, 0x0B2DF029, + 0x210520B1, 0x28401541, 0x43C32202, 0x00009000, + 0x21057945, 0x00010F82, 0x62BA0060, 0x0F812105, + 0x00630001, 0xF00EBA02, 0x0F822105, 0x00190001, + 0x7AB4B981, 0xBA02B985, 0x43C3B990, 0x00009000, + 0xB2C07A65, 0xB90261B9, 0xF0277965, 0x621C4976, + 0xF705E4FE, 0xE4FF611C, 0x090FF78A, 0x228700A5, + 0x4A700FC1, 0x2187F004, 0x49700FC1, 0x1F812305, + 0x006C0001, 0x42C361B9, 0x00009000, 0xB7C0B902, + 0xB1C07945, 0x1F812305, 0x006E0001, 0x180061B9, + 0xB9021004, 0xB1007945, 0x41C3C009, 0x00009000, + 0x340320F4, 0x02402005, 0x2270080D, 0x2840B802, + 0x78452282, 0xB0607825, 0x204C7106, 0x05DAA280, + 0x05A7FFC5, 0x7126FFEF, 0x20110B1D, 0x71001600, + 0x00C49004, 0x0002204F, 0x900741C3, 0xB140C0C4, + 0xB100B8A0, 0x7704C005, 0x03D87014, 0xC045FFE2, + 0x33042480, 0x341B1404, 0x78E0C6DA, 0x70801600, + 0x000D8000, 0x08002044, 0xB8257FE0, 0xC1A4C3E4, + 0x70CDDD37, 0x1501BD9F, 0xC0621480, 0x14801501, + 0x30021C09, 0x14801501, 0x30021C0A, 0x14801501, + 0x30021C0B, 0x14801501, 0x1501C063, 0x1C0D1480, + 0x15013002, 0x1C0E1480, 0x15143002, 0x1C0F1480, + 0xC0823002, 0x022141C3, 0x60CB0002, 0x0D02740C, + 0x42C1FB6F, 0x0EEF71C5, 0x15019214, 0xC0601480, + 0x14801501, 0x30021C01, 0x14801501, 0x30021C02, + 0x14801501, 0x30021C03, 0x14801501, 0x8D00C061, + 0x30021C05, 0x1C068D01, 0x8D023002, 0x1C0770AD, + 0xC0803002, 0x022241C3, 0x60AB0002, 0x0CB2740C, + 0x42A1FB6F, 0x0DEF71A5, 0xC7C49214, 0x46CBC2E6, + 0x04628000, 0x800045CB, 0x08131A20, 0x470802FF, + 0x20539600, 0xF41180BE, 0x950AF00D, 0xB50AB880, + 0x20538E00, 0xF20780BE, 0xA503700C, 0xA501A502, + 0x0E22A500, 0x262FF94F, 0x0008F3C5, 0xC6C60004, + 0x20538E00, 0xF20780BE, 0xA503700C, 0xA501A502, + 0x0E02A500, 0xC6C6F94F, 0x46A8C2EA, 0x40704788, + 0x0CDA4548, 0x4130FB6F, 0x2281215F, 0x25CAE589, + 0x60381221, 0x229F7A0F, 0x2200000E, 0x20000400, + 0x80000F81, 0x8960C444, 0x0B1D710C, 0x78B800F0, + 0x00700B3F, 0x0B5178CB, 0x78CB00B0, 0x78CBEB83, + 0xC6CAF22C, 0xF3FF78CB, 0x2180205F, 0x40C3621A, + 0xC1448000, 0x9340621B, 0x78429301, 0x93027C10, + 0x7A504F12, 0x10850C1B, 0xB300B3E1, 0xF3EBF009, + 0x2180205F, 0x70C36058, 0xC1468000, 0x1900B0E0, + 0xC6CA0083, 0x205FF5DF, 0x19002180, 0x605800C3, + 0x800070C3, 0xF00AC148, 0x2180205F, 0x00431900, + 0x70C36058, 0xC1448000, 0xC6CAB0E0, 0xC1A6C3F2, + 0x44104530, 0xF2B27014, 0x230A70ED, 0x25142500, + 0x244023D2, 0x21143511, 0x120023D1, 0x20532100, + 0x19010141, 0x702C2042, 0x1900B826, 0x0EBA2002, + 0x4022FE6F, 0x21001204, 0x34102440, 0x23D02014, + 0x01412053, 0x20421801, 0xB826702C, 0x20021800, + 0xFE6F0E96, 0x40224002, 0x0DB24102, 0x724C0060, + 0x2100120A, 0x7EF4C683, 0x01412053, 0x712CAE21, + 0xAE00B826, 0xFE6F0E72, 0x120E40C1, 0xC5822100, + 0x20537DF4, 0xAD210141, 0xB826712C, 0x0E5AAD00, + 0x40A1FE6F, 0x41A140C1, 0x00600D72, 0x1101724C, + 0xE0C02080, 0xD940F704, 0xF0044910, 0x003F2080, + 0x31812440, 0xA90061F9, 0x20801001, 0xF705E0C0, + 0x4910D940, 0x2080F003, 0xC181003F, 0xA90061F9, + 0xE0C08E01, 0xD940F704, 0xF0044910, 0x003F2080, + 0x30812440, 0xA90061F9, 0xE0C08D01, 0xD940F704, + 0xF0044910, 0x003F2080, 0x63F9C380, 0x238D71E5, + 0xA900227E, 0x7500240A, 0x708D70AD, 0x704C706D, + 0x054020A8, 0x30802440, 0x22086088, 0x13010001, + 0x21080480, 0x24400002, 0x60883180, 0x10012308, + 0x6088C081, 0x21087185, 0x270A000B, 0xC3830540, + 0x32042440, 0x35052440, 0x34062440, 0x24147BB4, + 0x25140344, 0x26140345, 0x78AF0346, 0xFA2F0812, + 0x71A54161, 0x95040DDB, 0x78E0C7D2, 0x1CFCC2FA, + 0x2482B6C8, 0x1C473D08, 0xC0413058, 0x36001447, + 0x30981C48, 0x800042C3, 0x1C081224, 0x08293100, + 0x1C490070, 0x144730D8, 0xE89F3600, 0x70801600, + 0x00258000, 0x00C02078, 0x00971200, 0xC0407104, + 0xF0118A01, 0x70801600, 0x00408000, 0x00412078, + 0x00971202, 0x7314C140, 0x20CAC000, 0xC04000A1, + 0x1C468A03, 0xC2013018, 0x41C3740C, 0x000200BD, + 0xFB6F09AE, 0xC001C300, 0x02D07014, 0xD9200021, + 0x0BC3216F, 0x780A8900, 0x301C1A1C, 0x780A8901, + 0x301C1A1D, 0x7014C000, 0x0021052C, 0x40DB708E, + 0x0A3C0000, 0x2619271F, 0x394F2456, 0x33102440, + 0x800043DB, 0x27801A3C, 0x20801084, 0x706E2084, + 0x36D92100, 0x30181C45, 0x7001248A, 0x218AC083, + 0x1A0D0FC7, 0x20A834C2, 0xB0210180, 0x00151804, + 0x39402456, 0x248AD9FF, 0x228A7001, 0x18000FC7, + 0x1C8627C3, 0x1C88351C, 0x20A8305C, 0xB0410180, + 0x00151804, 0x25C0210A, 0x3F802400, 0x02280000, + 0x17C31F00, 0x00051800, 0x1446B022, 0x08CF3600, + 0xC0830464, 0x36001448, 0x0447212F, 0x01200A86, + 0x34581A0B, 0xC04270AE, 0x08A9C002, 0x211A054E, + 0x1A0C2600, 0x231A3558, 0x00002F92, 0x220028F0, + 0x40A22012, 0x0184209A, 0x20007042, 0x0ED606CD, + 0x40A10260, 0xF4E47014, 0x41C3740C, 0x000200CA, + 0x08AE4222, 0x43A2FB6F, 0x0CCA4062, 0x4122FD6F, + 0x24404608, 0xE8843316, 0x39562456, 0x02400DBE, + 0x700C7014, 0x800042C3, 0xF2101B3E, 0xC083EE03, + 0x2456F003, 0x10823940, 0x40A20701, 0x0184209A, + 0x60587042, 0x78229001, 0x219A41A2, 0x71420184, + 0xEE05614A, 0x20811000, 0x8F20F002, 0x242F4A33, + 0x40C20006, 0x0D3241A1, 0x42C2FA6F, 0xF4A87014, + 0x0D5971A6, 0x7126A294, 0x0D16F199, 0xC1010060, + 0x70CE7014, 0xC101F49D, 0x00600D06, 0x39402456, + 0xF4977014, 0x20821000, 0x41C3740C, 0x000200CB, + 0xFB6F080E, 0x37031488, 0x24348F40, 0x00003F83, + 0x41C3022C, 0x000200CC, 0xFB2F0FF6, 0x1446740C, + 0x080F3600, 0x71CE05E5, 0x36001445, 0x462BF079, + 0x25C0210A, 0x36001448, 0x0447212F, 0x01200966, + 0x34581A0B, 0x02600CF6, 0x4508C042, 0x0BE64062, + 0x4122FD6F, 0xE808ED05, 0x208D1000, 0xE806F00A, + 0xF006C083, 0xF0068FA0, 0x39402456, 0x070D1082, + 0x45D1704E, 0x0867C002, 0x740C04AE, 0x00CD41C3, + 0x42220002, 0x0F8A4342, 0x1A0CFB2F, 0x0CAE3498, + 0xE8070240, 0x0C6A40A2, 0x41A1FC6F, 0x40A2F005, + 0xFC6F0B82, 0xE8BC41A1, 0x0084208A, 0x00CE41C3, + 0x25320004, 0x740C2005, 0x43224262, 0xFB2F0F52, + 0x0480240A, 0xE80BCA06, 0x40A2C101, 0x36021447, + 0x0B7A4362, 0x14490320, 0x71463604, 0xA2B40A99, + 0x21842580, 0x02400C56, 0x2602211A, 0x231A7014, + 0x00002F81, 0x40C328F0, 0x1B3E8000, 0xF2056159, + 0xA8A06038, 0x6038F003, 0x1446B0A1, 0x76033600, + 0xA000210C, 0xFFE50720, 0xF1887126, 0x70D670CE, + 0x00210292, 0xC1007166, 0xA040230C, 0xFFE50588, + 0x37942196, 0x00000281, 0xB99F700E, 0x780A8900, + 0x301C1A1C, 0x780A8901, 0x301C1A1D, 0x36001449, + 0x0D5EE805, 0xE803FB4F, 0x41D3710E, 0x51E00000, + 0x20D82941, 0x2440201F, 0x2619271F, 0x800043DB, + 0xC7831A3C, 0x10842780, 0x20007023, 0x144606D9, + 0x270C3600, 0x0230A000, 0x708E002D, 0x36001448, + 0x05C7212F, 0x080E706E, 0x1A0B0120, 0x1C8C35D8, + 0x1C453018, 0x148C3658, 0x20113600, 0xF2ED84C0, + 0x7001248A, 0x218AC083, 0x704E0FC7, 0x34D81A0C, + 0x014020A8, 0x1804B021, 0xD8FF0015, 0x17C31F00, + 0x301C1C88, 0x08BDC000, 0x1C860030, 0x1445349C, + 0xC002360E, 0x2025082B, 0x34821A0D, 0x250A70AD, + 0x66B82400, 0x0AFA702C, 0x1A0D0060, 0x44103558, + 0xF4BF7014, 0xC00271A6, 0xA0240DEB, 0x71467522, + 0x000045D3, 0xC00028F0, 0xA0240ACB, 0x70AD76A2, + 0x0869C002, 0x1A0D2025, 0x220A3342, 0x0B0E2400, + 0x1A0D0260, 0x251A3498, 0x70141542, 0x2441221A, + 0x800040C3, 0x271A1B3E, 0x708D2603, 0x42626159, + 0x0184229A, 0x627A633B, 0x6059F206, 0x14889161, + 0x4B343701, 0x06C12200, 0x8F00620A, 0x0306242F, + 0xC0834A13, 0xFA6F0A82, 0x4410C283, 0xF4817014, + 0xC0027146, 0xA0040AAB, 0xC00071A5, 0x90040D95, + 0x740CD95F, 0xFB2F0D7A, 0x8F40B911, 0x41C3740C, + 0x000200BF, 0xFB2F0D6A, 0x37031488, 0x0A42C083, + 0x702C0060, 0x08CD4410, 0x70CE0031, 0x740C8F40, + 0x00C041C3, 0x0D4A0002, 0x1488FB2F, 0xD9C13703, + 0x0D3E740C, 0xB910FB2F, 0x08A1C000, 0x71CE0030, + 0x220A70AE, 0x1A0D2400, 0xC0023542, 0x20250A85, + 0x0487202F, 0x2F81251A, 0x28F00000, 0x221A5035, + 0x271A2440, 0x6038260E, 0x4062661E, 0x0184209A, + 0x0A2A661D, 0x75630260, 0x8F20E806, 0xFC6F09E2, + 0xF00740A1, 0x37011488, 0xFC6F08FA, 0x441040A1, + 0x4062E8A7, 0x00C241C3, 0x209A0004, 0x42A20184, + 0x240A43E2, 0x60D804C0, 0x0F852032, 0x1B3E8000, + 0xFB2F0CBE, 0xCA06740C, 0x1447E80A, 0x40A13602, + 0x36041449, 0x08E6702C, 0x43A20320, 0xF1BF7146, + 0xC00071A6, 0xA0040D6F, 0x30141404, 0x70CEF002, + 0x20110E0B, 0x1404F018, 0x14453014, 0x71663600, + 0x01842080, 0xA280234C, 0x30181C45, 0xFFE5060A, + 0x35001C04, 0x36192100, 0x05D771E6, 0x1C04FFEF, + 0x44103500, 0x0507202F, 0x3D082480, 0x341B1404, + 0x78E0C6DA, 0x1600C2EA, 0x8000708D, 0x40500008, + 0x0E1E4130, 0x4608F92F, 0xD907706C, 0xDA284768, + 0x708CBF8F, 0x70AC40E1, 0xF96F0F82, 0x0A2A70CC, + 0x700CF98F, 0xDA08D907, 0x708C706C, 0x0F6E70AC, + 0x70CCF96F, 0xD907700C, 0x706C704C, 0x70AC708C, + 0xF96F0F5A, 0x6F1670CC, 0x704C752C, 0x0004238A, + 0x45C1708C, 0xF96F0F46, 0x257870CC, 0x781B1080, + 0x20300845, 0xD92B68A2, 0x010040C3, 0x42A1000C, + 0x708C706C, 0x70CC45C1, 0xF96F0F22, 0x2F404010, + 0xD92B1240, 0x706C42A1, 0x45C1708C, 0xF96F0F0E, + 0x0440260A, 0xD92B4002, 0x706C42A1, 0x45C1708C, + 0xF00B70CC, 0x12402F40, 0x42A1D92B, 0x708C706C, + 0x260A45C1, 0x0EE60440, 0x700CF94F, 0x744CD907, + 0x708C706C, 0x0ED670AC, 0x70CCF96F, 0xF98F0962, + 0xD907700C, 0x706CDA30, 0x70AC708C, 0xF96F0EBE, + 0xC6CA70CC, 0x1600C2E2, 0x80007080, 0x083F0001, + 0x45CB001E, 0xC148900B, 0x10451D00, 0x800042C3, + 0x12FF0203, 0x8A008481, 0xB810B918, 0x12FF7825, + 0xB9088081, 0x12FE7905, 0x20058080, 0x0F1E8040, + 0x20CAFEAF, 0x1D0002A1, 0xC6C21005, 0x1600C2E4, + 0x80007080, 0x45CB001A, 0xC40C900F, 0x00510821, + 0x900F40C3, 0x1D00C1E4, 0x1D001045, 0x18001005, + 0x18000185, 0x0E820005, 0xD820FEAF, 0x0E7A750C, + 0x1D00FEAF, 0xD8201045, 0x900F46CB, 0x0E6AC1E4, + 0x1E00FEAF, 0x1D001185, 0x1E001005, 0xC6C41005, + 0xD841C2E2, 0x900845CB, 0xB50001E4, 0xFEAF0E4A, + 0xD840750C, 0xC6C2B500, 0xC1A4C3F4, 0x800045CB, + 0x15020150, 0xD97B1500, 0xB2004283, 0x1502B910, + 0xB2011500, 0x15001502, 0x1502B202, 0xB2031500, + 0x15001502, 0x9500B204, 0x9501B205, 0x9502B206, + 0x0A6EB207, 0x740CFB2F, 0x908015D7, 0x1210E804, + 0xF0043092, 0x3092120F, 0x710C702E, 0xE80872CE, + 0x70801600, 0x00258000, 0xF045E888, 0x70801600, + 0x00408000, 0x00100887, 0xC08070AD, 0x78B5700E, + 0x70ED728E, 0x044020F4, 0x2005781B, 0x00040F93, + 0x0A571000, 0x250A2030, 0x70CD2480, 0x1B00255A, + 0x1F852632, 0x04788000, 0x430242A1, 0x0440240A, + 0x201478D5, 0x70020440, 0x0F812000, 0x12288000, + 0x706278EF, 0xB89CB802, 0x8000B89F, 0x262FA900, + 0x41C30007, 0x0005007C, 0xFB2F09D6, 0x71C5740C, + 0x27BF258D, 0x248D71E5, 0x710E25FF, 0x0D8F71A5, + 0x700C9114, 0x2D7E268D, 0xC7D4712E, 0x4350C2F8, + 0x08854630, 0x44100030, 0x20002678, 0x220A70D6, + 0x781B24C0, 0x202222CE, 0x70AE68E9, 0x250D255A, + 0x800041C3, 0x652012E0, 0xB89CB802, 0x0B53B89F, + 0x10002030, 0x653D0118, 0x8D29702E, 0x20008D0B, + 0x40100497, 0x044A222F, 0x72624628, 0x0D4E4003, + 0x702CF8AF, 0x00412044, 0x10400E17, 0x20300E11, + 0x20402042, 0x20402040, 0xF003AD0D, 0x7126AD0C, + 0xA4E409D5, 0x23D02000, 0x15C21D0B, 0x248DAD29, + 0x71A6243F, 0x78E0C6D8, 0x47CBC2EE, 0x12228000, + 0x42508FA0, 0x1090251F, 0x70911600, 0x00048000, + 0x46084330, 0x20D12153, 0x08A58F01, 0x0E390344, + 0x0A99161F, 0x2D402030, 0x6E321380, 0x704C7905, + 0x0408202F, 0x20032314, 0xB80A784F, 0x78257144, + 0xB89CB892, 0x9000B89F, 0x784FB300, 0x84A408E5, + 0xF0347106, 0x7E06C808, 0x1F802604, 0xFFFE0FFF, + 0xFEFF70C3, 0x2843FFF0, 0xF2118100, 0x00D00823, + 0x00900817, 0x0071081F, 0x0CCA40C1, 0x41A1FD2F, + 0x710C7014, 0x720CF408, 0x700CF006, 0x730CF004, + 0x740CF002, 0x2B01215F, 0x8F037915, 0x0340203C, + 0x26447914, 0x60381040, 0x882660F8, 0x0408202F, + 0x20002314, 0xB0207106, 0xF1B071A5, 0x78E0C6CE, + 0x4410C2F8, 0x03952840, 0x1600785B, 0x80007096, + 0x2044008E, 0xD8E40182, 0x2C407859, 0xB8C12318, + 0x2F8E2505, 0x01C89004, 0x0F112054, 0x040F2040, + 0x01972140, 0x704E706E, 0x700E70AD, 0x26012205, + 0x7825C808, 0xA07E2653, 0x900441C3, 0xF20D0000, + 0xB80278E5, 0x90007825, 0x01C120AD, 0xB8647314, + 0x002D20CA, 0x2005F00C, 0xB8020440, 0x218A7825, + 0x90000FBF, 0x770CB8E6, 0x004120CA, 0x20022700, + 0xE810CA07, 0x02310811, 0x37011221, 0x0F800915, + 0x68150000, 0x02510811, 0x0F81090D, 0x71960000, + 0xF003BA86, 0xD808BA87, 0xFEAF0B4E, 0x2505B640, + 0x225624C0, 0x20052812, 0x90040F80, 0x900001CC, + 0x20102380, 0x2800B8C0, 0x71060400, 0xA2740871, + 0x78B07D05, 0x087E4182, 0x1E00FB2F, 0x780F1005, + 0x78E0C6D8, 0x2840C2E6, 0x4708038E, 0x2605D889, + 0x90041F8D, 0xB50001C8, 0xFEAF0AFE, 0x244AD808, + 0x708D7240, 0x702C704C, 0x20A8706C, 0x26050400, + 0x22801080, 0x20050010, 0x90040F80, 0x900001CC, + 0x7838B8C0, 0x7B057124, 0x41E17870, 0xFB2F0826, + 0x780FB580, 0x78E0C6C6, 0x014422AA, 0x010421AA, + 0x800040C3, 0xA04104B0, 0xA0207FE0, 0x45CBC0E6, + 0x12228000, 0x46008D60, 0x0A1B718D, 0x700C00B0, + 0x0241235F, 0x00710A13, 0xE108DE08, 0xD808DC09, + 0x4160F003, 0x150170CD, 0x4E12108B, 0x00492240, + 0x0B377D6F, 0x0E2F1344, 0xBD0E1024, 0x7240240A, + 0x20A84008, 0x7A2F0440, 0x26146199, 0x2840008F, + 0x7AA51282, 0x22057105, 0x90040F82, 0x924001D0, + 0x7164B740, 0xC4C6F1E6, 0x40C3C5E1, 0x04988000, + 0xE9AE8820, 0x00431800, 0xE82ACA00, 0x70AD712D, + 0x800144CB, 0x2D404FA0, 0x244A1381, 0x42817240, + 0x706D700D, 0x05C020A8, 0x02002105, 0x20057405, + 0x90040F83, 0x8A000200, 0x2900B300, 0x120112C3, + 0x71650480, 0x7825B80A, 0x0F802005, 0x02F89004, + 0x71A5B060, 0x0DC3CA00, 0xE4099024, 0x78E0C4C2, + 0xDC25C808, 0x43C3BC9F, 0x12248000, 0x2005B802, + 0x90070F81, 0xCC23C408, 0x8C00B100, 0x8B01E818, + 0x082D8B20, 0x78220064, 0x240A7104, 0x20A87000, + 0x40C30400, 0x049C8000, 0x004220F4, 0x03802940, + 0x20057124, 0x90040F80, 0xB040028C, 0x70148C1B, + 0x8B037CE0, 0x72108B42, 0x07CD20E0, 0x71047842, + 0x7000240A, 0x03C020A8, 0x800040C3, 0x20F4049C, + 0x2A400081, 0x71440380, 0x0F802005, 0x028C9004, + 0x7EE0B020, 0x21326038, 0x80000F82, 0xA8401880, + 0x0F822132, 0x18CB8000, 0x0082184B, 0x0F822132, + 0x19168000, 0x00821896, 0x0F812132, 0x19618000, + 0x18E17FE0, 0x78E00042, 0x4748C2E6, 0x00851101, + 0x46288861, 0x00841100, 0x88404508, 0x41C3740C, + 0x000500D7, 0xFAEF0D6A, 0x8E0046E1, 0x71108D20, + 0xF7C7F233, 0x03E50915, 0xAD006909, 0x0835F00F, + 0x770403C5, 0xF01FAE00, 0x0F1349F0, 0xAD001070, + 0x10900F1B, 0x10C01501, 0x8D01F005, 0x08002054, + 0x262FAD01, 0x0032F005, 0xD87F0003, 0xF015AD01, + 0x0F1378E2, 0xAE001070, 0x10900F1B, 0x10C01601, + 0x8E01F005, 0x08002054, 0x262FAE01, 0x000AF005, + 0xD87F0003, 0x8E60AE01, 0x00D841C3, 0x8D400003, + 0x09F644E1, 0x2238F8AF, 0xC6C600C0, 0x41C3C2E4, + 0x0000031A, 0xFAEF0CDA, 0x086ED80A, 0xD80AFEAF, + 0xF98F0D2E, 0x800141C3, 0x080A6800, 0x206FFA2F, + 0xE8880043, 0x031B41C3, 0x0CB60000, 0xD80AFAEF, + 0xFC0F0FCE, 0x43204200, 0x031C41C3, 0x0CA20001, + 0xD80AFAEF, 0xF98F0CFA, 0x000046CB, 0x45CB3420, + 0x34D80000, 0x13650E37, 0x41C3D80A, 0x0001031D, + 0xFAEF0C7E, 0x700C42A1, 0xFA2F0872, 0x460841A1, + 0x031E41C3, 0x0C6A0000, 0xD80AFAEF, 0x40A1D941, + 0xF9EF0FA2, 0x60DDB90A, 0x41C3F017, 0x0001031F, + 0xFAEF0C4E, 0x700C42C1, 0xF9EF0F8A, 0xD91941C1, + 0xB9154508, 0xFAEF0C3A, 0xD941D80A, 0x082E40C1, + 0xB90AFA2F, 0xED88651D, 0x032141C3, 0x0C220000, + 0xD80AFAEF, 0xFC0F0F3A, 0x800045CB, 0x85400448, + 0x0003223D, 0x223D8541, 0x71500040, 0x00C120CA, + 0x0F1EE885, 0xA521FC0F, 0x0F16A500, 0x4200FC0F, + 0x41C34320, 0x00010322, 0xFAEF0BE6, 0x1600D80A, + 0x80007080, 0x082F0004, 0x8501015E, 0x70148520, + 0x0F81213C, 0xF42C0001, 0xE98D79C0, 0x032341C3, + 0x0BBE0000, 0xD80AFAEF, 0x700CD9C9, 0xF8AF08BA, + 0xC6C4B912, 0x4010C2E8, 0x085AD80F, 0xD90FFA2F, + 0x0EAAD80F, 0x712CF92F, 0x800046CB, 0x8EA01222, + 0x1280255F, 0x0F8F2000, 0x4DFC8001, 0x085F8E01, + 0x40C30344, 0x12D98000, 0x084D8800, 0x79AF036E, + 0x00A00D02, 0x2D404002, 0x244A138B, 0x708D7280, + 0x20A8706C, 0x082B0680, 0x240500EE, 0x210512C1, + 0x90040F82, 0x210502DC, 0x90040F81, 0x924002E0, + 0x213D9120, 0x793B0081, 0x67796949, 0x2480A940, + 0x71641010, 0x71A5E70A, 0xC6C8F1D2, 0x084EC2E2, + 0x45080220, 0x1600E888, 0x80007080, 0x0811000B, + 0x40A100BF, 0x0220091E, 0xC6C240A1, 0xFCEF0FC2, + 0xC6C2702C, 0x1600C2E6, 0x8000708E, 0x47280008, + 0xF8EF0CCE, 0x700C4508, 0x744CD907, 0x708C706C, + 0x0E3A70AC, 0x70CCF92F, 0x10802678, 0x08DA781B, + 0x68C2F96F, 0x700CEF11, 0x724CD907, 0x708C706C, + 0x0E1A70AC, 0x74CCF92F, 0x752C704C, 0x238A4040, + 0xB8950004, 0x704CF01B, 0x4040752C, 0x0004238A, + 0x708CB895, 0x0DF645A1, 0x70CCF92F, 0xD92B74ED, + 0x42C1BF98, 0x706C40E1, 0x45A1708C, 0xF92F0DDE, + 0x40E170CC, 0x42C1D92B, 0x708C706C, 0x0DCE45A1, + 0x70CCF92F, 0xD92BD841, 0x42C1B812, 0x708C706C, + 0x0DBA45A1, 0x70CCF92F, 0xD907700C, 0x706C744C, + 0x70AC708C, 0xF92F0DA6, 0x0280264A, 0xD907706C, + 0x744C4060, 0x708CB88F, 0x0D9270AC, 0x70CCF92F, + 0xD907700C, 0x706CDA08, 0x70AC708C, 0xF92F0D7E, + 0x080E70CC, 0x700CF94F, 0x744CD907, 0x708C706C, + 0x0D6A70AC, 0x70CCF92F, 0x78E0C6C6, 0x2482C3F0, + 0x42103403, 0x38002455, 0x702C4330, 0xF86F0A12, + 0x40C3DA50, 0xF0B00000, 0xB415448B, 0x73044899, + 0xB409B42F, 0x0A812057, 0x000040C3, 0x1C66FF74, + 0x21573004, 0x1C5A09C0, 0xB86E3004, 0x30041C42, + 0xB41BB863, 0x000140C3, 0xC049F0BA, 0x710C686E, + 0xB88EDA07, 0x30841C5C, 0x30841C44, 0xB45C71AD, + 0x03422342, 0x40C3B408, 0xFFB50001, 0x2080C043, + 0xC2400339, 0x1C6ADA40, 0x20403084, 0xC05B0802, + 0x6843C258, 0xB4237704, 0x41C3C04F, 0xFE030000, + 0x70801600, 0x00088000, 0x00802079, 0x30441C4E, + 0x30041C40, 0xB41D702C, 0xC255B802, 0x000742C3, + 0xB417F004, 0xB42EC808, 0xB425B42B, 0x30441C70, + 0x30441C64, 0x30441C5E, 0x30441C58, 0x30441C52, + 0x30441C4C, 0x6B4BC252, 0x30441C46, 0x2005B43A, + 0x000E0F81, 0xC15EF00B, 0x09412254, 0xC3467825, + 0x30041C72, 0xC24CB830, 0x1C74702C, 0x700C3004, + 0x706C704C, 0xB4B0B4B6, 0xB4A4B4AA, 0x33441C68, + 0x33441C50, 0xB4B1B4B4, 0x30851C04, 0x30851C7C, + 0xFCEF0A7E, 0x33441C76, 0x000042C3, 0x700C5555, + 0x4340722C, 0x09E24440, 0x4540FCEF, 0x094EC080, + 0xD97E0260, 0x0D6ED80F, 0xD90FF9EF, 0x900741D3, + 0x1900F804, 0x47CB2105, 0x12228000, 0x6832C808, + 0x2105D880, 0x90070F82, 0xB200FC48, 0x0F822105, + 0xFC4C9007, 0x2105B200, 0x90070F82, 0xB200FC40, + 0x0F822105, 0xFC449007, 0x2D00B200, 0xB8021480, + 0x200F8F40, 0x8F01048E, 0x00A4082B, 0xBA0E7842, + 0x240A7104, 0x20A87000, 0x210503C0, 0x72C30080, + 0x40000000, 0x0F802005, 0x057C9004, 0xBB8A9060, + 0x0C62B060, 0x09DEFC0F, 0x242F0000, 0xD8552387, + 0x704CD955, 0x0E5E706C, 0x240A0060, 0x40820500, + 0xFFEF0D26, 0xD860702C, 0xF92F0B22, 0x208A712C, + 0x40D30FC7, 0xC2CC9007, 0x20041800, 0x20041804, + 0x71001600, 0x02C09004, 0x0C002045, 0xA00418F4, + 0xA34418F8, 0x8F008F81, 0x10240C43, 0x2840D9AC, + 0x244A0388, 0x706D7240, 0x20A8704C, 0x0B1305C0, + 0x20002031, 0x111C0681, 0x0A190081, 0x20050040, + 0x210512C1, 0x90040F81, 0x916001D0, 0xB160E320, + 0x10102380, 0x71047144, 0x46CBF1E0, 0x01068000, + 0xD8538E40, 0x0DCE4340, 0x240A0060, 0x8E000500, + 0x8FA0E81C, 0x08258F01, 0x8E000344, 0x00A00916, + 0x2D4079AF, 0x21051381, 0x90040F81, 0xB1003830, + 0x75108F01, 0xF7B371A5, 0x0FC7218A, 0x900740C3, + 0x1800F834, 0xB0220005, 0x0C5E4082, 0x712CFFEF, + 0x000042C3, 0x700CAC53, 0x4340722C, 0x085A4440, + 0x4540FCEF, 0x0BEED80F, 0xD90FF9EF, 0xDD2870CD, + 0x0A3AD808, 0x712CF92F, 0x108B1701, 0x0B578F00, + 0xD90F1024, 0x03892840, 0x7240244A, 0x708D700D, + 0x07C020A8, 0x20310B11, 0x06812000, 0x0081111C, + 0x10400C29, 0x12412005, 0x210570CD, 0x90040F82, + 0x210502DC, 0x90040F81, 0x924001D0, 0xEA069160, + 0x08032354, 0xB1604648, 0x10102080, 0x71047185, + 0x0B82F1D7, 0xD80FF9EF, 0x133F258C, 0x10002678, + 0x02DD41C3, 0x0BC20001, 0x4242F86F, 0x38002455, + 0x0F9E712C, 0x704CFFAF, 0x0ABE4042, 0x712CFA2F, + 0x0F002054, 0x38012455, 0x706C714C, 0x70AC708C, + 0x0260081E, 0x40C34588, 0xF8309007, 0x73441E00, + 0xC29C9007, 0xA34418F8, 0x73441E00, 0x0004901C, + 0x23441900, 0xB0A2B0A0, 0x0020080A, 0xC7D0B0A4, + 0xD820C2E2, 0x900B45CB, 0x09EEC280, 0x1D00FE6F, + 0x1D001045, 0xC6C21005, 0x1CFCC2FA, 0x2482B6C8, + 0x41DB3002, 0xC17C9007, 0x901C43D3, 0x190004A8, + 0x42103005, 0x20551B5C, 0xC8084338, 0x800041C3, + 0xDA6C04B8, 0x71AD702E, 0x2005B802, 0x180004C0, + 0x0E160045, 0xC085F82F, 0x702C700C, 0x0FA2704C, + 0x706CFCAF, 0x722C700C, 0x706C704C, 0x0F0A708C, + 0x70ACFCAF, 0x0E76C085, 0xD96C0220, 0xFACF0BC2, + 0x0A92D80F, 0xD90FF9EF, 0xFF8F0B1A, 0x40C3D90A, + 0x4E748001, 0x00200E8A, 0x40024010, 0x09AAD90A, + 0x704CF96F, 0xD90A4002, 0xFDEF0B8A, 0x4002DA59, + 0x00200E6E, 0x4002D92E, 0x098ED92E, 0x704CF96F, + 0x0E5E4002, 0xD9120020, 0xD9124002, 0xF96F097A, + 0x0D1EDAEF, 0xC0810060, 0x09FEC081, 0xD90AFB6F, + 0x09F6C081, 0xD92EFB6F, 0x09EEC081, 0xD912FB6F, + 0x800047CB, 0x41421220, 0x219F8F00, 0x704C02C1, + 0x0582209F, 0x708CC381, 0x2D006119, 0xB8021480, + 0x200F7102, 0x6D12048D, 0x7E0F78A5, 0x087E40C1, + 0x40D90220, 0x0F824002, 0xD90AFFAF, 0x0F7A4002, + 0xD912FFAF, 0x0F724002, 0xD92EFFAF, 0x700C7DAF, + 0x704C702C, 0x0B4E706C, 0x44A10060, 0x098A710C, + 0x712C0060, 0x0CB640A1, 0x702C01E0, 0x02D341C3, + 0x0CFE0000, 0x740CFAAF, 0x0802D860, 0x712CF92F, + 0xFC8F0B6E, 0x8F228F03, 0x00640829, 0x68417822, + 0x03802940, 0x7080240A, 0x030020A8, 0x0F812005, + 0x01D09004, 0x70C39140, 0x40000000, 0xB140BAC5, + 0x712C700C, 0xF8EF0FC6, 0x3FC11C00, 0x0966D80F, + 0xD90FF9EF, 0x0C5640A1, 0x712C01E0, 0x0FC7208A, + 0x900746CB, 0xB600C2CC, 0xB602D9B5, 0x1EF8D881, + 0xD8309004, 0x1EF4B912, 0x0C869004, 0x740CFAAF, + 0x40A1DDFF, 0x461045B1, 0x700C44B1, 0xF8EF0F7E, + 0x8F03712C, 0x08618F22, 0x70EE0064, 0x29407822, + 0x7104038C, 0x7000240A, 0x07C020A8, 0x2405C280, + 0x90041F80, 0x900002DC, 0x2079623A, 0x8A000003, + 0x7865781B, 0x2053AA00, 0x240580BE, 0x90041F80, + 0x904001D0, 0x2254F205, 0x71EE0802, 0x7124B040, + 0x000074C3, 0x14034000, 0xC5203096, 0x30951402, + 0x30941401, 0x08BED80F, 0xD90FF9EF, 0x41C3740C, + 0x000402D5, 0x438242A1, 0x0540240A, 0xFAAF0BF2, + 0x0580250A, 0x090B7126, 0x0F732E15, 0x41C3A011, + 0x000002D7, 0xF86F08E2, 0x20002778, 0x740CD95B, + 0xFAAF0BCE, 0x8F03B913, 0x082D8F22, 0x78220064, + 0x29406841, 0x240A0380, 0x20A87080, 0x20050380, + 0x90040F81, 0x914001D0, 0x000070C3, 0x22554000, + 0xB1400802, 0xB6A070AD, 0x0A16B6A2, 0x1EF4FCAF, + 0x700C9344, 0x00200D42, 0xD881712C, 0x02D941C3, + 0x1EF80000, 0x0B7A9004, 0x740CFAAF, 0x0E7ED840, + 0x712CF8EF, 0x712C4063, 0xFFAF0C56, 0x8F23724C, + 0x09238F02, 0x79020024, 0x240A7124, 0x20A87040, + 0x23F402C0, 0x23143001, 0x21803002, 0x7104003E, + 0x4042B220, 0xF9EF0F52, 0x48C8712C, 0x7825C808, + 0x714C4163, 0x708C706C, 0x02200CB6, 0xD92071AC, + 0x900740C3, 0xB0A0C29C, 0x22C1229F, 0x804418EC, + 0x834418EC, 0x73441E00, 0xC164900B, 0x93441EF8, + 0x30451900, 0xB802C808, 0x04C12005, 0xFFEF0C96, + 0x8F00B1A0, 0x209F704C, 0xC3810582, 0x7042708C, + 0x04012000, 0x01E00E16, 0xCA004003, 0x10250D31, + 0x138C2D40, 0x7240244A, 0x702C704C, 0x038020A8, + 0x2405716C, 0x7B381080, 0x0F802005, 0x02F89004, + 0x00102280, 0xB0607124, 0xF1E971A5, 0x30022480, + 0x341B1404, 0x78E0C6DA, 0x4408C0F1, 0x2084880B, + 0xAC0B01C2, 0xB8A38C01, 0x1600AC01, 0x800070C0, + 0x080F000D, 0x8C130012, 0x03002046, 0x0A8EAC13, + 0xE808F88F, 0xB8858C0D, 0x8C03AC0D, 0xAC03B887, + 0xF98F0D4A, 0x8C15E807, 0xAC15B8A5, 0xB8868C03, + 0xD840AC03, 0x10831C14, 0x8C0DAC10, 0xAC0DB8A4, + 0x20458C11, 0xAC110E00, 0x206C8C12, 0xAC120080, + 0x20448C1C, 0xAC1C0300, 0x10801429, 0xC0D1B8C4, + 0x1C297FE0, 0x78E01002, 0x40C3C5E1, 0x04988000, + 0xE9328820, 0xA840704C, 0x0A5DCA00, 0x2A400025, + 0x244A0381, 0x706C7240, 0x090020A8, 0x00802216, + 0x20006078, 0x80010F8D, 0x6B124FA0, 0x20057825, + 0x90040F80, 0x90800200, 0x0B13AD80, 0xB0600231, + 0x22008D80, 0x181C0680, 0x2B400302, 0x718D0280, + 0x7C787825, 0x20057164, 0x90040F80, 0xB08002F8, + 0xF1D47144, 0x78E0C4C2, 0xC1A2C3E6, 0x900042C3, + 0x92800184, 0x903841C3, 0x246C0184, 0x91601140, + 0x236CB200, 0xB1000140, 0x9202722D, 0xB8C891A2, + 0x704CB280, 0x44CBBDC8, 0x05A48000, 0xC241B160, + 0xB1014183, 0xC808B1A0, 0x10832415, 0x30062440, + 0x70AD720D, 0xF41C7AAB, 0x13412415, 0x7E0583C1, + 0x79C58123, 0x2105B902, 0x90030F8E, 0xB99CC000, + 0x91E0B99F, 0x134124F4, 0xC1817F26, 0x034B21F4, + 0x008126F4, 0x02C12900, 0xB62079E5, 0x193F208D, + 0x218D71AD, 0x714C16FF, 0x2042C805, 0xF20E803C, + 0xD99C700C, 0x028020A8, 0x0F822005, 0x03649004, + 0x000070C3, 0xB2204000, 0x9661468B, 0x41C3740C, + 0x00020071, 0x08EA96A0, 0x42A1FAAF, 0xDC7FC808, + 0x2553BC09, 0x68321202, 0x0F832105, 0x20289024, + 0x21059300, 0x90240F81, 0x7884202C, 0x008D2005, + 0x78849100, 0x7845B3A0, 0x740CB100, 0x007241C3, + 0x08AE0001, 0x9640FAAF, 0x78E0C7C6, 0xDC25C808, + 0x43C3BC9F, 0x12248000, 0x21056832, 0x90070F80, + 0x2105C408, 0x90040F81, 0x91200408, 0x305C1A23, + 0x0F812104, 0xFF9F0000, 0x8C00B020, 0x8B01E818, + 0x082D8B20, 0x78220064, 0x240A7104, 0x20A87000, + 0x29400400, 0x26140380, 0x80007042, 0x2005049C, + 0x90040F80, 0x9000028C, 0xB2007124, 0x70148C1B, + 0x8B037CE0, 0x71108B22, 0x07CD20E0, 0x71047822, + 0x7000240A, 0x03C020A8, 0x03802940, 0x70422614, + 0x049C8000, 0x0F802005, 0x028C9004, 0x71249000, + 0x7EE0B200, 0x45CBC2E8, 0x12228000, 0x40108DC0, + 0x085B8D01, 0x40C30384, 0x12D98000, 0x084B8800, + 0x79CF03AE, 0x0060097E, 0x44084002, 0x2E40C808, + 0x244A1382, 0x68327280, 0x702C7A25, 0x054020A8, + 0x104E0C25, 0x1500265A, 0x20007834, 0x80010F83, + 0x29404E24, 0x78450280, 0x0F802005, 0x03209004, + 0xB3009000, 0x71C57124, 0xC6C8F1D4, 0x706CC808, + 0x6852726D, 0xE808710C, 0x70801600, 0x00258000, + 0xF020E888, 0x70801600, 0x00408000, 0x7CE07014, + 0x7180244A, 0x058020A8, 0x03802B40, 0x800044CB, + 0x784519AC, 0x20057C74, 0x90000F81, 0x912001C0, + 0x0F802005, 0x01B49000, 0x7164B420, 0xB40E9000, + 0x238DDB07, 0x700C16FF, 0x78E07EE0, 0x21006038, + 0x80000F83, 0x88401880, 0x2100AB40, 0x80000F83, + 0x104B18CB, 0xAB400082, 0x0F832100, 0x19168000, + 0x00821096, 0x800071C3, 0xAB401961, 0x008010E1, + 0xA9007FE0, 0x2142EA1E, 0x7CE0803C, 0x064020A8, + 0x04831001, 0x04811001, 0x04821001, 0x7B25B908, + 0x04811001, 0x7945B908, 0x7965B910, 0xB99CB902, + 0x9120B99F, 0x00521801, 0x1801B928, 0xF0200052, + 0x803C2142, 0x072220E8, 0x04831001, 0x04811001, + 0x04821001, 0x7B25B908, 0x04811001, 0x7945B908, + 0x04821001, 0x7965B910, 0x2105B902, 0x90030F83, + 0x1001C000, 0xB9080481, 0xB3207945, 0x78E07EE0, + 0x7915793B, 0x0F802100, 0x04588000, 0xB0407FE0, + 0x40C34100, 0x12DA8000, 0xE8898800, 0x70801600, + 0x00088000, 0x01110807, 0x7FE0793B, 0x78E07830, + 0xE0C04100, 0xD840F704, 0xF0044831, 0x003F2180, + 0x782F7FE0, 0x24056892, 0x90071F80, 0x1800C2D4, + 0x40C30005, 0x12228000, 0x88608841, 0x20E07350, + 0x4A7007CD, 0x7104BB0E, 0x7000240A, 0x030020A8, + 0x10C02405, 0x000073C3, 0x20054000, 0x90040F80, + 0xB02002D4, 0x78E07EE0, 0x0443206F, 0x800042C3, + 0x8820121E, 0x0703219F, 0x810010FE, 0x01031A01, + 0x77046038, 0x00402805, 0xAA007FE0, 0xC1A4C3E4, + 0x800145CB, 0x46084E74, 0x40A17034, 0xF20BD912, + 0xFFCF0E8E, 0xD91240A1, 0xFDAF0B9A, 0x714CDA10, + 0x0806F004, 0x704CFF8F, 0x41C3C808, 0x0504901C, + 0x7825B802, 0xC080B040, 0x00200D36, 0x804519A4, + 0x0A16C080, 0xD912FB2F, 0x702C40A1, 0x43C1C280, + 0x01E00D2A, 0xC7C4708C, 0x70CDC0E6, 0x800042C3, + 0x1E001222, 0x90077384, 0x8AE1FED4, 0x1047232F, + 0x0F638A60, 0x2B4010E4, 0x238C038D, 0xF4169FC3, + 0x1F822505, 0x3ED49004, 0x023F091D, 0x2300B200, + 0x121C0682, 0xBA0A0082, 0x25057D45, 0x90041F82, + 0xB2C002D4, 0xF1E77164, 0x4028702D, 0x08F9704C, + 0x0AF59010, 0x202F8275, 0xF7499202, 0x124C2505, + 0x1F8C2405, 0x02D49004, 0x2180B400, 0x71441010, + 0xC4C6F1EF, 0x0FB2C2E2, 0x4408F92F, 0x1843256F, + 0x09679520, 0x41C30050, 0x12218000, 0x800043C3, + 0x0C1B0458, 0x894010F1, 0x15307B55, 0x93401081, + 0x9321E909, 0x00422208, 0x2450F005, 0x79551001, + 0x621B6172, 0x6852C808, 0x0F802205, 0x0034901C, + 0xC805B060, 0x803C2042, 0x700CF20D, 0x02C020A8, + 0x00012205, 0x000070C3, 0xB9924000, 0xB99FB99C, + 0x0E42B160, 0xC6C2FF8F, 0xC808C2E6, 0x120570AD, + 0x706C3608, 0x1202212F, 0x800046CB, 0x68920458, + 0x02250B51, 0x233DD940, 0xB99F024B, 0x20798900, + 0x23040002, 0x26F4908F, 0xF20613C2, 0x00D10817, + 0xF0079623, 0x808111E5, 0x00D1090B, 0x22089622, + 0x26140042, 0x716413C1, 0xB142B140, 0x13412405, + 0x75C3B992, 0x40000000, 0xB99FB99C, 0xF1DAB140, + 0x96219600, 0xF92F0ED2, 0x000C2108, 0x60985020, + 0x2105B902, 0x901C0F81, 0xB1000034, 0x78E0C6C6, + 0xC1A4C3E6, 0xC0804708, 0x00200B96, 0xC0804528, + 0xFB2F0876, 0x46CBD918, 0x4E748001, 0xD91840C1, + 0x0020096A, 0x78BD42E1, 0x800041C3, 0xB8C01220, + 0x209F8920, 0x704C02C1, 0x0582219F, 0x708CC380, + 0x6D126119, 0x61D978A5, 0x01A00F02, 0xC7C6780F, + 0x4528C2E4, 0xF86F0D9A, 0x700C4608, 0x724C762C, + 0x244A43C1, 0x45A10780, 0xF8AF0F02, 0x700C70CC, + 0x09EED922, 0x704CF8EF, 0x0EA2700C, 0x712CF8AF, + 0x78E0C6C4, 0x900742C3, 0xB200C2E4, 0xB2227FE0, + 0xC1A4C3E8, 0xC0804010, 0x0B064548, 0x47280020, + 0xAFC3208C, 0x800146CB, 0xF20C4E74, 0x28C02054, + 0xC080790F, 0xFAEF0FD2, 0x40C14030, 0xF02C4102, + 0x0FC6C080, 0xD946FAEF, 0x0FBEC080, 0xD947FAEF, + 0x0FB6C080, 0xD948FAEF, 0x0FAEC080, 0xD949FAEF, + 0x0FA6C080, 0xD94AFAEF, 0xD94640C1, 0x0020089E, + 0x40C142E1, 0x0896D947, 0x42E10020, 0xD94840C1, + 0x0020088A, 0x40C142E1, 0x0882D949, 0x42E10020, + 0xD94A40C1, 0x00200876, 0x79BD42E1, 0x800040C3, + 0x88001220, 0x209FB9C0, 0x704C0582, 0x02C1219F, + 0x708CC380, 0x6D126119, 0x61D978A5, 0x01A00E0E, + 0xC7C8780F, 0xDB1FC0F1, 0xC8084100, 0x2085BB0B, + 0xDA0B08C1, 0x0AEA708C, 0x4128FC2F, 0xC8084600, + 0x09012085, 0xDA0B4121, 0xFC2F0AD6, 0xC0D1718C, + 0x40C07FE0, 0xC8084100, 0x08C12085, 0x238ADA09, + 0x02BD0008, 0x708CFC2F, 0x184B6038, 0xA8400082, + 0x00821896, 0x18E17FE0, 0x78E00082, 0x45CBC2E2, + 0x04588000, 0x0FA2E806, 0x700CFFEF, 0xC6C2B504, + 0xFFEF0F96, 0xC6C29504, 0x4528C2E4, 0xF86F0C32, + 0x700C4608, 0x724C762C, 0x248A43C1, 0x45A10141, + 0xF8AF0D9A, 0x700C70CC, 0x0886D922, 0x704CF8EF, + 0x0D3A700C, 0x712CF8AF, 0x78E0C6C4, 0xDD25C2E2, + 0x901C41C3, 0xBD9F01C8, 0x1480151B, 0x15C6B100, + 0x0BD29480, 0xB102FF6F, 0x08359500, 0x00000F84, + 0xC8080C81, 0x40C36852, 0x0C50902C, 0x22059020, + 0x90240F8C, 0x9062201C, 0x71046917, 0xB4006B37, + 0x0F802205, 0x20209024, 0xB0207124, 0x78E0C6C2, + 0x4588C2EA, 0x47484668, 0x0BA64030, 0x4110F86F, + 0x800140C3, 0x88604E88, 0xBBC5700C, 0xDA22762C, + 0x0500244A, 0x0D0645A1, 0x70CCF8AF, 0x762C700C, + 0x4322DA22, 0x0840244A, 0x0CF245A1, 0x70CCF8AF, + 0x700CDA22, 0x4302762C, 0x45A14440, 0xF8AF0CDE, + 0x700C70CC, 0xDA22762C, 0x244A43E1, 0x45A107C0, + 0xF8AF0CCA, 0x700C70CC, 0xDA22762C, 0x244A43C1, + 0x45A10800, 0xF8AF0CB6, 0x700C70CC, 0xF8AF0C5E, + 0xC6CA712C, 0xD925C2E6, 0x8900B99F, 0x7F0589FB, + 0x000540C3, 0x0D6ECC60, 0x752CFDEF, 0xFE2F0CD6, + 0x0B0E4608, 0xBFC1F84F, 0xD90C700C, 0x706CDA20, + 0x45E1708C, 0xF8AF0C76, 0x40C370CC, 0x1D4C0000, + 0xFDEF0D42, 0x60DD722C, 0x262F700C, 0xD9070347, + 0x706C704C, 0x0C56708C, 0x70ACF8AF, 0x920D2D41, + 0x700CF20D, 0x704CD907, 0x708C706C, 0x0C3E70AC, + 0x268AF8AF, 0x258C0FC3, 0x700C1DFF, 0x744CD910, + 0x708C706C, 0x0C2645E1, 0x70CCF8AF, 0x0387262F, + 0xD907700C, 0x706C704C, 0x0C12708C, 0x70ACF8AF, + 0x920D2E41, 0x700CF20D, 0x704CD907, 0x708C706C, + 0x0BFA70AC, 0x268AF8AF, 0x258C0FC3, 0xD8801DFF, + 0x704CD907, 0x708C706C, 0x0BE270AC, 0x70CCF8AF, + 0x0B8A700C, 0x712CF8AF, 0x78E0C6C6, 0xA023772C, + 0xA021A022, 0xA0207FE0, 0x4628C2E4, 0x21534508, + 0x710C0142, 0xF7EF0C1A, 0xBE23702C, 0x16022644, + 0x8540655D, 0xA5007845, 0x78258501, 0xC6C4A501, + 0x700CC0F1, 0x0E8AD910, 0x714CF8AF, 0x702CD810, + 0xF8AF0E7E, 0x700C714C, 0x0E76D90A, 0x714CF8AF, + 0x7EE0C0D1, 0x752C700C, 0xF8AF0665, 0x78E0714C, + 0x0FAAC0F1, 0x208AF8AF, 0x40C30B04, 0x04888000, + 0xF8AF0FAA, 0x710C9000, 0x1E00702C, 0x901C7004, + 0x0B2204C4, 0x700CF8AF, 0x000040C3, 0x0C06C350, + 0xD90FFDEF, 0x7EE0C0D1, 0x901C41C3, 0x190004C4, + 0x11C00005, 0xE87F8100, 0x800519BC, 0x000040C3, + 0x03E11388, 0x702CFDEF, 0x4030C2F0, 0x41004508, + 0x800040C3, 0x88C01220, 0x02C1219F, 0x47CB40C1, + 0x4E758001, 0x0582209F, 0x67386119, 0x710C882F, + 0x080F78B8, 0xB8022030, 0x00D4216C, 0x2145F003, + 0x095E0154, 0x200FF86F, 0x087B0351, 0x40822030, + 0x12C1259F, 0x1582269F, 0x01012085, 0x2447222F, + 0x700C7B0F, 0xDA22762C, 0x0400244A, 0x250A65DD, + 0x67BE0480, 0x13D32532, 0x10901613, 0xF8AF0A9E, + 0x234470CC, 0xF20CA213, 0x700C65EB, 0xDA22762C, + 0x250A718C, 0x0A860480, 0x70CCF8AF, 0x20D02053, + 0x20B1080D, 0x08F87076, 0xF00DF841, 0x700C8E73, + 0xDA22762C, 0x0500244A, 0x0480250A, 0xF8AF0A5E, + 0x244F70CC, 0x252F2183, 0x7B6F0447, 0x762CD880, + 0x244ADA22, 0x0A460400, 0x70CCF8AF, 0x09EE700C, + 0x712CF8AF, 0x71001600, 0x00068000, 0x000070D3, + 0x41C3257F, 0x57300005, 0x000340C3, 0x20CAD090, + 0x0AE2004D, 0x702CFDEF, 0x78E0C6D0, 0x88945020, + 0x69528801, 0x0F812205, 0xC054900F, 0x00C0206D, + 0x0F832205, 0xC02C903B, 0x2205B100, 0x90070F81, + 0x2444C1F0, 0xBCC11300, 0x2478B100, 0x783B1001, + 0x2205B300, 0x90070F80, 0x7FE0C3EC, 0x78E0B020, + 0x215FC0E4, 0x44CB0A03, 0x113A8000, 0x647970CD, + 0x63959141, 0x0E237D04, 0x231510A5, 0x61990381, + 0x08139123, 0x79DB006E, 0x00412314, 0x91226199, + 0x71C57D25, 0x40A1F1F1, 0x78E0C4C4, 0x901C44CB, + 0x16000004, 0x90047102, 0x94203804, 0x900743C3, + 0xBAA0F804, 0x7A05B9A0, 0xB3407825, 0x7FE0B400, + 0x00051B04, 0xE81EC2E2, 0x740CD9BF, 0xFA2F0E02, + 0x700CB912, 0xD92572AD, 0x8940B99F, 0x7A25893B, + 0x7918712C, 0x210FB902, 0x794B0001, 0x09FAF206, + 0x712CF9AF, 0xFB8F091A, 0x1BFF258D, 0xC6C2710C, + 0x02FB41C3, 0x0DCA0000, 0xD80AFA2F, 0x1A43256F, + 0xFC2F0E5A, 0x14051D00, 0x081ED807, 0x1A060020, + 0xD8103043, 0x30031A06, 0xB500B88F, 0xFEAF0B3E, + 0xC6C2740C, 0xC1B6C3F6, 0xD8404608, 0x1000B89F, + 0x0ABA0095, 0x10E50160, 0x70148092, 0x20CAD80C, + 0x267C01A2, 0x1A0B1393, 0x2E013002, 0x00007380, + 0x20443679, 0x0E150051, 0x230411F1, 0x16002453, + 0x80007080, 0xE88D0161, 0x73146E0B, 0x000D0212, + 0x70801600, 0x01608000, 0x02067014, 0x0DC20001, + 0x712CF8EF, 0x23524708, 0x26792001, 0x782B11C0, + 0x708EDDFF, 0x0D46F407, 0xE805F80F, 0x1FC7258A, + 0x088A718E, 0x730CFAEF, 0x08336E0B, 0x26790135, + 0x26791141, 0x200410C0, 0x6E0D0050, 0x00B5082D, + 0x09A6702C, 0x70140140, 0x70801600, 0x01818000, + 0x21CA742C, 0xE88F01E2, 0xE687F00F, 0xE68CF2E5, + 0x00E10B50, 0xF00E40A1, 0x70801600, 0x01828000, + 0x1A0BE803, 0x78F03002, 0x430242A1, 0xFD8F0A96, + 0x1381267D, 0x20002178, 0x24952505, 0x00122105, + 0x70EE70AD, 0x800040D3, 0x72F61220, 0x00260124, + 0xA5C02511, 0x40E2F28B, 0x08AE4162, 0x1801F9AF, + 0x08B22342, 0x4610FBAF, 0x702CC082, 0xF7AF0CA2, + 0x0FEADA50, 0x730CFAAF, 0x13950ED3, 0x03802025, + 0xF024F019, 0xF063F027, 0xF061F061, 0xF05FF05F, + 0xF037F025, 0xF042F004, 0xF002F059, 0x79F078AF, + 0x0AF64282, 0x43C10020, 0x13500E9B, 0x12D00E8B, + 0x78AFF04D, 0xFF6F0DF6, 0x700CC182, 0xF8EF0D8A, + 0x710C712C, 0xF027712C, 0x08EE78AF, 0xC18201E0, + 0x08E2F03D, 0x78AF01E0, 0x78AFF039, 0x714CC180, + 0x0B52706C, 0x4110FBAF, 0xC1804022, 0x716C714C, + 0x30011C04, 0xFBAF0B3E, 0x30011C00, 0x78AFF027, + 0xFF6F09EE, 0x700C4182, 0xF8EF0D3E, 0x710C702C, + 0x0D36702C, 0xF01BF8CF, 0x70801600, 0x00098000, + 0x78AFB8E3, 0x0CFEF404, 0xF0070040, 0x428279F0, + 0x00200A66, 0x1600DB0B, 0x80007080, 0x080F017C, + 0xCC22001E, 0x1A227104, 0x730C301C, 0xFAAF0F0E, + 0x20031800, 0xE88BCA0A, 0x70811600, 0x00048000, + 0x40427BAF, 0xFA6F0EB6, 0x71A542C2, 0xF16F71E6, + 0x12D00E0B, 0x13500E13, 0x1600F00E, 0x80007080, + 0x0815017C, 0x1600001E, 0x80007080, 0xB8E60001, + 0xF8C20A6C, 0x70801600, 0x00018000, 0x0970B8E6, + 0x40C1F8E2, 0x70031E00, 0x000F8000, 0x1600C7D6, + 0x80007080, 0xE8070163, 0xF203E68D, 0x05F2E68A, + 0x1600FFC1, 0x80007080, 0xB8E20001, 0x05EB70ED, + 0x27CAFFEF, 0x0E4E13E1, 0x2079F90F, 0x28400000, + 0x16000256, 0x80007080, 0xE8040183, 0x30021A0B, + 0x23562605, 0xBD9FDDF4, 0x08338D00, 0x085A005F, + 0xE8150140, 0x02DF41C3, 0x0AE60000, 0x740CFA2F, + 0x10901500, 0x204F702C, 0x42C22040, 0x78F0AD00, + 0xFDAF08A2, 0x1D00726C, 0x78F01402, 0x42C2702C, + 0xFFEF05FD, 0x78E0726C, 0xC1A1C3F4, 0x43304550, + 0xFAEF081A, 0x70CD4210, 0x800040D3, 0x22531138, + 0x708E204D, 0x800047CB, 0x0B351220, 0x18002030, + 0x16002382, 0x80007080, 0x0825001B, 0x708E007E, + 0xFCEF0B56, 0x8F404042, 0x750C4410, 0x017741C3, + 0x43420003, 0xFA2F0A6A, 0x0500240A, 0x41624042, + 0x0DD2704C, 0x2578FCEF, 0x71561096, 0x000341C3, + 0xC80808D8, 0x082221D6, 0x8F207825, 0x7825B90C, + 0x016009D2, 0x7DD0D940, 0xE5FF708D, 0x002D00A8, + 0x11C0234A, 0x2005C808, 0x8F000301, 0x7825B80C, + 0x0F802005, 0x00D80003, 0x016009AA, 0x238D41A1, + 0x24561D3F, 0x0EFA180C, 0x40C2FECF, 0x734CC180, + 0x708C4362, 0xF7EF082A, 0x1400702E, 0x25553009, + 0xD8071803, 0x10C82D41, 0x2006BB23, 0x244A034B, + 0x20A871C0, 0x29010900, 0x29401440, 0xB8C02142, + 0x02CC2800, 0x209F8F00, 0x70A20803, 0x70016058, + 0x79858820, 0x2140A820, 0x29012200, 0x71261000, + 0x2800B8C0, 0x8F0002C1, 0x0803209F, 0x621A70A2, + 0x88406278, 0xA8207945, 0x800040C3, 0x88000484, + 0xF1AB661E, 0x7885C808, 0x0F802005, 0xF0D80003, + 0x01600912, 0x238D702C, 0x24561E3F, 0x0E62180C, + 0x4042FECF, 0x085E702C, 0x1800FB2F, 0x40822043, + 0x78E0C7D4, 0x2482C3F8, 0x46503617, 0x47104130, + 0x3F802400, 0x03800000, 0xDA78702C, 0xF7AF0962, + 0x30C01CD4, 0x2400702C, 0x00003F80, 0x09520308, + 0xDA78F7AF, 0x2400702C, 0x00003F80, 0x09420290, + 0xDA78F7AF, 0x300014D4, 0x0819704E, 0x700F02B1, + 0x70981600, 0x000C8000, 0x30012084, 0x31982841, + 0x300514D4, 0x42E2740C, 0x01D641C3, 0x43220005, + 0x0580240A, 0xFA2F08EA, 0x0600260A, 0x702C710C, + 0x05D32800, 0xF96F0CF2, 0x084B40E2, 0x1CD83031, + 0xC0823000, 0xFBEF0FC6, 0x14C841E2, 0x42C33101, + 0x00009038, 0x7905C808, 0x7945B902, 0x216D9120, + 0x14CA0A10, 0x78253101, 0x01D741C3, 0xB8020002, + 0x92007A05, 0x206D4202, 0x740C0A0D, 0xFA2F0892, + 0x14D443A1, 0x2B403000, 0x0F122093, 0x2079FA2F, + 0x1C5A034E, 0x16003018, 0x80007080, 0x206D0009, + 0x70140940, 0x30001CE0, 0x006120CA, 0x30001CE0, + 0x300014D4, 0x03510815, 0xB802C808, 0x0F802005, + 0xC234903B, 0x00451800, 0x0CFE7FDB, 0x230F0120, + 0x1CDC25D4, 0x24003000, 0x00003F80, 0x702C0218, + 0xF7AF084E, 0x45D3DA78, 0x12228000, 0x303008BD, + 0x1E00DA60, 0x90077484, 0x1E00C17C, 0x901C7045, + 0xC80804A8, 0x800041C3, 0xB8020EAB, 0x0F802005, + 0x0504901C, 0x00451800, 0x70C51E00, 0xC164900B, + 0xF76F0FF6, 0x3E402455, 0x3E402455, 0x01A0086E, + 0x710CD960, 0xFFAF0C52, 0x212F712C, 0x700C0507, + 0x09DA704C, 0x4330F9EF, 0xF82F0CF6, 0x43104062, + 0x20801501, 0x20821500, 0x00A408C3, 0x27407842, + 0x6821280C, 0x240AC808, 0x20A87040, 0x2A4007C0, + 0x24000301, 0x00003F83, 0x61990210, 0x79057B54, + 0xB992B902, 0xB99FB99C, 0xB3209120, 0x8005218C, + 0x003C238A, 0x00CD21C0, 0x3F832400, 0x02080000, + 0x71447B54, 0xF03BB320, 0x308714D1, 0x2507232F, + 0x308314CC, 0x3E412455, 0x04C0240A, 0x32052440, + 0x308214CF, 0x0580260A, 0xF9AF0F4A, 0x300014DC, + 0x308714D1, 0x3F812400, 0x01840000, 0x308314CD, + 0x04C0240A, 0x34052440, 0x0580260A, 0x308214CF, + 0xF9AF0FB2, 0x300014DC, 0x36001440, 0x30181C68, + 0x308014E9, 0x710CE80B, 0x34801CEC, 0x1C63B890, + 0x1CF03498, 0x1C643000, 0xBD083018, 0xE70D6E06, + 0x2447212F, 0x33581C5B, 0x22102840, 0x1C5D70AD, + 0x1C5E3018, 0x1C5C33D8, 0x145E3418, 0x75103600, + 0x000604A0, 0x3600145D, 0x790E78A2, 0x300014E0, + 0x00012908, 0xF048262F, 0x7017F4AD, 0x40C3F2AD, + 0x0E9C8000, 0x68346508, 0x212F7825, 0x0C4E0507, + 0x780FFFAF, 0xF86F0E36, 0x0E42D8C8, 0x202FF86F, + 0x150104C8, 0x1C602081, 0x15003498, 0x09352080, + 0x1C5F0024, 0x79023498, 0x240A7124, 0x20A87040, + 0x28400480, 0x21050381, 0x90040F82, 0x24003DD0, + 0x00003F81, 0x21F40208, 0x71040001, 0xB220E120, + 0xFECF0B92, 0x0AFED80F, 0xD90FF92F, 0x0086208A, + 0x900746CB, 0xB600C2C4, 0x096AD840, 0x712CF86F, + 0x20811501, 0x20801500, 0x00240931, 0x71247902, + 0x7040240A, 0x048020A8, 0x03812840, 0x3F832400, + 0x017C0000, 0x21057B14, 0x90040F82, 0x922001D0, + 0xB3207104, 0xB220E120, 0xFECF0B3A, 0x0AA6D80F, + 0xD90FF92F, 0x712CD882, 0x091AB600, 0xD840F86F, + 0x208E1500, 0x20801501, 0x03A40877, 0x0DAA78AF, + 0x4010F9CF, 0x13802E40, 0x0F8F2005, 0x01D09004, + 0x3F802400, 0x017C0000, 0x20F49720, 0x78220380, + 0x88012054, 0x0023000E, 0x26024420, 0x00007001, + 0xD840FFC0, 0x483142C1, 0x3F802400, 0x02180000, + 0x430278B6, 0xB02078D4, 0x01DC41C3, 0x0D820003, + 0x740CF9EF, 0x3F802400, 0x02100000, 0x038020F4, + 0x1501B700, 0x76102080, 0xFFE5079C, 0x0AA671C5, + 0x71A5FECF, 0x702CF143, 0x3F802400, 0x05880000, + 0xF76F0D6E, 0x702CDA50, 0x3F802400, 0x05380000, + 0xF76F0D5E, 0x702CDA50, 0x3F802400, 0x04E80000, + 0xF76F0D4E, 0x702CDA50, 0x3F802400, 0x04980000, + 0xF76F0D3E, 0x702CDA50, 0x3F802400, 0x04480000, + 0xF76F0D2E, 0x702CDA50, 0x3F802400, 0x03F80000, + 0xF76F0D1E, 0x14D4DA50, 0x08773000, 0x6D340371, + 0x3600145B, 0x254E7905, 0x20051300, 0x145C004B, + 0x78103601, 0xB80479A5, 0x36091208, 0x15007825, + 0x7E3B2081, 0x43C3710D, 0x00009038, 0x034F2940, + 0x20811501, 0x10482014, 0x13A40857, 0x124C2705, + 0x310214C8, 0x10082796, 0x14D871C5, 0x61593001, + 0xB9027985, 0xB1007965, 0x310214CA, 0x300114D8, + 0x79856159, 0x7965B902, 0x02C41900, 0x40C3F1E6, + 0x0E9C8000, 0x14D46508, 0x68343002, 0x212F7825, + 0x0A190507, 0x780F02B1, 0xFF8F0A12, 0x0886F003, + 0x268AFB4F, 0xF0051FC7, 0xFF8F089A, 0x14CCDE7F, + 0x24553081, 0xC2823E40, 0xF9AF0B56, 0x3E4F2455, + 0x300014DC, 0x14CCE825, 0x42E23081, 0x2440C382, + 0x14CF3604, 0x250A3080, 0x70CC0580, 0xC74170EC, + 0xFBAF0CEE, 0x2455C640, 0x41E23E40, 0x2400704C, + 0x00003F84, 0x24000588, 0x00003F85, 0x24000538, + 0x00003F86, 0x09BE04E8, 0xC386FBEF, 0x081AF024, + 0x14D00200, 0x222F3087, 0x14CC0507, 0x43223081, + 0x3604145A, 0x32052440, 0x308014CF, 0x0580260A, + 0xF9AF0FB6, 0x2400C740, 0x00003F81, 0x24000588, + 0x00003F82, 0x24000538, 0x00003F83, 0x0C6204E8, + 0xC086FB2F, 0x308114CD, 0x3F802400, 0x01840000, + 0x3F8F2400, 0x01840000, 0xF9AF0AA6, 0x14DCC284, + 0xE8283000, 0x308114CD, 0xC38442E2, 0x38042440, + 0x308014CF, 0x0580250A, 0x71EC70CC, 0x0C42C741, + 0xC640FBAF, 0x240041E2, 0x00003F80, 0x714C0184, + 0x3F842400, 0x04980000, 0x3F852400, 0x04480000, + 0x3F862400, 0x03F80000, 0xFBEF090A, 0xF025C388, + 0x01C00F66, 0x308714D0, 0x0507222F, 0x308114CD, + 0x145A4322, 0x24403604, 0x14CF3405, 0x260A3080, + 0x0F060580, 0xC740F9AF, 0x3F812400, 0x04980000, + 0x3F822400, 0x04480000, 0x3F832400, 0x03F80000, + 0xFB2F0BAE, 0x1501C088, 0x14CE2087, 0x15003084, + 0x74F0208C, 0xFFED058E, 0x245A706D, 0x24001286, + 0x00003F8F, 0x24000308, 0x00003F8E, 0x7FB60380, + 0x7F947EB6, 0x218A7E94, 0xD97F1FC1, 0x11250B6D, + 0x9040210C, 0x20310E11, 0x16802400, 0x0080101C, + 0x10000B55, 0x11882300, 0x3F802400, 0x05380000, + 0x020220F4, 0x3F802400, 0x04E80000, 0x020020F4, + 0x96004853, 0xB6006078, 0x3F802400, 0x04480000, + 0x020220F4, 0x3F802400, 0x03F80000, 0x020020F4, + 0x97407842, 0x7810621A, 0x02492009, 0x20097870, + 0xB7400041, 0xF1CC7165, 0x9700F745, 0x4121B600, + 0xF407F007, 0x96209700, 0x804408F5, 0x2400F1F9, + 0x00003F80, 0x78B60290, 0x71857894, 0xF1A3B020, + 0x30300847, 0x3E402455, 0x74841E00, 0xC164900B, + 0x6832C808, 0x901C40C3, 0x79050504, 0x04841900, + 0x18A4D920, 0x40C38484, 0xC17C9007, 0x00451800, + 0x74841E00, 0xFED49007, 0x005C1886, 0xFF2F0B96, + 0x049C1886, 0x09B2F005, 0x14CCF9AF, 0x15003081, + 0x40C3208F, 0x07070707, 0x30181C5F, 0x20801501, + 0x3F8E2400, 0x017C0000, 0x02507710, 0x41E2002D, + 0x70AD66FE, 0x708E714E, 0x70CE706E, 0x3600145D, + 0x790E78A2, 0x300014E0, 0x00012908, 0xF048262F, + 0x081DF434, 0x42E13030, 0x3F802400, 0x02180000, + 0x20F478B6, 0x210A03D0, 0xF01B2400, 0x3F802400, + 0x03800000, 0x41C378B6, 0x000401E5, 0x20F443A1, + 0x240003D1, 0x00003F80, 0x78B60290, 0x0440250A, + 0x03D020F4, 0x095A740C, 0x240AF9EF, 0x200C0400, + 0xF705A580, 0x0B21F410, 0xAEA02445, 0x260A718E, + 0x230A2400, 0x714E2440, 0x145E71A5, 0x0D813600, + 0xF00D9004, 0x20300C13, 0xA580200C, 0xA4C121CC, + 0x206122C0, 0x708EF3F2, 0x202FF1F0, 0x68290487, + 0x300014E0, 0x8E00790C, 0x783D7914, 0x7D0FAE00, + 0x300014D4, 0xF48AE08D, 0x41C3740C, 0x000301E6, + 0x43A142E1, 0xF9EF08EA, 0x04C0240A, 0x41C3740C, + 0x000201E7, 0x08DA42E1, 0x43A1F9EF, 0x37041222, + 0x01E841C3, 0x202F0003, 0x42E10100, 0x43A178F6, + 0x800170C3, 0xB0A04D44, 0xF9EF08B6, 0x14C8740C, + 0x2F403101, 0x12081348, 0x254E360B, 0x14D81306, + 0x23053000, 0x60381203, 0x3601145C, 0x46CB7865, + 0x00009038, 0x79A5B802, 0x01022E40, 0x7A2578C5, + 0x1F892000, 0x10000000, 0x2305B040, 0x14C8124C, + 0x14D83100, 0x60383001, 0xB8027885, 0xB04078C5, + 0x310014CA, 0x300114D8, 0x6D346038, 0x145B7865, + 0xB8023603, 0x01832305, 0x7B2578C5, 0x14CAB060, + 0x14D83101, 0x60383000, 0xB8027885, 0xB06078C5, + 0x70801600, 0x017C8000, 0x001F08AB, 0x70801600, + 0x00098000, 0x013F089F, 0x15CB2305, 0x903840C3, + 0x23051540, 0xBC02120C, 0x10012405, 0x2305B140, + 0xB9021241, 0x000D2105, 0x08002054, 0x79057C05, + 0xB460B540, 0xF037B160, 0xF9AF0FBE, 0x460840A1, + 0x300014D4, 0x02B1081F, 0x0837740C, 0xD8403030, + 0x01E941C3, 0x20020003, 0x740C04C4, 0x43A142E1, + 0x41C3F017, 0x000301EC, 0x43A142E1, 0xF9AF0FB2, + 0x04C0240A, 0x41C3740C, 0x000201ED, 0x740CF00F, + 0x01EA41C3, 0x42E10003, 0x240A43A1, 0x0F9204C0, + 0x740CF98F, 0x01EB41C3, 0x42E10002, 0xF9AF0F82, + 0x05AD43C1, 0x71E5FFEF, 0x3F802400, 0x017C0000, + 0x016009D2, 0x300214D4, 0x30310897, 0x0B7A40E2, + 0x702CF92F, 0x4210D939, 0x0F56B913, 0x740CF9AF, + 0x20901500, 0x24132240, 0x24922240, 0x1407272F, + 0x20801501, 0x03E40863, 0x13112F40, 0x275F70AD, + 0xC0821501, 0x43A142E1, 0x740C603E, 0x41C37EB4, + 0x000401C9, 0x11051620, 0xF9AF0F16, 0x11041670, + 0x12012D40, 0x2105C808, 0x43C30441, 0x00009004, + 0x71A57825, 0x04812005, 0x04C02005, 0x96306952, + 0xB8027A65, 0x7865B220, 0x11011670, 0x92740DB3, + 0x7106B020, 0x0C1EF1CC, 0x0CC2FE8F, 0xC7D8FF0F, + 0x1CFCC2FA, 0x2482B6C8, 0x40103D06, 0xDA78702C, + 0x3F802400, 0x013C0000, 0xC1504528, 0xC14EC14F, + 0xC14CC14D, 0xC14AC14B, 0xF72F0EC6, 0x2455C149, + 0x702C3C40, 0xF72F0EBA, 0x2455DA78, 0x702C3880, + 0xC548DA3C, 0xF72F0EAA, 0xC093C547, 0x0EA2702C, + 0xDA3CF72F, 0xC552712C, 0x70441E00, 0x04A8901C, + 0xC546C808, 0x6852C545, 0x0F802205, 0x0504901C, + 0x2205B020, 0x90040F80, 0x90000090, 0x0F832205, + 0xC0909007, 0xB888C042, 0x1600B300, 0x80007083, + 0x16000004, 0x80007080, 0x0811017C, 0x2205001E, + 0x903B0F80, 0xB020C234, 0x040E2900, 0x7FCFBBC3, + 0x40E1752C, 0xF9EF0D7E, 0x44D3C343, 0x12228000, + 0x208D1400, 0x35112440, 0x20801401, 0x03640841, + 0x160040E1, 0x80007080, 0x083112D9, 0x4002036E, + 0xFBEF0A12, 0xE81241A1, 0x742C78AF, 0xFEAF0D86, + 0x42004202, 0x23402114, 0x41C343A1, 0x000201A7, + 0x0DCEB040, 0x750CF9AF, 0xF1E071A5, 0xF9EF0D26, + 0x1400762C, 0x706F208D, 0x20801401, 0x0364084D, + 0x16006E12, 0x80007080, 0x083D12D9, 0x4002036E, + 0xFBEF09C2, 0xE81841A1, 0x20F4C085, 0x08290340, + 0x78AF0071, 0x0D2E742C, 0x4202FEAF, 0x750C4708, + 0x41C342E1, 0x000201A8, 0xF9AF0D76, 0x0F0943A1, + 0x716F11D1, 0xF1DA71A5, 0x78CF7E05, 0xF7EF09EE, + 0xC044C040, 0x060640C3, 0xC0510606, 0x2005C808, + 0x14B70400, 0xB8022097, 0x0F802005, 0x15409038, + 0x01181000, 0x1401D80D, 0x2084208F, 0xC041300C, + 0x20831400, 0x35C7212F, 0xDEC0C808, 0x040B2005, + 0x10C40F9B, 0x30EE0993, 0x2B40C591, 0x65690342, + 0x06002105, 0x4E31B904, 0x22057905, 0x284002C0, + 0x22960088, 0x20050008, 0x90381F80, 0xB0201540, + 0x20056568, 0xB8040601, 0x79054E10, 0x02C02205, + 0x42C36892, 0x15809038, 0x1F802405, 0x15409038, + 0x6568B020, 0x06012005, 0x4E10B804, 0x20057905, + 0xB0201080, 0x65687A85, 0x06012005, 0x4E10B804, + 0x702C7825, 0xC08DB200, 0xB0207874, 0x7874C08F, + 0xC08BB020, 0xB0207874, 0x7874C089, 0x30300B0B, + 0x1800B020, 0x71640045, 0x70CDF1B4, 0x1F802632, + 0x0E9C8000, 0x78256834, 0x08BAC100, 0x780FFF6F, + 0xF82F0C0A, 0x0C16D8C8, 0xC004F82F, 0x0F96700C, + 0x712CF7EF, 0x089EC100, 0x700CFF6F, 0x0BB6C000, + 0xD91AF9EF, 0x704E72AE, 0x20100A0F, 0x70801600, + 0x00408000, 0x212FE827, 0x40020480, 0xFBEF0856, + 0x46104130, 0x20532140, 0x41227014, 0x04C121CA, + 0x742C782F, 0xFEAF0BBE, 0xC5924202, 0x75224708, + 0xB5004102, 0xFC2F0D12, 0xE80D4042, 0x23CA70D6, + 0x202F2441, 0x742C04C7, 0xFEAF0B9A, 0x78E54202, + 0x258DB500, 0x714E253F, 0xF9AF0BBE, 0x140078CF, + 0x4110208D, 0x20801401, 0x01347510, 0x2111002D, + 0xF294B340, 0x208F1403, 0x0FEA4002, 0x41A1FBAF, + 0x1342273C, 0x21F4C192, 0x2078008C, 0x781B0000, + 0x38822455, 0x73046862, 0x10C12C01, 0x21447C19, + 0x255A0043, 0xC09313C1, 0x6119623A, 0x61D862DA, + 0x2444AA60, 0xA8401042, 0x78B4C08B, 0x09299020, + 0x438900E0, 0xC08FB060, 0x902078B4, 0xB0806981, + 0x178C255A, 0x3F802400, 0x013C0000, 0x78346098, + 0x04441800, 0x78B4C089, 0x09239020, 0xB0400080, + 0x78B4C08D, 0x69819020, 0x255AB080, 0x2455178C, + 0x60983C40, 0x18007834, 0x0E910444, 0xC18F13B1, + 0x910079B4, 0x0050083D, 0x7074E88F, 0x1783255A, + 0x0E7F208A, 0x3F812400, 0x013C0000, 0x01E120CA, + 0xB1006179, 0xEB8EF00E, 0xB1606861, 0x1783255A, + 0x3F812400, 0x013C0000, 0x79146179, 0x01C51900, + 0x78B4C08D, 0xE9179020, 0x32C22305, 0x16CB2304, + 0x10032378, 0xF41A7A6B, 0x00700931, 0xB0406941, + 0x1782255A, 0x3C402455, 0x78346058, 0x01C51800, + 0x7054F00C, 0x1782255A, 0x0E7F208A, 0x3C412455, + 0x01E120CA, 0xB1006159, 0xF16671A5, 0xE68F71C5, + 0xFFC5061C, 0x41C3750C, 0x000101B4, 0xF9AF0A92, + 0x41C34202, 0x000001B5, 0xF9AF0A86, 0x70AD740C, + 0x0A56DE0F, 0x78AFF9AF, 0x41C34200, 0x000101B6, + 0xF9AF0A6E, 0x268D740C, 0x71A51DFF, 0x01B741C3, + 0x0A5E0000, 0x740CF9AF, 0x20911400, 0x215FC693, + 0x245523CD, 0x66BE3880, 0x1401651D, 0x0F71208F, + 0x740C1464, 0x01B841C3, 0x0A360001, 0x4222F9AF, + 0x42B1DF0F, 0x24821201, 0x01B941C3, 0x0A220001, + 0x740CF9AF, 0x1E3F278C, 0x740CD9DD, 0xF9AF0A12, + 0x740CB911, 0x01BB41C3, 0x0A060001, 0x4222F9AF, + 0x42D1DF0F, 0x24821201, 0x01BC41C3, 0x09F20001, + 0x740CF9AF, 0x1E3F278D, 0x41C3740C, 0x000001BD, + 0xF98F09DE, 0xE50FE60F, 0xF1C97126, 0x208D1400, + 0x13640FAB, 0x42A14FB0, 0x240A7104, 0x20A87000, + 0x096D0E40, 0xC08F30AE, 0x008120F4, 0x00B40925, + 0x0783225A, 0x3F802400, 0x013C0000, 0x20146078, + 0x98800041, 0x814111FE, 0x2C44643C, 0xB0201081, + 0x20F4C08D, 0x2455008C, 0x60783C40, 0x10B40C17, + 0x20149820, 0x14FE030C, 0x6199914C, 0x00812944, + 0x2400B020, 0x00003F8C, 0xC087013C, 0x10C32435, + 0x7854792E, 0x2B44633B, 0xB0200081, 0xC6877144, + 0x091F7EB4, 0x740C336E, 0x11441600, 0x41C34202, + 0x000301C1, 0xF9AF093A, 0x140143A1, 0x72C5208F, + 0x71A575F1, 0x1400F7AF, 0x0F99208D, 0xC1871364, + 0x79B44FB0, 0x240A7104, 0x42A17000, 0x034020A8, + 0x308E0913, 0x080B9900, 0xB8830052, 0x7813F002, + 0x7224B100, 0xF0367144, 0x270479B8, 0x262F2040, + 0xF22DF007, 0x70801600, 0x017C8000, 0xC08FE809, + 0x034020F4, 0xC08DE808, 0x034020F4, 0x2706E804, + 0xF01D2057, 0xC287C191, 0x22F561B9, 0x0A190342, + 0x890001F2, 0x03310815, 0x700C7104, 0x01C241C3, + 0xF00A0001, 0x7704E804, 0xF009A900, 0x41C3700C, + 0x000101C3, 0xF72F0DA2, 0x140142A1, 0x71A5208F, + 0x93650F99, 0xC001712C, 0x262F7704, 0xC041F007, + 0x262FF205, 0x034CF5C7, 0x1600FFC2, 0x80007080, + 0x0895017C, 0x1400001E, 0x0F8D2081, 0xC8081044, + 0x903841CB, 0x160015C0, 0x80007088, 0x200512D9, + 0x4F30040B, 0x240A7104, 0x20A87000, 0x08670D80, + 0xC491106E, 0x034D2940, 0x2205642A, 0x6A740600, + 0x4A76DAC0, 0x25057E05, 0x687212C0, 0x10082596, + 0x02402305, 0x6428B0C0, 0x060E2005, 0x4A10B804, + 0x25057E05, 0x68B212C0, 0x12402505, 0x6428B0C0, + 0x060E2005, 0x4A10B804, 0x21547E05, 0x7B051800, + 0xB3C078A5, 0x2305642B, 0xBB04060C, 0x7A857A62, + 0x7124B040, 0x716E70ED, 0xEF08724E, 0x70801600, + 0x00408000, 0x00100879, 0x40027EFB, 0xFBAF0BE6, + 0xC18741C1, 0x894079D4, 0xE8058922, 0x7D4569B4, + 0x6AB4F003, 0x710C7D25, 0x0B1278F8, 0x780FFA2F, + 0x2347212F, 0x4202750C, 0x01C541C3, 0x43E10003, + 0xF96F0F8E, 0x0440240A, 0x0BCAC100, 0x4022FF2F, + 0x205FC003, 0x60D80B00, 0x70827002, 0x20300815, + 0x0B27A8B6, 0x1E002010, 0x80007342, 0xF00800F7, + 0x20100B21, 0x73421E00, 0x00F28000, 0x228D71ED, + 0x706E2FFE, 0x1E00F00A, 0x80007342, 0xF0060101, + 0x73421E00, 0x00FC8000, 0xFA2F0AA2, 0xC808730C, + 0x2005B802, 0x90070F81, 0xC002C090, 0x2480B100, + 0x14043D06, 0xC6DA341B, 0x1CFCC2FA, 0xC1A5B6C8, + 0x702CC140, 0x0D5AC044, 0xC000F9AF, 0x1443256F, + 0x8D00C043, 0x900747CB, 0x2078C2C0, 0xD90F0100, + 0xE030B802, 0x0B9EB700, 0xD80FF8AF, 0x71AED9FF, + 0x208A700E, 0xB7320FC7, 0x15441F28, 0x94041FDC, + 0xB708B706, 0x15441F04, 0x7054C200, 0x093E711C, + 0x710CFF2F, 0xFACF0ADE, 0x1097150E, 0x720C776E, + 0x800046CB, 0x46D31220, 0x12D98000, 0x34041C0A, + 0x34041C08, 0x8E00C041, 0xD840E803, 0xD825F002, + 0x2D00B89F, 0xB9022401, 0x040D210F, 0x7D0B8800, + 0x40C3F2A1, 0x12DC8000, 0x40028020, 0x0F76C200, + 0xC300FBEF, 0x7DAFC203, 0x0872700C, 0x41A1F96F, + 0xF78F083E, 0x702C700C, 0xF92F0BB2, 0x450842A1, + 0xF7EF0DEA, 0x0DF6D8C8, 0x78B0F7EF, 0x329B2440, + 0x32192440, 0x341B2300, 0x34192100, 0x70AD700F, + 0x6892C808, 0x1F802405, 0xC034901F, 0x8E23B0A0, + 0x09338E02, 0x79020024, 0x20831600, 0x28406941, + 0x240A0381, 0x20A87080, 0x0B1303C0, 0x2405002E, + 0xBA921042, 0xBA9FBA9C, 0x7104B2A0, 0x000071C3, + 0x09864000, 0xD814FD2F, 0xFE8F0F8A, 0x712CC004, + 0xF7EF08EA, 0x8E027810, 0x4110704E, 0x03942840, + 0x083F8E03, 0xD80F0464, 0x20801600, 0x044E0827, + 0x2F802405, 0x02F49004, 0x22059000, 0xE88B2012, + 0x41C3740C, 0x0003024B, 0x43224202, 0xF96F0DA2, + 0x712644A1, 0x2F942400, 0x40000000, 0x0A46F1E2, + 0xD90FF8AF, 0x3011082D, 0x20310A33, 0x15C02500, + 0x7A10702C, 0x0EEE4002, 0x4150FEEF, 0x712C4002, + 0xFEEF0EE2, 0x1B004222, 0x23083342, 0xF0062353, + 0x20110A0B, 0x33421900, 0x71A5710F, 0x98D40D25, + 0x41C34003, 0x00010250, 0xF72F0A4E, 0x0F164202, + 0xC001F90F, 0x7704710E, 0xC0417014, 0x202FF54D, + 0x41C304CA, 0x00000252, 0xF72F0A2E, 0x202FB83F, + 0x43C304C7, 0x01328000, 0x140B70E2, 0x2049308D, + 0xC0220881, 0x140A4832, 0x49103080, 0x00802009, + 0xAB02AB00, 0x6852C808, 0x30801409, 0x0F8C2205, + 0xC034901F, 0x4834B420, 0x200949B0, 0xAB010300, + 0x8E03AB03, 0x08378E62, 0x786200E4, 0x038D2B40, + 0x40C36881, 0x12D98000, 0x240A88C0, 0x20A87300, + 0x0E1303C0, 0x220510EE, 0xB8920340, 0xB89FB89C, + 0x7164B020, 0x000075C3, 0x0E4A4000, 0x700CFE8F, + 0xB708B706, 0xC0A5B702, 0x341B1404, 0x78E0C6DA, + 0x1CFCC2FA, 0xC1BBB6C8, 0x710C4018, 0x01402800, + 0x2140250A, 0x160068B2, 0x80007080, 0x260A0162, + 0x44702100, 0x47304158, 0xB203208C, 0x31801C68, + 0xE899F403, 0xE809F009, 0xBD41208C, 0xBF8220CC, + 0x00700000, 0x2050F20F, 0x204A3080, 0x208C21C0, + 0xF40D8802, 0x70801600, 0x01648000, 0x80802053, + 0x0CAEF205, 0x712CF82F, 0x26424010, 0x250F20C0, + 0x212F1553, 0x08232007, 0x706F0135, 0x40C3790D, + 0x0FA08000, 0x02022040, 0x004D20F4, 0x005222F4, + 0xBB8E736C, 0x736CF006, 0x000045CB, 0x704EFFFF, + 0x44CB710C, 0xFE030000, 0xB60A468B, 0x000041C3, + 0xB604F0B0, 0x1C5C6943, 0x276F3004, 0x1C441443, + 0xB61C3004, 0x6C0AB610, 0x40C3B60F, 0xFFB50001, + 0xB969B629, 0x2258B643, 0xC0400B02, 0x000140C3, + 0x1C4EFE04, 0x24403084, 0xB63B1282, 0xB662489A, + 0x000743C3, 0xC058F004, 0x1C42B864, 0x42C33084, + 0xF0B40001, 0x6B0BC04C, 0x6A0BC049, 0x8F00C046, + 0x01002078, 0xB61AC152, 0xB617B962, 0xE030B802, + 0xB60BC14F, 0xD966C080, 0x33041C5A, 0x31C51C50, + 0x31C51C2C, 0x36C41C2A, 0x36C41C10, 0x1C0AC243, + 0x1C6436C4, 0x1C5E36C4, 0x1C5836C4, 0xC35536C4, + 0x36C41C52, 0x36C41C4C, 0x36C41C46, 0x36C41C40, + 0x36C41C3A, 0x31851C28, 0x30851C22, 0x00E00BAE, + 0x30C51C1C, 0x4142D80F, 0x43424242, 0xFB6F0BD2, + 0x0480240A, 0x722C700C, 0x706C704C, 0x0C1A44A1, + 0x45A1FB6F, 0x14C7262F, 0x12012D41, 0x704C78AF, + 0x0922706C, 0x44C1FF2F, 0x2102217D, 0x0407212F, + 0xFE2F0E96, 0x40C240C1, 0xF8AF0B12, 0x45CB41A2, + 0x4DAC8001, 0x0B2B43B1, 0x212F3135, 0x0C5606C7, + 0x4082FF2F, 0x7280244A, 0x20A8702C, 0x080B0240, + 0x1D00004E, 0x72A515C4, 0x71677124, 0x0F9FF1ED, + 0x46EA2030, 0xB203208C, 0x4082F406, 0x00E00C82, + 0xF010702C, 0xBC01208C, 0x40C2F406, 0x01600846, + 0xF0084182, 0x410340A2, 0x08CE4223, 0x706C0160, + 0xBC01208C, 0x76F2F205, 0xFE610EBC, 0x0EBA4082, + 0x4082FE6F, 0x2A102354, 0x2382222F, 0x456A702E, + 0x21350945, 0x0447212F, 0xFF2F0BDA, 0x704C4082, + 0x02950A2D, 0x008E081D, 0x20832033, 0xE90DC11A, + 0x00520B0B, 0x79C29520, 0x9520B520, 0xB5207142, + 0x714472A5, 0x0BF7F1EE, 0xF1F68013, 0x22902040, + 0xF1E07126, 0xA0310A71, 0x208C464A, 0xF407B203, + 0x0BEE4082, 0x702C00E0, 0x208CF00F, 0xF407BC01, + 0x0FB240C2, 0x41820120, 0x40A2F007, 0x42234103, + 0x01600836, 0x704C706C, 0x900741C3, 0x1924C29C, + 0x706C0015, 0x70841E00, 0xFED49007, 0x708C8F00, + 0x01002078, 0x1904B802, 0xD80F0014, 0xB144B140, + 0x1E00B146, 0x90077084, 0x1E00F804, 0x901F7084, + 0x0A5EC004, 0x702CFB6F, 0x1404C0BB, 0xC6DA341B, + 0x1CFCC2FA, 0xC1BAB6C8, 0x41C34510, 0x000003DD, + 0xF96F097E, 0x730C740C, 0x900741DB, 0x70EEC17C, + 0xF9EF0CDA, 0x30051900, 0xFEEF095E, 0x0D5240A2, + 0x710CF9EF, 0x45CBD840, 0x4E748001, 0xD90BB89F, + 0x10E588E0, 0x0A0A8090, 0x40A1FEEF, 0x0A0240A1, + 0xD911FEEF, 0xD90BC808, 0xB802DAF7, 0x0F802005, + 0x00B89038, 0xC0409000, 0xF7EF0D0E, 0x40A140A1, + 0x0D06D911, 0xDAF8F7EF, 0xD91140A1, 0xFC6F0EE6, + 0x089E724C, 0xC096FF2F, 0x0D7EC096, 0xD90BF9EF, + 0x0D76C096, 0xD911F9EF, 0x800046CB, 0x8E001220, + 0x209F704C, 0xC3960582, 0x60B9708C, 0x00A00C1E, + 0x2705750C, 0x40DB141B, 0x4EBF8001, 0x30F10B1F, + 0x30CF2378, 0x704C8E00, 0x0582209F, 0x708CC396, + 0x06012000, 0x00A00BF6, 0x6F01D80A, 0x903B46D3, + 0xC041C0B8, 0x000042C3, 0xC808BA68, 0x718C43A2, + 0x70CC70AC, 0x68324350, 0x2105D870, 0xB1000581, + 0x0C02D8C8, 0x218AFFEF, 0x44D30004, 0x4DAC8001, + 0x32112440, 0x800047CB, 0x220A12D9, 0x24402500, + 0x0F413210, 0xD8C82135, 0x082D8F00, 0x212F05EE, + 0x09F205C7, 0x40A2FF2F, 0x7280244A, 0x4342708D, + 0x20A84202, 0x080B0280, 0x9320030E, 0x7264B220, + 0x71857244, 0x25122240, 0x25102040, 0xF1E371E6, + 0x0004218A, 0x43A24262, 0x70AC708C, 0x0B9670CC, + 0x704EFFEF, 0x2500200A, 0x21350A45, 0x8F0040A2, + 0x04AE0831, 0x0487212F, 0xFF2F099A, 0x244A40A2, + 0x706D7280, 0x442A4302, 0x030020A8, 0x02CE080F, + 0x94209340, 0x793D6159, 0x7264B320, 0x71657285, + 0x25102040, 0x25112140, 0xF1E07146, 0x00E009C2, + 0xD870702C, 0x43A2D910, 0x000042C3, 0x718C2950, + 0x70CC70AC, 0xFFEF0B2E, 0xD8704050, 0x4202D910, + 0x708C43A2, 0x0B1E70AC, 0x70CCFFEF, 0xB802C808, + 0x05812005, 0xB100C000, 0x09DE40A1, 0xD90BFE6F, + 0x09D640A1, 0xD911FE6F, 0xFEEF0F16, 0xC096C096, + 0xF9EF0BF6, 0xC096D90B, 0xF9EF0BEE, 0x8E00D911, + 0x209F704C, 0xC3960582, 0x60B9708C, 0x00A00A9E, + 0x0B1D750C, 0x704C30F1, 0x209F8E00, 0xC3960582, + 0x2000708C, 0x0A860601, 0xD80A00A0, 0x45CB70CD, + 0xBF648000, 0x0E61C001, 0x252F1025, 0xD8C80387, + 0x0004218A, 0x43A24262, 0x0A9A728C, 0x70CCFFEF, + 0x2500200A, 0x093D702E, 0x8F002115, 0x046E082B, + 0x0447212F, 0xFF2F089E, 0x244A40A2, 0x708D7280, + 0x41A14302, 0x024020A8, 0x030E0809, 0xB1409340, + 0x72247264, 0x20407185, 0xE5142510, 0xF1E57126, + 0xF1D271C5, 0x08CA40A2, 0x712C00E0, 0xF9EF0AC2, + 0x1900700C, 0xC0BA3045, 0x341B1404, 0x78E0C6DA, + 0x1CFCC2FA, 0x2482B6C8, 0xC1443F17, 0xC08D4318, + 0x0ECE702C, 0xDA14F6AF, 0x0E0A750C, 0xD918F96F, + 0x800041DB, 0x11001222, 0x0ABA3081, 0x700CFB6F, + 0x00012052, 0x30801100, 0x742C6038, 0x704C7E0F, + 0xFE2F0E22, 0x206D40C1, 0x740C01CD, 0x41C342A1, + 0x0002033B, 0xF92F0E6A, 0xED8A43C1, 0x033D41C3, + 0x0E5E0000, 0xD80AF92F, 0x000007A9, 0x1243266F, + 0xF86F0982, 0x148F16F4, 0x750CC04C, 0xF96F0DA6, + 0x1100702C, 0x0A5E3081, 0x700CFB6F, 0x00012052, + 0x30801100, 0x742C6038, 0x704C7D0F, 0xFE2F0DC6, + 0x206D40A1, 0x41C301C0, 0x0002033C, 0xC04243A1, + 0x0E0E740C, 0xC202F92F, 0xB802C808, 0x0F812005, + 0xC0909007, 0x0F802005, 0x00909004, 0xB8899000, + 0xC004B100, 0x00002079, 0xC045E008, 0x7014C00C, + 0x20CAC005, 0xC04502A2, 0xC0438E00, 0x10801639, + 0x730C7014, 0xF219C046, 0xC003C102, 0x700C790B, + 0x20CAC048, 0xC04800E2, 0x70801600, 0x017B8000, + 0x001E081B, 0xC003C102, 0xD807790B, 0x20CAC046, + 0xC0460122, 0x700CF003, 0xC004C048, 0x2FC3268A, + 0x208A7014, 0xDE250FC7, 0x200226CA, 0xBE9FC106, + 0xBFC3C008, 0x700E6038, 0xC74A702E, 0xC007C047, + 0xA000210C, 0x002D0210, 0xC10272AE, 0x2440220A, + 0x790BC003, 0xF20E700C, 0x220AC006, 0x210C2440, + 0x700CA000, 0x1418F7C6, 0xC0063012, 0x0440200E, + 0x21012A40, 0x22056852, 0x7A052052, 0x68B66834, + 0x728E7945, 0x706E7D25, 0x8E204262, 0x716E8E1B, + 0x2B007825, 0xB9022081, 0x0081210F, 0xF211790B, + 0x202F7F2F, 0x08FE0487, 0x41E1FEEF, 0xC003C102, + 0xF207790B, 0xD8FF79AF, 0xFEEF097A, 0x248C42E1, + 0x160029BF, 0x80007080, 0x08130001, 0x244A00BF, + 0x16000FC0, 0x80007084, 0x40630120, 0x42C2702C, + 0x70AC726C, 0x091E70CC, 0x70EEF8AF, 0x230A720F, + 0x8E2025C0, 0x71EE8E1B, 0x2F007905, 0xB80224C0, + 0x04C0200F, 0xF2A3782B, 0x000045D3, 0x231F28F0, + 0x11022540, 0x2D41308D, 0x251F2095, 0x671F154F, + 0x30801105, 0x03640839, 0x44D3704E, 0x1A3C8000, + 0x0A27C005, 0xC0042005, 0x2500E887, 0x101C1680, + 0x0A0F0080, 0x0A7E2000, 0x24000060, 0x248023C0, + 0x71462184, 0x77A2F1EE, 0xF1E471A5, 0xC103C202, + 0xF2397A2B, 0x308D1102, 0x036408E3, 0x10522544, + 0x30801103, 0x0354203C, 0xC00570ED, 0x10050F4F, + 0xE888C004, 0x16802500, 0x0080101C, 0x10000F3B, + 0x30061410, 0x7BF079B0, 0x704C4062, 0x0822718C, + 0x71ACF7EF, 0x42624122, 0x0802219A, 0x229FC393, + 0x61790401, 0x245F6159, 0x623A2A02, 0x2501225F, + 0x7AF4623A, 0x71E5B200, 0x1105F1D9, 0x71A53080, + 0x708EF1CC, 0x20950C77, 0x20100C09, 0xF0038E1B, + 0xE8338E00, 0x20100C0B, 0x30921104, 0x1102F003, + 0x24783092, 0xE8852000, 0x308F1105, 0x1103F003, + 0xC305308F, 0x14104062, 0x41423006, 0x718C42E1, + 0xF7AF0FAE, 0x412270AC, 0x219A4262, 0xC3930802, + 0x0401229F, 0x30061410, 0x2A0D245A, 0x70AC728C, + 0xC3056179, 0x4142623A, 0x42E1655D, 0x0F82B500, + 0x4062F7AF, 0x7186B50A, 0x208CF1C6, 0x05F334FD, + 0x7126FFEF, 0x242FC005, 0x40A22000, 0x800043DB, + 0xC04B0025, 0x30811300, 0x3080131B, 0x710C7905, + 0x04002800, 0x200FB802, 0x782B0400, 0x702EF2AB, + 0x01527136, 0x090D000D, 0x131B2010, 0xF0043080, + 0x30801300, 0xF29D7014, 0x2214704E, 0x7156244F, + 0x002D012E, 0x702CC08D, 0xF6AF0B26, 0x24004282, + 0x00003F93, 0x231605EC, 0x70CD2413, 0x24532315, + 0x24932314, 0xC003C102, 0xF236790B, 0x79EF70AD, + 0x0B7A7AAF, 0x710CF92F, 0xE988C104, 0x16812700, + 0x0081111C, 0x10400D47, 0x230A41C1, 0x219A1400, + 0xC2930802, 0x1401239F, 0x2A0C215A, 0x2503225A, + 0x7261623A, 0x61796299, 0x000121F4, 0x78B4C08D, + 0x0A1B9040, 0xB0200045, 0x3F802400, 0x054C0000, + 0x60987061, 0x7BB4631B, 0x71A5B3C0, 0x0DA3C005, + 0xF0199004, 0x410240C1, 0x0802209A, 0x219FC293, + 0x60580401, 0x215A6038, 0x61192A01, 0x2500225A, + 0x14346110, 0x090F3101, 0x1B000005, 0x1C342384, + 0xC0073004, 0x07607610, 0x71C5FFE5, 0xC003C102, + 0xF21F790B, 0xC68D70AD, 0xE888C004, 0x16802700, + 0x0080101C, 0x10000D1F, 0xE88D9600, 0x41C3700C, + 0x00040343, 0x43224202, 0x0480240A, 0xF6AF0F1A, + 0x71A545A1, 0x0DD5C005, 0x72C59024, 0x1434F00E, + 0xE88C3100, 0x41C3700C, 0x00030344, 0x43224202, + 0xF6AF0EF6, 0x0480240A, 0x71E57146, 0x7126F169, + 0x258DF158, 0x710E22BD, 0x710C704E, 0x1300C049, + 0x131B3081, 0x79053080, 0x2800710C, 0xB8020480, + 0x0480200F, 0x02F4782B, 0xC0470021, 0xD9504042, + 0xF72F0A12, 0x200A734C, 0x24003480, 0x00003F80, + 0x209F054C, 0x70AE3401, 0x30182000, 0x02CC71B6, + 0x0D0D000D, 0x131B2010, 0xF0043080, 0x30801300, + 0x02AE7014, 0x710C0021, 0x05402800, 0xF9AF0CDE, + 0x252F780F, 0x40421540, 0xFB2F0D8A, 0x471041A1, + 0xC003C102, 0xF2C0790B, 0x20002752, 0x700E708E, + 0x23512200, 0x08FBC052, 0xDB0820B5, 0x2007C012, + 0x790F0400, 0x215F700C, 0x653E0502, 0x43484330, + 0x082BC105, 0x796F0065, 0xE988C104, 0x16812600, + 0x0081111C, 0x00400811, 0x30812034, 0x71917C6F, + 0x004523CA, 0x71047244, 0xC006F1EC, 0x708DC208, + 0x00032109, 0x3F802400, 0x05EC0000, 0x04802016, + 0x05402015, 0x04C02014, 0xC005B060, 0x7000240A, + 0x050020A8, 0xE888C004, 0x16802600, 0x0080101C, + 0x10000C15, 0x32C02000, 0x79629020, 0x00820907, + 0xB020C108, 0x71857265, 0x72CE70ED, 0x244A6F72, + 0x702C7100, 0x20A870CD, 0x40420640, 0x3F822400, + 0x054C0000, 0x0401209F, 0x255A6058, 0x621A2A02, + 0x2500235F, 0x20F46058, 0x783B00C2, 0x71647124, + 0x00002A00, 0x27147E05, 0xC207140F, 0x79CF78EF, + 0xFEAF0CF2, 0xC00A7A4F, 0x0B00205F, 0x71ED78F5, + 0x70237022, 0x253F268D, 0x7106A8DE, 0x4042F185, + 0x2A02255A, 0x0401209F, 0x3F812400, 0x054C0000, + 0x621A6038, 0xE886C004, 0x05041A24, 0x05041A10, + 0xE886C00C, 0x05041A26, 0x05041A12, 0x0F1B8A30, + 0x12242030, 0xB8020080, 0x8A127905, 0x7825B804, + 0x00811226, 0xB902F008, 0x12267905, 0xB8040080, + 0x8A327825, 0x7E0569D6, 0x79CFC007, 0x0C767A0F, + 0x740CFEAF, 0x205FC00A, 0x60B80B00, 0x70237042, + 0x0382182E, 0x3F802400, 0x05EC0000, 0x04802016, + 0x05402015, 0x20300F0D, 0x880290E0, 0xF004B804, + 0xBF049001, 0xC0077F05, 0x23C7242F, 0x0BA6790F, + 0x4082FEAF, 0x2140C00A, 0x205F3890, 0x21400B00, + 0x21403991, 0x42A23B93, 0x240A4342, 0x651D0500, + 0x21007542, 0x2032334E, 0xAEF22346, 0x3A8F2140, + 0x1085161E, 0x23472132, 0x233267A9, 0xC1402340, + 0x034541C3, 0xC0410008, 0xF8EF0F66, 0x0D27740C, + 0x8E322030, 0xE81EC009, 0x1E00C003, 0x80007042, + 0xC10200FB, 0xF23D790B, 0x40C38E3E, 0x01718000, + 0xC009F029, 0xC003E81B, 0x70421E00, 0x00F18000, + 0x790BC102, 0x8E3EF22D, 0x800040C3, 0xF01B0167, + 0x1E00C003, 0x80007042, 0xC1020100, 0xF221790B, + 0x40C38E3E, 0x01768000, 0xC003F00D, 0x70421E00, + 0x00F68000, 0x790BC102, 0x8E3EF213, 0x800040C3, + 0x1801016C, 0x20320052, 0x18012341, 0x21320052, + 0xA8202341, 0xA82167A9, 0x23412332, 0x2040A822, + 0x053D3A18, 0x71A6FFEF, 0x714EC00B, 0xC04B7704, + 0x700C7014, 0xFFE204EA, 0x0A22C049, 0x730CF9AF, + 0x3F172480, 0x341B1404, 0x78E0C6DA, 0x09FEC0F1, + 0x710CF9AF, 0x030541C3, 0x0E960000, 0xD80AF8EF, + 0x030641C3, 0x42C30001, 0x25030000, 0xF8EF0E82, + 0x740CD80A, 0x030741C3, 0x714C0004, 0x738C726C, + 0xF8EF0E6E, 0x740C74AC, 0x030841C3, 0x704C0004, + 0x123444C3, 0x45C3ABCD, 0xEF12ABCD, 0xF8EF0E52, + 0x09AADB07, 0x700CF9AF, 0x00200A7E, 0x700CD807, + 0x00C420AB, 0xF0007FFF, 0x2079C2E6, 0x4708000E, + 0x256F4E18, 0xB5001A43, 0x10002752, 0xF82F0946, + 0x30021A06, 0x41C3E808, 0x000002F6, 0xF8EF0E12, + 0xF018D80A, 0xEF05D80A, 0xB912D9BD, 0x41C3F004, + 0x000002F5, 0xF8CF0DFA, 0xF90F0C96, 0xEF86E802, + 0x085678DB, 0x7404FEEF, 0x084E78DB, 0x7304FEEF, + 0x40C370F5, 0x8009FFFF, 0x006120C2, 0x30031A06, + 0xD8FDB500, 0xFD6F0B66, 0x00E120CA, 0x78E0C6C6, + 0x7FE0710C, 0x00C420AB, 0x1E00710C, 0x900C7004, + 0x7EE00088, 0x7014C2F6, 0x42C3C808, 0x01238000, + 0x901C43C3, 0x404804B0, 0x0F8122CA, 0x01248000, + 0x008B2840, 0x23056BA4, 0xDF3F10C1, 0x23058A40, + 0x91001343, 0xBF08E50C, 0x12CD2505, 0x938078E4, + 0x784595C0, 0x2404B100, 0x7EE413C0, 0x7AC57845, + 0xB540B300, 0x901C41D3, 0x100004E4, 0x21401080, + 0x16002215, 0x80007081, 0x48350124, 0x14402305, + 0x254090C0, 0x25CE2116, 0x26531021, 0x23051181, + 0x23051542, 0x25001583, 0x92209057, 0x01131300, + 0x01902153, 0x001A4230, 0x23530024, 0x25002194, + 0x000E943E, 0x25000024, 0x0022953E, 0x752C0003, + 0x0A06700C, 0xB913F6AF, 0x6832C808, 0x05832105, + 0x05422105, 0x04402105, 0x7EE44328, 0x23D22204, + 0x15C12605, 0x23502000, 0x2305B020, 0x901C1F80, + 0x270404E8, 0x758214CF, 0x2005B020, 0x7DE52480, + 0xB3A0B200, 0x78E0C6D6, 0x4628C2E4, 0x16004508, + 0x90307100, 0x1A2103BC, 0xE909301C, 0x10710E3D, + 0x724C700C, 0x30831A07, 0x258CF020, 0x004E9804, + 0x258C0029, 0x00629FC3, 0x258C002C, 0x258C9002, + 0xF23D9004, 0x9404258C, 0x258CF23D, 0xF44F9804, + 0x1A07754C, 0xF00A3143, 0x030241C3, 0x096A0001, + 0x42C1F6AF, 0x30821207, 0x41C3D80A, 0x00030303, + 0x0C4E43A1, 0x44C1F8EF, 0x258CC6C4, 0xF6D597C8, + 0x9808258C, 0x258CF223, 0xF2259848, 0x9F800D97, + 0xE9010000, 0xF223F02B, 0x9402258C, 0x714CF427, + 0x30431A07, 0x258CF1E2, 0xF21D9844, 0x9408258C, + 0xDA07F41D, 0x31C31A07, 0x734CF1D8, 0x30C31A07, + 0x744CF1D4, 0x31031A07, 0xDA08F1D0, 0x32031A07, + 0xDA09F1CC, 0x32431A07, 0x704CF1C8, 0x30031A07, + 0x764CF1C4, 0x31831A07, 0xDA0AF1C0, 0x32831A07, + 0x78E0F1BC, 0x8FC3208C, 0x0821F209, 0x41C301D1, + 0x0470901C, 0x00451900, 0x41C3F006, 0x0470901C, + 0x01051900, 0x00051900, 0x903041C3, 0xB10000C8, + 0x0020001D, 0x00051904, 0x903041C3, 0xB10000C8, + 0xB104B830, 0x00200009, 0x00051904, 0x903041C3, + 0x91000010, 0x801F08FF, 0x0B822155, 0x080F9200, + 0x1A0408B1, 0x1ACE0045, 0x9100005D, 0x801E08FF, + 0x78E07EE0, 0x70801600, 0x01078000, 0x01002044, + 0xB8227FE0, 0x0343226F, 0x0500120E, 0x000070D3, + 0x700C0C80, 0x07C520E0, 0x050112E0, 0xF60BE1FF, + 0x02032142, 0x00940B23, 0x0430092B, 0xF20FE1C0, + 0x218CF014, 0xF20B8002, 0x8010218C, 0x091DF211, + 0x00000F81, 0x8A004000, 0x8A00F007, 0x0080206D, + 0x8A00F004, 0xB8C0781D, 0x20797FE0, 0x8A000000, + 0x00C0206D, 0x78E0F1FA, 0x70801600, 0x00058000, + 0x20797FE0, 0x78E00000, 0x0F8EC0F1, 0xE809FFCF, + 0x70801600, 0x00F48000, 0x710CB8E4, 0x700CF402, + 0x7EE0C0D1, 0x216FC0F1, 0x890005C3, 0x700CB8E6, + 0x895AF208, 0x00811135, 0x73347945, 0xFFC10FCC, + 0x7EE0C0D1, 0x0F43216F, 0xB8E18900, 0x7CE0700C, + 0x810011E8, 0x7000263C, 0x0C7F0000, 0x78E07EE0, + 0x4300C0F1, 0x70801600, 0x00018000, 0x013F0825, + 0x0EA64428, 0xD808FFEF, 0xFFEF0ED2, 0x232F4060, + 0xF20880C8, 0xFFEF0EC6, 0x14001404, 0x0F3F238C, + 0x7EE0C0D1, 0x44CBC5E1, 0x28F00000, 0x030D201F, + 0x786A789B, 0x0184229F, 0x2C4160BB, 0x782A1080, + 0x605C6078, 0x800042C3, 0x22561A3E, 0x64080800, + 0x10012415, 0x60336A0A, 0x0A256152, 0x700C00E4, + 0x1F812434, 0x1B408000, 0x21CC7230, 0xF78880C6, + 0x4A314970, 0x79307810, 0x00002109, 0x78E0C4C2, + 0x1600C2E8, 0x80007101, 0x47C3000A, 0x18000000, + 0x21044010, 0x248A01C1, 0x27507001, 0x700D0307, + 0x70CC702D, 0x70CD70ED, 0x706D704C, 0x20A8708D, + 0x20150101, 0x906023C0, 0x087B9001, 0x631D00E4, + 0x6B014873, 0x7D0C73C0, 0x00462340, 0x21007034, + 0x20DA1349, 0x20D503C1, 0xF22D1001, 0x01E10915, + 0x8C07208B, 0x271A780C, 0x621A1003, 0xF0237E75, + 0x083BF20D, 0xDB08023F, 0x8003208B, 0x262FF213, + 0xDB07F005, 0x01A323CA, 0x204BF011, 0xF2078300, + 0x736CB8E3, 0x00A123CA, 0x781DF009, 0x00432044, + 0xB8E5F005, 0x23CA756C, 0x647C0121, 0x23157BEC, + 0x71E510CB, 0x00300E4B, 0x2905D8C9, 0x21781180, + 0x71F00003, 0x767D729D, 0x26CA7074, 0x20CA0081, + 0x71041381, 0x118D2805, 0xFFEF0E42, 0xE8897E1D, + 0xBD2271A5, 0x1FC0257C, 0x25CA7014, 0x18821FE1, + 0x2080239C, 0x18002084, 0x700C2342, 0x41C3C6C8, + 0x00020215, 0x08EA4201, 0x4321F8EF, 0x021641C3, + 0x08DE0000, 0xD8C9F8EF, 0xC6C8730C, 0x42C3C2E4, + 0x12208000, 0x8A404300, 0x02C1239F, 0x0582229F, + 0x2232627A, 0x80010F8D, 0x714C4E86, 0xE9047A18, + 0x12012585, 0x0A8A6A12, 0x2005F6EF, 0x252F008E, + 0x700C0387, 0xDA22762C, 0x244A43A1, 0x0BEE0480, + 0x70CCF72F, 0xD907D880, 0x706C724C, 0x70AC708C, + 0xF72F0BDA, 0x700C70CC, 0xF72F0B82, 0xC6C4712C, + 0xB80243E3, 0x0F822005, 0x00009000, 0xFE6F09E6, + 0x7B204020, 0x78E0B200, 0x4608C2E6, 0x70801600, + 0x00088000, 0x72AD7214, 0x0A264728, 0x25CAF6EF, + 0x0E461161, 0x0A02F70F, 0x0819F6CF, 0x700C003F, + 0x704CD907, 0x708C706C, 0x0B8270AC, 0x70CCF72F, + 0x752CD809, 0x704CB813, 0x0008238A, 0x45C1708C, + 0xF72F0B6A, 0xD80C70CC, 0x42A1D92B, 0x708C706C, + 0x0B5A45C1, 0x70CCF72F, 0xD92BD80C, 0x706C42A1, + 0x45C1708C, 0xF72F0B46, 0xEF0670CC, 0xD80C6D41, + 0xF005D92B, 0xD92BD80C, 0x706C42A1, 0x45C1708C, + 0xF72F0B2A, 0x708C70CC, 0x4788D92B, 0xBF9242A1, + 0x40E1726C, 0x0B1645C1, 0x70CCF72F, 0xD92BD80C, + 0x726C42A1, 0x45C1708C, 0xF72F0B02, 0x700C70CC, + 0x744CD907, 0x708C706C, 0x0AF270AC, 0x264AF72F, + 0x7DFB0280, 0x40A1D907, 0x706CDA10, 0x45C1708C, + 0xF72F0ADA, 0x2F4170CC, 0xD90710C0, 0x706C744C, + 0x70AC708C, 0xF72F0AC6, 0x700C70CC, 0x744CD907, + 0x708C706C, 0x0AB670AC, 0x264AF72F, 0x0D420BC0, + 0x700CF70F, 0x744CD907, 0x708C706C, 0x0A9E70AC, + 0x70CCF72F, 0x18002555, 0x704CD907, 0x708C706C, + 0x0A8A45C1, 0x70CCF72F, 0x78E0C6C6, 0xC1A6C3FA, + 0xC045D977, 0x0F1AB910, 0x740CF8AF, 0x800040C3, + 0x10020150, 0x42830501, 0x1002B220, 0xB2210501, + 0x05011002, 0x1002B222, 0xB2230501, 0x05011002, + 0x9020B224, 0x9021B225, 0x9022B226, 0x808010D7, + 0xE805B227, 0x30961210, 0x120FF003, 0x700E3096, + 0x800040C3, 0xC0441228, 0x01F07216, 0x702C0026, + 0x20510811, 0x70801600, 0x003F8000, 0xF2E97014, + 0x2800710C, 0x0A160400, 0x780FF96F, 0x702EC005, + 0xF29C7014, 0x202FC704, 0xC0803407, 0x04402015, + 0x040020F4, 0xF6EF086A, 0x0C8268B2, 0x78B0F72F, + 0x70AD45F1, 0x010875D2, 0x704E0026, 0x3540210A, + 0x0BF7706E, 0x11012095, 0x740C3494, 0x1F8E2532, + 0x04788000, 0x41C34222, 0x00050078, 0x240A4362, + 0x45C10400, 0xF8AF0E4A, 0x0500260A, 0x13310E1B, + 0x3083120E, 0x0407202F, 0xFB2F0F3E, 0x0487212F, + 0xDA22E803, 0x6B09F00A, 0x2538DA22, 0x23781001, + 0x20052000, 0x7AC0807E, 0x4382710C, 0x04C02800, + 0x683244C1, 0x782570CC, 0x272F762C, 0x700C2007, + 0xF72F095A, 0x05C0250A, 0x13310E79, 0x1487262F, + 0x0EF64003, 0x41C1FB2F, 0x244FE823, 0x740C21D4, + 0x41C34222, 0x00050079, 0x240A4362, 0x254A0400, + 0x0DCE0300, 0x260AF8AF, 0x0B130500, 0x704C2030, + 0x7704CA0E, 0x10000D07, 0x700CDA22, 0x4382762C, + 0x0300244A, 0x05C0250A, 0xF72F0902, 0x400370CC, + 0xFB2F0EA6, 0xE88E41C1, 0x742C700C, 0xF72F0BE2, + 0x0B11704C, 0x700C2030, 0x0BD6702C, 0x704CF72F, + 0x71667146, 0x74A6F187, 0xF17E71A5, 0x74367126, + 0xFFE506DA, 0xF045E72C, 0x704E740F, 0x72EEC080, + 0x04802015, 0x70AD70AE, 0x040020F4, 0x2005781B, + 0x00040F93, 0x0E4D1000, 0x240A2030, 0x25002580, + 0x80002F95, 0x70ED1228, 0x2B00225A, 0x1F822732, + 0x04788000, 0x007A41C3, 0x78F50002, 0x04002014, + 0x200E2532, 0x0D1A740C, 0x43C1F8AF, 0x71E578AF, + 0x71A57062, 0xB89CB802, 0x248DB89F, 0xA0C02A3F, + 0x26FF278D, 0x0D1571AE, 0x78AF103E, 0xB8027062, + 0xB89FB89C, 0x04441800, 0x30BF208D, 0xC0047146, + 0x72047106, 0xF10AC044, 0x901C40C3, 0xB02001F8, + 0x804418F0, 0x78E0C7DA, 0x716EC2F4, 0x23064010, + 0x16002013, 0x80007080, 0x70140131, 0x2740224A, + 0x2100240A, 0x46504570, 0x0E864628, 0x22CAF6AF, + 0x70AD25A1, 0x011C7552, 0x40A20026, 0x1F912532, + 0x06188000, 0x092A4122, 0x2632FAEF, 0x08BD144F, + 0x0D1B0010, 0x700C1131, 0x744CD910, 0x708C706C, + 0x0400250A, 0xF6EF0FC6, 0x700C70CC, 0x704C762C, + 0x240A43E1, 0x250A0440, 0x0FB20400, 0x70CCF6EF, + 0xD922700C, 0xF72F0A9A, 0x0D85704C, 0x0E191755, + 0x1F08734E, 0x16000000, 0x80007080, 0x085D00CA, + 0xF034001F, 0x734F0E55, 0x00000006, 0x14110D61, + 0x800040C3, 0x88201222, 0x203C8803, 0x0D1A0040, + 0x4162FB2F, 0x0F96E81A, 0xD8FAFBAF, 0x700C7910, + 0xF72F0A4E, 0x274F704C, 0x700C11C3, 0x704C762C, + 0x0440240A, 0x0400250A, 0xF6EF0F42, 0x700C70CC, + 0x0A2ED922, 0x704CF72F, 0x0F62D8FA, 0x7910FB8F, + 0x0A1E700C, 0x704CF72F, 0xF19671A5, 0x0C41EDFE, + 0x8E012010, 0x00DF080D, 0x20538E14, 0xF21880FE, + 0x0EBA700C, 0x712CF6EF, 0xF68F0D86, 0x000040C3, + 0x0FC23A98, 0xD908FC2F, 0xFE6F0CE6, 0x40C340C1, + 0x0D400003, 0xFC2F0FAE, 0xF1E0D908, 0xF1D7D8C8, + 0xD941700C, 0xF72F09CA, 0x700C704C, 0xF6EF0E7E, + 0x0E41712C, 0x8E1C2010, 0x015E0831, 0xF68F0D42, + 0x20452053, 0xD919D880, 0xDB85744C, 0x0EAE708C, + 0x70CCF6EF, 0x0E56700C, 0x712CF6EF, 0x005B40C3, + 0x0F628D80, 0x702CFC2F, 0x09EE700C, 0x4102F8EF, + 0x78E0C6D4, 0x716EC2F6, 0x23064010, 0x16002013, + 0x80007080, 0x70140131, 0x2740224A, 0x2140240A, + 0x2100250A, 0x47504670, 0x0BD24628, 0x22CAF96F, + 0x0CDE25A1, 0x0AE2F68F, 0x70ADFE4F, 0x012A7552, + 0x40C20026, 0x1F912532, 0x06188000, 0x0F824122, + 0x2632FAAF, 0x7014144F, 0x0D11F285, 0x700C2030, + 0x091ED91E, 0x714CF72F, 0x11310D55, 0x762C700C, + 0xF72F090E, 0x700C714C, 0x704CD92C, 0x708C706C, + 0x0400250A, 0xF6EF0E06, 0x700C70CC, 0x704CD92D, + 0x708C706C, 0x0400250A, 0xF6EF0DF2, 0x700C70CC, + 0x08DE762C, 0x714CF72F, 0x41E14022, 0xF72F09B2, + 0x25424202, 0x08451600, 0xF0500154, 0x41E14022, + 0xF72F099E, 0xED234202, 0x14D00D31, 0x94110DE7, + 0x800040C3, 0x88201222, 0x203C8803, 0x0B5A0040, + 0x4162FB2F, 0x700CE867, 0x0896762C, 0x714CF72F, + 0x11C1274F, 0xF1DC4022, 0x70801600, 0x00CA8000, + 0x003E0859, 0xD91E700C, 0x0C47F025, 0x8E012010, + 0x00DF080D, 0x20538E14, 0xF21B80FE, 0xFE4F09D6, + 0x0D1A700C, 0x712CF6EF, 0xF68F0BE6, 0xFE4F09EA, + 0x000040C3, 0x0E1E3A98, 0xD908FC2F, 0xFE6F0B42, + 0x40C340C1, 0x0D400003, 0xFC2F0E0A, 0x700CD908, + 0x082ED918, 0x714CF72F, 0x762C700C, 0xF72F0822, + 0x71A5714C, 0x098EF16C, 0x700CFE4F, 0xF6EF0CCE, + 0x0F5B712C, 0x8E1C2010, 0x015E084B, 0xF68F0B92, + 0xFE4F0996, 0xD925700C, 0xDB85704C, 0x250A708C, + 0x0CFA0400, 0x70CCF6EF, 0xD926700C, 0xDB85704C, + 0x70AC708C, 0xF6EF0CE6, 0x094A70CC, 0x700CFE4F, + 0xF6EF0C8A, 0x40C3712C, 0x8D80005B, 0xFC2F0D96, + 0x710C702C, 0xF8EF0822, 0x09B64102, 0xC6D6F98F, + 0x47CBC2EA, 0x02FE8000, 0x10911700, 0xF92F0CBE, + 0x40C3730C, 0x11388000, 0xE80B8800, 0x70801600, + 0x00018000, 0x02002044, 0x00002078, 0x700CF002, + 0x0E36D911, 0xB913F62F, 0x207E090B, 0x0D5AD820, + 0x09EAFF8F, 0x8FA1F94F, 0x10901700, 0xF6AF0AF2, + 0x10022589, 0xFE4F08F2, 0x70CDED1B, 0x1F802600, + 0x03808000, 0xDA0F8820, 0xF72F0826, 0x80801080, + 0x762C700C, 0xF6EF0F3A, 0x258D714C, 0x71C51CBF, + 0xFE4F08A2, 0x0BE6700C, 0x712CF6EF, 0x0896F003, + 0x080FFE4F, 0xD822207E, 0xFF8F0CFE, 0x0912F1D5, + 0x090DF98F, 0xD821207E, 0xFF8F0CEE, 0x78E0C6CA, + 0x43C3C5E1, 0x04628000, 0x93034008, 0xF042242F, + 0x7A1DF215, 0x2200706D, 0x00040F8C, 0x20A81000, + 0x201503C0, 0x716512C2, 0x924192A0, 0x7D45BA10, + 0xBA9C6C52, 0xBA9F7185, 0x6038A2A0, 0x9300B303, + 0xB3006038, 0x78E0C4C2, 0x1CFCC2FA, 0x4710B6C8, + 0xB89FD840, 0x2100240A, 0x45504378, 0x00991000, + 0x10E54630, 0x700E8098, 0x716E724E, 0x24002B00, + 0x2004722E, 0xB80206CF, 0x040E200F, 0x70AD4003, + 0xF23078EB, 0x23402B00, 0xF92F0B92, 0x40C3780F, + 0x11388000, 0xE8188800, 0x70801600, 0x00018000, + 0x00FF0825, 0x259F4002, 0x209F1582, 0x42C202C1, + 0x708C43A2, 0x0500250A, 0x651975E2, 0xFFEF0CCA, + 0xF01078CF, 0x259F4002, 0x209F1582, 0x42C202C1, + 0x240A43A2, 0x75E20500, 0x0B126519, 0x78CFFFEF, + 0x218D4023, 0x71AD243F, 0x20BF228D, 0x0B2E710E, + 0x730CF92F, 0x341B1404, 0x78E0C6DA, 0x4568C3E6, + 0x47284648, 0xB0091CF8, 0x30011C04, 0x30C21C01, + 0xF6EF0D9A, 0x2578C360, 0x41C11000, 0x6841781B, + 0xF6EF0D3E, 0x0D86C080, 0x40E1F6EF, 0x0A8E700C, + 0x712CF6EF, 0x78E0C7C6, 0x2945C2E4, 0x4608018B, + 0x0D3D70AD, 0x8E0112C5, 0x8E228E40, 0x7A05B808, + 0xB8088E03, 0xB8107825, 0x00812005, 0x8E448E05, + 0xB8087734, 0xF2077845, 0xB99CB902, 0xB100B99F, + 0x0AD6F003, 0x76C5FC0F, 0xF1E571A5, 0x78E0C6C4, + 0x7034C2E4, 0x800041C3, 0xF22712E0, 0x00C1110A, + 0x7180244A, 0x7B31C808, 0x2144B923, 0x68520401, + 0x22057965, 0x90030F8C, 0x7B2FD580, 0x0F812205, + 0xD5849003, 0x800042C3, 0xB4600548, 0x20A8B160, + 0x12100300, 0x79050401, 0x2105B902, 0x90030F81, + 0xB160C000, 0x2042F017, 0xF215803C, 0x20A86944, + 0x120604C0, 0xB8020400, 0x0F832005, 0x00009000, + 0x04C0120E, 0xB8237911, 0x04002044, 0x780F7825, + 0x720CB300, 0x900345CB, 0x46CBD478, 0xF07C9007, + 0x10C51D00, 0xFC2F0A32, 0x10C51E00, 0x900F41C3, + 0x2150E008, 0x710C04C2, 0x01451900, 0x01451A00, + 0xB200B100, 0xB600B500, 0x78E0C6C4, 0x42C3C0E6, + 0x12228000, 0x40288A81, 0x0C518AA0, 0x43001364, + 0x00022479, 0xE20970B4, 0x22CAC808, 0x20050062, + 0x221F00CE, 0x2D40034B, 0x240A130F, 0x7FC57080, + 0x20A8706C, 0x2B400440, 0x70B40200, 0x20F478C0, + 0x78E512C1, 0xB8027164, 0xB8927165, 0xB89FB89C, + 0x7591B020, 0xF7A971A5, 0x78E0C4C6, 0x4010C2E8, + 0x800046CB, 0x47CB1222, 0x4DAC8001, 0x2754E903, + 0x8EA01F0F, 0x08578E01, 0xD8C80364, 0x800040C3, + 0x880012D9, 0x036E0843, 0x0F7A79AF, 0x4002FE2F, + 0xC8084408, 0x13822D40, 0x7280244A, 0x700C6832, + 0x20A87A25, 0x0C2104C0, 0x255A100E, 0x61F91501, + 0x000321F4, 0x02812840, 0x21057945, 0x90040F81, + 0xB1600320, 0x71A57104, 0x09A2F1D6, 0xC6C8FC0F, + 0x718EC2F4, 0x2C004610, 0x16002040, 0x80007093, + 0xB8020004, 0x200F4230, 0x0AAF0051, 0x235302F0, + 0xE28A20D3, 0x700EF4B4, 0x081372AE, 0x16002010, + 0x80007080, 0x08890040, 0x272F0010, 0x40421400, + 0xFAAF0982, 0x260041E1, 0x42C323C1, 0x0E9C8000, + 0x89218960, 0x6149634D, 0x6914E804, 0xF0047D05, + 0x7D25BD04, 0x2800710C, 0x08A20400, 0x780FF92F, + 0x750C7EAF, 0x41C34242, 0x000301D3, 0x0D224302, + 0x44C1F86F, 0x0447212F, 0xFE2F0AC2, 0x235F40C1, + 0x60F82B00, 0x70C37042, 0x123C8000, 0x20300A15, + 0x0CC7A8A0, 0x1E002010, 0x80007342, 0xF008017E, + 0x20100CCB, 0x73421E00, 0x017D8000, 0x258D710E, + 0x708E2DFE, 0x700EF064, 0x081372AE, 0x16002010, + 0x80007080, 0x08890040, 0x272F0010, 0x40421400, + 0xFAAF08E2, 0x260041E1, 0x42C323C1, 0x0E9C8000, + 0x89218960, 0x6149634D, 0x6914E804, 0xF0047D05, + 0x7D25BD04, 0x2800710C, 0x08020400, 0x780FF92F, + 0x750C7EAF, 0x41C34242, 0x000301D4, 0x0C824302, + 0x44C1F86F, 0x0447212F, 0xFE2F08BA, 0x235F40C1, + 0x60F82B00, 0x70C37042, 0x12388000, 0x20300A15, + 0x0C31A8A0, 0x1E002010, 0x80007342, 0xF00800F7, + 0x20100C35, 0x73421E00, 0x00F28000, 0x258D710E, + 0x708E2DFE, 0x1E00F014, 0x80007342, 0xF0100180, + 0x73421E00, 0x01018000, 0x1E00F00A, 0x80007342, + 0xF006017F, 0x73421E00, 0x00FC8000, 0x70801600, + 0x00408000, 0x730CE803, 0x710CF002, 0xF8CF0F6E, + 0x78E0C6D4, 0xC1A8C3E6, 0x1243276F, 0x800145CB, + 0x8FC04E74, 0x1756712C, 0x20441080, 0x09B60202, + 0x40A1FBAF, 0xD91440A1, 0xF6EF0FBE, 0x178A704C, + 0x40A11082, 0x099EBAC3, 0xD914FBAF, 0xF8EF0F22, + 0x0B4EC084, 0xC080FE2F, 0x082EC080, 0xD910F92F, + 0x08358F17, 0x40C3001E, 0x12D88000, 0xE8148800, + 0x41C3BEC3, 0x12288000, 0x1B00265F, 0x6119602A, + 0x1DA28902, 0x89011002, 0x10021D57, 0xAD4C8903, + 0x10021DED, 0xD91040A1, 0xF6EF0F5E, 0x40A1DAFB, + 0x0942D910, 0xDA41FBAF, 0x702C40A1, 0xDBFFC284, + 0xFFEF0AFA, 0x40A1708C, 0x092AD910, 0x744CFBAF, + 0x702C40A1, 0x0BDEC280, 0x716CF72F, 0x78E0C7C6, + 0x78E07EE0, 0x1CFCC2FA, 0x2482B6C8, 0x46303604, + 0x0F46702C, 0x4318F7AF, 0x451071AD, 0x16C02D00, + 0xF9EF0DE2, 0x0DEA68F2, 0x4210F9EF, 0x8E82208C, + 0x238A70CD, 0xF7062F83, 0xF9CF0DD6, 0x08932054, + 0x70831600, 0x00048000, 0x750CBBC3, 0x41C34263, + 0x0002040D, 0xF86F0AEA, 0x16D0270F, 0x41C3D82E, + 0x0E010001, 0xB70F478B, 0xB709D895, 0xB890D897, + 0x41C3C155, 0x012A0007, 0x2154C040, 0xB86C0942, + 0xC043C149, 0xC808E115, 0xC2466989, 0x00422005, + 0x7224B755, 0xBA30C24F, 0xB7567905, 0xC14C6C49, + 0x00812005, 0x03032005, 0x30441C42, 0x1C44B930, + 0x6A2E3044, 0x20057905, 0x00010F80, 0xB73B00FB, + 0xB703B930, 0xB73CB830, 0xB704D90F, 0x714CC080, + 0x31C51C50, 0x33441C4E, 0xB7AAB7B0, 0x1C58B7C2, + 0x1C523384, 0x1C4C3384, 0x1C463384, 0x1C403384, + 0xB7DD3384, 0xB7D7B7DA, 0xB7D1B7D4, 0xB7CBB7CE, + 0xB7C5B7C8, 0xFDEF0B32, 0x1600C352, 0x80007083, + 0x245512D9, 0x244A3801, 0x700C7200, 0x33801C8C, + 0x33801C88, 0x33801C84, 0x33801C80, 0x040020A8, + 0x0B137A1D, 0x2605008E, 0x90381F82, 0x9240012C, + 0x7224B140, 0x000076C3, 0x71044000, 0x1643276F, + 0x20448F00, 0xF2068202, 0x70851E00, 0xC3789007, + 0x41C3700C, 0xC25C9007, 0x800046CB, 0x1E001222, + 0x901C7004, 0x1E000004, 0x90077004, 0xB100F804, + 0x1964EA99, 0xD9400205, 0x900740C3, 0xB020C2C4, + 0x8E41B0A8, 0x0A778E20, 0x7A5B0064, 0x70402614, + 0x048C8000, 0x00412217, 0x09B66942, 0x702CF5EF, + 0x1600F02D, 0x80007082, 0x72540008, 0x901C43C3, + 0x42C30000, 0xF8009007, 0x1964F406, 0xB3000004, + 0xF006B200, 0x01051964, 0xB2A0B3A0, 0x8E008E21, + 0x0024092B, 0x71247902, 0x7040240A, 0x03C020A8, + 0x06812000, 0x70022614, 0x048C8000, 0x0081111C, + 0x21787104, 0xB9080001, 0xD8AAB220, 0x70041E00, + 0xC0B89007, 0xF64F0B0A, 0x0407202F, 0xC057D907, + 0x145CD841, 0xB8133005, 0x706C744C, 0x0C6E708C, + 0x70CCF6AF, 0xD907700C, 0x706CDA08, 0x70AC708C, + 0xF6AF0C5A, 0x145C70CC, 0xD8803005, 0xD907B893, + 0x706C744C, 0x0C46708C, 0x70CCF6AF, 0x0BEE700C, + 0x712CF6AF, 0x000040C3, 0x0CFA1388, 0x752CFBEF, + 0xD9FF710C, 0xFB6F0986, 0x216F704C, 0x40D32443, + 0x048C8000, 0x20801100, 0x01012078, 0x7424B902, + 0x180AB806, 0x20892042, 0x41C30E43, 0x000103E3, + 0x740C6846, 0xF86F089A, 0x20841808, 0x6872C808, + 0x901C40C3, 0x23050504, 0xB1A00001, 0x0F812305, + 0x04FC901C, 0x834418A4, 0x0F802305, 0x04DC901C, + 0x11009000, 0x0A1B2082, 0xB8C500B1, 0x02C2204F, + 0x8F20B140, 0x00FE0925, 0x0301204F, 0x204FF009, + 0xB1400302, 0x09158F20, 0x204F00FE, 0x23050341, + 0x901C0F80, 0xB02004F4, 0x0F802305, 0xC3EC9007, + 0x71051E00, 0xC12C903B, 0x088EB0A0, 0x710CFB2F, + 0xB802C808, 0x0F812005, 0x00949004, 0x1C909120, + 0x8F203040, 0x00DE091B, 0x0F812005, 0xC0949007, + 0x30001490, 0x0080206C, 0x00C02045, 0x1600B100, + 0x80007080, 0x22440126, 0xB8E22051, 0xF9A20C48, + 0x21004063, 0x42D32491, 0x0FB08000, 0x3A402455, + 0x28012240, 0x0FD2DA72, 0x2344F5AF, 0x40C32054, + 0xF0A70000, 0x30041C66, 0x000140C3, 0xC058FF74, + 0x0004208A, 0x30041C6A, 0x100AD972, 0x1C682080, + 0xB8063344, 0x30041C64, 0xFFEF0822, 0x3A402455, + 0x204B8F00, 0xF4068E00, 0x0812C098, 0xD90CFFEF, + 0xD90FD80F, 0x24CD2400, 0xF76F0C2A, 0x27912140, + 0x204B8F00, 0xF4088E00, 0xF84F0D46, 0x0E924063, + 0x712CFF6F, 0x78AFC217, 0x0447212F, 0xFB2F0BDA, + 0x8F404118, 0x8E00224B, 0x0A67F20B, 0x700C00FF, + 0x041441C3, 0x0C420001, 0x026FF5CF, 0x41C30000, + 0x0000040F, 0xF82F0F2A, 0xD861740C, 0x900745CB, + 0xB808C29C, 0xB500712C, 0xF6AF0A22, 0xD941D808, + 0x0004208A, 0xB500B914, 0xF82F0F06, 0x1600740C, + 0x80007080, 0xB8E20001, 0x002201FA, 0x1008DD0A, + 0x09FA2100, 0x712CF6AF, 0x1EFF258C, 0x41C3F0F8, + 0x00000411, 0xF82F0EDA, 0x710C740C, 0xF6AF09DE, + 0x2455712C, 0x41423A40, 0xF5AF0ECE, 0x2455DA10, + 0x22403940, 0x0EC22401, 0xDA10F5AF, 0x8E20700C, + 0xC05EC05F, 0xC05CC05D, 0x082F8E01, 0x78220064, + 0xC8086841, 0x7080240A, 0x20A86872, 0x294003C0, + 0xC2980380, 0x7A357865, 0x0F802005, 0x00A89004, + 0x71249000, 0x700CA200, 0xF6AF0982, 0x8E01712C, + 0x2001258A, 0x082F8E20, 0x78220064, 0xC8086861, + 0x70C0240A, 0x20A86852, 0x294003C0, 0x78450380, + 0x0F832005, 0x00A89004, 0x3A402455, 0x71244820, + 0x0FE2B300, 0x700CFD4F, 0xF6AF0942, 0x8EA0712C, + 0x08D98E01, 0x2D400364, 0xD8891391, 0x2F922105, + 0x01C89004, 0x20041A00, 0xFBEF09AE, 0x20F4D808, + 0x24552340, 0x23153A53, 0x24552353, 0x26153956, + 0x41C32356, 0x00050412, 0xB80242A1, 0x04402005, + 0x3E112454, 0x0F802005, 0x01CC9004, 0x21159000, + 0x1A002351, 0x20442005, 0x43660058, 0x1600740C, + 0x260A2017, 0x11000600, 0x240A2012, 0x250A05C0, + 0x0DBE0480, 0x4470F82F, 0x3011081B, 0x20330A17, + 0x20402740, 0x00F5080B, 0x71EE714E, 0x2F84F003, + 0x081D2FBF, 0x0A193010, 0x27402072, 0x080D2040, + 0x774E00F5, 0xF00477EE, 0x2FBF2F84, 0x20310A19, + 0x30002078, 0x00002079, 0xB805791B, 0x00522142, + 0x04172042, 0x25D42400, 0x25C01E00, 0x24801900, + 0x1B0071A5, 0xF1962500, 0x2DBD258C, 0x096A4063, + 0x702CF7AF, 0x00100883, 0x8E408E21, 0x00A40941, + 0x0A832040, 0x7942C808, 0x240A7124, 0x20A87040, + 0x2A400600, 0x7C05030C, 0x10C12405, 0x2105B902, + 0x90040F8D, 0x6C320000, 0x0F8C2105, 0x00A89004, + 0xB5209420, 0x4941C198, 0xB4207144, 0xFD0F0A46, + 0x1008F01B, 0x08062100, 0x712CF6AF, 0x0C224063, + 0x702CFF6F, 0x702C40C2, 0xFD2F0DD6, 0x2540724C, + 0xC8082A95, 0x05402005, 0x704C41C2, 0x708C706C, + 0xFFAF0E5E, 0x0E6E71AC, 0x70CDFD4F, 0x900745CB, + 0x4063C29C, 0xFAAF0F2E, 0x41C3B5C0, 0x00000415, + 0xF82F0CAE, 0x700C740C, 0x0D62702C, 0x704CFB2F, + 0xB5D4B5D2, 0x08218F00, 0xC80800DE, 0x2005B802, + 0x90070F81, 0x1490C094, 0xB1003000, 0x73841E00, + 0xC3789007, 0xF60F0E5A, 0x752C700C, 0xF6AF0AC2, + 0x700C714C, 0xF66F0F76, 0x0CCE712C, 0x700CFAEF, + 0xF60F0E3E, 0xD907700C, 0x706C744C, 0x70AC708C, + 0xF66F0FAA, 0x708C70CC, 0x3005145C, 0x732C4080, + 0x4223B890, 0x01032841, 0xF66F0F92, 0xD88070CC, + 0x744CD907, 0x708C706C, 0x0F8270AC, 0x70CCF66F, + 0x0F2A700C, 0x712CF66F, 0xFD0F095A, 0xFD4F0DB6, + 0xD90FC080, 0xFDAF0D02, 0x1600704C, 0x8000708C, + 0x245512D9, 0x244A3801, 0x700C7200, 0x040020A8, + 0x0C137A1D, 0x9140108E, 0x1F832605, 0x012C9038, + 0x7224B340, 0x000076C3, 0x71044000, 0x36042480, + 0x341B1404, 0x78E0C6DA, 0x2482C3F4, 0x228A3102, + 0x10822084, 0x2033070F, 0x250A048E, 0x46702100, + 0x43304450, 0xFF6F08D6, 0xE8084110, 0x710478CF, + 0x2049B822, 0xF0050FCE, 0x10320E45, 0x2648700E, + 0x40D11000, 0x780F7104, 0x7000240A, 0x034020A8, + 0x0407202F, 0x20002115, 0x09139020, 0x900103C5, + 0x10050F0B, 0x700E7706, 0x0892F006, 0x7014FF4F, + 0x206220C0, 0xDD3FE6BF, 0xF01DF6C2, 0xD940E6C0, + 0x45C96E01, 0x004B20CA, 0x240A78C2, 0x20A87000, + 0x21150300, 0x90202340, 0x03C50911, 0x0F0D9001, + 0x71A51005, 0xF007DD3F, 0xFF4F0852, 0x25C27014, + 0x084A1062, 0xE809FF4F, 0x24802132, 0x79026D32, + 0x04022018, 0x4DD1F004, 0x14022602, 0x7E2F78CF, + 0x200C2115, 0x4F109400, 0x94017B10, 0x7F4F78E2, + 0x081A7810, 0x2009FF6F, 0x701400CD, 0x138E2709, + 0xFF6F080A, 0x106225C0, 0x40A17014, 0x138125CA, + 0x710CF213, 0x20300B0F, 0x30431C05, 0x704C712C, + 0x702CF003, 0x0E2A42A2, 0xC380F9AF, 0x3100140C, + 0x710478CA, 0x7CB0B822, 0x0C177B10, 0x24892030, + 0x0E1B1FC3, 0x0B272051, 0xD9592071, 0x0E17F016, + 0x0B232051, 0xD93E2071, 0x0B17F010, 0xD9552071, + 0x0B17F00C, 0xD93A2071, 0xD957F008, 0xD953F006, + 0xD93CF004, 0xD938F002, 0x6909B99F, 0xC2608840, + 0x0A0DC220, 0x23890325, 0xC4200FC3, 0x8900A880, + 0xC020C060, 0x00C50807, 0xA960C320, 0x78E0C7D4, + 0x1600C2EA, 0x8000708E, 0x71141222, 0xDD75D870, + 0x25CA4130, 0x16001001, 0x80007080, 0x08771223, + 0x16000384, 0x80007080, 0x086712D9, 0x79CF03AE, + 0xFDEF0BA2, 0x46004022, 0x742D70EC, 0x702C720D, + 0x03822114, 0xBA0CC808, 0x27157845, 0x702C0042, + 0x02450937, 0x00AE0E2D, 0x7B0561BB, 0x2305BB02, + 0x90380F8C, 0x265A0000, 0x7B541503, 0x0F8B2334, + 0x4DAC8001, 0x800043C3, 0x23F40F60, 0xB46002C3, + 0x71447124, 0x712CF1E6, 0x173F208D, 0x71C5752D, + 0xC6CAF1C3, 0x1CFCC2FA, 0x44D3B6C8, 0x12228000, + 0x14014018, 0x14002080, 0x200C2090, 0x011AA000, + 0x4748002D, 0x0C172140, 0x000E45D3, 0x21400000, + 0x21400816, 0x21540402, 0x21050819, 0x2705055B, + 0x26052557, 0x25052556, 0x46CB2095, 0x00009000, + 0x800041C3, 0x892012D9, 0x040E09D5, 0x2513205A, + 0x800145CB, 0x7F604DAC, 0x23402334, 0x23512840, + 0x21055020, 0x75622612, 0x26C22205, 0xB9027945, + 0xB10079C5, 0x95017F60, 0x25422205, 0x79455020, + 0x79C5B902, 0x7F60B100, 0x22059502, 0x50202582, + 0xB9027945, 0xB10079C5, 0x95037F60, 0x25D22205, + 0x21055020, 0xB9020481, 0xB10079C5, 0x95047F60, + 0x26112100, 0x21964100, 0xC8082008, 0x26C22105, + 0xB8027845, 0xB02078C5, 0x95057F60, 0x25422105, + 0x79455020, 0x79C5B902, 0x7F60B100, 0x21059506, + 0x50202582, 0xB9027945, 0xB10079C5, 0x95077F60, + 0x25C22105, 0x79455020, 0x79C5B902, 0x7F60B100, + 0x21059508, 0x50202651, 0x04412105, 0x2105B902, + 0x90380F81, 0xB1000000, 0x20801401, 0xA000200C, + 0xFFE50720, 0x14047106, 0xC6DA341B, 0x1CFCC2FA, + 0x2482B6C8, 0x45683902, 0xC0414730, 0x700C700E, + 0x31001C90, 0x30801C8C, 0xEB05C040, 0xF80F0EF2, + 0x41DBC040, 0xC0C49007, 0xFF2F0D72, 0x30451900, + 0x30021C0D, 0x702C710C, 0x0BA642A1, 0xC382F9AF, + 0xD825726F, 0x8820B89F, 0x7905881B, 0x2800710C, + 0xB8020400, 0x0400200F, 0x0252782B, 0x16000001, + 0x8000708D, 0x16001222, 0x80007080, 0x75101223, + 0x000D023A, 0x800040C3, 0x880012D9, 0x83402011, + 0x00210224, 0x097E79AF, 0x148CFDEF, 0x1C983000, + 0x20143000, 0x70CD2340, 0x0F962000, 0x04708000, + 0x13002D40, 0x30001C94, 0x30001498, 0x83802011, + 0x40C3F2EF, 0x28F00000, 0xC1017A1B, 0x200B201F, + 0x794AB822, 0x251A40C9, 0x44CB1003, 0x1B3C8000, + 0x1184209A, 0x3089140D, 0x61787161, 0x64197001, + 0x89026097, 0x10300919, 0x14149142, 0x782A3101, + 0xB8227104, 0x10112700, 0xF0044748, 0x4150671F, + 0x12012E40, 0x30001494, 0xC8087905, 0xC0017905, + 0x0412214F, 0xE80A4330, 0x09717361, 0x23001030, + 0x60980200, 0xF0379002, 0x20110F23, 0x1A00255A, + 0x201478D5, 0x20000400, 0x80000F81, 0x70C3BEC4, + 0xC0048000, 0x04441900, 0x2455B0E0, 0x09463A01, + 0x78F0F96F, 0xE807CA05, 0x3A002455, 0xFB2F0A6A, + 0x09AE41E2, 0xE808FC8F, 0x20811600, 0xFB2F0A5A, + 0x3A002455, 0x24002205, 0x2005B802, 0x90000F8F, + 0x24550048, 0xF0773A00, 0x60906419, 0x60388922, + 0x09027810, 0x2455F96F, 0x24003A01, 0x00003F81, + 0x08F2009E, 0x78F0F96F, 0xE806C000, 0x3100149E, + 0x30041CA0, 0xE80ECA05, 0x3A002455, 0xFB2F0A0A, + 0x240041E2, 0x00003F80, 0x09FE009E, 0x41E2FB2F, + 0xFC8F093E, 0x1600E80F, 0x09EE2081, 0x2455FB2F, + 0x24003A00, 0x00003F80, 0x09DE009E, 0x1600FB2F, + 0xCA052081, 0x091AE887, 0x08A1FC8F, 0x24550030, + 0x24553A00, 0x24003A00, 0x00003F81, 0x724C009E, + 0xFD0F08DA, 0x20310F37, 0x3A002455, 0x1A15255A, + 0x800044D3, 0x2515C004, 0x25142395, 0x0F022415, + 0x2400F7EF, 0x1C002554, 0x25002004, 0x80002F80, + 0x1CA0BEC4, 0x180023C4, 0x22050444, 0xBF02240F, + 0x1F922705, 0x00489000, 0xF7EF0ECA, 0x3A002455, + 0x1A00BF86, 0xBF9C2004, 0x3F802400, 0x009E0000, + 0x0EB2BF9F, 0xB700F7CF, 0x30001490, 0x2B40E809, + 0x20052080, 0x90040F80, 0x18000320, 0x71C50444, + 0x0618E689, 0xF008FFC5, 0x3F812400, 0x009E0000, + 0xF1B8714C, 0xFFEF05C3, 0x238D71A5, 0x710E337B, + 0x30051900, 0x39022480, 0x341B1404, 0x78E0C6DA, + 0x1600C3F2, 0x80007091, 0x0AD20004, 0x2482FF2F, + 0x1C053102, 0x710C3002, 0x704C712C, 0xF9AF0902, + 0x2153C380, 0x718E20D1, 0x726E700E, 0x47CB714E, + 0x12208000, 0xB89FD825, 0x881B8820, 0x2C007905, + 0xB8022400, 0x0400200F, 0xF2C1782B, 0x8F038FC2, + 0x017A7610, 0x40C3000D, 0x12D98000, 0x20118800, + 0xF2B38380, 0x13002E40, 0x30881405, 0x04012005, + 0x7825C808, 0x7280244A, 0x706D6892, 0x1F892405, + 0x00A09004, 0x0A0020A8, 0x000040C3, 0x68320A3C, + 0x201F78CC, 0x41C32042, 0x1B3C8000, 0x4061621A, + 0x0184209A, 0x1030080D, 0x60386058, 0xF0069002, + 0x6030611B, 0x60788B62, 0x12710B0F, 0x12832B40, + 0x10041900, 0x7B85F007, 0x0F832305, 0x01E89004, + 0x7165B300, 0x70801600, 0x00EE8000, 0xF4757014, + 0x10100821, 0x6159622D, 0x140C8922, 0x782A3100, + 0x20047104, 0x00000F80, 0xB822FFFC, 0xF004651D, + 0x89A46159, 0x08118F05, 0x720C03A5, 0xF88F080E, + 0xF006710C, 0xF8AF0806, 0x700C710C, 0x4002AF00, + 0xFA2F08B2, 0x451041C1, 0x08AA4002, 0x41C1FA2F, + 0x2B01215F, 0x00002078, 0x7404B802, 0x8F006119, + 0x00002114, 0x700279AF, 0xA8A860F8, 0x20002578, + 0x0CC26841, 0x4002F5EF, 0x20300D17, 0xE8118F00, + 0x20100A3B, 0x73421E00, 0x00508000, 0xE810F02A, + 0x20100A35, 0x73421E00, 0x00FA8000, 0x0A33F022, + 0x1E002010, 0x80007342, 0xF01C0035, 0x20100A2D, + 0x73421E00, 0x00F08000, 0x1E00F014, 0x80007342, + 0xF0100051, 0x73421E00, 0x00FF8000, 0x1E00F00A, + 0x80007342, 0xF0060036, 0x73421E00, 0x00F58000, + 0xF86F0F5A, 0x71C5730C, 0x704EF143, 0x2D3C238D, + 0xC7D2710E, 0x7A00244A, 0x800040C3, 0x20A8C444, + 0x180001C0, 0x20800003, 0x7EE0000E, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_DCCM[] = { + 0x00000000, 0x21500030, 0x00044004, 0x00006000, + 0x00FF56DF, 0x00020000, 0x07000000, 0x08010000, + 0x00000000, 0x00000110, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x10000000, + 0x00000001, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0xD0D00000, 0xDDDDD0D0, + 0x8686DDDD, 0x54548686, 0xB4B45454, 0x2E2EB4B4, + 0x00002E2E, 0x28280000, 0x28282828, 0x00002828, + 0x2E060000, 0x0C0C2E06, 0x10100C0C, 0x02021010, + 0x00000202, 0x00000000, 0x77770000, 0x00007777, + 0x00000000, 0x00000000, 0x24240000, 0x00002424, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x60600000, 0x00006060, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x0000001F, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x57000001, 0x0000004F, 0x00000000, 0x00000000, + 0x00000100, 0x00000000, 0x001E001E, 0x00FF00FF, + 0x000F6E0A, 0x0005000F, 0x00000000, 0x00000000, + 0x005C0032, 0x00E000B6, 0x0164013A, 0x01E801BE, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x01000000, 0x00000000, + 0x00000000, 0x00000000, 0x06400C80, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x050B0000, + 0x00000006, 0x00000000, 0x00000000, 0x08080808, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x010CA635, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000004, 0x00000000, 0x00040000, + 0x00000000, 0x00000000, 0x180F0E0C, 0x4746451E, + 0x004A4948, 0x01000000, 0x00000000, 0x00000000, + 0x00000000, 0x00040000, 0x00000001, 0x00000000, + 0x00000000, 0xFFFFFFFF, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0002F059, 0xFFB50003, + 0x00000001, 0x0001F0B5, 0xF0B30001, 0x00000001, + 0x0001F0B4, 0xF0B00000, 0x00300001, 0x0007F003, + 0xF0040000, 0x00000007, 0x0001FE03, 0xFE040000, + 0x00000001, 0x0007F011, 0xFE210000, 0x00000001, + 0x0001F0B1, 0xFFBE0182, 0x00000001, 0x0001F0BE, + 0xF0A70001, 0x00000001, 0x0001F0A2, 0x00790002, + 0x00400002, 0x00000308, 0x00000560, 0x00000000, + 0x80000DB4, 0x00000309, 0x00000561, 0x00000001, + 0x80000DC5, 0x000E0305, 0x000E0205, 0x00000003, + 0x80000DD6, 0x000E0300, 0x000E0200, 0x00000003, + 0x80000E3C, 0x000E0301, 0x000E0201, 0x00000003, + 0x80000E4F, 0x000E0302, 0x000E0202, 0x00000003, + 0x80000E62, 0x000E0303, 0x000E0203, 0x00000003, + 0x80000E75, 0x000E0304, 0x000E0204, 0x00000002, + 0x80000E88, 0x01FF01FF, 0x000E0000, 0x00000000, + 0x00000063, 0x00000064, 0x00000660, 0x00000000, + 0x80000D87, 0x00000661, 0x00000001, 0x80000DA5, + 0x000E00F0, 0x00000003, 0x80000DE7, 0x000E00F1, + 0x00000003, 0x80000DF8, 0x000E00F2, 0x00000003, + 0x80000E09, 0x000E00F3, 0x00000003, 0x80000E1A, + 0x000E00F4, 0x00000002, 0x80000E2B, 0x000E00F5, + 0x00000003, 0x80000D96, 0x02011210, 0x1C0A1403, + 0x0B112E29, 0x1916150D, 0x180F0E0C, 0x453A131E, + 0x49484746, 0x02006E4A, 0x00000100, 0x02150028, + 0x0085000A, 0x00000000, 0x02150001, 0x0085042B, + 0x0001010B, 0x00020000, 0x0640042B, 0x0190010B, + 0x00010002, 0x06400002, 0x01900855, 0x00030215, + 0x00030001, 0x0ABE0855, 0x02B00215, 0x00010004, + 0x0ABE0004, 0x02B00C80, 0x00050320, 0x00040002, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00280000, + 0x00050215, 0x00000043, 0x00010000, 0x042B0215, + 0x00850043, 0x00000001, 0x042B0001, 0x00850640, + 0x000200C8, 0x00010001, 0x08550640, 0x010B00C8, + 0x00010003, 0x08550002, 0x010B0ABE, 0x00040158, + 0x00020001, 0x0C800ABE, 0x01900158, 0x00010005, + 0x0C800002, 0x01900E95, 0x000601D3, 0x00030001, + 0x10AB0E95, 0x021501D3, 0x00010007, 0x10AB0003, + 0x021512C0, 0x00080258, 0x00030002, 0x157C12C0, + 0x02B00258, 0x00020009, 0x157C0004, 0x02B01770, + 0x000A02EE, 0x00040002, 0x19001770, 0x032002EE, + 0x0002000B, 0x19000004, 0x03201D4C, 0x000C03AA, + 0x00050003, 0x21551D4C, 0x042B03AA, 0x0003000D, + 0x21550006, 0x042B2580, 0x000E04B0, 0x00070003, + 0x02150028, 0x0085000A, 0x00040004, 0x00010001, + 0x00030001, 0x02150004, 0x0085042B, 0x0004010B, + 0x00000006, 0x00020002, 0x00050003, 0x0640042B, + 0x0190010B, 0x00080006, 0x00030001, 0x00040002, + 0x06400006, 0x01900855, 0x00080215, 0x0002000A, + 0x00030004, 0x00070004, 0x0ABE0855, 0x02B00215, + 0x000E0008, 0x00070001, 0x00040004, 0x0ABE0008, + 0x02B00C80, 0x000A0320, 0x00030010, 0x00040009, + 0x00080004, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00280000, 0x00050215, + 0x00020043, 0x00000002, 0x00010000, 0x00030002, + 0x042B0215, 0x00850043, 0x00030002, 0x00010000, + 0x00020001, 0x042B0003, 0x00850640, 0x000300C8, + 0x00010004, 0x00010002, 0x00030002, 0x08550640, + 0x010B00C8, 0x00050004, 0x00020001, 0x00020002, + 0x08550004, 0x010B0ABE, 0x00040158, 0x00010007, + 0x00020004, 0x00040002, 0x0C800ABE, 0x01900158, + 0x00080005, 0x00050002, 0x00020002, 0x0C800004, + 0x01900E95, 0x000601D3, 0x00020009, 0x00030005, + 0x00050002, 0x10AB0E95, 0x021501D3, 0x000B0006, + 0x00070002, 0x00020003, 0x10AB0005, 0x021512C0, + 0x00070258, 0x0003000C, 0x00030008, 0x00050002, + 0x157C12C0, 0x02B00258, 0x000E0008, 0x00090003, + 0x00020004, 0x157C0006, 0x02B01770, 0x000902EE, + 0x0004000F, 0x0004000A, 0x00060002, 0x19001770, + 0x032002EE, 0x00100009, 0x000B0004, 0x00020004, + 0x19000006, 0x03201D4C, 0x000B03AA, 0x00050013, + 0x0005000D, 0x00070002, 0x21551D4C, 0x042B03AA, + 0x0016000C, 0x000F0005, 0x00020006, 0x21550008, + 0x042B2580, 0x000E04B0, 0x00060018, 0x00070010, + 0x00090002, 0x02150028, 0x0085000A, 0x00060006, + 0x00000006, 0x00000000, 0x00060001, 0x02150007, + 0x0085042B, 0x0008010B, 0x00080008, 0x00000000, + 0x00020000, 0x00090007, 0x0640042B, 0x0190010B, + 0x000A000A, 0x0001000C, 0x00030001, 0x00080002, + 0x0640000A, 0x01900855, 0x000C0215, 0x000E000E, + 0x00040002, 0x00030004, 0x000B0008, 0x0ABE0855, + 0x02B00215, 0x00100010, 0x00030012, 0x00050003, + 0x000A0004, 0x0ABE000E, 0x02B00C80, 0x00120320, + 0x00140014, 0x00070005, 0x00040007, 0x000E000A, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00280000, 0x00050215, + 0x00030043, 0x00030003, 0x00000000, 0x00010000, + 0x00040003, 0x042B0215, 0x00850043, 0x00040004, + 0x00000004, 0x00000000, 0x00040001, 0x042B0005, + 0x00850640, 0x000500C8, 0x00050005, 0x00010001, + 0x00010002, 0x00050004, 0x08550640, 0x010B00C8, + 0x00070006, 0x00010007, 0x00020002, 0x00040002, + 0x08550006, 0x010B0ABE, 0x00080158, 0x00090008, + 0x00020002, 0x00020003, 0x00070005, 0x0C800ABE, + 0x01900158, 0x000A0009, 0x0003000A, 0x00040004, + 0x00050002, 0x0C800007, 0x01900E95, 0x000A01D3, + 0x000C000B, 0x00040003, 0x00030005, 0x00080005, + 0x10AB0E95, 0x021501D3, 0x000D000C, 0x0004000E, + 0x00060005, 0x00060003, 0x10AB0009, 0x021512C0, + 0x000D0258, 0x000F000E, 0x00060005, 0x00030007, + 0x00090006, 0x157C12C0, 0x02B00258, 0x0010000F, + 0x00060011, 0x00080007, 0x00060004, 0x157C000A, + 0x02B01770, 0x001002EE, 0x00130011, 0x00070006, + 0x00040009, 0x000B0007, 0x19001770, 0x032002EE, + 0x00120011, 0x00070014, 0x000A0008, 0x00070004, + 0x1900000B, 0x03201D4C, 0x001403AA, 0x00180016, + 0x00090007, 0x0005000B, 0x000E0009, 0x21551D4C, + 0x042B03AA, 0x00190017, 0x0008001A, 0x000B000A, + 0x000A0006, 0x21550010, 0x042B2580, 0x001904B0, + 0x001D001C, 0x000B0008, 0x0007000C, 0x0012000B, + 0x00000A05, 0x50000000, 0x446B6C63, 0x6F434143, + 0x43416564, 0x63500030, 0x43446B6C, 0x646F4341, + 0x53514465, 0x6C635000, 0x4143446B, 0x65646F43, + 0x00314341, 0x6B6C6350, 0x4F444344, 0x65736666, + 0x30434174, 0x6C635000, 0x4443446B, 0x7366664F, + 0x43417465, 0x63500031, 0x43446B6C, 0x66664F44, + 0x44746573, 0x50005351, 0x446B6C63, 0x6F434143, + 0x71446564, 0x00306E4C, 0x6B6C6350, 0x43414344, + 0x4465646F, 0x316E4C71, 0x6C635000, 0x4143446B, + 0x65646F43, 0x6E4C7144, 0x63500032, 0x43446B6C, + 0x646F4341, 0x4C714465, 0x5000336E, 0x446B6C63, + 0x6F434143, 0x71446564, 0x00346E4C, 0x6B6C6350, + 0x4F444344, 0x65736666, 0x4C714474, 0x5000306E, + 0x446B6C63, 0x664F4443, 0x74657366, 0x6E4C7144, + 0x63500031, 0x43446B6C, 0x66664F44, 0x44746573, + 0x326E4C71, 0x6C635000, 0x4443446B, 0x7366664F, + 0x71447465, 0x00336E4C, 0x6B6C6350, 0x4F444344, + 0x65736666, 0x4C714474, 0x0000346E, 0x04050607, + 0x00010203, 0x0C0B0A09, 0xB50F0E0D, 0x000001FF, + 0x01F0B500, 0xB3000100, 0x000001F0, 0x01F0B400, + 0xB0000100, 0x300001F0, 0x07F00300, 0x04000000, + 0x000007F0, 0x01FE0300, 0x04000000, 0x000001FE, + 0x07F01100, 0x21000000, 0x000001FE, 0x01FFBE00, + 0xBE000000, 0x010001F0, 0x01F0A700, 0xA2000000, + 0x020001F0, 0x02007900, 0x00004000, 0x0001008B, + 0xF05F0000, 0x00000001, 0x0001FFB5, 0xF0B30001, + 0x01FF0001, 0x0001F0B4, 0xF0B001FF, 0x00300001, + 0x0007F003, 0xF0040000, 0x00000007, 0x0001FE03, + 0xFE040000, 0x00000001, 0x0007F011, 0xFE210000, + 0x00000001, 0x0001F0B1, 0xF0A70002, 0x00000001, + 0x000E000F, 0x000C000D, 0x000A000B, 0x00080009, + 0x00060007, 0x00040005, 0x00020003, 0x00000001, + 0x00110010, 0x00130012, 0x00150014, 0x00170016, + 0x00190018, 0x001B001A, 0x001D001C, 0x001F001E, + 0xEF77DBB7, 0xFBDFF7BD, 0xBDDFB76F, 0xBDFFBDEF, + 0x00000200, 0x00000200, 0x00000200, 0x00000200, + 0x00000010, 0x00000010, 0x00000010, 0x00000010, + 0x0001FFB5, 0xF0B30001, 0x00000001, 0x0001F0B4, + 0xF0B90000, 0x00010001, 0x0001F0BA, 0xF0B10001, + 0x00020001, 0x0007F003, 0xF0040000, 0x00000007, + 0x0001FE03, 0xFE040000, 0x00000001, 0x0007F011, + 0xFE210000, 0x00000001, 0x0007F010, 0xFE200002, + 0x00020001, 0x0007F01B, 0xF01CFFFF, 0xFFFF0007, + 0x0001FE2A, 0xFE2BFFFF, 0xFFFF0001, 0x00020079, + 0xFFB50040, 0x00010001, 0x0001F0B3, 0xF0B40000, + 0x00000001, 0x0001F0B9, 0xF0BA0001, 0x00010001, + 0x0001F0B1, 0xF0B00002, 0x00300001, 0x0007F003, + 0xF0040000, 0x00000007, 0x0001FE03, 0xFE040000, + 0x00000001, 0x0007F011, 0xFE210000, 0x00000001, + 0x0007F010, 0xFE200002, 0x00020001, 0x0007F01B, + 0xF01CFFFF, 0xFFFF0007, 0x0001FE2A, 0xFE2BFFFF, + 0xFFFF0001, 0x00020079, 0x00000040, 0x08840884, + 0x00000020, 0x00010010, 0x00010012, 0x0001007A, + 0x00010028, 0x00060000, 0x50005000, 0x02008050, + 0x00000000, 0x00060080, 0x3C5A5555, 0x00600000, + 0x00000000, 0x00000000, 0x00000070, 0x00000075, + 0x00000026, 0x000000A0, 0x000000A1, 0x000000A4, + 0x000000A5, 0x0A030201, 0x0E0D0C0B, 0x1413120F, + 0x18171615, 0x1E1C1A19, 0x2221201F, 0x2E292825, + 0x4746453A, 0x004A4948, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_ACSM[] = { + 0x0000C028, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000C858, 0x00100000, 0x0000E088, 0x00100000, + 0x0000E038, 0x00100000, 0x0000C858, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x0000C028, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000C858, 0x00100000, 0x0000E208, 0x00100000, + 0x0000E038, 0x00100000, 0x0000C858, 0x00100000, + 0x0000C208, 0x00100000, 0x00000000, 0x00000000, + 0x0000C040, 0x00100000, 0x00000000, 0x00100000, + 0x0000C068, 0x00100000, 0x00000000, 0x00000000, + 0x0000C2F0, 0x00100000, 0x00000000, 0x00000000, + 0x0000C370, 0x00100000, 0x00000000, 0x00000000, + 0x0000D2D8, 0x00100000, 0x0000E008, 0x00100000, + 0x00000000, 0x7B000000, 0x00000000, 0x00000000, + 0x0000C0F0, 0x00100000, 0x0000CFD8, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D058, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D0D8, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D158, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x04000001, 0x08004050, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x08034050, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x08000000, + 0x00000000, 0x04000000, 0x0000407C, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x04100001, 0x08008050, 0x00100000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x08038050, 0x00100000, + 0x00000000, 0x1F000000, 0x00000000, 0x08000000, + 0x00000000, 0x04000000, 0x0000807C, 0x00100000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x00000001, 0x08004050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08004050, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000407C, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x1C000000, + 0x0D00802C, 0x00100001, 0x08008050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08008050, 0x00100000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000807C, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x28000000, + 0x0D00402C, 0x00000001, 0x08035198, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08035218, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000407C, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x00100001, 0x08039198, 0x00100000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08039218, 0x00100000, + 0x00000000, 0x1B000000, 0x00000000, 0x08000000, + 0x00000000, 0x00000000, 0x0000807C, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x04000000, + 0x0000D2D8, 0x00100000, 0x0000E008, 0x00100000, + 0x00000000, 0x7B000000, 0x00000000, 0x00000000, + 0x0000C0F0, 0x00100000, 0x0000CFD8, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D058, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D0D8, 0x00100000, + 0x0000C088, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x3B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x0000D158, 0x00100000, + 0x0000C008, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x04000001, 0x08004050, 0x00000000, + 0x00000000, 0x04000000, 0x08034050, 0x00000000, + 0x00000000, 0x4F000000, 0x00000000, 0x08000000, + 0x0000407C, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x04100001, 0x08008050, 0x00100000, + 0x00000000, 0x04000000, 0x08038050, 0x00100000, + 0x00000000, 0x4F000000, 0x00000000, 0x08000000, + 0x0000807C, 0x04100000, 0x00000000, 0x00000000, + 0x00000000, 0x1F000000, 0x00000000, 0x00000000, + 0x00000000, 0x04000001, 0x00000000, 0x00000000, + 0x00000000, 0x04000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00402C, 0x00000001, 0x08004050, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x08034050, 0x00000000, + 0x00000000, 0x00000000, 0x08004050, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000407C, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x1C000000, + 0x0D00802C, 0x00100001, 0x08008050, 0x00100000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x08038050, 0x00100000, + 0x00000000, 0x00000000, 0x08008050, 0x00100000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000807C, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x28000000, + 0x0D00402C, 0x00000001, 0x08035198, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08035218, 0x00000000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000407C, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0D00802C, 0x00100001, 0x08039198, 0x00100000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x08039218, 0x00100000, + 0x00000000, 0x4B000000, 0x00000000, 0x08000000, + 0x0000807C, 0x00100000, 0x00000000, 0x00000000, + 0x00000000, 0x1B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x6B000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_A[] = { + 0x00000001, 0x00000019, 0x0000002E, 0x00000043, + 0x0000005B, 0x00000070, 0x00000085, 0x0000009D, + 0x000000B2, 0x000000C7, 0x000000DF, 0x000000F4, + 0x00000109, 0x00000113, 0x00000115, 0x00000119, +}; + +static const u32 DATA_B[] = { + 0x00000018, 0x0000002D, 0x00000042, 0x0000005A, + 0x0000006F, 0x00000084, 0x0000009C, 0x000000B1, + 0x000000C6, 0x000000DE, 0x000000F3, 0x00000108, + 0x00000112, 0x00000114, 0x00000118, 0x0000011A, +}; + +static const u32 ACSM_0[] = { + 0x0000C9D8, 0x00000000, 0x0000C808, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C958, 0x00000000, 0x0000C608, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C0D8, 0x00000000, 0x0000E848, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C158, 0x00000000, 0x0000EEC8, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C1D8, 0x00000000, 0x0000C348, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C558, 0x00000000, 0x0000EA08, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000C5D8, 0x00000000, 0x0000DA48, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x000048D8, 0x00000000, 0x00004308, 0x00000000, + 0x000088D8, 0x00000000, 0x00009708, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000CA58, 0x00000000, 0x0000C108, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000CB58, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000D4D8, 0x00000000, 0x0000F008, 0x00000000, + 0x00000000, 0x5B000000, 0x00000000, 0x00000000, + 0x0000DD58, 0x00000000, 0x0000C008, 0x00000000, +}; + +static const u32 ACSM_123[] = { + 0x0000C9D8, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C958, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C0D8, 0x00000000, 0x0000E808, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C158, 0x00000000, 0x0000EA88, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C1D8, 0x00000000, 0x0000C308, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C558, 0x00000000, 0x0000EA08, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000C5D8, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x000048D8, 0x00000000, 0x00004008, 0x00000000, + 0x000088D8, 0x00000000, 0x00009408, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000CA58, 0x00000000, 0x0000C108, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000CB58, 0x00000000, 0x0000C008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000D4D8, 0x00000000, 0x0000F008, 0x00000000, + 0x00000000, 0x2B000000, 0x00000000, 0x00000000, + 0x0000DD58, 0x00000000, 0x0000C008, 0x00000000, +}; + +static const u32 DATA_C[] = { + 0x00000000, 0x000000FE, 0x000000A8, 0x0000F040, + 0x0000F040, 0x00000000, 0x0000FFFF, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_1[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x0000084F, + 0x0000084F, 0x0000082B, 0x0000082B, 0x0000084F, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00001810, 0x00001810, 0x00000428, 0x0000192C, + 0x0000181C, 0x0000181C, 0x00000434, 0x00003938, + 0x00001808, 0x00001808, 0x00000420, 0x00001124, +}; + +static const u32 DATA_3_2[] = { + 0x000040A0, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x00000000, 0x00000000, + 0x00000000, 0x0000024E, 0x0000004E, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x0000024E, 0x0000004E, 0x0000006F, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_3[] = { + 0x00000086, 0x00000190, 0x00000A69, 0x00000058, + 0x0000001B, 0x00000000, 0x00000043, 0x00000000, + 0x00000017, 0x0000004F, 0x00000006, 0x00000006, + 0x0000000E, 0x00000068, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_4[] = { + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000009, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x0000001C, 0x0000071C, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000077, 0x00000707, 0x00000030, 0x00003300, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000099, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DATA_3_5[] = { + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000009, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000001, 0x0000001C, 0x0000071C, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000077, 0x00007777, 0x00000030, 0x00003300, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000099, 0x00000000, 0x00000000, 0x00000000, +}; + +static const u32 DMAC_TRANS_PIE[] = { + 0x3f7ab480, 0x00016420, 0x00000400, 0x00000000, + 0x80000480, 0x00000fc0, 0x04000c00, 0x00000000, + 0x84000480, 0x00000c00, 0x04000800, 0x00000000, + 0x84000080, 0x00000c00, 0x000001e0, 0x00000000, + 0x80068200, 0x0000400f, 0x00008d40, 0x00000000, + 0xa0000480, 0x00002420, 0x04000400, 0x00000000, + 0x9c001ca0, 0x00001c04, 0xa8000880, 0x00001c06, + 0x80010080, 0x00001c04, 0x04000400, 0x00000000, + 0x80010480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000040, 0x00006000, 0xa0000080, 0x00002420, + 0x00001020, 0x00000000, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x00003020, 0x00000000, + 0x80000080, 0x00001c04, 0xa8000880, 0x00001c06, + 0x80010880, 0x00001c04, 0x04000400, 0x00000000, + 0x80010c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00001020, 0x00000000, 0x00002c20, 0x00000000, + 0x00002c20, 0x00000000, 0x00002c20, 0x00000000, + 0x80000080, 0x00001c04, 0x000001e0, 0x00000000, + 0xa8000480, 0x00001c04, 0x04000400, 0x00000000, + 0x40004200, 0x00004000, 0x00011140, 0x00000000, + 0xc80038a0, 0x00001c01, 0xcc003ca0, 0x00001c01, + 0xa40000a0, 0x00001c06, 0xa8001c80, 0x00001c06, + 0x80051080, 0x00001c04, 0x04000400, 0x00000000, + 0x80051480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xcc000080, 0x00001c01, 0xa8001c80, 0x00001c06, + 0x80051880, 0x00001c04, 0x04000400, 0x00000000, + 0x80051c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xc8000080, 0x00001c01, 0xcc003ca0, 0x00001c01, + 0xa8001c80, 0x00001c06, 0x80052080, 0x00001c04, + 0x04000400, 0x00000000, 0x80052480, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0xc80038a0, 0x00001c01, + 0x54000091, 0x00018fc0, 0x54000091, 0x00014fc0, + 0xf0000091, 0x000187c1, 0xf0000091, 0x000147c1, + 0x08000611, 0x00001800, 0x00013d71, 0x00000000, + 0x04000911, 0x0001a420, 0x04001000, 0x00000000, + 0x00000a11, 0x00001800, 0x00017551, 0x00000000, + 0x00014571, 0x00000000, 0x00000611, 0x00001800, + 0x00017571, 0x00000000, 0x24000491, 0x0001e420, + 0x000021d1, 0x00000000, 0x00001031, 0x00000000, + 0x00001031, 0x00000000, 0x00002c31, 0x00000000, + 0xa8000091, 0x00001c06, 0x80016891, 0x00001c04, + 0x04000400, 0x00000000, 0x80016c91, 0x00001c04, + 0x04000800, 0x00000000, 0x00000851, 0x00006000, + 0x80000091, 0x00001c04, 0xa8000080, 0x00001c04, + 0x04000800, 0x00000000, 0x000001e0, 0x00000000, + 0xa8000080, 0x00001c06, 0x80012880, 0x00001c04, + 0x04000400, 0x00000000, 0x80012c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x000001e0, 0x00000000, + 0x00080200, 0x0000400e, 0x0001b540, 0x00000000, + 0x00020200, 0x0000400e, 0x0001b540, 0x00000000, + 0x80068200, 0x0000400f, 0x30000cc0, 0x000007c4, + 0x000001e0, 0x00000000, 0x00100600, 0x00000010, + 0x2c0004c0, 0x000003c0, 0x8c0028a0, 0x00017bc1, + 0xa0000480, 0x00002420, 0x04000400, 0x00000000, + 0x8c0014a0, 0x000143c1, 0xa0000080, 0x00002420, + 0x78000480, 0x000003d8, 0x7c000480, 0x000007f8, + 0x08000080, 0x00000fe0, 0x08000080, 0x000007e0, + 0x00080600, 0x00000008, 0x000004c0, 0x00014fc4, + 0x000004c0, 0x000147c4, 0x00002420, 0x00000000, + 0x08000480, 0x00000fe0, 0x08000480, 0x000007e0, + 0x00000080, 0x00014fc4, 0x00000080, 0x000147c4, + 0x78000080, 0x000003d8, 0x7c000080, 0x000007f8, + 0x8c002ca0, 0x00017bc1, 0xa0000480, 0x00002420, + 0x04000400, 0x00000000, 0x8c0018a0, 0x000143c1, + 0xa0000080, 0x00002420, 0x2c000080, 0x00000000, + 0x2c000080, 0x00000040, 0x2c000080, 0x00000080, + 0x2c000080, 0x000000c0, 0x2c000080, 0x00000100, + 0x2c000080, 0x00000140, 0x00200600, 0x00000020, + 0x2c0000c0, 0x000001c0, 0x2c0000c0, 0x00000200, + 0x2c0000c0, 0x00000240, 0x2c0000c0, 0x00000280, + 0x2c0000c0, 0x000002c0, 0x2c0000c0, 0x00000300, + 0xc4000880, 0x000007c0, 0x04000400, 0x00000000, + 0x0c000480, 0x00000fc4, 0x04002000, 0x00000000, + 0x0c000480, 0x000007c4, 0x04002000, 0x00000000, + 0x0c000080, 0x00000fc4, 0x0c000080, 0x000007c4, + 0xc4000080, 0x000007c0, 0x04000400, 0x00000000, + 0xe0000480, 0x00000803, 0x04002000, 0x00000000, + 0x04000600, 0x00000400, 0x265a58c0, 0x000187c8, + 0x58000080, 0x000007c0, 0x04000400, 0x00000000, + 0xe0000080, 0x00000803, 0x04002000, 0x00000000, + 0x000001e0, 0x00000000, 0x50000080, 0x00001c01, + 0x40000480, 0x00002c0c, 0xc4000080, 0x000007c0, + 0x2c000080, 0x000007c2, 0x8c200080, 0x00000fc2, + 0x00200600, 0x00000020, 0x880c0080, 0x00000c02, + 0x880c00c0, 0x00000c42, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0x800c0080, 0x00000fc2, 0x04000800, 0x00000000, + 0x98000480, 0x00000fc2, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0x80fffc80, 0x00000fc2, + 0x30000080, 0x000007c4, 0x00010600, 0x00000001, + 0x0002fd40, 0x00000000, 0x80068200, 0x0000400f, + 0x00030160, 0x00000000, 0x0001a1c0, 0x00000000, + 0xe0000480, 0x00000803, 0x04001c00, 0x00000000, + 0x28000080, 0x00000fc0, 0x88000480, 0x00000802, + 0x04000400, 0x00000000, 0x5c000080, 0x000007c2, + 0x02000600, 0x00000200, 0x2c0010c0, 0x00003bc1, + 0x2c001880, 0x00003bc1, 0x18001880, 0x00003bc1, + 0x1c001880, 0x00003bc1, 0x20001880, 0x00003bc1, + 0x24001880, 0x00003bc1, 0x28001880, 0x00003bc1, + 0x00020200, 0x0000400e, 0x00036d40, 0x00000000, + 0x40004600, 0x00000000, 0x00035940, 0x00000000, + 0x04000900, 0x0001a420, 0x04001000, 0x00000000, + 0x40004a00, 0x00000000, 0x0c0010e0, 0x00001800, + 0x0c0000c0, 0x00001800, 0x04000480, 0x00001800, + 0x04000800, 0x00000000, 0x08000480, 0x00001800, + 0x04000800, 0x00000000, 0x000001e0, 0x00000000, + 0x9c000cb1, 0x00001c01, 0x9c0010b1, 0x00001c03, + 0x24000091, 0x00001c01, 0x00000051, 0x00004000, + 0x00039531, 0x00000000, 0x40001a01, 0x00000000, + 0x00039561, 0x00000000, 0x24000081, 0x00001c01, + 0x00000041, 0x00004000, 0x000001e0, 0x00000000, + 0x84000900, 0x0000241c, 0xc0014200, 0x0000c001, + 0x0003ad40, 0x00000000, 0x04001000, 0x00000000, + 0x2c0008a0, 0x00000802, 0x000001e0, 0x00000000, + 0x40000480, 0x00002c0c, 0x04000400, 0x00000000, + 0x04000080, 0x00002c00, 0x04000400, 0x00000000, + 0x00020200, 0x0000400e, 0x00044540, 0x00000000, + 0x40004600, 0x00000000, 0x040004c0, 0x00001800, + 0x080004c0, 0x00001800, 0x00044540, 0x00000000, + 0x08000080, 0x00001800, 0x04000400, 0x00000000, + 0x04000080, 0x00001800, 0x00000081, 0x00001800, + 0x04000400, 0x00000000, 0x88000480, 0x00000802, + 0x04000800, 0x00000000, 0x0c000900, 0x00001800, + 0x04001000, 0x00000000, 0x00010a00, 0x00000001, + 0x00042140, 0x00000000, 0x0c000c80, 0x00001800, + 0x00000020, 0x00000000, 0x00000020, 0x00000000, + 0x0c000880, 0x00001800, 0x00000020, 0x00000000, + 0x0c000080, 0x00001800, 0x00044920, 0x00000000, + 0x0c001c80, 0x00001800, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x0c001880, 0x00001800, + 0x00001020, 0x00000000, 0x00001020, 0x00000000, + 0x00001020, 0x00000000, 0x0c001080, 0x00001800, + 0x00044920, 0x00000000, 0x00000080, 0x00001800, + 0x00200600, 0x00000020, 0x0004a160, 0x00000000, + 0x18000080, 0x00003bc1, 0x1c000080, 0x00003bc1, + 0x20000080, 0x00003bc1, 0x24000080, 0x00003bc1, + 0x28000080, 0x00003bc1, 0x2c000880, 0x00003801, + 0x2c001080, 0x00003841, 0x2c000880, 0x00003881, + 0x2c001080, 0x000038c1, 0x2c000880, 0x00003901, + 0x2c001080, 0x00003941, 0x2c000880, 0x00003981, + 0x2c001080, 0x000039c1, 0x02000600, 0x00000200, + 0x2c0010c0, 0x00003bc1, 0x58000080, 0x000003cf, + 0x5c000080, 0x000003cf, 0x5c000880, 0x000000cf, + 0x5c000880, 0x0000028f, 0x00052d20, 0x00000000, + 0x18000080, 0x00003801, 0x18000080, 0x00003841, + 0x18000080, 0x00003881, 0x18000080, 0x000038c1, + 0x1c000080, 0x00003801, 0x1c000080, 0x00003841, + 0x1c000080, 0x00003881, 0x1c000080, 0x000038c1, + 0x20000080, 0x00003801, 0x20000080, 0x00003841, + 0x20000080, 0x00003881, 0x20000080, 0x000038c1, + 0x24000080, 0x00003801, 0x24000080, 0x00003841, + 0x24000080, 0x00003881, 0x24000080, 0x000038c1, + 0x28000080, 0x00003841, 0x28000080, 0x000038c1, + 0x2c000880, 0x00003801, 0x2c001080, 0x00003841, + 0x2c000880, 0x00003881, 0x2c001080, 0x000038c1, + 0x02000600, 0x00000200, 0x2c0010c0, 0x00003bc1, + 0x58000080, 0x0000000f, 0x5c000080, 0x0000000f, + 0x58000080, 0x0000004f, 0x5c000080, 0x0000004f, + 0x58000080, 0x0000008f, 0x5c000080, 0x0000008f, + 0x58000080, 0x000000cf, 0x58000080, 0x0000010f, + 0x5c000080, 0x0000010f, 0x58000080, 0x0000014f, + 0x5c000080, 0x0000014f, 0x20000080, 0x00002bcc, + 0x00053d31, 0x00000000, 0x40001a00, 0x00000000, + 0x00053d60, 0x00000000, 0x040030a0, 0x00002c00, + 0x88000080, 0x00000802, 0x5c1ffc80, 0x000007c2, + 0x00800600, 0x00000080, 0xbc000900, 0x00016c0c, + 0x040000c0, 0x00002424, 0x040080e0, 0x00002424, + 0x04000000, 0x00000000, 0x98000095, 0x00002c0c, + 0x9c000095, 0x00002c0c, 0x98001cb5, 0x00002c0c, + 0x9c0020b5, 0x00002c0c, 0x98000095, 0x00002c0c, + 0x9c000095, 0x00002c0c, 0x40000095, 0x00002c0c, + 0x00000605, 0x00002000, 0x400000c5, 0x00002c0c, + 0x800004c5, 0x00002c0c, 0x800000c5, 0x00002c0c, + 0x040000e5, 0x00002c00, 0xbc0000e5, 0x00016c0c, + 0x04000000, 0x00000000, 0x9bfe00e5, 0x00002c0c, + 0x9ffe00e5, 0x00002c0c, 0x9bfe04e5, 0x00002c0c, + 0x9ffe04e5, 0x00002c0c, 0x9bfe00e5, 0x00002c0c, + 0x9ffe00e5, 0x00002c0c, 0x400004e5, 0x00002c0c, + 0x04000400, 0x00000000, 0xbc0008a5, 0x00016c0c, + 0x000001e0, 0x00000000, 0xe8030c80, 0x00001c01, + 0x04000400, 0x00000000, 0xe8000080, 0x00001c01, + 0x000001e0, 0x00000000, 0x88000080, 0x00000802, + 0x04000c00, 0x00000000, 0x0000cc80, 0x00000808, + 0x1c000480, 0x00000fc1, 0x1c000080, 0x00000fc1, + 0x1c000480, 0x000007c1, 0x1c000080, 0x000007c1, + 0x00000080, 0x00000808, 0x50000080, 0x00001c01, + 0xb8000480, 0x00000801, 0x04000400, 0x00000000, + 0x00040600, 0x00000004, 0x598000e0, 0x000007c0, + 0x28000480, 0x00000fc0, 0x04001000, 0x00000000, + 0xe0000080, 0x00000803, 0x04001400, 0x00000000, + 0x88000880, 0x00000802, 0x00000c20, 0x00000000, + 0x40004600, 0x00000000, 0x00062160, 0x00000000, + 0x1c000880, 0x00000fc1, 0x1c000080, 0x00000fc1, + 0x1c000880, 0x000007c1, 0x1c000080, 0x000007c1, + 0x04003c00, 0x00000000, 0x00040600, 0x00000004, + 0x00064140, 0x00000000, 0x0001bdc0, 0x00000000, + 0x28000080, 0x00000fc0, 0x80000080, 0x00000fc2, + 0x98000080, 0x00000fc2, 0x24000080, 0x000007c2, + 0x28000080, 0x000007c2, 0x883c0080, 0x00000fc2, + 0x80040200, 0x0000400f, 0x00067940, 0x00000000, + 0x00080200, 0x0000400e, 0x00067940, 0x00000000, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0xe8030c81, 0x00001c01, 0x04000800, 0x00000000, + 0xe8000081, 0x00001c01, 0x04000400, 0x00000000, + 0x40001a01, 0x00000000, 0x0006a541, 0x00000000, + 0xa0000481, 0x00002420, 0x04000400, 0x00000000, + 0x40003201, 0x00000000, 0x0006c541, 0x00000000, + 0x0006a561, 0x00000000, 0x00001c21, 0x00000000, + 0xa0000081, 0x00002420, 0x04000400, 0x00000000, + 0x00020601, 0x00000002, 0xe8030cc1, 0x00001c01, + 0x04000800, 0x00000000, 0xe80000c1, 0x00001c01, + 0x04000400, 0x00000000, 0xa0000081, 0x00002420, + 0x04000400, 0x00000000, 0xe8030c91, 0x00001c01, + 0x04000800, 0x00000000, 0xe8000091, 0x00001c01, + 0x04000400, 0x00000000, 0xa8000480, 0x00001c04, + 0x04000400, 0x00000000, 0x18000081, 0x0001e420, + 0x40006611, 0x00000000, 0x0006f551, 0x00000000, + 0x000021d1, 0x00000000, 0xa0000491, 0x00002420, + 0x04000400, 0x00000000, 0x540020b1, 0x00014fc0, + 0xf00024b1, 0x000147c1, 0xa0000091, 0x00002420, + 0x000001e0, 0x00000000, 0xa8000080, 0x00001c06, + 0x80013080, 0x00001c04, 0x04000400, 0x00000000, + 0x80013480, 0x00001c04, 0x04000800, 0x00000000, + 0x04001c00, 0x00000000, 0x80000080, 0x00001c04, + 0x00000420, 0x00000000, 0xa8000080, 0x00001c06, + 0x80013880, 0x00001c04, 0x04000400, 0x00000000, + 0x80013c80, 0x00001c04, 0x04000800, 0x00000000, + 0x04001c00, 0x00000000, 0x80000080, 0x00001c04, + 0x000001e0, 0x00000000, 0x20000086, 0x0001c7c4, + 0x9e000480, 0x000007c2, 0xc4060080, 0x000007c2, + 0xd4000480, 0x000007c2, 0xe4000480, 0x000007c2, + 0x9c003080, 0x00001c04, 0x7c000080, 0x0001c7c1, + 0x88000c80, 0x000007c2, 0x64000c80, 0x00000801, + 0x90000880, 0x000007c2, 0xec0ffc80, 0x000007c2, + 0xec000080, 0x000007c2, 0xf8000080, 0x000007fe, + 0xf8000480, 0x000007c2, 0xf8000480, 0x000007d2, + 0xa8001080, 0x00001c06, 0x80014880, 0x00001c04, + 0x04000400, 0x00000000, 0x80014c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0xf8000080, 0x000007c2, + 0xf8000080, 0x000007d2, 0xec0ffc80, 0x000007c2, + 0xec000080, 0x000007c2, 0xf8000480, 0x000007c6, + 0xf8000480, 0x000007d6, 0xa8001080, 0x00001c06, + 0x80015080, 0x00001c04, 0x04000400, 0x00000000, + 0x80015480, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0xf8000080, 0x000007c6, 0xf8000080, 0x000007d6, + 0x64000880, 0x00000801, 0x00001420, 0x00000000, + 0xc4000480, 0x000007c0, 0x04001000, 0x00000000, + 0xc4000080, 0x000007c0, 0x04000600, 0x00000400, + 0x24c8c8c0, 0x000147c8, 0x80000480, 0x00000802, + 0x04000400, 0x00000000, 0x80000080, 0x00000802, + 0x90000080, 0x000007c2, 0x98000c80, 0x000007c2, + 0xa8001080, 0x00001c06, 0x80015880, 0x00001c04, + 0x04000400, 0x00000000, 0x80015c80, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x04000800, 0x00000000, + 0x98000080, 0x000007c2, 0x88000080, 0x000007c2, + 0x64000080, 0x00000801, 0x7c000480, 0x0001c7c1, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0x00001820, 0x00000000, 0x90000480, 0x000007c2, + 0xa8001080, 0x00001c06, 0x80016080, 0x00001c04, + 0x04000400, 0x00000000, 0x80016480, 0x00001c04, + 0x04000800, 0x00000000, 0x00000840, 0x00006000, + 0x80000080, 0x00001c04, 0x04000800, 0x00000000, + 0x80000480, 0x00000802, 0x04000400, 0x00000000, + 0x80000080, 0x00000802, 0x90000080, 0x000007c2, + 0x04000800, 0x00000000, 0xe4000480, 0x00000801, + 0x04000800, 0x00000000, 0xe4000080, 0x00000801, + 0x04000800, 0x00000000, 0xa8000080, 0x00001c04, + 0x50000480, 0x00001c01, 0x20000486, 0x0001c7c4, + 0x000001e0, 0x00000000, 0x80008600, 0x00000000, + 0x0008d560, 0x00000000, 0x80000480, 0x00000802, + 0x04000400, 0x00000000, 0x80000080, 0x00000802, + 0x04000400, 0x00000000, 0xe4000480, 0x00000801, + 0x04000800, 0x00000000, 0xe4000080, 0x00000801, + 0xa8000080, 0x00001c04, 0xb8000080, 0x00000801, + 0x04000800, 0x00000000, 0x00001080, 0x000033c2, + 0x50000480, 0x00001c01, 0xb4000080, 0x00002400, + 0x88000481, 0x00000c00, 0x24000480, 0x00001c01, + 0x000001e0, 0x00000000, 0x40000480, 0x00002c0c, + 0x2c000080, 0x000007c2, 0x8c000080, 0x00000fc2, + 0x00200600, 0x00000020, 0x880c0080, 0x00000c02, + 0x880c00c0, 0x00000c42, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0x98000480, 0x00000fc2, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0x80fffc80, 0x00000fc2, + 0x04000400, 0x00000000, 0xe0000480, 0x00000803, + 0x04002000, 0x00000000, 0x28000080, 0x00000fc0, + 0x50000080, 0x00001c01, 0x00000480, 0x00001800, + 0x0c000080, 0x00001800, 0x5c000080, 0x000007c2, + 0x04000080, 0x00002c00, 0x02000600, 0x00000200, + 0x2c0010c0, 0x00003bc1, 0x2c001880, 0x00003bc1, + 0x18001880, 0x00003bc1, 0x1c001880, 0x00003bc1, + 0x20001880, 0x00003bc1, 0x24001880, 0x00003bc1, + 0x28001880, 0x00003bc1, 0x20000880, 0x00002bcc, + 0x040030a0, 0x00002c00, 0x24000080, 0x00001c01, + 0xb4000480, 0x00002400, 0x00000040, 0x00004000, + 0x00000020, 0x00000000, 0x00000020, 0x00000000, + 0x88000c80, 0x00000c00, 0x80000080, 0x00000fc0, + 0x04000c00, 0x00000000, 0x88000480, 0x00000802, + 0x000001e0, 0x00000000, 0x00001880, 0x000033c2, + 0x000009c1, 0x00000000, 0x9c000d11, 0x00001c01, + 0x04001011, 0x00000000, 0x9c001111, 0x00001c03, + 0x04001011, 0x00000000, 0x9c000091, 0x00001c01, + 0x9c000091, 0x00001c03, 0x0009dd21, 0x00000000, + 0xb8000480, 0x00000801, 0x04000800, 0x00000000, + 0x80068200, 0x0000400f, 0x0009d540, 0x00000000, + 0x000091c0, 0x00000000, 0x000181c0, 0x00000000, + 0x0002a5c0, 0x00000000, 0x000371c0, 0x00000000, + 0x000399c0, 0x00000000, 0x0003b1c0, 0x00000000, + 0x0005cdc0, 0x00000000, 0x40004200, 0x00000000, + 0x6001c0e0, 0x00002425, 0x00080200, 0x0000400e, + 0x000a2140, 0x00000000, 0x000a0531, 0x00000000, + 0x00070dc0, 0x00000000, 0x80008600, 0x00000000, + 0x000a2140, 0x00000000, 0x00074dc2, 0x00000000, + 0x80068200, 0x0000400f, 0xc40004c0, 0x000007c0, + 0x04001000, 0x00000000, 0xc40000c0, 0x000007c0, + 0x40006611, 0x00000000, 0x000a6951, 0x00000000, + 0x80068211, 0x0000400f, 0x000a6951, 0x00000000, + 0x00080211, 0x0000400e, 0x000a4151, 0x00000000, + 0x80008611, 0x00000000, 0x000a4d71, 0x00000000, + 0x00001031, 0x00000000, 0x00001031, 0x00000000, + 0x00002c31, 0x00000000, 0xa8000091, 0x00001c06, + 0x80016891, 0x00001c04, 0x04000400, 0x00000000, + 0x80016c91, 0x00001c04, 0x04000800, 0x00000000, + 0x00000851, 0x00006000, 0x80000091, 0x00001c04, + 0x24000091, 0x0001e420, 0x0008adc0, 0x00000000, + 0x00000000, 0x00000000, 0x0008f5c0, 0x00000000, + 0x24000480, 0x00001c01, 0x00000400, 0x00000000, + 0x50000080, 0x00001c01, 0x9c000d00, 0x00001c01, + 0x04001000, 0x00000000, 0x9c001100, 0x00001c03, + 0x04001000, 0x00000000, 0x9c000080, 0x00001c01, + 0x9c000080, 0x00001c03, 0x00001880, 0x000033c2, + 0xb8000480, 0x00000801, 0x04000c00, 0x00000000, + 0x24000491, 0x0001e420, 0xa8000080, 0x00001c06, + 0x80012880, 0x00001c04, 0x04000400, 0x00000000, + 0x80012c80, 0x00001c04, 0x04000800, 0x00000000, + 0x00000840, 0x00006000, 0x80000080, 0x00001c04, + 0x2c000080, 0x000007c2, 0x8c200080, 0x00000fc2, + 0x00200600, 0x00000020, 0x883c0080, 0x00000c02, + 0x883c00c0, 0x00000c42, 0x98000480, 0x00000fc2, + 0x28000480, 0x00000fc0, 0x04001000, 0x00000000, + 0x80fffc80, 0x00000fc2, 0x247ffc80, 0x000007c2, + 0x281ffc80, 0x000007c2, 0x04000400, 0x00000000, + 0xe0000480, 0x00000803, 0x28000080, 0x00000fc0, + 0x00800600, 0x00000080, 0x040000c0, 0x00002424, + 0x040080e0, 0x00002424, 0x400004e2, 0x00002c0c, + 0x04000800, 0x00000000, 0x400000e2, 0x00002c0c, + 0x04000800, 0x00000000, 0x800004e0, 0x00002c0c, + 0x800000e0, 0x00002c0c, 0x00000605, 0x00002000, + 0x400004c2, 0x00002c0c, 0x04000800, 0x00000000, + 0x400000c2, 0x00002c0c, 0x04000800, 0x00000000, + 0x800004c0, 0x00002c0c, 0x800000c0, 0x00002c0c, + 0x04000c00, 0x00000000, 0x24000080, 0x00001c01, + 0x10000200, 0x00005000, 0x000b5540, 0x00000000, + 0x00000040, 0x00004000, 0x28000480, 0x00000fc0, + 0x04001000, 0x00000000, 0xe0000080, 0x00000803, + 0x04000800, 0x00000000, 0x28000080, 0x00000fc0, + 0x80000080, 0x00000fc2, 0x98000080, 0x00000fc2, + 0x24000080, 0x000007c2, 0x28000080, 0x000007c2, + 0xe4000480, 0x00000801, 0x04000800, 0x00000000, + 0xe4000080, 0x00000801, 0x04000800, 0x00000000, + 0xa8000480, 0x00001c04, 0xe8030c80, 0x00001c01, + 0x04000800, 0x00000000, 0xe8000080, 0x00001c01, + 0x04000400, 0x00000000, 0x9c000ca0, 0x00001c01, + 0x9c0010a0, 0x00001c03, 0x000a0520, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, +}; + +#endif /* __DRIVERS_RAM_RENESAS_DBSC5_R8A78000_DRAM_H__ */ diff --git a/include/dbsc5.h b/include/dbsc5.h deleted file mode 100644 index b9b8703141a..00000000000 --- a/include/dbsc5.h +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2024-2025 Renesas Electronics Corp. - */ - -#ifndef __INCLUDE_DBSC5_H__ -#define __INCLUDE_DBSC5_H__ - -/* The number of channels V4H has */ -#define DRAM_CH_CNT 4 -/* The number of slices V4H has */ -#define SLICE_CNT 2 -/* The number of chip select V4H has */ -#define CS_CNT 2 - -struct renesas_dbsc5_board_config { - /* Channels in use */ - u8 bdcfg_phyvalid; - /* Read vref (SoC) training range */ - u32 bdcfg_vref_r; - /* Write vref (MR14, MR15) training range */ - u16 bdcfg_vref_w; - /* CA vref (MR12) training range */ - u16 bdcfg_vref_ca; - /* RFM required check */ - bool bdcfg_rfm_chk; - - /* Board parameter about channels */ - struct { - /* - * 0x00: 4Gb dual channel die / 2Gb single channel die - * 0x01: 6Gb dual channel die / 3Gb single channel die - * 0x02: 8Gb dual channel die / 4Gb single channel die - * 0x03: 12Gb dual channel die / 6Gb single channel die - * 0x04: 16Gb dual channel die / 8Gb single channel die - * 0x05: 24Gb dual channel die / 12Gb single channel die - * 0x06: 32Gb dual channel die / 16Gb single channel die - * 0x07: 24Gb single channel die - * 0x08: 32Gb single channel die - * 0xFF: NO_MEMORY - */ - u8 bdcfg_ddr_density[CS_CNT]; - /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ - u32 bdcfg_ca_swap; - /* SoC dqsX([1][0]) -> MEM dqsY: */ - u8 bdcfg_dqs_swap; - /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ - u32 bdcfg_dq_swap[SLICE_CNT]; - /* SoC dm -> MEM dqY/dm: (8 means DM) */ - u8 bdcfg_dm_swap[SLICE_CNT]; - /* SoC ckeX([1][0]) -> MEM csY */ - u8 bdcfg_cs_swap; - } ch[DRAM_CH_CNT]; -}; - -#endif /* __INCLUDE_DBSC5_H__ */ diff --git a/include/r8a779g0-dbsc5.h b/include/r8a779g0-dbsc5.h new file mode 100644 index 00000000000..b9b8703141a --- /dev/null +++ b/include/r8a779g0-dbsc5.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2024-2025 Renesas Electronics Corp. + */ + +#ifndef __INCLUDE_DBSC5_H__ +#define __INCLUDE_DBSC5_H__ + +/* The number of channels V4H has */ +#define DRAM_CH_CNT 4 +/* The number of slices V4H has */ +#define SLICE_CNT 2 +/* The number of chip select V4H has */ +#define CS_CNT 2 + +struct renesas_dbsc5_board_config { + /* Channels in use */ + u8 bdcfg_phyvalid; + /* Read vref (SoC) training range */ + u32 bdcfg_vref_r; + /* Write vref (MR14, MR15) training range */ + u16 bdcfg_vref_w; + /* CA vref (MR12) training range */ + u16 bdcfg_vref_ca; + /* RFM required check */ + bool bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + /* SoC ckeX([1][0]) -> MEM csY */ + u8 bdcfg_cs_swap; + } ch[DRAM_CH_CNT]; +}; + +#endif /* __INCLUDE_DBSC5_H__ */ diff --git a/include/r8a78000-dbsc5.h b/include/r8a78000-dbsc5.h new file mode 100644 index 00000000000..7954f5b0761 --- /dev/null +++ b/include/r8a78000-dbsc5.h @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2026 Renesas Electronics Corp. + * + * Portions Copyright (C) 2026 Synopsys, Inc. Used with permission. All rights reserved. + */ + +#ifndef __INCLUDE_DBSC5_H__ +#define __INCLUDE_DBSC5_H__ + +/* The number of channels X5H has */ +#define DRAM_CH_CNT 16 +/* The number of slices X5H has */ +#define SLICE_CNT 2 +/* The number of chip select X5H has */ +#define CS_CNT 2 + +struct renesas_dbsc5_board_config { + u32 bdcfg_phyvalid; + u32 bdcfg_tx_drv; + u32 bdcfg_tx_ffc; + u32 bdcfg_rx_odt; + u8 bdcfg_rx_dfe; + u8 bdcfg_tx_odt; + u8 bdcfg_tx_ntodt; + u8 bdcfg_tx_dfe; + u8 bdcfg_rx_dca; + u8 bdcfg_rx_drv; + u32 bdcfg_rx_emphasis; + u8 bdcfg_tx_dca; + u8 bdcfg_ca_vref; + u32 bdcfg_rx_vref; + u32 bdcfg_rx_vref_step; + u32 bdcfg_tx_vref; + u8 bdcfg_rfm_chk; + + /* Board parameter about channels */ + struct { + /* + * 0x00: 4Gb dual channel die / 2Gb single channel die + * 0x01: 6Gb dual channel die / 3Gb single channel die + * 0x02: 8Gb dual channel die / 4Gb single channel die + * 0x03: 12Gb dual channel die / 6Gb single channel die + * 0x04: 16Gb dual channel die / 8Gb single channel die + * 0x05: 24Gb dual channel die / 12Gb single channel die + * 0x06: 32Gb dual channel die / 16Gb single channel die + * 0x07: 24Gb single channel die + * 0x08: 32Gb single channel die + * 0xFF: NO_MEMORY + */ + u8 bdcfg_ddr_density[CS_CNT]; + /* SoC caX([6][5][4][3][2][1][0]) -> MEM caY: */ + u32 bdcfg_ca_swap; + /* SoC dqsX([1][0]) -> MEM dqsY: */ + u8 bdcfg_dqs_swap; + /* SoC dq([7][6][5][4][3][2][1][0]) -> MEM dqY/dm: (8 means DM) */ + u32 bdcfg_dq_swap[SLICE_CNT]; + /* SoC dm -> MEM dqY/dm: (8 means DM) */ + u8 bdcfg_dm_swap[SLICE_CNT]; + } ch[DRAM_CH_CNT]; +}; + +#endif /* __INCLUDE_DBSC5_H__ */ -- cgit v1.3.1 From 28f675023da174b1b4817266cac7bcf3ffb6d908 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 10 Jun 2026 20:20:59 +0200 Subject: arm: dts: renesas: Enable DBSC5 on R-Car R8A78000 X5H Cortex-M33 RSIP port Bind the DBSC5 DRAM controller driver on boot in board_early_init_r(), which brings up the DBSC5 DRAM controller and its PHY and which enables access to DRAM present on this system. Add default boot command which loads additional bootloader components from HF and UFS storage into SRAM and DRAM, and starts those components on SCP and AP core 0. The system is then capable of reaching U-Boot on the AP core 0. Specifically, the following components are loaded: - SCP firmware, 384 kiB from HF offset 0x4c0000 to SCP STCM - TFA BL31, 256 kiB from UFS0 offset 0x5000 * 4 kiB sectors to DRAM 0x8c200000 - TEE, 2 MiB from UFS0 offset 0x5200 * 4 kiB sectors to DRAM 0x8c400000 - U-Boot, 1 MiB from UFS0 offset 0x7200 * 4 kiB sectors to DRAM 0x8c300000 - IPL parameters table is generated at DRAM address 0x8c100000 Enable pstore command support to allow dumping kernel console from pstore/ramoops, which is convenient for debugging. Use as follows: => pstore set 0x80000000 0x10000 0x400 0x8000 0 0 0 => pstore display console Signed-off-by: Marek Vasut --- arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi | 10 +++++ arch/arm/mach-renesas/Kconfig.rcar5 | 1 + board/renesas/common/gen5-cm33.c | 49 +++++++++++++++++++++++++ configs/r8a78000_ironhide_cm33_defconfig | 8 +++- include/configs/rcar-gen5-common.h | 42 ++++++++++++++++++++- 5 files changed, 108 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi index 2d4cdbac62a..356f633135d 100644 --- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -65,10 +65,20 @@ syscon = <&ctl>; }; + ram@b8940000 { /* RT-VRAM */ + compatible = "renesas,r8a78000-rtvram"; + reg = <0 0xb8940000 0 0xf000>; + }; + scp@c1340000 { compatible = "renesas,r8a78000-rproc"; reg = <0 0xc1340000 0 0x80000>; }; + + ram@e9800000 { /* DBSC5 */ + compatible = "renesas,r8a78000-dbsc"; + reg = <0 0xe9800000 0 0x1000000>; + }; }; &cpg { diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index fcca3811241..33ad8522f07 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -2,6 +2,7 @@ if RCAR_GEN5 config RCAR_64_RSIP bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)" + select LMB_ARCH_MEM_MAP select SKIP_RELOCATE_CODE select TMU_TIMER help diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index e07db9817f2..f06df824019 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -904,6 +904,24 @@ static void mfis_unprotect(void) writel(MFIS_CODEVALUE, MFIS_WPCNTR); } +/** + * rsip_write_reg() - Write RSIP control register + * @reg: Register to write + * @val: Value to set in the register + */ +static void rsip_write_reg(const u32 reg, const int val) +{ + for (;;) { + writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD); + writel(val, reg); + writel(~val, reg); + writel(val, reg); + + if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR) + break; + } +} + /** * rsip_irq_setup() - Configure RSIP interrupts */ @@ -1353,6 +1371,26 @@ int mach_cpu_init(void) return 0; } +int board_early_init_r(void) +{ + u32 remaptmp = readl(RSIP_CTL_ESICREMAP0); + struct udevice *dev; + int ret; + + /* Remap DDR PHY during DRAM init. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000); + + /* Start DBSC5 */ + ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev); + if (ret) + printf("DBSC5 init failed: %d\n", ret); + + /* Restore remapping. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp); + + return 0; +} + /** * board_debug_uart_init() - Initialize all HSCIF */ @@ -1407,3 +1445,14 @@ void __weak reset_cpu(void) writel(RST_KCPROT_DIS, RST_RESKCPROT0); writel(0x1, RST_SWSRES1A); } + +/** + * lmb_arch_add_memory() - Add memory to LMB + * + * Add the window to a subset of 32bit DRAM are into LMB, + * to make it possible to TFTP into it. + */ +void lmb_arch_add_memory(void) +{ + lmb_add(0x60000000, 0x40000000); +} diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig index dda096634b5..7ea3ae993ba 100644 --- a/configs/r8a78000_ironhide_cm33_defconfig +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000 CONFIG_ARCH_CPU_INIT=y CONFIG_BAUDRATE=1843200 -CONFIG_BOOTCOMMAND="" +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0" CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_IMI=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000 +CONFIG_CMD_PSTORE_RECORD_SIZE=0x400 +CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000 CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_DM_DMA=y @@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y CONFIG_PHY_TI_DP83869=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y +CONFIG_RAM_RENESAS_DBSC5=y CONFIG_REMOTEPROC_RENESAS_RSIP=y CONFIG_RENESAS_ETHER_SWITCH=y CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 5ff2a76fc05..a0c05521c85 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -26,10 +26,50 @@ #if defined(CONFIG_RCAR_64_RSIP) #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) -#endif +/* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "rsip_ipl_params_base=0x8c100000\0" \ + "rsip_ipl_params_optee=0x8c100088\0" \ + "rsip_ipl_params_uboot=0x8c100030\0" \ + "rsip_ipl_optee_ep=0x8c400000\0" \ + "rsip_ipl_tfa_ep=0x8c200000\0" \ + "rsip_ipl_uboot_ep=0x8e300000\0" \ + "rsip_ipl_params_write=" \ + "base ${rsip_ipl_params_base} ; " \ + "mw 0x00 0 0x9e ; " /* Clear the area */ \ + "mw 0x00 0x00300103 ; " /* type, version, size */ \ + "mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \ + "" \ + "base ${rsip_ipl_params_uboot} ; " \ + "mw 0x00 0x00580101 ; " /* type, version, size */ \ + "mw 0x04 0x00000001 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base ${rsip_ipl_params_optee} ; " \ + "mw 0x00 0x00580201 ; " /* type, version, size */ \ + "mw 0x04 0x00000008 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base 0\0" \ + "rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \ + "scsi scan && " /* Scan for UFS devices */ \ + "rproc init && " /* Start remoteproc */ \ + "rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \ + "rproc start 0 && " /* Start SCP */ \ + "scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \ + "scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \ + "scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \ + "run rsip_ipl_params_write && " /* Write entry point descriptors */ \ + "rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \ + "rproc start 13\0" /* Start Cortex-A720AE Core 0 */ + +#else /* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" +#endif #endif /* __RCAR_GEN5_COMMON_H */ -- cgit v1.3.1 From eb6f420836bb30e8c54c140f1bea3e2c88f5b201 Mon Sep 17 00:00:00 2001 From: Denis Mukhin Date: Sat, 20 Jun 2026 22:14:43 -0700 Subject: bootdev: fix typos Signed-off-by: Denis Mukhin Reviewed-by: Heinrich Schuchardt Reviewed-by: Simon Glass --- include/bootdev.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/bootdev.h b/include/bootdev.h index 12c90c4ec1b..14f8a98633b 100644 --- a/include/bootdev.h +++ b/include/bootdev.h @@ -30,10 +30,10 @@ struct udevice; * generally very quick to access, e.g. less than 100ms * @BOOTDEVP_3_INTERNAL_SLOW: Internal devices which don't need scanning but * take a significant fraction of a second to access - * @BOOTDEVP_4_SCAN_FAST: Extenal devices which need scanning or bus + * @BOOTDEVP_4_SCAN_FAST: External devices which need scanning or bus * enumeration to find, but this enumeration happens quickly, typically under * 100ms - * @BOOTDEVP_5_SCAN_SLOW: Extenal devices which need scanning or bus + * @BOOTDEVP_5_SCAN_SLOW: External devices which need scanning or bus * enumeration to find. The enumeration takes significant fraction of a second * to complete * @BOOTDEVP_6_NET_BASE: Basic network devices which are quickly and easily @@ -327,7 +327,7 @@ int bootdev_hunt_and_find_by_label(const char *label, struct udevice **devp, * Bootdev scanners are used as needed. For example a label "mmc1" results in * running the "mmc" bootdrv. * - * @iter: Interation info, containing iter->cur_label + * @iter: Iteration info, containing iter->cur_label * @devp: New bootdev found, if any was found * @method_flagsp: If non-NULL, returns any flags implied by the label * (enum bootflow_meth_flags_t), 0 if none @@ -342,7 +342,7 @@ int bootdev_next_label(struct bootflow_iter *iter, struct udevice **devp, * This moves @devp to the next bootdev with the current priority. If there is * none, then it moves to the next priority and scans for new bootdevs there. * - * @iter: Interation info, containing iter->cur_prio + * @iter: Iteration info, containing iter->cur_prio * @devp: On entry this is the previous bootdev that was considered. On exit * this is the new bootdev, if any was found * Returns 0 on success (*devp is updated), -ENODEV if there are no more -- cgit v1.3.1