From 1db7ee464f28d72bd1af87b1136c9c158833da13 Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 15:19:35 -0700 Subject: fdtdec: Add API to read pci bus-range property Add fdtdec_get_pci_bus_range to read bus-range property values. Signed-off-by: Suneel Garapati Reviewed-by: Simon Glass --- include/fdtdec.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index bc79389260a..152eb07b9e0 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -444,6 +444,19 @@ int fdtdec_get_pci_vendev(const void *blob, int node, int fdtdec_get_pci_bar32(const struct udevice *dev, struct fdt_pci_addr *addr, u32 *bar); +/** + * Look at the bus range property of a device node and return the pci bus + * range for this node. + * The property must hold one fdt_pci_addr with a length. + * @param blob FDT blob + * @param node node to examine + * @param res the resource structure to return the bus range + * @return 0 if ok, negative on error + */ + +int fdtdec_get_pci_bus_range(const void *blob, int node, + struct fdt_resource *res); + /** * Look up a 32-bit integer property in a node and return it. The property * must have at least 4 bytes of data. The value of the first cell is -- cgit v1.3.1 From 68f81b857563e8f739323385795f1e99b3d2e598 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 5 Aug 2020 13:56:11 +0200 Subject: dm: core: Add API to read PCI bus-range property Add dev_read_pci_bus_range() to read bus-range property values Signed-off-by: Stefan Roese Reviewed-by: Simon Glass --- drivers/core/read.c | 17 +++++++++++++++++ include/dm/read.h | 12 ++++++++++++ 2 files changed, 29 insertions(+) (limited to 'include') diff --git a/drivers/core/read.c b/drivers/core/read.c index 8bb456bc3f0..86f3f881706 100644 --- a/drivers/core/read.c +++ b/drivers/core/read.c @@ -10,6 +10,7 @@ #include #include #include +#include int dev_read_u32(const struct udevice *dev, const char *propname, u32 *outp) { @@ -359,3 +360,19 @@ int dev_get_child_count(const struct udevice *dev) { return ofnode_get_child_count(dev_ofnode(dev)); } + +int dev_read_pci_bus_range(const struct udevice *dev, + struct resource *res) +{ + const u32 *values; + int len; + + values = dev_read_prop(dev, "bus-range", &len); + if (!values || len < sizeof(*values) * 2) + return -EINVAL; + + res->start = *values++; + res->end = *values; + + return 0; +} diff --git a/include/dm/read.h b/include/dm/read.h index 0a7aacd2d04..67db94adfc1 100644 --- a/include/dm/read.h +++ b/include/dm/read.h @@ -680,6 +680,18 @@ int dev_read_alias_highest_id(const char *stem); */ int dev_get_child_count(const struct udevice *dev); +/** + * dev_read_pci_bus_range - Read PCI bus-range resource + * + * Look at the bus range property of a device node and return the pci bus + * range for this node. + * + * @dev: device to examine + * @res returns the resource + * @return 0 if ok, negative on error + */ +int dev_read_pci_bus_range(const struct udevice *dev, struct resource *res); + #else /* CONFIG_DM_DEV_READ_INLINE is enabled */ static inline int dev_read_u32(const struct udevice *dev, -- cgit v1.3.1 From e002474158d1054a7a2ff9a66149384c639ff242 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 23 Jul 2020 16:34:10 +0200 Subject: pci: pci-uclass: Dynamically allocate the PCI regions Instead of using a fixed length pre-allocated array of regions, this patch moves to dynamically allocating the regions based on the number of available regions plus the necessary regions for DRAM banks. Since MAX_PCI_REGIONS is not needed any more, its removed completely with this patch. Signed-off-by: Stefan Roese Reviewed-by: Simon Glass Cc: Bin Meng Cc: Thierry Reding Cc: Marek Vasut --- drivers/pci/pci-uclass.c | 14 ++++++++------ include/pci.h | 4 +--- 2 files changed, 9 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 601557a875d..337ac137d13 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -874,6 +874,7 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, struct bd_info *bd = gd->bd; int cells_per_record; const u32 *prop; + int max_regions; int len; int i; @@ -893,7 +894,13 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, hose->region_count = 0; debug("%s: len=%d, cells_per_record=%d\n", __func__, len, cells_per_record); - for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) { + + /* Dynamically allocate the regions array */ + max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS; + hose->regions = (struct pci_region *) + calloc(1, max_regions * sizeof(struct pci_region)); + + for (i = 0; i < max_regions; i++, len -= cells_per_record) { u64 pci_addr, addr, size; int space_code; u32 flags; @@ -943,11 +950,6 @@ static void decode_regions(struct pci_controller *hose, ofnode parent_node, return; for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { - if (hose->region_count == MAX_PCI_REGIONS) { - pr_err("maximum number of regions parsed, aborting\n"); - break; - } - if (bd->bi_dram[i].size) { pci_set_region(hose->regions + hose->region_count++, bd->bi_dram[i].start, diff --git a/include/pci.h b/include/pci.h index 2089db9f16f..da755af852c 100644 --- a/include/pci.h +++ b/include/pci.h @@ -590,8 +590,6 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev, extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *); -#define MAX_PCI_REGIONS 7 - #define INDIRECT_TYPE_NO_PCIE_LINK 1 /** @@ -632,7 +630,7 @@ struct pci_controller { * for PCI controllers and a separate UCLASS (or perhaps * UCLASS_PCI_GENERIC) is used for bridges. */ - struct pci_region regions[MAX_PCI_REGIONS]; + struct pci_region *regions; int region_count; struct pci_config_table *config_table; -- cgit v1.3.1 From b8852dcfcb0facb37839a8cf9b01cb549153fba8 Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 16:07:20 -0700 Subject: pci: pci-uclass: Add support for Single-Root I/O Virtualization SR-IOV - Single Root I/O Virtualization PF - Physical Function VF - Virtual Function If SR-IOV capability is present, use it to initialize Virtual Function PCI device instances. pci_sriov_init function will read SR-IOV registers to create VF devices under the PF PCI device and also bind driver if available. This function needs to be invoked from Physical function device driver which expects VF device support, creating minimal impact on existing framework. Signed-off-by: Suneel Garapati Cc: Simon Glass Cc: Bin Meng --- drivers/pci/Kconfig | 10 +++++ drivers/pci/pci-uclass.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++ include/pci.h | 38 ++++++++++++++++ 3 files changed, 162 insertions(+) (limited to 'include') diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 1c47a21101d..4635752a95c 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -53,6 +53,16 @@ config PCI_REGION_MULTI_ENTRY region type. This helps to add support for SoC's like OcteonTX/TX2 where every peripheral is on the PCI bus. +config PCI_SRIOV + bool "Enable Single Root I/O Virtualization support for PCI" + depends on PCI || DM_PCI + default n + help + Say Y here if you want to enable PCI Single Root I/O Virtualization + capability support. This helps to enumerate Virtual Function devices + if available on a PCI Physical Function device and probe for + applicable drivers. + config PCIE_ECAM_GENERIC bool "Generic ECAM-based PCI host controller support" default n diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index fa6115a105e..51871bfe624 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1586,6 +1586,120 @@ int dm_pci_flr(struct udevice *dev) return 0; } +#if defined(CONFIG_PCI_SRIOV) +int pci_sriov_init(struct udevice *pdev, int vf_en) +{ + u16 vendor, device; + struct udevice *bus; + struct udevice *dev; + pci_dev_t bdf; + u16 ctrl; + u16 num_vfs; + u16 total_vf; + u16 vf_offset; + u16 vf_stride; + int vf, ret; + int pos; + + pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); + if (!pos) { + debug("Error: SRIOV capability not found\n"); + return -ENOENT; + } + + dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl); + + dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf); + if (vf_en > total_vf) + vf_en = total_vf; + dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en); + + ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE; + dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl); + + dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs); + if (num_vfs > vf_en) + num_vfs = vf_en; + + dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset); + dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride); + + dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor); + dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device); + + bdf = dm_pci_get_bdf(pdev); + + pci_get_bus(PCI_BUS(bdf), &bus); + + if (!bus) + return -ENODEV; + + bdf += PCI_BDF(0, 0, vf_offset); + + for (vf = 0; vf < num_vfs; vf++) { + struct pci_child_platdata *pplat; + ulong class; + + pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE, + &class, PCI_SIZE_16); + + debug("%s: bus %d/%s: found VF %x:%x\n", __func__, + bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf)); + + /* Find this device in the device tree */ + ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev); + + if (ret == -ENODEV) { + struct pci_device_id find_id; + + memset(&find_id, '\0', sizeof(find_id)); + find_id.vendor = vendor; + find_id.device = device; + find_id.class = class; + + ret = pci_find_and_bind_driver(bus, &find_id, + bdf, &dev); + + if (ret) + return ret; + } + + /* Update the platform data */ + pplat = dev_get_parent_platdata(dev); + pplat->devfn = PCI_MASK_BUS(bdf); + pplat->vendor = vendor; + pplat->device = device; + pplat->class = class; + pplat->is_virtfn = true; + pplat->pfdev = pdev; + pplat->virtid = vf * vf_stride + vf_offset; + + debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n", + __func__, dev->seq, dev->name, PCI_DEV(bdf), + PCI_FUNC(bdf), vendor, device, class, pplat->virtid); + bdf += PCI_BDF(0, 0, vf_stride); + } + + return 0; +} + +int pci_sriov_get_totalvfs(struct udevice *pdev) +{ + u16 total_vf; + int pos; + + pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV); + if (!pos) { + debug("Error: SRIOV capability not found\n"); + return -ENOENT; + } + + dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf); + + return total_vf; +} +#endif /* SRIOV */ + UCLASS_DRIVER(pci) = { .id = UCLASS_PCI, .name = "pci", diff --git a/include/pci.h b/include/pci.h index da755af852c..115d3312a4a 100644 --- a/include/pci.h +++ b/include/pci.h @@ -493,6 +493,17 @@ #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */ +/* Single Root I/O Virtualization Registers */ +#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ +#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */ +#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */ +#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */ +#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */ +#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */ +#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */ +#define PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */ +#define PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */ +#define PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ /* Include the ID list */ @@ -890,12 +901,20 @@ struct udevice; * @vendor: PCI vendor ID (see pci_ids.h) * @device: PCI device ID (see pci_ids.h) * @class: PCI class, 3 bytes: (base, sub, prog-if) + * @is_virtfn: True for Virtual Function device + * @pfdev: Handle to Physical Function device + * @virtid: Virtual Function Index */ struct pci_child_platdata { int devfn; unsigned short vendor; unsigned short device; unsigned int class; + + /* Variables for CONFIG_PCI_SRIOV */ + bool is_virtfn; + struct udevice *pfdev; + int virtid; }; /* PCI bus operations */ @@ -1208,6 +1227,25 @@ int pci_generic_mmap_read_config( ulong *valuep, enum pci_size_t size); +#if defined(CONFIG_PCI_SRIOV) +/** + * pci_sriov_init() - Scan Virtual Function devices + * + * @pdev: Physical Function udevice handle + * @vf_en: Number of Virtual Function devices to enable + * @return 0 on success, -ve on error + */ +int pci_sriov_init(struct udevice *pdev, int vf_en); + +/** + * pci_sriov_get_totalvfs() - Get total available Virtual Function devices + * + * @pdev: Physical Function udevice handle + * @return count on success, -ve on error + */ +int pci_sriov_get_totalvfs(struct udevice *pdev); +#endif + #ifdef CONFIG_DM_PCI_COMPAT /* Compatibility with old naming */ static inline int pci_write_config_dword(pci_dev_t pcidev, int offset, -- cgit v1.3.1 From 51eeae91c5e7b8f7c1bdf46aa6d6bb1675fd2ebc Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 16:34:16 -0700 Subject: pci: pci-uclass: Add VF BAR map support for Enhanced Allocation Makes dm_pci_map_bar API available to map BAR for Virtual function PCI devices which support Enhanced Allocation. Signed-off-by: Suneel Garapati Cc: Simon Glass Cc: Bin Meng --- drivers/pci/pci-uclass.c | 67 ++++++++++++++++++++++++++++++++++++++++++++---- include/pci.h | 3 +++ 2 files changed, 65 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/pci/pci-uclass.c b/drivers/pci/pci-uclass.c index 51871bfe624..23135ebe04e 100644 --- a/drivers/pci/pci-uclass.c +++ b/drivers/pci/pci-uclass.c @@ -1409,14 +1409,55 @@ pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr, return bus_addr; } +static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off, + struct pci_child_platdata *pdata) +{ + phys_addr_t addr = 0; + + /* + * In the case of a Virtual Function device using BAR + * base and size, add offset for VFn BAR(1, 2, 3...n) + */ + if (pdata->is_virtfn) { + size_t sz; + u32 ea_entry; + + /* MaxOffset, 1st DW */ + dm_pci_read_config32(dev, ea_off + 8, &ea_entry); + sz = ea_entry & PCI_EA_FIELD_MASK; + /* Fill up lower 2 bits */ + sz |= (~PCI_EA_FIELD_MASK); + + if (ea_entry & PCI_EA_IS_64) { + /* MaxOffset 2nd DW */ + dm_pci_read_config32(dev, ea_off + 16, &ea_entry); + sz |= ((u64)ea_entry) << 32; + } + + addr = (pdata->virtid - 1) * (sz + 1); + } + + return addr; +} + static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, - int ea_off) + int ea_off, struct pci_child_platdata *pdata) { int ea_cnt, i, entry_size; int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2; u32 ea_entry; phys_addr_t addr; + if (IS_ENABLED(CONFIG_PCI_SRIOV)) { + /* + * In the case of a Virtual Function device, device is + * Physical function, so pdata will point to required VF + * specific data. + */ + if (pdata->is_virtfn) + bar_id += PCI_EA_BEI_VF_BAR0; + } + /* EA capability structure header */ dm_pci_read_config32(dev, ea_off, &ea_entry); ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK; @@ -1439,6 +1480,9 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, addr |= ((u64)ea_entry) << 32; } + if (IS_ENABLED(CONFIG_PCI_SRIOV)) + addr += dm_pci_map_ea_virt(dev, ea_off, pdata); + /* size ignored for now */ return map_physmem(addr, 0, flags); } @@ -1448,20 +1492,33 @@ static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags, void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) { + struct pci_child_platdata *pdata = dev_get_parent_platdata(dev); + struct udevice *udev = dev; pci_addr_t pci_bus_addr; u32 bar_response; int ea_off; + if (IS_ENABLED(CONFIG_PCI_SRIOV)) { + /* + * In case of Virtual Function devices, use PF udevice + * as EA capability is defined in Physical Function + */ + if (pdata->is_virtfn) + udev = pdata->pfdev; + } + /* * if the function supports Enhanced Allocation use that instead of * BARs + * Incase of virtual functions, pdata will help read VF BEI + * and EA entry size. */ - ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA); + ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA); if (ea_off) - return dm_pci_map_ea_bar(dev, bar, flags, ea_off); + return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata); /* read BAR address */ - dm_pci_read_config32(dev, bar, &bar_response); + dm_pci_read_config32(udev, bar, &bar_response); pci_bus_addr = (pci_addr_t)(bar_response & ~0xf); /* @@ -1470,7 +1527,7 @@ void *dm_pci_map_bar(struct udevice *dev, int bar, int flags) * linear mapping. In the future, this could read the BAR size * and pass that as the size if needed. */ - return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE); + return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE); } static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap) diff --git a/include/pci.h b/include/pci.h index 115d3312a4a..1c5b36617e3 100644 --- a/include/pci.h +++ b/include/pci.h @@ -465,6 +465,9 @@ #define PCI_EA_FIRST_ENT 4 /* First EA Entry in List */ #define PCI_EA_ES 0x00000007 /* Entry Size */ #define PCI_EA_BEI 0x000000f0 /* BAR Equivalent Indicator */ +/* 9-14 map to VF BARs 0-5 respectively */ +#define PCI_EA_BEI_VF_BAR0 9 +#define PCI_EA_BEI_VF_BAR5 14 /* Base, MaxOffset registers */ /* bit 0 is reserved */ #define PCI_EA_IS_64 0x00000002 /* 64-bit field flag */ -- cgit v1.3.1 From 03c2288070155ee88d0c3341748a1b2b13418d8c Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 18:37:55 -0700 Subject: arm: octeontx: Add support for OcteonTX SoC platforms This patch adds support for all OcteonTX 81xx/83xx boards from Marvell. For 81xx boards, use octeontx_81xx_defconfig and for 83xx boards, use octeontx_83xx_defconfig. Signed-off-by: Suneel Garapati --- arch/arm/Kconfig | 10 ++ arch/arm/Makefile | 1 + arch/arm/mach-octeontx/Kconfig | 23 +++ arch/arm/mach-octeontx/Makefile | 9 + arch/arm/mach-octeontx/clock.c | 35 ++++ arch/arm/mach-octeontx/cpu.c | 76 ++++++++ arch/arm/mach-octeontx/lowlevel_init.S | 33 ++++ board/Marvell/octeontx/Kconfig | 14 ++ board/Marvell/octeontx/MAINTAINERS | 8 + board/Marvell/octeontx/Makefile | 9 + board/Marvell/octeontx/board-fdt.c | 311 +++++++++++++++++++++++++++++++++ board/Marvell/octeontx/board.c | 152 ++++++++++++++++ board/Marvell/octeontx/smc.c | 25 +++ board/Marvell/octeontx/soc-utils.c | 50 ++++++ configs/octeontx_81xx_defconfig | 130 ++++++++++++++ configs/octeontx_83xx_defconfig | 129 ++++++++++++++ include/configs/octeontx_common.h | 89 ++++++++++ 17 files changed, 1104 insertions(+) create mode 100644 arch/arm/mach-octeontx/Kconfig create mode 100644 arch/arm/mach-octeontx/Makefile create mode 100644 arch/arm/mach-octeontx/clock.c create mode 100644 arch/arm/mach-octeontx/cpu.c create mode 100644 arch/arm/mach-octeontx/lowlevel_init.S create mode 100644 board/Marvell/octeontx/Kconfig create mode 100644 board/Marvell/octeontx/MAINTAINERS create mode 100644 board/Marvell/octeontx/Makefile create mode 100644 board/Marvell/octeontx/board-fdt.c create mode 100644 board/Marvell/octeontx/board.c create mode 100644 board/Marvell/octeontx/smc.c create mode 100644 board/Marvell/octeontx/soc-utils.c create mode 100644 configs/octeontx_81xx_defconfig create mode 100644 configs/octeontx_83xx_defconfig create mode 100644 include/configs/octeontx_common.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 9b8dadce837..f5f668944f2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1728,6 +1728,14 @@ config ARCH_ROCKCHIP imply TPL_SYSRESET imply USB_FUNCTION_FASTBOOT +config ARCH_OCTEONTX + bool "Support OcteonTX SoCs" + select DM + select ARM64 + select OF_CONTROL + select OF_LIVE + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1826,6 +1834,7 @@ source "arch/arm/mach-lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" +source "arch/arm/mach-octeontx/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1909,6 +1918,7 @@ source "board/bosch/guardian/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" +source "board/Marvell/octeontx/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index bf3890e99bf..87b41983128 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -80,6 +80,7 @@ machine-$(CONFIG_ARCH_STM32MP) += stm32mp machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += u8500 +machine-$(CONFIG_ARCH_OCTEONTX) += octeontx machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQ) += zynq diff --git a/arch/arm/mach-octeontx/Kconfig b/arch/arm/mach-octeontx/Kconfig new file mode 100644 index 00000000000..28ecf9821f9 --- /dev/null +++ b/arch/arm/mach-octeontx/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX + +choice + prompt "OcteonTX board select" + optional + +config TARGET_OCTEONTX_81XX + bool "Marvell OcteonTX CN81XX" + +config TARGET_OCTEONTX_83XX + bool "Marvell OcteonTX CN83XX" + +endchoice + +config SYS_SOC + string + default "octeontx" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx/Makefile b/arch/arm/mach-octeontx/Makefile new file mode 100644 index 00000000000..20cb48ad925 --- /dev/null +++ b/arch/arm/mach-octeontx/Makefile @@ -0,0 +1,9 @@ +#/* SPDX-License-Identifier: GPL-2.0 +# * +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * https://spdx.org/licenses +# */ + +obj-y += lowlevel_init.o clock.o cpu.o + diff --git a/arch/arm/mach-octeontx/clock.c b/arch/arm/mach-octeontx/clock.c new file mode 100644 index 00000000000..9da21077ecd --- /dev/null +++ b/arch/arm/mach-octeontx/clock.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeontx_get_io_clock(void) +{ + union rst_boot rst_boot; + + rst_boot.u = readq(RST_BOOT); + + return rst_boot.s.pnr_mul * PLL_REF_CLK; +} + +/** + * Returns the core clock speed in Hz + */ +u64 octeontx_get_core_clock(void) +{ + union rst_boot rst_boot; + + rst_boot.u = readq(RST_BOOT); + + return rst_boot.s.c_mul * PLL_REF_CLK; +} diff --git a/arch/arm/mach-octeontx/cpu.c b/arch/arm/mach-octeontx/cpu.c new file mode 100644 index 00000000000..9c29c31393c --- /dev/null +++ b/arch/arm/mach-octeontx/cpu.c @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define OTX_MEM_MAP_USED 3 + +/* 1 for 83xx, +1 is end of list which needs to be empty */ +#define OTX_MEM_MAP_MAX (OTX_MEM_MAP_USED + 1 + CONFIG_NR_DRAM_BANKS + 1) + +static struct mm_region otx_mem_map[OTX_MEM_MAP_MAX] = { + { + .virt = 0x800000000000UL, + .phys = 0x800000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0x840000000000UL, + .phys = 0x840000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0x880000000000UL, + .phys = 0x880000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + } + +}; + +struct mm_region *mem_map = otx_mem_map; + +void mem_map_fill(void) +{ + int banks = OTX_MEM_MAP_USED; + u32 dram_start = CONFIG_SYS_TEXT_BASE; + + if (otx_is_soc(CN83XX)) { + otx_mem_map[banks].virt = 0x8c0000000000UL; + otx_mem_map[banks].phys = 0x8c0000000000UL; + otx_mem_map[banks].size = 0x40000000000UL; + otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE; + banks = banks + 1; + } + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + otx_mem_map[banks].virt = dram_start; + otx_mem_map[banks].phys = dram_start; + otx_mem_map[banks].size = gd->ram_size; + otx_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE; + banks = banks + 1; + } +} + +u64 get_page_table_size(void) +{ + return 0x80000; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/arch/arm/mach-octeontx/lowlevel_init.S b/arch/arm/mach-octeontx/lowlevel_init.S new file mode 100644 index 00000000000..41a9f08aedb --- /dev/null +++ b/arch/arm/mach-octeontx/lowlevel_init.S @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include + +.align 8 +.global fdt_base_addr +fdt_base_addr: + .dword 0x0 + +.global save_boot_params +save_boot_params: + /* Read FDT base from x1 register passed by ATF */ + adr x21, fdt_base_addr + str x1, [x21] + + /* Returns */ + b save_boot_params_ret + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + + /* any lowlevel init should go here */ + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/board/Marvell/octeontx/Kconfig b/board/Marvell/octeontx/Kconfig new file mode 100644 index 00000000000..45d115916c9 --- /dev/null +++ b/board/Marvell/octeontx/Kconfig @@ -0,0 +1,14 @@ +if TARGET_OCTEONTX_81XX || TARGET_OCTEONTX_83XX + +config SYS_VENDOR + string + default "Marvell" + +config SYS_BOARD + string + default "octeontx" + +config SYS_CONFIG_NAME + default "octeontx_common" + +endif diff --git a/board/Marvell/octeontx/MAINTAINERS b/board/Marvell/octeontx/MAINTAINERS new file mode 100644 index 00000000000..1f3b12b1abf --- /dev/null +++ b/board/Marvell/octeontx/MAINTAINERS @@ -0,0 +1,8 @@ +OCTEONTX BOARD +M: Aaron Williams +S: Maintained +F: board/Marvell/octeontx/ +F: include/configs/octeontx_81xx.h +F: include/configs/octeontx_83xx.h +F: configs/octeontx_81xx_defconfig +F: configs/octeontx_83xx_defconfig diff --git a/board/Marvell/octeontx/Makefile b/board/Marvell/octeontx/Makefile new file mode 100644 index 00000000000..fbe32ae0035 --- /dev/null +++ b/board/Marvell/octeontx/Makefile @@ -0,0 +1,9 @@ +#/* +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * SPDX-License-Identifier: GPL-2.0 +# * https://spdx.org/licenses +# */ + +obj-y := board.o smc.o soc-utils.o +obj-$(CONFIG_OF_LIBFDT) += board-fdt.o diff --git a/board/Marvell/octeontx/board-fdt.c b/board/Marvell/octeontx/board-fdt.c new file mode 100644 index 00000000000..0b05ef11e9c --- /dev/null +++ b/board/Marvell/octeontx/board-fdt.c @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int fdt_get_mdio_bus(const void *fdt, int phy_offset) +{ + int node, bus = -1; + const u64 *reg; + u64 addr; + + if (phy_offset < 0) + return -1; + /* obtain mdio node and get the reg prop */ + node = fdt_parent_offset(fdt, phy_offset); + if (node < 0) + return -1; + + reg = fdt_getprop(fdt, node, "reg", NULL); + addr = fdt64_to_cpu(*reg); + bus = (addr & (1 << 7)) ? 1 : 0; + return bus; +} + +static int fdt_get_phy_addr(const void *fdt, int phy_offset) +{ + const u32 *reg; + int addr = -1; + + if (phy_offset < 0) + return -1; + reg = fdt_getprop(fdt, phy_offset, "reg", NULL); + addr = fdt32_to_cpu(*reg); + return addr; +} + +void fdt_parse_phy_info(void) +{ + const void *fdt = gd->fdt_blob; + int offset = 0, node, bgx_id = 0, lmacid = 0; + const u32 *val; + char bgxname[24]; + int len, rgx_id = 0, eth_id = 0; + int phandle, phy_offset; + int subnode, i; + int bdknode; + + bdknode = fdt_path_offset(fdt, "/cavium,bdk"); + if (bdknode < 0) { + printf("%s: bdk node is missing from device tree: %s\n", + __func__, fdt_strerror(bdknode)); + } + + offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge"); + if (offset < 1) + return; + + for (bgx_id = 0; bgx_id < MAX_BGX_PER_NODE; bgx_id++) { + int phy_addr[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1}; + bool autoneg_dis[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0}; + int mdio_bus[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = -1}; + bool lmac_reg[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0}; + bool lmac_enable[LMAC_CNT] = {[0 ... LMAC_CNT - 1] = 0}; + + snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx_id); + node = fdt_subnode_offset(fdt, offset, bgxname); + if (node < 0) { + /* check if it is rgx node */ + snprintf(bgxname, sizeof(bgxname), "rgx%d", rgx_id); + node = fdt_subnode_offset(fdt, offset, bgxname); + if (node < 0) { + debug("bgx%d/rgx0 node not found\n", bgx_id); + return; + } + } + debug("bgx%d node found\n", bgx_id); + + /* + * loop through each of the bgx/rgx nodes + * to find PHY nodes + */ + fdt_for_each_subnode(subnode, fdt, node) { + /* Check for reg property */ + val = fdt_getprop(fdt, subnode, "reg", &len); + if (val) { + debug("lmacid = %d\n", lmacid); + lmac_reg[lmacid] = 1; + } + /* check for phy-handle property */ + val = fdt_getprop(fdt, subnode, "phy-handle", &len); + if (val) { + phandle = fdt32_to_cpu(*val); + if (!phandle) { + debug("phandle not valid %d\n", lmacid); + } else { + phy_offset = fdt_node_offset_by_phandle + (fdt, phandle); + phy_addr[lmacid] = fdt_get_phy_addr + (fdt, phy_offset); + mdio_bus[lmacid] = fdt_get_mdio_bus + (fdt, phy_offset); + } + } else { + debug("phy-handle prop not found %d\n", + lmacid); + } + /* check for autonegotiation property */ + val = fdt_getprop(fdt, subnode, + "cavium,disable-autonegotiation", + &len); + if (val) + autoneg_dis[lmacid] = 1; + + eth_id++; + lmacid++; + } + + for (i = 0; i < MAX_LMAC_PER_BGX; i++) { + const char *str; + + snprintf(bgxname, sizeof(bgxname), + "BGX-ENABLE.N0.BGX%d.P%d", bgx_id, i); + if (bdknode >= 0) { + str = fdt_getprop(fdt, bdknode, + bgxname, &len); + if (str) + lmac_enable[i] = + simple_strtol(str, NULL, + 10); + } + } + + lmacid = 0; + bgx_set_board_info(bgx_id, mdio_bus, phy_addr, + autoneg_dis, lmac_reg, lmac_enable); + } +} + +static int fdt_get_bdk_node(void) +{ + int node, ret; + const void *fdt = gd->fdt_blob; + + if (!fdt) { + printf("ERROR: %s: no valid device tree found\n", __func__); + return 0; + } + + ret = fdt_check_header(fdt); + if (ret < 0) { + printf("fdt: %s\n", fdt_strerror(ret)); + return 0; + } + + node = fdt_path_offset(fdt, "/cavium,bdk"); + if (node < 0) { + printf("%s: /cavium,bdk is missing from device tree: %s\n", + __func__, fdt_strerror(node)); + return 0; + } + return node; +} + +const char *fdt_get_board_serial(void) +{ + const void *fdt = gd->fdt_blob; + int node, len = 64; + const char *str = NULL; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + + str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len); + if (!str) + printf("Error: cannot retrieve board serial from fdt\n"); + return str; +} + +const char *fdt_get_board_revision(void) +{ + const void *fdt = gd->fdt_blob; + int node, len = 64; + const char *str = NULL; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + + str = fdt_getprop(fdt, node, "BOARD-REVISION", &len); + if (!str) + printf("Error: cannot retrieve board revision from fdt\n"); + return str; +} + +const char *fdt_get_board_model(void) +{ + const void *fdt = gd->fdt_blob; + int node, len = 16; + const char *str = NULL; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + + str = fdt_getprop(fdt, node, "BOARD-MODEL", &len); + if (!str) + printf("Error: cannot retrieve board model from fdt\n"); + return str; +} + +void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth) +{ + const void *fdt = gd->fdt_blob; + const char *mac = NULL; + int offset = 0, node, len; + int subnode, i = 0; + char bgxname[24]; + + offset = fdt_node_offset_by_compatible(fdt, -1, "pci-bridge"); + if (offset < 0) { + printf("%s couldn't find mrml bridge node in fdt\n", + __func__); + return; + } + if (bgx == 2 && otx_is_soc(CN81XX)) { + snprintf(bgxname, sizeof(bgxname), "rgx%d", 0); + lmac = 0; + } else { + snprintf(bgxname, sizeof(bgxname), "bgx%d", bgx); + } + + node = fdt_subnode_offset(fdt, offset, bgxname); + + fdt_for_each_subnode(subnode, fdt, node) { + if (i++ != lmac) + continue; + /* check for local-mac-address */ + mac = fdt_getprop(fdt, subnode, "local-mac-address", &len); + if (mac) { + debug("%s mac %pM\n", __func__, mac); + memcpy(eth, mac, ARP_HLEN); + } else { + memset(eth, 0, ARP_HLEN); + } + debug("%s eth %pM\n", __func__, eth); + return; + } +} + +int arch_fixup_memory_node(void *blob) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + /* remove "cavium, bdk" node from DT */ + int ret = 0, offset; + + ret = fdt_check_header(blob); + if (ret < 0) { + printf("ERROR: %s\n", fdt_strerror(ret)); + return ret; + } + + if (blob) { + offset = fdt_path_offset(blob, "/cavium,bdk"); + if (offset < 0) { + printf("ERROR: FDT BDK node not found\n"); + return offset; + } + + /* delete node */ + ret = fdt_del_node(blob, offset); + if (ret < 0) { + printf("WARNING : could not remove bdk node\n"); + return ret; + } + + debug("%s deleted bdk node\n", __func__); + } + + return 0; +} + +/** + * Return the FDT base address that was passed by ATF + * + * @return FDT base address received from ATF in x1 register + */ +void *board_fdt_blob_setup(void) +{ + return (void *)fdt_base_addr; +} diff --git a/board/Marvell/octeontx/board.c b/board/Marvell/octeontx/board.c new file mode 100644 index 00000000000..940faacbe37 --- /dev/null +++ b/board/Marvell/octeontx/board.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void octeontx_cleanup_ethaddr(void) +{ + char ename[32]; + + for (int i = 0; i < 20; i++) { + sprintf(ename, i ? "eth%daddr" : "ethaddr", i); + if (env_get(ename)) + env_set(ename, NULL); + } +} + +int octeontx_board_has_pmp(void) +{ + return (otx_is_board("sff8104") || otx_is_board("nas8104")); +} + +int board_early_init_r(void) +{ + pci_init(); + return 0; +} + +int board_init(void) +{ + if (IS_ENABLED(CONFIG_NET_OCTEONTX)) + fdt_parse_phy_info(); + + return 0; +} + +int timer_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = smc_dram_size(0); + gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + mem_map_fill(); + + return 0; +} + +void board_late_probe_devices(void) +{ + struct udevice *dev; + int err, bgx_cnt, i; + + /* Probe MAC(BGX) and NIC PF devices before Network stack init */ + bgx_cnt = otx_is_soc(CN81XX) ? 2 : 4; + for (i = 0; i < bgx_cnt; i++) { + err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_CAVIUM_BGX, i, &dev); + if (err) + debug("%s BGX%d device not found\n", __func__, i); + } + if (otx_is_soc(CN81XX)) { + err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_CAVIUM_RGX, 0, &dev); + if (err) + debug("%s RGX device not found\n", __func__); + } + err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_CAVIUM_NIC, 0, &dev); + if (err) + debug("NIC PF device not found\n"); +} + +/** + * Board late initialization routine. + */ +int board_late_init(void) +{ + char boardname[32]; + char boardserial[150], boardrev[150]; + bool save_env = false; + const char *str; + + /* + * Try to cleanup ethaddr env variables, this is needed + * as with each boot, configuration of network interfaces can change. + */ + octeontx_cleanup_ethaddr(); + + snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model()); + env_set("prompt", boardname); + + set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr)); + + str = fdt_get_board_revision(); + if (str) { + snprintf(boardrev, sizeof(boardrev), "%s", str); + if (env_get("boardrev") && + strcmp(boardrev, env_get("boardrev"))) + save_env = true; + env_set("boardrev", boardrev); + } + + str = fdt_get_board_serial(); + if (str) { + snprintf(boardserial, sizeof(boardserial), "%s", str); + if (env_get("serial#") && + strcmp(boardserial, env_get("serial#"))) + save_env = true; + env_set("serial#", boardserial); + } + + if (IS_ENABLED(CONFIG_NET_OCTEONTX)) + board_late_probe_devices(); + + if (save_env) + env_save(); + + return 0; +} + +/* + * Invoked before relocation, so limit to stack variables. + */ +int checkboard(void) +{ + printf("Board: %s\n", fdt_get_board_model()); + + return 0; +} diff --git a/board/Marvell/octeontx/smc.c b/board/Marvell/octeontx/smc.c new file mode 100644 index 00000000000..5eeba2358b0 --- /dev/null +++ b/board/Marvell/octeontx/smc.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t smc_dram_size(unsigned int node) +{ + struct pt_regs regs; + + regs.regs[0] = OCTEONTX_DRAM_SIZE; + regs.regs[1] = node; + smc_call(®s); + + return regs.regs[0]; +} + diff --git a/board/Marvell/octeontx/soc-utils.c b/board/Marvell/octeontx/soc-utils.c new file mode 100644 index 00000000000..5fd5afd48d5 --- /dev/null +++ b/board/Marvell/octeontx/soc-utils.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include + +int read_platform(void) +{ + int plat = PLATFORM_HW; + + const char *model = fdt_get_board_model(); + + if (model && !strncmp(model, "ASIM-", 5)) + plat = PLATFORM_ASIM; + if (model && !strncmp(model, "EMUL-", 5)) + plat = PLATFORM_EMULATOR; + return plat; +} + +static inline u64 read_midr(void) +{ + u64 result; + + asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result)); + return result; +} + +u8 read_partnum(void) +{ + return ((read_midr() >> 4) & 0xFF); +} + +const char *read_board_name(void) +{ + return fdt_get_board_model(); +} + +bool read_alt_pkg(void) +{ + return false; +} diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig new file mode 100644 index 00000000000..00df57432a8 --- /dev/null +++ b/configs/octeontx_81xx_defconfig @@ -0,0 +1,130 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_OCTEONTX=y +CONFIG_SYS_TEXT_BASE=0x2800000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xF00000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_TARGET_OCTEONTX_81XX=y +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0x87e028000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=4 rootwait rw root=/dev/sda2 coherent_pool=16M" +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Marvell> " +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x2800000 +CONFIG_SYS_MEMTEST_END=0x28f0000 +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_PXE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=16000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=16000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_E1000_SPI=y +CONFIG_CMD_E1000=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCI_SRIOV=y +CONFIG_PCI_ARID=y +CONFIG_PCI_OCTEONTX=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_WDT=y +CONFIG_ERRNO_STR=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig new file mode 100644 index 00000000000..e8cacb859fd --- /dev/null +++ b/configs/octeontx_83xx_defconfig @@ -0,0 +1,129 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_OCTEONTX=y +CONFIG_SYS_TEXT_BASE=0x2800000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xF00000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_TARGET_OCTEONTX_83XX=y +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0x87e028000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/sda2 coherent_pool=16M" +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Marvell> " +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_PXE=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=16000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=16000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_AQUANTIA=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_E1000_SPI=y +CONFIG_CMD_E1000=y +CONFIG_NET_OCTEONTX=y +CONFIG_OCTEONTX_SMI=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCI_SRIOV=y +CONFIG_PCI_ARID=y +CONFIG_PCI_OCTEONTX=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_WDT=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h new file mode 100644 index 00000000000..b66aa8b54e2 --- /dev/null +++ b/include/configs/octeontx_common.h @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __OCTEONTX_COMMON_H__ +#define __OCTEONTX_COMMON_H__ + +#define CONFIG_SUPPORT_RAW_INITRD + +/** Maximum size of image supported for bootm (and bootable FIT images) */ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) + +/** Memory base address */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE + +/** Stack starting address */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + +/** Heap size for U-Boot */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +/* Allow environment variable to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/** Reduce hashes printed out */ +#define CONFIG_TFTP_TSIZE + +/* Autoboot options */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 30 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/* AHCI support Definitions */ +#ifdef CONFIG_DM_SCSI +/** Enable 48-bit SATA addressing */ +# define CONFIG_LBA48 +/** Enable 64-bit addressing */ +# define CONFIG_SYS_64BIT_LBA +#endif + +/***** SPI Defines *********/ +#ifdef CONFIG_DM_SPI_FLASH +# define CONFIG_SF_DEFAULT_BUS 0 +# define CONFIG_SF_DEFAULT_CS 0 +#endif + +/** Extra environment settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=20080000\0" \ + "autoload=0\0" + +/** Environment defines */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MAXARGS 64 /** max command args */ + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT env_get("prompt") + +/** EMMC specific defines */ +#if defined(CONFIG_MMC_OCTEONTX) +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_CMD_BKOPS_ENABLE +#endif + +#if defined(CONFIG_NAND_OCTEONTX) +/*#define CONFIG_MTD_CONCAT */ +#define CONFIG_SYS_MAX_NAND_DEVICE 8 +#define CONFIG_SYS_NAND_ONFI_DETECTION +#endif + +#endif /* __OCTEONTX_COMMON_H__ */ -- cgit v1.3.1 From 0a668f6d38a2a631eb872f4f1107399db46b1c15 Mon Sep 17 00:00:00 2001 From: Suneel Garapati Date: Sat, 19 Oct 2019 18:47:37 -0700 Subject: arm: octeontx2: Add support for OcteonTX2 SoC platforms This patch adds support for all OcteonTX2 96xx/95xx boards from Marvell. For 96xx boards, use octeontx_96xx_defconfig and for 95xx boards, use octeontx_95xx_defconfig. Signed-off-by: Suneel Garapati --- arch/arm/Kconfig | 14 ++ arch/arm/Makefile | 1 + arch/arm/mach-octeontx2/Kconfig | 23 +++ arch/arm/mach-octeontx2/Makefile | 9 ++ arch/arm/mach-octeontx2/clock.c | 35 +++++ arch/arm/mach-octeontx2/config.mk | 4 + arch/arm/mach-octeontx2/cpu.c | 72 ++++++++++ arch/arm/mach-octeontx2/lowlevel_init.S | 33 +++++ board/Marvell/octeontx2/Kconfig | 14 ++ board/Marvell/octeontx2/MAINTAINERS | 8 ++ board/Marvell/octeontx2/Makefile | 9 ++ board/Marvell/octeontx2/board-fdt.c | 221 ++++++++++++++++++++++++++++ board/Marvell/octeontx2/board.c | 247 ++++++++++++++++++++++++++++++++ board/Marvell/octeontx2/smc.c | 58 ++++++++ board/Marvell/octeontx2/soc-utils.c | 49 +++++++ configs/octeontx2_95xx_defconfig | 105 ++++++++++++++ configs/octeontx2_96xx_defconfig | 131 +++++++++++++++++ include/configs/octeontx2_common.h | 72 ++++++++++ 18 files changed, 1105 insertions(+) create mode 100644 arch/arm/mach-octeontx2/Kconfig create mode 100644 arch/arm/mach-octeontx2/Makefile create mode 100644 arch/arm/mach-octeontx2/clock.c create mode 100644 arch/arm/mach-octeontx2/config.mk create mode 100644 arch/arm/mach-octeontx2/cpu.c create mode 100644 arch/arm/mach-octeontx2/lowlevel_init.S create mode 100644 board/Marvell/octeontx2/Kconfig create mode 100644 board/Marvell/octeontx2/MAINTAINERS create mode 100644 board/Marvell/octeontx2/Makefile create mode 100644 board/Marvell/octeontx2/board-fdt.c create mode 100644 board/Marvell/octeontx2/board.c create mode 100644 board/Marvell/octeontx2/smc.c create mode 100644 board/Marvell/octeontx2/soc-utils.c create mode 100644 configs/octeontx2_95xx_defconfig create mode 100644 configs/octeontx2_96xx_defconfig create mode 100644 include/configs/octeontx2_common.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f5f668944f2..870620713b3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1736,6 +1736,16 @@ config ARCH_OCTEONTX select OF_LIVE select BOARD_LATE_INIT select SYS_CACHE_SHIFT_7 + +config ARCH_OCTEONTX2 + bool "Support OcteonTX2 SoCs" + select DM + select ARM64 + select OF_CONTROL + select OF_LIVE + select BOARD_LATE_INIT + select SYS_CACHE_SHIFT_7 + config TARGET_THUNDERX_88XX bool "Support ThunderX 88xx" select ARM64 @@ -1835,6 +1845,9 @@ source "arch/arm/mach-lpc32xx/Kconfig" source "arch/arm/mach-mvebu/Kconfig" source "arch/arm/mach-octeontx/Kconfig" + +source "arch/arm/mach-octeontx2/Kconfig" + source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/mach-imx/mx2/Kconfig" @@ -1919,6 +1932,7 @@ source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/Marvell/octeontx/Kconfig" +source "board/Marvell/octeontx2/Kconfig" source "board/armadeus/apf27/Kconfig" source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress64/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 87b41983128..28b523b37c7 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -81,6 +81,7 @@ machine-$(CONFIG_ARCH_SUNXI) += sunxi machine-$(CONFIG_ARCH_TEGRA) += tegra machine-$(CONFIG_ARCH_U8500) += u8500 machine-$(CONFIG_ARCH_OCTEONTX) += octeontx +machine-$(CONFIG_ARCH_OCTEONTX2) += octeontx2 machine-$(CONFIG_ARCH_UNIPHIER) += uniphier machine-$(CONFIG_ARCH_VERSAL) += versal machine-$(CONFIG_ARCH_ZYNQ) += zynq diff --git a/arch/arm/mach-octeontx2/Kconfig b/arch/arm/mach-octeontx2/Kconfig new file mode 100644 index 00000000000..8e5cb0f6380 --- /dev/null +++ b/arch/arm/mach-octeontx2/Kconfig @@ -0,0 +1,23 @@ +if ARCH_OCTEONTX2 + +choice + prompt "OcteonTX2 board select" + optional + +config TARGET_OCTEONTX2_95XX + bool "Marvell OcteonTX2 CN95XX" + +config TARGET_OCTEONTX2_96XX + bool "Marvell OcteonTX2 CN96XX" + +endchoice + +config SYS_SOC + string + default "octeontx2" + +config SYS_PCI_64BIT + bool + default y + +endif diff --git a/arch/arm/mach-octeontx2/Makefile b/arch/arm/mach-octeontx2/Makefile new file mode 100644 index 00000000000..c3192343dd2 --- /dev/null +++ b/arch/arm/mach-octeontx2/Makefile @@ -0,0 +1,9 @@ +#/* +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * SPDX-License-Identifier: GPL-2.0 +# * https://spdx.org/licenses +# */ + +obj-y += lowlevel_init.o clock.o cpu.o + diff --git a/arch/arm/mach-octeontx2/clock.c b/arch/arm/mach-octeontx2/clock.c new file mode 100644 index 00000000000..9da21077ecd --- /dev/null +++ b/arch/arm/mach-octeontx2/clock.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +/** + * Returns the I/O clock speed in Hz + */ +u64 octeontx_get_io_clock(void) +{ + union rst_boot rst_boot; + + rst_boot.u = readq(RST_BOOT); + + return rst_boot.s.pnr_mul * PLL_REF_CLK; +} + +/** + * Returns the core clock speed in Hz + */ +u64 octeontx_get_core_clock(void) +{ + union rst_boot rst_boot; + + rst_boot.u = readq(RST_BOOT); + + return rst_boot.s.c_mul * PLL_REF_CLK; +} diff --git a/arch/arm/mach-octeontx2/config.mk b/arch/arm/mach-octeontx2/config.mk new file mode 100644 index 00000000000..9214f6b7425 --- /dev/null +++ b/arch/arm/mach-octeontx2/config.mk @@ -0,0 +1,4 @@ +ifeq ($(CONFIG_ARCH_OCTEONTX2),y) +PLATFORM_CPPFLAGS += $(call cc-option,-march=armv8.2-a,) +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=octeontx2,) +endif diff --git a/arch/arm/mach-octeontx2/cpu.c b/arch/arm/mach-octeontx2/cpu.c new file mode 100644 index 00000000000..2a6d5e86613 --- /dev/null +++ b/arch/arm/mach-octeontx2/cpu.c @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define OTX2_MEM_MAP_USED 4 + +/* +1 is end of list which needs to be empty */ +#define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1) + +static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = { + { + .virt = 0x800000000000UL, + .phys = 0x800000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0x840000000000UL, + .phys = 0x840000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0x880000000000UL, + .phys = 0x880000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + }, { + .virt = 0x8c0000000000UL, + .phys = 0x8c0000000000UL, + .size = 0x40000000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE + } +}; + +struct mm_region *mem_map = otx2_mem_map; + +void mem_map_fill(void) +{ + int banks = OTX2_MEM_MAP_USED; + u32 dram_start = CONFIG_SYS_TEXT_BASE; + + for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + otx2_mem_map[banks].virt = dram_start; + otx2_mem_map[banks].phys = dram_start; + otx2_mem_map[banks].size = gd->ram_size; + otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NON_SHARE; + banks = banks + 1; + } +} + +u64 get_page_table_size(void) +{ + return 0x80000; +} + +void reset_cpu(ulong addr) +{ +} diff --git a/arch/arm/mach-octeontx2/lowlevel_init.S b/arch/arm/mach-octeontx2/lowlevel_init.S new file mode 100644 index 00000000000..41a9f08aedb --- /dev/null +++ b/arch/arm/mach-octeontx2/lowlevel_init.S @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include + +.align 8 +.global fdt_base_addr +fdt_base_addr: + .dword 0x0 + +.global save_boot_params +save_boot_params: + /* Read FDT base from x1 register passed by ATF */ + adr x21, fdt_base_addr + str x1, [x21] + + /* Returns */ + b save_boot_params_ret + +ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ + + /* any lowlevel init should go here */ + + mov lr, x29 /* Restore LR */ + ret +ENDPROC(lowlevel_init) diff --git a/board/Marvell/octeontx2/Kconfig b/board/Marvell/octeontx2/Kconfig new file mode 100644 index 00000000000..99291d795b5 --- /dev/null +++ b/board/Marvell/octeontx2/Kconfig @@ -0,0 +1,14 @@ +if TARGET_OCTEONTX2_95XX || TARGET_OCTEONTX2_96XX + +config SYS_VENDOR + string + default "Marvell" + +config SYS_BOARD + string + default "octeontx2" + +config SYS_CONFIG_NAME + default "octeontx2_common" + +endif diff --git a/board/Marvell/octeontx2/MAINTAINERS b/board/Marvell/octeontx2/MAINTAINERS new file mode 100644 index 00000000000..eec1d77dd10 --- /dev/null +++ b/board/Marvell/octeontx2/MAINTAINERS @@ -0,0 +1,8 @@ +OCTEONTX2 BOARD +M: Aaron Williams +S: Maintained +F: board/Marvell/octeontx2/ +F: include/configs/octeontx2_96xx.h +F: include/configs/octeontx2_95xx.h +F: configs/octeontx2_96xx_defconfig +F: configs/octeontx2_95xx_defconfig diff --git a/board/Marvell/octeontx2/Makefile b/board/Marvell/octeontx2/Makefile new file mode 100644 index 00000000000..1f763b197b2 --- /dev/null +++ b/board/Marvell/octeontx2/Makefile @@ -0,0 +1,9 @@ +#/* SPDX-License-Identifier: GPL-2.0 +# * +# * Copyright (C) 2018 Marvell International Ltd. +# * +# * https://spdx.org/licenses +# */ + +obj-y := board.o smc.o soc-utils.o +obj-$(CONFIG_OF_LIBFDT) += board-fdt.o diff --git a/board/Marvell/octeontx2/board-fdt.c b/board/Marvell/octeontx2/board-fdt.c new file mode 100644 index 00000000000..a4771af4c1d --- /dev/null +++ b/board/Marvell/octeontx2/board-fdt.c @@ -0,0 +1,221 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int fdt_get_bdk_node(void) +{ + int node, ret; + const void *fdt = gd->fdt_blob; + + if (!fdt) { + printf("ERROR: %s: no valid device tree found\n", __func__); + return 0; + } + + ret = fdt_check_header(fdt); + if (ret < 0) { + printf("fdt: %s\n", fdt_strerror(ret)); + return 0; + } + + node = fdt_path_offset(fdt, "/cavium,bdk"); + if (node < 0) { + printf("%s: /cavium,bdk is missing from device tree: %s\n", + __func__, fdt_strerror(node)); + return 0; + } + return node; +} + +u64 fdt_get_board_mac_addr(void) +{ + int node, len = 16; + const char *str = NULL; + const void *fdt = gd->fdt_blob; + u64 mac_addr = 0; + + node = fdt_get_bdk_node(); + if (!node) + return mac_addr; + str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS", &len); + if (str) + mac_addr = simple_strtol(str, NULL, 16); + return mac_addr; +} + +int fdt_get_board_mac_cnt(void) +{ + int node, len = 16; + const char *str = NULL; + const void *fdt = gd->fdt_blob; + int mac_count = 0; + + node = fdt_get_bdk_node(); + if (!node) + return mac_count; + str = fdt_getprop(fdt, node, "BOARD-MAC-ADDRESS-NUM", &len); + if (str) { + mac_count = simple_strtol(str, NULL, 10); + if (!mac_count) + mac_count = simple_strtol(str, NULL, 16); + debug("fdt: MAC_NUM %d\n", mac_count); + } else { + printf("Error: cannot retrieve mac count prop from fdt\n"); + } + str = fdt_getprop(gd->fdt_blob, node, "BOARD-MAC-ADDRESS-NUM-OVERRIDE", + &len); + if (str) { + if (simple_strtol(str, NULL, 10) >= 0) + mac_count = simple_strtol(str, NULL, 10); + debug("fdt: MAC_NUM %d\n", mac_count); + } else { + printf("Error: cannot retrieve mac num override prop\n"); + } + return mac_count; +} + +const char *fdt_get_board_serial(void) +{ + const void *fdt = gd->fdt_blob; + int node, len = 64; + const char *str = NULL; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + + str = fdt_getprop(fdt, node, "BOARD-SERIAL", &len); + if (!str) + printf("Error: cannot retrieve board serial from fdt\n"); + return str; +} + +const char *fdt_get_board_revision(void) +{ + const void *fdt = gd->fdt_blob; + int node, len = 64; + const char *str = NULL; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + + str = fdt_getprop(fdt, node, "BOARD-REVISION", &len); + if (!str) + printf("Error: cannot retrieve board revision from fdt\n"); + return str; +} + +const char *fdt_get_board_model(void) +{ + int node, len = 16; + const char *str = NULL; + const void *fdt = gd->fdt_blob; + + node = fdt_get_bdk_node(); + if (!node) + return NULL; + str = fdt_getprop(fdt, node, "BOARD-MODEL", &len); + if (!str) + printf("Error: cannot retrieve board model from fdt\n"); + return str; +} + +int arch_fixup_memory_node(void *blob) +{ + return 0; +} + +int ft_board_setup(void *blob, struct bd_info *bd) +{ + int nodeoff, node, ret, i; + const char *temp; + + static const char * const + octeontx_brd_nodes[] = {"BOARD-MODEL", + "BOARD-SERIAL", + "BOARD-MAC-ADDRESS", + "BOARD-REVISION", + "BOARD-MAC-ADDRESS-NUM" + }; + char nodes[ARRAY_SIZE(octeontx_brd_nodes)][32]; + + ret = fdt_check_header(blob); + if (ret < 0) { + printf("ERROR: %s\n", fdt_strerror(ret)); + return ret; + } + + if (blob) { + nodeoff = fdt_path_offset(blob, "/cavium,bdk"); + if (nodeoff < 0) { + printf("ERROR: FDT BDK node not found\n"); + return nodeoff; + } + + /* Read properties in temporary variables */ + for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) { + temp = fdt_getprop(blob, nodeoff, + octeontx_brd_nodes[i], NULL); + strncpy(nodes[i], temp, sizeof(nodes[i])); + } + + /* Delete cavium,bdk node */ + ret = fdt_del_node(blob, nodeoff); + if (ret < 0) { + printf("WARNING : could not remove cavium, bdk node\n"); + return ret; + } + debug("%s deleted 'cavium,bdk' node\n", __func__); + /* + * Add a new node at root level which would have + * necessary info + */ + node = fdt_add_subnode(blob, 0, "octeontx_brd"); + if (node < 0) { + printf("Cannot create node octeontx_brd: %s\n", + fdt_strerror(node)); + return -EIO; + } + + /* Populate properties in node */ + for (i = 0; i < ARRAY_SIZE(octeontx_brd_nodes); i++) { + if (fdt_setprop_string(blob, node, + octeontx_brd_nodes[i], + nodes[i])) { + printf("Can't set %s\n", nodes[i]); + return -EIO; + } + } + } + + return 0; +} + +/** + * Return the FDT base address that was passed by ATF + * + * @return FDT base address received from ATF in x1 register + */ +void *board_fdt_blob_setup(void) +{ + return (void *)fdt_base_addr; +} diff --git a/board/Marvell/octeontx2/board.c b/board/Marvell/octeontx2/board.c new file mode 100644 index 00000000000..50e903d9aa9 --- /dev/null +++ b/board/Marvell/octeontx2/board.c @@ -0,0 +1,247 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void cleanup_env_ethaddr(void) +{ + char ename[32]; + + for (int i = 0; i < 20; i++) { + sprintf(ename, i ? "eth%daddr" : "ethaddr", i); + if (env_get(ename)) + env_set(ename, NULL); + } +} + +void octeontx2_board_get_mac_addr(u8 index, u8 *mac_addr) +{ + u64 tmp_mac, board_mac_addr = fdt_get_board_mac_addr(); + static int board_mac_num; + + board_mac_num = fdt_get_board_mac_cnt(); + if ((!is_zero_ethaddr((u8 *)&board_mac_addr)) && board_mac_num) { + tmp_mac = board_mac_addr; + tmp_mac += index; + tmp_mac = swab64(tmp_mac) >> 16; + memcpy(mac_addr, (u8 *)&tmp_mac, ARP_HLEN); + board_mac_num--; + } else { + memset(mac_addr, 0, ARP_HLEN); + } + debug("%s mac %pM\n", __func__, mac_addr); +} + +void board_quiesce_devices(void) +{ + struct uclass *uc_dev; + int ret; + + /* Removes all RVU PF devices */ + ret = uclass_get(UCLASS_ETH, &uc_dev); + if (uc_dev) + ret = uclass_destroy(uc_dev); + if (ret) + printf("couldn't remove rvu pf devices\n"); + + if (IS_ENABLED(CONFIG_OCTEONTX2_CGX_INTF)) { + /* Bring down all cgx lmac links */ + cgx_intf_shutdown(); + } + + /* Removes all CGX and RVU AF devices */ + ret = uclass_get(UCLASS_MISC, &uc_dev); + if (uc_dev) + ret = uclass_destroy(uc_dev); + if (ret) + printf("couldn't remove misc (cgx/rvu_af) devices\n"); + + /* SMC call - removes all LF<->PF mappings */ + smc_disable_rvu_lfs(0); +} + +int board_early_init_r(void) +{ + pci_init(); + return 0; +} + +int board_init(void) +{ + return 0; +} + +int timer_init(void) +{ + return 0; +} + +int dram_init(void) +{ + gd->ram_size = smc_dram_size(0); + gd->ram_size -= CONFIG_SYS_SDRAM_BASE; + + mem_map_fill(); + + return 0; +} + +void board_late_probe_devices(void) +{ + struct udevice *dev; + int err, cgx_cnt = 3, i; + + /* Probe MAC(CGX) and NIC AF devices before Network stack init */ + for (i = 0; i < cgx_cnt; i++) { + err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_CAVIUM_CGX, i, &dev); + if (err) + debug("%s CGX%d device not found\n", __func__, i); + } + err = dm_pci_find_device(PCI_VENDOR_ID_CAVIUM, + PCI_DEVICE_ID_CAVIUM_RVU_AF, 0, &dev); + if (err) + debug("NIC AF device not found\n"); +} + +/** + * Board late initialization routine. + */ +int board_late_init(void) +{ + char boardname[32]; + char boardserial[150], boardrev[150]; + long val; + bool save_env = false; + const char *str; + + debug("%s()\n", __func__); + + /* + * Now that pci_init initializes env device. + * Try to cleanup ethaddr env variables, this is needed + * as with each boot, configuration of QLM can change. + */ + cleanup_env_ethaddr(); + + snprintf(boardname, sizeof(boardname), "%s> ", fdt_get_board_model()); + env_set("prompt", boardname); + set_working_fdt_addr(env_get_hex("fdtcontroladdr", fdt_base_addr)); + + str = fdt_get_board_revision(); + if (str) { + snprintf(boardrev, sizeof(boardrev), "%s", str); + if (env_get("boardrev") && + strcmp(boardrev, env_get("boardrev"))) + save_env = true; + env_set("boardrev", boardrev); + } + + str = fdt_get_board_serial(); + if (str) { + snprintf(boardserial, sizeof(boardserial), "%s", str); + if (env_get("serial#") && + strcmp(boardserial, env_get("serial#"))) + save_env = true; + env_set("serial#", boardserial); + } + + val = env_get_hex("disable_ooo", 0); + smc_configure_ooo(val); + + if (IS_ENABLED(CONFIG_NET_OCTEONTX2)) + board_late_probe_devices(); + + if (save_env) + env_save(); + + return 0; +} + +/* + * Invoked before relocation, so limit to stack variables. + */ +int checkboard(void) +{ + printf("Board: %s\n", fdt_get_board_model()); + + return 0; +} + +void board_acquire_flash_arb(bool acquire) +{ + union cpc_boot_ownerx ownerx; + + if (!acquire) { + ownerx.u = readl(CPC_BOOT_OWNERX(3)); + ownerx.s.boot_req = 0; + writel(ownerx.u, CPC_BOOT_OWNERX(3)); + } else { + ownerx.u = 0; + ownerx.s.boot_req = 1; + writel(ownerx.u, CPC_BOOT_OWNERX(3)); + udelay(1); + do { + ownerx.u = readl(CPC_BOOT_OWNERX(3)); + } while (ownerx.s.boot_wait); + } +} + +int last_stage_init(void) +{ + (void)smc_flsf_fw_booted(); + return 0; +} + +static int do_go_uboot(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + typedef void __noreturn (*uboot_entry_t)(ulong, void *); + uboot_entry_t entry; + ulong addr; + void *fdt; + + if (argc < 2) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[1], NULL, 16); + fdt = board_fdt_blob_setup(); + entry = (uboot_entry_t)addr; + flush_cache((ulong)addr, 1 << 20); /* 1MiB should be enough */ + dcache_disable(); + + printf("## Starting U-Boot at %p (FDT at %p)...\n", entry, fdt); + + entry(0, fdt); + + return 0; +} + +U_BOOT_CMD(go_uboot, 2, 0, do_go_uboot, + "Start U-Boot from RAM (pass FDT via x1 register)", + ""); diff --git a/board/Marvell/octeontx2/smc.c b/board/Marvell/octeontx2/smc.c new file mode 100644 index 00000000000..9e3169576c6 --- /dev/null +++ b/board/Marvell/octeontx2/smc.c @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +ssize_t smc_dram_size(unsigned int node) +{ + struct pt_regs regs; + + regs.regs[0] = OCTEONTX2_DRAM_SIZE; + regs.regs[1] = node; + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t smc_disable_rvu_lfs(unsigned int node) +{ + struct pt_regs regs; + + regs.regs[0] = OCTEONTX2_DISABLE_RVU_LFS; + regs.regs[1] = node; + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t smc_configure_ooo(unsigned int val) +{ + struct pt_regs regs; + + regs.regs[0] = OCTEONTX2_CONFIG_OOO; + regs.regs[1] = val; + smc_call(®s); + + return regs.regs[0]; +} + +ssize_t smc_flsf_fw_booted(void) +{ + struct pt_regs regs; + + regs.regs[0] = OCTEONTX2_FSAFE_PR_BOOT_SUCCESS; + smc_call(®s); + + return regs.regs[0]; +} diff --git a/board/Marvell/octeontx2/soc-utils.c b/board/Marvell/octeontx2/soc-utils.c new file mode 100644 index 00000000000..1cba7fb5963 --- /dev/null +++ b/board/Marvell/octeontx2/soc-utils.c @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int read_platform(void) +{ + int plat = PLATFORM_HW; + + const char *model = fdt_get_board_model(); + + if (model && !strncmp(model, "ASIM-", 5)) + plat = PLATFORM_ASIM; + if (model && !strncmp(model, "EMUL-", 5)) + plat = PLATFORM_EMULATOR; + + return plat; +} + +static inline u64 read_midr(void) +{ + u64 result; + + asm ("mrs %[rd],MIDR_EL1" : [rd] "=r" (result)); + return result; +} + +u8 read_partnum(void) +{ + return ((read_midr() >> 4) & 0xFF); +} + +const char *read_board_name(void) +{ + return fdt_get_board_model(); +} + diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig new file mode 100644 index 00000000000..6aeb12c3f90 --- /dev/null +++ b/configs/octeontx2_95xx_defconfig @@ -0,0 +1,105 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_OCTEONTX2=y +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xF00000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_TARGET_OCTEONTX2_95XX=y +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0x87e028000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=6 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M" +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Marvell> " +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_MEMTEST_START=0x04000000 +CONFIG_SYS_MEMTEST_END=0x040f0000 +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_PXE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=125000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM_I2C=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=125000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_DM_ETH=y +CONFIG_NET_OCTEONTX2=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCI_SRIOV=y +CONFIG_PCI_ARID=y +CONFIG_PCI_OCTEONTX=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_WDT=y +CONFIG_ERRNO_STR=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig new file mode 100644 index 00000000000..05cc1332d6b --- /dev/null +++ b/configs/octeontx2_96xx_defconfig @@ -0,0 +1,131 @@ +CONFIG_ARM=y +# CONFIG_ARM64_SUPPORT_AARCH32 is not set +CONFIG_ARCH_OCTEONTX2=y +CONFIG_SYS_TEXT_BASE=0x04000000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x8000 +CONFIG_ENV_OFFSET=0xF00000 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_TARGET_OCTEONTX2_96XX=y +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0x87e028000000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_AHCI=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyAMA0,115200n8 earlycon=pl011,0x87e028000000 maxcpus=24 rootwait rw root=/dev/mmcblk0p2 coherent_pool=16M" +CONFIG_VERSION_VARIABLE=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="Marvell> " +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MX_CYCLIC=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_SHA1SUM=y +CONFIG_SHA1SUM_VERIFY=y +CONFIG_CMD_DM=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_RARP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CDP=y +CONFIG_CMD_SNTP=y +CONFIG_CMD_DNS=y +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_PXE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_BOARD=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=125000000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SCSI_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_DM_I2C=y +CONFIG_I2C_SET_DEFAULT_BUS_NUM=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_MMC_OCTEONTX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=125000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_PHYLIB=y +CONFIG_PHY_MARVELL=y +CONFIG_PHY_VITESSE=y +CONFIG_DM_ETH=y +CONFIG_E1000=y +CONFIG_E1000_SPI=y +CONFIG_CMD_E1000=y +CONFIG_NET_OCTEONTX2=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_REGION_MULTI_ENTRY=y +CONFIG_PCI_SRIOV=y +CONFIG_PCI_ARID=y +CONFIG_PCI_OCTEONTX=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RTC=y +CONFIG_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_PL01X_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_OCTEON_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_WDT=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h new file mode 100644 index 00000000000..87dcf5fb37f --- /dev/null +++ b/include/configs/octeontx2_common.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright (C) 2018 Marvell International Ltd. + * + * https://spdx.org/licenses + */ + +#ifndef __OCTEONTX2_COMMON_H__ +#define __OCTEONTX2_COMMON_H__ + +#define CONFIG_SUPPORT_RAW_INITRD + +/** Maximum size of image supported for bootm (and bootable FIT images) */ +#define CONFIG_SYS_BOOTM_LEN (256 << 20) + +/** Memory base address */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_TEXT_BASE + +/** Stack starting address */ +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xffff0) + +/** Heap size for U-Boot */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 64 * 1024 * 1024) + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_LAST_STAGE_INIT + +/* Allow environment variable to be overwritten */ +#define CONFIG_ENV_OVERWRITE + +/** Reduce hashes printed out */ +#define CONFIG_TFTP_TSIZE + +/* Autoboot options */ +#define CONFIG_RESET_TO_RETRY +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 30 + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE + +/** Extra environment settings */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=20080000\0" \ + "ethrotate=yes\0" \ + "autoload=0\0" + +/** Environment defines */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#endif + +/* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /** Console I/O Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_MAXARGS 64 /** max command args */ + +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 + +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT env_get("prompt") + +#if defined(CONFIG_MMC_OCTEONTX) +#define MMC_SUPPORTS_TUNING +/** EMMC specific defines */ +#define CONFIG_SUPPORT_EMMC_BOOT +#define CONFIG_SUPPORT_EMMC_RPMB +#define CONFIG_CMD_BKOPS_ENABLE +#endif + +#endif /* __OCTEONTX2_COMMON_H__ */ -- cgit v1.3.1