From a078ebb86f6c414f12aa132fc6d15c4946fedad0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 10 Nov 2025 16:24:12 +0100 Subject: firmware: xilinx: Add support for enhancement SMC format Versal Gen 2 is using different SMC format that's why firmware and clock drivers needs to be align with it. Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/16bdee56fd75113c6d531bae7a8a34900b10280d.1762788250.git.michal.simek@amd.com --- include/zynqmp_firmware.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 7f93241b193..72f6459b91c 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -521,4 +521,10 @@ typedef int (*smc_call_handler_t)(u32 api_id, u32 arg0, u32 arg1, u32 arg2, extern smc_call_handler_t __data smc_call_handler; +#define PM_MODULE_ID 2 + +#define PASS_THROUGH_FW_CMD_ID GENMASK(11, 0) +#define PLM_MODULE_ID_MASK GENMASK(15, 8) +#define API_ID_MASK GENMASK(7, 0) + #endif /* _ZYNQMP_FIRMWARE_H_ */ -- cgit v1.2.3