From 5d2d5c4f2348fb0e7156a42f78d0627392bb6966 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 7 Apr 2021 09:12:38 +0200 Subject: mips: octeon: Add Octeon III NIC23 board support This patch adds the basic support for the PCIe target board equipped with the Octeon III CN2350 SoC. Signed-off-by: Stefan Roese --- include/configs/octeon_nic23.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/configs/octeon_nic23.h (limited to 'include') diff --git a/include/configs/octeon_nic23.h b/include/configs/octeon_nic23.h new file mode 100644 index 00000000000..0a7b4d8f93e --- /dev/null +++ b/include/configs/octeon_nic23.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 + * Marvell + */ + +#ifndef __CONFIG_H__ +#define __CONFIG_H__ + +/* + * SATA/SCSI/AHCI configuration + */ +/* AHCI support Definitions */ +/** Enable 48-bit SATA addressing */ +#define CONFIG_LBA48 +/** Enable 64-bit addressing */ +#define CONFIG_SYS_64BIT_LBA + +#include "octeon_common.h" + +#endif /* __CONFIG_H__ */ -- cgit v1.3.1 From c83f63ae544b819522300c2363fb6dca51890dee Mon Sep 17 00:00:00 2001 From: Ivan Uvarov Date: Mon, 19 Apr 2021 12:30:57 +0300 Subject: sunxi: DT: R40: Update device tree files from Linux 5.12 Update R40 .dts{,i} and dt-binding headers to current version from kernel. Files taken from Linux 5.12-rc1 release (commit fe07bfda2fb9cdef8a4d4008a409bb02f35f1bd8) Signed-off-by: Ivan Uvarov Reviewed-by: Andre Przywara Signed-off-by: Andre Przywara --- arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts | 23 +- arch/arm/dts/sun8i-r40.dtsi | 375 +++++++++++++++++++-- arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts | 12 +- include/dt-bindings/clock/sun8i-r40-ccu.h | 6 +- include/dt-bindings/interrupt-controller/arm-gic.h | 5 +- include/dt-bindings/thermal/thermal.h | 3 +- 6 files changed, 375 insertions(+), 49 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts index c488aaacbd6..a6a1087a0c9 100644 --- a/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts +++ b/arch/arm/dts/sun8i-r40-bananapi-m2-ultra.dts @@ -129,7 +129,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_dc1sw>; status = "okay"; }; @@ -164,6 +164,10 @@ #include "axp22x.dtsi" +&ir0 { + status = "okay"; +}; + &mmc0 { vmmc-supply = <®_dcdc1>; bus-width = <4>; @@ -201,10 +205,15 @@ &pio { pinctrl-names = "default"; pinctrl-0 = <&clk_out_a_pin>; + vcc-pa-supply = <®_aldo2>; + vcc-pc-supply = <®_dcdc1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_eldo1>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; }; ®_aldo2 { - regulator-always-on; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-name = "vcc-pa"; @@ -218,16 +227,16 @@ }; ®_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy"; }; ®_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; ®_dcdc2 { diff --git a/arch/arm/dts/sun8i-r40.dtsi b/arch/arm/dts/sun8i-r40.dtsi index 06b685869f5..d5ad3b9efd1 100644 --- a/arch/arm/dts/sun8i-r40.dtsi +++ b/arch/arm/dts/sun8i-r40.dtsi @@ -44,8 +44,10 @@ #include #include #include +#include #include #include +#include / { #address-cells = <1>; @@ -78,25 +80,25 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; }; - cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <1>; }; - cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <2>; }; - cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <3>; @@ -109,6 +111,22 @@ status = "disabled"; }; + thermal-zones { + cpu_thermal: cpu0-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 0>; + }; + + gpu_thermal: gpu-thermal { + /* milliseconds */ + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -118,11 +136,11 @@ display_clocks: clock@1000000 { compatible = "allwinner,sun8i-r40-de2-clk", "allwinner,sun8i-h3-de2-clk"; - reg = <0x01000000 0x100000>; - clocks = <&ccu CLK_DE>, - <&ccu CLK_BUS_DE>; - clock-names = "mod", - "bus"; + reg = <0x01000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, + <&ccu CLK_DE>; + clock-names = "bus", + "mod"; resets = <&ccu RST_BUS_DE>; #clock-cells = <1>; #reset-cells = <1>; @@ -172,6 +190,48 @@ }; }; + deinterlace: deinterlace@1400000 { + compatible = "allwinner,sun8i-r40-deinterlace", + "allwinner,sun8i-h3-deinterlace"; + reg = <0x01400000 0x20000>; + clocks = <&ccu CLK_BUS_DEINTERLACE>, + <&ccu CLK_DEINTERLACE>, + /* + * NOTE: Contrary to what datasheet claims, + * DRAM deinterlace gate doesn't exist and + * it's shared with CSI1. + */ + <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_DEINTERLACE>; + interrupts = ; + interconnects = <&mbus 9>; + interconnect-names = "dma-mem"; + }; + + syscon: system-control@1c00000 { + compatible = "allwinner,sun8i-r40-system-control", + "allwinner,sun4i-a10-system-control"; + reg = <0x01c00000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + sram_c: sram@1d00000 { + compatible = "mmio-sram"; + reg = <0x01d00000 0xd0000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x01d00000 0xd0000>; + + ve_sram: sram-section@0 { + compatible = "allwinner,sun8i-r40-sram-c1", + "allwinner,sun4i-a10-sram-c1"; + reg = <0x000000 0x80000>; + }; + }; + }; + nmi_intc: interrupt-controller@1c00030 { compatible = "allwinner,sun7i-a20-sc-nmi"; interrupt-controller; @@ -180,6 +240,69 @@ interrupts = ; }; + dma: dma-controller@1c02000 { + compatible = "allwinner,sun8i-r40-dma", + "allwinner,sun50i-a64-dma"; + reg = <0x01c02000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>; + dma-channels = <16>; + dma-requests = <31>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + + spi0: spi@1c05000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c05000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@1c06000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c06000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + csi0: csi@1c09000 { + compatible = "allwinner,sun8i-r40-csi0", + "allwinner,sun7i-a20-csi0"; + reg = <0x01c09000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI0>; + clock-names = "bus", "isp", "ram"; + resets = <&ccu RST_BUS_CSI0>; + interconnects = <&mbus 5>; + interconnect-names = "dma-mem"; + status = "disabled"; + }; + + video-codec@1c0e000 { + compatible = "allwinner,sun8i-r40-video-engine"; + reg = <0x01c0e000 0x1000>; + clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, + <&ccu CLK_DRAM_VE>; + clock-names = "ahb", "mod", "ram"; + resets = <&ccu RST_BUS_VE>; + interrupts = ; + allwinner,sram = <&ve_sram 1>; + }; + mmc0: mmc@1c0f000 { compatible = "allwinner,sun8i-r40-mmc", "allwinner,sun50i-a64-mmc"; @@ -266,6 +389,38 @@ #phy-cells = <1>; }; + crypto: crypto@1c15000 { + compatible = "allwinner,sun8i-r40-crypto"; + reg = <0x01c15000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_CE>; + }; + + spi2: spi@1c17000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c17000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI2>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + ahci: sata@1c18000 { + compatible = "allwinner,sun8i-r40-ahci"; + reg = <0x01c18000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; + resets = <&ccu RST_BUS_SATA>; + reset-names = "ahci"; + status = "disabled"; + }; + ehci1: usb@1c19000 { compatible = "allwinner,sun8i-r40-ehci", "generic-ehci"; reg = <0x01c19000 0x100>; @@ -312,6 +467,19 @@ status = "disabled"; }; + spi3: spi@1c1f000 { + compatible = "allwinner,sun8i-r40-spi", + "allwinner,sun8i-h3-spi"; + reg = <0x01c1f000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>; + clock-names = "ahb", "mod"; + resets = <&ccu RST_BUS_SPI3>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ccu: clock@1c20000 { compatible = "allwinner,sun8i-r40-ccu"; reg = <0x01c20000 0x400>; @@ -322,8 +490,7 @@ }; rtc: rtc@1c20400 { - compatible = "allwinner,sun8i-r40-rtc", - "allwinner,sun8i-h3-rtc"; + compatible = "allwinner,sun8i-r40-rtc"; reg = <0x01c20400 0x400>; interrupts = ; clock-output-names = "osc32k", "osc32k-out"; @@ -347,6 +514,20 @@ function = "clk_out_a"; }; + /omit-if-no-ref/ + csi0_8bits_pins: csi0-8bits-pins { + pins = "PE0", "PE2", "PE3", "PE4", "PE5", + "PE6", "PE7", "PE8", "PE9", "PE10", + "PE11"; + function = "csi0"; + }; + + /omit-if-no-ref/ + csi0_mclk_pin: csi0-mclk-pin { + pins = "PE1"; + function = "csi0"; + }; + gmac_rgmii_pins: gmac-rgmii-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", @@ -365,6 +546,36 @@ function = "i2c0"; }; + i2c1_pins: i2c1-pins { + pins = "PB18", "PB19"; + function = "i2c1"; + }; + + i2c2_pins: i2c2-pins { + pins = "PB20", "PB21"; + function = "i2c2"; + }; + + i2c3_pins: i2c3-pins { + pins = "PI0", "PI1"; + function = "i2c3"; + }; + + i2c4_pins: i2c4-pins { + pins = "PI2", "PI3"; + function = "i2c4"; + }; + + ir0_pins: ir0-pins { + pins = "PB4"; + function = "ir0"; + }; + + ir1_pins: ir1-pins { + pins = "PB23"; + function = "ir1"; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -390,6 +601,36 @@ bias-pull-up; }; + /omit-if-no-ref/ + spi0_pc_pins: spi0-pc-pins { + pins = "PC0", "PC1", "PC2"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi0_cs0_pc_pin: spi0-cs0-pc-pin { + pins = "PC23"; + function = "spi0"; + }; + + /omit-if-no-ref/ + spi1_pi_pins: spi1-pi-pins { + pins = "PI17", "PI18", "PI19"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs0_pi_pin: spi1-cs0-pi-pin { + pins = "PI16"; + function = "spi1"; + }; + + /omit-if-no-ref/ + spi1_cs1_pi_pin: spi1-cs1-pi-pin { + pins = "PI15"; + function = "spi1"; + }; + uart0_pb_pins: uart0-pb-pins { pins = "PB22", "PB23"; function = "uart0"; @@ -409,6 +650,45 @@ wdt: watchdog@1c20c90 { compatible = "allwinner,sun4i-a10-wdt"; reg = <0x01c20c90 0x10>; + interrupts = ; + clocks = <&osc24M>; + }; + + ir0: ir@1c21800 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21800 0x400>; + pinctrl-0 = <&ir0_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR0>, <&ccu CLK_IR0>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR0>; + status = "disabled"; + }; + + ir1: ir@1c21c00 { + compatible = "allwinner,sun8i-r40-ir", + "allwinner,sun6i-a31-ir"; + reg = <0x01c21c00 0x400>; + pinctrl-0 = <&ir1_pins>; + pinctrl-names = "default"; + clocks = <&ccu CLK_BUS_IR1>, <&ccu CLK_IR1>; + clock-names = "apb", "ir"; + interrupts = ; + resets = <&ccu RST_BUS_IR1>; + status = "disabled"; + }; + + ths: thermal-sensor@1c24c00 { + compatible = "allwinner,sun8i-r40-ths"; + reg = <0x01c24c00 0x100>; + clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; + clock-names = "bus", "mod"; + interrupts = ; + resets = <&ccu RST_BUS_THS>; + /* TODO: add nvmem-cells for calibration */ + #thermal-sensor-cells = <1>; }; uart0: serial@1c28000 { @@ -518,6 +798,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C1>; resets = <&ccu RST_BUS_I2C1>; + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -529,6 +811,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C2>; resets = <&ccu RST_BUS_I2C2>; + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -540,6 +824,8 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C3>; resets = <&ccu RST_BUS_I2C3>; + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -551,22 +837,33 @@ interrupts = ; clocks = <&ccu CLK_BUS_I2C4>; resets = <&ccu RST_BUS_I2C4>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; status = "disabled"; #address-cells = <1>; #size-cells = <0>; }; - ahci: sata@1c18000 { - compatible = "allwinner,sun8i-r40-ahci"; - reg = <0x01c18000 0x1000>; - interrupts = ; - clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>; - resets = <&ccu RST_BUS_SATA>; - resets-name = "ahci"; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - + mali: gpu@1c40000 { + compatible = "allwinner,sun8i-r40-mali", "arm,mali-400"; + reg = <0x01c40000 0x10000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pmu"; + clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; + clock-names = "bus", "core"; + resets = <&ccu RST_BUS_GPU>; }; gmac: ethernet@1c50000 { @@ -588,6 +885,16 @@ }; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun8i-r40-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu 155>; + #address-cells = <1>; + #size-cells = <1>; + dma-ranges = <0x00000000 0x40000000 0x80000000>; + #interconnect-cells = <1>; + }; + tcon_top: tcon-top@1c70000 { compatible = "allwinner,sun8i-r40-tcon-top"; reg = <0x01c70000 0x1000>; @@ -614,12 +921,9 @@ #size-cells = <0>; tcon_top_mixer0_in: port@0 { - #address-cells = <1>; - #size-cells = <0>; reg = <0>; - tcon_top_mixer0_in_mixer0: endpoint@0 { - reg = <0>; + tcon_top_mixer0_in_mixer0: endpoint { remote-endpoint = <&mixer0_out_tcon_top>; }; }; @@ -713,7 +1017,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c73000 0x1000>; interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>; + clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top CLK_TCON_TOP_TV0>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV0>; reset-names = "lcd"; @@ -756,7 +1060,7 @@ compatible = "allwinner,sun8i-r40-tcon-tv"; reg = <0x01c74000 0x1000>; interrupts = ; - clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top 1>; + clocks = <&ccu CLK_BUS_TCON_TV1>, <&tcon_top CLK_TCON_TOP_TV1>; clock-names = "ahb", "tcon-ch1"; resets = <&ccu RST_BUS_TCON_TV1>; reset-names = "lcd"; @@ -798,7 +1102,7 @@ gic: interrupt-controller@1c81000 { compatible = "arm,gic-400"; reg = <0x01c81000 0x1000>, - <0x01c82000 0x1000>, + <0x01c82000 0x2000>, <0x01c84000 0x2000>, <0x01c86000 0x2000>; interrupt-controller; @@ -818,7 +1122,7 @@ resets = <&ccu RST_BUS_HDMI1>; reset-names = "ctrl"; phys = <&hdmi_phy>; - phy-names = "hdmi-phy"; + phy-names = "phy"; status = "disabled"; ports { @@ -843,7 +1147,7 @@ compatible = "allwinner,sun8i-r40-hdmi-phy"; reg = <0x01ef0000 0x10000>; clocks = <&ccu CLK_BUS_HDMI1>, <&ccu CLK_HDMI_SLOW>, - <&ccu 7>, <&ccu 16>; + <&ccu CLK_PLL_VIDEO0>, <&ccu CLK_PLL_VIDEO1>; clock-names = "bus", "mod", "pll-0", "pll-1"; resets = <&ccu RST_BUS_HDMI0>; reset-names = "phy"; @@ -851,6 +1155,15 @@ }; }; + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + timer { compatible = "arm,armv7-timer"; interrupts = , diff --git a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts index 15c22b06fc4..47954551f57 100644 --- a/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts +++ b/arch/arm/dts/sun8i-v40-bananapi-m2-berry.dts @@ -120,7 +120,7 @@ pinctrl-names = "default"; pinctrl-0 = <&gmac_rgmii_pins>; phy-handle = <&phy1>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; phy-supply = <®_dc1sw>; status = "okay"; }; @@ -198,16 +198,16 @@ }; ®_dc1sw { - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-name = "vcc-gmac-phy"; }; ®_dcdc1 { regulator-always-on; - regulator-min-microvolt = <3000000>; - regulator-max-microvolt = <3000000>; - regulator-name = "vcc-3v0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; }; ®_dcdc2 { diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h index 4fa5f69fc29..d7337b55a4e 100644 --- a/include/dt-bindings/clock/sun8i-r40-ccu.h +++ b/include/dt-bindings/clock/sun8i-r40-ccu.h @@ -43,6 +43,10 @@ #ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_ #define _DT_BINDINGS_CLK_SUN8I_R40_H_ +#define CLK_PLL_VIDEO0 7 + +#define CLK_PLL_VIDEO1 16 + #define CLK_CPU 24 #define CLK_BUS_MIPI_DSI 29 @@ -172,7 +176,7 @@ #define CLK_AVS 152 #define CLK_HDMI 153 #define CLK_HDMI_SLOW 154 - +#define CLK_MBUS 155 #define CLK_DSI_DPHY 156 #define CLK_TVE0 157 #define CLK_TVE1 158 diff --git a/include/dt-bindings/interrupt-controller/arm-gic.h b/include/dt-bindings/interrupt-controller/arm-gic.h index 1ea1b702fec..35b6f69b7db 100644 --- a/include/dt-bindings/interrupt-controller/arm-gic.h +++ b/include/dt-bindings/interrupt-controller/arm-gic.h @@ -1,3 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ /* * This header provides constants for the ARM GIC. */ @@ -7,14 +8,14 @@ #include -/* interrupt specific cell 0 */ +/* interrupt specifier cell 0 */ #define GIC_SPI 0 #define GIC_PPI 1 /* * Interrupt specifier cell 2. - * The flaggs in irq.h are valid, plus those below. + * The flags in irq.h are valid, plus those below. */ #define GIC_CPU_MASK_RAW(x) ((x) << 8) #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) diff --git a/include/dt-bindings/thermal/thermal.h b/include/dt-bindings/thermal/thermal.h index b5e6b0069ac..bc7babb1a67 100644 --- a/include/dt-bindings/thermal/thermal.h +++ b/include/dt-bindings/thermal/thermal.h @@ -1,10 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ /* * This header provides constants for most thermal bindings. * * Copyright (C) 2013 Texas Instruments * Eduardo Valentin - * - * GPLv2 only */ #ifndef _DT_BINDINGS_THERMAL_THERMAL_H -- cgit v1.3.1 From ee0a7760fde78ed6c6c266e1e75f3eb745a7d086 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 4 Apr 2021 01:10:15 +0200 Subject: ARM: rmobile: Enable CONFIG_SYS_FLASH_PROTECTION Enable CONFIG_SYS_FLASH_PROTECTION on Salvator-X(S), ULCB, Ebisu, which means the Spansion HF PPB protection bits can be operated using the 'protect' U-Boot command. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/r8a77990_ebisu_defconfig | 3 +++ configs/rcar3_salvator-x_defconfig | 3 +++ configs/rcar3_ulcb_defconfig | 3 +++ include/configs/ebisu.h | 2 -- include/configs/salvator-x.h | 2 -- include/configs/ulcb.h | 2 -- 6 files changed, 9 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index cb75b5c3a60..d5797378b01 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -58,7 +58,10 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y CONFIG_RENESAS_RPC_HF=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 6109a23a319..cd250e93d34 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -60,7 +60,10 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y +CONFIG_FLASH_CFI_MTD=y +CONFIG_SYS_FLASH_PROTECTION=y CONFIG_RENESAS_RPC_HF=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index df202a75983..e345086f304 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -60,9 +60,12 @@ CONFIG_RENESAS_SDHI=y CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y +CONFIG_FLASH_CFI_DRIVER=y CONFIG_CFI_FLASH=y CONFIG_RENESAS_RPC_HF=y +CONFIG_FLASH_CFI_MTD=y CONFIG_DM_SPI_FLASH=y +CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index ee9ddb13362..19ec74fb588 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -23,8 +23,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_MTD #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index db06fa5ffd6..1eafff10ff3 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -20,8 +20,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_MTD #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 165c82d508e..1ce844f4920 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -20,8 +20,6 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_FLASH_CFI_MTD #define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -- cgit v1.3.1 From fec8c900c8b2a08661f6ac3e1e71d6af6aaa67cd Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Mon, 29 May 2017 15:59:38 +0300 Subject: power: regulator: Add support for regulator-force-boot-off Add support for regulator-force-boot-off DT property. This property can be used by the board/device drivers for turning off regulators on early init stages as pre-requisite for the other components initialization. Signed-off-by: Konstantin Porotchkin Signed-off-by: Stefan Roese Cc: Jaehoon Chung Cc: Simon Glass Reviewed-by: Jaehoon Chung --- drivers/power/regulator/regulator-uclass.c | 38 ++++++++++++++++++++++++++++++ include/power/regulator.h | 23 ++++++++++++++++++ 2 files changed, 61 insertions(+) (limited to 'include') diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index 4d2e730271f..fac96068233 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -311,6 +311,17 @@ int regulator_autoset(struct udevice *dev) return ret; } +int regulator_unset(struct udevice *dev) +{ + struct dm_regulator_uclass_plat *uc_pdata; + + uc_pdata = dev_get_uclass_plat(dev); + if (uc_pdata && uc_pdata->force_off) + return regulator_set_enable(dev, false); + + return -EMEDIUMTYPE; +} + static void regulator_show(struct udevice *dev, int ret) { struct dm_regulator_uclass_plat *uc_pdata; @@ -443,6 +454,7 @@ static int regulator_pre_probe(struct udevice *dev) uc_pdata->boot_on = dev_read_bool(dev, "regulator-boot-on"); uc_pdata->ramp_delay = dev_read_u32_default(dev, "regulator-ramp-delay", 0); + uc_pdata->force_off = dev_read_bool(dev, "regulator-force-boot-off"); node = dev_read_subnode(dev, "regulator-state-mem"); if (ofnode_valid(node)) { @@ -495,6 +507,32 @@ int regulators_enable_boot_on(bool verbose) return ret; } +int regulators_enable_boot_off(bool verbose) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + ret = uclass_get(UCLASS_REGULATOR, &uc); + if (ret) + return ret; + for (uclass_first_device(UCLASS_REGULATOR, &dev); + dev; + uclass_next_device(&dev)) { + ret = regulator_unset(dev); + if (ret == -EMEDIUMTYPE) { + ret = 0; + continue; + } + if (verbose) + regulator_show(dev, ret); + if (ret == -ENOSYS) + ret = 0; + } + + return ret; +} + UCLASS_DRIVER(regulator) = { .id = UCLASS_REGULATOR, .name = "regulator", diff --git a/include/power/regulator.h b/include/power/regulator.h index da9a065bdde..fad87c99e5d 100644 --- a/include/power/regulator.h +++ b/include/power/regulator.h @@ -151,6 +151,7 @@ enum regulator_flag { * @max_uA* - maximum amperage (micro Amps) * @always_on* - bool type, true or false * @boot_on* - bool type, true or false + * @force_off* - bool type, true or false * TODO(sjg@chromium.org): Consider putting the above two into @flags * @ramp_delay - Time to settle down after voltage change (unit: uV/us) * @flags: - flags value (see REGULATOR_FLAG_...) @@ -176,6 +177,7 @@ struct dm_regulator_uclass_plat { unsigned int ramp_delay; bool always_on; bool boot_on; + bool force_off; const char *name; int flags; u8 ctrl_reg; @@ -420,6 +422,15 @@ int regulator_set_mode(struct udevice *dev, int mode_id); */ int regulators_enable_boot_on(bool verbose); +/** + * regulators_enable_boot_off() - disable regulators needed for boot + * + * This disables all regulators which are marked to be off at boot time. + * + * This effectively calls regulator_unset() for every regulator. + */ +int regulators_enable_boot_off(bool verbose); + /** * regulator_autoset: setup the voltage/current on a regulator * @@ -439,6 +450,18 @@ int regulators_enable_boot_on(bool verbose); */ int regulator_autoset(struct udevice *dev); +/** + * regulator_unset: turn off a regulator + * + * The setup depends on constraints found in device's uclass's platform data + * (struct dm_regulator_uclass_platdata): + * + * - Disable - will set - if 'force_off' is set to true, + * + * The function returns on the first-encountered error. + */ +int regulator_unset(struct udevice *dev); + /** * regulator_autoset_by_name: setup the regulator given by its uclass's * platform data name field. The setup depends on constraints found in device's -- cgit v1.3.1 From 4568e2041c9fb6288f841bfb63474aecc1560af9 Mon Sep 17 00:00:00 2001 From: jinghua Date: Mon, 24 Apr 2017 15:51:03 +0800 Subject: phy: marvell: add comphy type PHY_TYPE_USB3 - For some Marvell SoCs, like armada-3700, there are both USB host and device controller, but on PHY level the configuration is the same. - The new type supports both USB device and USB host - This patch is cherry-picked from u-boot-2015 as-is. Change-Id: I01262027edd8ec23391cff6fb409b3009aedfbb9 Signed-off-by: jinghua Signed-off-by: Ken Ma Reviewed-by: Igal Liberman --- drivers/phy/marvell/comphy_core.c | 2 +- include/dt-bindings/comphy/comphy_data.h | 25 +++++++++++++------------ 2 files changed, 14 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cd54e7f8890..cffceb1395b 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -40,7 +40,7 @@ static const char *get_type_string(u32 type) static const char * const type_strings[] = { "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", - "SGMII1", "SGMII2", "SGMII3", "QSGMII", + "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3" "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", "XAUI0", "XAUI1", "XAUI2", "XAUI3", "RXAUI0", "RXAUI1", "SFI", "IGNORE" diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 4f7e2821b8e..08544fa758b 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -33,18 +33,19 @@ #define PHY_TYPE_SGMII2 11 #define PHY_TYPE_SGMII3 12 #define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3_HOST0 14 -#define PHY_TYPE_USB3_HOST1 15 -#define PHY_TYPE_USB3_DEVICE 16 -#define PHY_TYPE_XAUI0 17 -#define PHY_TYPE_XAUI1 18 -#define PHY_TYPE_XAUI2 19 -#define PHY_TYPE_XAUI3 20 -#define PHY_TYPE_RXAUI0 21 -#define PHY_TYPE_RXAUI1 22 -#define PHY_TYPE_SFI 23 -#define PHY_TYPE_IGNORE 24 -#define PHY_TYPE_MAX 25 +#define PHY_TYPE_USB3 14 +#define PHY_TYPE_USB3_HOST0 15 +#define PHY_TYPE_USB3_HOST1 16 +#define PHY_TYPE_USB3_DEVICE 17 +#define PHY_TYPE_XAUI0 18 +#define PHY_TYPE_XAUI1 19 +#define PHY_TYPE_XAUI2 20 +#define PHY_TYPE_XAUI3 21 +#define PHY_TYPE_RXAUI0 22 +#define PHY_TYPE_RXAUI1 23 +#define PHY_TYPE_SFI 24 +#define PHY_TYPE_IGNORE 25 +#define PHY_TYPE_MAX 26 #define PHY_TYPE_INVALID 0xff #define PHY_POLARITY_NO_INVERT 0 -- cgit v1.3.1 From 2dbba24088b8ef06aabee5df17ff7105ff259aca Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Wed, 26 Apr 2017 15:40:00 +0300 Subject: phy: marvell: rename comphy related definitions to COMPHY_XX Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman Signed-off-by: Konstantin Porotchkin --- arch/arm/dts/armada-3720-db.dts | 8 +- arch/arm/dts/armada-3720-espressobin.dts | 12 +-- arch/arm/dts/armada-3720-turris-mox.dts | 12 +-- arch/arm/dts/armada-3720-uDPU.dts | 23 +++--- arch/arm/dts/armada-7040-db-nand.dts | 24 +++--- arch/arm/dts/armada-7040-db.dts | 22 ++--- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 30 +++---- arch/arm/dts/armada-8040-db.dts | 24 +++--- arch/arm/dts/armada-8040-mcbin.dts | 27 +++--- arch/arm/dts/armada-8040-puzzle-m801.dts | 32 +++---- arch/arm/dts/cn9130-crb-A.dts | 16 ++-- arch/arm/dts/cn9130-crb-B.dts | 16 ++-- board/CZ.NIC/turris_mox/turris_mox.c | 8 +- drivers/phy/marvell/comphy_a3700.c | 70 ++++++++-------- drivers/phy/marvell/comphy_core.c | 14 ++-- drivers/phy/marvell/comphy_cp110.c | 124 +++++++++++++++------------- drivers/phy/marvell/comphy_mux.c | 10 +-- include/dt-bindings/comphy/comphy_data.h | 90 ++++++++++---------- 18 files changed, 288 insertions(+), 274 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 1b1b66b94de..42e7ddd25c5 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -70,13 +70,13 @@ &comphy { phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-3720-espressobin.dts b/arch/arm/dts/armada-3720-espressobin.dts index 96a4b3d95b8..d86d8f0b63c 100644 --- a/arch/arm/dts/armada-3720-espressobin.dts +++ b/arch/arm/dts/armada-3720-espressobin.dts @@ -83,18 +83,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy2 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-3720-turris-mox.dts b/arch/arm/dts/armada-3720-turris-mox.dts index 974270cc8c6..8e0ebf508d4 100644 --- a/arch/arm/dts/armada-3720-turris-mox.dts +++ b/arch/arm/dts/armada-3720-turris-mox.dts @@ -73,18 +73,18 @@ &comphy { max-lanes = <3>; phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy2 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-3720-uDPU.dts b/arch/arm/dts/armada-3720-uDPU.dts index 7f4b8222f4a..4b30f3cea8c 100644 --- a/arch/arm/dts/armada-3720-uDPU.dts +++ b/arch/arm/dts/armada-3720-uDPU.dts @@ -108,18 +108,19 @@ &comphy { phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; + }; + + phy1 { + phy-type = ; + phy-speed = ; + }; + + phy2 { + phy-type = ; + phy-speed = ; }; - phy1 { - phy-type = ; - phy-speed = ; - }; - - phy2 { - phy-type = ; - phy-speed = ; - }; }; ð0 { diff --git a/arch/arm/dts/armada-7040-db-nand.dts b/arch/arm/dts/armada-7040-db-nand.dts index f249c71f656..ccf470b317f 100644 --- a/arch/arm/dts/armada-7040-db-nand.dts +++ b/arch/arm/dts/armada-7040-db-nand.dts @@ -129,33 +129,33 @@ &cp0_comphy { phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy2 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy3 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy4 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index 6037f12f0e9..f475fb36107 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -122,32 +122,32 @@ &cp0_comphy { phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy4 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index 86df6ac0b20..ce5832c2fbd 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -160,22 +160,22 @@ * Lane 5: Not connected */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; }; }; @@ -272,25 +272,25 @@ * Lane 5: SGMII2 - Connected to Topaz switch */ phy0 { - phy-type = ; - phy-invert = ; + phy-type = ; + phy-invert = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index a2b7c992a40..1edfaab682e 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -89,22 +89,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; }; }; @@ -188,22 +188,22 @@ * Lane 5: PCIe2 (x1) */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; }; }; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index b0a36e328bc..98a582df26f 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -171,22 +171,22 @@ * Lane 5: SATA1 */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; }; }; @@ -286,22 +286,23 @@ * Lane 5: SGMII3 */ phy0 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index ff46ce50cbc..0becc4ff0d3 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -220,24 +220,24 @@ * Lane 5: SATA1 */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; }; }; @@ -367,23 +367,23 @@ * Lane 5: SGMII2 */ phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index fa21ef314cb..5c5e0fb2eb1 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -15,29 +15,29 @@ &cp0_comphy { phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 7cb587ada82..6041084a2c8 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -15,29 +15,29 @@ &cp0_comphy { phy0 { - phy-type = ; + phy-type = ; }; phy1 { - phy-type = ; + phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { - phy-type = ; + phy-type = ; }; phy4 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; phy5 { - phy-type = ; - phy-speed = ; + phy-type = ; + phy-speed = ; }; }; diff --git a/board/CZ.NIC/turris_mox/turris_mox.c b/board/CZ.NIC/turris_mox/turris_mox.c index 486680a49e8..15cbf92550e 100644 --- a/board/CZ.NIC/turris_mox/turris_mox.c +++ b/board/CZ.NIC/turris_mox/turris_mox.c @@ -216,13 +216,13 @@ int comphy_update_map(struct comphy_map *serdes_map, int count) if (sfpindex >= 0 && swindex >= 0) { if (sfpindex < swindex) - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; else - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } else if (sfpindex >= 0) { - serdes_map[0].speed = PHY_SPEED_1_25G; + serdes_map[0].speed = COMPHY_SPEED_1_25G; } else if (swindex >= 0) { - serdes_map[0].speed = PHY_SPEED_3_125G; + serdes_map[0].speed = COMPHY_SPEED_3_125G; } return 0; diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c index 12523d18a80..06822d1d12e 100644 --- a/drivers/phy/marvell/comphy_a3700.c +++ b/drivers/phy/marvell/comphy_a3700.c @@ -17,33 +17,33 @@ DECLARE_GLOBAL_DATA_PTR; struct comphy_mux_data a3700_comphy_mux_data[] = { -/* Lane 0 */ + /* Lane 0 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0 }, - { PHY_TYPE_SGMII1, 0x0 }, - { PHY_TYPE_USB3_HOST0, 0x1 }, - { PHY_TYPE_USB3_DEVICE, 0x1 } + { COMPHY_TYPE_UNCONNECTED, 0x0 }, + { COMPHY_TYPE_SGMII1, 0x0 }, + { COMPHY_TYPE_USB3_HOST0, 0x1 }, + { COMPHY_TYPE_USB3_DEVICE, 0x1 } } }, -/* Lane 1 */ + /* Lane 1 */ { 3, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SGMII0, 0x0}, - { PHY_TYPE_PEX0, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SGMII0, 0x0}, + { COMPHY_TYPE_PEX0, 0x1} } }, -/* Lane 2 */ + /* Lane 2 */ { 4, { - { PHY_TYPE_UNCONNECTED, 0x0}, - { PHY_TYPE_SATA0, 0x0}, - { PHY_TYPE_USB3_HOST0, 0x1}, - { PHY_TYPE_USB3_DEVICE, 0x1} + { COMPHY_TYPE_UNCONNECTED, 0x0}, + { COMPHY_TYPE_SATA0, 0x0}, + { COMPHY_TYPE_USB3_HOST0, 0x1}, + { COMPHY_TYPE_USB3_DEVICE, 0x1} } }, }; @@ -228,10 +228,10 @@ static int comphy_pcie_power_up(u32 speed, u32 invert) /* * 10. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -284,10 +284,10 @@ static int comphy_sata_power_up(u32 invert) /* * 0. Check the Polarity invert bits */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) data |= bs_txd_inv; - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) data |= bs_rxd_inv; reg_set_indirect(vphy_sync_pattern_reg, data, bs_txd_inv | bs_rxd_inv); @@ -465,10 +465,10 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) /* * 9. Check the Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane); /* @@ -513,7 +513,7 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) * Set Soft ID for Host mode (Device mode works with Hard ID * detection) */ - if (type == PHY_TYPE_USB3_HOST0) { + if (type == COMPHY_TYPE_USB3_HOST0) { /* * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1) * clear BIT1: set SOFT_ID = Host @@ -685,8 +685,8 @@ static void comphy_sgmii_phy_init(u32 lane, u32 speed) * comparison to 3.125 Gbps values. These register values are * stored in "sgmii_phy_init_fix" array. */ - if ((speed != PHY_SPEED_1_25G) && - (sgmii_phy_init_fix[fix_idx].addr == addr)) { + if (speed != COMPHY_SPEED_1_25G && + sgmii_phy_init_fix[fix_idx].addr == addr) { /* Use new value */ val = sgmii_phy_init_fix[fix_idx].value; if (fix_idx < fix_arr_sz) @@ -737,13 +737,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide * COMPHY bit rate */ - if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */ + if (speed == COMPHY_SPEED_3_125G) { /* 3.125 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x8 << rf_gen_rx_sel_shift) | (0x8 << rf_gen_tx_sel_shift), rf_gen_rx_select | rf_gen_tx_select); - } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */ + } else if (speed == COMPHY_SPEED_1_25G) { /* 1.25 GHz */ reg_set(COMPHY_PHY_CFG1_ADDR(lane), (0x6 << rf_gen_rx_sel_shift) | (0x6 << rf_gen_tx_sel_shift), @@ -819,7 +819,7 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) * registers are OK. */ debug("Running C-DPI phy init %s mode\n", - speed == PHY_SPEED_3_125G ? "2G5" : "1G"); + speed == COMPHY_SPEED_3_125G ? "2G5" : "1G"); if (get_ref_clk() == 40) comphy_sgmii_phy_init(lane, speed); @@ -837,10 +837,10 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert) /* * 18. Check the PHY Polarity invert bit */ - if (invert & PHY_POLARITY_TXD_INVERT) + if (invert & COMPHY_POLARITY_TXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0); - if (invert & PHY_POLARITY_RXD_INVERT) + if (invert & COMPHY_POLARITY_RXD_INVERT) reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0); /* @@ -976,30 +976,30 @@ int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg, comphy_map->type, comphy_map->invert); switch (comphy_map->type) { - case PHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_UNCONNECTED: continue; break; - case PHY_TYPE_PEX0: + case COMPHY_TYPE_PEX0: ret = comphy_pcie_power_up(comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, comphy_map->type, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: ret = comphy_sgmii_power_up(lane, comphy_map->speed, comphy_map->invert); break; - case PHY_TYPE_SATA0: + case COMPHY_TYPE_SATA0: ret = comphy_sata_power_up(comphy_map->invert); break; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index cffceb1395b..f1f061d7c11 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -29,7 +29,7 @@ static const char *get_speed_string(u32 speed) "6.25 Gbps", "10.31 Gbps" }; - if (speed < 0 || speed > PHY_SPEED_MAX) + if (speed < 0 || speed > COMPHY_SPEED_MAX) return "invalid"; return speed_strings[speed]; @@ -46,7 +46,7 @@ static const char *get_type_string(u32 type) "RXAUI0", "RXAUI1", "SFI", "IGNORE" }; - if (type < 0 || type > PHY_TYPE_MAX) + if (type < 0 || type > COMPHY_TYPE_MAX) return "invalid"; return type_strings[type]; @@ -59,7 +59,7 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, for (lane = 0; lane < chip_cfg->comphy_lanes_count; lane++, comphy_map_data++) { - if (comphy_map_data->speed == PHY_SPEED_INVALID) { + if (comphy_map_data->speed == COMPHY_SPEED_INVALID) { printf("Comphy-%d: %-13s\n", lane, get_type_string(comphy_map_data->type)); } else { @@ -136,16 +136,16 @@ static int comphy_probe(struct udevice *dev) continue; comphy_map_data[lane].speed = fdtdec_get_int( - blob, subnode, "phy-speed", PHY_TYPE_INVALID); + blob, subnode, "phy-speed", COMPHY_TYPE_INVALID); comphy_map_data[lane].type = fdtdec_get_int( - blob, subnode, "phy-type", PHY_SPEED_INVALID); + blob, subnode, "phy-type", COMPHY_SPEED_INVALID); comphy_map_data[lane].invert = fdtdec_get_int( - blob, subnode, "phy-invert", PHY_POLARITY_NO_INVERT); + blob, subnode, "phy-invert", COMPHY_POLARITY_NO_INVERT); comphy_map_data[lane].clk_src = fdtdec_get_bool(blob, subnode, "clk-src"); comphy_map_data[lane].end_point = fdtdec_get_bool(blob, subnode, "end_point"); - if (comphy_map_data[lane].type == PHY_TYPE_INVALID) { + if (comphy_map_data[lane].type == COMPHY_TYPE_INVALID) { printf("no phy type for lane %d, setting lane as unconnected\n", lane + 1); } diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index a323de7c76d..e4ab90121c7 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -74,35 +74,47 @@ struct utmi_phy_data { * Eth_port_0 that include (SGMII0, RXAUI0, SFI) */ struct comphy_mux_data cp110_comphy_phy_mux_data[] = { - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, /* Lane 0 */ - {PHY_TYPE_SATA1, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 1 */ - {PHY_TYPE_SATA0, 0x4} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, /* Lane 2 */ - {PHY_TYPE_RXAUI0, 0x1}, {PHY_TYPE_SFI, 0x1}, - {PHY_TYPE_SATA0, 0x4} } }, - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, /* Lane 3 */ - {PHY_TYPE_SGMII1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, /* Lane 4 */ - {PHY_TYPE_RXAUI0, 0x2}, {PHY_TYPE_SFI, 0x2}, - {PHY_TYPE_SGMII1, 0x1} } }, - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, /* Lane 5 */ - {PHY_TYPE_RXAUI1, 0x2}, {PHY_TYPE_SATA1, 0x4} } }, + /* Lane 0 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, + {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 2 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, + {COMPHY_TYPE_RXAUI0, 0x1}, {COMPHY_TYPE_SFI, 0x1}, + {COMPHY_TYPE_SATA0, 0x4} } }, + /* Lane 3 */ + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, + {COMPHY_TYPE_SGMII1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, + /* Lane 4 */ + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, + {COMPHY_TYPE_RXAUI0, 0x2}, {COMPHY_TYPE_SFI, 0x2}, + {COMPHY_TYPE_SGMII1, 0x1} } }, + /* Lane 5 */ + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, + {COMPHY_TYPE_RXAUI1, 0x2}, {COMPHY_TYPE_SATA1, 0x4} } }, }; struct comphy_mux_data cp110_comphy_pipe_mux_data[] = { - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX0, 0x4} } }, /* Lane 0 */ - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 1 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_USB3_DEVICE, 0x2}, - {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 2 */ - {PHY_TYPE_USB3_HOST0, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 3 */ - {PHY_TYPE_USB3_HOST1, 0x1}, {PHY_TYPE_PEX0, 0x4} } }, - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, /* Lane 4 */ - {PHY_TYPE_USB3_HOST1, 0x1}, - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PEX1, 0x4} } }, - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PEX2, 0x4} } }, /* Lane 5 */ + /* Lane 0 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 1 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_USB3_DEVICE, 0x2}, + {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 2 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST0, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 3 */ + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, {COMPHY_TYPE_PEX0, 0x4} } }, + /* Lane 4 */ + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, + {COMPHY_TYPE_USB3_HOST1, 0x1}, + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PEX1, 0x4} } }, + /* Lane 5 */ + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PEX2, 0x4} } }, }; static u32 polling_with_timeout(void __iomem *addr, u32 val, @@ -868,9 +880,9 @@ static void comphy_mux_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, comphy_base_addr + COMMON_SELECTOR_PIPE_OFFSET); /* Fix the type after check the PHY and PIPE configuration */ for (lane = 0; lane < comphy_max_count; lane++) { - if ((comphy_map_pipe_data[lane].type == PHY_TYPE_UNCONNECTED) && - (comphy_map_phy_data[lane].type == PHY_TYPE_UNCONNECTED)) - serdes_map[lane].type = PHY_TYPE_UNCONNECTED; + if ((comphy_map_pipe_data[lane].type == COMPHY_TYPE_UNCONNECTED) && + (comphy_map_phy_data[lane].type == COMPHY_TYPE_UNCONNECTED)) + serdes_map[lane].type = COMPHY_TYPE_UNCONNECTED; } } @@ -895,7 +907,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, /* Check if the first 4 lanes configured as By-4 */ for (lane = 0, ptr_comphy_map = serdes_map; lane < 4; lane++, ptr_comphy_map++) { - if (ptr_comphy_map->type != PHY_TYPE_PEX0) + if (ptr_comphy_map->type != COMPHY_TYPE_PEX0) break; pcie_width++; } @@ -912,14 +924,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, pcie_width = 1; } switch (ptr_comphy_map->type) { - case PHY_TYPE_UNCONNECTED: - case PHY_TYPE_IGNORE: + case COMPHY_TYPE_UNCONNECTED: + case COMPHY_TYPE_IGNORE: continue; break; - case PHY_TYPE_PEX0: - case PHY_TYPE_PEX1: - case PHY_TYPE_PEX2: - case PHY_TYPE_PEX3: + case COMPHY_TYPE_PEX0: + case COMPHY_TYPE_PEX1: + case COMPHY_TYPE_PEX2: + case COMPHY_TYPE_PEX3: mode = COMPHY_FW_PCIE_FORMAT(pcie_width, ptr_comphy_map->clk_src, COMPHY_PCIE_MODE, @@ -928,30 +940,30 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SATA0: - case PHY_TYPE_SATA1: - case PHY_TYPE_SATA2: - case PHY_TYPE_SATA3: + case COMPHY_TYPE_SATA0: + case COMPHY_TYPE_SATA1: + case COMPHY_TYPE_SATA2: + case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, ptr_chip_cfg->cp_index, mode); break; - case PHY_TYPE_USB3_HOST0: - case PHY_TYPE_USB3_HOST1: - case PHY_TYPE_USB3_DEVICE: + case COMPHY_TYPE_USB3_HOST0: + case COMPHY_TYPE_USB3_HOST1: + case COMPHY_TYPE_USB3_DEVICE: ret = comphy_usb3_power_up(lane, hpipe_base_addr, comphy_base_addr); break; - case PHY_TYPE_SGMII0: - case PHY_TYPE_SGMII1: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII0: + case COMPHY_TYPE_SGMII1: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: "); debug("SGMII PHY speed in lane %d is invalid,", lane); debug(" set PHY speed to 1.25G\n"); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; } /* @@ -965,12 +977,12 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SGMII2: - case PHY_TYPE_SGMII3: - if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { + case COMPHY_TYPE_SGMII2: + case COMPHY_TYPE_SGMII3: + if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); - ptr_comphy_map->speed = PHY_SPEED_1_25G; + ptr_comphy_map->speed = COMPHY_SPEED_1_25G; } mode = COMPHY_FW_FORMAT(COMPHY_SGMII_MODE, @@ -980,7 +992,7 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_SFI: + case COMPHY_TYPE_SFI: mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, COMPHY_UNIT_ID0, ptr_comphy_map->speed); @@ -988,8 +1000,8 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case PHY_TYPE_RXAUI0: - case PHY_TYPE_RXAUI1: + case COMPHY_TYPE_RXAUI0: + case COMPHY_TYPE_RXAUI1: ret = comphy_rxauii_power_up(lane, hpipe_base_addr, comphy_base_addr); break; @@ -1001,9 +1013,9 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, if (ret == 0) { /* * If interface wans't initialized, set the lane to - * PHY_TYPE_UNCONNECTED state. + * COMPHY_TYPE_UNCONNECTED state. */ - ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; + ptr_comphy_map->type = COMPHY_TYPE_UNCONNECTED; pr_err("PLL is not locked - Failed to initialize lane %d\n", lane); } diff --git a/drivers/phy/marvell/comphy_mux.c b/drivers/phy/marvell/comphy_mux.c index 98327557a89..aaef736b75d 100644 --- a/drivers/phy/marvell/comphy_mux.c +++ b/drivers/phy/marvell/comphy_mux.c @@ -15,7 +15,7 @@ * description: this function passes over the COMPHY lanes and check if the type * is valid for specific lane. If the type is not valid, * the function update the struct and set the type of the lane as - * PHY_TYPE_UNCONNECTED + * COMPHY_TYPE_UNCONNECTED */ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, struct comphy_map *comphy_map_data, int comphy_max_lanes) @@ -28,7 +28,7 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { /* Don't check ignored COMPHYs */ - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; mux_opt = mux_data->mux_values; @@ -43,8 +43,8 @@ static void comphy_mux_check_config(struct comphy_mux_data *mux_data, debug("lane number %d, had invalid type %d\n", lane, comphy_map_data->type); debug("set lane %d as type %d\n", lane, - PHY_TYPE_UNCONNECTED); - comphy_map_data->type = PHY_TYPE_UNCONNECTED; + COMPHY_TYPE_UNCONNECTED); + comphy_map_data->type = COMPHY_TYPE_UNCONNECTED; } else { debug("lane number %d, has type %d\n", lane, comphy_map_data->type); @@ -88,7 +88,7 @@ static void comphy_mux_reg_write(struct comphy_mux_data *mux_data, for (lane = 0; lane < comphy_max_lanes; lane++, comphy_map_data++, mux_data++) { - if (comphy_map_data->type == PHY_TYPE_IGNORE) + if (comphy_map_data->type == COMPHY_TYPE_IGNORE) continue; /* diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 08544fa758b..7d62dcf7fa5 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -6,53 +6,53 @@ #ifndef _COMPHY_DATA_H_ #define _COMPHY_DATA_H_ -#define PHY_SPEED_1_25G 0 -#define PHY_SPEED_1_5G 1 -#define PHY_SPEED_2_5G 2 -#define PHY_SPEED_3G 3 -#define PHY_SPEED_3_125G 4 -#define PHY_SPEED_5G 5 -#define PHY_SPEED_5_15625G 6 -#define PHY_SPEED_6G 7 -#define PHY_SPEED_6_25G 8 -#define PHY_SPEED_10_3125G 9 -#define PHY_SPEED_MAX 10 -#define PHY_SPEED_INVALID 0xff +#define COMPHY_SPEED_1_25G 0 +#define COMPHY_SPEED_1_5G 1 +#define COMPHY_SPEED_2_5G 2 +#define COMPHY_SPEED_3G 3 +#define COMPHY_SPEED_3_125G 4 +#define COMPHY_SPEED_5G 5 +#define COMPHY_SPEED_5_15625G 6 +#define COMPHY_SPEED_6G 7 +#define COMPHY_SPEED_6_25G 8 +#define COMPHY_SPEED_10_3125G 9 +#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_INVALID 0xff -#define PHY_TYPE_UNCONNECTED 0 -#define PHY_TYPE_PEX0 1 -#define PHY_TYPE_PEX1 2 -#define PHY_TYPE_PEX2 3 -#define PHY_TYPE_PEX3 4 -#define PHY_TYPE_SATA0 5 -#define PHY_TYPE_SATA1 6 -#define PHY_TYPE_SATA2 7 -#define PHY_TYPE_SATA3 8 -#define PHY_TYPE_SGMII0 9 -#define PHY_TYPE_SGMII1 10 -#define PHY_TYPE_SGMII2 11 -#define PHY_TYPE_SGMII3 12 -#define PHY_TYPE_QSGMII 13 -#define PHY_TYPE_USB3 14 -#define PHY_TYPE_USB3_HOST0 15 -#define PHY_TYPE_USB3_HOST1 16 -#define PHY_TYPE_USB3_DEVICE 17 -#define PHY_TYPE_XAUI0 18 -#define PHY_TYPE_XAUI1 19 -#define PHY_TYPE_XAUI2 20 -#define PHY_TYPE_XAUI3 21 -#define PHY_TYPE_RXAUI0 22 -#define PHY_TYPE_RXAUI1 23 -#define PHY_TYPE_SFI 24 -#define PHY_TYPE_IGNORE 25 -#define PHY_TYPE_MAX 26 -#define PHY_TYPE_INVALID 0xff +#define COMPHY_TYPE_UNCONNECTED 0 +#define COMPHY_TYPE_PEX0 1 +#define COMPHY_TYPE_PEX1 2 +#define COMPHY_TYPE_PEX2 3 +#define COMPHY_TYPE_PEX3 4 +#define COMPHY_TYPE_SATA0 5 +#define COMPHY_TYPE_SATA1 6 +#define COMPHY_TYPE_SATA2 7 +#define COMPHY_TYPE_SATA3 8 +#define COMPHY_TYPE_SGMII0 9 +#define COMPHY_TYPE_SGMII1 10 +#define COMPHY_TYPE_SGMII2 11 +#define COMPHY_TYPE_SGMII3 12 +#define COMPHY_TYPE_QSGMII 13 +#define COMPHY_TYPE_USB3 14 +#define COMPHY_TYPE_USB3_HOST0 15 +#define COMPHY_TYPE_USB3_HOST1 16 +#define COMPHY_TYPE_USB3_DEVICE 17 +#define COMPHY_TYPE_XAUI0 18 +#define COMPHY_TYPE_XAUI1 19 +#define COMPHY_TYPE_XAUI2 20 +#define COMPHY_TYPE_XAUI3 21 +#define COMPHY_TYPE_RXAUI0 22 +#define COMPHY_TYPE_RXAUI1 23 +#define COMPHY_TYPE_SFI 24 +#define COMPHY_TYPE_IGNORE 25 +#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_INVALID 0xff -#define PHY_POLARITY_NO_INVERT 0 -#define PHY_POLARITY_TXD_INVERT 1 -#define PHY_POLARITY_RXD_INVERT 2 -#define PHY_POLARITY_ALL_INVERT \ - (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT) +#define COMPHY_POLARITY_NO_INVERT 0 +#define COMPHY_POLARITY_TXD_INVERT 1 +#define COMPHY_POLARITY_RXD_INVERT 2 +#define COMPHY_POLARITY_ALL_INVERT \ + (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT) #define UTMI_PHY_TO_USB3_HOST0 0 #define UTMI_PHY_TO_USB3_HOST1 1 -- cgit v1.3.1 From e49cdbe10b082980029b8e215842be4fbbd13f5f Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Tue, 23 Mar 2021 11:57:57 +0100 Subject: phy: marvell: add RX training command This patch adds support for running RX training using new command called "rx_training" Usage: rx_training - rx_training RX training allows to improve link quality (for SFI mode) by running training sequence between us and the link partner, this allows to reach better link quality then using static configuration. Change-Id: I818fe67ccaf19a87af50d4c34a9db7d6802049a5 Signed-off-by: Igal Liberman Signed-off-by: Marcin Wojtas --- cmd/mvebu/Kconfig | 7 ++ cmd/mvebu/Makefile | 2 +- cmd/mvebu/rx_training.c | 57 +++++++++++ configs/mvebu_db_armada8k_defconfig | 1 + drivers/phy/marvell/comphy_core.c | 18 +++- drivers/phy/marvell/comphy_core.h | 14 +++ drivers/phy/marvell/comphy_cp110.c | 190 ++++++++++++++++++++++++++++++++++++ drivers/phy/marvell/comphy_hpipe.h | 62 +++++++++++- include/mvebu/comphy.h | 2 +- 9 files changed, 348 insertions(+), 5 deletions(-) create mode 100644 cmd/mvebu/rx_training.c (limited to 'include') diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig index f1eb00614dd..f0e4f884d70 100644 --- a/cmd/mvebu/Kconfig +++ b/cmd/mvebu/Kconfig @@ -49,4 +49,11 @@ config MVEBU_UBOOT_DFLT_NAME This option should contain a default file name to be used with MVEBU "bubt" command if the source file name is omitted +config CMD_MVEBU_RX_TRAINING + bool "rx_training" + depends on TARGET_MVEBU_ARMADA_8K + default n + help + Perform RX training sequence + endmenu diff --git a/cmd/mvebu/Makefile b/cmd/mvebu/Makefile index 96829c48ebd..79299b0814f 100644 --- a/cmd/mvebu/Makefile +++ b/cmd/mvebu/Makefile @@ -4,5 +4,5 @@ # # https://spdx.org/licenses - obj-$(CONFIG_CMD_MVEBU_BUBT) += bubt.o +obj-$(CONFIG_CMD_MVEBU_RX_TRAINING) += rx_training.o diff --git a/cmd/mvebu/rx_training.c b/cmd/mvebu/rx_training.c new file mode 100644 index 00000000000..4bae7653aca --- /dev/null +++ b/cmd/mvebu/rx_training.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2017 Marvell International Ltd. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include + +int rx_training_cmd(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + struct udevice *dev; + struct uclass *uc; + int ret, cp_index, comphy_index, i = 0; + + if (argc != 3) { + printf("missing arguments\n"); + return -1; + } + + cp_index = simple_strtoul(argv[1], NULL, 16); + comphy_index = simple_strtoul(argv[2], NULL, 16); + + ret = uclass_get(UCLASS_MISC, &uc); + if (ret) { + printf("Couldn't find UCLASS_MISC\n"); + return ret; + } + + uclass_foreach_dev(dev, uc) { + if (!(memcmp(dev->name, "comphy", 5))) { + if (i == cp_index) { + comphy_rx_training(dev, comphy_index); + return 0; + } + + i++; + } + } + + printf("Coudn't find comphy %d\n", cp_index); + + return 0; +} + +U_BOOT_CMD( + rx_training, 3, 0, rx_training_cmd, + "rx_training \n", + "\n\tRun RX training sequence, the user must state CP index (0/1) and comphy ID (0/5)" +); diff --git a/configs/mvebu_db_armada8k_defconfig b/configs/mvebu_db_armada8k_defconfig index ffe8e029050..96baea76fc1 100644 --- a/configs/mvebu_db_armada8k_defconfig +++ b/configs/mvebu_db_armada8k_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_TFTPPUT=y CONFIG_CMD_CACHE=y CONFIG_CMD_TIME=y CONFIG_CMD_MVEBU_BUBT=y +CONFIG_CMD_MVEBU_RX_TRAINING=y CONFIG_CMD_EXT4_WRITE=y CONFIG_MAC_PARTITION=y CONFIG_ENV_OVERWRITE=y diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index d8df7ac949a..b29decd8269 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -71,6 +71,16 @@ void comphy_print(struct chip_serdes_phy_config *chip_cfg, } } +int comphy_rx_training(struct udevice *dev, u32 lane) +{ + struct chip_serdes_phy_config *chip_cfg = dev_get_priv(dev); + + if (chip_cfg->rx_training) + return chip_cfg->rx_training(chip_cfg, lane); + + return 0; +} + __weak int comphy_update_map(struct comphy_map *serdes_map, int count) { return 0; @@ -114,11 +124,15 @@ static int comphy_probe(struct udevice *dev) fdtdec_locate_array(blob, node, "mux-lane-order", chip_cfg->comphy_lanes_count); - if (device_is_compatible(dev, "marvell,comphy-armada-3700")) + if (device_is_compatible(dev, "marvell,comphy-armada-3700")) { chip_cfg->ptr_comphy_chip_init = comphy_a3700_init; + chip_cfg->rx_training = NULL; + } - if (device_is_compatible(dev, "marvell,comphy-cp110")) + if (device_is_compatible(dev, "marvell,comphy-cp110")) { chip_cfg->ptr_comphy_chip_init = comphy_cp110_init; + chip_cfg->rx_training = comphy_cp110_sfi_rx_training; + } /* * Bail out if no chip_init function is defined, e.g. no diff --git a/drivers/phy/marvell/comphy_core.h b/drivers/phy/marvell/comphy_core.h index c08677e56d2..32895dc4aa3 100644 --- a/drivers/phy/marvell/comphy_core.h +++ b/drivers/phy/marvell/comphy_core.h @@ -84,6 +84,7 @@ struct chip_serdes_phy_config { struct comphy_mux_data *mux_data; int (*ptr_comphy_chip_init)(struct chip_serdes_phy_config *, struct comphy_map *); + int (*rx_training)(struct chip_serdes_phy_config *, u32); void __iomem *comphy_base_addr; void __iomem *hpipe3_base_addr; u32 comphy_lanes_count; @@ -151,6 +152,8 @@ static inline int comphy_a3700_init(struct chip_serdes_phy_config *ptr_chip_cfg, #ifdef CONFIG_ARMADA_8K int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map); +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane); #else static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, struct comphy_map *serdes_map) @@ -161,6 +164,17 @@ static inline int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, */ return -1; } + +static inline int comphy_cp110_sfi_rx_training( + struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + /* + * This function should never be called in this configuration, so + * lets return an error here. + */ + return -1; +} #endif void comphy_dedicated_phys_init(void); diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 72563f8bc1c..11dc46b28a6 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -133,6 +133,196 @@ static u32 polling_with_timeout(void __iomem *addr, u32 val, return 0; } +/* This function performs RX training for single FFE value. + * The result of the RX training is located in: + * Saved DFE values Register[10:15]. + * + * The result is returned to the caller using *result + * + * Return '1' on succsess. + * Return '0' on failure. + */ +static int comphy_cp110_test_single_ffe( + struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane, u32 ffe, u32 *result) +{ + u32 mask, data, timeout; + void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; + void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane); + void __iomem *sd_ip_addr = SD_ADDR(hpipe_base_addr, lane); + + /* Configure PRBS counters */ + mask = HPIPE_PHY_TEST_PATTERN_SEL_MASK; + data = 0xe << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mask = HPIPE_PHY_TEST_DATA_MASK; + data = 0x64 << HPIPE_PHY_TEST_DATA_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_DATA_REG, data, mask); + + mask = HPIPE_PHY_TEST_EN_MASK; + data = 0x1 << HPIPE_PHY_TEST_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mdelay(50); + + /* Set the FFE value */ + mask = HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; + data = ffe << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* Start RX training */ + mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK; + data = 1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET; + reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask); + + /* Check the result of RX training */ + timeout = RX_TRAINING_TIMEOUT; + while (timeout) { + data = readl(sd_ip_addr + SD_EXTERNAL_STATUS1_REG); + if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK) + break; + mdelay(1); + timeout--; + } + + if (timeout == 0) + return 0; + + if (data & SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK) + return 0; + + /* Stop RX training */ + mask = SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK; + data = 0 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET; + reg_set(sd_ip_addr + SD_EXTERNAL_STATUS_REG, data, mask); + + /* Read the result */ + data = readl(hpipe_addr + HPIPE_SAVED_DFE_VALUES_REG); + data &= HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK; + data >>= HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET; + *result = data; + + printf("FFE = %d, result = 0x%x\n", ffe, *result); + + /* Clear the PRBS counters */ + mask = HPIPE_PHY_TEST_RESET_MASK; + data = 0x1 << HPIPE_PHY_TEST_RESET_OFFSET; + mask |= HPIPE_PHY_TEST_EN_MASK; + data |= 0x0 << HPIPE_PHY_TEST_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + mask = HPIPE_PHY_TEST_RESET_MASK; + data = 0x0 << HPIPE_PHY_TEST_RESET_OFFSET; + reg_set(hpipe_addr + HPIPE_PHY_TEST_CONTROL_REG, data, mask); + + return 1; +} + +/* This function performs RX training for all FFE possible values. + * We get the result for each FFE and eventually the best FFE will + * be used and set to the HW. + * + * Return '1' on succsess. + * Return '0' on failure. + */ +int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, + u32 lane) +{ + u32 mask, data, i, rx_train_result; + u32 max_rx_train = 0, max_rx_train_index = 0; + void __iomem *hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; + void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base_addr, lane); + int ret; + + debug_enter(); + + if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) { + pr_err("Comphy %d isn't configured to SFI\n", lane); + return 0; + } + + /* Configure SQ threshold and CDR lock */ + mask = HPIPE_SQUELCH_THRESH_IN_MASK; + data = 0xc << HPIPE_SQUELCH_THRESH_IN_OFFSET; + reg_set(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG, data, mask); + + mask = HPIPE_SQ_DEGLITCH_WIDTH_P_MASK; + data = 0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET; + mask |= HPIPE_SQ_DEGLITCH_WIDTH_N_MASK; + data |= 0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET; + mask |= HPIPE_SQ_DEGLITCH_EN_MASK; + data |= 0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_SQ_GLITCH_FILTER_CTRL, data, mask); + + mask = HPIPE_CDR_LOCK_DET_EN_MASK; + data = 0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET; + reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); + + udelay(100); + + /* Determine if we have a cable attached to this comphy, if not, + * we can't perform RX training. + */ + data = readl(hpipe_addr + HPIPE_SQUELCH_FFE_SETTING_REG); + if (data & HPIPE_SQUELCH_DETECTED_MASK) { + pr_err("Squelsh is not detected, can't perform RX training\n"); + return 0; + } + + data = readl(hpipe_addr + HPIPE_LOOPBACK_REG); + if (!(data & HPIPE_CDR_LOCK_MASK)) { + pr_err("CDR is not locked, can't perform RX training\n"); + return 0; + } + + /* Do preparations for RX training */ + mask = HPIPE_DFE_RES_FORCE_MASK; + data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); + + mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; + data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; + mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; + data |= 1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; + reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); + + /* Performs RX training for all possible FFE (Feed Forward + * Equalization, possible values are 0-7). + * We update the best value reached and the FFE which gave this value. + */ + for (i = 0; i < MAX_NUM_OF_FFE; i++) { + rx_train_result = 0; + ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane, + i, &rx_train_result); + + if (ret && (rx_train_result > max_rx_train)) { + max_rx_train = rx_train_result; + max_rx_train_index = i; + } + } + + /* If we were able to determine which FFE gives the best value, + * now we need to set it and run RX training again (only for this + * FFE). + */ + if (max_rx_train) { + ret = comphy_cp110_test_single_ffe(ptr_chip_cfg, lane, + max_rx_train_index, + &rx_train_result); + if (ret == 1) + printf("RX Training passed(FFE = %d, result = 0x%x)\n", + max_rx_train_index, rx_train_result); + } else { + pr_err("RX training failed\n"); + ret = 0; + } + + debug_exit(); + + return ret; +} + static int comphy_usb3_power_up(u32 lane, void __iomem *hpipe_base, void __iomem *comphy_base) { diff --git a/drivers/phy/marvell/comphy_hpipe.h b/drivers/phy/marvell/comphy_hpipe.h index a692035c941..cf2f986281e 100644 --- a/drivers/phy/marvell/comphy_hpipe.h +++ b/drivers/phy/marvell/comphy_hpipe.h @@ -6,6 +6,9 @@ #ifndef _COMPHY_HPIPE_H_ #define _COMPHY_HPIPE_H_ +#define MAX_NUM_OF_FFE 8 +#define RX_TRAINING_TIMEOUT 500 + /* SerDes IP register */ #define SD_EXTERNAL_CONFIG0_REG 0 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 @@ -52,6 +55,11 @@ #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) +#define SD_EXTERNAL_STATUS_REG 0xc +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7 +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \ + (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) + #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 #define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ @@ -66,6 +74,14 @@ #define SD_EXTERNAL_STATUS0_RF_RESET_IN_MASK \ (0x1 << SD_EXTERNAL_STATUS0_RF_RESET_IN_OFFSET) +#define SD_EXTERNAL_STATUS1_REG 0x1c +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET 0 +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_MASK \ + (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_COMP_OFFSET) +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET 1 +#define SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_MASK \ + (1 << SD_EXTERNAL_STATUS1_REG_RX_TRAIN_FAILED_OFFSET) + /* HPIPE register */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 @@ -88,7 +104,13 @@ #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) -#define HPIPE_SQUELCH_FFE_SETTING_REG 0x018 +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 +#define HPIPE_SQUELCH_THRESH_IN_OFFSET 8 +#define HPIPE_SQUELCH_THRESH_IN_MASK \ + (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) +#define HPIPE_SQUELCH_DETECTED_OFFSET 14 +#define HPIPE_SQUELCH_DETECTED_MASK \ + (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) #define HPIPE_DFE_REG0 0x01C #define HPIPE_DFE_RES_FORCE_OFFSET 15 @@ -215,10 +237,32 @@ #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) +#define HPIPE_PHY_TEST_CONTROL_REG 0x54 +#define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4 +#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \ + (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) +#define HPIPE_PHY_TEST_RESET_OFFSET 14 +#define HPIPE_PHY_TEST_RESET_MASK \ + (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) +#define HPIPE_PHY_TEST_EN_OFFSET 15 +#define HPIPE_PHY_TEST_EN_MASK \ + (0x1 << HPIPE_PHY_TEST_EN_OFFSET) + +#define HPIPE_PHY_TEST_DATA_REG 0x6c +#define HPIPE_PHY_TEST_DATA_OFFSET 0 +#define HPIPE_PHY_TEST_DATA_MASK \ + (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) + #define HPIPE_LOOPBACK_REG 0x08c #define HPIPE_LOOPBACK_SEL_OFFSET 1 #define HPIPE_LOOPBACK_SEL_MASK \ (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) +#define HPIPE_CDR_LOCK_OFFSET 7 +#define HPIPE_CDR_LOCK_MASK \ + (0x1 << HPIPE_CDR_LOCK_OFFSET) +#define HPIPE_CDR_LOCK_DET_EN_OFFSET 8 +#define HPIPE_CDR_LOCK_DET_EN_MASK \ + (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) #define HPIPE_SYNC_PATTERN_REG 0x090 #define HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET 10 @@ -382,6 +426,17 @@ #define HPIPE_OS_PH_VALID_MASK \ (0x1 << HPIPE_OS_PH_VALID_OFFSET) +#define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8 +#define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0 +#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4 +#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) +#define HPIPE_SQ_DEGLITCH_EN_OFFSET 8 +#define HPIPE_SQ_DEGLITCH_EN_MASK \ + (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) + #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 #define HPIPE_TRAIN_PAT_NUM_MASK \ @@ -452,6 +507,11 @@ #define HPIPE_TX_TRAIN_PAT_SEL_MASK \ (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) +#define HPIPE_SAVED_DFE_VALUES_REG 0x328 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \ + (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) + #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ diff --git a/include/mvebu/comphy.h b/include/mvebu/comphy.h index cde7a022af1..4d1b70393b2 100644 --- a/include/mvebu/comphy.h +++ b/include/mvebu/comphy.h @@ -16,7 +16,7 @@ struct comphy_map { bool end_point; }; +int comphy_rx_training(struct udevice *dev, u32 lane); int comphy_update_map(struct comphy_map *serdes_map, int count); #endif /* _MVEBU_COMPHY_H_ */ - -- cgit v1.3.1 From 5ed3dc27bb41fc3e9ab92e703e86fdd7fa1b4ef6 Mon Sep 17 00:00:00 2001 From: Marcin Wojtas Date: Tue, 15 Oct 2019 12:30:39 +0200 Subject: phy: marvell: cp110: remove unused definitions Even if comphy types of SATA2/SATA3/SGMII3 and comphy speeds of 1.5G/3G/6.25G were referenced in the driver non configuration (dts) was using it. This patch removes unused definitions. Change-Id: I53ed6f9d3a82b9d18cb4e488bc14d3cf687f9488 Signed-off-by: Grzegorz Jaszczyk Signed-off-by: Konstantin Porotchkin --- arch/arm/dts/armada-8040-mcbin.dts | 2 +- drivers/phy/marvell/comphy_core.c | 14 ++++----- drivers/phy/marvell/comphy_cp110.c | 3 -- include/dt-bindings/comphy/comphy_data.h | 50 +++++++++++++------------------- 4 files changed, 27 insertions(+), 42 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index 98a582df26f..a6ef40138da 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -302,7 +302,7 @@ phy-type = ; }; phy5 { - phy-type = ; + phy-type = ; phy-speed = ; }; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 45dba738662..92936079263 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -24,9 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; static const char *get_speed_string(u32 speed) { static const char * const speed_strings[] = { - "1.25 Gbps", "1.5 Gbps", "2.5 Gbps", - "3.0 Gbps", "3.125 Gbps", "5 Gbps", - "5.125 Gpbs", "6 Gbps", "6.25 Gbps", + "1.25 Gbps", "2.5 Gbps", "3.125 Gbps", + "5 Gbps", "5.125 Gpbs", "6 Gbps", "10.3125 Gbps" }; @@ -40,11 +39,10 @@ static const char *get_type_string(u32 type) { static const char * const type_strings[] = { "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", - "SATA0", "SATA1", "SATA2", "SATA3", "SGMII0", - "SGMII1", "SGMII2", "SGMII3", "QSGMII", "USB3" - "USB3_HOST0", "USB3_HOST1", "USB3_DEVICE", - "XAUI0", "XAUI1", "XAUI2", "XAUI3", - "RXAUI0", "RXAUI1", "SFI", "IGNORE" + "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2", + "USB3", "USB3_HOST0", "USB3_HOST1", + "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP", + "IGNORE" }; if (type < 0 || type > COMPHY_TYPE_MAX) diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 11dc46b28a6..620a749bb1f 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -1130,8 +1130,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, break; case COMPHY_TYPE_SATA0: case COMPHY_TYPE_SATA1: - case COMPHY_TYPE_SATA2: - case COMPHY_TYPE_SATA3: mode = COMPHY_FW_MODE_FORMAT(COMPHY_SATA_MODE); ret = comphy_sata_power_up(lane, hpipe_base_addr, comphy_base_addr, @@ -1166,7 +1164,6 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, mode); break; case COMPHY_TYPE_SGMII2: - case COMPHY_TYPE_SGMII3: if (ptr_comphy_map->speed == COMPHY_SPEED_INVALID) { debug("Warning: SGMII PHY speed in lane %d is invalid, set PHY speed to 1.25G\n", lane); diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 7d62dcf7fa5..8e927059892 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -7,16 +7,13 @@ #define _COMPHY_DATA_H_ #define COMPHY_SPEED_1_25G 0 -#define COMPHY_SPEED_1_5G 1 -#define COMPHY_SPEED_2_5G 2 -#define COMPHY_SPEED_3G 3 -#define COMPHY_SPEED_3_125G 4 -#define COMPHY_SPEED_5G 5 -#define COMPHY_SPEED_5_15625G 6 -#define COMPHY_SPEED_6G 7 -#define COMPHY_SPEED_6_25G 8 -#define COMPHY_SPEED_10_3125G 9 -#define COMPHY_SPEED_MAX 10 +#define COMPHY_SPEED_2_5G 1 +#define COMPHY_SPEED_3_125G 2 +#define COMPHY_SPEED_5G 3 +#define COMPHY_SPEED_5_15625G 4 +#define COMPHY_SPEED_6G 5 +#define COMPHY_SPEED_10_3125G 6 +#define COMPHY_SPEED_MAX 7 #define COMPHY_SPEED_INVALID 0xff #define COMPHY_TYPE_UNCONNECTED 0 @@ -26,26 +23,19 @@ #define COMPHY_TYPE_PEX3 4 #define COMPHY_TYPE_SATA0 5 #define COMPHY_TYPE_SATA1 6 -#define COMPHY_TYPE_SATA2 7 -#define COMPHY_TYPE_SATA3 8 -#define COMPHY_TYPE_SGMII0 9 -#define COMPHY_TYPE_SGMII1 10 -#define COMPHY_TYPE_SGMII2 11 -#define COMPHY_TYPE_SGMII3 12 -#define COMPHY_TYPE_QSGMII 13 -#define COMPHY_TYPE_USB3 14 -#define COMPHY_TYPE_USB3_HOST0 15 -#define COMPHY_TYPE_USB3_HOST1 16 -#define COMPHY_TYPE_USB3_DEVICE 17 -#define COMPHY_TYPE_XAUI0 18 -#define COMPHY_TYPE_XAUI1 19 -#define COMPHY_TYPE_XAUI2 20 -#define COMPHY_TYPE_XAUI3 21 -#define COMPHY_TYPE_RXAUI0 22 -#define COMPHY_TYPE_RXAUI1 23 -#define COMPHY_TYPE_SFI 24 -#define COMPHY_TYPE_IGNORE 25 -#define COMPHY_TYPE_MAX 26 +#define COMPHY_TYPE_SGMII0 7 +#define COMPHY_TYPE_SGMII1 8 +#define COMPHY_TYPE_SGMII2 9 +#define COMPHY_TYPE_USB3 10 +#define COMPHY_TYPE_USB3_HOST0 11 +#define COMPHY_TYPE_USB3_HOST1 12 +#define COMPHY_TYPE_USB3_DEVICE 13 +#define COMPHY_TYPE_RXAUI0 14 +#define COMPHY_TYPE_RXAUI1 15 +#define COMPHY_TYPE_SFI 16 +#define COMPHY_TYPE_AP 17 +#define COMPHY_TYPE_IGNORE 18 +#define COMPHY_TYPE_MAX 19 #define COMPHY_TYPE_INVALID 0xff #define COMPHY_POLARITY_NO_INVERT 0 -- cgit v1.3.1 From 341e548eb8f586c39c49efbd0b90eaf283fbee63 Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Mon, 14 May 2018 11:20:54 +0300 Subject: phy: marvell: add support for SFI1 In CP115, comphy4 can be configured into SFI port1 (in addition to SFI0). This patch adds the option described above. In addition, rename all existing SFI/XFI references: COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0 No functional change for exsiting configuration. Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0 Signed-off-by: Igal Liberman Signed-off-by: Konstantin Porotchkin --- arch/arm/dts/armada-7040-db.dts | 3 ++- arch/arm/dts/armada-8040-clearfog-gt-8k.dts | 4 ++-- arch/arm/dts/armada-8040-db.dts | 4 ++-- arch/arm/dts/armada-8040-mcbin.dts | 4 ++-- arch/arm/dts/armada-8040-puzzle-m801.dts | 4 ++-- arch/arm/dts/cn9130-crb-A.dts | 2 +- arch/arm/dts/cn9130-crb-B.dts | 2 +- drivers/phy/marvell/comphy_core.c | 2 +- drivers/phy/marvell/comphy_cp110.c | 14 ++++++++------ include/dt-bindings/comphy/comphy_data.h | 9 +++++---- 10 files changed, 26 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/armada-7040-db.dts b/arch/arm/dts/armada-7040-db.dts index f475fb36107..b158f923491 100644 --- a/arch/arm/dts/armada-7040-db.dts +++ b/arch/arm/dts/armada-7040-db.dts @@ -132,7 +132,8 @@ }; phy2 { - phy-type = ; + phy-type = ; + phy-speed = ; }; phy3 { diff --git a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts index ce5832c2fbd..6a586dbbba1 100644 --- a/arch/arm/dts/armada-8040-clearfog-gt-8k.dts +++ b/arch/arm/dts/armada-8040-clearfog-gt-8k.dts @@ -154,7 +154,7 @@ * CP0 Serdes Configuration: * Lane 0: PCIe0 (x1) * Lane 1: Not connected - * Lane 2: SFI (10G) + * Lane 2: SFI0 (10G) * Lane 3: Not connected * Lane 4: USB 3.0 host port1 (can be PCIe) * Lane 5: Not connected @@ -166,7 +166,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-db.dts b/arch/arm/dts/armada-8040-db.dts index 1edfaab682e..51c2f23f4db 100644 --- a/arch/arm/dts/armada-8040-db.dts +++ b/arch/arm/dts/armada-8040-db.dts @@ -95,7 +95,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; @@ -194,7 +194,7 @@ phy-type = ; }; phy2 { - phy-type = ; + phy-type = ; }; phy3 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts index a6ef40138da..21846483186 100644 --- a/arch/arm/dts/armada-8040-mcbin.dts +++ b/arch/arm/dts/armada-8040-mcbin.dts @@ -183,7 +183,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; @@ -299,7 +299,7 @@ phy-type = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; diff --git a/arch/arm/dts/armada-8040-puzzle-m801.dts b/arch/arm/dts/armada-8040-puzzle-m801.dts index 0becc4ff0d3..510fb84d5a9 100644 --- a/arch/arm/dts/armada-8040-puzzle-m801.dts +++ b/arch/arm/dts/armada-8040-puzzle-m801.dts @@ -234,7 +234,7 @@ phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; @@ -380,7 +380,7 @@ phy-speed = ; }; phy4 { - phy-type = ; + phy-type = ; }; phy5 { phy-type = ; diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts index 5c5e0fb2eb1..fcfcd15d8de 100644 --- a/arch/arm/dts/cn9130-crb-A.dts +++ b/arch/arm/dts/cn9130-crb-A.dts @@ -31,7 +31,7 @@ }; phy4 { - phy-type = ; + phy-type = ; phy-speed = ; }; diff --git a/arch/arm/dts/cn9130-crb-B.dts b/arch/arm/dts/cn9130-crb-B.dts index 6041084a2c8..b681b6032d6 100644 --- a/arch/arm/dts/cn9130-crb-B.dts +++ b/arch/arm/dts/cn9130-crb-B.dts @@ -31,7 +31,7 @@ }; phy4 { - phy-type = ; + phy-type = ; phy-speed = ; }; diff --git a/drivers/phy/marvell/comphy_core.c b/drivers/phy/marvell/comphy_core.c index 92936079263..2c9d7b2288d 100644 --- a/drivers/phy/marvell/comphy_core.c +++ b/drivers/phy/marvell/comphy_core.c @@ -41,7 +41,7 @@ static const char *get_type_string(u32 type) "UNCONNECTED", "PEX0", "PEX1", "PEX2", "PEX3", "SATA0", "SATA1", "SGMII0", "SGMII1", "SGMII2", "USB3", "USB3_HOST0", "USB3_HOST1", - "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI", "AP", + "USB3_DEVICE", "RXAUI0", "RXAUI1", "SFI0", "SFI1", "AP", "IGNORE" }; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index 349109b6dc0..576538feb70 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -109,10 +109,11 @@ int comphy_cp110_sfi_rx_training(struct chip_serdes_phy_config *ptr_chip_cfg, u32 lane) { int ret; + u32 type = ptr_chip_cfg->comphy_map_data[lane].type; debug_enter(); - if (ptr_chip_cfg->comphy_map_data[lane].type != COMPHY_TYPE_SFI) { + if (type != COMPHY_TYPE_SFI0 && type != COMPHY_TYPE_SFI1) { pr_err("Comphy %d isn't configured to SFI\n", lane); return 0; } @@ -630,13 +631,14 @@ int comphy_cp110_init(struct chip_serdes_phy_config *ptr_chip_cfg, ptr_chip_cfg->comphy_base_addr, lane, mode); break; - case COMPHY_TYPE_SFI: - mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, - COMPHY_UNIT_ID0, + case COMPHY_TYPE_SFI0: + case COMPHY_TYPE_SFI1: + /* Calculate SFI id */ + id = ptr_comphy_map->type - COMPHY_TYPE_SFI0; + mode = COMPHY_FW_FORMAT(COMPHY_SFI_MODE, id, ptr_comphy_map->speed); ret = comphy_smc(MV_SIP_COMPHY_POWER_ON, - ptr_chip_cfg->comphy_base_addr, lane, - mode); + ptr_chip_cfg->comphy_base_addr, lane, mode); break; case COMPHY_TYPE_RXAUI0: case COMPHY_TYPE_RXAUI1: diff --git a/include/dt-bindings/comphy/comphy_data.h b/include/dt-bindings/comphy/comphy_data.h index 8e927059892..8353a787405 100644 --- a/include/dt-bindings/comphy/comphy_data.h +++ b/include/dt-bindings/comphy/comphy_data.h @@ -32,10 +32,11 @@ #define COMPHY_TYPE_USB3_DEVICE 13 #define COMPHY_TYPE_RXAUI0 14 #define COMPHY_TYPE_RXAUI1 15 -#define COMPHY_TYPE_SFI 16 -#define COMPHY_TYPE_AP 17 -#define COMPHY_TYPE_IGNORE 18 -#define COMPHY_TYPE_MAX 19 +#define COMPHY_TYPE_SFI0 16 +#define COMPHY_TYPE_SFI1 17 +#define COMPHY_TYPE_AP 18 +#define COMPHY_TYPE_IGNORE 19 +#define COMPHY_TYPE_MAX 20 #define COMPHY_TYPE_INVALID 0xff #define COMPHY_POLARITY_NO_INVERT 0 -- cgit v1.3.1