From 7a11c7f9747240dc770954d320569596c0fbcb50 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 12 Jun 2009 21:20:37 +0200 Subject: pm9263: lowlevel init update move PSRAM init to pm9263.c this will allow us after to make the nor lowlevel_init generic Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/pm9263.h | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index f0dbe81d140..5ebf2863669 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -67,8 +67,6 @@ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ #define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A -/* EBI1_CSA, 3.3v, no pull-ups */ -#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100 /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -100,13 +98,7 @@ #define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ #define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ #define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */ - -/* setup SMC1, CS0 (PSRAM) - 16-bit */ -#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */ -#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */ -#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */ +#define CONFIG_SYS_SMC0_MODE0_VAL 0x00161003 /* SMC_MODE */ #define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ -- cgit v1.3.1 From 01550a2b650fbabc03334f9eadcc6083601a2414 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Fri, 12 Jun 2009 21:20:38 +0200 Subject: pm9263: use macro instead of hardcode value for the lowlevel_init optimize a few the RAM init Signed-off-by: Ilko Iliev Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/ronetix/pm9263/lowlevel_init.S | 2 +- board/ronetix/pm9263/pm9263.c | 2 +- include/asm-arm/arch-at91/at91_pmc.h | 1 + include/configs/pm9263.h | 109 ++++++++++++++++++++++++++--------- 4 files changed, 84 insertions(+), 30 deletions(-) (limited to 'include') diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S index 561722c7099..b139c893896 100644 --- a/board/ronetix/pm9263/lowlevel_init.S +++ b/board/ronetix/pm9263/lowlevel_init.S @@ -87,7 +87,7 @@ POS1: */ ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) - ldr r0, =0x0000FF01 + ldr r0, =CONFIG_SYS_MOR_VAL str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */ /* Reading the PMC Status to detect when the Main Oscillator is enabled */ diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index 8ca71da9ce5..29555f8db32 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -239,7 +239,7 @@ static int pm9263_lcd_hw_psram_init(void) at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY | (AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) | AT91_MATRIX_DEFMSTR_TYPE_FIXED | - (AT91_MATRIX_SLOT_CYCLE & (0x80 << 0))); + (AT91_MATRIX_SLOT_CYCLE & (0xFF << 0))); return 0; } diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h index 07580da6925..a82955c1bf2 100644 --- a/include/asm-arm/arch-at91/at91_pmc.h +++ b/include/asm-arm/arch-at91/at91_pmc.h @@ -65,6 +65,7 @@ #define AT91_PMC_USBDIV_2 (1 << 28) #define AT91_PMC_USBDIV_4 (2 << 28) #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ +#define AT91_PMC_PLLA_WR_ERRATA (1 << 29) /* Bit 29 must always be set to 1 when programming the CKGR_PLLAR register */ #define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 5ebf2863669..94e1eb9d8a4 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -32,8 +32,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define MASTER_PLL_DIV 15 -#define MASTER_PLL_MUL 162 +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ #define AT91_MAIN_CLOCK 18432000 @@ -46,39 +46,76 @@ #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ /* clocks */ -#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_PLLAR_VAL \ - (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL 0x00000100 +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL 0x00000102 +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL 0x00000200 +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91RM9200_PMC_MDIV_3 | \ + AT91_PMC_PDIV_1) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL 0x00000202 +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91RM9200_PMC_MDIV_3 | \ + AT91_PMC_PDIV_1) #endif /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC) /* SDRAM */ /* SDRAMC_MR Mode register */ #define CONFIG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/ +#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (7 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL 0 -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -87,25 +124,41 @@ #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ -#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ -#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC0_MODE0_VAL 0x00161003 /* SMC_MODE */ - -#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ - -/* Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ - -/* */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -- cgit v1.3.1 From 329492329700812c6df275aa0fda09d609cd0fd4 Mon Sep 17 00:00:00 2001 From: Ilko Iliev Date: Fri, 12 Jun 2009 21:20:39 +0200 Subject: at91: add support for the PM9261 board of Ronetix GmbH The PM9261 board is based on the AT91SAM9261-EK board. Here is the page on Ronetix website: http://www.ronetix.at/starter_kit_9261.html Signed-off-by: Ilko Iliev Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/ronetix/pm9261/Makefile | 61 ++++++ board/ronetix/pm9261/config.mk | 1 + board/ronetix/pm9261/led.c | 44 ++++ board/ronetix/pm9261/lowlevel_init.S | 259 ++++++++++++++++++++++++ board/ronetix/pm9261/partition.c | 47 +++++ board/ronetix/pm9261/pm9261.c | 288 ++++++++++++++++++++++++++ include/configs/pm9261.h | 382 +++++++++++++++++++++++++++++++++++ 10 files changed, 1087 insertions(+) create mode 100644 board/ronetix/pm9261/Makefile create mode 100644 board/ronetix/pm9261/config.mk create mode 100644 board/ronetix/pm9261/led.c create mode 100644 board/ronetix/pm9261/lowlevel_init.S create mode 100644 board/ronetix/pm9261/partition.c create mode 100644 board/ronetix/pm9261/pm9261.c create mode 100644 include/configs/pm9261.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 9379c7e0cd5..b5b54849e0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -209,6 +209,7 @@ Klaus Heydeck Ilko Iliev + PM9261 AT91SAM9261 PM9263 AT91SAM9263 Gary Jennejohn diff --git a/MAKEALL b/MAKEALL index f4599d6f394..fb80cfa8ada 100755 --- a/MAKEALL +++ b/MAKEALL @@ -589,6 +589,7 @@ LIST_at91=" \ kb9202 \ mp2usb \ m501sk \ + pm9261 \ pm9263 \ " diff --git a/Makefile b/Makefile index bcc81c93593..eb58dfea0d0 100644 --- a/Makefile +++ b/Makefile @@ -2782,6 +2782,9 @@ at91sam9rlek_config : unconfig fi; @$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91 +pm9261_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91 + pm9263_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91 diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile new file mode 100644 index 00000000000..1db9de2f85f --- /dev/null +++ b/board/ronetix/pm9261/Makefile @@ -0,0 +1,61 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# Ilko Iliev +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-y += led.o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS-y := lowlevel_init.o +endif + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ronetix/pm9261/config.mk b/board/ronetix/pm9261/config.mk new file mode 100644 index 00000000000..71854192f86 --- /dev/null +++ b/board/ronetix/pm9261/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x23f00000 \ No newline at end of file diff --git a/board/ronetix/pm9261/led.c b/board/ronetix/pm9261/led.c new file mode 100644 index 00000000000..396c3e73401 --- /dev/null +++ b/board/ronetix/pm9261/led.c @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * Ilko Iliev + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +void coloured_LED_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + + at91_set_gpio_output(CONFIG_RED_LED, 1); + at91_set_gpio_output(CONFIG_GREEN_LED, 1); + at91_set_gpio_output(CONFIG_YELLOW_LED, 1); + + at91_set_gpio_value(CONFIG_RED_LED, 0); + at91_set_gpio_value(CONFIG_GREEN_LED, 1); + at91_set_gpio_value(CONFIG_YELLOW_LED, 1); +} diff --git a/board/ronetix/pm9261/lowlevel_init.S b/board/ronetix/pm9261/lowlevel_init.S new file mode 100644 index 00000000000..5880a84ca66 --- /dev/null +++ b/board/ronetix/pm9261/lowlevel_init.S @@ -0,0 +1,259 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) + * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +.type lowlevel_init,function +lowlevel_init: + + mov r5, pc /* r5 = POS1 + 4 current */ +POS1: + ldr r0, =POS1 /* r0 = POS1 compile */ + ldr r2, _TEXT_BASE + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ + sub r5, r5, #4 /* r1 = text base - current */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/* ---------------------------------------------------------------------------- + * PMC Init Step 1. + * ---------------------------------------------------------------------------- + * - Check if the PLL is already initialized + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne PLL_setup_end + +/* --------------------------------------------------------------------------- + * - Enable the Main Oscillator + * --------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + /* Main oscillator Enable register PMC_MOR: */ + /* Enable main oscillator, OSCOUNT = 0xFF */ + ldr r0, =CONFIG_SYS_MOR_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MOSCS + bne MOSCS_Loop + +/* ---------------------------------------------------------------------------- + * PMC Init Step 2. + * ---------------------------------------------------------------------------- + * Setup PLLA + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r0, =CONFIG_SYS_PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKA + bne MOSCS_Loop1 + +/* ---------------------------------------------------------------------------- + * PMC Init Step 3. + * ---------------------------------------------------------------------------- + * - Switch on the Main Oscillator 18.432 MHz + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =CONFIG_SYS_MCKR1_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop + + ldr r0, =CONFIG_SYS_MCKR2_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop1 + +PLL_setup_end: + +/* ---------------------------------------------------------------------------- + * - memory control configuration 2 + * ---------------------------------------------------------------------------- + */ + ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 + +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word (AT91_BASE_SYS + AT91_WDT_MR) + .word CONFIG_SYS_WDTC_WDMR_VAL + + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word CONFIG_SYS_PIOC_PDR_VAL1 + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word CONFIG_SYS_PIOC_PPUDR_VAL + + .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word CONFIG_SYS_MATRIX_EBICSA_VAL + + /* flash */ + .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word CONFIG_SYS_SMC0_MODE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word CONFIG_SYS_SMC0_CYCLE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word CONFIG_SYS_SMC0_PULSE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word CONFIG_SYS_SMC0_SETUP0_VAL + +SMRDATA1: + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word CONFIG_SYS_SDRC_CR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word CONFIG_SYS_SDRC_MDR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL6 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL7 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL8 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL9 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL10 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL11 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL12 + /* User reset enable*/ + .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word CONFIG_SYS_RSTC_RMR_VAL + +SMRDATA2: + .word 0 diff --git a/board/ronetix/pm9261/partition.c b/board/ronetix/pm9261/partition.c new file mode 100644 index 00000000000..cc6cbef1fc0 --- /dev/null +++ b/board/ronetix/pm9261/partition.c @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson + * Ilko Iliev + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/*define the area offsets*/ +#ifdef CONFIG_SYS_USE_DATAFLASH +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, + {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, + {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, +}; +#else +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, ""}, +}; + +#endif diff --git a/board/ronetix/pm9261/pm9261.c b/board/ronetix/pm9261/pm9261.c new file mode 100644 index 00000000000..46948546ae2 --- /dev/null +++ b/board/ronetix/pm9261/pm9261.c @@ -0,0 +1,288 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) + * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000) +#include +#endif +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void pm9261_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBICSA); + at91_sys_write(AT91_MATRIX_EBICSA, + csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + /* Configure RDY/BSY */ + at91_set_gpio_input(AT91_PIN_PA16, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(AT91_PIN_PC14, 1); + + at91_set_A_periph(AT91_PIN_PC0, 0); /* NANDOE */ + at91_set_A_periph(AT91_PIN_PC1, 0); /* NANDWE */ +} +#endif + + +#ifdef CONFIG_DRIVER_DM9000 +static void pm9261_dm9000_hw_init(void) +{ + /* Configure SMC CS2 for DM9000 */ + at91_sys_write(AT91_SMC_SETUP(2), + AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(2), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8)); + at91_sys_write(AT91_SMC_CYCLE(2), + AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16)); + at91_sys_write(AT91_SMC_MODE(2), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | + AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | + AT91_SMC_TDF_(1)); + + /* Configure Interrupt pin as input, no pull-up */ + at91_set_gpio_input(AT91_PIN_PA24, 0); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 240, + vl_row: 320, + vl_clk: 4965000, + vl_sync: ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: 3, + vl_tft: 1, + vl_hsync_len: 5, + vl_left_margin: 1, + vl_right_margin:33, + vl_vsync_len: 1, + vl_upper_margin:1, + vl_lower_margin:0, + mmio: AT91SAM9261_LCDC_BASE, +}; + +void lcd_enable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 0); /* power up */ +} + +void lcd_disable(void) +{ + at91_set_gpio_value(AT91_PIN_PA22, 1); /* power down */ +} + +static void pm9261_lcd_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ + at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ + at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ + at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ + at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ + at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ + at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ + at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ + at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ + at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ + at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ + at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ + at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ + at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ + at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ + at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ + at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ + at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ + + at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); + + gd->fb_base = AT91SAM9261_SRAM_BASE; +} + +#ifdef CONFIG_LCD_INFO +#include +#include + +extern flash_info_t flash_info[]; + +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size, flash_size, dataflash_size; + int i; + char temp[32]; + + lcd_printf ("%s\n", U_BOOT_VERSION); + lcd_printf ("(C) 2009 Ronetix GmbH\n"); + lcd_printf ("support@ronetix.at\n"); + lcd_printf ("%s CPU at %s MHz", + AT91_CPU_NAME, + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; + + flash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) + flash_size += flash_info[i].size; + + dataflash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_DATAFLASH_BANKS; i++) + dataflash_size += (unsigned int) dataflash_info[i].Device.pages_number * + dataflash_info[i].Device.pages_size; + + lcd_printf ("%ld MB SDRAM, %ld MB NAND\n%ld MB NOR Flash\n" + "%ld MB DataFlash\n", + dram_size >> 20, + nand_size >> 20, + flash_size >> 20, + dataflash_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +#endif /* CONFIG_LCD */ + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOA); + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC); + + /* arch number of PM9261-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PM9261; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + pm9261_nand_hw_init(); +#endif +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_DRIVER_DM9000 + pm9261_dm9000_hw_init(); +#endif +#ifdef CONFIG_LCD + pm9261_lcd_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_DRIVER_DM9000 + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard (void) +{ + char buf[32]; + + printf ("Board : Ronetix PM9261\n"); + printf ("Crystal frequency: %8s MHz\n", + strmhz(buf, get_main_clk_rate())); + printf ("CPU clock : %8s MHz\n", + strmhz(buf, get_cpu_clk_rate())); + printf ("Master clock : %8s MHz\n", + strmhz(buf, get_mck_clk_rate())); + + return 0; +} +#endif diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h new file mode 100644 index 00000000000..ac09cf29479 --- /dev/null +++ b/include/configs/pm9261.h @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * Ilko Iliev + * + * Configuation settings for the RONETIX PM9261 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* ARM asynchronous clock */ +#define AT91_CPU_NAME "AT91SAM9261" + +#define CONFIG_DISPLAY_BOARDINFO + +#define MASTER_PLL_DIV 15 +#define MASTER_PLL_MUL 162 +#define MAIN_PLL_DIV 2 +#define AT91_MAIN_CLOCK 18432000 + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ +#define CONFIG_PM9261 1 /* on a Ronetix PM9261 Board */ +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* clocks */ +/* CKGR_MOR - enable main osc. */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 + +/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ +#define CONFIG_SYS_MATRIX_EBICSA_VAL \ + (AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (3 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#undef CONFIG_SKIP_LOWLEVEL_INIT +#undef CONFIG_SKIP_RELOCATE_UBOOT + +/* + * Hardware drivers + */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +/* LCD */ +#define CONFIG_LCD 1 +#define LCD_BPP LCD_COLOR8 +#define CONFIG_LCD_LOGO 1 +#undef LCD_TEST_PATTERN +#define CONFIG_LCD_INFO 1 +#define CONFIG_LCD_INFO_BELOW_LOGO 1 +#define CONFIG_SYS_WHITE_ON_BLACK 1 +#define CONFIG_ATMEL_LCD 1 +#define CONFIG_ATMEL_LCD_BGR555 1 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 + +/* LED */ +#define CONFIG_AT91_LED +#define CONFIG_RED_LED AT91_PIN_PC12 +#define CONFIG_GREEN_LED AT91_PIN_PC13 +#define CONFIG_YELLOW_LED AT91_PIN_PC15 + +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_USB 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD22 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) +/* our CLE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA16 + + +/* NOR flash */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x30000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_USE_16BIT 1 +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_RESET_PHY_R 1 + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_DOS_PARTITION 1 +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE 1 + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x23e00000 + +#undef CONFIG_SYS_USE_DATAFLASH_CS0 +#undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_USE_FLASH 1 + +#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE \ + (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=at91_nand:-(root) " \ + "rw rootfstype=jffs2" + +#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=at91_nand:128k(bootstrap)ro," \ + "256k(uboot)ro,128k(env1)ro," \ + "128k(env2)ro,2M(linux),-(root) " \ + "rw rootfstype=jffs2" + +#elif defined (CONFIG_SYS_USE_FLASH) + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x10000 +#define CONFIG_ENV_OVERWRITE 1 + +/* JFFS Partition offset set */ +#define CONFIG_SYS_JFFS2_FIRST_BANK 0 +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* 512k reserved for u-boot */ +#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 + +#define CONFIG_BOOTCOMMAND "run flashboot" + +#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=nand" +#define MTDPARTS_DEFAULT \ + "mtdparts=physmap-flash.0:" \ + "256k(u-boot)ro," \ + "64k(u-boot-env)ro," \ + "1408k(kernel)," \ + "-(rootfs);" \ + "nand:-(nand)" + +#define CONFIG_CON_ROT "fbcon=rotate:3 " +#define CONFIG_BOOTARGS "root=/dev/mtdblock4 rootfstype=jffs2 " CONFIG_CON_ROT + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "partition=nand0,0\0" \ + "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + CONFIG_CON_ROT \ + "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ + "addip=setenv bootargs $(bootargs) " \ + "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ + ":$(hostname):eth0:off\0" \ + "ramboot=tftpboot 0x22000000 vmImage;" \ + "run ramargs;run addip;bootm 22000000\0" \ + "nfsboot=tftpboot 0x22000000 vmImage;" \ + "run nfsargs;run addip;bootm 22000000\0" \ + "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ + "" +#else +#error "Undefined memory device" +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "pm9261> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit v1.3.1 From 1b3b7c640d04df2ba9a9d947117d112a75fee7f4 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 13 Jun 2009 12:48:36 +0200 Subject: at91sam9263ek: add nor flash support this will allow you to store use it for the env and to boot directly U-Boot from Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- Makefile | 9 + board/atmel/at91sam9263ek/Makefile | 7 +- board/atmel/at91sam9263ek/at91sam9263ek.c | 19 ++- board/atmel/at91sam9263ek/lowlevel_init.S | 264 ++++++++++++++++++++++++++++++ doc/README.at91 | 5 + include/configs/at91sam9263ek.h | 142 +++++++++++++++- 6 files changed, 437 insertions(+), 9 deletions(-) create mode 100644 board/atmel/at91sam9263ek/lowlevel_init.S (limited to 'include') diff --git a/Makefile b/Makefile index eb58dfea0d0..a6f42319366 100644 --- a/Makefile +++ b/Makefile @@ -2754,6 +2754,8 @@ at91sam9261ek_config : unconfig fi; @$(MKCONFIG) -a at91sam9261ek arm arm926ejs at91sam9261ek atmel at91 +at91sam9263ek_norflash_config \ +at91sam9263ek_norflash_boot_config \ at91sam9263ek_nandflash_config \ at91sam9263ek_dataflash_config \ at91sam9263ek_dataflash_cs0_config \ @@ -2762,10 +2764,17 @@ at91sam9263ek_config : unconfig @if [ "$(findstring _nandflash,$@)" ] ; then \ echo "#define CONFIG_SYS_USE_NANDFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in NAND FLASH" ; \ + elif [ "$(findstring norflash,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_NORFLASH 1" >>$(obj)include/config.h ; \ + $(XECHO) "... with environment variable in NOR FLASH" ; \ else \ echo "#define CONFIG_SYS_USE_DATAFLASH 1" >>$(obj)include/config.h ; \ $(XECHO) "... with environment variable in SPI DATAFLASH CS0" ; \ fi; + @if [ "$(findstring norflash_boot,$@)" ] ; then \ + echo "#define CONFIG_SYS_USE_BOOT_NORFLASH 1" >>$(obj)include/config.h ; \ + $(XECHO) "... and boot from NOR FLASH" ; \ + fi; @$(MKCONFIG) -a at91sam9263ek arm arm926ejs at91sam9263ek atmel at91 at91sam9rlek_nandflash_config \ diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 013ed215f9f..19a354b6e1c 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -32,10 +32,13 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += at91sam9263ek.o COBJS-y += led.o COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS-y += lowlevel_init.o +endif -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) -SOBJS := $(addprefix $(obj),$(SOBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS-y)) $(LIB): $(obj).depend $(OBJS) $(SOBJS) $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index 57d5c953f77..660c4734454 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -196,9 +196,16 @@ static void at91sam9263ek_lcd_hw_init(void) #include #include +#ifndef CONFIG_SYS_NO_FLASH +extern flash_info_t flash_info[]; +#endif + void lcd_show_board_info(void) { ulong dram_size, nand_size; +#ifndef CONFIG_SYS_NO_FLASH + ulong flash_size; +#endif int i; char temp[32]; @@ -215,9 +222,19 @@ void lcd_show_board_info(void) nand_size = 0; for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) nand_size += nand_info[i].size; - lcd_printf (" %ld MB SDRAM, %ld MB NAND\n", +#ifndef CONFIG_SYS_NO_FLASH + flash_size = 0; + for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) + flash_size += flash_info[i].size; +#endif + lcd_printf (" %ld MB SDRAM, %ld MB NAND", dram_size >> 20, nand_size >> 20 ); +#ifndef CONFIG_SYS_NO_FLASH + lcd_printf (",\n %ld MB NOR", + flash_size >> 20); +#endif + lcd_puts ("\n"); } #endif /* CONFIG_LCD_INFO */ #endif diff --git a/board/atmel/at91sam9263ek/lowlevel_init.S b/board/atmel/at91sam9263ek/lowlevel_init.S new file mode 100644 index 00000000000..3a957776df9 --- /dev/null +++ b/board/atmel/at91sam9263ek/lowlevel_init.S @@ -0,0 +1,264 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) + * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +.type lowlevel_init,function +lowlevel_init: + + mov r5, pc /* r5 = POS1 + 4 current */ +POS1: + ldr r0, =POS1 /* r0 = POS1 compile */ + ldr r2, _TEXT_BASE + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ + sub r5, r5, #4 /* r1 = text base - current */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/* ---------------------------------------------------------------------------- + * PMC Init Step 1. + * ---------------------------------------------------------------------------- + * - Check if the PLL is already initialized + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne PLL_setup_end + +/* --------------------------------------------------------------------------- + * - Enable the Main Oscillator + * --------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + ldr r0, =CONFIG_SYS_MOR_VAL + str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */ + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MOSCS + bne MOSCS_Loop + +/* ---------------------------------------------------------------------------- + * PMC Init Step 2. + * ---------------------------------------------------------------------------- + * Setup PLLA + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r0, =CONFIG_SYS_PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKA + bne MOSCS_Loop1 + +/* ---------------------------------------------------------------------------- + * PMC Init Step 3. + * ---------------------------------------------------------------------------- + * - Switch on the Main Oscillator 16.367 MHz + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =CONFIG_SYS_MCKR1_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop + + ldr r0, =CONFIG_SYS_MCKR2_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop1 + +PLL_setup_end: + +/* ---------------------------------------------------------------------------- + * - memory control configuration 2 + * ---------------------------------------------------------------------------- + */ + ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 + +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word (AT91_BASE_SYS + AT91_WDT_MR) + .word CONFIG_SYS_WDTC_WDMR_VAL + + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word CONFIG_SYS_PIOD_PDR_VAL1 + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word CONFIG_SYS_PIOD_PPUDR_VAL + .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word CONFIG_SYS_PIOD_PPUDR_VAL + + .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) + .word CONFIG_SYS_MATRIX_EBI0CSA_VAL + + /* flash */ + .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word CONFIG_SYS_SMC0_MODE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word CONFIG_SYS_SMC0_CYCLE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word CONFIG_SYS_SMC0_PULSE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word CONFIG_SYS_SMC0_SETUP0_VAL + +SMRDATA1: + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word CONFIG_SYS_SDRC_CR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word CONFIG_SYS_SDRC_MDR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL6 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL7 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL8 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL9 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL10 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL11 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL12 + /* User reset enable*/ + .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word CONFIG_SYS_RSTC_RMR_VAL +#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP + /* MATRIX_MCFG - REMAP all masters */ + .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word 0x1FF +#endif + +SMRDATA2: + .word 0 diff --git a/doc/README.at91 b/doc/README.at91 index 9b4eae6e143..4a2c56bd9ed 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -62,11 +62,16 @@ Environment variables U-Boot environment variables can be stored at different places: - Dataflash on SPI chip select 0 (dataflash card) - Nand flash. + - Nor falsh (not populate by default) You can choose your storage location at config step (here for at91sam9260ek) : make at91sam9263ek_config - use data flash (spi cs0) (default) make at91sam9263ek_nandflash_config - use nand flash make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) + make at91sam9263ek_norflash_config - use nor falsh + + You can choose to boot directly from U-Boot at config step + make at91sam9263ek_norflash_boot_config - boot from nor falsh ------------------------------------------------------------------------------ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index c212d11d0d2..00f3114fb5d 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -41,8 +41,10 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SKIP_RELOCATE_UBOOT +#endif /* * Hardware drivers @@ -113,15 +115,143 @@ #define DATAFLASH_TCHS (0x1 << 24) /* NOR flash, if populated */ -#if 1 -#define CONFIG_SYS_NO_FLASH 1 -#else +#ifdef CONFIG_SYS_USE_NORFLASH #define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define PHYS_FLASH_1 0x10000000 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_MONITOR_SEC 1:0-3 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000) +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) + +/* Address and size of Primary Environment Sector */ +#define CONFIG_ENV_SIZE 0x2000 + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \ + "update=" \ + "protect off ${monitor_base} +${filesize};" \ + "erase ${monitor_base} +${filesize};" \ + "cp.b ${load_addr} ${monitor_base} ${filesize};" \ + "protect on ${monitor_base} +${filesize}\0" + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define MASTER_PLL_MUL 171 +#define MASTER_PLL_DIV 14 + +/* clocks */ +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLA_WR_ERRATA | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_OUT | \ + AT91_PMC_PLLCOUNT | /* PLL Counter */ \ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_CSS_SLOW | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_CSS_PLLA | \ + AT91_PMC_PRES_1 | \ + AT91SAM9_PMC_MDIV_2 | \ + AT91_PMC_PDIV_1) + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +/* no pull-up for D[31:16] */ +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V | \ + AT91_MATRIX_EBI0_CS1A_SDRAMC) + +/* SDRAM */ +/* SDRAMC_MR Mode register */ +#define CONFIG_SYS_SDRC_MR_VAL1 0 +/* SDRAMC_TR - Refresh Timer register */ +#define CONFIG_SYS_SDRC_TR_VAL1 0x13C +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (1 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (1 << 28)) /* Exit Self Refresh to Active Delay */ + +/* Memory Device Register -> SDRAM */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_NWESETUP_(10) | AT91_SMC_NCS_WRSETUP_(10) | \ + AT91_SMC_NRDSETUP_(10) | AT91_SMC_NCS_RDSETUP_(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_NWEPULSE_(11) | AT91_SMC_NCS_WRPULSE_(11) | \ + AT91_SMC_NRDPULSE_(11) | AT91_SMC_NCS_RDPULSE_(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_NWECYCLE_(22) | AT91_SMC_NRDCYCLE_(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_READMODE | AT91_SMC_WRITEMODE | \ + AT91_SMC_DBW_16 | \ + AT91_SMC_TDFMODE | \ + AT91_SMC_TDF_(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_PROCRST | \ + AT91_RSTC_RSTTYP_WAKEUP | \ + AT91_RSTC_RSTTYP_WATCHDOG) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_WDIDLEHLT | AT91_WDT_WDDBGHLT | \ + AT91_WDT_WDV | \ + AT91_WDT_WDDIS | \ + AT91_WDT_WDD) +#endif + +#else +#define CONFIG_SYS_NO_FLASH 1 #endif /* NAND flash */ @@ -175,7 +305,7 @@ "mtdparts=at91_nand:-(root) "\ "rw rootfstype=jffs2" -#else /* CONFIG_SYS_USE_NANDFLASH */ +#elif CONFIG_SYS_USE_NANDFLASH /* bootstrap + u-boot + env + linux in nandflash */ #define CONFIG_ENV_IS_IN_NAND 1 -- cgit v1.3.1 From 8096c51fd4e611ed666dbe77767e81af5d94fc7b Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 13 Jun 2009 12:50:04 +0200 Subject: at91: unify nor boot support the lowlevel init sequence is the same so unify it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- board/atmel/at91sam9263ek/Makefile | 3 - board/atmel/at91sam9263ek/lowlevel_init.S | 264 -------------------------- board/ronetix/pm9261/Makefile | 4 - board/ronetix/pm9261/lowlevel_init.S | 259 -------------------------- board/ronetix/pm9263/Makefile | 4 - board/ronetix/pm9263/lowlevel_init.S | 264 -------------------------- cpu/arm926ejs/at91/Makefile | 8 +- cpu/arm926ejs/at91/lowlevel_init.S | 278 ++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91sam9_matrix.h | 28 +++ 9 files changed, 312 insertions(+), 800 deletions(-) delete mode 100644 board/atmel/at91sam9263ek/lowlevel_init.S delete mode 100644 board/ronetix/pm9261/lowlevel_init.S delete mode 100644 board/ronetix/pm9263/lowlevel_init.S create mode 100644 cpu/arm926ejs/at91/lowlevel_init.S create mode 100644 include/asm-arm/arch-at91/at91sam9_matrix.h (limited to 'include') diff --git a/board/atmel/at91sam9263ek/Makefile b/board/atmel/at91sam9263ek/Makefile index 19a354b6e1c..79ec45fd9f9 100644 --- a/board/atmel/at91sam9263ek/Makefile +++ b/board/atmel/at91sam9263ek/Makefile @@ -32,9 +32,6 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += at91sam9263ek.o COBJS-y += led.o COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y += lowlevel_init.o -endif SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/atmel/at91sam9263ek/lowlevel_init.S b/board/atmel/at91sam9263ek/lowlevel_init.S deleted file mode 100644 index 3a957776df9..00000000000 --- a/board/atmel/at91sam9263ek/lowlevel_init.S +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -.type lowlevel_init,function -lowlevel_init: - - mov r5, pc /* r5 = POS1 + 4 current */ -POS1: - ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ - sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ - - /* memory control configuration 1 */ - ldr r0, =SMRDATA - ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - -/* ---------------------------------------------------------------------------- - * PMC Init Step 1. - * ---------------------------------------------------------------------------- - * - Check if the PLL is already initialized - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - ldr r0, [r1] - and r0, r0, #3 - cmp r0, #0 - bne PLL_setup_end - -/* --------------------------------------------------------------------------- - * - Enable the Main Oscillator - * --------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) - ldr r0, =CONFIG_SYS_MOR_VAL - str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */ - - /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS -MOSCS_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS - bne MOSCS_Loop - -/* ---------------------------------------------------------------------------- - * PMC Init Step 2. - * ---------------------------------------------------------------------------- - * Setup PLLA - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL - str r0, [r1] - - /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA -MOSCS_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA - bne MOSCS_Loop1 - -/* ---------------------------------------------------------------------------- - * PMC Init Step 3. - * ---------------------------------------------------------------------------- - * - Switch on the Main Oscillator 16.367 MHz - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - - /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop - - ldr r0, =CONFIG_SYS_MCKR2_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop1 - -PLL_setup_end: - -/* ---------------------------------------------------------------------------- - * - memory control configuration 2 - * ---------------------------------------------------------------------------- - */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) - ldr r1, [r0] - cmp r1, #0 - bne SDRAM_setup_end - - ldr r0, =SMRDATA1 - ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 - -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - -SDRAM_setup_end: - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) - .word CONFIG_SYS_WDTC_WDMR_VAL - - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) - .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) - .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) - .word CONFIG_SYS_PIOD_PPUDR_VAL - - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL - - /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) - .word CONFIG_SYS_SMC0_MODE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) - .word CONFIG_SYS_SMC0_CYCLE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) - .word CONFIG_SYS_SMC0_PULSE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) - .word CONFIG_SYS_SMC0_SETUP0_VAL - -SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) - .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) - .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 - /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) - .word CONFIG_SYS_RSTC_RMR_VAL -#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP - /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) - .word 0x1FF -#endif - -SMRDATA2: - .word 0 diff --git a/board/ronetix/pm9261/Makefile b/board/ronetix/pm9261/Makefile index 1db9de2f85f..2e065a2bc90 100644 --- a/board/ronetix/pm9261/Makefile +++ b/board/ronetix/pm9261/Makefile @@ -34,10 +34,6 @@ COBJS-y += $(BOARD).o COBJS-y += led.o COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y := lowlevel_init.o -endif - SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) diff --git a/board/ronetix/pm9261/lowlevel_init.S b/board/ronetix/pm9261/lowlevel_init.S deleted file mode 100644 index 5880a84ca66..00000000000 --- a/board/ronetix/pm9261/lowlevel_init.S +++ /dev/null @@ -1,259 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009 Jean-Christopher PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -.type lowlevel_init,function -lowlevel_init: - - mov r5, pc /* r5 = POS1 + 4 current */ -POS1: - ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ - sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ - - /* memory control configuration 1 */ - ldr r0, =SMRDATA - ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - -/* ---------------------------------------------------------------------------- - * PMC Init Step 1. - * ---------------------------------------------------------------------------- - * - Check if the PLL is already initialized - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - ldr r0, [r1] - and r0, r0, #3 - cmp r0, #0 - bne PLL_setup_end - -/* --------------------------------------------------------------------------- - * - Enable the Main Oscillator - * --------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) - /* Main oscillator Enable register PMC_MOR: */ - /* Enable main oscillator, OSCOUNT = 0xFF */ - ldr r0, =CONFIG_SYS_MOR_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS -MOSCS_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS - bne MOSCS_Loop - -/* ---------------------------------------------------------------------------- - * PMC Init Step 2. - * ---------------------------------------------------------------------------- - * Setup PLLA - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL - str r0, [r1] - - /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA -MOSCS_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA - bne MOSCS_Loop1 - -/* ---------------------------------------------------------------------------- - * PMC Init Step 3. - * ---------------------------------------------------------------------------- - * - Switch on the Main Oscillator 18.432 MHz - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - - /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop - - ldr r0, =CONFIG_SYS_MCKR2_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop1 - -PLL_setup_end: - -/* ---------------------------------------------------------------------------- - * - memory control configuration 2 - * ---------------------------------------------------------------------------- - */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) - ldr r1, [r0] - cmp r1, #0 - bne SDRAM_setup_end - - ldr r0, =SMRDATA1 - ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 - -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - -SDRAM_setup_end: - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) - .word CONFIG_SYS_WDTC_WDMR_VAL - - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) - .word CONFIG_SYS_PIOC_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) - .word CONFIG_SYS_PIOC_PPUDR_VAL - - .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) - .word CONFIG_SYS_MATRIX_EBICSA_VAL - - /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) - .word CONFIG_SYS_SMC0_MODE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) - .word CONFIG_SYS_SMC0_CYCLE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) - .word CONFIG_SYS_SMC0_PULSE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) - .word CONFIG_SYS_SMC0_SETUP0_VAL - -SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) - .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) - .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 - /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) - .word CONFIG_SYS_RSTC_RMR_VAL - -SMRDATA2: - .word 0 diff --git a/board/ronetix/pm9263/Makefile b/board/ronetix/pm9263/Makefile index 270abd801fe..ebc2adfa3dc 100644 --- a/board/ronetix/pm9263/Makefile +++ b/board/ronetix/pm9263/Makefile @@ -34,10 +34,6 @@ COBJS-y += pm9263.o COBJS-y += led.o COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o -ifndef CONFIG_SKIP_LOWLEVEL_INIT -SOBJS-y := lowlevel_init.o -endif - SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y) $(SOBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS-y)) diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S deleted file mode 100644 index b139c893896..00000000000 --- a/board/ronetix/pm9263/lowlevel_init.S +++ /dev/null @@ -1,264 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -_TEXT_BASE: - .word TEXT_BASE - -.globl lowlevel_init -.type lowlevel_init,function -lowlevel_init: - - mov r5, pc /* r5 = POS1 + 4 current */ -POS1: - ldr r0, =POS1 /* r0 = POS1 compile */ - ldr r2, _TEXT_BASE - sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ - sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ - sub r5, r5, #4 /* r1 = text base - current */ - - /* memory control configuration 1 */ - ldr r0, =SMRDATA - ldr r2, =SMRDATA1 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - -/* ---------------------------------------------------------------------------- - * PMC Init Step 1. - * ---------------------------------------------------------------------------- - * - Check if the PLL is already initialized - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - ldr r0, [r1] - and r0, r0, #3 - cmp r0, #0 - bne PLL_setup_end - -/* --------------------------------------------------------------------------- - * - Enable the Main Oscillator - * --------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) - ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) - ldr r0, =CONFIG_SYS_MOR_VAL - str r0, [r1] /* Enable main oscillator, OSCOUNT = 0xFF */ - - /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_MOSCS -MOSCS_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MOSCS - bne MOSCS_Loop - -/* ---------------------------------------------------------------------------- - * PMC Init Step 2. - * ---------------------------------------------------------------------------- - * Setup PLLA - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL - str r0, [r1] - - /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_LOCKA -MOSCS_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_LOCKA - bne MOSCS_Loop1 - -/* ---------------------------------------------------------------------------- - * PMC Init Step 3. - * ---------------------------------------------------------------------------- - * - Switch on the Main Oscillator 18.432 MHz - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) - - /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop - - ldr r0, =CONFIG_SYS_MCKR2_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_MCKRDY -MCKRDY_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_MCKRDY - bne MCKRDY_Loop1 - -PLL_setup_end: - -/* ---------------------------------------------------------------------------- - * - memory control configuration 2 - * ---------------------------------------------------------------------------- - */ - ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) - ldr r1, [r0] - cmp r1, #0 - bne SDRAM_setup_end - - ldr r0, =SMRDATA1 - ldr r2, =SMRDATA2 - ldr r1, _TEXT_BASE - sub r0, r0, r1 - sub r2, r2, r1 - add r0, r0, r5 - add r2, r2, r5 - -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - -SDRAM_setup_end: - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word (AT91_BASE_SYS + AT91_WDT_MR) - .word CONFIG_SYS_WDTC_WDMR_VAL - - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) - .word CONFIG_SYS_PIOD_PDR_VAL1 - .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) - .word CONFIG_SYS_PIOD_PPUDR_VAL - .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) - .word CONFIG_SYS_PIOD_PPUDR_VAL - - .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) - .word CONFIG_SYS_MATRIX_EBI0CSA_VAL - - /* flash */ - .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) - .word CONFIG_SYS_SMC0_MODE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) - .word CONFIG_SYS_SMC0_CYCLE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) - .word CONFIG_SYS_SMC0_PULSE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) - .word CONFIG_SYS_SMC0_SETUP0_VAL - -SMRDATA1: - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_CR) - .word CONFIG_SYS_SDRC_CR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) - .word CONFIG_SYS_SDRC_MDR_VAL - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL4 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 - .word (AT91_BASE_SYS + AT91_SDRAMC_MR) - .word CONFIG_SYS_SDRC_MR_VAL5 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 - .word (AT91_BASE_SYS + AT91_SDRAMC_TR) - .word CONFIG_SYS_SDRC_TR_VAL2 - .word AT91_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 - /* User reset enable*/ - .word (AT91_BASE_SYS + AT91_RSTC_MR) - .word CONFIG_SYS_RSTC_RMR_VAL -#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP - /* MATRIX_MCFG - REMAP all masters */ - .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) - .word 0x1FF -#endif - -SMRDATA2: - .word 0 diff --git a/cpu/arm926ejs/at91/Makefile b/cpu/arm926ejs/at91/Makefile index 66eec76ea19..3da89f4fba9 100644 --- a/cpu/arm926ejs/at91/Makefile +++ b/cpu/arm926ejs/at91/Makefile @@ -37,8 +37,12 @@ COBJS-y += cpu.o COBJS-y += reset.o COBJS-y += timer.o -SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) +ifndef CONFIG_SKIP_LOWLEVEL_INIT +SOBJS-y := lowlevel_init.o +endif + +SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S new file mode 100644 index 00000000000..5ed518cc2db --- /dev/null +++ b/cpu/arm926ejs/at91/lowlevel_init.S @@ -0,0 +1,278 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +_TEXT_BASE: + .word TEXT_BASE + +.globl lowlevel_init +.type lowlevel_init,function +lowlevel_init: + + mov r5, pc /* r5 = POS1 + 4 current */ +POS1: + ldr r0, =POS1 /* r0 = POS1 compile */ + ldr r2, _TEXT_BASE + sub r0, r0, r2 /* r0 = POS1-_TEXT_BASE (POS1 relative) */ + sub r5, r5, r0 /* r0 = TEXT_BASE-1 */ + sub r5, r5, #4 /* r1 = text base - current */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/* ---------------------------------------------------------------------------- + * PMC Init Step 1. + * ---------------------------------------------------------------------------- + * - Check if the PLL is already initialized + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne PLL_setup_end + +/* --------------------------------------------------------------------------- + * - Enable the Main Oscillator + * --------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_MOR) + ldr r2, =(AT91_BASE_SYS + AT91_PMC_SR) + /* Main oscillator Enable register PMC_MOR: */ + ldr r0, =CONFIG_SYS_MOR_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MOSCS + bne MOSCS_Loop + +/* ---------------------------------------------------------------------------- + * PMC Init Step 2. + * ---------------------------------------------------------------------------- + * Setup PLLA + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR) + ldr r0, =CONFIG_SYS_PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_LOCKA + bne MOSCS_Loop1 + +/* ---------------------------------------------------------------------------- + * PMC Init Step 3. + * ---------------------------------------------------------------------------- + * - Switch on the Main Oscillator + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_BASE_SYS + AT91_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =CONFIG_SYS_MCKR1_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop + + ldr r0, =CONFIG_SYS_MCKR2_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_MCKRDY +MCKRDY_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_MCKRDY + bne MCKRDY_Loop1 + +PLL_setup_end: + +/* ---------------------------------------------------------------------------- + * - memory control configuration 2 + * ---------------------------------------------------------------------------- + */ + ldr r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR) + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + ldr r1, _TEXT_BASE + sub r0, r0, r1 + sub r2, r2, r1 + add r0, r0, r5 + add r2, r2, r5 + +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word (AT91_BASE_SYS + AT91_WDT_MR) + .word CONFIG_SYS_WDTC_WDMR_VAL + + /* configure PIOx as EBI0 D[16-31] */ +#if defined(CONFIG_AT91SAM9263) + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PDR) + .word CONFIG_SYS_PIOD_PDR_VAL1 + .word (AT91_BASE_SYS + AT91_PIOD + PIO_PUDR) + .word CONFIG_SYS_PIOD_PPUDR_VAL + .word (AT91_BASE_SYS + AT91_PIOD + PIO_ASR) + .word CONFIG_SYS_PIOD_PPUDR_VAL +#elif defined(CONFIG_AT91SAM9261) + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PDR) + .word CONFIG_SYS_PIOC_PDR_VAL1 + .word (AT91_BASE_SYS + AT91_PIOC + PIO_PUDR) + .word CONFIG_SYS_PIOC_PPUDR_VAL +#endif + +#if defined(AT91_MATRIX_EBI0CSA) + .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) + .word CONFIG_SYS_MATRIX_EBI0CSA_VAL +#else /* AT91_MATRIX_EBICSA */ + .word (AT91_BASE_SYS + AT91_MATRIX_EBICSA) + .word CONFIG_SYS_MATRIX_EBICSA_VAL +#endif + + /* flash */ + .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) + .word CONFIG_SYS_SMC0_MODE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) + .word CONFIG_SYS_SMC0_CYCLE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_PULSE(0)) + .word CONFIG_SYS_SMC0_PULSE0_VAL + + .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) + .word CONFIG_SYS_SMC0_SETUP0_VAL + +SMRDATA1: + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_CR) + .word CONFIG_SYS_SDRC_CR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MDR) + .word CONFIG_SYS_SDRC_MDR_VAL + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL1 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL3 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL6 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL7 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL8 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL9 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL4 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL10 + .word (AT91_BASE_SYS + AT91_SDRAMC_MR) + .word CONFIG_SYS_SDRC_MR_VAL5 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL11 + .word (AT91_BASE_SYS + AT91_SDRAMC_TR) + .word CONFIG_SYS_SDRC_TR_VAL2 + .word AT91_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL12 + /* User reset enable*/ + .word (AT91_BASE_SYS + AT91_RSTC_MR) + .word CONFIG_SYS_RSTC_RMR_VAL +#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP + /* MATRIX_MCFG - REMAP all masters */ + .word (AT91_BASE_SYS + AT91_MATRIX_MCFG0) + .word 0x1FF +#endif + +SMRDATA2: + .word 0 diff --git a/include/asm-arm/arch-at91/at91sam9_matrix.h b/include/asm-arm/arch-at91/at91sam9_matrix.h new file mode 100644 index 00000000000..913f3747908 --- /dev/null +++ b/include/asm-arm/arch-at91/at91sam9_matrix.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H +#define __ASM_ARCH_AT91SAM9_MATRIX_H + +#if defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20) +#include +#elif defined(CONFIG_AT91SAM9261) +#include +#elif defined(CONFIG_AT91SAM9263) +#include +#elif defined(CONFIG_AT91SAM9RL) +#include +#elif defined(CONFIG_AT91CAP9) +#include +#else +#error "Unsupported AT91SAM9/CAP9 processor" +#endif + +#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */ -- cgit v1.3.1 From 40c642bc19b9fa2906e3172487a522fee456340b Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sat, 13 Jun 2009 20:50:01 +0200 Subject: MX31: Add NAND SPL for i.MX31. This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov Signed-off-by: Magnus Lilja --- cpu/arm1136/start.S | 9 +- include/asm-arm/arch-mx31/mx31-regs.h | 5 + include/fsl_nfc.h | 109 ++++++++++++++ nand_spl/nand_boot_fsl_nfc.c | 259 ++++++++++++++++++++++++++++++++++ 4 files changed, 380 insertions(+), 2 deletions(-) create mode 100644 include/fsl_nfc.h create mode 100644 nand_spl/nand_boot_fsl_nfc.c (limited to 'include') diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 28cb5fdf93e..957f4389b2b 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -200,12 +200,15 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot +#ifdef CONFIG_NAND_SPL +_start_armboot: .word nand_boot +#else #ifdef CONFIG_ONENAND_IPL _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot -#endif - +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ /* ************************************************************************* @@ -217,6 +220,7 @@ _start_armboot: .word start_armboot * ************************************************************************* */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT cpu_init_crit: /* * flush v4 I/D caches @@ -243,6 +247,7 @@ cpu_init_crit: bl lowlevel_init /* go setup pll,mux,memory */ mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ #ifndef CONFIG_PRELOADER /* diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index a8a05c873de..c2e7dcf8318 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -194,4 +194,9 @@ #define CS5_BASE 0xB6000000 #define PCMCIA_MEM_BASE 0xC0000000 +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 + #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/include/fsl_nfc.h b/include/fsl_nfc.h new file mode 100644 index 00000000000..da5be379d19 --- /dev/null +++ b/include/fsl_nfc.h @@ -0,0 +1,109 @@ +/* + * + * (c) 2009 Magnus Lilja + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __FSL_NFC_H +#define __FSL_NFC_H + +/* + * Register map and bit definitions for the Freescale NAND Flash + * Controller present in i.MX31 and other devices. + */ + +struct fsl_nfc_regs { + u32 main_area0[128]; /* @0x000 */ + u32 main_area1[128]; + u32 main_area2[128]; + u32 main_area3[128]; + u32 spare_area0[4]; + u32 spare_area1[4]; + u32 spare_area2[4]; + u32 spare_area3[4]; + u32 reserved1[64 - 16 + 64 * 5]; + u16 bufsiz; /* @ 0xe00 */ + u16 reserved2; + u16 buffer_address; + u16 flash_add; + u16 flash_cmd; + u16 configuration; + u16 ecc_status_result; + u16 ecc_rslt_main_area; + u16 ecc_rslt_spare_area; + u16 nf_wr_prot; + u16 unlock_start_blk_add; + u16 unlock_end_blk_add; + u16 nand_flash_wr_pr_st; + u16 nand_flash_config1; + u16 nand_flash_config2; +}; + +/* + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/* + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/* + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/* + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data + * Output operation + */ +#define NFC_OUTPUT 0x8 + +/* + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/* + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read + * Status operation + */ +#define NFC_STATUS 0x20 + +/* + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +#endif /* __FSL_NFC_H */ diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c new file mode 100644 index 00000000000..a9df2a8273f --- /dev/null +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2009 + * Magnus Lilja + * + * (C) Copyright 2008 + * Maxim Artamonov, + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr at denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +static struct fsl_nfc_regs *nfc; + +static void nfc_wait_ready(void) +{ + uint32_t tmp; + + while (!(readw(&nfc->nand_flash_config2) & NFC_INT)) + ; + + /* Reset interrupt flag */ + tmp = readw(&nfc->nand_flash_config2); + tmp &= ~NFC_INT; + writew(tmp, &nfc->nand_flash_config2); +} + +static void nfc_nand_init(void) +{ + /* unlocking RAM Buff */ + writew(0x2, &nfc->configuration); + + /* hardware ECC checking and correct */ + writew(NFC_ECC_EN, &nfc->nand_flash_config1); +} + +static void nfc_nand_command(unsigned short command) +{ + writew(command, &nfc->flash_cmd); + writew(NFC_CMD, &nfc->nand_flash_config2); + nfc_wait_ready(); +} + +static void nfc_nand_page_address(unsigned int page_address) +{ + unsigned int page_count; + + writew(0x00, &nfc->flash_cmd); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + + /* code only for 2kb flash */ + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) { + writew(0x00, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + } + + page_count = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; + + if (page_address <= page_count) { + page_count--; /* transform 0x01000000 to 0x00ffffff */ + do { + writew(page_address & 0xff, &nfc->flash_add); + writew(NFC_ADDR, &nfc->nand_flash_config2); + nfc_wait_ready(); + page_address = page_address >> 8; + page_count = page_count >> 8; + } while (page_count); + } +} + +static void nfc_nand_data_output(void) +{ + int i; + + /* + * The NAND controller requires four output commands for + * large page devices. + */ + for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 512); i++) { + writew(NFC_ECC_EN, &nfc->nand_flash_config1); + writew(i, &nfc->buffer_address); /* read in i:th buffer */ + writew(NFC_OUTPUT, &nfc->nand_flash_config2); + nfc_wait_ready(); + } +} + +static int nfc_nand_check_ecc(void) +{ + return readw(&nfc->ecc_status_result); +} + +static int nfc_read_page(unsigned int page_address, unsigned char *buf) +{ + int i; + u32 *src; + u32 *dst; + + writew(0, &nfc->buffer_address); /* read in first 0 buffer */ + nfc_nand_command(NAND_CMD_READ0); + nfc_nand_page_address(page_address); + + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + nfc_nand_command(NAND_CMD_READSTART); + + nfc_nand_data_output(); /* fill the main buffer 0 */ + + if (nfc_nand_check_ecc()) + return -1; + + src = &nfc->main_area0[0]; + dst = (u32 *)buf; + + /* main copy loop from NAND-buffer to SDRAM memory */ + for (i = 0; i < (CONFIG_SYS_NAND_PAGE_SIZE / 4); i++) { + writel(readl(src), dst); + src++; + dst++; + } + + return 0; +} + +static int is_badblock(int pagenumber) +{ + int page = pagenumber; + u32 badblock; + u32 *src; + + /* Check the first two pages for bad block markers */ + for (page = pagenumber; page < pagenumber + 2; page++) { + writew(0, &nfc->buffer_address); /* read in first 0 buffer */ + nfc_nand_command(NAND_CMD_READ0); + nfc_nand_page_address(page); + + if (CONFIG_SYS_NAND_PAGE_SIZE == 0x800) + nfc_nand_command(NAND_CMD_READSTART); + + nfc_nand_data_output(); /* fill the main buffer 0 */ + + src = &nfc->spare_area0[0]; + + /* + * IMPORTANT NOTE: The nand flash controller uses a non- + * standard layout for large page devices. This can + * affect the position of the bad block marker. + */ + /* Get the bad block marker */ + badblock = readl(&src[CONFIG_SYS_NAND_BAD_BLOCK_POS / 4]); + badblock >>= 8 * (CONFIG_SYS_NAND_BAD_BLOCK_POS % 4); + badblock &= 0xff; + + /* bad block marker verify */ + if (badblock != 0xff) + return 1; /* potential bad block */ + } + + return 0; +} + +static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) +{ + int i; + unsigned int page; + unsigned int maxpages = CONFIG_SYS_NAND_SIZE / + CONFIG_SYS_NAND_PAGE_SIZE; + + nfc = (void *)NFC_BASE_ADDR; + + nfc_nand_init(); + + /* Convert to page number */ + page = from / CONFIG_SYS_NAND_PAGE_SIZE; + i = 0; + + while (i < (size / CONFIG_SYS_NAND_PAGE_SIZE)) { + if (nfc_read_page(page, buf) < 0) + return -1; + + page++; + i++; + buf = buf + CONFIG_SYS_NAND_PAGE_SIZE; + + /* + * Check if we have crossed a block boundary, and if so + * check for bad block. + */ + if (!(page % CONFIG_SYS_NAND_PAGE_COUNT)) { + /* + * Yes, new block. See if this block is good. If not, + * loop until we find i good block. + */ + while (is_badblock(page)) { + page = page + CONFIG_SYS_NAND_PAGE_COUNT; + /* Check i we've reached the end of flash. */ + if (page >= maxpages) + return -1; + } + } + } + + return 0; +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + nfc = (void *)NFC_BASE_ADDR; + + /* + * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must + * be aligned to full pages + */ + if (!nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, + (uchar *)CONFIG_SYS_NAND_U_BOOT_DST)) { + /* Copy from NAND successful, start U-boot */ + uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START; + uboot(); + } else { + /* Unrecoverable error when copying from NAND */ + hang(); + } +} + +/* + * Called in case of an exception. + */ +void hang(void) +{ + /* Loop forever */ + while (1) ; +} -- cgit v1.3.1 From 958f7da7887fea4a2091ae60944d62c1708c2c55 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 13 Jun 2009 20:50:02 +0200 Subject: ARM: Add macros.h to be used in assembler file. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-arm/macro.h | 74 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 include/asm-arm/macro.h (limited to 'include') diff --git a/include/asm-arm/macro.h b/include/asm-arm/macro.h new file mode 100644 index 00000000000..57b52606581 --- /dev/null +++ b/include/asm-arm/macro.h @@ -0,0 +1,74 @@ +/* + * include/asm-arm/macro.h + * + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_MACRO_H__ +#define __ASM_ARM_MACRO_H__ +#ifdef __ASSEMBLY__ + +/* + * These macros provide a convenient way to write 8, 16 and 32 bit data + * to any address. + * Registers r4 and r5 are used, any data in these registers are + * overwritten by the macros. + * The macros are valid for any ARM architecture, they do not implement + * any memory barriers so caution is recommended when using these when the + * caches are enabled or on a multi-core system. + */ + +.macro write32, addr, data + ldr r4, =\addr + ldr r5, =\data + str r5, [r4] +.endm + +.macro write16, addr, data + ldr r4, =\addr + ldrh r5, =\data + strh r5, [r4] +.endm + +.macro write8, addr, data + ldr r4, =\addr + ldrb r5, =\data + strb r5, [r4] +.endm + +/* + * This macro generates a loop that can be used for delays in the code. + * Register r4 is used, any data in this register is overwritten by the + * macro. + * The macro is valid for any ARM architeture. The actual time spent in the + * loop will vary from CPU to CPU though. + */ + +.macro wait_timer, time + ldr r4, =\time +1: + nop + subs r4, r4, #1 + bcs 1b +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_MACRO_H__ */ -- cgit v1.3.1 From dd2f6965a6c71f6f711ec98827880152e022c236 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sat, 13 Jun 2009 20:50:03 +0200 Subject: i.MX31: Create a common device file. Signed-off-by: Magnus Lilja --- cpu/arm1136/mx31/Makefile | 1 + cpu/arm1136/mx31/devices.c | 56 ++++++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31.h | 3 +++ 3 files changed, 60 insertions(+) create mode 100644 cpu/arm1136/mx31/devices.c (limited to 'include') diff --git a/cpu/arm1136/mx31/Makefile b/cpu/arm1136/mx31/Makefile index 1e49e8d80f9..c8e18f7f025 100644 --- a/cpu/arm1136/mx31/Makefile +++ b/cpu/arm1136/mx31/Makefile @@ -27,6 +27,7 @@ LIB = $(obj)lib$(SOC).a COBJS += generic.o COBJS += timer.o +COBJS += devices.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/arm1136/mx31/devices.c b/cpu/arm1136/mx31/devices.c new file mode 100644 index 00000000000..1f4ca7eb443 --- /dev/null +++ b/cpu/arm1136/mx31/devices.c @@ -0,0 +1,56 @@ +/* + * + * (C) Copyright 2009 Magnus Lilja + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +#ifdef CONFIG_SYS_MX31_UART1 +void mx31_uart1_hw_init(void) +{ + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); +} +#endif + +#ifdef CONFIG_MXC_SPI +void mx31_spi2_hw_init(void) +{ + /* SPI2 */ + mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); +} +#endif diff --git a/include/asm-arm/arch-mx31/mx31.h b/include/asm-arm/arch-mx31/mx31.h index 1d475dde7ef..53b9f27333d 100644 --- a/include/asm-arm/arch-mx31/mx31.h +++ b/include/asm-arm/arch-mx31/mx31.h @@ -47,4 +47,7 @@ static inline void mx31_gpio_set(unsigned int gpio, unsigned int value) } #endif +void mx31_uart1_hw_init(void); +void mx31_spi2_hw_init(void); + #endif /* __ASM_ARCH_MX31_H */ -- cgit v1.3.1 From 1dc4da749dbde27ec862f5b65703e8e4541fbba3 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 8 Jun 2009 04:12:45 +0400 Subject: mx27: basic cpu support This patch adds generic code to support Freescale's i.MX27 SoCs. Signed-off-by: Ilya Yanok --- cpu/arm926ejs/mx27/Makefile | 44 +++ cpu/arm926ejs/mx27/generic.c | 241 +++++++++++++++ cpu/arm926ejs/mx27/reset.c | 57 ++++ cpu/arm926ejs/mx27/timer.c | 191 ++++++++++++ include/asm-arm/arch-mx27/asm-offsets.h | 16 + include/asm-arm/arch-mx27/clock.h | 39 +++ include/asm-arm/arch-mx27/imx-regs.h | 509 ++++++++++++++++++++++++++++++++ 7 files changed, 1097 insertions(+) create mode 100644 cpu/arm926ejs/mx27/Makefile create mode 100644 cpu/arm926ejs/mx27/generic.c create mode 100644 cpu/arm926ejs/mx27/reset.c create mode 100644 cpu/arm926ejs/mx27/timer.c create mode 100644 include/asm-arm/arch-mx27/asm-offsets.h create mode 100644 include/asm-arm/arch-mx27/clock.h create mode 100644 include/asm-arm/arch-mx27/imx-regs.h (limited to 'include') diff --git a/cpu/arm926ejs/mx27/Makefile b/cpu/arm926ejs/mx27/Makefile new file mode 100644 index 00000000000..67d1b0e3037 --- /dev/null +++ b/cpu/arm926ejs/mx27/Makefile @@ -0,0 +1,44 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = generic.o reset.o timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c new file mode 100644 index 00000000000..eab54d86df4 --- /dev/null +++ b/cpu/arm926ejs/mx27/generic.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2008 Eric Jarrige + * Copyright (c) 2009 Ilya Yanok + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* + * get the system pll clock in Hz + * + * mfi + mfn / (mfd +1) + * f = 2 * f_ref * -------------------- + * pd + 1 + */ +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) +{ + unsigned int mfi = (pll >> 10) & 0xf; + unsigned int mfn = pll & 0x3ff; + unsigned int mfd = (pll >> 16) & 0x3ff; + unsigned int pd = (pll >> 26) & 0xf; + + mfi = mfi <= 5 ? 5 : mfi; + + return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn), + (mfd + 1) * (pd + 1)); +} + +static ulong clk_in_32k(void) +{ + return 1024 * CONFIG_MX27_CLK32; +} + +static ulong clk_in_26m(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { + /* divide by 1.5 */ + return 26000000 * 2 / 3; + } else { + return 26000000; + } +} + +ulong imx_get_mpllclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref; + + if (cscr & CSCR_MCU_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + return imx_decode_pll(readl(&pll->mpctl0), fref); +} + +ulong imx_get_armclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref = imx_get_mpllclk(); + ulong div; + + if (!(cscr & CSCR_ARM_SRC_MPLL)) + fref = lldiv((fref * 2), 3); + + div = ((cscr >> 12) & 0x3) + 1; + + return lldiv(fref, div); +} + +ulong imx_get_ahbclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref = imx_get_mpllclk(); + ulong div; + + div = ((cscr >> 8) & 0x3) + 1; + + return lldiv(fref * 2, 3 * div); +} + +ulong imx_get_spllclk(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + ulong cscr = readl(&pll->cscr); + ulong fref; + + if (cscr & CSCR_SP_SEL) + fref = clk_in_26m(); + else + fref = clk_in_32k(); + + return imx_decode_pll(readl(&pll->spctl0), fref); +} + +static ulong imx_decode_perclk(ulong div) +{ + return lldiv((imx_get_mpllclk() * 2), (div * 3)); +} + +ulong imx_get_perclk1(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); +} + +ulong imx_get_perclk2(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); +} + +ulong imx_get_perclk3(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); +} + +ulong imx_get_perclk4(void) +{ + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo (void) +{ + char buf[32]; + + printf("CPU: Freescale i.MX27 at %s MHz\n\n", + strmhz(buf, imx_get_mpllclk())); + return 0; +} +#endif + +void imx_gpio_mode(int gpio_mode) +{ + struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE; + unsigned int pin = gpio_mode & GPIO_PIN_MASK; + unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT; + unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT; + unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT; + unsigned int tmp; + + /* Pullup enable */ + if (gpio_mode & GPIO_PUEN) { + writel(readl(®s->port[port].puen) | (1 << pin), + ®s->port[port].puen); + } else { + writel(readl(®s->port[port].puen) & ~(1 << pin), + ®s->port[port].puen); + } + + /* Data direction */ + if (gpio_mode & GPIO_OUT) { + writel(readl(®s->port[port].ddir) | 1 << pin, + ®s->port[port].ddir); + } else { + writel(readl(®s->port[port].ddir) & ~(1 << pin), + ®s->port[port].ddir); + } + + /* Primary / alternate function */ + if (gpio_mode & GPIO_AF) { + writel(readl(®s->port[port].gpr) | (1 << pin), + ®s->port[port].gpr); + } else { + writel(readl(®s->port[port].gpr) & ~(1 << pin), + ®s->port[port].gpr); + } + + /* use as gpio? */ + if (!(gpio_mode & (GPIO_PF | GPIO_AF))) { + writel(readl(®s->port[port].gius) | (1 << pin), + ®s->port[port].gius); + } else { + writel(readl(®s->port[port].gius) & ~(1 << pin), + ®s->port[port].gius); + } + + /* Output / input configuration */ + if (pin < 16) { + tmp = readl(®s->port[port].ocr1); + tmp &= ~(3 << (pin * 2)); + tmp |= (ocr << (pin * 2)); + writel(tmp, ®s->port[port].ocr1); + + writel(readl(®s->port[port].iconfa1) & ~(3 << (pin * 2)), + ®s->port[port].iconfa1); + writel(readl(®s->port[port].iconfa1) | aout << (pin * 2), + ®s->port[port].iconfa1); + writel(readl(®s->port[port].iconfb1) & ~(3 << (pin * 2)), + ®s->port[port].iconfb1); + writel(readl(®s->port[port].iconfb1) | bout << (pin * 2), + ®s->port[port].iconfb1); + } else { + pin -= 16; + + tmp = readl(®s->port[port].ocr2); + tmp &= ~(3 << (pin * 2)); + tmp |= (ocr << (pin * 2)); + writel(tmp, ®s->port[port].ocr2); + + writel(readl(®s->port[port].iconfa2) & ~(3 << (pin * 2)), + ®s->port[port].iconfa2); + writel(readl(®s->port[port].iconfa2) | aout << (pin * 2), + ®s->port[port].iconfa2); + writel(readl(®s->port[port].iconfb2) & ~(3 << (pin * 2)), + ®s->port[port].iconfb2); + writel(readl(®s->port[port].iconfb2) | bout << (pin * 2), + ®s->port[port].iconfb2); + } +} + diff --git a/cpu/arm926ejs/mx27/reset.c b/cpu/arm926ejs/mx27/reset.c new file mode 100644 index 00000000000..6c54eafd37d --- /dev/null +++ b/cpu/arm926ejs/mx27/reset.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * Reset the cpu by setting up the watchdog timer and let it time out + */ +void reset_cpu (ulong ignored) +{ + struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE; + /* Disable watchdog and set Time-Out field to 0 */ + writel(0x00000000, ®s->wcr); + + /* Write Service Sequence */ + writel(0x00005555, ®s->wsr); + writel(0x0000AAAA, ®s->wsr); + + /* Enable watchdog */ + writel(WCR_WDE, ®s->wcr); + + while (1); + /*NOTREACHED*/ +} diff --git a/cpu/arm926ejs/mx27/timer.c b/cpu/arm926ejs/mx27/timer.c new file mode 100644 index 00000000000..d22252e1311 --- /dev/null +++ b/cpu/arm926ejs/mx27/timer.c @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 + * Ilya Yanok, Emcraft Systems Ltd, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_FRR (1 << 8) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */ +#define GPTCR_TEN 1 /* Timer enable */ + +static ulong timestamp; +static ulong lastinc; + +/* + * "time" is measured in 1 / CONFIG_SYS_HZ seconds, + * "tick" is internal timer period + */ +#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, CONFIG_MX27_CLK32); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + time *= CONFIG_MX27_CLK32; + do_div(time, CONFIG_SYS_HZ); + return time; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us = us * CONFIG_MX27_CLK32 + 999999; + do_div(us, 1000000); + return us; +} +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \ + CONFIG_SYS_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + do_div(tick, TICK_PER_TIME); + return tick; +} + +static inline unsigned long long time_to_tick(unsigned long long time) +{ + return time * TICK_PER_TIME; +} + +static inline unsigned long long us_to_tick(unsigned long long us) +{ + us += US_PER_TICK - 1; + do_div(us, US_PER_TICK); + return us; +} +#endif + +/* nothing really to do with interrupts, just starts up a counter. */ +/* The 32768Hz 32-bit timer overruns in 131072 seconds */ +int timer_init(void) +{ + int i; + struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; + struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; + + /* setup GP Timer 1 */ + writel(GPTCR_SWR, ®s->gpt_tctl); + + writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); + writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); + + for (i = 0; i < 100; i++) + writel(0, ®s->gpt_tctl); /* We have no udelay by now */ + writel(0, ®s->gpt_tprer); /* 32Khz */ + /* Freerun Mode, PERCLK1 input */ + writel(readl(®s->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR, + ®s->gpt_tctl); + writel(readl(®s->gpt_tctl) | GPTCR_TEN, ®s->gpt_tctl); + + return 0; +} + +void reset_timer_masked(void) +{ + struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; + /* reset time */ + /* capture current incrementer value time */ + lastinc = readl(®s->gpt_tcn); + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +unsigned long long get_ticks (void) +{ + struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE; + ulong now = readl(®s->gpt_tcn); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; +} + +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + timestamp = time_to_tick(t); +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; + + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; +} + diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h new file mode 100644 index 00000000000..497afe57454 --- /dev/null +++ b/include/asm-arm/arch-mx27/asm-offsets.h @@ -0,0 +1,16 @@ +#define AIPI1_PSR0 0x10000000 +#define AIPI1_PSR1 0x10000004 +#define AIPI2_PSR0 0x10020000 +#define AIPI2_PSR1 0x10020004 +#define CSCR 0x10027000 +#define MPCTL0 0x10027004 +#define SPCTL0 0x1002700c +#define PCDR0 0x10027018 +#define PCDR1 0x1002701c +#define PCCR0 0x10027020 +#define PCCR1 0x10027024 +#define ESDCTL0_ROF 0x00 +#define ESDCFG0_ROF 0x04 +#define ESDCTL1_ROF 0x08 +#define ESDCFG1_ROF 0x0C +#define ESDMISC_ROF 0x10 diff --git a/include/asm-arm/arch-mx27/clock.h b/include/asm-arm/arch-mx27/clock.h new file mode 100644 index 00000000000..5fc75c5d5c2 --- /dev/null +++ b/include/asm-arm/arch-mx27/clock.h @@ -0,0 +1,39 @@ +/* + * + * (c) 2009 Ilya Yanok, Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +ulong imx_get_mpllclk(void); +ulong imx_get_armclk(void); +ulong imx_get_spllclk(void); +ulong imx_get_fclk(void); +ulong imx_get_hclk(void); +ulong imx_get_bclk(void); +ulong imx_get_perclk1(void); +ulong imx_get_perclk2(void); +ulong imx_get_perclk3(void); +ulong imx_get_ahbclk(void); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h new file mode 100644 index 00000000000..5d2e0b36369 --- /dev/null +++ b/include/asm-arm/arch-mx27/imx-regs.h @@ -0,0 +1,509 @@ +/* + * + * (c) 2007 Pengutronix, Sascha Hauer + * (c) 2009 Ilya Yanok, Emcraft Systems + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _IMX_REGS_H +#define _IMX_REGS_H + +#ifndef __ASSEMBLY__ + +extern void imx_gpio_mode (int gpio_mode); + +/* AIPI */ +struct aipi_regs { + u32 psr0; + u32 psr1; +}; + +/* System Control */ +struct system_control_regs { + u32 res[5]; + u32 fmcr; + u32 gpcr; + u32 wbcr; + u32 dscr1; + u32 dscr2; + u32 dscr3; + u32 dscr4; + u32 dscr5; + u32 dscr6; + u32 dscr7; + u32 dscr8; + u32 dscr9; + u32 dscr10; + u32 dscr11; + u32 dscr12; + u32 dscr13; + u32 pscr; + u32 pmcr; + u32 res1; + u32 dcvr0; + u32 dcvr1; + u32 dcvr2; + u32 dcvr3; +}; + +/* Chip Select Registers */ +struct weim_regs { + u32 cs0u; /* Chip Select 0 Upper Register */ + u32 cs0l; /* Chip Select 0 Lower Register */ + u32 cs0a; /* Chip Select 0 Addition Register */ + u32 pad0; + u32 cs1u; /* Chip Select 1 Upper Register */ + u32 cs1l; /* Chip Select 1 Lower Register */ + u32 cs1a; /* Chip Select 1 Addition Register */ + u32 pad1; + u32 cs2u; /* Chip Select 2 Upper Register */ + u32 cs2l; /* Chip Select 2 Lower Register */ + u32 cs2a; /* Chip Select 2 Addition Register */ + u32 pad2; + u32 cs3u; /* Chip Select 3 Upper Register */ + u32 cs3l; /* Chip Select 3 Lower Register */ + u32 cs3a; /* Chip Select 3 Addition Register */ + u32 pad3; + u32 cs4u; /* Chip Select 4 Upper Register */ + u32 cs4l; /* Chip Select 4 Lower Register */ + u32 cs4a; /* Chip Select 4 Addition Register */ + u32 pad4; + u32 cs5u; /* Chip Select 5 Upper Register */ + u32 cs5l; /* Chip Select 5 Lower Register */ + u32 cs5a; /* Chip Select 5 Addition Register */ + u32 pad5; + u32 eim; /* WEIM Configuration Register */ +}; + +/* SDRAM Controller registers */ +struct esdramc_regs { +/* Enhanced SDRAM Control Register 0 */ + u32 esdctl0; +/* Enhanced SDRAM Configuration Register 0 */ + u32 esdcfg0; +/* Enhanced SDRAM Control Register 1 */ + u32 esdctl1; +/* Enhanced SDRAM Configuration Register 1 */ + u32 esdcfg1; +/* Enhanced SDRAM Miscellanious Register */ + u32 esdmisc; +}; + +/* Watchdog Registers*/ +struct wdog_regs { + u32 wcr; + u32 wsr; + u32 wstr; +}; + +/* PLL registers */ +struct pll_regs { + u32 cscr; /* Clock Source Control Register */ + u32 mpctl0; /* MCU PLL Control Register 0 */ + u32 mpctl1; /* MCU PLL Control Register 1 */ + u32 spctl0; /* System PLL Control Register 0 */ + u32 spctl1; /* System PLL Control Register 1 */ + u32 osc26mctl; /* Oscillator 26M Register */ + u32 pcdr0; /* Peripheral Clock Divider Register 0 */ + u32 pcdr1; /* Peripheral Clock Divider Register 1 */ + u32 pccr0; /* Peripheral Clock Control Register 0 */ + u32 pccr1; /* Peripheral Clock Control Register 1 */ + u32 ccsr; /* Clock Control Status Register */ +}; + +/* + * Definitions for the clocksource registers + */ +struct gpt_regs { + u32 gpt_tctl; + u32 gpt_tprer; + u32 gpt_tcmp; + u32 gpt_tcr; + u32 gpt_tcn; + u32 gpt_tstat; +}; + +/* + * GPIO Module and I/O Multiplexer + */ +#define PORTA 0 +#define PORTB 1 +#define PORTC 2 +#define PORTD 3 +#define PORTE 4 +#define PORTF 5 + +struct gpio_regs { + struct { + u32 ddir; + u32 ocr1; + u32 ocr2; + u32 iconfa1; + u32 iconfa2; + u32 iconfb1; + u32 iconfb2; + u32 dr; + u32 gius; + u32 ssr; + u32 icr1; + u32 icr2; + u32 imr; + u32 isr; + u32 gpr; + u32 swr; + u32 puen; + u32 res[0x2f]; + } port[6]; +}; + +/* IIM Control Registers */ +struct iim_regs { + u32 iim_stat; + u32 iim_statm; + u32 iim_err; + u32 iim_emask; + u32 iim_fctl; + u32 iim_ua; + u32 iim_la; + u32 iim_sdat; + u32 iim_prev; + u32 iim_srev; + u32 iim_prog_p; + u32 iim_scs0; + u32 iim_scs1; + u32 iim_scs2; + u32 iim_scs3; + u32 res[0x1F0]; + u32 iim_bank_area0[0x100]; +}; +#endif + +#define IMX_IO_BASE 0x10000000 + +#define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) +#define IMX_WDT_BASE (0x02000 + IMX_IO_BASE) +#define IMX_TIM1_BASE (0x03000 + IMX_IO_BASE) +#define IMX_TIM2_BASE (0x04000 + IMX_IO_BASE) +#define IMX_TIM3_BASE (0x05000 + IMX_IO_BASE) +#define IMX_UART1_BASE (0x0a000 + IMX_IO_BASE) +#define IMX_UART2_BASE (0x0b000 + IMX_IO_BASE) +#define IMX_UART3_BASE (0x0c000 + IMX_IO_BASE) +#define IMX_UART4_BASE (0x0d000 + IMX_IO_BASE) +#define IMX_I2C1_BASE (0x12000 + IMX_IO_BASE) +#define IMX_GPIO_BASE (0x15000 + IMX_IO_BASE) +#define IMX_TIM4_BASE (0x19000 + IMX_IO_BASE) +#define IMX_TIM5_BASE (0x1a000 + IMX_IO_BASE) +#define IMX_UART5_BASE (0x1b000 + IMX_IO_BASE) +#define IMX_UART6_BASE (0x1c000 + IMX_IO_BASE) +#define IMX_I2C2_BASE (0x1D000 + IMX_IO_BASE) +#define IMX_TIM6_BASE (0x1f000 + IMX_IO_BASE) +#define IMX_AIPI2_BASE (0x20000 + IMX_IO_BASE) +#define IMX_PLL_BASE (0x27000 + IMX_IO_BASE) +#define IMX_SYSTEM_CTL_BASE (0x27800 + IMX_IO_BASE) +#define IMX_IIM_BASE (0x28000 + IMX_IO_BASE) +#define IMX_FEC_BASE (0x2b000 + IMX_IO_BASE) + +#define IMX_ESD_BASE (0xD8001000) +#define IMX_WEIM_BASE (0xD8002000) + +/* FMCR System Control bit definition*/ +#define UART4_RXD_CTL (1 << 25) +#define UART4_RTS_CTL (1 << 24) +#define KP_COL6_CTL (1 << 18) +#define KP_ROW7_CTL (1 << 17) +#define KP_ROW6_CTL (1 << 16) +#define PC_WAIT_B_CTL (1 << 14) +#define PC_READY_CTL (1 << 13) +#define PC_VS1_CTL (1 << 12) +#define PC_VS2_CTL (1 << 11) +#define PC_BVD1_CTL (1 << 10) +#define PC_BVD2_CTL (1 << 9) +#define IOS16_CTL (1 << 8) +#define NF_FMS (1 << 5) +#define NF_16BIT_SEL (1 << 4) +#define SLCDC_SEL (1 << 2) +#define SDCS1_SEL (1 << 1) +#define SDCS0_SEL (1 << 0) + + +/* important definition of some bits of WCR */ +#define WCR_WDE 0x04 + +#define CSCR_MPEN (1 << 0) +#define CSCR_SPEN (1 << 1) +#define CSCR_FPM_EN (1 << 2) +#define CSCR_OSC26M_DIS (1 << 3) +#define CSCR_OSC26M_DIV1P5 (1 << 4) +#define CSCR_AHB_DIV +#define CSCR_ARM_DIV +#define CSCR_ARM_SRC_MPLL (1 << 15) +#define CSCR_MCU_SEL (1 << 16) +#define CSCR_SP_SEL (1 << 17) +#define CSCR_MPLL_RESTART (1 << 18) +#define CSCR_SPLL_RESTART (1 << 19) +#define CSCR_MSHC_SEL (1 << 20) +#define CSCR_H264_SEL (1 << 21) +#define CSCR_SSI1_SEL (1 << 22) +#define CSCR_SSI2_SEL (1 << 23) +#define CSCR_SD_CNT +#define CSCR_USB_DIV +#define CSCR_UPDATE_DIS (1 << 31) + +#define MPCTL1_BRMO (1 << 6) +#define MPCTL1_LF (1 << 15) + +#define PCCR0_SSI2_EN (1 << 0) +#define PCCR0_SSI1_EN (1 << 1) +#define PCCR0_SLCDC_EN (1 << 2) +#define PCCR0_SDHC3_EN (1 << 3) +#define PCCR0_SDHC2_EN (1 << 4) +#define PCCR0_SDHC1_EN (1 << 5) +#define PCCR0_SDC_EN (1 << 6) +#define PCCR0_SAHARA_EN (1 << 7) +#define PCCR0_RTIC_EN (1 << 8) +#define PCCR0_RTC_EN (1 << 9) +#define PCCR0_PWM_EN (1 << 11) +#define PCCR0_OWIRE_EN (1 << 12) +#define PCCR0_MSHC_EN (1 << 13) +#define PCCR0_LCDC_EN (1 << 14) +#define PCCR0_KPP_EN (1 << 15) +#define PCCR0_IIM_EN (1 << 16) +#define PCCR0_I2C2_EN (1 << 17) +#define PCCR0_I2C1_EN (1 << 18) +#define PCCR0_GPT6_EN (1 << 19) +#define PCCR0_GPT5_EN (1 << 20) +#define PCCR0_GPT4_EN (1 << 21) +#define PCCR0_GPT3_EN (1 << 22) +#define PCCR0_GPT2_EN (1 << 23) +#define PCCR0_GPT1_EN (1 << 24) +#define PCCR0_GPIO_EN (1 << 25) +#define PCCR0_FEC_EN (1 << 26) +#define PCCR0_EMMA_EN (1 << 27) +#define PCCR0_DMA_EN (1 << 28) +#define PCCR0_CSPI3_EN (1 << 29) +#define PCCR0_CSPI2_EN (1 << 30) +#define PCCR0_CSPI1_EN (1 << 31) + +#define PCCR1_MSHC_BAUDEN (1 << 2) +#define PCCR1_NFC_BAUDEN (1 << 3) +#define PCCR1_SSI2_BAUDEN (1 << 4) +#define PCCR1_SSI1_BAUDEN (1 << 5) +#define PCCR1_H264_BAUDEN (1 << 6) +#define PCCR1_PERCLK4_EN (1 << 7) +#define PCCR1_PERCLK3_EN (1 << 8) +#define PCCR1_PERCLK2_EN (1 << 9) +#define PCCR1_PERCLK1_EN (1 << 10) +#define PCCR1_HCLK_USB (1 << 11) +#define PCCR1_HCLK_SLCDC (1 << 12) +#define PCCR1_HCLK_SAHARA (1 << 13) +#define PCCR1_HCLK_RTIC (1 << 14) +#define PCCR1_HCLK_LCDC (1 << 15) +#define PCCR1_HCLK_H264 (1 << 16) +#define PCCR1_HCLK_FEC (1 << 17) +#define PCCR1_HCLK_EMMA (1 << 18) +#define PCCR1_HCLK_EMI (1 << 19) +#define PCCR1_HCLK_DMA (1 << 20) +#define PCCR1_HCLK_CSI (1 << 21) +#define PCCR1_HCLK_BROM (1 << 22) +#define PCCR1_HCLK_ATA (1 << 23) +#define PCCR1_WDT_EN (1 << 24) +#define PCCR1_USB_EN (1 << 25) +#define PCCR1_UART6_EN (1 << 26) +#define PCCR1_UART5_EN (1 << 27) +#define PCCR1_UART4_EN (1 << 28) +#define PCCR1_UART3_EN (1 << 29) +#define PCCR1_UART2_EN (1 << 30) +#define PCCR1_UART1_EN (1 << 31) + +/* SDRAM Controller registers bitfields */ +#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0) +#define ESDCTL_BL (1 << 7) +#define ESDCTL_FP (1 << 8) +#define ESDCTL_PWDT(x) (((x) & 3) << 10) +#define ESDCTL_SREFR(x) (((x) & 7) << 13) +#define ESDCTL_DSIZ_16_UPPER (0 << 16) +#define ESDCTL_DSIZ_16_LOWER (1 << 16) +#define ESDCTL_DSIZ_32 (2 << 16) +#define ESDCTL_COL8 (0 << 20) +#define ESDCTL_COL9 (1 << 20) +#define ESDCTL_COL10 (2 << 20) +#define ESDCTL_ROW11 (0 << 24) +#define ESDCTL_ROW12 (1 << 24) +#define ESDCTL_ROW13 (2 << 24) +#define ESDCTL_ROW14 (3 << 24) +#define ESDCTL_ROW15 (4 << 24) +#define ESDCTL_SP (1 << 27) +#define ESDCTL_SMODE_NORMAL (0 << 28) +#define ESDCTL_SMODE_PRECHARGE (1 << 28) +#define ESDCTL_SMODE_AUTO_REF (2 << 28) +#define ESDCTL_SMODE_LOAD_MODE (3 << 28) +#define ESDCTL_SMODE_MAN_REF (4 << 28) +#define ESDCTL_SDE (1 << 31) + +#define ESDCFG_TRC(x) (((x) & 0xf) << 0) +#define ESDCFG_TRCD(x) (((x) & 0x7) << 4) +#define ESDCFG_TCAS(x) (((x) & 0x3) << 8) +#define ESDCFG_TRRD(x) (((x) & 0x3) << 10) +#define ESDCFG_TRAS(x) (((x) & 0x7) << 12) +#define ESDCFG_TWR (1 << 15) +#define ESDCFG_TMRD(x) (((x) & 0x3) << 16) +#define ESDCFG_TRP(x) (((x) & 0x3) << 18) +#define ESDCFG_TWTR (1 << 20) +#define ESDCFG_TXP(x) (((x) & 0x3) << 21) + +#define ESDMISC_RST (1 << 1) +#define ESDMISC_MDDREN (1 << 2) +#define ESDMISC_MDDR_DL_RST (1 << 3) +#define ESDMISC_MDDR_MDIS (1 << 4) +#define ESDMISC_LHD (1 << 5) +#define ESDMISC_MA10_SHARE (1 << 6) +#define ESDMISC_SDRAM_RDY (1 << 31) + +#define PC5_PF_I2C2_DATA (GPIO_PORTC | GPIO_OUT | GPIO_PF | 5) +#define PC6_PF_I2C2_CLK (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6) +#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7) +#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8) +#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9) +#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10) +#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11) +#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12) +#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13) + +#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0) +#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1) +#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2) +#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3) +#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4) +#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5) +#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6) +#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7) +#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8) +#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9) +#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10) +#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11) +#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12) +#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13) +#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14) +#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15) +#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16) +#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23) + +#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0) +#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1) +#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2) +#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3) +#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4) +#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6) +#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7) +#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8) +#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9) +#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10) +#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11) +#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12) +#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13) +#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14) +#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15) +#define PE18_PF_SD1_D0 (GPIO_PORTE | GPIO_PF | 18) +#define PE19_PF_SD1_D1 (GPIO_PORTE | GPIO_PF | 19) +#define PE20_PF_SD1_D2 (GPIO_PORTE | GPIO_PF | 20) +#define PE21_PF_SD1_D3 (GPIO_PORTE | GPIO_PF | 21) +#define PE22_PF_SD1_CMD (GPIO_PORTE | GPIO_PF | 22) +#define PE23_PF_SD1_CLK (GPIO_PORTE | GPIO_PF | 23) +#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4) +#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5) +#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6) +#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7) +#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8) +#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9) +#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17) +#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18) +#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24) +#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25) + +/* Clocksource Bitfields */ +#define TCTL_SWR (1 << 15) /* Software reset */ +#define TCTL_FRR (1 << 8) /* Freerun / restart */ +#define TCTL_CAP (3 << 6) /* Capture Edge */ +#define TCTL_OM (1 << 5) /* output mode */ +#define TCTL_IRQEN (1 << 4) /* interrupt enable */ +#define TCTL_CLKSOURCE 1 /* Clock source bit position */ +#define TCTL_TEN 1 /* Timer enable */ +#define TPRER_PRES 0xff /* Prescale */ +#define TSTAT_CAPT (1 << 1) /* Capture event */ +#define TSTAT_COMP 1 /* Compare event */ + +#define GPIO_PIN_MASK 0x1f + +#define GPIO_PORT_SHIFT 5 +#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT) + +#define GPIO_PORTA (PORTA << GPIO_PORT_SHIFT) +#define GPIO_PORTB (PORTB << GPIO_PORT_SHIFT) +#define GPIO_PORTC (PORTC << GPIO_PORT_SHIFT) +#define GPIO_PORTD (PORTD << GPIO_PORT_SHIFT) +#define GPIO_PORTE (PORTE << GPIO_PORT_SHIFT) +#define GPIO_PORTF (PORTF << GPIO_PORT_SHIFT) + +#define GPIO_OUT (1 << 8) +#define GPIO_IN (0 << 8) +#define GPIO_PUEN (1 << 9) + +#define GPIO_PF (1 << 10) +#define GPIO_AF (1 << 11) + +#define GPIO_OCR_SHIFT 12 +#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT) +#define GPIO_AIN (0 << GPIO_OCR_SHIFT) +#define GPIO_BIN (1 << GPIO_OCR_SHIFT) +#define GPIO_CIN (2 << GPIO_OCR_SHIFT) +#define GPIO_GPIO (3 << GPIO_OCR_SHIFT) + +#define GPIO_AOUT_SHIFT 14 +#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT) +#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT) + +#define GPIO_BOUT_SHIFT 16 +#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT) +#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT) + +#define IIM_STAT_BUSY (1 << 7) +#define IIM_STAT_PRGD (1 << 1) +#define IIM_STAT_SNSD (1 << 0) +#define IIM_ERR_PRGE (1 << 7) +#define IIM_ERR_WPE (1 << 6) +#define IIM_ERR_OPE (1 << 5) +#define IIM_ERR_RPE (1 << 4) +#define IIM_ERR_WLRE (1 << 3) +#define IIM_ERR_SNSE (1 << 2) +#define IIM_ERR_PARITYE (1 << 1) + +/* Definitions for i.MX27 TO2 */ +#define IIM0_MAC 5 +#define IIM0_SCC_KEY 11 +#define IIM1_SUID 1 + +#endif /* _IMX_REGS_H */ + -- cgit v1.3.1 From 47d19da4d3f9ac4787abe9dee32406478424be52 Mon Sep 17 00:00:00 2001 From: Ilya Yanok Date: Mon, 8 Jun 2009 04:12:46 +0400 Subject: serial_mx31: allow it to work with mx27 too and rename to serial_mxc UART hardware on i.MX27 is the same as on the i.MX31 so we just need to provide the driver with correct address of the registers. Signed-off-by: Ilya Yanok --- drivers/serial/Makefile | 2 +- drivers/serial/serial_mx31.c | 226 ------------------------------------ drivers/serial/serial_mxc.c | 247 ++++++++++++++++++++++++++++++++++++++++ include/configs/imx31_litekit.h | 2 +- include/configs/imx31_phycore.h | 2 +- include/configs/mx31ads.h | 2 +- include/configs/qong.h | 2 +- 7 files changed, 252 insertions(+), 231 deletions(-) delete mode 100644 drivers/serial/serial_mx31.c create mode 100644 drivers/serial/serial_mxc.c (limited to 'include') diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index ab5d5654d62..64882a2e8ef 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -41,7 +41,7 @@ COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o -COBJS-$(CONFIG_MX31_UART) += serial_mx31.o +COBJS-$(CONFIG_MXC_UART) += serial_mxc.o COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o COBJS-$(CONFIG_PL011_SERIAL) += serial_pl01x.o diff --git a/drivers/serial/serial_mx31.c b/drivers/serial/serial_mx31.c deleted file mode 100644 index 7c0682ad777..00000000000 --- a/drivers/serial/serial_mx31.c +++ /dev/null @@ -1,226 +0,0 @@ -/* - * (c) 2007 Sascha Hauer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - * - */ - -#include -#include - -#define __REG(x) (*((volatile u32 *)(x))) - -#ifdef CONFIG_SYS_MX31_UART1 -#define UART_PHYS 0x43f90000 -#elif defined(CONFIG_SYS_MX31_UART2) -#define UART_PHYS 0x43f94000 -#elif defined(CONFIG_SYS_MX31_UART3) -#define UART_PHYS 0x5000c000 -#elif defined(CONFIG_SYS_MX31_UART4) -#define UART_PHYS 0x43fb0000 -#elif defined(CONFIG_SYS_MX31_UART5) -#define UART_PHYS 0x43fb4000 -#else -#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" -#endif - -/* Register definitions */ -#define URXD 0x0 /* Receiver Register */ -#define UTXD 0x40 /* Transmitter Register */ -#define UCR1 0x80 /* Control Register 1 */ -#define UCR2 0x84 /* Control Register 2 */ -#define UCR3 0x88 /* Control Register 3 */ -#define UCR4 0x8c /* Control Register 4 */ -#define UFCR 0x90 /* FIFO Control Register */ -#define USR1 0x94 /* Status Register 1 */ -#define USR2 0x98 /* Status Register 2 */ -#define UESC 0x9c /* Escape Character Register */ -#define UTIM 0xa0 /* Escape Timer Register */ -#define UBIR 0xa4 /* BRM Incremental Register */ -#define UBMR 0xa8 /* BRM Modulator Register */ -#define UBRC 0xac /* Baud Rate Count Register */ -#define UTS 0xb4 /* UART Test Register (mx31) */ - -/* UART Control Register Bit Fields.*/ -#define URXD_CHARRDY (1<<15) -#define URXD_ERR (1<<14) -#define URXD_OVRRUN (1<<13) -#define URXD_FRMERR (1<<12) -#define URXD_BRK (1<<11) -#define URXD_PRERR (1<<10) -#define URXD_RX_DATA (0xFF) -#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ -#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ -#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ -#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ -#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ -#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ -#define UCR1_IREN (1<<7) /* Infrared interface enable */ -#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ -#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ -#define UCR1_SNDBRK (1<<4) /* Send break */ -#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ -#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ -#define UCR1_DOZE (1<<1) /* Doze */ -#define UCR1_UARTEN (1<<0) /* UART enabled */ -#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ -#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ -#define UCR2_CTSC (1<<13) /* CTS pin control */ -#define UCR2_CTS (1<<12) /* Clear to send */ -#define UCR2_ESCEN (1<<11) /* Escape enable */ -#define UCR2_PREN (1<<8) /* Parity enable */ -#define UCR2_PROE (1<<7) /* Parity odd/even */ -#define UCR2_STPB (1<<6) /* Stop */ -#define UCR2_WS (1<<5) /* Word size */ -#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ -#define UCR2_TXEN (1<<2) /* Transmitter enabled */ -#define UCR2_RXEN (1<<1) /* Receiver enabled */ -#define UCR2_SRST (1<<0) /* SW reset */ -#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ -#define UCR3_PARERREN (1<<12) /* Parity enable */ -#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ -#define UCR3_DSR (1<<10) /* Data set ready */ -#define UCR3_DCD (1<<9) /* Data carrier detect */ -#define UCR3_RI (1<<8) /* Ring indicator */ -#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ -#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ -#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ -#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ -#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ -#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ -#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ -#define UCR3_BPEN (1<<0) /* Preset registers enable */ -#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ -#define UCR4_INVR (1<<9) /* Inverted infrared reception */ -#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ -#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ -#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ -#define UCR4_IRSC (1<<5) /* IR special case */ -#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ -#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ -#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ -#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ -#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ -#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ -#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ -#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ -#define USR1_RTSS (1<<14) /* RTS pin status */ -#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ -#define USR1_RTSD (1<<12) /* RTS delta */ -#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ -#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ -#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ -#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ -#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ -#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ -#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ -#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ -#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ -#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ -#define USR2_IDLE (1<<12) /* Idle condition */ -#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ -#define USR2_WAKE (1<<7) /* Wake */ -#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ -#define USR2_TXDC (1<<3) /* Transmitter complete */ -#define USR2_BRCD (1<<2) /* Break condition */ -#define USR2_ORE (1<<1) /* Overrun error */ -#define USR2_RDR (1<<0) /* Recv data ready */ -#define UTS_FRCPERR (1<<13) /* Force parity error */ -#define UTS_LOOP (1<<12) /* Loop tx and rx */ -#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ -#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ -#define UTS_TXFULL (1<<4) /* TxFIFO full */ -#define UTS_RXFULL (1<<3) /* RxFIFO full */ -#define UTS_SOFTRST (1<<0) /* Software reset */ - -DECLARE_GLOBAL_DATA_PTR; - -void serial_setbrg (void) -{ - u32 clk = mx31_get_ipg_clk(); - - if (!gd->baudrate) - gd->baudrate = CONFIG_BAUDRATE; - - __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ - __REG(UART_PHYS + UBIR) = 0xf; - __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); - -} - -int serial_getc (void) -{ - while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); - return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ -} - -void serial_putc (const char c) -{ - __REG(UART_PHYS + UTXD) = c; - - /* wait for transmitter to be ready */ - while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); - - /* If \n, also do \r */ - if (c == '\n') - serial_putc ('\r'); -} - -/* - * Test whether a character is in the RX buffer - */ -int serial_tstc (void) -{ - /* If receive fifo is empty, return false */ - if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) - return 0; - return 1; -} - -void -serial_puts (const char *s) -{ - while (*s) { - serial_putc (*s++); - } -} - -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * - */ -int serial_init (void) -{ - __REG(UART_PHYS + UCR1) = 0x0; - __REG(UART_PHYS + UCR2) = 0x0; - - while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); - - __REG(UART_PHYS + UCR3) = 0x0704; - __REG(UART_PHYS + UCR4) = 0x8000; - __REG(UART_PHYS + UESC) = 0x002b; - __REG(UART_PHYS + UTIM) = 0x0; - - __REG(UART_PHYS + UTS) = 0x0; - - serial_setbrg(); - - __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; - - __REG(UART_PHYS + UCR1) = UCR1_UARTEN; - - return 0; -} diff --git a/drivers/serial/serial_mxc.c b/drivers/serial/serial_mxc.c new file mode 100644 index 00000000000..acc5b7d83bd --- /dev/null +++ b/drivers/serial/serial_mxc.c @@ -0,0 +1,247 @@ +/* + * (c) 2007 Sascha Hauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include +#ifdef CONFIG_MX31 +#include +#else +#include +#include +#endif + +#define __REG(x) (*((volatile u32 *)(x))) + +#ifdef CONFIG_SYS_MX31_UART1 +#define UART_PHYS 0x43f90000 +#elif defined(CONFIG_SYS_MX31_UART2) +#define UART_PHYS 0x43f94000 +#elif defined(CONFIG_SYS_MX31_UART3) +#define UART_PHYS 0x5000c000 +#elif defined(CONFIG_SYS_MX31_UART4) +#define UART_PHYS 0x43fb0000 +#elif defined(CONFIG_SYS_MX31_UART5) +#define UART_PHYS 0x43fb4000 +#elif defined(CONFIG_SYS_MX27_UART1) +#define UART_PHYS 0x1000a000 +#elif defined(CONFIG_SYS_MX27_UART2) +#define UART_PHYS 0x1000b000 +#elif defined(CONFIG_SYS_MX27_UART3) +#define UART_PHYS 0x1000c000 +#elif defined(CONFIG_SYS_MX27_UART4) +#define UART_PHYS 0x1000d000 +#elif defined(CONFIG_SYS_MX27_UART5) +#define UART_PHYS 0x1001b000 +#elif defined(CONFIG_SYS_MX27_UART6) +#define UART_PHYS 0x1001c000 +#else +#error "define CONFIG_SYS_MX31_UARTx to use the mx31 UART driver" +#endif + +/* Register definitions */ +#define URXD 0x0 /* Receiver Register */ +#define UTXD 0x40 /* Transmitter Register */ +#define UCR1 0x80 /* Control Register 1 */ +#define UCR2 0x84 /* Control Register 2 */ +#define UCR3 0x88 /* Control Register 3 */ +#define UCR4 0x8c /* Control Register 4 */ +#define UFCR 0x90 /* FIFO Control Register */ +#define USR1 0x94 /* Status Register 1 */ +#define USR2 0x98 /* Status Register 2 */ +#define UESC 0x9c /* Escape Character Register */ +#define UTIM 0xa0 /* Escape Timer Register */ +#define UBIR 0xa4 /* BRM Incremental Register */ +#define UBMR 0xa8 /* BRM Modulator Register */ +#define UBRC 0xac /* Baud Rate Count Register */ +#define UTS 0xb4 /* UART Test Register (mx31) */ + +/* UART Control Register Bit Fields.*/ +#define URXD_CHARRDY (1<<15) +#define URXD_ERR (1<<14) +#define URXD_OVRRUN (1<<13) +#define URXD_FRMERR (1<<12) +#define URXD_BRK (1<<11) +#define URXD_PRERR (1<<10) +#define URXD_RX_DATA (0xFF) +#define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ +#define UCR1_ADBR (1<<14) /* Auto detect baud rate */ +#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ +#define UCR1_IDEN (1<<12) /* Idle condition interrupt */ +#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ +#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ +#define UCR1_IREN (1<<7) /* Infrared interface enable */ +#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ +#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ +#define UCR1_SNDBRK (1<<4) /* Send break */ +#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ +#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ +#define UCR1_DOZE (1<<1) /* Doze */ +#define UCR1_UARTEN (1<<0) /* UART enabled */ +#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ +#define UCR2_IRTS (1<<14) /* Ignore RTS pin */ +#define UCR2_CTSC (1<<13) /* CTS pin control */ +#define UCR2_CTS (1<<12) /* Clear to send */ +#define UCR2_ESCEN (1<<11) /* Escape enable */ +#define UCR2_PREN (1<<8) /* Parity enable */ +#define UCR2_PROE (1<<7) /* Parity odd/even */ +#define UCR2_STPB (1<<6) /* Stop */ +#define UCR2_WS (1<<5) /* Word size */ +#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ +#define UCR2_TXEN (1<<2) /* Transmitter enabled */ +#define UCR2_RXEN (1<<1) /* Receiver enabled */ +#define UCR2_SRST (1<<0) /* SW reset */ +#define UCR3_DTREN (1<<13) /* DTR interrupt enable */ +#define UCR3_PARERREN (1<<12) /* Parity enable */ +#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ +#define UCR3_DSR (1<<10) /* Data set ready */ +#define UCR3_DCD (1<<9) /* Data carrier detect */ +#define UCR3_RI (1<<8) /* Ring indicator */ +#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ +#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ +#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ +#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ +#define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ +#define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ +#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ +#define UCR3_BPEN (1<<0) /* Preset registers enable */ +#define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ +#define UCR4_INVR (1<<9) /* Inverted infrared reception */ +#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ +#define UCR4_WKEN (1<<7) /* Wake interrupt enable */ +#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ +#define UCR4_IRSC (1<<5) /* IR special case */ +#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ +#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ +#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ +#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ +#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ +#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ +#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ +#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ +#define USR1_RTSS (1<<14) /* RTS pin status */ +#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ +#define USR1_RTSD (1<<12) /* RTS delta */ +#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ +#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ +#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ +#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ +#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ +#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ +#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ +#define USR2_ADET (1<<15) /* Auto baud rate detect complete */ +#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ +#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ +#define USR2_IDLE (1<<12) /* Idle condition */ +#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ +#define USR2_WAKE (1<<7) /* Wake */ +#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ +#define USR2_TXDC (1<<3) /* Transmitter complete */ +#define USR2_BRCD (1<<2) /* Break condition */ +#define USR2_ORE (1<<1) /* Overrun error */ +#define USR2_RDR (1<<0) /* Recv data ready */ +#define UTS_FRCPERR (1<<13) /* Force parity error */ +#define UTS_LOOP (1<<12) /* Loop tx and rx */ +#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ +#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ +#define UTS_TXFULL (1<<4) /* TxFIFO full */ +#define UTS_RXFULL (1<<3) /* RxFIFO full */ +#define UTS_SOFTRST (1<<0) /* Software reset */ + +DECLARE_GLOBAL_DATA_PTR; + +void serial_setbrg (void) +{ +#ifdef CONFIG_MX31 + u32 clk = mx31_get_ipg_clk(); +#else + u32 clk = imx_get_perclk1(); +#endif + + if (!gd->baudrate) + gd->baudrate = CONFIG_BAUDRATE; + + __REG(UART_PHYS + UFCR) = 4 << 7; /* divide input clock by 2 */ + __REG(UART_PHYS + UBIR) = 0xf; + __REG(UART_PHYS + UBMR) = clk / (2 * gd->baudrate); + +} + +int serial_getc (void) +{ + while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); + return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */ +} + +void serial_putc (const char c) +{ + __REG(UART_PHYS + UTXD) = c; + + /* wait for transmitter to be ready */ + while(!(__REG(UART_PHYS + UTS) & UTS_TXEMPTY)); + + /* If \n, also do \r */ + if (c == '\n') + serial_putc ('\r'); +} + +/* + * Test whether a character is in the RX buffer + */ +int serial_tstc (void) +{ + /* If receive fifo is empty, return false */ + if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY) + return 0; + return 1; +} + +void +serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +/* + * Initialise the serial port with the given baudrate. The settings + * are always 8 data bits, no parity, 1 stop bit, no start bits. + * + */ +int serial_init (void) +{ + __REG(UART_PHYS + UCR1) = 0x0; + __REG(UART_PHYS + UCR2) = 0x0; + + while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST)); + + __REG(UART_PHYS + UCR3) = 0x0704; + __REG(UART_PHYS + UCR4) = 0x8000; + __REG(UART_PHYS + UESC) = 0x002b; + __REG(UART_PHYS + UTIM) = 0x0; + + __REG(UART_PHYS + UTS) = 0x0; + + serial_setbrg(); + + __REG(UART_PHYS + UCR2) = UCR2_WS | UCR2_IRTS | UCR2_RXEN | UCR2_TXEN | UCR2_SRST; + + __REG(UART_PHYS + UCR1) = UCR1_UARTEN; + + return 0; +} diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 9ac6eec3b45..74f54c0c785 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -60,7 +60,7 @@ * Hardware drivers */ -#define CONFIG_MX31_UART 1 +#define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 #define CONFIG_HARD_SPI 1 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index cbc0b9259a4..cb42a7cc96b 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -64,7 +64,7 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0xfe -#define CONFIG_MX31_UART 1 +#define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 /* allow to overwrite serial and ethaddr */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index c31c06acc42..363ea1ba1fe 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -57,7 +57,7 @@ * Hardware drivers */ -#define CONFIG_MX31_UART 1 +#define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 #define CONFIG_HARD_SPI 1 diff --git a/include/configs/qong.h b/include/configs/qong.h index 7e6718503ee..64d0214e273 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -49,7 +49,7 @@ * Hardware drivers */ -#define CONFIG_MX31_UART 1 +#define CONFIG_MXC_UART 1 #define CONFIG_SYS_MX31_UART1 1 /* FPGA */ -- cgit v1.3.1 From 46937b27427688a56bf7f5944a92d962dc43c3fa Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 17 May 2009 00:58:36 +0200 Subject: integratorap/cp: use cfi driver Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Acked-by: Peter Pearse --- board/armltd/integratorap/Makefile | 1 - board/armltd/integratorap/flash.c | 473 ------------------------------- board/armltd/integratorcp/Makefile | 1 - board/armltd/integratorcp/flash.c | 564 ------------------------------------- include/configs/integratorap.h | 8 +- include/configs/integratorcp.h | 4 +- 6 files changed, 7 insertions(+), 1044 deletions(-) delete mode 100644 board/armltd/integratorap/flash.c delete mode 100644 board/armltd/integratorcp/flash.c (limited to 'include') diff --git a/board/armltd/integratorap/Makefile b/board/armltd/integratorap/Makefile index 1af37f3f877..da82f5c0e7b 100644 --- a/board/armltd/integratorap/Makefile +++ b/board/armltd/integratorap/Makefile @@ -32,7 +32,6 @@ LIB = $(obj)lib$(BOARD).a SOBJS-y := lowlevel_init.o COBJS-y := integratorap.o -COBJS-y += flash.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += timer.o diff --git a/board/armltd/integratorap/flash.c b/board/armltd/integratorap/flash.c deleted file mode 100644 index 0492be76201..00000000000 --- a/board/armltd/integratorap/flash.c +++ /dev/null @@ -1,473 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - OrgDef *pOrgDef; - - pOrgDef = OrgIntel_28F256L18T; - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start, last; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - - start = get_timer (0); - last = start; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return (2); - } - flash_unprotect_sectors (addr); - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/armltd/integratorcp/Makefile b/board/armltd/integratorcp/Makefile index 5e3c6468e8a..76a85d936cb 100644 --- a/board/armltd/integratorcp/Makefile +++ b/board/armltd/integratorcp/Makefile @@ -28,7 +28,6 @@ LIB = $(obj)lib$(BOARD).a SOBJS := lowlevel_init.o COBJS := integratorcp.o -COBJS += flash.o COBJS += timer.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/board/armltd/integratorcp/flash.c b/board/armltd/integratorcp/flash.c deleted file mode 100644 index 5059daeec92..00000000000 --- a/board/armltd/integratorcp/flash.c +++ /dev/null @@ -1,564 +0,0 @@ -/* - * (C) Copyright 2004 - * Xiaogeng (Shawn) Jin, Agilent Technologies, xiaogeng_jin@agilent.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define DEBUG - -#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#define FLASH_PORT_WIDTH32 -#undef FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - -/* CP control register base address */ -#define CPCR_BASE 0xCB000000 -#define CPCR_EXTRABANK 0x8 -#define CPCR_FLASHSIZE 0x4 -#define CPCR_FLWREN 0x2 -#define CPCR_FLVPPEN 0x1 - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); - -/*----------------------------------------------------------------------- - */ -unsigned long flash_init (void) -{ - int i, nbanks; - ulong size = 0; - vu_long *cpcr = (vu_long *)CPCR_BASE; - - /* Check if there is an extra bank of flash */ - if (cpcr[1] & CPCR_EXTRABANK) - nbanks = 2; - else - nbanks = 1; - - if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS) - nbanks = CONFIG_SYS_MAX_FLASH_BANKS; - - /* Enable flash write */ - cpcr[1] |= 3; - - for (i = 0; i < nbanks; i++) { - flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]); - size += flash_info[i].size; - } - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]); -#endif - -#ifdef CONFIG_ENV_IS_IN_FLASH - /* ENV protection ON */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); -#endif - - /* Protect SIB (0x24800000) and bootMonitor (0x24c00000) */ - flash_protect (FLAG_PROTECT_SET, - flash_info[0].start[62], - flash_info[0].start[63] + PHYS_FLASH_SECT_SIZE - 1, - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - /* Integrator CP board uses 28F640J3C or 28F128J3C parts, - * which have the same device id numbers as 28F640J3A or - * 28F128J3A - */ - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - case FLASH_28F640J3A: - printf ("FLASH 28F640J3C\n"); - break; - case FLASH_28F128J3A: - printf ("FLASH 28F128J3C\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - vu_long *cpcr = (vu_long *)CPCR_BASE; - int nsects; - - /* Check the flash size */ - if (cpcr[1] & CPCR_FLASHSIZE) - nsects = 128; - else - nsects = 64; - - if (nsects > CONFIG_SYS_MAX_FLASH_SECT) - nsects = CONFIG_SYS_MAX_FLASH_SECT; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - case (FPW) (INTEL_ID_28F640J3A): - info->flash_id += FLASH_28F640J3A; - info->sector_count = nsects; - info->size = nsects * PHYS_FLASH_SECT_SIZE; - break; - - case (FPW) (INTEL_ID_28F128J3A): - info->flash_id += FLASH_28F128J3A; - info->sector_count = nsects; - info->size = nsects * PHYS_FLASH_SECT_SIZE; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ - FPW status; - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; - - reset_timer_masked(); - while (((status = *addr) & (FPW)0x00800080) != 0x00800080) { - if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf("Timeout"); - break; - } - } - - *addr = (FPW) 0x00FF00FF; -} - - -/*----------------------------------------------------------------------- - */ -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* flash_unprotect_sectors (addr); */ - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - *addr = (FPW) 0x00500050; /* clear status register */ - *addr = (FPW) 0x00200020; /* erase setup */ - *addr = (FPW) 0x00D000D0; /* erase confirm */ - mb(); - - udelay(1000); /* Let's wait 1 ms */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - *addr = (FPW)0x00700070; - status = *addr; - if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) { - /* erase suspended? Resume it */ - reset_timer_masked(); - *addr = (FPW) 0x00D000D0; - } else { -#ifdef DEBUG - printf ("Timeout,0x%08lx\n", status); -#else - printf("Timeout\n"); -#endif - - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF; /* reset to read mode */ - rcode = 1; - break; - } - } - } - - *addr = (FPW) 0x00FF00FF; /* resest to read mode */ - printf (" done\n"); - } - } - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* flash_unprotect_sectors (addr); */ - - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - mb(); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) { -#ifdef DEBUG - *addr = (FPW) 0x00700070; - status = *addr; - printf("## status=0x%08lx, addr=0x%p\n", status, addr); -#endif - *addr = (FPW) 0x00500050; /* clear status register cmd */ - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (1); - } - } - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 09270ff0a80..e0e82583410 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -122,21 +122,21 @@ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CONFIG_SYS_FLASH_BASE 0x24000000 /*----------------------------------------------------------------------- * FLASH and environment organization */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ /* timeout values are in ticks */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ #define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_ENV_SIZE 32768 +#define CONFIG_ENV_SIZE 32768 -#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE) /*----------------------------------------------------------------------- * PCI definitions diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index b4219d03e12..e38d569108b 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -155,9 +155,11 @@ SIB at Block62 End Block62 address 0x24f80000 */ #define CONFIG_SYS_FLASH_BASE 0x24000000 +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT 64 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ #define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ #define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ -- cgit v1.3.1 From 5710de45808eb8f1cc34b51dc3e67e2422113249 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Sat, 30 May 2009 01:13:33 +0530 Subject: spi: Add Marvell Kirkwood SPI driver This patch adds a SPI driver for the Marvell Kirkwood SoC's. Signed-off-by: Prafulla Wadaskar --- drivers/spi/Makefile | 1 + drivers/spi/kirkwood_spi.c | 185 ++++++++++++++++++++++++++++++++++++ include/asm-arm/arch-kirkwood/spi.h | 56 +++++++++++ 3 files changed, 242 insertions(+) create mode 100644 drivers/spi/kirkwood_spi.c create mode 100644 include/asm-arm/arch-kirkwood/spi.h (limited to 'include') diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 1350f3e0bff..7ffa47db5c3 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libspi.a COBJS-$(CONFIG_ATMEL_DATAFLASH_SPI) += atmel_dataflash_spi.o COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o +COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c new file mode 100644 index 00000000000..a1c307059c3 --- /dev/null +++ b/drivers/spi/kirkwood_spi.c @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Derived from drivers/spi/mpc8xxx_spi.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include + +static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE; + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct spi_slave *slave; + u32 data; + u32 kwspi_mpp_config[] = { + MPP0_GPIO, + MPP7_SPI_SCn, + 0 + }; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + writel(~KWSPI_CSN_ACT | KWSPI_SMEMRDY, &spireg->ctrl); + + /* calculate spi clock prescaller using max_hz */ + data = ((CONFIG_SYS_TCLK / 2) / max_hz) & KWSPI_CLKPRESCL_MASK; + data |= 0x10; + + /* program spi clock prescaller using max_hz */ + writel(KWSPI_ADRLEN_3BYTE | data, &spireg->cfg); + debug("data = 0x%08x \n", data); + + writel(KWSPI_SMEMRDIRQ, &spireg->irq_cause); + writel(KWSPI_IRQMASK, spireg->irq_mask); + + /* program mpp registers to select SPI_CSn */ + if (cs) { + kwspi_mpp_config[0] = MPP0_GPIO; + kwspi_mpp_config[1] = MPP7_SPI_SCn; + } else { + kwspi_mpp_config[0] = MPP0_SPI_SCn; + kwspi_mpp_config[1] = MPP7_GPO; + } + kirkwood_mpp_conf(kwspi_mpp_config); + + return slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free(slave); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ +} + +#ifndef CONFIG_SPI_CS_IS_VALID +/* + * you can define this function board specific + * define above CONFIG in board specific config file and + * provide the function in board specific src file + */ +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return (bus == 0 && (cs == 0 || cs == 1)); +} +#endif + +void spi_cs_activate(struct spi_slave *slave) +{ + writel(readl(&spireg->ctrl) | KWSPI_IRQUNMASK, &spireg->ctrl); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + writel(readl(&spireg->ctrl) & KWSPI_IRQMASK, &spireg->ctrl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + unsigned int tmpdout, tmpdin; + int tm, isread = 0; + + debug("spi_xfer: slave %u:%u dout %08X din %08X bitlen %u\n", + slave->bus, slave->cs, dout, din, bitlen); + + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + + /* + * handle data in 8-bit chunks + * TBD: 2byte xfer mode to be enabled + */ + writel(((readl(&spireg->cfg) & ~KWSPI_XFERLEN_MASK) | + KWSPI_XFERLEN_1BYTE), &spireg->cfg); + + while (bitlen > 4) { + debug("loopstart bitlen %d\n", bitlen); + tmpdout = 0; + + /* Shift data so it's msb-justified */ + if (dout) + tmpdout = *(u32 *) dout & 0x0ff; + + writel(~KWSPI_SMEMRDIRQ, &spireg->irq_cause); + writel(tmpdout, &spireg->dout); /* Write the data out */ + debug("*** spi_xfer: ... %08x written, bitlen %d\n", + tmpdout, bitlen); + + /* + * Wait for SPI transmit to get out + * or time out (1 second = 1000 ms) + * The NE event must be read and cleared first + */ + for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { + if (readl(&spireg->irq_cause) & KWSPI_SMEMRDIRQ) { + isread = 1; + tmpdin = readl(&spireg->din); + debug + ("spi_xfer: din %08x..%08x read\n", + din, tmpdin); + + if (din) { + *((u8 *) din) = (u8) tmpdin; + din += 1; + } + if (dout) + dout += 1; + bitlen -= 8; + } + if (isread) + break; + } + if (tm >= KWSPI_TIMEOUT) + printf("*** spi_xfer: Time out during SPI transfer\n"); + + debug("loopend bitlen %d\n", bitlen); + } + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return 0; +} diff --git a/include/asm-arm/arch-kirkwood/spi.h b/include/asm-arm/arch-kirkwood/spi.h new file mode 100644 index 00000000000..1d5043f94f7 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/spi.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Derived from drivers/spi/mpc8xxx_spi.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __KW_SPI_H__ +#define __KW_SPI_H__ + +/* SPI Registers on kirkwood SOC */ +struct kwspi_registers { + u32 ctrl; /* 0x10600 */ + u32 cfg; /* 0x10604 */ + u32 dout; /* 0x10608 */ + u32 din; /* 0x1060c */ + u32 irq_cause; /* 0x10610 */ + u32 irq_mask; /* 0x10614 */ +}; + +#define KWSPI_CLKPRESCL_MASK 0x1f +#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */ +#define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ +#define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ +#define KWSPI_IRQMASK 0 /* mask SPI interrupt */ +#define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ +#define KWSPI_XFERLEN_1BYTE 0 +#define KWSPI_XFERLEN_2BYTE (1 << 5) +#define KWSPI_XFERLEN_MASK (1 << 5) +#define KWSPI_ADRLEN_1BYTE 0 +#define KWSPI_ADRLEN_2BYTE 1 << 8 +#define KWSPI_ADRLEN_3BYTE 2 << 8 +#define KWSPI_ADRLEN_4BYTE 3 << 8 +#define KWSPI_ADRLEN_MASK 3 << 8 +#define KWSPI_TIMEOUT 10000 + +#endif /* __KW_SPI_H__ */ -- cgit v1.3.1 From 9c8c706c92e53433a871a563946c38075d76504d Mon Sep 17 00:00:00 2001 From: Matthias Ludwig Date: Sat, 20 Jun 2009 11:01:50 +0200 Subject: OMAP3EVM: fix typo. replace CS6 by CS5, no functionality change Signed-off-by: Matthias Ludwig --- board/omap3/evm/evm.c | 16 ++++++++-------- include/asm-arm/arch-omap3/cpu.h | 5 +++-- 2 files changed, 11 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/board/omap3/evm/evm.c b/board/omap3/evm/evm.c index c008c2e4aa4..5fd5efad9c2 100644 --- a/board/omap3/evm/evm.c +++ b/board/omap3/evm/evm.c @@ -92,17 +92,17 @@ void set_muxconf_regs(void) static void setup_net_chip(void) { gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE; - gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE; + gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE; ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; /* Configure GPMC registers */ - writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1); - writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2); - writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3); - writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4); - writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5); - writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6); - writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7); + writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1); + writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2); + writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3); + writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4); + writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5); + writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6); + writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7); /* Enable off mode for NWE in PADCONF_GPMC_NWE register */ writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index c544e0c5d3a..a4ce45ab2c3 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -84,9 +84,10 @@ typedef struct ctrl_id { /* GPMC CS3/cs4/cs6 not avaliable */ #define GPMC_BASE (OMAP34XX_GPMC_BASE) #define GPMC_CONFIG_CS0 0x60 -#define GPMC_CONFIG_CS6 0x150 +#define GPMC_CONFIG_CS5 0x150 + #define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0) -#define GPMC_CONFIG_CS6_BASE (GPMC_BASE + GPMC_CONFIG_CS6) +#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5) #define GPMC_CONFIG_WP 0x10 #define GPMC_CONFIG_WIDTH 0x30 -- cgit v1.3.1 From 5c3d5817e5e68b828c165c501c215e793dc63aac Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Sat, 20 Jun 2009 11:01:52 +0200 Subject: arm: generic cache.h for ARM architectures This patch is required for Kirkwood SoC support may be used by other ARM architectures Signed-off-by: Prafulla Wadaskar --- include/asm-arm/cache.h | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 include/asm-arm/cache.h (limited to 'include') diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h new file mode 100644 index 00000000000..248240bef0a --- /dev/null +++ b/include/asm-arm/cache.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#include + +/* + * Invalidate L2 Cache using co-proc instruction + */ +static inline void invalidate_l2_cache(void) +{ + unsigned int val=0; + + asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); + isb(); +} +#endif /* _ASM_CACHE_H */ -- cgit v1.3.1 From 4efb77d41f9c5d93f0f92dda60e742023fa03c72 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Sat, 20 Jun 2009 11:01:53 +0200 Subject: arm: Kirkwood: Basic SOCs support Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon Michael Blostein Acked-by: Stefan Rose Signed-off-by: Prafulla Wadaskar --- cpu/arm926ejs/kirkwood/Makefile | 49 +++++ cpu/arm926ejs/kirkwood/cpu.c | 315 ++++++++++++++++++++++++++++++ cpu/arm926ejs/kirkwood/dram.c | 58 ++++++ cpu/arm926ejs/kirkwood/mpp.c | 80 ++++++++ cpu/arm926ejs/kirkwood/timer.c | 168 ++++++++++++++++ drivers/serial/serial.c | 3 + include/asm-arm/arch-kirkwood/cpu.h | 159 +++++++++++++++ include/asm-arm/arch-kirkwood/kirkwood.h | 69 +++++++ include/asm-arm/arch-kirkwood/kw88f6192.h | 37 ++++ include/asm-arm/arch-kirkwood/kw88f6281.h | 37 ++++ include/asm-arm/arch-kirkwood/mpp.h | 303 ++++++++++++++++++++++++++++ 11 files changed, 1278 insertions(+) create mode 100644 cpu/arm926ejs/kirkwood/Makefile create mode 100644 cpu/arm926ejs/kirkwood/cpu.c create mode 100644 cpu/arm926ejs/kirkwood/dram.c create mode 100644 cpu/arm926ejs/kirkwood/mpp.c create mode 100644 cpu/arm926ejs/kirkwood/timer.c create mode 100644 include/asm-arm/arch-kirkwood/cpu.h create mode 100644 include/asm-arm/arch-kirkwood/kirkwood.h create mode 100644 include/asm-arm/arch-kirkwood/kw88f6192.h create mode 100644 include/asm-arm/arch-kirkwood/kw88f6281.h create mode 100644 include/asm-arm/arch-kirkwood/mpp.h (limited to 'include') diff --git a/cpu/arm926ejs/kirkwood/Makefile b/cpu/arm926ejs/kirkwood/Makefile new file mode 100644 index 00000000000..d73e2104eb7 --- /dev/null +++ b/cpu/arm926ejs/kirkwood/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor +# Written-by: Prafulla Wadaskar +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y = dram.o +COBJS-y += cpu.o +COBJS-y += mpp.o +COBJS-y += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c new file mode 100644 index 00000000000..194ba1c85df --- /dev/null +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#define BUFLEN 16 + +void reset_cpu(unsigned long ignored) +{ + struct kwcpu_registers *cpureg = + (struct kwcpu_registers *)KW_CPU_REG_BASE; + + writel(readl(&cpureg->rstoutn_mask) | (1 << 2), + &cpureg->rstoutn_mask); + writel(readl(&cpureg->sys_soft_rst) | 1, + &cpureg->sys_soft_rst); + while (1) ; +} + +/* + * Generates Ramdom hex number reading some time varient system registers + * and using md5 algorithm + */ +unsigned char get_random_hex(void) +{ + int i; + u32 inbuf[BUFLEN]; + u8 outbuf[BUFLEN]; + + /* + * in case of 88F6281/88F6192 A0, + * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470 + * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are reserved regs and + * Does not have names at this moment (no errata available) + */ + writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478); + for (i = 0; i < BUFLEN; i++) { + inbuf[i] = readl(KW_REG_UNDOC_0x1470); + } + md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf); + return outbuf[outbuf[7] % 0x0f]; +} + +/* + * Window Size + * Used with the Base register to set the address window size and location. + * Must be programmed from LSB to MSB as sequence of ones followed by + * sequence of zeros. The number of ones specifies the size of the window in + * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). + * NOTE: A value of 0x0 specifies 64-KByte size. + */ +static unsigned int kw_winctrl_calcsize(unsigned int sizeval) +{ + int i; + unsigned int j = 0; + u32 val = sizeval >> 1; + + for (i = 0; val > 0x10000; i++) { + j |= (1 << i); + val = val >> 1; + } + return (0x0000ffff & j); +} + +/* prepares data to be loaded in win_Ctrl register */ +#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) + +/* + * kw_config_adr_windows - Configure address Windows + * + * There are 8 address windows supported by Kirkwood Soc to addess different + * devices. Each window can be configured for size, BAR and remap addr + * Below configuration is standard for most of the cases + * + * If remap function not used, remap_lo must be set as base + * + * Reference Documentation: + * Mbus-L to Mbus Bridge Registers Configuration. + * (Sec 25.1 and 25.3 of Datasheet) + */ +int kw_config_adr_windows(void) +{ + struct kwwin_registers *winregs = + (struct kwwin_registers *)KW_CPU_WIN_BASE; + + /* Window 0: PCIE MEM address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 256, KWCPU_TARGET_PCIE, + KWCPU_ATTR_PCIE_MEM, KWCPU_WIN_ENABLE), &winregs[0].ctrl); + + writel(KW_DEFADR_PCI_MEM, &winregs[0].base); + writel(KW_DEFADR_PCI_MEM, &winregs[0].remap_lo); + writel(0x0, &winregs[0].remap_hi); + + /* Window 1: PCIE IO address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_PCIE, + KWCPU_ATTR_PCIE_IO, KWCPU_WIN_ENABLE), &winregs[1].ctrl); + writel(KW_DEFADR_PCI_IO, &winregs[1].base); + writel(KW_DEFADR_PCI_IO_REMAP, &winregs[1].remap_lo); + writel(0x0, &winregs[1].remap_hi); + + /* Window 2: NAND Flash address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, + KWCPU_ATTR_NANDFLASH, KWCPU_WIN_ENABLE), &winregs[2].ctrl); + writel(KW_DEFADR_NANDF, &winregs[2].base); + writel(KW_DEFADR_NANDF, &winregs[2].remap_lo); + writel(0x0, &winregs[2].remap_hi); + + /* Window 3: SPI Flash address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, + KWCPU_ATTR_SPIFLASH, KWCPU_WIN_ENABLE), &winregs[3].ctrl); + writel(KW_DEFADR_SPIF, &winregs[3].base); + writel(KW_DEFADR_SPIF, &winregs[3].remap_lo); + writel(0x0, &winregs[3].remap_hi); + + /* Window 4: BOOT Memory address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 1024 * 128, KWCPU_TARGET_MEMORY, + KWCPU_ATTR_BOOTROM, KWCPU_WIN_ENABLE), &winregs[4].ctrl); + writel(KW_DEFADR_BOOTROM, &winregs[4].base); + + /* Window 5: Security SRAM address space */ + writel(KWCPU_WIN_CTRL_DATA(1024 * 64, KWCPU_TARGET_SASRAM, + KWCPU_ATTR_SASRAM, KWCPU_WIN_ENABLE), &winregs[5].ctrl); + writel(KW_DEFADR_SASRAM, &winregs[5].base); + + /* Window 6-7: Disabled */ + writel(KWCPU_WIN_DISABLE, &winregs[6].ctrl); + writel(KWCPU_WIN_DISABLE, &winregs[7].ctrl); + + return 0; +} + +/* + * kw_config_gpio - GPIO configuration + */ +void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe) +{ + struct kwgpio_registers *gpio0reg = + (struct kwgpio_registers *)KW_GPIO0_BASE; + struct kwgpio_registers *gpio1reg = + (struct kwgpio_registers *)KW_GPIO1_BASE; + + /* Init GPIOS to default values as per board requirement */ + writel(gpp0_oe_val, &gpio0reg->dout); + writel(gpp1_oe_val, &gpio1reg->dout); + writel(gpp0_oe, &gpio0reg->oe); + writel(gpp1_oe, &gpio1reg->oe); +} + +/* + * kw_config_mpp - Multi-Purpose Pins Functionality configuration + * + * Each MPP can be configured to different functionality through + * MPP control register, ref (sec 6.1 of kirkwood h/w specification) + * + * There are maximum 64 Multi-Pourpose Pins on Kirkwood + * Each MPP functionality can be configuration by a 4bit value + * of MPP control reg, the value and associated functionality depends + * upon used SoC varient + */ +int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31, + u32 mpp32_39, u32 mpp40_47, u32 mpp48_55) +{ + u32 *mppreg = (u32 *) KW_MPP_BASE; + + /* program mpp registers */ + writel(mpp0_7, &mppreg[0]); + writel(mpp8_15, &mppreg[1]); + writel(mpp16_23, &mppreg[2]); + writel(mpp24_31, &mppreg[3]); + writel(mpp32_39, &mppreg[4]); + writel(mpp40_47, &mppreg[5]); + writel(mpp48_55, &mppreg[6]); + return 0; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char *name = "Unknown"; + + switch (readl(KW_REG_DEVICE_ID) & 0x03) { + case 1: + name = "88F6192_A0"; + break; + case 2: + name = "88F6281_A0"; + break; + default: + printf("SoC: Unsupported Kirkwood\n"); + return -1; + } + printf("SoC: Kirkwood %s\n", name); + return 0; +} +#endif /* CONFIG_DISPLAY_CPUINFO */ + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + u32 reg; + struct kwcpu_registers *cpureg = + (struct kwcpu_registers *)KW_CPU_REG_BASE; + + /* Linux expects` the internal registers to be at 0xf1000000 */ + writel(KW_REGS_PHY_BASE, KW_OFFSET_REG); + + /* Enable and invalidate L2 cache in write through mode */ + writel(readl(&cpureg->l2_cfg) | 0x18, &cpureg->l2_cfg); + invalidate_l2_cache(); + + kw_config_adr_windows(); + +#ifdef CONFIG_KIRKWOOD_RGMII_PAD_1V8 + /* + * Configures the I/O voltage of the pads connected to Egigabit + * Ethernet interface to 1.8V + * By defult it is set to 3.3V + */ + reg = readl(KW_REG_MPP_OUT_DRV_REG); + reg |= (1 << 7); + writel(reg, KW_REG_MPP_OUT_DRV_REG); +#endif +#ifdef CONFIG_KIRKWOOD_EGIGA_INIT + /* + * Set egiga port0/1 in normal functional mode + * This is required becasue on kirkwood by default ports are in reset mode + * OS egiga driver may not have provision to set them in normal mode + * and if u-boot is build without network support, network may fail at OS level + */ + reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(0)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(0))); + reg = readl(KWGBE_PORT_SERIAL_CONTROL1_REG(1)); + reg &= ~(1 << 4); /* Clear PortReset Bit */ + writel(reg, (KWGBE_PORT_SERIAL_CONTROL1_REG(1))); +#endif +#ifdef CONFIG_KIRKWOOD_PCIE_INIT + /* + * Enable PCI Express Port0 + */ + reg = readl(&cpureg->ctrl_stat); + reg |= (1 << 0); /* Set PEX0En Bit */ + writel(reg, &cpureg->ctrl_stat); +#endif + return 0; +} +#endif /* CONFIG_ARCH_CPU_INIT */ + +/* + * SOC specific misc init + */ +#if defined(CONFIG_ARCH_MISC_INIT) +int arch_misc_init(void) +{ + volatile u32 temp; + + /*CPU streaming & write allocate */ + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 28); /* disable wr alloc */ + writefr_extra_feature_reg(temp); + + temp = readfr_extra_feature_reg(); + temp &= ~(1 << 29); /* streaming disabled */ + writefr_extra_feature_reg(temp); + + /* L2Cache settings */ + temp = readfr_extra_feature_reg(); + /* Disable L2C pre fetch - Set bit 24 */ + temp |= (1 << 24); + /* enable L2C - Set bit 22 */ + temp |= (1 << 22); + writefr_extra_feature_reg(temp); + + icache_enable(); + /* Change reset vector to address 0x0 */ + temp = get_cr(); + set_cr(temp & ~CR_V); + + return 0; +} +#endif /* CONFIG_ARCH_MISC_INIT */ + +#ifdef CONFIG_KIRKWOOD_EGIGA +int cpu_eth_init(bd_t *bis) +{ + kirkwood_egiga_initialize(bis); + return 0; +} +#endif diff --git a/cpu/arm926ejs/kirkwood/dram.c b/cpu/arm926ejs/kirkwood/dram.c new file mode 100644 index 00000000000..8f2a18af6b3 --- /dev/null +++ b/cpu/arm926ejs/kirkwood/dram.c @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include + +#define KW_REG_CPUCS_WIN_BAR(x) (KW_REGISTER(0x1500) + (x * 0x08)) +#define KW_REG_CPUCS_WIN_SZ(x) (KW_REGISTER(0x1504) + (x * 0x08)) +/* + * kw_sdram_bar - reads SDRAM Base Address Register + */ +u32 kw_sdram_bar(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + + result = readl(KW_REG_CPUCS_WIN_BAR(bank)); + return result; +} + +/* + * kw_sdram_bs - reads SDRAM Bank size + */ +u32 kw_sdram_bs(enum memory_bank bank) +{ + u32 result = 0; + u32 enable = 0x01 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + + if ((!enable) || (bank > BANK3)) + return 0; + result = 0xff000000 & readl(KW_REG_CPUCS_WIN_SZ(bank)); + result += 0x01000000; + return result; +} diff --git a/cpu/arm926ejs/kirkwood/mpp.c b/cpu/arm926ejs/kirkwood/mpp.c new file mode 100644 index 00000000000..b2f0ad55e3c --- /dev/null +++ b/cpu/arm926ejs/kirkwood/mpp.c @@ -0,0 +1,80 @@ +/* + * arch/arm/mach-kirkwood/mpp.c + * + * MPP functions for Marvell Kirkwood SoCs + * Referenced from Linux kernel source + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include + +static u32 kirkwood_variant(void) +{ + switch (readl(KW_REG_DEVICE_ID) & 0x03) { + case 1: + return MPP_F6192_MASK; + case 2: + return MPP_F6281_MASK; + default: + debug("MPP setup: unknown kirkwood variant\n"); + return 0; + } +} + +#define MPP_CTRL(i) (KW_MPP_BASE + (i* 4)) +#define MPP_NR_REGS (1 + MPP_MAX/8) + +void kirkwood_mpp_conf(u32 *mpp_list) +{ + u32 mpp_ctrl[MPP_NR_REGS]; + unsigned int variant_mask; + int i; + + variant_mask = kirkwood_variant(); + if (!variant_mask) + return; + + debug( "initial MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + mpp_ctrl[i] = readl(MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + + + while (*mpp_list) { + unsigned int num = MPP_NUM(*mpp_list); + unsigned int sel = MPP_SEL(*mpp_list); + int shift; + + if (num > MPP_MAX) { + debug("kirkwood_mpp_conf: invalid MPP " + "number (%u)\n", num); + continue; + } + if (!(*mpp_list & variant_mask)) { + debug("kirkwood_mpp_conf: requested MPP%u config " + "unavailable on this hardware\n", num); + continue; + } + + shift = (num & 7) << 2; + mpp_ctrl[num / 8] &= ~(0xf << shift); + mpp_ctrl[num / 8] |= sel << shift; + + mpp_list++; + } + + debug(" final MPP regs:"); + for (i = 0; i < MPP_NR_REGS; i++) { + writel(mpp_ctrl[i], MPP_CTRL(i)); + debug(" %08x", mpp_ctrl[i]); + } + debug("\n"); + +} diff --git a/cpu/arm926ejs/kirkwood/timer.c b/cpu/arm926ejs/kirkwood/timer.c new file mode 100644 index 00000000000..817ff4284f2 --- /dev/null +++ b/cpu/arm926ejs/kirkwood/timer.c @@ -0,0 +1,168 @@ +/* + * Copyright (C) Marvell International Ltd. and its affiliates + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include + +#define UBOOT_CNTR 0 /* counter to use for uboot timer */ + +/* Timer reload and current value registers */ +struct kwtmr_val { + u32 reload; /* Timer reload reg */ + u32 val; /* Timer value reg */ +}; + +/* Timer registers */ +struct kwtmr_registers { + u32 ctrl; /* Timer control reg */ + u32 pad[3]; + struct kwtmr_val tmr[2]; + u32 wdt_reload; + u32 wdt_val; +}; + +struct kwtmr_registers *kwtmr_regs = (struct kwtmr_registers *)KW_TIMER_BASE; + +/* + * ARM Timers Registers Map + */ +#define CNTMR_CTRL_REG &kwtmr_regs->ctrl +#define CNTMR_RELOAD_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].reload +#define CNTMR_VAL_REG(tmrnum) &kwtmr_regs->tmr[tmrnum].val + +/* + * ARM Timers Control Register + * CPU_TIMERS_CTRL_REG (CTCR) + */ +#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2) +#define CTCR_ARM_TIMER_EN_MASK(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS) +#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr)) +#define CTCR_ARM_TIMER_DIS(cntr) (0 << CTCR_ARM_TIMER_EN_OFFS(cntr)) + +#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1) +#define CTCR_ARM_TIMER_AUTO_MASK(cntr) (1 << 1) +#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) +#define CTCR_ARM_TIMER_AUTO_DIS(cntr) (0 << CTCR_ARM_TIMER_AUTO_OFFS(cntr)) + +/* + * ARM Timer\Watchdog Reload Register + * CNTMR_RELOAD_REG (TRR) + */ +#define TRG_ARM_TIMER_REL_OFFS 0 +#define TRG_ARM_TIMER_REL_MASK 0xffffffff + +/* + * ARM Timer\Watchdog Register + * CNTMR_VAL_REG (TVRG) + */ +#define TVR_ARM_TIMER_OFFS 0 +#define TVR_ARM_TIMER_MASK 0xffffffff +#define TVR_ARM_TIMER_MAX 0xffffffff +#define TIMER_LOAD_VAL 0xffffffff + +#define READ_TIMER (readl(CNTMR_VAL_REG(UBOOT_CNTR)) / \ + (CONFIG_SYS_TCLK / 1000)) + +static ulong timestamp; +static ulong lastdec; + +void reset_timer_masked(void) +{ + /* reset time */ + lastdec = READ_TIMER; + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong now = READ_TIMER; + + if (lastdec >= now) { + /* normal mode */ + timestamp += lastdec - now; + } else { + /* we have an overflow ... */ + timestamp += lastdec + + (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now; + } + lastdec = now; + + return timestamp; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +void udelay(unsigned long usec) +{ + uint current; + ulong delayticks; + + current = readl(CNTMR_VAL_REG(UBOOT_CNTR)); + delayticks = (usec * (CONFIG_SYS_TCLK / 1000000)); + + if (current < delayticks) { + delayticks -= current; + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ; + while ((TIMER_LOAD_VAL - delayticks) < + readl(CNTMR_VAL_REG(UBOOT_CNTR))) ; + } else { + while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) > + (current - delayticks)) ; + } +} + +/* + * init the counter + */ +int timer_init(void) +{ + unsigned int cntmrctrl; + + /* load value into timer */ + writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR)); + writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR)); + + /* enable timer in auto reload mode */ + cntmrctrl = readl(CNTMR_CTRL_REG); + cntmrctrl |= CTCR_ARM_TIMER_EN(UBOOT_CNTR); + cntmrctrl |= CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR); + writel(cntmrctrl, CNTMR_CTRL_REG); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 966df9ac3bf..dd5f332ba93 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -27,6 +27,9 @@ #ifdef CONFIG_NS87308 #include #endif +#ifdef CONFIG_KIRKWOOD +#include +#endif #if defined (CONFIG_SERIAL_MULTI) #include diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/include/asm-arm/arch-kirkwood/cpu.h new file mode 100644 index 00000000000..36064ae0c63 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/cpu.h @@ -0,0 +1,159 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _KWCPU_H +#define _KWCPU_H + +#include + +#ifndef __ASSEMBLY__ + +#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) + +#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) +#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum kwcpu_winen { + KWCPU_WIN_DISABLE, + KWCPU_WIN_ENABLE +}; + +enum kwcpu_target { + KWCPU_TARGET_RESERVED, + KWCPU_TARGET_MEMORY, + KWCPU_TARGET_1RESERVED, + KWCPU_TARGET_SASRAM, + KWCPU_TARGET_PCIE +}; + +enum kwcpu_attrib { + KWCPU_ATTR_SASRAM = 0x01, + KWCPU_ATTR_NANDFLASH = 0x2f, + KWCPU_ATTR_SPIFLASH = 0x1e, + KWCPU_ATTR_BOOTROM = 0x1d, + KWCPU_ATTR_PCIE_IO = 0xe0, + KWCPU_ATTR_PCIE_MEM = 0xe8 +}; + +/* + * Default Device Address MAP BAR values + */ +#define KW_DEFADR_PCI_MEM 0x90000000 +#define KW_DEFADR_PCI_IO 0xC0000000 +#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 +#define KW_DEFADR_SASRAM 0xC8010000 +#define KW_DEFADR_NANDF 0xD8000000 +#define KW_DEFADR_SPIF 0xE8000000 +#define KW_DEFADR_BOOTROM 0xF8000000 + +/* + * read feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * MBus-L to Mbus Bridge Registers + * Ref: Datasheet sec:A.3 + */ +struct kwwin_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Ref: Datasheet sec:A.3.2 + */ +struct kwcpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ + u32 pad1[2]; + u32 ftdll_config; /* 0x20120 */ + u32 pad2; + u32 l2_cfg; /* 0x20128 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct kwgpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +void reset_cpu(unsigned long ignored); +unsigned char get_random_hex(void); +unsigned int kw_sdram_bar(enum memory_bank bank); +unsigned int kw_sdram_bs(enum memory_bank bank); +int kw_config_adr_windows(void); +void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, + unsigned int gpp0_oe, unsigned int gpp1_oe); +int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, + unsigned int mpp16_23, unsigned int mpp24_31, + unsigned int mpp32_39, unsigned int mpp40_47, + unsigned int mpp48_55); +#endif /* __ASSEMBLY__ */ +#endif /* _KWCPU_H */ diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h new file mode 100644 index 00000000000..d5f25f9e5a0 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for the Marvell's Feroceon CPU core. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_KIRKWOOD_H +#define _ASM_ARCH_KIRKWOOD_H + +#ifndef __ASSEMBLY__ +#include +#include +#endif /* __ASSEMBLY__ */ + +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) +#include + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) +#define KW_OFFSET_REG (INTREG_BASE + 0x20080) + +/* undocumented registers */ +#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) +#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) + +#define KW_UART0_BASE (KW_REGISTER(0x12000)) +#define KW_UART1_BASE (KW_REGISTER(0x13000)) +#define KW_MPP_BASE (KW_REGISTER(0x10000)) +#define KW_GPIO0_BASE (KW_REGISTER(0x10100)) +#define KW_GPIO1_BASE (KW_REGISTER(0x10140)) +#define KW_NANDF_BASE (KW_REGISTER(0x10418)) +#define KW_SPI_BASE (KW_REGISTER(0x10600)) +#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) +#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) +#define KW_TIMER_BASE (KW_REGISTER(0x20300)) +#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) +#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) +#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) + +#if defined (CONFIG_KW88F6281) +#include +#elif defined (CONFIG_KW88F6192) +#include +#else +#error "SOC Name not defined" +#endif /* CONFIG_KW88F6281 */ +#endif /* CONFIG_FEROCEON_88FR131 */ +#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/include/asm-arm/arch-kirkwood/kw88f6192.h b/include/asm-arm/arch-kirkwood/kw88f6192.h new file mode 100644 index 00000000000..bbb7ceebbae --- /dev/null +++ b/include/asm-arm/arch-kirkwood/kw88f6192.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CONFIG_KW88F6192_H +#define _CONFIG_KW88F6192_H + +/* SOC specific definations */ +#define KW88F6192_REGS_PHYS_BASE 0xf1000000 +#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_KW88F6192_H */ diff --git a/include/asm-arm/arch-kirkwood/kw88f6281.h b/include/asm-arm/arch-kirkwood/kw88f6281.h new file mode 100644 index 00000000000..80723eac542 --- /dev/null +++ b/include/asm-arm/arch-kirkwood/kw88f6281.h @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_KW88F6281_H +#define _ASM_ARCH_KW88F6281_H + +/* SOC specific definations */ +#define KW88F6281_REGS_PHYS_BASE 0xf1000000 +#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE + +/* TCLK Core Clock defination*/ +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ + +#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h new file mode 100644 index 00000000000..e021a80c2ca --- /dev/null +++ b/include/asm-arm/arch-kirkwood/mpp.h @@ -0,0 +1,303 @@ +/* + * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins + * + * Copyright 2009: Marvell Technology Group Ltd. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __KIRKWOOD_MPP_H +#define __KIRKWOOD_MPP_H + +#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F6180 */ ((!!(_F6180)) << 14) | \ + /* available on F6190 */ ((!!(_F6190)) << 15) | \ + /* available on F6192 */ ((!!(_F6192)) << 16) | \ + /* available on F6281 */ ((!!(_F6281)) << 17)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 6180 6190 6192 6281 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) + +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) + +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) + +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) +#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) + +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) + +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) + +#define MPP_MAX 49 + +void kirkwood_mpp_conf(unsigned int *mpp_list); + +#endif -- cgit v1.3.1 From 2600b8571a26c10c1c43401d7af38e2333cc5381 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sat, 20 Jun 2009 11:02:17 +0200 Subject: versatile: config coding style cleanup Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD Cc: Peter Pearse --- include/configs/versatile.h | 118 ++++++++++++++++++++++---------------------- 1 file changed, 58 insertions(+), 60 deletions(-) (limited to 'include') diff --git a/include/configs/versatile.h b/include/configs/versatile.h index 8f6383b0514..300271f9d61 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -35,24 +35,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ +#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ #define CONFIG_VERSATILE 1 /* in Versatile Platform Board */ -#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ +#define CONFIG_ARCH_VERSATILE 1 /* Specifically, a Versatile */ - -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_HZ (1000000 / 256) -#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ +#define CONFIG_SYS_MEMTEST_START 0x100000 +#define CONFIG_SYS_MEMTEST_END 0x10000000 +#define CONFIG_SYS_HZ (1000000 / 256) +#define CONFIG_SYS_TIMERBASE 0x101E2000 /* Timer 0 and 1 base */ #define CONFIG_SYS_TIMER_INTERVAL 10000 -#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4) /* Divide by 16 */ -#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ +#define CONFIG_SYS_TIMER_RELOAD (CONFIG_SYS_TIMER_INTERVAL >> 4) +#define CONFIG_SYS_TIMER_CTRL 0x84 /* Enable, Clock / 16 */ /* * control registers */ -#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ +#define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ /* * System controller bit assignment @@ -65,14 +64,15 @@ #define VERSATILE_TIMER3_EnSel 19 #define VERSATILE_TIMER4_EnSel 21 -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ +#define CONFIG_MISC_INIT_R 1 /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* * Hardware drivers @@ -88,61 +88,57 @@ */ #define CONFIG_PL011_SERIAL #define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_PL01x_PORTS \ + {(void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BAUDRATE 38400 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_SERIAL0 0x101F1000 #define CONFIG_SYS_SERIAL1 0x101F2000 - /* * Command line configuration. */ +#define CONFIG_CMD_BDI #define CONFIG_CMD_DHCP +#define CONFIG_CMD_FLASH #define CONFIG_CMD_IMI +#define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET #define CONFIG_CMD_PING -#define CONFIG_CMD_BDI -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_FLASH #define CONFIG_CMD_SAVEENV - /* * BOOTP options */ -#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_BOOTPATH #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - +#define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp netdev=25,0,0xf1010000,0xf1010010,eth0" -/*#define CONFIG_BOOTCOMMAND "bootp ; bootm" */ +#define CONFIG_BOOTARGS "root=/dev/nfs mem=128M ip=dhcp "\ + "netdev=25,0,0xf1010000,0xf1010010,eth0" /* * Static configuration when assigning fixed address */ -/*#define CONFIG_NETMASK 255.255.255.0 /--* talk on MY local net */ -/*#define CONFIG_IPADDR xx.xx.xx.xx /--* static IP I currently own */ -/*#define CONFIG_SERVERIP xx.xx.xx.xx /--* current IP of my dev pc */ -#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ - +#define CONFIG_BOOTFILE "/tftpboot/uImage" /* file to load */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "Versatile # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ @@ -151,43 +147,45 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_FLASH_BASE 0x34000000 +#define CONFIG_SYS_FLASH_BASE 0x34000000 /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define VERSATILE_SYS_BASE 0x10000000 -#define VERSATILE_SYS_FLASH_OFFSET 0x4C -#define VERSATILE_FLASHCTRL (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) -#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ +#define VERSATILE_SYS_BASE 0x10000000 +#define VERSATILE_SYS_FLASH_OFFSET 0x4C +#define VERSATILE_FLASHCTRL \ + (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) +/* Enable writing to flash */ +#define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define PHYS_FLASH_SIZE 0x34000000 /* 64MB */ /* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Erase Timeout */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (20 * CONFIG_SYS_HZ) /* Write Timeout */ #define CONFIG_SYS_MAX_FLASH_SECT (256) -#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE) +#define PHYS_FLASH_1 (CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash instead of CONFIG_ENV_IS_NOWHERE */ -#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts here */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_IS_IN_FLASH 1 /* env in flash */ +#define CONFIG_ENV_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ +#define CONFIG_ENV_SIZE 0x10000 /* Size of Environment */ +#define CONFIG_ENV_OFFSET 0x01f00000 /* environment starts */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 06e758e75c79ce8761866bf8165c443584a20893 Mon Sep 17 00:00:00 2001 From: "Kim, Heung Jun" Date: Sat, 20 Jun 2009 11:02:17 +0200 Subject: move L2 cache enable/disable function to cache.c in the omap3 SoC directory Signed-off-by: HeungJun, Kim CC: Dirk Behme Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm_cortexa8/cpu.c | 70 ++---------------------------- cpu/arm_cortexa8/omap3/Makefile | 1 + cpu/arm_cortexa8/omap3/board.c | 5 ++- cpu/arm_cortexa8/omap3/cache.c | 96 +++++++++++++++++++++++++++++++++++++++++ include/asm-arm/cache.h | 4 ++ 5 files changed, 108 insertions(+), 68 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache.c (limited to 'include') diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c index 6fd07d0b737..fcb5775a1c3 100644 --- a/cpu/arm_cortexa8/cpu.c +++ b/cpu/arm_cortexa8/cpu.c @@ -33,12 +33,8 @@ #include #include -#include #include - -#ifndef CONFIG_L2_OFF -void l2cache_disable(void); -#endif +#include static void cache_flush(void); @@ -63,7 +59,7 @@ int cleanup_before_linux(void) #ifndef CONFIG_L2_OFF /* turn off L2 cache */ - l2cache_disable(); + l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif @@ -72,72 +68,14 @@ int cleanup_before_linux(void) asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF - l2cache_enable(); + l2_cache_enable(); #endif return 0; } -void l2cache_enable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("orr r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } - -} - -void l2cache_disable() -{ - unsigned long i; - volatile unsigned int j; - - /* ES2 onwards we can disable/enable L2 ourselves */ - if (get_cpu_rev() >= CPU_3XX_ES20) { - __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); - __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); - __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); - } else { - /* Save r0, r12 and restore them after usage */ - __asm__ __volatile__("mov %0, r12":"=r"(j)); - __asm__ __volatile__("mov %0, r0":"=r"(i)); - - /* - * GP Device ROM code API usage here - * r12 = AUXCR Write function and r0 value - */ - __asm__ __volatile__("mov r12, #0x3"); - __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); - __asm__ __volatile__("bic r0, r0, #0x2"); - /* SMI instruction to call ROM Code API */ - __asm__ __volatile__(".word 0xE1600070"); - __asm__ __volatile__("mov r0, %0":"=r"(i)); - __asm__ __volatile__("mov r12, %0":"=r"(j)); - } -} - static void cache_flush(void) { asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } + diff --git a/cpu/arm_cortexa8/omap3/Makefile b/cpu/arm_cortexa8/omap3/Makefile index 50176eeb35f..1fbd0dcdac7 100644 --- a/cpu/arm_cortexa8/omap3/Makefile +++ b/cpu/arm_cortexa8/omap3/Makefile @@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o COBJS += board.o +COBJS += cache.o COBJS += clock.o COBJS += gpio.o COBJS += mem.o diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c index 6e295994ab5..b665ec9eda9 100644 --- a/cpu/arm_cortexa8/omap3/board.c +++ b/cpu/arm_cortexa8/omap3/board.c @@ -36,6 +36,7 @@ #include #include #include +#include extern omap3_sysinfo sysinfo; @@ -206,9 +207,9 @@ void s_init(void) #endif #ifdef CONFIG_L2_OFF - l2cache_disable(); + l2_cache_disable(); #else - l2cache_enable(); + l2_cache_enable(); #endif /* * Writing to AuxCR in U-boot using SMI for GP DEV diff --git a/cpu/arm_cortexa8/omap3/cache.c b/cpu/arm_cortexa8/omap3/cache.c new file mode 100644 index 00000000000..f49ed4afd8f --- /dev/null +++ b/cpu/arm_cortexa8/omap3/cache.c @@ -0,0 +1,96 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * omap3 L2 cache code + */ + +#include +#include +#include + +void l2_cache_enable(void) +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2_cache_disable(void) +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() >= CPU_3XX_ES20) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* + * GP Device ROM code API usage here + * r12 = AUXCR Write function and r0 value + */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h index 248240bef0a..d0518be28ca 100644 --- a/include/asm-arm/cache.h +++ b/include/asm-arm/cache.h @@ -38,4 +38,8 @@ static inline void invalidate_l2_cache(void) : : "r" (val) : "cc"); isb(); } + +void l2_cache_enable(void); +void l2_cache_disable(void); + #endif /* _ASM_CACHE_H */ -- cgit v1.3.1 From c8badbe500a752f42049e51042767ee62ea714e0 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 28 Jun 2009 14:14:21 +0200 Subject: dm355/pm9261: add missing CONFIG_NET_MULTI Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/davinci_dm355evm.h | 1 + include/configs/pm9261.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index 9a7df083fb0..c35f5c933fa 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -57,6 +57,7 @@ #define CONFIG_DM9000_BASE 0x04014000 #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE + 2) +#define CONFIG_NET_MULTI /* I2C */ #define CONFIG_HARD_I2C diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index ac09cf29479..4784c40d46e 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -253,6 +253,7 @@ #define CONFIG_DM9000_USE_16BIT 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 +#define CONFIG_NET_MULTI /* USB */ #define CONFIG_USB_ATMEL -- cgit v1.3.1 From 8d460a573e2a2ac4834636903865a0428ad0e629 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 23 Jun 2009 00:12:01 +0200 Subject: S3C24x0: extract interrupts from timer Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm920t/interrupts.c | 8 ++----- cpu/arm920t/s3c24x0/Makefile | 14 ++++++------ cpu/arm920t/s3c24x0/interrupts.c | 46 ++++++++++++++++++++++++++++++++++++++++ cpu/arm920t/s3c24x0/timer.c | 9 -------- include/common.h | 2 -- 5 files changed, 56 insertions(+), 23 deletions(-) create mode 100644 cpu/arm920t/s3c24x0/interrupts.c (limited to 'include') diff --git a/cpu/arm920t/interrupts.c b/cpu/arm920t/interrupts.c index 539eb5c4517..561083ec73e 100644 --- a/cpu/arm920t/interrupts.c +++ b/cpu/arm920t/interrupts.c @@ -32,16 +32,12 @@ #include #include +#if defined (CONFIG_ARCH_INTEGRATOR) void do_irq (struct pt_regs *pt_regs) { -#if defined (ARM920_IRQ_CALLBACK) - ARM920_IRQ_CALLBACK(); -#elif defined (CONFIG_ARCH_INTEGRATOR) /* ASSUMED to be a timer interrupt */ /* Just clear it - count handled in */ /* integratorap.c */ *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0x0C) = 0; -#else -#error do_irq() not defined for this cpu type -#endif } +#endif diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile index 5d2be2c1b29..7e8d6ed5f2f 100644 --- a/cpu/arm920t/s3c24x0/Makefile +++ b/cpu/arm920t/s3c24x0/Makefile @@ -25,13 +25,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a -COBJS += speed.o -COBJS += timer.o -COBJS += usb.o -COBJS += usb_ohci.o +COBJS-$(CONFIG_USE_IRQ) += interrupts.o +COBJS-y += speed.o +COBJS-y += timer.o +COBJS-y += usb.o +COBJS-y += usb_ohci.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) all: $(obj).depend $(LIB) diff --git a/cpu/arm920t/s3c24x0/interrupts.c b/cpu/arm920t/s3c24x0/interrupts.c new file mode 100644 index 00000000000..11ec95e1266 --- /dev/null +++ b/cpu/arm920t/s3c24x0/interrupts.c @@ -0,0 +1,46 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include + +#if defined(CONFIG_S3C2400) +#include +#elif defined(CONFIG_S3C2410) +#include +#endif +#include + +void do_irq (struct pt_regs *pt_regs) +{ + S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); + u_int32_t intpnd = irq->INTPND; + +} diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c index f0a09cddff5..c8c7cdb5202 100644 --- a/cpu/arm920t/s3c24x0/timer.c +++ b/cpu/arm920t/s3c24x0/timer.c @@ -215,13 +215,4 @@ void reset_cpu (ulong ignored) /*NOTREACHED*/ } -#ifdef CONFIG_USE_IRQ -void s3c2410_irq(void) -{ - S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT(); - u_int32_t intpnd = irq->INTPND; - -} -#endif /* USE_IRQ */ - #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ diff --git a/include/common.h b/include/common.h index ff4f821dd25..6284b8aff80 100644 --- a/include/common.h +++ b/include/common.h @@ -493,8 +493,6 @@ ulong get_PCI_freq (void); #endif #if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \ defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400) -void s3c2410_irq(void); -#define ARM920_IRQ_CALLBACK s3c2410_irq ulong get_FCLK (void); ulong get_HCLK (void); ulong get_PCLK (void); -- cgit v1.3.1 From 8449f287f5c53d59db13c3c512e6bd1750b692d1 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Wed, 1 Jul 2009 01:07:55 +0200 Subject: MX31: Add basic support for Freescale i.MX31 PDK board. Add support for Freescale's i.MX31 PDK board (a.k.a. 3 stack board). This patch assumes that some other program performs the actual NAND boot. Signed-off-by: Magnus Lilja Acked-by: Fabio Estevam Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/freescale/mx31pdk/Makefile | 52 +++++++++++ board/freescale/mx31pdk/config.mk | 1 + board/freescale/mx31pdk/mx31pdk.c | 63 +++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 2 + include/configs/mx31pdk.h | 162 ++++++++++++++++++++++++++++++++++ 8 files changed, 288 insertions(+) create mode 100644 board/freescale/mx31pdk/Makefile create mode 100644 board/freescale/mx31pdk/config.mk create mode 100644 board/freescale/mx31pdk/mx31pdk.c create mode 100644 include/configs/mx31pdk.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index b5b54849e0b..ade25ae33ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,10 @@ Thomas Elste modnet50 ARM720T (NET+50) +Fabio Estevam + + mx31pdk i.MX31 + Peter Figuli wepep250 xscale diff --git a/MAKEALL b/MAKEALL index fb80cfa8ada..3777f4228e1 100755 --- a/MAKEALL +++ b/MAKEALL @@ -554,6 +554,7 @@ LIST_ARM11=" \ imx31_phycore \ imx31_phycore_eet \ mx31ads \ + mx31pdk \ qong \ smdk6400 \ " diff --git a/Makefile b/Makefile index ebb12e91f93..4c9884c5669 100644 --- a/Makefile +++ b/Makefile @@ -3135,6 +3135,9 @@ imx31_phycore_config : unconfig mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 +mx31pdk_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 mx31pdk freescale mx31 + omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx diff --git a/board/freescale/mx31pdk/Makefile b/board/freescale/mx31pdk/Makefile new file mode 100644 index 00000000000..d5d8f0475dc --- /dev/null +++ b/board/freescale/mx31pdk/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2008 Magnus Lilja +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx31pdk.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk new file mode 100644 index 00000000000..d34dc02d96a --- /dev/null +++ b/board/freescale/mx31pdk/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x87f00000 diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c new file mode 100644 index 00000000000..6b60c17dca8 --- /dev/null +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -0,0 +1,63 @@ +/* + * + * (C) Copyright 2009 Magnus Lilja + * + * (c) 2007 Pengutronix, Sascha Hauer + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + /* CS5: CPLD incl. network controller */ + __REG(CSCR_U(5)) = 0x0000d843; + __REG(CSCR_L(5)) = 0x22252521; + __REG(CSCR_A(5)) = 0x22220a00; + + /* Setup UART1 and SPI2 pins */ + mx31_uart1_hw_init(); + mx31_spi2_hw_init(); + + gd->bd->bi_arch_number = MACH_TYPE_MX31_3DS; /* board id for linux */ + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int checkboard(void) +{ + printf("Board: i.MX31 MAX PDK (3DS)\n"); + return 0; +} diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index c2e7dcf8318..76f4d53a32e 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -84,6 +84,8 @@ #define IPU_CONF_IC_EN (1<<1) #define IPU_CONF_SCI_EN (1<<0) +#define ARM_PPMRR 0x40000015 + #define WDOG_BASE 0x53FDC000 /* diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h new file mode 100644 index 00000000000..7167e9d0db2 --- /dev/null +++ b/include/configs/mx31pdk.h @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2008 Magnus Lilja + * + * (C) Copyright 2004 + * Texas Instruments. + * Richard Woodruff + * Kshitij Gupta + * + * Configuration settings for the Freescale i.MX31 PDK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other + * program to initialize the SDRAM. + */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +/* Bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ + +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX31_UART1 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) + +#define CONFIG_RTC_MC13783 1 + +/* MC13783 connected to CSPI2 and SS2 */ +#define CONFIG_MC13783_SPI_BUS 1 +#define CONFIG_MC13783_SPI_CS 2 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SPI +#define CONFIG_CMD_DATE + +/* + * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require + * that CFG_NO_FLASH is undefined). + */ +#undef CONFIG_CMD_IMLS + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ + "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ + "tftpboot 0x81000000 uImage-mx31; bootm\0" + +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0xB6000000 +#define CONFIG_DRIVER_SMC911X_32_BIT 1 + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "uboot> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x10000 + +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x81000000 + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +/* No NOR flash present */ +#define CONFIG_SYS_NO_FLASH 1 + +#define CONFIG_ENV_IS_NOWHERE 1 + +#define CONFIG_ENV_SIZE (128 * 1024) + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 2e23008e5dbde7fe4c4758bee5a393e1db796cdf Mon Sep 17 00:00:00 2001 From: Simon Kagstrom Date: Tue, 30 Jun 2009 23:03:31 +0200 Subject: arm: Kirkwood: Correct header define Correct define typo (. -> ,) Signed-off-by: Simon Kagstrom --- include/asm-arm/arch-kirkwood/mpp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-arm/arch-kirkwood/mpp.h b/include/asm-arm/arch-kirkwood/mpp.h index e021a80c2ca..bc74278ed31 100644 --- a/include/asm-arm/arch-kirkwood/mpp.h +++ b/include/asm-arm/arch-kirkwood/mpp.h @@ -289,7 +289,7 @@ #define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) #define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48. 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) #define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) #define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -- cgit v1.3.1 From 45627fce18139a74e0755124d27376b520db156c Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Tue, 30 Jun 2009 23:03:33 +0200 Subject: at91: Add CAN init function To enable CAN init, CONFIG_CAN has to be defined in the board config file and at91_can_hw_init() has to be called in the board specific code. CAN is available on AT91SAM9263 and AT91CAP9 SoC. Signed-off-by: Daniel Gorsulowski --- cpu/arm926ejs/at91/at91cap9_devices.c | 15 +++++++++++++++ cpu/arm926ejs/at91/at91sam9263_devices.c | 15 +++++++++++++++ include/asm-arm/arch-at91/at91_common.h | 1 + 3 files changed, 31 insertions(+) (limited to 'include') diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index c0024acf04e..39e405fee13 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -3,6 +3,10 @@ * Stelian Pop * Lead Tech Design * + * (C) Copyright 2009 + * Daniel Gorsulowski + * esd electronic system design gmbh + * * See file CREDITS for list of people who contributed to this * project. * @@ -174,3 +178,14 @@ void at91_macb_hw_init(void) #endif } #endif + +#ifdef CONFIG_AT91_CAN +void at91_can_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA12, 0); /* CAN_TX */ + at91_set_A_periph(AT91_PIN_PA13, 1); /* CAN_RX */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_CAN); +} +#endif diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index 0f2613e7b8c..f72efdfe807 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -3,6 +3,10 @@ * Stelian Pop * Lead Tech Design * + * (C) Copyright 2009 + * Daniel Gorsulowski + * esd electronic system design gmbh + * * See file CREDITS for list of people who contributed to this * project. * @@ -182,3 +186,14 @@ void at91_uhp_hw_init(void) at91_set_gpio_output(AT91_PIN_PA24, 0); } #endif + +#ifdef CONFIG_AT91_CAN +void at91_can_hw_init(void) +{ + at91_set_A_periph(AT91_PIN_PA13, 0); /* CAN_TX */ + at91_set_A_periph(AT91_PIN_PA14, 1); /* CAN_RX */ + + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN); +} +#endif diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h index 9c4e0197155..01840eede41 100644 --- a/include/asm-arm/arch-at91/at91_common.h +++ b/include/asm-arm/arch-at91/at91_common.h @@ -25,6 +25,7 @@ #ifndef AT91_COMMON_H #define AT91_COMMON_H +void at91_can_hw_init(void); void at91_macb_hw_init(void); void at91_serial_hw_init(void); void at91_serial0_hw_init(void); -- cgit v1.3.1 From 21761540b43c7086c75ee9afb412da1e5ddde2e9 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Tue, 30 Jun 2009 21:03:35 +0200 Subject: ARM: Update mach-types update against linux v2.6.30 Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/asm-arm/mach-types.h | 1651 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 1612 insertions(+), 39 deletions(-) (limited to 'include') diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index 9b8485d47e8..5293d679eb0 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -912,7 +912,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_APF9328 906 #define MACH_TYPE_OMAP_WIPOQ 907 #define MACH_TYPE_OMAP_TWIP 908 -#define MACH_TYPE_PALMT650 909 +#define MACH_TYPE_TREO650 909 #define MACH_TYPE_ACUMEN 910 #define MACH_TYPE_XP100 911 #define MACH_TYPE_FS2410 912 @@ -1228,7 +1228,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_VPAC270 1227 #define MACH_TYPE_RD129 1228 #define MACH_TYPE_HTCWIZARD 1229 -#define MACH_TYPE_XSCALE_TREO680 1230 +#define MACH_TYPE_TREO680 1230 #define MACH_TYPE_TECON_TMEZON 1231 #define MACH_TYPE_ZYLONITE 1233 #define MACH_TYPE_GENE1270 1234 @@ -1414,10 +1414,10 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CNTY_TITAN 1418 #define MACH_TYPE_APP3XX 1419 #define MACH_TYPE_SIDEOATSGRAMA 1420 -#define MACH_TYPE_PALMTREO700P 1421 -#define MACH_TYPE_PALMTREO700W 1422 -#define MACH_TYPE_PALMTREO750 1423 -#define MACH_TYPE_PALMTREO755P 1424 +#define MACH_TYPE_TREO700P 1421 +#define MACH_TYPE_TREO700W 1422 +#define MACH_TYPE_TREO750 1423 +#define MACH_TYPE_TREO755P 1424 #define MACH_TYPE_EZREGANUT9200 1425 #define MACH_TYPE_SARGE 1426 #define MACH_TYPE_A696 1427 @@ -1717,7 +1717,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_CSB637XO 1730 #define MACH_TYPE_EVISIONG 1731 #define MACH_TYPE_STMP37XX 1732 -#define MACH_TYPE_STMP38XX 1733 +#define MACH_TYPE_STMP378X 1733 #define MACH_TYPE_TNT 1734 #define MACH_TYPE_TBXT 1735 #define MACH_TYPE_PLAYMATE 1736 @@ -1813,7 +1813,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_TAVOREVB 1827 #define MACH_TYPE_SAAR 1828 #define MACH_TYPE_DEISTER_EYECAM 1829 -#define MACH_TYPE_AT91SAM9M10EK 1830 +#define MACH_TYPE_AT91SAM9M10G45EK 1830 #define MACH_TYPE_LINKSTATION_PRODUO 1831 #define MACH_TYPE_HIT_B0 1832 #define MACH_TYPE_ADX_RMU 1833 @@ -2120,6 +2120,127 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_FMZWEBMODUL 2134 #define MACH_TYPE_RD78X00_MASA 2135 #define MACH_TYPE_SMALLOGGER 2136 +#define MACH_TYPE_CCW9P9215 2137 +#define MACH_TYPE_DM355_LEOPARD 2138 +#define MACH_TYPE_TS219 2139 +#define MACH_TYPE_TNY_A9263 2140 +#define MACH_TYPE_APOLLO 2141 +#define MACH_TYPE_AT91CAP9STK 2142 +#define MACH_TYPE_SPC300 2143 +#define MACH_TYPE_EKO 2144 +#define MACH_TYPE_CCW9M2443 2145 +#define MACH_TYPE_CCW9M2443JS 2146 +#define MACH_TYPE_M2M_ROUTER_DEVICE 2147 +#define MACH_TYPE_STAR9104NAS 2148 +#define MACH_TYPE_PCA100 2149 +#define MACH_TYPE_Z3_DM365_MOD_01 2150 +#define MACH_TYPE_HIPOX 2151 +#define MACH_TYPE_OMAP3_PITEDS 2152 +#define MACH_TYPE_BM150R 2153 +#define MACH_TYPE_TBONE 2154 +#define MACH_TYPE_MERLIN 2155 +#define MACH_TYPE_FALCON 2156 +#define MACH_TYPE_DAVINCI_DA850_EVM 2157 +#define MACH_TYPE_S5P6440 2158 +#define MACH_TYPE_AT91SAM9G10EK 2159 +#define MACH_TYPE_OMAP_4430SDP 2160 +#define MACH_TYPE_LPC313X 2161 +#define MACH_TYPE_MAGX_ZN5 2162 +#define MACH_TYPE_MAGX_EM30 2163 +#define MACH_TYPE_MAGX_VE66 2164 +#define MACH_TYPE_MEESC 2165 +#define MACH_TYPE_OTC570 2166 +#define MACH_TYPE_BCU2412 2167 +#define MACH_TYPE_BEACON 2168 +#define MACH_TYPE_ACTIA_TGW 2169 +#define MACH_TYPE_E4430 2170 +#define MACH_TYPE_QL300 2171 +#define MACH_TYPE_BTMAVB101 2172 +#define MACH_TYPE_BTMAWB101 2173 +#define MACH_TYPE_SQ201 2174 +#define MACH_TYPE_QUATRO45XX 2175 +#define MACH_TYPE_OPENPAD 2176 +#define MACH_TYPE_TX25 2177 +#define MACH_TYPE_OMAP3_TORPEDO 2178 +#define MACH_TYPE_HTCRAPHAEL_K 2179 +#define MACH_TYPE_LAL43 2181 +#define MACH_TYPE_HTCRAPHAEL_CDMA500 2182 +#define MACH_TYPE_ANW6410 2183 +#define MACH_TYPE_HTCPROPHET 2185 +#define MACH_TYPE_CFA_10022 2186 +#define MACH_TYPE_IMX27_VISSTRIM_M10 2187 +#define MACH_TYPE_PX2IMX27 2188 +#define MACH_TYPE_STM3210E_EVAL 2189 +#define MACH_TYPE_DVS10 2190 +#define MACH_TYPE_PORTUXG20 2191 +#define MACH_TYPE_ARM_SPV 2192 +#define MACH_TYPE_SMDKC110 2193 +#define MACH_TYPE_CABESPRESSO 2194 +#define MACH_TYPE_HMC800 2195 +#define MACH_TYPE_SHOLES 2196 +#define MACH_TYPE_BTMXC31 2197 +#define MACH_TYPE_DT501 2198 +#define MACH_TYPE_KTX 2199 +#define MACH_TYPE_OMAP3517EVM 2200 +#define MACH_TYPE_NETSPACE_V2 2201 +#define MACH_TYPE_NETSPACE_MAX_V2 2202 +#define MACH_TYPE_D2NET_V2 2203 +#define MACH_TYPE_NET2BIG_V2 2204 +#define MACH_TYPE_NET4BIG_V2 2205 +#define MACH_TYPE_NET5BIG_V2 2206 +#define MACH_TYPE_ENDB2443 2207 +#define MACH_TYPE_INETSPACE_V2 2208 +#define MACH_TYPE_TROS 2209 +#define MACH_TYPE_PELCO_HOMER 2210 +#define MACH_TYPE_OFSP8 2211 +#define MACH_TYPE_AT91SAM9G45EKES 2212 +#define MACH_TYPE_GUF_CUPID 2213 +#define MACH_TYPE_EAB1R 2214 +#define MACH_TYPE_DESIREC 2215 +#define MACH_TYPE_CORDOBA 2216 +#define MACH_TYPE_IRVINE 2217 +#define MACH_TYPE_SFF772 2218 +#define MACH_TYPE_PELCO_MILANO 2219 +#define MACH_TYPE_PC7302 2220 +#define MACH_TYPE_BIP6000 2221 +#define MACH_TYPE_SILVERMOON 2222 +#define MACH_TYPE_VC0830 2223 +#define MACH_TYPE_DT430 2224 +#define MACH_TYPE_JI42PF 2225 +#define MACH_TYPE_GNET_KSM 2226 +#define MACH_TYPE_GNET_SGM 2227 +#define MACH_TYPE_GNET_SGR 2228 +#define MACH_TYPE_OMAP3_ICETEKEVM 2229 +#define MACH_TYPE_PNP 2230 +#define MACH_TYPE_CTERA_2BAY_K 2231 +#define MACH_TYPE_CTERA_2BAY_U 2232 +#define MACH_TYPE_SAS_C 2233 +#define MACH_TYPE_VMA2315 2234 +#define MACH_TYPE_VCS 2235 +#define MACH_TYPE_SPEAR600 2236 +#define MACH_TYPE_SPEAR300 2237 +#define MACH_TYPE_SPEAR1300 2238 +#define MACH_TYPE_LILLY1131 2239 +#define MACH_TYPE_ARVOO_AX301 2240 +#define MACH_TYPE_MAPPHONE 2241 +#define MACH_TYPE_LEGEND 2242 +#define MACH_TYPE_SALSA 2243 +#define MACH_TYPE_LOUNGE 2244 +#define MACH_TYPE_VISION 2245 +#define MACH_TYPE_VMB20 2246 +#define MACH_TYPE_HY2410 2247 +#define MACH_TYPE_HY9315 2248 +#define MACH_TYPE_BULLWINKLE 2249 +#define MACH_TYPE_ARM_ULTIMATOR2 2250 +#define MACH_TYPE_VS_V210 2252 +#define MACH_TYPE_VS_V212 2253 +#define MACH_TYPE_HMT 2254 +#define MACH_TYPE_SUEN3 2255 +#define MACH_TYPE_VESPER 2256 +#define MACH_TYPE_STR9 2257 +#define MACH_TYPE_OMAP3_WL_FF 2258 +#define MACH_TYPE_SIMCOM 2259 +#define MACH_TYPE_MCWEBIO 2260 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -12921,16 +13042,16 @@ extern unsigned int __machine_arch_type; # define machine_is_omap_twip() (0) #endif -#ifdef CONFIG_MACH_PALMT650 +#ifdef CONFIG_MACH_TREO650 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PALMT650 +# define machine_arch_type MACH_TYPE_TREO650 # endif -# define machine_is_palmt650() (machine_arch_type == MACH_TYPE_PALMT650) +# define machine_is_treo650() (machine_arch_type == MACH_TYPE_TREO650) #else -# define machine_is_palmt650() (0) +# define machine_is_treo650() (0) #endif #ifdef CONFIG_MACH_ACUMEN @@ -16713,16 +16834,16 @@ extern unsigned int __machine_arch_type; # define machine_is_htcwizard() (0) #endif -#ifdef CONFIG_MACH_XSCALE_TREO680 +#ifdef CONFIG_MACH_TREO680 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_XSCALE_TREO680 +# define machine_arch_type MACH_TYPE_TREO680 # endif -# define machine_is_xscale_treo680() (machine_arch_type == MACH_TYPE_XSCALE_TREO680) +# define machine_is_treo680() (machine_arch_type == MACH_TYPE_TREO680) #else -# define machine_is_xscale_treo680() (0) +# define machine_is_treo680() (0) #endif #ifdef CONFIG_MACH_TECON_TMEZON @@ -18945,52 +19066,52 @@ extern unsigned int __machine_arch_type; # define machine_is_sideoatsgrama() (0) #endif -#ifdef CONFIG_MACH_PALMTREO700P +#ifdef CONFIG_MACH_TREO700P # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PALMTREO700P +# define machine_arch_type MACH_TYPE_TREO700P # endif -# define machine_is_palmtreo700p() (machine_arch_type == MACH_TYPE_PALMTREO700P) +# define machine_is_treo700p() (machine_arch_type == MACH_TYPE_TREO700P) #else -# define machine_is_palmtreo700p() (0) +# define machine_is_treo700p() (0) #endif -#ifdef CONFIG_MACH_PALMTREO700W +#ifdef CONFIG_MACH_TREO700W # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PALMTREO700W +# define machine_arch_type MACH_TYPE_TREO700W # endif -# define machine_is_palmtreo700w() (machine_arch_type == MACH_TYPE_PALMTREO700W) +# define machine_is_treo700w() (machine_arch_type == MACH_TYPE_TREO700W) #else -# define machine_is_palmtreo700w() (0) +# define machine_is_treo700w() (0) #endif -#ifdef CONFIG_MACH_PALMTREO750 +#ifdef CONFIG_MACH_TREO750 # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PALMTREO750 +# define machine_arch_type MACH_TYPE_TREO750 # endif -# define machine_is_palmtreo750() (machine_arch_type == MACH_TYPE_PALMTREO750) +# define machine_is_treo750() (machine_arch_type == MACH_TYPE_TREO750) #else -# define machine_is_palmtreo750() (0) +# define machine_is_treo750() (0) #endif -#ifdef CONFIG_MACH_PALMTREO755P +#ifdef CONFIG_MACH_TREO755P # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_PALMTREO755P +# define machine_arch_type MACH_TYPE_TREO755P # endif -# define machine_is_palmtreo755p() (machine_arch_type == MACH_TYPE_PALMTREO755P) +# define machine_is_treo755p() (machine_arch_type == MACH_TYPE_TREO755P) #else -# define machine_is_palmtreo755p() (0) +# define machine_is_treo755p() (0) #endif #ifdef CONFIG_MACH_EZREGANUT9200 @@ -22581,14 +22702,14 @@ extern unsigned int __machine_arch_type; # define machine_is_stmp37xx() (0) #endif -#ifdef CONFIG_MACH_STMP38XX +#ifdef CONFIG_MACH_STMP378X # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_STMP38XX +# define machine_arch_type MACH_TYPE_STMP378X # endif -# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP38XX) +# define machine_is_stmp378x() (machine_arch_type == MACH_TYPE_STMP378X) #else # define machine_is_stmp378x() (0) #endif @@ -23733,16 +23854,16 @@ extern unsigned int __machine_arch_type; # define machine_is_deister_eyecam() (0) #endif -#ifdef CONFIG_MACH_AT91SAM9M10EK +#ifdef CONFIG_MACH_AT91SAM9M10G45EK # ifdef machine_arch_type # undef machine_arch_type # define machine_arch_type __machine_arch_type # else -# define machine_arch_type MACH_TYPE_AT91SAM9M10EK +# define machine_arch_type MACH_TYPE_AT91SAM9M10G45EK # endif -# define machine_is_at91sam9m10ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10EK) +# define machine_is_at91sam9m10g45ek() (machine_arch_type == MACH_TYPE_AT91SAM9M10G45EK) #else -# define machine_is_at91sam9m10ek() (0) +# define machine_is_at91sam9m10g45ek() (0) #endif #ifdef CONFIG_MACH_LINKSTATION_PRODUO @@ -27417,6 +27538,1458 @@ extern unsigned int __machine_arch_type; # define machine_is_smallogger() (0) #endif +#ifdef CONFIG_MACH_CCW9P9215 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9P9215 +# endif +# define machine_is_ccw9p9215() (machine_arch_type == MACH_TYPE_CCW9P9215) +#else +# define machine_is_ccw9p9215() (0) +#endif + +#ifdef CONFIG_MACH_DM355_LEOPARD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DM355_LEOPARD +# endif +# define machine_is_dm355_leopard() (machine_arch_type == MACH_TYPE_DM355_LEOPARD) +#else +# define machine_is_dm355_leopard() (0) +#endif + +#ifdef CONFIG_MACH_TS219 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TS219 +# endif +# define machine_is_ts219() (machine_arch_type == MACH_TYPE_TS219) +#else +# define machine_is_ts219() (0) +#endif + +#ifdef CONFIG_MACH_TNY_A9263 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TNY_A9263 +# endif +# define machine_is_tny_a9263() (machine_arch_type == MACH_TYPE_TNY_A9263) +#else +# define machine_is_tny_a9263() (0) +#endif + +#ifdef CONFIG_MACH_APOLLO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_APOLLO +# endif +# define machine_is_apollo() (machine_arch_type == MACH_TYPE_APOLLO) +#else +# define machine_is_apollo() (0) +#endif + +#ifdef CONFIG_MACH_AT91CAP9STK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91CAP9STK +# endif +# define machine_is_at91cap9stk() (machine_arch_type == MACH_TYPE_AT91CAP9STK) +#else +# define machine_is_at91cap9stk() (0) +#endif + +#ifdef CONFIG_MACH_SPC300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPC300 +# endif +# define machine_is_spc300() (machine_arch_type == MACH_TYPE_SPC300) +#else +# define machine_is_spc300() (0) +#endif + +#ifdef CONFIG_MACH_EKO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EKO +# endif +# define machine_is_eko() (machine_arch_type == MACH_TYPE_EKO) +#else +# define machine_is_eko() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443 +# endif +# define machine_is_ccw9m2443() (machine_arch_type == MACH_TYPE_CCW9M2443) +#else +# define machine_is_ccw9m2443() (0) +#endif + +#ifdef CONFIG_MACH_CCW9M2443JS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CCW9M2443JS +# endif +# define machine_is_ccw9m2443js() (machine_arch_type == MACH_TYPE_CCW9M2443JS) +#else +# define machine_is_ccw9m2443js() (0) +#endif + +#ifdef CONFIG_MACH_M2M_ROUTER_DEVICE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_M2M_ROUTER_DEVICE +# endif +# define machine_is_m2m_router_device() (machine_arch_type == MACH_TYPE_M2M_ROUTER_DEVICE) +#else +# define machine_is_m2m_router_device() (0) +#endif + +#ifdef CONFIG_MACH_STAR9104NAS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STAR9104NAS +# endif +# define machine_is_str9104nas() (machine_arch_type == MACH_TYPE_STAR9104NAS) +#else +# define machine_is_str9104nas() (0) +#endif + +#ifdef CONFIG_MACH_PCA100 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PCA100 +# endif +# define machine_is_pca100() (machine_arch_type == MACH_TYPE_PCA100) +#else +# define machine_is_pca100() (0) +#endif + +#ifdef CONFIG_MACH_Z3_DM365_MOD_01 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_Z3_DM365_MOD_01 +# endif +# define machine_is_z3_dm365_mod_01() (machine_arch_type == MACH_TYPE_Z3_DM365_MOD_01) +#else +# define machine_is_z3_dm365_mod_01() (0) +#endif + +#ifdef CONFIG_MACH_HIPOX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HIPOX +# endif +# define machine_is_hipox() (machine_arch_type == MACH_TYPE_HIPOX) +#else +# define machine_is_hipox() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_PITEDS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_PITEDS +# endif +# define machine_is_omap3_piteds() (machine_arch_type == MACH_TYPE_OMAP3_PITEDS) +#else +# define machine_is_omap3_piteds() (0) +#endif + +#ifdef CONFIG_MACH_BM150R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BM150R +# endif +# define machine_is_bm150r() (machine_arch_type == MACH_TYPE_BM150R) +#else +# define machine_is_bm150r() (0) +#endif + +#ifdef CONFIG_MACH_TBONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TBONE +# endif +# define machine_is_tbone() (machine_arch_type == MACH_TYPE_TBONE) +#else +# define machine_is_tbone() (0) +#endif + +#ifdef CONFIG_MACH_MERLIN +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MERLIN +# endif +# define machine_is_merlin() (machine_arch_type == MACH_TYPE_MERLIN) +#else +# define machine_is_merlin() (0) +#endif + +#ifdef CONFIG_MACH_FALCON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_FALCON +# endif +# define machine_is_falcon() (machine_arch_type == MACH_TYPE_FALCON) +#else +# define machine_is_falcon() (0) +#endif + +#ifdef CONFIG_MACH_DAVINCI_DA850_EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DAVINCI_DA850_EVM +# endif +# define machine_is_davinci_da850_evm() (machine_arch_type == MACH_TYPE_DAVINCI_DA850_EVM) +#else +# define machine_is_davinci_da850_evm() (0) +#endif + +#ifdef CONFIG_MACH_S5P6440 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_S5P6440 +# endif +# define machine_is_s5p6440() (machine_arch_type == MACH_TYPE_S5P6440) +#else +# define machine_is_s5p6440() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G10EK +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G10EK +# endif +# define machine_is_at91sam9g10ek() (machine_arch_type == MACH_TYPE_AT91SAM9G10EK) +#else +# define machine_is_at91sam9g10ek() (0) +#endif + +#ifdef CONFIG_MACH_OMAP_4430SDP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP_4430SDP +# endif +# define machine_is_omap_4430sdp() (machine_arch_type == MACH_TYPE_OMAP_4430SDP) +#else +# define machine_is_omap_4430sdp() (0) +#endif + +#ifdef CONFIG_MACH_LPC313X +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LPC313X +# endif +# define machine_is_lpc313x() (machine_arch_type == MACH_TYPE_LPC313X) +#else +# define machine_is_lpc313x() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_ZN5 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_ZN5 +# endif +# define machine_is_magx_zn5() (machine_arch_type == MACH_TYPE_MAGX_ZN5) +#else +# define machine_is_magx_zn5() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_EM30 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_EM30 +# endif +# define machine_is_magx_em30() (machine_arch_type == MACH_TYPE_MAGX_EM30) +#else +# define machine_is_magx_em30() (0) +#endif + +#ifdef CONFIG_MACH_MAGX_VE66 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAGX_VE66 +# endif +# define machine_is_magx_ve66() (machine_arch_type == MACH_TYPE_MAGX_VE66) +#else +# define machine_is_magx_ve66() (0) +#endif + +#ifdef CONFIG_MACH_MEESC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MEESC +# endif +# define machine_is_meesc() (machine_arch_type == MACH_TYPE_MEESC) +#else +# define machine_is_meesc() (0) +#endif + +#ifdef CONFIG_MACH_OTC570 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OTC570 +# endif +# define machine_is_otc570() (machine_arch_type == MACH_TYPE_OTC570) +#else +# define machine_is_otc570() (0) +#endif + +#ifdef CONFIG_MACH_BCU2412 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BCU2412 +# endif +# define machine_is_bcu2412() (machine_arch_type == MACH_TYPE_BCU2412) +#else +# define machine_is_bcu2412() (0) +#endif + +#ifdef CONFIG_MACH_BEACON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BEACON +# endif +# define machine_is_beacon() (machine_arch_type == MACH_TYPE_BEACON) +#else +# define machine_is_beacon() (0) +#endif + +#ifdef CONFIG_MACH_ACTIA_TGW +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ACTIA_TGW +# endif +# define machine_is_actia_tgw() (machine_arch_type == MACH_TYPE_ACTIA_TGW) +#else +# define machine_is_actia_tgw() (0) +#endif + +#ifdef CONFIG_MACH_E4430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_E4430 +# endif +# define machine_is_e4430() (machine_arch_type == MACH_TYPE_E4430) +#else +# define machine_is_e4430() (0) +#endif + +#ifdef CONFIG_MACH_QL300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QL300 +# endif +# define machine_is_ql300() (machine_arch_type == MACH_TYPE_QL300) +#else +# define machine_is_ql300() (0) +#endif + +#ifdef CONFIG_MACH_BTMAVB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAVB101 +# endif +# define machine_is_btmavb101() (machine_arch_type == MACH_TYPE_BTMAVB101) +#else +# define machine_is_btmavb101() (0) +#endif + +#ifdef CONFIG_MACH_BTMAWB101 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMAWB101 +# endif +# define machine_is_btmawb101() (machine_arch_type == MACH_TYPE_BTMAWB101) +#else +# define machine_is_btmawb101() (0) +#endif + +#ifdef CONFIG_MACH_SQ201 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SQ201 +# endif +# define machine_is_sq201() (machine_arch_type == MACH_TYPE_SQ201) +#else +# define machine_is_sq201() (0) +#endif + +#ifdef CONFIG_MACH_QUATRO45XX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_QUATRO45XX +# endif +# define machine_is_quatro45xx() (machine_arch_type == MACH_TYPE_QUATRO45XX) +#else +# define machine_is_quatro45xx() (0) +#endif + +#ifdef CONFIG_MACH_OPENPAD +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OPENPAD +# endif +# define machine_is_openpad() (machine_arch_type == MACH_TYPE_OPENPAD) +#else +# define machine_is_openpad() (0) +#endif + +#ifdef CONFIG_MACH_TX25 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TX25 +# endif +# define machine_is_tx25() (machine_arch_type == MACH_TYPE_TX25) +#else +# define machine_is_tx25() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_TORPEDO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_TORPEDO +# endif +# define machine_is_omap3_torpedo() (machine_arch_type == MACH_TYPE_OMAP3_TORPEDO) +#else +# define machine_is_omap3_torpedo() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_K +# endif +# define machine_is_htcraphael_k() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_K) +#else +# define machine_is_htcraphael_k() (0) +#endif + +#ifdef CONFIG_MACH_LAL43 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LAL43 +# endif +# define machine_is_lal43() (machine_arch_type == MACH_TYPE_LAL43) +#else +# define machine_is_lal43() (0) +#endif + +#ifdef CONFIG_MACH_HTCRAPHAEL_CDMA500 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCRAPHAEL_CDMA500 +# endif +# define machine_is_htcraphael_cdma500() (machine_arch_type == MACH_TYPE_HTCRAPHAEL_CDMA500) +#else +# define machine_is_htcraphael_cdma500() (0) +#endif + +#ifdef CONFIG_MACH_ANW6410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ANW6410 +# endif +# define machine_is_anw6410() (machine_arch_type == MACH_TYPE_ANW6410) +#else +# define machine_is_anw6410() (0) +#endif + +#ifdef CONFIG_MACH_HTCPROPHET +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HTCPROPHET +# endif +# define machine_is_htcprophet() (machine_arch_type == MACH_TYPE_HTCPROPHET) +#else +# define machine_is_htcprophet() (0) +#endif + +#ifdef CONFIG_MACH_CFA_10022 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CFA_10022 +# endif +# define machine_is_cfa_10022() (machine_arch_type == MACH_TYPE_CFA_10022) +#else +# define machine_is_cfa_10022() (0) +#endif + +#ifdef CONFIG_MACH_IMX27_VISSTRIM_M10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IMX27_VISSTRIM_M10 +# endif +# define machine_is_imx27_visstrim_m10() (machine_arch_type == MACH_TYPE_IMX27_VISSTRIM_M10) +#else +# define machine_is_imx27_visstrim_m10() (0) +#endif + +#ifdef CONFIG_MACH_PX2IMX27 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PX2IMX27 +# endif +# define machine_is_px2imx27() (machine_arch_type == MACH_TYPE_PX2IMX27) +#else +# define machine_is_px2imx27() (0) +#endif + +#ifdef CONFIG_MACH_STM3210E_EVAL +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STM3210E_EVAL +# endif +# define machine_is_stm3210e_eval() (machine_arch_type == MACH_TYPE_STM3210E_EVAL) +#else +# define machine_is_stm3210e_eval() (0) +#endif + +#ifdef CONFIG_MACH_DVS10 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DVS10 +# endif +# define machine_is_dvs10() (machine_arch_type == MACH_TYPE_DVS10) +#else +# define machine_is_dvs10() (0) +#endif + +#ifdef CONFIG_MACH_PORTUXG20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PORTUXG20 +# endif +# define machine_is_portuxg20() (machine_arch_type == MACH_TYPE_PORTUXG20) +#else +# define machine_is_portuxg20() (0) +#endif + +#ifdef CONFIG_MACH_ARM_SPV +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_SPV +# endif +# define machine_is_arm_spv() (machine_arch_type == MACH_TYPE_ARM_SPV) +#else +# define machine_is_arm_spv() (0) +#endif + +#ifdef CONFIG_MACH_SMDKC110 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SMDKC110 +# endif +# define machine_is_smdkc110() (machine_arch_type == MACH_TYPE_SMDKC110) +#else +# define machine_is_smdkc110() (0) +#endif + +#ifdef CONFIG_MACH_CABESPRESSO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CABESPRESSO +# endif +# define machine_is_cabespresso() (machine_arch_type == MACH_TYPE_CABESPRESSO) +#else +# define machine_is_cabespresso() (0) +#endif + +#ifdef CONFIG_MACH_HMC800 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMC800 +# endif +# define machine_is_hmc800() (machine_arch_type == MACH_TYPE_HMC800) +#else +# define machine_is_hmc800() (0) +#endif + +#ifdef CONFIG_MACH_SHOLES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SHOLES +# endif +# define machine_is_sholes() (machine_arch_type == MACH_TYPE_SHOLES) +#else +# define machine_is_sholes() (0) +#endif + +#ifdef CONFIG_MACH_BTMXC31 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BTMXC31 +# endif +# define machine_is_btmxc31() (machine_arch_type == MACH_TYPE_BTMXC31) +#else +# define machine_is_btmxc31() (0) +#endif + +#ifdef CONFIG_MACH_DT501 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT501 +# endif +# define machine_is_dt501() (machine_arch_type == MACH_TYPE_DT501) +#else +# define machine_is_dt501() (0) +#endif + +#ifdef CONFIG_MACH_KTX +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_KTX +# endif +# define machine_is_ktx() (machine_arch_type == MACH_TYPE_KTX) +#else +# define machine_is_ktx() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3517EVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3517EVM +# endif +# define machine_is_omap3517evm() (machine_arch_type == MACH_TYPE_OMAP3517EVM) +#else +# define machine_is_omap3517evm() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_V2 +# endif +# define machine_is_netspace_v2() (machine_arch_type == MACH_TYPE_NETSPACE_V2) +#else +# define machine_is_netspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_NETSPACE_MAX_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NETSPACE_MAX_V2 +# endif +# define machine_is_netspace_max_v2() (machine_arch_type == MACH_TYPE_NETSPACE_MAX_V2) +#else +# define machine_is_netspace_max_v2() (0) +#endif + +#ifdef CONFIG_MACH_D2NET_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_D2NET_V2 +# endif +# define machine_is_d2net_v2() (machine_arch_type == MACH_TYPE_D2NET_V2) +#else +# define machine_is_d2net_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET2BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET2BIG_V2 +# endif +# define machine_is_net2big_v2() (machine_arch_type == MACH_TYPE_NET2BIG_V2) +#else +# define machine_is_net2big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET4BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET4BIG_V2 +# endif +# define machine_is_net4big_v2() (machine_arch_type == MACH_TYPE_NET4BIG_V2) +#else +# define machine_is_net4big_v2() (0) +#endif + +#ifdef CONFIG_MACH_NET5BIG_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_NET5BIG_V2 +# endif +# define machine_is_net5big_v2() (machine_arch_type == MACH_TYPE_NET5BIG_V2) +#else +# define machine_is_net5big_v2() (0) +#endif + +#ifdef CONFIG_MACH_ENDB2443 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ENDB2443 +# endif +# define machine_is_endb2443() (machine_arch_type == MACH_TYPE_ENDB2443) +#else +# define machine_is_endb2443() (0) +#endif + +#ifdef CONFIG_MACH_INETSPACE_V2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_INETSPACE_V2 +# endif +# define machine_is_inetspace_v2() (machine_arch_type == MACH_TYPE_INETSPACE_V2) +#else +# define machine_is_inetspace_v2() (0) +#endif + +#ifdef CONFIG_MACH_TROS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_TROS +# endif +# define machine_is_tros() (machine_arch_type == MACH_TYPE_TROS) +#else +# define machine_is_tros() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_HOMER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_HOMER +# endif +# define machine_is_pelco_homer() (machine_arch_type == MACH_TYPE_PELCO_HOMER) +#else +# define machine_is_pelco_homer() (0) +#endif + +#ifdef CONFIG_MACH_OFSP8 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OFSP8 +# endif +# define machine_is_ofsp8() (machine_arch_type == MACH_TYPE_OFSP8) +#else +# define machine_is_ofsp8() (0) +#endif + +#ifdef CONFIG_MACH_AT91SAM9G45EKES +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_AT91SAM9G45EKES +# endif +# define machine_is_at91sam9g45ekes() (machine_arch_type == MACH_TYPE_AT91SAM9G45EKES) +#else +# define machine_is_at91sam9g45ekes() (0) +#endif + +#ifdef CONFIG_MACH_GUF_CUPID +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GUF_CUPID +# endif +# define machine_is_guf_cupid() (machine_arch_type == MACH_TYPE_GUF_CUPID) +#else +# define machine_is_guf_cupid() (0) +#endif + +#ifdef CONFIG_MACH_EAB1R +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_EAB1R +# endif +# define machine_is_eab1r() (machine_arch_type == MACH_TYPE_EAB1R) +#else +# define machine_is_eab1r() (0) +#endif + +#ifdef CONFIG_MACH_DESIREC +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DESIREC +# endif +# define machine_is_desirec() (machine_arch_type == MACH_TYPE_DESIREC) +#else +# define machine_is_desirec() (0) +#endif + +#ifdef CONFIG_MACH_CORDOBA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CORDOBA +# endif +# define machine_is_cordoba() (machine_arch_type == MACH_TYPE_CORDOBA) +#else +# define machine_is_cordoba() (0) +#endif + +#ifdef CONFIG_MACH_IRVINE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_IRVINE +# endif +# define machine_is_irvine() (machine_arch_type == MACH_TYPE_IRVINE) +#else +# define machine_is_irvine() (0) +#endif + +#ifdef CONFIG_MACH_SFF772 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFF772 +# endif +# define machine_is_sff772() (machine_arch_type == MACH_TYPE_SFF772) +#else +# define machine_is_sff772() (0) +#endif + +#ifdef CONFIG_MACH_PELCO_MILANO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PELCO_MILANO +# endif +# define machine_is_pelco_milano() (machine_arch_type == MACH_TYPE_PELCO_MILANO) +#else +# define machine_is_pelco_milano() (0) +#endif + +#ifdef CONFIG_MACH_PC7302 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PC7302 +# endif +# define machine_is_pc7302() (machine_arch_type == MACH_TYPE_PC7302) +#else +# define machine_is_pc7302() (0) +#endif + +#ifdef CONFIG_MACH_BIP6000 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BIP6000 +# endif +# define machine_is_bip6000() (machine_arch_type == MACH_TYPE_BIP6000) +#else +# define machine_is_bip6000() (0) +#endif + +#ifdef CONFIG_MACH_SILVERMOON +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SILVERMOON +# endif +# define machine_is_silvermoon() (machine_arch_type == MACH_TYPE_SILVERMOON) +#else +# define machine_is_silvermoon() (0) +#endif + +#ifdef CONFIG_MACH_VC0830 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VC0830 +# endif +# define machine_is_vc0830() (machine_arch_type == MACH_TYPE_VC0830) +#else +# define machine_is_vc0830() (0) +#endif + +#ifdef CONFIG_MACH_DT430 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_DT430 +# endif +# define machine_is_dt430() (machine_arch_type == MACH_TYPE_DT430) +#else +# define machine_is_dt430() (0) +#endif + +#ifdef CONFIG_MACH_JI42PF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_JI42PF +# endif +# define machine_is_ji42pf() (machine_arch_type == MACH_TYPE_JI42PF) +#else +# define machine_is_ji42pf() (0) +#endif + +#ifdef CONFIG_MACH_GNET_KSM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_KSM +# endif +# define machine_is_gnet_ksm() (machine_arch_type == MACH_TYPE_GNET_KSM) +#else +# define machine_is_gnet_ksm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGM +# endif +# define machine_is_gnet_sgm() (machine_arch_type == MACH_TYPE_GNET_SGM) +#else +# define machine_is_gnet_sgm() (0) +#endif + +#ifdef CONFIG_MACH_GNET_SGR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_GNET_SGR +# endif +# define machine_is_gnet_sgr() (machine_arch_type == MACH_TYPE_GNET_SGR) +#else +# define machine_is_gnet_sgr() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_ICETEKEVM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_ICETEKEVM +# endif +# define machine_is_omap3_icetekevm() (machine_arch_type == MACH_TYPE_OMAP3_ICETEKEVM) +#else +# define machine_is_omap3_icetekevm() (0) +#endif + +#ifdef CONFIG_MACH_PNP +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_PNP +# endif +# define machine_is_pnp() (machine_arch_type == MACH_TYPE_PNP) +#else +# define machine_is_pnp() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_K +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_K +# endif +# define machine_is_ctera_2bay_k() (machine_arch_type == MACH_TYPE_CTERA_2BAY_K) +#else +# define machine_is_ctera_2bay_k() (0) +#endif + +#ifdef CONFIG_MACH_CTERA_2BAY_U +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_CTERA_2BAY_U +# endif +# define machine_is_ctera_2bay_u() (machine_arch_type == MACH_TYPE_CTERA_2BAY_U) +#else +# define machine_is_ctera_2bay_u() (0) +#endif + +#ifdef CONFIG_MACH_SAS_C +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SAS_C +# endif +# define machine_is_sas_c() (machine_arch_type == MACH_TYPE_SAS_C) +#else +# define machine_is_sas_c() (0) +#endif + +#ifdef CONFIG_MACH_VMA2315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMA2315 +# endif +# define machine_is_vma2315() (machine_arch_type == MACH_TYPE_VMA2315) +#else +# define machine_is_vma2315() (0) +#endif + +#ifdef CONFIG_MACH_VCS +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VCS +# endif +# define machine_is_vcs() (machine_arch_type == MACH_TYPE_VCS) +#else +# define machine_is_vcs() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR600 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR600 +# endif +# define machine_is_spear600() (machine_arch_type == MACH_TYPE_SPEAR600) +#else +# define machine_is_spear600() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR300 +# endif +# define machine_is_spear300() (machine_arch_type == MACH_TYPE_SPEAR300) +#else +# define machine_is_spear300() (0) +#endif + +#ifdef CONFIG_MACH_SPEAR1300 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SPEAR1300 +# endif +# define machine_is_spear1300() (machine_arch_type == MACH_TYPE_SPEAR1300) +#else +# define machine_is_spear1300() (0) +#endif + +#ifdef CONFIG_MACH_LILLY1131 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LILLY1131 +# endif +# define machine_is_lilly1131() (machine_arch_type == MACH_TYPE_LILLY1131) +#else +# define machine_is_lilly1131() (0) +#endif + +#ifdef CONFIG_MACH_ARVOO_AX301 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARVOO_AX301 +# endif +# define machine_is_arvoo_ax301() (machine_arch_type == MACH_TYPE_ARVOO_AX301) +#else +# define machine_is_arvoo_ax301() (0) +#endif + +#ifdef CONFIG_MACH_MAPPHONE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MAPPHONE +# endif +# define machine_is_mapphone() (machine_arch_type == MACH_TYPE_MAPPHONE) +#else +# define machine_is_mapphone() (0) +#endif + +#ifdef CONFIG_MACH_LEGEND +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LEGEND +# endif +# define machine_is_legend() (machine_arch_type == MACH_TYPE_LEGEND) +#else +# define machine_is_legend() (0) +#endif + +#ifdef CONFIG_MACH_SALSA +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SALSA +# endif +# define machine_is_salsa() (machine_arch_type == MACH_TYPE_SALSA) +#else +# define machine_is_salsa() (0) +#endif + +#ifdef CONFIG_MACH_LOUNGE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_LOUNGE +# endif +# define machine_is_lounge() (machine_arch_type == MACH_TYPE_LOUNGE) +#else +# define machine_is_lounge() (0) +#endif + +#ifdef CONFIG_MACH_VISION +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VISION +# endif +# define machine_is_vision() (machine_arch_type == MACH_TYPE_VISION) +#else +# define machine_is_vision() (0) +#endif + +#ifdef CONFIG_MACH_VMB20 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VMB20 +# endif +# define machine_is_vmb20() (machine_arch_type == MACH_TYPE_VMB20) +#else +# define machine_is_vmb20() (0) +#endif + +#ifdef CONFIG_MACH_HY2410 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY2410 +# endif +# define machine_is_hy2410() (machine_arch_type == MACH_TYPE_HY2410) +#else +# define machine_is_hy2410() (0) +#endif + +#ifdef CONFIG_MACH_HY9315 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HY9315 +# endif +# define machine_is_hy9315() (machine_arch_type == MACH_TYPE_HY9315) +#else +# define machine_is_hy9315() (0) +#endif + +#ifdef CONFIG_MACH_BULLWINKLE +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_BULLWINKLE +# endif +# define machine_is_bullwinkle() (machine_arch_type == MACH_TYPE_BULLWINKLE) +#else +# define machine_is_bullwinkle() (0) +#endif + +#ifdef CONFIG_MACH_ARM_ULTIMATOR2 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_ARM_ULTIMATOR2 +# endif +# define machine_is_arm_ultimator2() (machine_arch_type == MACH_TYPE_ARM_ULTIMATOR2) +#else +# define machine_is_arm_ultimator2() (0) +#endif + +#ifdef CONFIG_MACH_VS_V210 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V210 +# endif +# define machine_is_vs_v210() (machine_arch_type == MACH_TYPE_VS_V210) +#else +# define machine_is_vs_v210() (0) +#endif + +#ifdef CONFIG_MACH_VS_V212 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VS_V212 +# endif +# define machine_is_vs_v212() (machine_arch_type == MACH_TYPE_VS_V212) +#else +# define machine_is_vs_v212() (0) +#endif + +#ifdef CONFIG_MACH_HMT +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_HMT +# endif +# define machine_is_hmt() (machine_arch_type == MACH_TYPE_HMT) +#else +# define machine_is_hmt() (0) +#endif + +#ifdef CONFIG_MACH_SUEN3 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SUEN3 +# endif +# define machine_is_suen3() (machine_arch_type == MACH_TYPE_SUEN3) +#else +# define machine_is_suen3() (0) +#endif + +#ifdef CONFIG_MACH_VESPER +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_VESPER +# endif +# define machine_is_vesper() (machine_arch_type == MACH_TYPE_VESPER) +#else +# define machine_is_vesper() (0) +#endif + +#ifdef CONFIG_MACH_STR9 +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_STR9 +# endif +# define machine_is_str9() (machine_arch_type == MACH_TYPE_STR9) +#else +# define machine_is_str9() (0) +#endif + +#ifdef CONFIG_MACH_OMAP3_WL_FF +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_OMAP3_WL_FF +# endif +# define machine_is_omap3_wl_ff() (machine_arch_type == MACH_TYPE_OMAP3_WL_FF) +#else +# define machine_is_omap3_wl_ff() (0) +#endif + +#ifdef CONFIG_MACH_SIMCOM +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SIMCOM +# endif +# define machine_is_simcom() (machine_arch_type == MACH_TYPE_SIMCOM) +#else +# define machine_is_simcom() (0) +#endif + +#ifdef CONFIG_MACH_MCWEBIO +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_MCWEBIO +# endif +# define machine_is_mcwebio() (machine_arch_type == MACH_TYPE_MCWEBIO) +#else +# define machine_is_mcwebio() (0) +#endif + /* * These have not yet been registered */ -- cgit v1.3.1 From 33b1d3f43a16fbb79004075ce89ae4e618b288a2 Mon Sep 17 00:00:00 2001 From: Daniel Gorsulowski Date: Tue, 30 Jun 2009 21:03:37 +0200 Subject: at91: Add esd gmbh MEESC board support This patch adds support for esd gmbh MEESC board. The MEESC is based on an Atmel AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/esd/meesc/Makefile | 55 ++++++++++++ board/esd/meesc/config.mk | 1 + board/esd/meesc/meesc.c | 198 ++++++++++++++++++++++++++++++++++++++++++++ board/esd/meesc/partition.c | 37 +++++++++ include/configs/meesc.h | 188 +++++++++++++++++++++++++++++++++++++++++ 8 files changed, 487 insertions(+) create mode 100644 board/esd/meesc/Makefile create mode 100644 board/esd/meesc/config.mk create mode 100644 board/esd/meesc/meesc.c create mode 100644 board/esd/meesc/partition.c create mode 100644 include/configs/meesc.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index ade25ae33ef..b0e370f7b3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -537,6 +537,10 @@ Peter Figuli wepep250 xscale +Daniel Gorsulowski + + meesc ARM926EJS (AT91SAM9263 SoC) + Marius Gröger impa7 ARM720T (EP7211) diff --git a/MAKEALL b/MAKEALL index 3777f4228e1..027207d1a31 100755 --- a/MAKEALL +++ b/MAKEALL @@ -588,6 +588,7 @@ LIST_at91=" \ cmc_pu2 \ csb637 \ kb9202 \ + meesc \ mp2usb \ m501sk \ pm9261 \ diff --git a/Makefile b/Makefile index 4c9884c5669..0ae1d360226 100644 --- a/Makefile +++ b/Makefile @@ -2791,6 +2791,9 @@ at91sam9rlek_config : unconfig fi; @$(MKCONFIG) -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91 +meesc_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs meesc esd at91 + pm9261_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs pm9261 ronetix at91 diff --git a/board/esd/meesc/Makefile b/board/esd/meesc/Makefile new file mode 100644 index 00000000000..2dd6b25c948 --- /dev/null +++ b/board/esd/meesc/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2008 +# Stelian Pop +# Lead Tech Design +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y += $(BOARD).o +COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/esd/meesc/config.mk b/board/esd/meesc/config.mk new file mode 100644 index 00000000000..9ce161e55f0 --- /dev/null +++ b/board/esd/meesc/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x21f00000 diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c new file mode 100644 index 00000000000..636d0ed5f20 --- /dev/null +++ b/board/esd/meesc/meesc.c @@ -0,0 +1,198 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2009 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +static int hw_rev = -1; /* hardware revision */ + +int get_hw_rev(void) +{ + if (hw_rev >= 0) + return hw_rev; + + hw_rev = at91_get_gpio_value(AT91_PIN_PB19); + hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; + hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + + if (hw_rev == 15) + hw_rev = 0; + + return hw_rev; +} + +#ifdef CONFIG_CMD_NAND +static void meesc_nand_hw_init(void) +{ + unsigned long csa; + + /* Enable CS3 */ + csa = at91_sys_read(AT91_MATRIX_EBI0CSA); + at91_sys_write(AT91_MATRIX_EBI0CSA, + csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | +#ifdef CONFIG_SYS_NAND_DBW_16 + AT91_SMC_DBW_16 | +#else /* CONFIG_SYS_NAND_DBW_8 */ + AT91_SMC_DBW_8 | +#endif + AT91_SMC_TDF_(2)); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif /* CONFIG_CMD_NAND */ + +#ifdef CONFIG_MACB +static void meesc_macb_hw_init(void) +{ + /* Enable clock */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + at91_macb_hw_init(); +} +#endif + +/* + * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT + * controller debugging + * The ET1100 is located at physical address 0x70000000 + * Its process memory is located at physical address 0x70001000 + */ +static void meesc_ethercat_hw_init(void) +{ + /* Configure SMC EBI1_CS0 for EtherCAT */ + at91_sys_write(AT91_SMC1_SETUP(0), + AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC1_PULSE(0), + AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | + AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9)); + at91_sys_write(AT91_SMC1_CYCLE(0), + AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5)); + /* Configure behavior at external wait signal, byte-select mode, 16 bit + data bus width, none data float wait states and TDF optimization */ + at91_sys_write(AT91_SMC1_MODE(0), + AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | + AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | + AT91_SMC_TDFMODE); + + /* Configure RDY/BSY */ + at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27)); + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); +#endif + return rc; +} + +int checkboard(void) +{ + char str[32]; + + puts("Board: esd CAN-EtherCAT Gateway"); + if (getenv_r("serial#", str, sizeof(str)) > 0) { + puts(", serial# "); + puts(str); + } + printf("\nHardware-revision: 1.%d\n", get_hw_rev()); + printf("Mach-type: %lu\n", gd->bd->bi_arch_number); + return 0; +} + +int board_init(void) +{ + /* Peripheral Clock Enable Register */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE); + + /* arch number of MEESC-Board */ + gd->bd->bi_arch_number = MACH_TYPE_MEESC; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + at91_serial_hw_init(); +#ifdef CONFIG_CMD_NAND + meesc_nand_hw_init(); +#endif + meesc_ethercat_hw_init(); +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif +#ifdef CONFIG_MACB + meesc_macb_hw_init(); +#endif +#ifdef CONFIG_AT91_CAN + at91_can_hw_init(); +#endif + return 0; +} diff --git a/board/esd/meesc/partition.c b/board/esd/meesc/partition.c new file mode 100644 index 00000000000..df0e1db34f9 --- /dev/null +++ b/board/esd/meesc/partition.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2008 + * Ulf Samuelsson + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include +#include +#include +#include + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ +}; + +/* define the area offsets */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, + {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, + {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, +}; diff --git a/include/configs/meesc.h b/include/configs/meesc.h new file mode 100644 index 00000000000..28c4de0217a --- /dev/null +++ b/include/configs/meesc.h @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2009 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * Configuation settings for the esd MEESC board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Common stuff */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ +#define CONFIG_MEESC 1 /* Board is esd MEESC */ +#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ +#define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_ENV_OVERWRITE 1 /* necessary on prototypes */ +#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ +#define CONFIG_PREBOOT /* enable preboot variable */ +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#undef CONFIG_USE_IRQ /* don't need IRQ/FIQ stuff */ + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT + +/* + * Hardware drivers + */ + +/* Console output */ +#define CONFIG_ATMEL_USART 1 +#undef CONFIG_USART0 +#undef CONFIG_USART1 +#undef CONFIG_USART2 +#define CONFIG_USART3 1 /* USART 3 is DBGU */ + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_AUTOSCRIPT +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_USB + +#define CONFIG_CMD_PING 1 +#define CONFIG_CMD_DHCP 1 +#define CONFIG_CMD_NAND 1 + +/* LED */ +#define CONFIG_AT91_LED 1 + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x20000000 + +/* DataFlash */ +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH 1 +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +/* NOR flash is not populated, disable it */ +#define CONFIG_SYS_NO_FLASH 1 + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#endif + +/* Ethernet */ +#define CONFIG_MACB 1 +#define CONFIG_RMII 1 +#define CONFIG_NET_MULTI 1 +#define CONFIG_NET_RETRY_COUNT 20 +#undef CONFIG_RESET_PHY_R + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +#define CONFIG_SYS_USE_DATAFLASH 1 +#undef CONFIG_SYS_USE_NANDFLASH + +#ifdef CONFIG_SYS_USE_DATAFLASH + +/* CAN */ +#define CONFIG_AT91_CAN 1 + +/* bootstrap + u-boot + env + linux in dataflash on CS0 */ +#define CONFIG_ENV_IS_IN_DATAFLASH 1 +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + 0x8400) +#define CONFIG_ENV_OFFSET 0x4200 +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \ + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE 0x4200 +#define CONFIG_BOOTCOMMAND "cp.b C0042000 22000000 210000; bootm" + +#else /* CONFIG_SYS_USE_NANDFLASH */ + +/* bootstrap + u-boot + env + linux in nandflash */ +#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_OFFSET 0x60000 +#define CONFIG_ENV_OFFSET_REDUND 0x80000 +#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ +#define CONFIG_BOOTCOMMAND "nand read 22000000 A0000 200000; bootm" + +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN 0x2D000 +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif -- cgit v1.3.1 From 040f8f63e922bbfb8ba0958bf637f11a917f5c38 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 1 Jul 2009 20:40:41 +0200 Subject: xscale: add support for the polaris board The Polaris board is based on the TrizepsIV module of Keith & Koep (http://www.keith-koep.com). Signed-off-by: Stefano Babic --- MAINTAINERS | 5 +++++ MAKEALL | 2 ++ Makefile | 7 ++++++- board/trizepsiv/conxs.c | 22 ++++++++++++---------- include/configs/trizepsiv.h | 25 ++++++++++++++++++++++--- 5 files changed, 47 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index b0e370f7b3f..41e6830b239 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -501,6 +501,11 @@ Rowel Atienza armadillo ARM720T +Stefano Babic + + polaris xscale + trizepsiv xscale + Dirk Behme omap3_beagle ARM CORTEX-A8 (OMAP3530 SoC) diff --git a/MAKEALL b/MAKEALL index 027207d1a31..e6f6c147de0 100755 --- a/MAKEALL +++ b/MAKEALL @@ -607,7 +607,9 @@ LIST_pxa=" \ innokom \ lubbock \ pleb2 \ + polaris \ pxa255_idp \ + trizepsiv \ wepep250 \ xaeniax \ xm250 \ diff --git a/Makefile b/Makefile index 0ae1d360226..9b9f7bfef2a 100644 --- a/Makefile +++ b/Makefile @@ -3095,8 +3095,13 @@ scpu_config: unconfig pxa255_idp_config: unconfig @$(MKCONFIG) $(@:_config=) arm pxa pxa255_idp +polaris_config \ trizepsiv_config : unconfig - @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv + @mkdir -p $(obj)include + @if [ "$(findstring polaris,$@)" ] ; then \ + echo "#define CONFIG_POLARIS 1" >>$(obj)include/config.h ; \ + fi; + @$(MKCONFIG) -a trizepsiv arm pxa trizepsiv wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 53b6e0014e3..8c1145629f1 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -44,6 +44,11 @@ extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; extern struct serial_device serial_stuart_device; +#if CONFIG_POLARIS +#define BOOT_CONSOLE "serial_stuart" +#else +#define BOOT_CONSOLE "serial_ffuart" +#endif /* ------------------------------------------------------------------------- */ /* @@ -113,17 +118,14 @@ int board_late_init(void) #if defined(CONFIG_SERIAL_MULTI) char *console=getenv("boot_console"); - if ((strcmp(console,"serial_btuart") == 0) || - (strcmp(console,"serial_stuart") == 0) || - (strcmp(console,"serial_ffuart") == 0)) { - setenv("stdout",console); - setenv("stdin", console); - setenv("stderr",console); - } else { - setenv("stdout", "serial"); - setenv("stdin", "serial"); - setenv("stderr", "serial"); + if ((console == NULL) || (strcmp(console,"serial_btuart") && + strcmp(console,"serial_stuart") && + strcmp(console,"serial_ffuart"))) { + console = BOOT_CONSOLE; } + setenv("stdout",console); + setenv("stdin", console); + setenv("stderr",console); #endif return 0; } diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index bfa7157214f..fa5aae8a5c5 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -239,11 +239,17 @@ #define CONFIG_SYS_GRER1_VAL 0x00000000 #define CONFIG_SYS_GRER2_VAL 0x00000000 #define CONFIG_SYS_GRER3_VAL 0x00000000 -#define CONFIG_SYS_GFER0_VAL 0x00000000 + #define CONFIG_SYS_GFER1_VAL 0x00000000 -#define CONFIG_SYS_GFER2_VAL 0x00000000 #define CONFIG_SYS_GFER3_VAL 0x00000020 +#if CONFIG_POLARIS +#define CONFIG_SYS_GFER0_VAL 0x00000001 +#define CONFIG_SYS_GFER2_VAL 0x00200000 +#else +#define CONFIG_SYS_GFER0_VAL 0x00000000 +#define CONFIG_SYS_GFER2_VAL 0x00000000 +#endif #define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ @@ -259,7 +265,11 @@ #define CONFIG_SYS_MSC0_VAL 0x4df84df0 #define CONFIG_SYS_MSC1_VAL 0x7ff87ff4 +#if CONFIG_POLARIS +#define CONFIG_SYS_MSC2_VAL 0xa2697ff8 +#else #define CONFIG_SYS_MSC2_VAL 0xa26936d4 +#endif #define CONFIG_SYS_MDCNFG_VAL 0x880009C9 #define CONFIG_SYS_MDREFR_VAL 0x20ca201e #define CONFIG_SYS_MDMRS_VAL 0x00220022 @@ -280,7 +290,13 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000000 + +#if CONFIG_POLARIS +#define CONFIG_DM9000_BASE 0x0C800000 +#else +#define CONFIG_DM9000_BASE 0x08000000 +#endif + #define DM9000_IO CONFIG_DM9000_BASE #define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) @@ -312,6 +328,9 @@ /* write flash less slowly */ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 +/* Unlock to be used with Intel chips */ +#define CONFIG_SYS_FLASH_PROTECTION 1 + /* Flash environment locations */ #define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ -- cgit v1.3.1 From ee1363f2da3996bafdecdd8f4e48862ebff3f271 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 22 Jun 2009 09:18:37 +0200 Subject: arm nomadik: rename board to nhk8815 This is an error in my side in the initial submission: nobody calls it ""nmdk8815", it's "nomadik hardware kit", nhk8815, instead. Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- Makefile | 6 +- board/st/nhk8815/Makefile | 55 +++++++ board/st/nhk8815/config.mk | 26 ++++ board/st/nhk8815/nhk8815.c | 75 ++++++++++ board/st/nhk8815/platform.S | 340 +++++++++++++++++++++++++++++++++++++++++++ board/st/nmdk8815/Makefile | 55 ------- board/st/nmdk8815/config.mk | 26 ---- board/st/nmdk8815/nmdk8815.c | 75 ---------- board/st/nmdk8815/platform.S | 340 ------------------------------------------- doc/README.nhk8815 | 22 +++ doc/README.nmdk8815 | 22 --- include/configs/nhk8815.h | 168 +++++++++++++++++++++ include/configs/nmdk8815.h | 167 --------------------- 13 files changed, 689 insertions(+), 688 deletions(-) create mode 100644 board/st/nhk8815/Makefile create mode 100644 board/st/nhk8815/config.mk create mode 100644 board/st/nhk8815/nhk8815.c create mode 100644 board/st/nhk8815/platform.S delete mode 100644 board/st/nmdk8815/Makefile delete mode 100644 board/st/nmdk8815/config.mk delete mode 100644 board/st/nmdk8815/nmdk8815.c delete mode 100644 board/st/nmdk8815/platform.S create mode 100644 doc/README.nhk8815 delete mode 100644 doc/README.nmdk8815 create mode 100644 include/configs/nhk8815.h delete mode 100644 include/configs/nmdk8815.h (limited to 'include') diff --git a/Makefile b/Makefile index 9b9f7bfef2a..3877c972098 100644 --- a/Makefile +++ b/Makefile @@ -2854,8 +2854,8 @@ mx1fs2_config : unconfig netstar_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm925t netstar -nmdk8815_config \ -nmdk8815_onenand_config: unconfig +nhk8815_config \ +nhk8815_onenand_config: unconfig @mkdir -p $(obj)include @ > $(obj)include/config.h @if [ "$(findstring _onenand, $@)" ] ; then \ @@ -2864,7 +2864,7 @@ nmdk8815_onenand_config: unconfig else \ $(XECHO) "... configured for Nand Flash"; \ fi - @$(MKCONFIG) -a nmdk8815 arm arm926ejs nmdk8815 st nomadik + @$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik omap1510inn_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm925t omap1510inn diff --git a/board/st/nhk8815/Makefile b/board/st/nhk8815/Makefile new file mode 100644 index 00000000000..b37fe534acc --- /dev/null +++ b/board/st/nhk8815/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2004 +# ARM Ltd. +# Philippe Robin, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := nhk8815.o +SOBJS := platform.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/st/nhk8815/config.mk b/board/st/nhk8815/config.mk new file mode 100644 index 00000000000..590393bd64c --- /dev/null +++ b/board/st/nhk8815/config.mk @@ -0,0 +1,26 @@ +# (C) Copyright 2007 +# STMicroelectronics, +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# +# image should be loaded at 0x01000000 +# + +TEXT_BASE = 0x03F80000 diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c new file mode 100644 index 00000000000..edf46262f5d --- /dev/null +++ b/board/st/nhk8815/nhk8815.c @@ -0,0 +1,75 @@ +/* + * (C) Copyright 2005 + * STMicrolelctronics, + * + * (C) Copyright 2004 + * ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_SHOW_BOOT_PROGRESS +void show_boot_progress(int progress) +{ + printf("%i\n", progress); +} +#endif + +/* + * Miscellaneous platform dependent initialisations + */ +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_NOMADIK; + gd->bd->bi_boot_params = 0x00000100; + writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); + writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); + writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); + writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); + + /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ + writel(0x0000305b, REG_FSMC_BCR1); + writel(0x00033f33, REG_FSMC_BTR1); + + icache_enable(); + return 0; +} + +int misc_init_r(void) +{ + setenv("verify", "n"); + return 0; +} + +int dram_init(void) +{ + /* set dram bank start addr and size */ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + return 0; +} diff --git a/board/st/nhk8815/platform.S b/board/st/nhk8815/platform.S new file mode 100644 index 00000000000..2a671102312 --- /dev/null +++ b/board/st/nhk8815/platform.S @@ -0,0 +1,340 @@ +/* + * Board specific setup info + * + * (C) Copyright 2005 + * STMicrolelctronics, + * + * (C) Copyright 2004, ARM Ltd. + * Philippe Robin, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +.globl lowlevel_init +lowlevel_init: + /* Jump to the flash address */ + ldr r0, =CFG_ONENAND_BASE + + /* + * Make it independent whether we boot from 0x0 or 0x30000000. + * Non-portable: it relies on the knowledge that ip has to be updated + */ + orr ip, ip, r0 /* adjust return address of cpu_init_crit */ + orr lr, lr, r0 /* adjust return address */ + orr pc, pc, r0 /* jump to the normal address */ + nop + + /* Initialize PLL, Remap clear, FSMC, MPMC here! */ + /* What about GPIO, CLCD and UART */ + + /* PLL Initialization */ + /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */ + ldr r0, =NOMADIK_SRC_BASE + + ldr r1, =0x2B013502 + + str r1, [r0, #0x14] + + /* Used to set all the timers clock to 2.4MHZ */ + ldr r1, =0x2AAAA004 + str r1, [r0] + + ldr r1, =0x10000000 + str r1, [r0, #0x10] + + /* FSMC setup ---- */ + ldr r0, =NOMADIK_FSMC_BASE + + ldr r1, =0x10DB /* For 16-bit NOR flash */ + str r1, [r0, #0x08] + + ldr r1, =0x03333333 /* For 16-bit NOR flash */ + str r1, [r0, #0xc] + + /* oneNAND setting */ + ldr r1, =0x0000105B /* BCR0 Prog control register */ + str r1, [r0] + + ldr r1, =0x0A200551 /* BTR0 Prog timing register */ + str r1, [r0, #0x04] + + /* preload the instructions into icache */ + add r0, pc, #0x1F + bic r0, r0, #0x1F + mcr p15, 0, r0, c7, c13, 1 + add r0, r0, #0x20 + mcr p15, 0, r0, c7, c13, 1 + + /* Now Clear Remap */ + ldr r0, =NOMADIK_SRC_BASE + + ldr r1, =0x2004 + str r1, [r0] + + ldr r1, =0x10000000 + str r1, [r0, #0x10] + + ldr r0, =0x101E9000 + ldr r1, =0x2004 + str r1, [r0] + + ldr r0, =NOMADIK_SRC_BASE + ldr r1, =0x2104 + str r1, [r0] + + /* FSMC setup -- */ + mov r0, #(NOMADIK_FSMC_BASE & 0x10000000) + orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF) + + ldr r1, =0x10DB /* For 16-bit NOR flash */ + str r1, [r0, #0x8] + + ldr r1, =0x03333333 /* For 16-bit NOR flash */ + str r1, [r0, #0xc] + + /* MPMC Setup */ + ldr r0, =NOMADIK_MPMC_BASE + + ldr r1, =0xF00003 + str r1, [r0] /* Enable the MPMC and the DLL */ + + ldr r1, =0x183 + str r1, [r0, #0x20] + + ldr r2, =NOMADIK_PMU_BASE + + ldr r1, =0x1111 + str r1, [r2] + + ldr r1, =0x1111 /* Prog the, mand delay strategy */ + str r1, [r0, #0x28] + + ldr r1, =0x103 /* NOP ,mand */ + str r1, [r0, #0x20] + + /* FIXME -- Wait required here */ + + ldr r1, =0x103 /* PALL ,mand*/ + str r1, [r0, #0x20] + + ldr r1, =0x1 + str r1, [r0, #0x24] /* To do at least two auto-refresh */ + + /* FIXME -- Wait required here */ + + /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */ + ldr r1, =0x31 + str r1, [r0, #0x24] + + /* Prog Little Endian, Not defined in 8800 board */ + ldr r1, =0x0 + str r1, [r0, #0x8] + + + ldr r1, =0x2 + str r1, [r0, #0x30] /* Prog tRP timing */ + + ldr r1, =0x4 /* Change for 8815 */ + str r1, [r0, #0x34] /* Prog tRAS timing */ + + ldr r1, =0xB + str r1, [r0, #0x38] /* Prog tSREX timing */ + + + ldr r1, =0x1 + str r1, [r0, #0x44] /* Prog tWR timing */ + + ldr r1, =0x8 + str r1, [r0, #0x48] /* Prog tRC timing */ + + ldr r1, =0xA + str r1, [r0, #0x4C] /* Prog tRFC timing */ + + ldr r1, =0xB + str r1, [r0, #0x50] /* Prog tXSR timing */ + + ldr r1, =0x1 + str r1, [r0, #0x54] /* Prog tRRD timing */ + + ldr r1, =0x1 + str r1, [r0, #0x58] /* Prog tMRD timing */ + + ldr r1, =0x1 + str r1, [r0, #0x5C] /* Prog tCDLR timing */ + + /* DDR-SDRAM MEMORY IS ON BANK0 8815 */ + ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */ + str r1, [r0, #0x104] + + /* SDR-SDRAM MEMORY IS ON BANK1 8815 */ + ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */ + str r1, [r0, #0x124] + /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */ + /* DDR-SDRAM MEMORY IS ON BANK0*/ + + ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */ + str r1, [r0, #0x100] + + /*SDR-SDRAM MEMORY IS ON BANK1*/ + + ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */ + str r1, [r0, #0x120] + + ldr r1, =0x83 /*MODE Mand*/ + str r1, [r0, #0x20] + + /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */ + + ldr r1, =0x62000 /*Data in*/ + ldr r1, [r1] + + /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */ + + ldr r1, =0x8062000 + ldr r1, [r1] + + ldr r1, =0x003 + str r1, [r0, #0x20] + + /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/ + + ldr r1, =0x01 /* Enable buffer 0 */ + str r1, [r0, #0x400] + + ldr r1, =0x01 /* Enable buffer 1 */ + str r1, [r0, #0x420] + + ldr r1, =0x01 /* Enable buffer 2 */ + str r1, [r0, #0x440] + + ldr r1, =0x01 /* Enable buffer 3 */ + str r1, [r0, #0x460] + + ldr r1, =0x01 /* Enable buffer 4 */ + str r1, [r0, #0x480] + + ldr r1, =0x01 /* Enable buffer 5 */ + str r1, [r0, #0x4A0] + + /* GPIO settings */ + + ldr r0, =NOMADIK_GPIO1_BASE + + ldr r1, =0xC0600000 + str r1, [r0, #0x20] + + ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ + str r1, [r0, #0x24] + + ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ + str r1, [r0, #0x28] + + ldr r0, =NOMADIK_GPIO0_BASE + + ldr r1, =0xFFFFFFFF + str r1, [r0, #0x20] + + ldr r1, =0x00 + str r1, [r0, #0x24] + + ldr r1, =0x00 + str r1, [r0, #0x28] + + /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */ + + ldr r0, =NOMADIK_FSMC_BASE + + ldr r1, =0x10DB /* INIT FSMC bank 0 */ + str r1, [r0, #0x00] + + ldr r1, =0x0FFFFFFF + str r1, [r0, #0x04] + + ldr r1, =0x010DB /* INIT FSMC bank 1 */ + str r1, [r0, #0x08] + + ldr r1, =0x00FFFFFFF + str r1, [r0, #0x0C] + + ldr r0, =NOMADIK_UART0_BASE + + ldr r1, =0x00000000 + str r1, [r0, #0x30] + + ldr r1, =0x0000004e + str r1, [r0, #0x24] + + ldr r1, =0x00000008 + str r1, [r0, #0x28] + + ldr r1, =0x00000060 + str r1, [r0, #0x2C] + + ldr r1, =0x00000301 + str r1, [r0, #0x30] + + ldr r1, =0x00000066 + str r1, [r0] + + ldr r0, =NOMADIK_UART1_BASE + + ldr r1, =0x00000000 + str r1, [r0, #0x30] + + ldr r1, =0x0000004e + str r1, [r0, #0x24] + + ldr r1, =0x00000008 + str r1, [r0, #0x28] + + ldr r1, =0x00000060 + str r1, [r0, #0x2C] + + ldr r1, =0x00000301 + str r1, [r0, #0x30] + + ldr r1, =0x00000066 + str r1, [r0] + + ldr r0, =NOMADIK_UART2_BASE + + ldr r1, =0x00000000 + str r1, [r0, #0x30] + + ldr r1, =0x0000004e + str r1, [r0, #0x24] + + ldr r1, =0x00000008 + str r1, [r0, #0x28] + + ldr r1, =0x00000060 + str r1, [r0, #0x2C] + + ldr r1, =0x00000301 + str r1, [r0, #0x30] + + ldr r1, =0x00000066 + str r1, [r0] + + /* Configure CPLD to enable UART0 */ + + mov pc, lr diff --git a/board/st/nmdk8815/Makefile b/board/st/nmdk8815/Makefile deleted file mode 100644 index be9a4242055..00000000000 --- a/board/st/nmdk8815/Makefile +++ /dev/null @@ -1,55 +0,0 @@ -# -# (C) Copyright 2000-2004 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2004 -# ARM Ltd. -# Philippe Robin, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := nmdk8815.o -SOBJS := platform.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/st/nmdk8815/config.mk b/board/st/nmdk8815/config.mk deleted file mode 100644 index 590393bd64c..00000000000 --- a/board/st/nmdk8815/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# (C) Copyright 2007 -# STMicroelectronics, -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# -# image should be loaded at 0x01000000 -# - -TEXT_BASE = 0x03F80000 diff --git a/board/st/nmdk8815/nmdk8815.c b/board/st/nmdk8815/nmdk8815.c deleted file mode 100644 index edf46262f5d..00000000000 --- a/board/st/nmdk8815/nmdk8815.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * (C) Copyright 2005 - * STMicrolelctronics, - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_SHOW_BOOT_PROGRESS -void show_boot_progress(int progress) -{ - printf("%i\n", progress); -} -#endif - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - gd->bd->bi_arch_number = MACH_TYPE_NOMADIK; - gd->bd->bi_boot_params = 0x00000100; - writel(0xC37800F0, NOMADIK_GPIO1_BASE + 0x20); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x24); - writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); - writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); - - /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ - writel(0x0000305b, REG_FSMC_BCR1); - writel(0x00033f33, REG_FSMC_BTR1); - - icache_enable(); - return 0; -} - -int misc_init_r(void) -{ - setenv("verify", "n"); - return 0; -} - -int dram_init(void) -{ - /* set dram bank start addr and size */ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; - return 0; -} diff --git a/board/st/nmdk8815/platform.S b/board/st/nmdk8815/platform.S deleted file mode 100644 index 2a671102312..00000000000 --- a/board/st/nmdk8815/platform.S +++ /dev/null @@ -1,340 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2005 - * STMicrolelctronics, - * - * (C) Copyright 2004, ARM Ltd. - * Philippe Robin, - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -.globl lowlevel_init -lowlevel_init: - /* Jump to the flash address */ - ldr r0, =CFG_ONENAND_BASE - - /* - * Make it independent whether we boot from 0x0 or 0x30000000. - * Non-portable: it relies on the knowledge that ip has to be updated - */ - orr ip, ip, r0 /* adjust return address of cpu_init_crit */ - orr lr, lr, r0 /* adjust return address */ - orr pc, pc, r0 /* jump to the normal address */ - nop - - /* Initialize PLL, Remap clear, FSMC, MPMC here! */ - /* What about GPIO, CLCD and UART */ - - /* PLL Initialization */ - /* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */ - ldr r0, =NOMADIK_SRC_BASE - - ldr r1, =0x2B013502 - - str r1, [r0, #0x14] - - /* Used to set all the timers clock to 2.4MHZ */ - ldr r1, =0x2AAAA004 - str r1, [r0] - - ldr r1, =0x10000000 - str r1, [r0, #0x10] - - /* FSMC setup ---- */ - ldr r0, =NOMADIK_FSMC_BASE - - ldr r1, =0x10DB /* For 16-bit NOR flash */ - str r1, [r0, #0x08] - - ldr r1, =0x03333333 /* For 16-bit NOR flash */ - str r1, [r0, #0xc] - - /* oneNAND setting */ - ldr r1, =0x0000105B /* BCR0 Prog control register */ - str r1, [r0] - - ldr r1, =0x0A200551 /* BTR0 Prog timing register */ - str r1, [r0, #0x04] - - /* preload the instructions into icache */ - add r0, pc, #0x1F - bic r0, r0, #0x1F - mcr p15, 0, r0, c7, c13, 1 - add r0, r0, #0x20 - mcr p15, 0, r0, c7, c13, 1 - - /* Now Clear Remap */ - ldr r0, =NOMADIK_SRC_BASE - - ldr r1, =0x2004 - str r1, [r0] - - ldr r1, =0x10000000 - str r1, [r0, #0x10] - - ldr r0, =0x101E9000 - ldr r1, =0x2004 - str r1, [r0] - - ldr r0, =NOMADIK_SRC_BASE - ldr r1, =0x2104 - str r1, [r0] - - /* FSMC setup -- */ - mov r0, #(NOMADIK_FSMC_BASE & 0x10000000) - orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF) - - ldr r1, =0x10DB /* For 16-bit NOR flash */ - str r1, [r0, #0x8] - - ldr r1, =0x03333333 /* For 16-bit NOR flash */ - str r1, [r0, #0xc] - - /* MPMC Setup */ - ldr r0, =NOMADIK_MPMC_BASE - - ldr r1, =0xF00003 - str r1, [r0] /* Enable the MPMC and the DLL */ - - ldr r1, =0x183 - str r1, [r0, #0x20] - - ldr r2, =NOMADIK_PMU_BASE - - ldr r1, =0x1111 - str r1, [r2] - - ldr r1, =0x1111 /* Prog the, mand delay strategy */ - str r1, [r0, #0x28] - - ldr r1, =0x103 /* NOP ,mand */ - str r1, [r0, #0x20] - - /* FIXME -- Wait required here */ - - ldr r1, =0x103 /* PALL ,mand*/ - str r1, [r0, #0x20] - - ldr r1, =0x1 - str r1, [r0, #0x24] /* To do at least two auto-refresh */ - - /* FIXME -- Wait required here */ - - /* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */ - ldr r1, =0x31 - str r1, [r0, #0x24] - - /* Prog Little Endian, Not defined in 8800 board */ - ldr r1, =0x0 - str r1, [r0, #0x8] - - - ldr r1, =0x2 - str r1, [r0, #0x30] /* Prog tRP timing */ - - ldr r1, =0x4 /* Change for 8815 */ - str r1, [r0, #0x34] /* Prog tRAS timing */ - - ldr r1, =0xB - str r1, [r0, #0x38] /* Prog tSREX timing */ - - - ldr r1, =0x1 - str r1, [r0, #0x44] /* Prog tWR timing */ - - ldr r1, =0x8 - str r1, [r0, #0x48] /* Prog tRC timing */ - - ldr r1, =0xA - str r1, [r0, #0x4C] /* Prog tRFC timing */ - - ldr r1, =0xB - str r1, [r0, #0x50] /* Prog tXSR timing */ - - ldr r1, =0x1 - str r1, [r0, #0x54] /* Prog tRRD timing */ - - ldr r1, =0x1 - str r1, [r0, #0x58] /* Prog tMRD timing */ - - ldr r1, =0x1 - str r1, [r0, #0x5C] /* Prog tCDLR timing */ - - /* DDR-SDRAM MEMORY IS ON BANK0 8815 */ - ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */ - str r1, [r0, #0x104] - - /* SDR-SDRAM MEMORY IS ON BANK1 8815 */ - ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */ - str r1, [r0, #0x124] - /* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */ - /* DDR-SDRAM MEMORY IS ON BANK0*/ - - ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */ - str r1, [r0, #0x100] - - /*SDR-SDRAM MEMORY IS ON BANK1*/ - - ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */ - str r1, [r0, #0x120] - - ldr r1, =0x83 /*MODE Mand*/ - str r1, [r0, #0x20] - - /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */ - - ldr r1, =0x62000 /*Data in*/ - ldr r1, [r1] - - /* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */ - - ldr r1, =0x8062000 - ldr r1, [r1] - - ldr r1, =0x003 - str r1, [r0, #0x20] - - /* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/ - - ldr r1, =0x01 /* Enable buffer 0 */ - str r1, [r0, #0x400] - - ldr r1, =0x01 /* Enable buffer 1 */ - str r1, [r0, #0x420] - - ldr r1, =0x01 /* Enable buffer 2 */ - str r1, [r0, #0x440] - - ldr r1, =0x01 /* Enable buffer 3 */ - str r1, [r0, #0x460] - - ldr r1, =0x01 /* Enable buffer 4 */ - str r1, [r0, #0x480] - - ldr r1, =0x01 /* Enable buffer 5 */ - str r1, [r0, #0x4A0] - - /* GPIO settings */ - - ldr r0, =NOMADIK_GPIO1_BASE - - ldr r1, =0xC0600000 - str r1, [r0, #0x20] - - ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ - str r1, [r0, #0x24] - - ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */ - str r1, [r0, #0x28] - - ldr r0, =NOMADIK_GPIO0_BASE - - ldr r1, =0xFFFFFFFF - str r1, [r0, #0x20] - - ldr r1, =0x00 - str r1, [r0, #0x24] - - ldr r1, =0x00 - str r1, [r0, #0x28] - - /* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */ - - ldr r0, =NOMADIK_FSMC_BASE - - ldr r1, =0x10DB /* INIT FSMC bank 0 */ - str r1, [r0, #0x00] - - ldr r1, =0x0FFFFFFF - str r1, [r0, #0x04] - - ldr r1, =0x010DB /* INIT FSMC bank 1 */ - str r1, [r0, #0x08] - - ldr r1, =0x00FFFFFFF - str r1, [r0, #0x0C] - - ldr r0, =NOMADIK_UART0_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - ldr r0, =NOMADIK_UART1_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - ldr r0, =NOMADIK_UART2_BASE - - ldr r1, =0x00000000 - str r1, [r0, #0x30] - - ldr r1, =0x0000004e - str r1, [r0, #0x24] - - ldr r1, =0x00000008 - str r1, [r0, #0x28] - - ldr r1, =0x00000060 - str r1, [r0, #0x2C] - - ldr r1, =0x00000301 - str r1, [r0, #0x30] - - ldr r1, =0x00000066 - str r1, [r0] - - /* Configure CPLD to enable UART0 */ - - mov pc, lr diff --git a/doc/README.nhk8815 b/doc/README.nhk8815 new file mode 100644 index 00000000000..453cfaeab8b --- /dev/null +++ b/doc/README.nhk8815 @@ -0,0 +1,22 @@ + +The Nomadik 8815 CPU has a "secure" boot mode where no external access +(not even JTAG) is allowed. The "remap" bits in the evaluation board +are configured in order to boot from the internal ROM memory (in +secure mode). + +The boot process as defined by the manufacturer executes external code +(loaded from NAND or OneNAND) that that disables such "security" in +order to run u-boot and later the kernel without constraints. Such +code is a proprietary initial boot loader, called "X-Loader" (in case +anyone wonders, it has no relations with other loaders with the same +name and there is no GPL code inside the ST X-Loader). + +SDRAM configuration, PLL setup and initial loading from NAND is +implemented in the X-Loader, so U-Boot is already running in SDRAM +when control is handed over to it. + + +On www.st.com/nomadik and on www.stnwireless.com there are documents, +summary data and white papers on Nomadik. The full datasheet for +STn8815 is not currently available on line but under specific request +to the local ST sales offices. diff --git a/doc/README.nmdk8815 b/doc/README.nmdk8815 deleted file mode 100644 index 453cfaeab8b..00000000000 --- a/doc/README.nmdk8815 +++ /dev/null @@ -1,22 +0,0 @@ - -The Nomadik 8815 CPU has a "secure" boot mode where no external access -(not even JTAG) is allowed. The "remap" bits in the evaluation board -are configured in order to boot from the internal ROM memory (in -secure mode). - -The boot process as defined by the manufacturer executes external code -(loaded from NAND or OneNAND) that that disables such "security" in -order to run u-boot and later the kernel without constraints. Such -code is a proprietary initial boot loader, called "X-Loader" (in case -anyone wonders, it has no relations with other loaders with the same -name and there is no GPL code inside the ST X-Loader). - -SDRAM configuration, PLL setup and initial loading from NAND is -implemented in the X-Loader, so U-Boot is already running in SDRAM -when control is handed over to it. - - -On www.st.com/nomadik and on www.stnwireless.com there are documents, -summary data and white papers on Nomadik. The full datasheet for -STn8815 is not currently available on line but under specific request -to the local ST sales offices. diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h new file mode 100644 index 00000000000..df9d5235e98 --- /dev/null +++ b/include/configs/nhk8815.h @@ -0,0 +1,168 @@ +/* + * (C) Copyright 2005 + * STMicroelectronics. + * Configuration settings for the "Nomadik Hardware Kit" NHK-8815, + * the evaluation board for the Nomadik 8815 System on Chip. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +#define CONFIG_ARM926EJS +#define CONFIG_NOMADIK +#define CONFIG_NOMADIK_8815 +#define CONFIG_NOMADIK_NDK15 +#define CONFIG_NOMADIK_NHK15 + +#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ + +/* commands */ +#include + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +/* There is no NOR flash, so undefine these commands */ +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_SYS_NO_FLASH +/* There is NAND storage */ +#define CONFIG_NAND_NOMADIK +#define CONFIG_CMD_JFFS2 + +/* user interface */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Nomadik> " +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* boot config */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_TAG +#define CONFIG_BOOTDELAY 1 +#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" +#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ + " fsload 0x800000 initrd.gz.uimg;" \ + " bootm 0x100000 0x800000" + +/* memory-related information */ +#define CONFIG_NR_DRAM_BANKS 2 +#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ +#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ + +#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ + +/* timing informazion */ +#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ +#define CONFIG_SYS_TIMERBASE 0x101E2000 + +/* serial port (PL011) configuration */ +#define CONFIG_PL011_SERIAL +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_SERIAL0 0x101FD000 +#define CFG_SERIAL1 0x101FB000 + +#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } +#define CONFIG_PL011_CLOCK 48000000 + +/* Ethernet */ +#define PCI_MEMORY_VADDR 0xe8000000 +#define PCI_IO_VADDR 0xee000000 +#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) +#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) + +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/ +#define CONFIG_SMC91111_BASE 0x34000300 +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT +#define CONFIG_BOOTFILE "uImage" + +/* flash memory and filesystem information */ +#define CONFIG_DOS_PARTITION +#define CONFIG_MTD_ONENAND_VERIFY_WRITE +#define CONFIG_SYS_ONENAND_BASE 0x30000000 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ + +#ifdef CONFIG_BOOT_ONENAND + +# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ + /* Partition Size Start + * XloaderTOC + X-Loader 256KB 0x00000000 + * Memory init function 256KB 0x00040000 + * U-Boot 2MB 0x00080000 + * Sysimage (kernel + ramdisk) 4MB 0x00280000 + * JFFS2 Root filesystem 22MB 0x00680000 + * JFFS2 User Data 227.5MB 0x01C80000 + */ +# define CONFIG_JFFS2_PART_SIZE 0x400000 +# define CONFIG_JFFS2_PART_OFFSET 0x280000 + +# define CONFIG_ENV_IS_IN_ONENAND +# define CONFIG_ENV_SIZE (256 * 1024) +# define CONFIG_ENV_ADDR 0x30300000 + +#else /* ! CONFIG_BOOT_ONENAND */ + +# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ + +# define CONFIG_JFFS2_DEV "nand0" +# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ +# define CONFIG_JFFS2_PART_SIZE 0x00300000 +# define CONFIG_JFFS2_PART_OFFSET 0x00280000 + +# define CONFIG_ENV_IS_IN_NAND +# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ +# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE) + +#endif /* CONFIG_BOOT_ONENAND */ + +/* this is needed to make hello_world.c and other stuff happy */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#endif /* __CONFIG_H */ diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h deleted file mode 100644 index 6d7b94f9c9e..00000000000 --- a/include/configs/nmdk8815.h +++ /dev/null @@ -1,167 +0,0 @@ -/* - * (C) Copyright 2005 - * STMicroelectronics. - * Configuration settings for the STn8815 nomadik board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_ARM926EJS -#define CONFIG_NOMADIK -#define CONFIG_NOMADIK_8815 -#define CONFIG_NOMADIK_NDK15 -#define CONFIG_NOMADIK_NHK15 - -#define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ - -/* commands */ -#include - -#define CONFIG_CMD_NET -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_NFS -/* There is no NOR flash, so undefine these commands */ -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_SYS_NO_FLASH -/* There is NAND storage */ -#define CONFIG_NAND_NOMADIK -#define CONFIG_CMD_JFFS2 - -/* user interface */ -#define CONFIG_SYS_LONGHELP -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "Nomadik> " -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Arg Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_LOAD_ADDR 0x800000 /* default load address */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* boot config */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_BOOTDELAY 1 -#define CONFIG_BOOTARGS "root=/dev/ram0 console=ttyAMA1,115200n8 init=linuxrc" -#define CONFIG_BOOTCOMMAND "fsload 0x100000 kernel.uimg;" \ - " fsload 0x800000 initrd.gz.uimg;" \ - " bootm 0x100000 0x800000" - -/* memory-related information */ -#define CONFIG_NR_DRAM_BANKS 2 -#define PHYS_SDRAM_1 0x00000000 /* DDR-SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2 0x08000000 /* SDR-SDRAM BANK #2*/ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -# define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ -# define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ - -#define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ - -/* timing informazion */ -#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ -#define CONFIG_SYS_TIMERBASE 0x101E2000 - -/* serial port (PL011) configuration */ -#define CONFIG_PL011_SERIAL -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SERIAL0 0x101FD000 -#define CFG_SERIAL1 0x101FB000 - -#define CONFIG_PL01x_PORTS { (void *)CFG_SERIAL0, (void *)CFG_SERIAL1 } -#define CONFIG_PL011_CLOCK 48000000 - -/* Ethernet */ -#define PCI_MEMORY_VADDR 0xe8000000 -#define PCI_IO_VADDR 0xee000000 -#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) -#define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) - -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/ -#define CONFIG_SMC91111_BASE 0x34000300 -#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_BOOTFILE "uImage" - -/* flash memory and filesystem information */ -#define CONFIG_DOS_PARTITION -#define CONFIG_MTD_ONENAND_VERIFY_WRITE -#define CONFIG_SYS_ONENAND_BASE 0x30000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ - -#ifdef CONFIG_BOOT_ONENAND - -# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ - /* Partition Size Start - * XloaderTOC + X-Loader 256KB 0x00000000 - * Memory init function 256KB 0x00040000 - * U-Boot 2MB 0x00080000 - * Sysimage (kernel + ramdisk) 4MB 0x00280000 - * JFFS2 Root filesystem 22MB 0x00680000 - * JFFS2 User Data 227.5MB 0x01C80000 - */ -# define CONFIG_JFFS2_PART_SIZE 0x400000 -# define CONFIG_JFFS2_PART_OFFSET 0x280000 - -# define CONFIG_ENV_IS_IN_ONENAND -# define CONFIG_ENV_SIZE (256 * 1024) -# define CONFIG_ENV_ADDR 0x30300000 - -#else /* ! CONFIG_BOOT_ONENAND */ - -# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ - -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ -# define CONFIG_JFFS2_PART_SIZE 0x00300000 -# define CONFIG_JFFS2_PART_OFFSET 0x00280000 - -# define CONFIG_ENV_IS_IN_NAND -# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE) - -#endif /* CONFIG_BOOT_ONENAND */ - -/* this is needed to make hello_world.c and other stuff happy */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From fd14c41a861cd38ee2fe3abd61d59b57b4eb23c9 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 22 Jun 2009 09:18:47 +0200 Subject: arm nomadik: cleanup reset There is only one public release of the Nomadik chip, so the ifdef in reset code as well as a define in the config file are not needed Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- cpu/arm926ejs/nomadik/reset.S | 13 +------------ include/configs/nhk8815.h | 5 ++--- 2 files changed, 3 insertions(+), 15 deletions(-) (limited to 'include') diff --git a/cpu/arm926ejs/nomadik/reset.S b/cpu/arm926ejs/nomadik/reset.S index 948996b2e7b..ec954726aeb 100644 --- a/cpu/arm926ejs/nomadik/reset.S +++ b/cpu/arm926ejs/nomadik/reset.S @@ -6,20 +6,9 @@ .align 5 .globl reset_cpu reset_cpu: -#if defined CONFIG_NOMADIK_8815 - ldr r0, =NOMADIK_SRC_BASE + ldr r0, =NOMADIK_SRC_BASE /* System and Reset Controller */ ldr r1, =0x1 str r1, [r0, #0x18] -#else - ldr r1, rstctl1 /* get clkm1 reset ctl */ - mov r3, #0x0 - strh r3, [r1] /* clear it */ - mov r3, #0x8 - strh r3, [r1] /* force dsp+arm reset */ -#endif _loop_forever: b _loop_forever - -rstctl1: - .word 0xfffece10 diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index df9d5235e98..321adfacfda 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -30,9 +30,8 @@ #define CONFIG_ARM926EJS #define CONFIG_NOMADIK -#define CONFIG_NOMADIK_8815 -#define CONFIG_NOMADIK_NDK15 -#define CONFIG_NOMADIK_NHK15 +#define CONFIG_NOMADIK_8815 /* cpu variant */ +#define CONFIG_NOMADIK_NHK8815 /* board variant */ #define CONFIG_SKIP_LOWLEVEL_INIT /* we have already been loaded to RAM */ -- cgit v1.3.1 From f7aa59b29a451cc502078a9e4ba32345a4250c05 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 22 Jun 2009 09:18:57 +0200 Subject: arm nomadik: allow Nand and OneNand to coexists The evaluation kit has both Nand and OneNand, both drivers are there and the two configurations only select a different default for the jffs partition. This adds the OneNand driver and cleans up storage. Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- Makefile | 4 ++-- board/st/nhk8815/nhk8815.c | 4 ++++ doc/README.nhk8815 | 10 ++++++++++ include/configs/nhk8815.h | 49 +++++++++++++++++++++++++++++----------------- 4 files changed, 47 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index 3877c972098..d486b55422c 100644 --- a/Makefile +++ b/Makefile @@ -2860,9 +2860,9 @@ nhk8815_onenand_config: unconfig @ > $(obj)include/config.h @if [ "$(findstring _onenand, $@)" ] ; then \ echo "#define CONFIG_BOOT_ONENAND" >> $(obj)include/config.h; \ - $(XECHO) "... configured for OneNand Flash"; \ + $(XECHO) "... configured to boot from OneNand Flash"; \ else \ - $(XECHO) "... configured for Nand Flash"; \ + $(XECHO) "... configured to boot from Nand Flash"; \ fi @$(MKCONFIG) -a nhk8815 arm arm926ejs nhk8815 st nomadik diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c index edf46262f5d..085a5e0a427 100644 --- a/board/st/nhk8815/nhk8815.c +++ b/board/st/nhk8815/nhk8815.c @@ -53,6 +53,10 @@ int board_init(void) writel(0x0000305b, REG_FSMC_BCR1); writel(0x00033f33, REG_FSMC_BTR1); + /* Set up SMCS0 for OneNand: sram-like once again */ + writel(0x000030db, NOMADIK_FSMC_BASE + 0x00); /* FSMC_BCR0 */ + writel(0x02100551, NOMADIK_FSMC_BASE + 0x04); /* FSMC_BTR0 */ + icache_enable(); return 0; } diff --git a/doc/README.nhk8815 b/doc/README.nhk8815 index 453cfaeab8b..9008e393637 100644 --- a/doc/README.nhk8815 +++ b/doc/README.nhk8815 @@ -15,6 +15,16 @@ SDRAM configuration, PLL setup and initial loading from NAND is implemented in the X-Loader, so U-Boot is already running in SDRAM when control is handed over to it. +The Makefile offers two different configurations to be used if you +boot from Nand or OneNand. + + make nhk8815_config + make nhk8815_onenand_config + +Both support OneNand and Nand. Since U-Boot, running in RAM, can't know +where it was loaded from, the configurations differ in where the filesystem +is looked for by default. + On www.st.com/nomadik and on www.stnwireless.com there are documents, summary data and white papers on Nomadik. The full datasheet for diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 321adfacfda..bf1a9153819 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -55,6 +55,7 @@ #define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "Nomadik> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ + sizeof(CONFIG_SYS_PROMPT) + 16) @@ -90,6 +91,7 @@ #define CONFIG_SYS_MEMTEST_END 0x0FFFFFFF #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 256 * 1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ +#define CONFIG_SYS_64BIT_VSPRINTF /* mtd desires this */ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ @@ -120,43 +122,54 @@ #define CONFIG_SMC_USE_32_BIT #define CONFIG_BOOTFILE "uImage" -/* flash memory and filesystem information */ -#define CONFIG_DOS_PARTITION +/* Storage information: onenand and nand */ +#define CONFIG_CMD_ONENAND #define CONFIG_MTD_ONENAND_VERIFY_WRITE #define CONFIG_SYS_ONENAND_BASE 0x30000000 + +#define CONFIG_CMD_NAND #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ +/* + * Filesystem information + * + * Since U-Boot has been loaded to RAM by vendor code, we could use + * either or both OneNand and Nand. However, we need to know where the + * filesystem lives. Comments below report vendor-selected partitions + */ #ifdef CONFIG_BOOT_ONENAND - -# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ /* Partition Size Start * XloaderTOC + X-Loader 256KB 0x00000000 * Memory init function 256KB 0x00040000 - * U-Boot 2MB 0x00080000 + * U-Boot + env 2MB 0x00080000 * Sysimage (kernel + ramdisk) 4MB 0x00280000 * JFFS2 Root filesystem 22MB 0x00680000 * JFFS2 User Data 227.5MB 0x01C80000 */ -# define CONFIG_JFFS2_PART_SIZE 0x400000 -# define CONFIG_JFFS2_PART_OFFSET 0x280000 - +# define CONFIG_JFFS2_DEV "onenand0" +# define CONFIG_JFFS2_PART_SIZE 0x01600000 +# define CONFIG_JFFS2_PART_OFFSET 0x00680000 # define CONFIG_ENV_IS_IN_ONENAND -# define CONFIG_ENV_SIZE (256 * 1024) -# define CONFIG_ENV_ADDR 0x30300000 - -#else /* ! CONFIG_BOOT_ONENAND */ - -# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ +# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ +# define CONFIG_ENV_ADDR (0x00280000 - CONFIG_ENV_SIZE) +#else /* BOOT_NAND */ + /* Partition Size Start + * XloaderTOC + X-Loader 256KB 0x00000000 + * Memory init function 256KB 0x00040000 + * U-Boot + env 2MB 0x00080000 + * Kernel Image 3MB 0x00280000 + * JFFS2 Root filesystem 22MB 0x00580000 + * JFFS2 User Data 100.5MB 0x01b80000 + */ # define CONFIG_JFFS2_DEV "nand0" # define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ -# define CONFIG_JFFS2_PART_SIZE 0x00300000 -# define CONFIG_JFFS2_PART_OFFSET 0x00280000 - +# define CONFIG_JFFS2_PART_SIZE 0x01600000 +# define CONFIG_JFFS2_PART_OFFSET 0x00580000 # define CONFIG_ENV_IS_IN_NAND # define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ -# define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE) +# define CONFIG_ENV_OFFSET (0x00280000 - CONFIG_ENV_SIZE) #endif /* CONFIG_BOOT_ONENAND */ -- cgit v1.3.1 From 095a460b49022e64df76134300643606e3acb4e9 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 29 Jun 2009 10:52:37 +0200 Subject: arm nomadik: use 1000 as HZ value and rewrite timer code This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. mtu.h is copied literally from the kernel sources. Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- cpu/arm926ejs/nomadik/timer.c | 166 ++++++------------------------------- include/asm-arm/arch-nomadik/mtu.h | 66 +++++++++++++++ include/configs/nhk8815.h | 2 +- 3 files changed, 94 insertions(+), 140 deletions(-) create mode 100644 include/asm-arm/arch-nomadik/mtu.h (limited to 'include') diff --git a/cpu/arm926ejs/nomadik/timer.c b/cpu/arm926ejs/nomadik/timer.c index 2870d24ad54..16067c900ae 100644 --- a/cpu/arm926ejs/nomadik/timer.c +++ b/cpu/arm926ejs/nomadik/timer.c @@ -1,20 +1,5 @@ /* - * (C) Copyright 2003 - * Texas Instruments - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * (C) Copyright 2002-2004 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2004 - * Philippe Robin, ARM Ltd. + * (C) Copyright 2009 Alessandro Rubini * * See file CREDITS for list of people who contributed to this * project. @@ -37,146 +22,49 @@ #include #include +#include -#define TIMER_LOAD_VAL 0xffffffff - -/* macro to read the 32 bit timer */ -#define READ_TIMER readl(CONFIG_SYS_TIMERBASE + 20) +/* + * The timer is a decrementer, we'll left it free running at 2.4MHz. + * We have 2.4 ticks per microsecond and an overflow in almost 30min + */ +#define TIMER_CLOCK (24 * 100 * 1000) +#define COUNT_TO_USEC(x) ((x) * 5 / 12) /* overflows at 6min */ +#define USEC_TO_COUNT(x) ((x) * 12 / 5) /* overflows at 6min */ +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) -static ulong timestamp; -static ulong lastdec; +/* macro to read the 32 bit timer: since it decrements, we invert read value */ +#define READ_TIMER() (~readl(CONFIG_SYS_TIMERBASE + MTU_VAL(0))) -/* nothing really to do with interrupts, just starts up a counter. */ +/* Configure a free-running, auto-wrap counter with no prescaler */ int timer_init(void) { - /* Load timer with initial value */ - writel(TIMER_LOAD_VAL, CONFIG_SYS_TIMERBASE + 16); - - /* - * Set timer to be enabled, free-running, no interrupts, 256 divider, - * 32-bit, wrap-mode - */ - writel(0x8a, CONFIG_SYS_TIMERBASE + 24); - - /* init the timestamp and lastdec value */ - reset_timer_masked(); - + writel(MTU_CRn_ENA | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS, + CONFIG_SYS_TIMERBASE + MTU_CR(0)); + reset_timer(); return 0; } -/* - * timer without interrupts - */ +/* Restart counting from 0 */ void reset_timer(void) { - reset_timer_masked(); + writel(0, CONFIG_SYS_TIMERBASE + MTU_LR(0)); /* Immediate effect */ } +/* Return how many HZ passed since "base" */ ulong get_timer(ulong base) { - return get_timer_masked() - base; + return TICKS_TO_HZ(READ_TIMER()) - base; } -void set_timer(ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND perserve advance timstamp value */ +/* Delay x useconds */ void udelay(unsigned long usec) { - ulong tmo, tmp; - - if (usec >= 1000) { - /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */ - tmo /= 1000; /* finish normalize. */ - } else { - /* small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000 * 1000); - } - - tmp = get_timer(0); /* get current timestamp */ - if ((tmo + tmp + 1) < tmp) /* will roll time stamp? */ - reset_timer_masked(); /* reset to 0, set lastdec value */ - else - tmo += tmp; - - while (get_timer_masked() < tmo) - /* nothing */ ; -} - -void reset_timer_masked(void) -{ - /* reset time */ - lastdec = READ_TIMER; /* capure current decrementer value time */ - timestamp = 0; /* start "advancing" time stamp from 0 */ -} - -ulong get_timer_masked(void) -{ - ulong now = READ_TIMER; /* current tick value */ - - if (lastdec >= now) { /* normal mode (non roll) */ - /* move stamp fordward */ - timestamp += lastdec - now; - } else { - /* - * An overflow is expected. - * nts = ts + ld + (TLV - now) - * ts=old stamp, ld=time that passed before passing through -1 - * (TLV-now) amount of time after passing though -1 - * nts = new "advancing time stamp"...it could also roll - */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - - return timestamp; -} - -/* waits specified delay value and resets timestamp */ -void udelay_masked(unsigned long usec) -{ - ulong tmo; - - if (usec >= 1000) { - /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize */ - tmo *= CONFIG_SYS_HZ; /* find number of "ticks" */ - tmo /= 1000; /* finish normalize. */ - } else { - /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CONFIG_SYS_HZ; - tmo /= (1000*1000); - } - - reset_timer_masked(); - /* set "advancing" timestamp to 0, set lastdec vaule */ - - while (get_timer_masked() < tmo) - /* nothing */ ; -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; + ulong ini, end; - tbclk = CONFIG_SYS_HZ; - return tbclk; + ini = READ_TIMER(); + end = ini + USEC_TO_COUNT(usec); + while ((signed)(end - READ_TIMER()) > 0) + ; } diff --git a/include/asm-arm/arch-nomadik/mtu.h b/include/asm-arm/arch-nomadik/mtu.h new file mode 100644 index 00000000000..a87be9ef4fc --- /dev/null +++ b/include/asm-arm/arch-nomadik/mtu.h @@ -0,0 +1,66 @@ +/* + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MTU_H +#define __ASM_ARCH_MTU_H + +/* + * The MTU device hosts four different counters, with 4 set of + * registers. These are register names. + */ + +#define MTU_IMSC 0x00 /* Interrupt mask set/clear */ +#define MTU_RIS 0x04 /* Raw interrupt status */ +#define MTU_MIS 0x08 /* Masked interrupt status */ +#define MTU_ICR 0x0C /* Interrupt clear register */ + +/* per-timer registers take 0..3 as argument */ +#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ +#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ +#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ +#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ + +/* bits for the control register */ +#define MTU_CRn_ENA 0x80 +#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ +#define MTU_CRn_PRESCALE_MASK 0x0c +#define MTU_CRn_PRESCALE_1 0x00 +#define MTU_CRn_PRESCALE_16 0x04 +#define MTU_CRn_PRESCALE_256 0x08 +#define MTU_CRn_32BITS 0x02 +#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ + +/* Other registers are usual amba/primecell registers, currently not used */ +#define MTU_ITCR 0xff0 +#define MTU_ITOP 0xff4 + +#define MTU_PERIPH_ID0 0xfe0 +#define MTU_PERIPH_ID1 0xfe4 +#define MTU_PERIPH_ID2 0xfe8 +#define MTU_PERIPH_ID3 0xfeC + +#define MTU_PCELL0 0xff0 +#define MTU_PCELL1 0xff4 +#define MTU_PCELL2 0xff8 +#define MTU_PCELL3 0xffC + +#endif /* __ASM_ARCH_MTU_H */ diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index bf1a9153819..3e2e09fb836 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -96,7 +96,7 @@ #define CONFIG_MISC_INIT_R /* call misc_init_r during start up */ /* timing informazion */ -#define CONFIG_SYS_HZ (2400000 / 256) /* Timer0: 2.4Mhz + divider */ +#define CONFIG_SYS_HZ 1000 /* Mandatory... */ #define CONFIG_SYS_TIMERBASE 0x101E2000 /* serial port (PL011) configuration */ -- cgit v1.3.1 From 78eabb90b793fafe875a7469526d1715fa56cbb4 Mon Sep 17 00:00:00 2001 From: Prafulla Wadaskar Date: Mon, 29 Jun 2009 20:55:54 +0530 Subject: arm: Kirkwood: arch specific updated for ehci-Kirkwood driver support This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver Signed-off-by: Prafulla Wadaskar --- cpu/arm926ejs/kirkwood/cpu.c | 6 +----- include/asm-arm/arch-kirkwood/cpu.h | 8 ++++++++ include/asm-arm/arch-kirkwood/kirkwood.h | 1 + 3 files changed, 10 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c index 194ba1c85df..795a739023d 100644 --- a/cpu/arm926ejs/kirkwood/cpu.c +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -74,7 +74,7 @@ unsigned char get_random_hex(void) * 64 KByte granularity (e.g., a value of 0x00FF specifies 256 = 16 MByte). * NOTE: A value of 0x0 specifies 64-KByte size. */ -static unsigned int kw_winctrl_calcsize(unsigned int sizeval) +unsigned int kw_winctrl_calcsize(unsigned int sizeval) { int i; unsigned int j = 0; @@ -87,10 +87,6 @@ static unsigned int kw_winctrl_calcsize(unsigned int sizeval) return (0x0000ffff & j); } -/* prepares data to be loaded in win_Ctrl register */ -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) - /* * kw_config_adr_windows - Configure address Windows * diff --git a/include/asm-arm/arch-kirkwood/cpu.h b/include/asm-arm/arch-kirkwood/cpu.h index 36064ae0c63..d1440af4b78 100644 --- a/include/asm-arm/arch-kirkwood/cpu.h +++ b/include/asm-arm/arch-kirkwood/cpu.h @@ -29,6 +29,9 @@ #ifndef __ASSEMBLY__ +#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) + #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c) @@ -57,6 +60,10 @@ enum kwcpu_target { enum kwcpu_attrib { KWCPU_ATTR_SASRAM = 0x01, + KWCPU_ATTR_DRAM_CS0 = 0x0e, + KWCPU_ATTR_DRAM_CS1 = 0x0d, + KWCPU_ATTR_DRAM_CS2 = 0x0b, + KWCPU_ATTR_DRAM_CS3 = 0x07, KWCPU_ATTR_NANDFLASH = 0x2f, KWCPU_ATTR_SPIFLASH = 0x1e, KWCPU_ATTR_BOOTROM = 0x1d, @@ -155,5 +162,6 @@ int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, unsigned int mpp16_23, unsigned int mpp24_31, unsigned int mpp32_39, unsigned int mpp40_47, unsigned int mpp48_55); +unsigned int kw_winctrl_calcsize(unsigned int sizeval); #endif /* __ASSEMBLY__ */ #endif /* _KWCPU_H */ diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h index d5f25f9e5a0..52dafc22cc6 100644 --- a/include/asm-arm/arch-kirkwood/kirkwood.h +++ b/include/asm-arm/arch-kirkwood/kirkwood.h @@ -55,6 +55,7 @@ #define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) #define KW_TIMER_BASE (KW_REGISTER(0x20300)) #define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) +#define KW_USB20_BASE (KW_REGISTER(0x50000)) #define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) #define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) -- cgit v1.3.1 From d08e5ca301b69ab77ecdd34e2b06aee30d6057d1 Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sat, 4 Jul 2009 10:31:24 +0200 Subject: MX31: Add NAND SPL boot support to i.MX31 PDK board. Signed-off-by: Magnus Lilja --- MAKEALL | 1 + Makefile | 12 +++- board/freescale/mx31pdk/config.mk | 4 ++ board/freescale/mx31pdk/lowlevel_init.S | 93 +++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 54 +++++++++++++++++ include/configs/mx31pdk.h | 43 ++++++++++++- nand_spl/board/freescale/mx31pdk/Makefile | 54 +++++++++++++++++ nand_spl/board/freescale/mx31pdk/config.mk | 1 + nand_spl/board/freescale/mx31pdk/u-boot.lds | 36 +++++++++++ 9 files changed, 293 insertions(+), 5 deletions(-) create mode 100644 board/freescale/mx31pdk/lowlevel_init.S create mode 100644 nand_spl/board/freescale/mx31pdk/Makefile create mode 100644 nand_spl/board/freescale/mx31pdk/config.mk create mode 100644 nand_spl/board/freescale/mx31pdk/u-boot.lds (limited to 'include') diff --git a/MAKEALL b/MAKEALL index e6f6c147de0..f2d3b6fad59 100755 --- a/MAKEALL +++ b/MAKEALL @@ -555,6 +555,7 @@ LIST_ARM11=" \ imx31_phycore_eet \ mx31ads \ mx31pdk \ + mx31pdk_nand \ qong \ smdk6400 \ " diff --git a/Makefile b/Makefile index d486b55422c..763a202b361 100644 --- a/Makefile +++ b/Makefile @@ -3143,8 +3143,16 @@ imx31_phycore_config : unconfig mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 -mx31pdk_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm1136 mx31pdk freescale mx31 +mx31pdk_config \ +mx31pdk_nand_config : unconfig + @mkdir -p $(obj)include + @if [ -n "$(findstring _nand_,$@)" ]; then \ + echo "#define CONFIG_NAND_U_BOOT" >> $(obj)include/config.h; \ + else \ + echo "#define CONFIG_SKIP_LOWLEVEL_INIT" >> $(obj)include/config.h; \ + echo "#define CONFIG_SKIP_RELOCATE_UBOOT" >> $(obj)include/config.h; \ + fi + @$(MKCONFIG) -a mx31pdk arm arm1136 mx31pdk freescale mx31 omap2420h4_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 omap2420h4 NULL omap24xx diff --git a/board/freescale/mx31pdk/config.mk b/board/freescale/mx31pdk/config.mk index d34dc02d96a..dcaa09ff837 100644 --- a/board/freescale/mx31pdk/config.mk +++ b/board/freescale/mx31pdk/config.mk @@ -1 +1,5 @@ +ifdef CONFIG_NAND_SPL +TEXT_BASE = 0x87ec0000 +else TEXT_BASE = 0x87f00000 +endif diff --git a/board/freescale/mx31pdk/lowlevel_init.S b/board/freescale/mx31pdk/lowlevel_init.S new file mode 100644 index 00000000000..cd0503ec3a5 --- /dev/null +++ b/board/freescale/mx31pdk/lowlevel_init.S @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2009 Magnus Lilja + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =ARM_PPMRR /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + write32 IPU_CONF, IPU_CONF_DI_EN + write32 CCM_CCMR, CCM_CCMR_SETUP + + wait_timer 0x40000 + + write32 CCM_CCMR, CCM_CCMR_SETUP | CCMR_MPE + write32 CCM_CCMR, (CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS + + /* Set up clock to 532MHz */ + write32 CCM_PDR0, CCM_PDR0_SETUP_532MHZ + write32 CCM_MPCTL, CCM_MPCTL_SETUP_532MHZ + + write32 CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* Set up MX31 DDR pins */ + write32 IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B, 0 + write32 IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0, 0 + write32 IOMUXC_SW_PAD_CTL_BCLK_RW_RAS, 0 + write32 IOMUXC_SW_PAD_CTL_CS2_CS3_CS4, 0x1000 + write32 IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1, 0 + write32 IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2, 0 + write32 IOMUXC_SW_PAD_CTL_SD29_SD30_SD31, 0 + write32 IOMUXC_SW_PAD_CTL_SD26_SD27_SD28, 0 + write32 IOMUXC_SW_PAD_CTL_SD23_SD24_SD25, 0 + write32 IOMUXC_SW_PAD_CTL_SD20_SD21_SD22, 0 + write32 IOMUXC_SW_PAD_CTL_SD17_SD18_SD19, 0 + write32 IOMUXC_SW_PAD_CTL_SD14_SD15_SD16, 0 + write32 IOMUXC_SW_PAD_CTL_SD11_SD12_SD13, 0 + write32 IOMUXC_SW_PAD_CTL_SD8_SD9_SD10, 0 + write32 IOMUXC_SW_PAD_CTL_SD5_SD6_SD7, 0 + write32 IOMUXC_SW_PAD_CTL_SD2_SD3_SD4, 0 + write32 IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1, 0 + write32 IOMUXC_SW_PAD_CTL_A24_A25_SDBA1, 0 + write32 IOMUXC_SW_PAD_CTL_A21_A22_A23, 0 + write32 IOMUXC_SW_PAD_CTL_A18_A19_A20, 0 + write32 IOMUXC_SW_PAD_CTL_A15_A16_A17, 0 + write32 IOMUXC_SW_PAD_CTL_A12_A13_A14, 0 + write32 IOMUXC_SW_PAD_CTL_A10_MA10_A11, 0 + write32 IOMUXC_SW_PAD_CTL_A7_A8_A9, 0 + write32 IOMUXC_SW_PAD_CTL_A4_A5_A6, 0 + write32 IOMUXC_SW_PAD_CTL_A1_A2_A3, 0 + write32 IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0, 0 + + /* Set up MX31 DDR Memory Controller */ + write32 WEIM_ESDMISC, ESDMISC_MDDR_SETUP + write32 WEIM_ESDCFG0, ESDCFG0_MDDR_SETUP + + /* Perform DDR init sequence */ + write32 WEIM_ESDCTL0, ESDCTL_PRECHARGE + write32 CSD0_BASE | 0x0f00, 0x12344321 + write32 WEIM_ESDCTL0, ESDCTL_AUTOREFRESH + write32 CSD0_BASE, 0x12344321 + write32 CSD0_BASE, 0x12344321 + write32 WEIM_ESDCTL0, ESDCTL_LOADMODEREG + write8 CSD0_BASE | 0x00000033, 0xda + write8 CSD0_BASE | 0x01000000, 0xff + write32 WEIM_ESDCTL0, ESDCTL_RW + write32 CSD0_BASE, 0xDEADBEEF + write32 WEIM_ESDMISC, ESDMISC_MDDR_RESET_DL + + mov pc, lr diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 76f4d53a32e..51b02a2a260 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -61,6 +61,29 @@ #define PLL_MFI(x) (((x) & 0xf) << 10) #define PLL_MFN(x) (((x) & 0x3ff) << 0) +#define WEIM_ESDCTL0 0xB8001000 +#define WEIM_ESDCFG0 0xB8001004 +#define WEIM_ESDCTL1 0xB8001008 +#define WEIM_ESDCFG1 0xB800100C +#define WEIM_ESDMISC 0xB8001010 + +#define ESDCTL_SDE (1 << 31) +#define ESDCTL_CMD_RW (0 << 28) +#define ESDCTL_CMD_PRECHARGE (1 << 28) +#define ESDCTL_CMD_AUTOREFRESH (2 << 28) +#define ESDCTL_CMD_LOADMODEREG (3 << 28) +#define ESDCTL_CMD_MANUALREFRESH (4 << 28) +#define ESDCTL_ROW_13 (2 << 24) +#define ESDCTL_ROW(x) ((x) << 24) +#define ESDCTL_COL_9 (1 << 20) +#define ESDCTL_COL(x) ((x) << 20) +#define ESDCTL_DSIZ(x) ((x) << 16) +#define ESDCTL_SREFR(x) ((x) << 13) +#define ESDCTL_PWDT(x) ((x) << 10) +#define ESDCTL_FP(x) ((x) << 8) +#define ESDCTL_BL(x) ((x) << 7) +#define ESDCTL_PRCT(x) ((x) << 0) + #define WEIM_BASE 0xb8002000 #define CSCR_U(x) (WEIM_BASE + (x) * 0x10) #define CSCR_L(x) (WEIM_BASE + 4 + (x) * 0x10) @@ -181,6 +204,37 @@ #define MUX_CSPI2_MOSI__I2C2_SCL IOMUX_MODE(MUX_CTL_CSPI2_MOSI, MUX_CTL_ALT1) #define MUX_CSPI2_MISO__I2C2_SDA IOMUX_MODE(MUX_CTL_CSPI2_MISO, MUX_CTL_ALT1) +/* PAD control registers for SDR/DDR */ +#define IOMUXC_SW_PAD_CTL_SDCKE1_SDCLK_SDCLK_B (IOMUXC_BASE + 0x26C) +#define IOMUXC_SW_PAD_CTL_CAS_SDWE_SDCKE0 (IOMUXC_BASE + 0x270) +#define IOMUXC_SW_PAD_CTL_BCLK_RW_RAS (IOMUXC_BASE + 0x274) +#define IOMUXC_SW_PAD_CTL_CS5_ECB_LBA (IOMUXC_BASE + 0x278) +#define IOMUXC_SW_PAD_CTL_CS2_CS3_CS4 (IOMUXC_BASE + 0x27C) +#define IOMUXC_SW_PAD_CTL_OE_CS0_CS1 (IOMUXC_BASE + 0x280) +#define IOMUXC_SW_PAD_CTL_DQM3_EB0_EB1 (IOMUXC_BASE + 0x284) +#define IOMUXC_SW_PAD_CTL_DQM0_DQM1_DQM2 (IOMUXC_BASE + 0x288) +#define IOMUXC_SW_PAD_CTL_SD29_SD30_SD31 (IOMUXC_BASE + 0x28C) +#define IOMUXC_SW_PAD_CTL_SD26_SD27_SD28 (IOMUXC_BASE + 0x290) +#define IOMUXC_SW_PAD_CTL_SD23_SD24_SD25 (IOMUXC_BASE + 0x294) +#define IOMUXC_SW_PAD_CTL_SD20_SD21_SD22 (IOMUXC_BASE + 0x298) +#define IOMUXC_SW_PAD_CTL_SD17_SD18_SD19 (IOMUXC_BASE + 0x29C) +#define IOMUXC_SW_PAD_CTL_SD14_SD15_SD16 (IOMUXC_BASE + 0x2A0) +#define IOMUXC_SW_PAD_CTL_SD11_SD12_SD13 (IOMUXC_BASE + 0x2A4) +#define IOMUXC_SW_PAD_CTL_SD8_SD9_SD10 (IOMUXC_BASE + 0x2A8) +#define IOMUXC_SW_PAD_CTL_SD5_SD6_SD7 (IOMUXC_BASE + 0x2AC) +#define IOMUXC_SW_PAD_CTL_SD2_SD3_SD4 (IOMUXC_BASE + 0x2B0) +#define IOMUXC_SW_PAD_CTL_SDBA0_SD0_SD1 (IOMUXC_BASE + 0x2B4) +#define IOMUXC_SW_PAD_CTL_A24_A25_SDBA1 (IOMUXC_BASE + 0x2B8) +#define IOMUXC_SW_PAD_CTL_A21_A22_A23 (IOMUXC_BASE + 0x2BC) +#define IOMUXC_SW_PAD_CTL_A18_A19_A20 (IOMUXC_BASE + 0x2C0) +#define IOMUXC_SW_PAD_CTL_A15_A16_A17 (IOMUXC_BASE + 0x2C4) +#define IOMUXC_SW_PAD_CTL_A12_A13_A14 (IOMUXC_BASE + 0x2C8) +#define IOMUXC_SW_PAD_CTL_A10_MA10_A11 (IOMUXC_BASE + 0x2CC) +#define IOMUXC_SW_PAD_CTL_A7_A8_A9 (IOMUXC_BASE + 0x2D0) +#define IOMUXC_SW_PAD_CTL_A4_A5_A6 (IOMUXC_BASE + 0x2D4) +#define IOMUXC_SW_PAD_CTL_A1_A2_A3 (IOMUXC_BASE + 0x2D8) +#define IOMUXC_SW_PAD_CTL_VPG0_VPG1_A0 (IOMUXC_BASE + 0x2DC) + /* * Memory regions and CS */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 7167e9d0db2..a4862c6fc5a 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -43,10 +43,10 @@ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -/* No support for NAND boot for i.MX31 PDK yet, so we rely on some other - * program to initialize the SDRAM. - */ +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif /* * Size of malloc() pool @@ -159,4 +159,41 @@ #define CONFIG_ENV_SIZE (128 * 1024) +/* NAND configuration for the NAND_SPL */ + +/* Start copying real U-boot from the second page */ +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +/* Load U-Boot to this address */ +#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 + + +/* Configuration of lowlevel_init.S (clocks and SDRAM) */ +#define CCM_CCMR_SETUP 0x074B0BF5 +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ + PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ + PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ + PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ + PLL_MFN(12)) + +#define ESDMISC_MDDR_SETUP 0x00000004 +#define ESDMISC_MDDR_RESET_DL 0x0000000c +#define ESDCFG0_MDDR_SETUP 0x006ac73a + +#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) +#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ + ESDCTL_DSIZ(2) | ESDCTL_BL(1)) +#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) +#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) +#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) +#define ESDCTL_RW ESDCTL_SETTINGS + #endif /* __CONFIG_H */ diff --git a/nand_spl/board/freescale/mx31pdk/Makefile b/nand_spl/board/freescale/mx31pdk/Makefile new file mode 100644 index 00000000000..a9572ba6ad7 --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/Makefile @@ -0,0 +1,54 @@ +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_PRELOADER -DCONFIG_NAND_SPL + +SOBJS = start.o lowlevel_init.o +COBJS = nand_boot_fsl_nfc.o + +SRCS := $(SRCTREE)/nand_spl/nand_boot_fsl_nfc.c +SRCS += $(SRCTREE)/cpu/arm1136/start.S +SRCS += $(SRCTREE)/board/freescale/mx31pdk/lowlevel_init.S +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $@ + +######################################################################### + +$(obj)%.o: $(SRCTREE)/cpu/arm1136/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/board/freescale/mx31pdk/%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(SRCTREE)/nand_spl/%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/freescale/mx31pdk/config.mk b/nand_spl/board/freescale/mx31pdk/config.mk new file mode 100644 index 00000000000..68afbf1dccf --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/config.mk @@ -0,0 +1 @@ +PAD_TO := 2048 diff --git a/nand_spl/board/freescale/mx31pdk/u-boot.lds b/nand_spl/board/freescale/mx31pdk/u-boot.lds new file mode 100644 index 00000000000..edd843089b0 --- /dev/null +++ b/nand_spl/board/freescale/mx31pdk/u-boot.lds @@ -0,0 +1,36 @@ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + lowlevel_init.o (.text) + nand_boot_fsl_nfc.o (.text) + *(.text) + . = 2K; + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} -- cgit v1.3.1