From 021382cad2fbe8a2cb69ea682e348ecd0bbedae2 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 19 Oct 2012 08:35:12 +0000 Subject: powerpc/qoriq: Move FMAN microcode location Move FMAN microcude from 0xEF000000 to 0xEFF40000 to free up the beginning of this virtual bank so that this bank can store RCW or be used together with other banks to store large images. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- include/configs/P1023RDS.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/corenet_ds.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/P1023RDS.h b/include/configs/P1023RDS.h index 800d666ab23..878bd5fa5e6 100644 --- a/include/configs/P1023RDS.h +++ b/include/configs/P1023RDS.h @@ -524,7 +524,7 @@ extern unsigned long get_clock_freq(void); /* Default address of microcode for the Linux Fman driver */ /* QE microcode/firmware address */ #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x1f00000 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 5cdb628ab17..e2f86dbb862 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -539,7 +539,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index c41b0399964..3f42cd9a38e 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -549,7 +549,7 @@ #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR -#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF40000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -- cgit v1.3.1 From d31e53b42c35a9285c1e688733ceaa995689418b Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 23 Oct 2012 09:40:22 +0000 Subject: powerpc/85xx: add support for the Freescale P5040DS Superhydra reference board The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi Signed-off-by: Shaohui Xie Signed-off-by: Andy Fleming --- board/freescale/common/Makefile | 2 + board/freescale/common/ngpixis.h | 2 +- board/freescale/corenet_ds/Makefile | 2 + board/freescale/corenet_ds/corenet_ds.c | 22 +- board/freescale/corenet_ds/eth_superhydra.c | 722 ++++++++++++++++++++++++++++ board/freescale/corenet_ds/p5040ds_ddr.c | 18 + boards.cfg | 1 + drivers/net/fm/Makefile | 1 + drivers/net/fm/p5040.c | 113 +++++ include/configs/P5040DS.h | 40 ++ 10 files changed, 916 insertions(+), 7 deletions(-) create mode 100644 board/freescale/corenet_ds/eth_superhydra.c create mode 100644 board/freescale/corenet_ds/p5040ds_ddr.c create mode 100644 drivers/net/fm/p5040.c create mode 100644 include/configs/P5040DS.h (limited to 'include') diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 36f7c4f30f4..75725b49ad8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +COBJS-$(CONFIG_P5040DS) += ics307_clk.o COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o # deal with common files for P-series corenet based devices @@ -60,6 +61,7 @@ SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 1d4483d8b9d..a239ee31df9 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -45,7 +45,7 @@ typedef struct ngpixis { struct { u8 sw; u8 en; - } s[8]; + } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ } __attribute__ ((packed)) ngpixis_t; /* Pointer to the PIXIS register set */ diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1fdf8b706bf..d79193af2a9 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -31,9 +31,11 @@ COBJS-y += ddr.o COBJS-$(CONFIG_P3041DS) += eth_hydra.o COBJS-$(CONFIG_P4080DS) += eth_p4080.o COBJS-$(CONFIG_P5020DS) += eth_hydra.o +COBJS-$(CONFIG_P5040DS) += eth_superhydra.o COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o +COBJS-$(CONFIG_P5040DS) += p5040ds_ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index a33c936fa00..21428e33476 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -45,6 +45,7 @@ int checkboard (void) struct cpu_type *cpu = gd->cpu; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; + static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", @@ -83,20 +84,28 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { - static const char *freq[] = {"100", "125", "156.25", "212.5" }; unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } +#ifdef CONFIG_P5040DS + /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ + sw = in_8(&PIXIS_SW(9)); + printf("Bank4=%sMhz ", freq[sw & 3]); +#endif puts("\n"); #else sw = in_8(&PIXIS_SW(3)); - printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); - printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); - printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); + /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ + /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ + /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ + printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); + printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); + printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); #endif return 0; @@ -168,7 +177,8 @@ int misc_init_r(void) unsigned int i; u8 sw; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c new file mode 100644 index 00000000000..ef9de25bd8f --- /dev/null +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -0,0 +1,722 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Author: Srikanth Srinivasan + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference + * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are + * provided by the standard Freescale four-port SGMII riser card. The 10Gb + * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans + * and 5 1G interfaces and 10G interface per FMan. Based on the options in + * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. + * + * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is + * always the same (0). The value for SGMII depends on which slot the riser is + * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, + * the value is based on which slot the XAUI is inserted in. + * + * The SERDES configuration is used to determine where the SGMII and XAUI cards + * exist, and also which Fman's MACs are routed to which PHYs. So for a given + * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed + * to PHYs dynamically. + * + * + * This file also updates the device tree in three ways: + * + * 1) The status of each virtual MDIO node that is referenced by an Ethernet + * node is set to "okay". + * + * 2) The phy-handle property of each active Ethernet MAC node is set to the + * appropriate PHY node. + * + * 3) The "mux value" for each virtual MDIO node is set to the correct value, + * if necessary. Some virtual MDIO nodes do not have configurable mux + * values, so those values are hard-coded in the DTS. On the HYDRA board, + * the virtual MDIO node for the SGMII card needs to be updated. + * + * For all this to work, the device tree needs to have the following: + * + * 1) An alias for each PHY node that an Ethernet node could be routed to. + * + * 2) An alias for each real and virtual MDIO node that is disabled by default + * and might need to be enabled, and also might need to have its mux-value + * updated. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/ngpixis.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET + +#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_SLOT1 0x10 +#define BRDCFG1_EMI1_SEL_SLOT2 0x20 +#define BRDCFG1_EMI1_SEL_SLOT5 0x30 +#define BRDCFG1_EMI1_SEL_SLOT6 0x40 +#define BRDCFG1_EMI1_SEL_SLOT7 0x50 +#define BRDCFG1_EMI1_SEL_SLOT3 0x60 +#define BRDCFG1_EMI1_SEL_RGMII 0x00 +#define BRDCFG1_EMI1_EN 0x08 +#define BRDCFG1_EMI2_SEL_MASK 0x06 +#define BRDCFG1_EMI2_SEL_SLOT1 0x00 +#define BRDCFG1_EMI2_SEL_SLOT2 0x02 + +#define BRDCFG2_REG_GPIO_SEL 0x20 + +/* + * BRDCFG1 mask and value for each MAC + * + * This array contains the BRDCFG1 values (in mask/val format) that route the + * MDIO bus to a particular RGMII or SGMII PHY. + */ +static struct { + u8 mask; + u8 val; +} mdio_mux[NUM_FM_PORTS]; + +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 +}; + +/* + * Set the board muxing for a given MAC + * + * The MDIO layer calls this function every time it wants to talk to a PHY. + */ +void super_hydra_mux_mdio(u8 mask, u8 val) +{ + clrsetbits_8(&pixis->brdcfg1, mask, val); +} + +struct super_hydra_mdio { + u8 mask; + u8 val; + struct mii_dev *realbus; +}; + +static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int super_hydra_mdio_reset(struct mii_dev *bus) +{ + struct super_hydra_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) +{ + struct mii_dev *bus = miiphy_get_dev_by_name(name); + struct super_hydra_mdio *priv = bus->priv; + + priv->mask = mask; + priv->val = val; +} + +static int super_hydra_mdio_init(char *realbusname, char *fakebusname) +{ + struct super_hydra_mdio *hmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate Hydra MDIO bus\n"); + return -1; + } + + hmdio = malloc(sizeof(*hmdio)); + if (!hmdio) { + printf("Failed to allocate Hydra private data\n"); + free(bus); + return -1; + } + + bus->read = super_hydra_mdio_read; + bus->write = super_hydra_mdio_write; + bus->reset = super_hydra_mdio_reset; + sprintf(bus->name, fakebusname); + + hmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!hmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(hmdio); + return -1; + } + + bus->priv = hmdio; + + return mdio_register(bus); +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. That + * information is stored in mdio_mux[]. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + enum srds_prtcl device; + int lane, slot, phy; + char alias[32]; + + /* RGMII and XGMII are already mapped correctly in the DTS */ + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + device = serdes_device_from_fm_port(port); + lane = serdes_get_first_lane(device); + slot = lane_to_slot[lane]; + phy = fm_info_get_phy_address(port); + + sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + } +} + +#define PIXIS_SW2_LANE_23_SEL 0x80 +#define PIXIS_SW2_LANE_45_SEL 0x40 +#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 +#define PIXIS_SW2_LANE_67_SEL_5 0x00 +#define PIXIS_SW2_LANE_67_SEL_6 0x20 +#define PIXIS_SW2_LANE_67_SEL_7 0x10 +#define PIXIS_SW2_LANE_8_SEL 0x08 +#define PIXIS_SW2_LANE_1617_SEL 0x04 +#define PIXIS_SW11_LANE_9_SEL 0x04 +/* + * Initialize the lane_to_slot[] array. + * + * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board + * slots is hard-coded. On the Hydra board, however, the mapping is controlled + * by board switch SW2, so the lane_to_slot[] array needs to be dynamically + * initialized. + */ +static void initialize_lane_to_slot(void) +{ + u8 sw2 = in_8(&PIXIS_SW(2)); + /* SW11 appears in the programming model as SW9 */ + u8 sw11 = in_8(&PIXIS_SW(9)); + + lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; + lane_to_slot[3] = lane_to_slot[2]; + + lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; + lane_to_slot[5] = lane_to_slot[4]; + + switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { + case PIXIS_SW2_LANE_67_SEL_5: + lane_to_slot[6] = 5; + break; + case PIXIS_SW2_LANE_67_SEL_6: + lane_to_slot[6] = 6; + break; + case PIXIS_SW2_LANE_67_SEL_7: + lane_to_slot[6] = 7; + break; + } + lane_to_slot[7] = lane_to_slot[6]; + + lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; + lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; + + lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; + lane_to_slot[17] = lane_to_slot[16]; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +/* + * Configure the status for the virtual MDIO nodes + * + * Rather than create the virtual MDIO nodes from scratch for each active + * virtual MDIO, we expect the DTS to have the nodes defined already, and we + * only enable the ones that are actually active. + * + * We assume that the DTS already hard-codes the status for all the + * virtual MDIO nodes to "disabled", so all we need to do is enable the + * active ones. + */ +void fdt_fixup_board_enet(void *fdt) +{ +#ifdef CONFIG_FMAN_ENET + enum fm_port i; + int lane, slot; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } + +#if CONFIG_SYS_NUM_FMAN == 2 + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } +#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CONFIG_FMAN_ENET */ +} + +/* + * Mapping of SerDes Protocol to MDIO MUX value and PHY address. + * + * Fman 1: + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 2 1c | 2 1d | 2 1e | 2 1f + * 0x01 | | 6 1c | + * 0x02 | | 3 1c | 3 1d + * 0x03 2 1c | 2 1d | 2 1e | 2 1f + * 0x04 2 1c | 2 1d | 2 1e | 2 1f + * 0x05 | | 3 1c | 3 1d + * 0x06 2 1c | 2 1d | 2 1e | 2 1f + * 0x07 | | 6 1c | + * 0x11 2 1c | 2 1d | 2 1e | 2 1f + * 0x2a 2 | | 2 1e | 2 1f + * 0x34 6 1c | 6 1d | 4 1e | 4 1f + * 0x35 | | 3 1c | 3 1d + * 0x36 6 1c | 6 1d | 4 1e | 4 1f + * | | | + * Fman 2: | | | + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * EMI1 | EMI1 | EMI1 | EMI1 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 | | 6 1c | 6 1d + * 0x01 | | | + * 0x02 | | 6 1c | 6 1d + * 0x03 3 1c | 3 1d | 6 1c | 6 1d + * 0x04 3 1c | 3 1d | 6 1c | 6 1d + * 0x05 | | 6 1c | 6 1d + * 0x06 | | 6 1c | 6 1d + * 0x07 | | | + * 0x11 | | | + * 0x2a | | | + * 0x34 | | | + * 0x35 | | | + * 0x36 | | | + */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ + setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); + + memset(mdio_mux, 0, sizeof(mdio_mux)); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* Register the three virtual MDIO front-ends */ + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_RGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM1_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM2_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM1_TGEC_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM2_TGEC_MDIO"); + + /* + * Program the DTSEC PHY addresses assuming that they are all SGMII. + * For any DTSEC that's RGMII, we'll override its PHY address later. + * We assume that DTSEC5 is only used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); + +#if (CONFIG_SYS_NUM_FMAN == 2) + fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); +#endif + + switch (srds_prtcl) { + case 0: + case 3: + case 4: + case 6: + case 0x11: + case 0x2a: + case 0x34: + case 0x36: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + break; + case 1: + case 2: + case 5: + case 7: + case 0x35: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + break; + default: + printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM1@DTSEC%u is RGMII at address %u\n", + idx + 1, 0); + fm_info_set_phy_address(i, 0); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM2@DTSEC%u is RGMII at address %u\n", + idx + 1, 1); + fm_info_set_phy_address(i, 1); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman2: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM2_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); + +#endif + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c new file mode 100644 index 00000000000..e65de364d73 --- /dev/null +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -0,0 +1,18 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include +#include + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {0, 0, NULL} +}; diff --git a/boards.cfg b/boards.cfg index 7ae663c7d96..1f49b4840bf 100644 --- a/boards.cfg +++ b/boards.cfg @@ -848,6 +848,7 @@ P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P5020DS_SRIO_PCIE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000 +P5040DS powerpc mpc85xx corenet_ds freescale BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/drivers/net/fm/Makefile b/drivers/net/fm/Makefile index 7a1fcdd81fb..7fbb50a5623 100644 --- a/drivers/net/fm/Makefile +++ b/drivers/net/fm/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_PPC_P2041) += p5020.o COBJS-$(CONFIG_PPC_P3041) += p5020.o COBJS-$(CONFIG_PPC_P4080) += p4080.o COBJS-$(CONFIG_PPC_P5020) += p5020.o +COBJS-$(CONFIG_PPC_P5040) += p5040.o COBJS-$(CONFIG_PPC_T4240) += t4240.o COBJS-$(CONFIG_PPC_B4860) += b4860.o endif diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c new file mode 100644 index 00000000000..bc6b4ba0bb8 --- /dev/null +++ b/drivers/net/fm/p5040.c @@ -0,0 +1,113 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include + +u32 port_to_devdisr[] = { + [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1, + [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2, + [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3, + [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4, + [FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5, + [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1, + [FM2_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC2_1, + [FM2_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC2_2, + [FM2_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC2_3, + [FM2_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC2_4, + [FM2_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC2_5, + [FM2_10GEC1] = FSL_CORENET_DEVDISR2_10GEC2, +}; + +static int is_device_disabled(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 devdisr2 = in_be32(&gur->devdisr2); + + return port_to_devdisr[port] & devdisr2; +} + +void fman_disable_port(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); +} + +phy_interface_t fman_port_enet_if(enum fm_port port) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + + if (is_device_disabled(port)) + return PHY_INTERFACE_MODE_NONE; + + if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) + return PHY_INTERFACE_MODE_XGMII; + + if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) + return PHY_INTERFACE_MODE_XGMII; + + /* handle RGMII first */ + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == + FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) + return PHY_INTERFACE_MODE_RGMII; + + if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == + FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) + return PHY_INTERFACE_MODE_MII; + + switch (port) { + case FM1_DTSEC1: + case FM1_DTSEC2: + case FM1_DTSEC3: + case FM1_DTSEC4: + case FM1_DTSEC5: + if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + case FM2_DTSEC1: + case FM2_DTSEC2: + case FM2_DTSEC3: + case FM2_DTSEC4: + case FM2_DTSEC5: + if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) + return PHY_INTERFACE_MODE_SGMII; + break; + default: + return PHY_INTERFACE_MODE_NONE; + } + + return PHY_INTERFACE_MODE_NONE; +} diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h new file mode 100644 index 00000000000..50d9e541a80 --- /dev/null +++ b/include/configs/P5040DS.h @@ -0,0 +1,40 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P5040 DS board configuration file + * + */ +#define CONFIG_P5040DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P5040 + +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#define CONFIG_MMC +#define CONFIG_NAND_FSL_ELBC +#define CONFIG_PCIE3 +#define CONFIG_SYS_FSL_RAID_ENGINE + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" -- cgit v1.3.1 From ca1b0b89568cecaf2ecdbcbef714722d70021094 Mon Sep 17 00:00:00 2001 From: York Sun Date: Fri, 26 Oct 2012 16:40:15 +0000 Subject: powerpc/P2041RDB: Fix Flash address LAW address P2041RDB uses common corenet TLB and LAW. However it doesn't have promjet connector. It is necessary to use the same base address for correct LAW address. An offset is added for NOR flash. Signed-off-by: York Sun Signed-off-by: Andy Fleming --- include/configs/P2041RDB.h | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e2f86dbb862..c888d7a014c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -202,15 +202,21 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* Set the local bus clock 1/8 of platform clock */ #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 -#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ +/* + * This board doesn't have a promjet connector. + * However, it uses commone corenet board LAW and TLB. + * It is necessary to use the same start address with proper offset. + */ +#define CONFIG_SYS_FLASH_BASE 0xe0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull #else #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif #define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) + (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ + BR_PS_16 | BR_V) #define CONFIG_SYS_FLASH_OR_PRELIM \ ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) @@ -294,7 +300,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -- cgit v1.3.1 From 9760b274df8fdc5a6d124f3192535ebe281a78a6 Mon Sep 17 00:00:00 2001 From: Zang Roy-R61911 Date: Mon, 26 Nov 2012 00:05:38 +0000 Subject: powerpc/corenet_ds: move SATA config to board configuration board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang Signed-off-by: Andy Fleming --- arch/powerpc/include/asm/config_mpc85xx.h | 7 ------- include/configs/P1010RDB.h | 1 + include/configs/P1022DS.h | 1 + include/configs/P2041RDB.h | 4 +++- include/configs/P3041DS.h | 1 + include/configs/P5020DS.h | 1 + 6 files changed, 7 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1ccc5c54e24..965d4312c78 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -137,7 +137,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -181,7 +180,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -194,7 +192,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -248,7 +245,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -324,7 +320,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -357,7 +352,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -435,7 +429,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 57aef21e96c..437ee6ee6b9 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -553,6 +553,7 @@ extern unsigned long get_sdram_size(void); /* SATA */ #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2 #define CONFIG_LIBATA #ifdef CONFIG_FSL_SATA diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b3c850d584e..14d597aad26 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -360,6 +360,7 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c888d7a014c..8b9b0dbc221 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -566,8 +566,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ /* SATA */ +#define CONFIG_FSL_SATA_V2 + +#ifdef CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA -#ifdef CONFIG_FSL_SATA #define CONFIG_LIBATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index cf184e74ab8..ce8f9b0b2eb 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -32,6 +32,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 7018d7a3221..778230d3356 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -32,6 +32,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE -- cgit v1.3.1