From 95c3b0635ea4323c82e3f7ecdac69460897a907c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 19 Oct 2023 15:51:39 +0100 Subject: sunxi: dts: arm64: update devicetree files from Linux-v6.6-rc6 Sync the devicetree files from the official Linux kernel tree, v6.6-rc6. This is covering Allwinner SoCs with 64-bit ARM cores. Only small cosmetic changes (clock name fixed), but we add the DT for the new OrangePi Zero 3 board, for which U-Boot enablement patches are pending. As before, this omits the non-backwards compatible changes to the R_INTC controller, to remain compatible with older kernels. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- include/dt-bindings/clock/sun50i-h6-ccu.h | 2 +- include/dt-bindings/clock/sun50i-h616-ccu.h | 2 +- include/dt-bindings/clock/sun6i-rtc.h | 2 +- include/dt-bindings/reset/sun50i-h6-ccu.h | 2 +- include/dt-bindings/reset/sun50i-h6-r-ccu.h | 2 +- include/dt-bindings/reset/sun50i-h616-ccu.h | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/sun50i-h6-ccu.h b/include/dt-bindings/clock/sun50i-h6-ccu.h index a1545cd60e7..ef9123d8193 100644 --- a/include/dt-bindings/clock/sun50i-h6-ccu.h +++ b/include/dt-bindings/clock/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng */ diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h index 1191aca53ac..6f8f01e6762 100644 --- a/include/dt-bindings/clock/sun50i-h616-ccu.h +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ diff --git a/include/dt-bindings/clock/sun6i-rtc.h b/include/dt-bindings/clock/sun6i-rtc.h index c845493e4d3..3bd3aa3d57c 100644 --- a/include/dt-bindings/clock/sun6i-rtc.h +++ b/include/dt-bindings/clock/sun6i-rtc.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ #ifndef _DT_BINDINGS_CLK_SUN6I_RTC_H_ #define _DT_BINDINGS_CLK_SUN6I_RTC_H_ diff --git a/include/dt-bindings/reset/sun50i-h6-ccu.h b/include/dt-bindings/reset/sun50i-h6-ccu.h index 81106f45509..d038ddfa481 100644 --- a/include/dt-bindings/reset/sun50i-h6-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-ccu.h @@ -1,4 +1,4 @@ -// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2017 Icenowy Zheng */ diff --git a/include/dt-bindings/reset/sun50i-h6-r-ccu.h b/include/dt-bindings/reset/sun50i-h6-r-ccu.h index 7950e799c76..d541ade884f 100644 --- a/include/dt-bindings/reset/sun50i-h6-r-ccu.h +++ b/include/dt-bindings/reset/sun50i-h6-r-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2016 Icenowy Zheng */ diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h index cb6285a8d12..1bd8bb0a11b 100644 --- a/include/dt-bindings/reset/sun50i-h616-ccu.h +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ /* * Copyright (C) 2020 Arm Ltd. */ -- cgit v1.3.1 From a14c250625570bb545d06c0e5b21445eb1b15716 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Thu, 19 Oct 2023 15:45:32 +0100 Subject: sunxi: dts: arm: add T113s/D1 DT files from Linux-v6.6-rc6 This copies in some devicetree files from the official Linux kernel tree, v6.6-rc6. It covers a board with the Allwinner T113s SoC, which shares many devices with its RISC-V sibling, the Allwinner D1(s). This is the reason for the core .dtsi files landing in the arch/riscv directory. We are only adjusting the include path to accommodate for the differences in the U-Boot build system. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 + arch/arm/dts/sun8i-t113s.dtsi | 59 ++ arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 ++++ arch/riscv/dts/sunxi-d1-t113.dtsi | 15 + arch/riscv/dts/sunxi-d1s-t113.dtsi | 927 +++++++++++++++++++++++++ include/dt-bindings/clock/sun20i-d1-ccu.h | 158 +++++ include/dt-bindings/clock/sun20i-d1-r-ccu.h | 19 + include/dt-bindings/reset/sun20i-d1-ccu.h | 79 +++ include/dt-bindings/reset/sun20i-d1-r-ccu.h | 16 + 9 files changed, 1434 insertions(+) create mode 100644 arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/dts/sun8i-t113s.dtsi create mode 100644 arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi create mode 100644 arch/riscv/dts/sunxi-d1-t113.dtsi create mode 100644 arch/riscv/dts/sunxi-d1s-t113.dtsi create mode 100644 include/dt-bindings/clock/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/clock/sun20i-d1-r-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-ccu.h create mode 100644 include/dt-bindings/reset/sun20i-d1-r-ccu.h (limited to 'include') diff --git a/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts new file mode 100644 index 00000000000..8b3a7538381 --- /dev/null +++ b/arch/arm/dts/sun8i-t113s-mangopi-mq-r-t113.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2022 Arm Ltd. + +#include + +/dts-v1/; + +#include "sun8i-t113s.dtsi" +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" + +/ { + model = "MangoPi MQ-R-T113"; + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; + + aliases { + ethernet0 = &rtl8189ftv; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&mmc1 { + rtl8189ftv: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-t113s.dtsi new file mode 100644 index 00000000000..b94b69142af --- /dev/null +++ b/arch/arm/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include <../../riscv/dts/sunxi-d1s-t113.dtsi> +#include <../../riscv/dts/sunxi-d1-t113.dtsi> + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi new file mode 100644 index 00000000000..a415c4a78a7 --- /dev/null +++ b/arch/arm/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +// Copyright (C) 2022 Arm Ltd. +/* + * Common peripherals and configurations for MangoPi MQ-R boards. + */ + +#include +#include + +/ { + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + /* board wide 5V supply directly from the USB-C socket */ + reg_vcc5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc5v>; + }; + + /* XC6206 LDO on the board */ + reg_avdd2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_3v3>; + vcc-pd-supply = <®_3v3>; + vcc-pe-supply = <®_avdd2v8>; + vcc-pf-supply = <®_3v3>; + vcc-pg-supply = <®_3v3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pb_pins>; + status = "okay"; +}; + +/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; diff --git a/arch/riscv/dts/sunxi-d1-t113.dtsi b/arch/riscv/dts/sunxi-d1-t113.dtsi new file mode 100644 index 00000000000..b7156123df5 --- /dev/null +++ b/arch/riscv/dts/sunxi-d1-t113.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +/ { + soc { + dsp_wdt: watchdog@1700400 { + compatible = "allwinner,sun20i-d1-wdt"; + reg = <0x1700400 0x20>; + interrupts = ; + clocks = <&dcxo>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "reserved"; + }; + }; +}; diff --git a/arch/riscv/dts/sunxi-d1s-t113.dtsi b/arch/riscv/dts/sunxi-d1s-t113.dtsi new file mode 100644 index 00000000000..822f022eec2 --- /dev/null +++ b/arch/riscv/dts/sunxi-d1s-t113.dtsi @@ -0,0 +1,927 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2021-2022 Samuel Holland + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + dcxo: dcxo-clk { + compatible = "fixed-clock"; + clock-output-names = "dcxo"; + #clock-cells = <0>; + }; + + de: display-engine { + compatible = "allwinner,sun20i-d1-display-engine"; + allwinner,pipelines = <&mixer0>, <&mixer1>; + status = "disabled"; + }; + + soc { + compatible = "simple-bus"; + ranges; + dma-noncoherent; + #address-cells = <1>; + #size-cells = <1>; + + pio: pinctrl@2000000 { + compatible = "allwinner,sun20i-d1-pinctrl"; + reg = <0x2000000 0x800>; + interrupts = , + , + , + , + , + ; + clocks = <&ccu CLK_APB0>, + <&dcxo>, + <&rtc CLK_OSC32K>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + interrupt-controller; + #gpio-cells = <3>; + #interrupt-cells = <3>; + + /omit-if-no-ref/ + can0_pins: can0-pins { + pins = "PB2", "PB3"; + function = "can0"; + }; + + /omit-if-no-ref/ + can1_pins: can1-pins { + pins = "PB4", "PB5"; + function = "can1"; + }; + + /omit-if-no-ref/ + clk_pg11_pin: clk-pg11-pin { + pins = "PG11"; + function = "clk"; + }; + + /omit-if-no-ref/ + dsi_4lane_pins: dsi-4lane-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9"; + drive-strength = <30>; + function = "dsi"; + }; + + /omit-if-no-ref/ + lcd_rgb666_pins: lcd-rgb666-pins { + pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", + "PD6", "PD7", "PD8", "PD9", "PD10", "PD11", + "PD12", "PD13", "PD14", "PD15", "PD16", "PD17", + "PD18", "PD19", "PD20", "PD21"; + function = "lcd0"; + }; + + /omit-if-no-ref/ + mmc0_pins: mmc0-pins { + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; + function = "mmc0"; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins = "PG0", "PG1", "PG2", "PG3", "PG4", "PG5"; + function = "mmc1"; + }; + + /omit-if-no-ref/ + mmc2_pins: mmc2-pins { + pins = "PC2", "PC3", "PC4", "PC5", "PC6", "PC7"; + function = "mmc2"; + }; + + /omit-if-no-ref/ + rgmii_pe_pins: rgmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE11", "PE12", "PE13", "PE14", "PE15"; + function = "emac"; + }; + + /omit-if-no-ref/ + rmii_pe_pins: rmii-pe-pins { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9"; + function = "emac"; + }; + + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5"; + function = "spi0"; + }; + + /omit-if-no-ref/ + uart1_pg6_pins: uart1-pg6-pins { + pins = "PG6", "PG7"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart1_pg8_rts_cts_pins: uart1-pg8-rts-cts-pins { + pins = "PG8", "PG9"; + function = "uart1"; + }; + + /omit-if-no-ref/ + uart3_pb_pins: uart3-pb-pins { + pins = "PB6", "PB7"; + function = "uart3"; + }; + }; + + ccu: clock-controller@2001000 { + compatible = "allwinner,sun20i-d1-ccu"; + reg = <0x2001000 0x1000>; + clocks = <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>; + clock-names = "hosc", "losc", "iosc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpadc: adc@2009000 { + compatible = "allwinner,sun20i-d1-gpadc"; + reg = <0x2009000 0x400>; + clocks = <&ccu CLK_BUS_GPADC>; + resets = <&ccu RST_BUS_GPADC>; + interrupts = ; + status = "disabled"; + #io-channel-cells = <1>; + }; + + dmic: dmic@2031000 { + compatible = "allwinner,sun20i-d1-dmic", + "allwinner,sun50i-h6-dmic"; + reg = <0x2031000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMIC>, + <&ccu CLK_DMIC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_DMIC>; + dmas = <&dma 8>; + dma-names = "rx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + i2s1: i2s@2033000 { + compatible = "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x2033000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S1>, + <&ccu CLK_I2S1>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S1>; + dmas = <&dma 4>, <&dma 4>; + dma-names = "rx", "tx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + i2s2: i2s@2034000 { + compatible = "allwinner,sun20i-d1-i2s", + "allwinner,sun50i-r329-i2s"; + reg = <0x2034000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2S2>, + <&ccu CLK_I2S2>; + clock-names = "apb", "mod"; + resets = <&ccu RST_BUS_I2S2>; + dmas = <&dma 5>, <&dma 5>; + dma-names = "rx", "tx"; + status = "disabled"; + #sound-dai-cells = <0>; + }; + + timer: timer@2050000 { + compatible = "allwinner,sun20i-d1-timer", + "allwinner,sun8i-a23-timer"; + reg = <0x2050000 0xa0>; + interrupts = , + ; + clocks = <&dcxo>; + }; + + wdt: watchdog@20500a0 { + compatible = "allwinner,sun20i-d1-wdt-reset", + "allwinner,sun20i-d1-wdt"; + reg = <0x20500a0 0x20>; + interrupts = ; + clocks = <&dcxo>, <&rtc CLK_OSC32K>; + clock-names = "hosc", "losc"; + status = "reserved"; + }; + + uart0: serial@2500000 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART0>; + resets = <&ccu RST_BUS_UART0>; + dmas = <&dma 14>, <&dma 14>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@2500400 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART1>; + resets = <&ccu RST_BUS_UART1>; + dmas = <&dma 15>, <&dma 15>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@2500800 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500800 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART2>; + resets = <&ccu RST_BUS_UART2>; + dmas = <&dma 16>, <&dma 16>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart3: serial@2500c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x2500c00 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART3>; + resets = <&ccu RST_BUS_UART3>; + dmas = <&dma 17>, <&dma 17>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart4: serial@2501000 { + compatible = "snps,dw-apb-uart"; + reg = <0x2501000 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART4>; + resets = <&ccu RST_BUS_UART4>; + dmas = <&dma 18>, <&dma 18>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart5: serial@2501400 { + compatible = "snps,dw-apb-uart"; + reg = <0x2501400 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clocks = <&ccu CLK_BUS_UART5>; + resets = <&ccu RST_BUS_UART5>; + dmas = <&dma 19>, <&dma 19>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + i2c0: i2c@2502000 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + dmas = <&dma 43>, <&dma 43>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@2502400 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + dmas = <&dma 44>, <&dma 44>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@2502800 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502800 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + dmas = <&dma 45>, <&dma 45>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c3: i2c@2502c00 { + compatible = "allwinner,sun20i-d1-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg = <0x2502c00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C3>; + resets = <&ccu RST_BUS_I2C3>; + dmas = <&dma 46>, <&dma 46>; + dma-names = "rx", "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + can0: can@2504000 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN0>; + resets = <&ccu RST_BUS_CAN0>; + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins>; + status = "disabled"; + }; + + can1: can@2504400 { + compatible = "allwinner,sun20i-d1-can"; + reg = <0x02504400 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_CAN1>; + resets = <&ccu RST_BUS_CAN1>; + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins>; + status = "disabled"; + }; + + syscon: syscon@3000000 { + compatible = "allwinner,sun20i-d1-system-control"; + reg = <0x3000000 0x1000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + }; + + dma: dma-controller@3002000 { + compatible = "allwinner,sun20i-d1-dma"; + reg = <0x3002000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; + clock-names = "bus", "mbus"; + resets = <&ccu RST_BUS_DMA>; + dma-channels = <16>; + dma-requests = <48>; + #dma-cells = <1>; + }; + + sid: efuse@3006000 { + compatible = "allwinner,sun20i-d1-sid"; + reg = <0x3006000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + + mbus: dram-controller@3102000 { + compatible = "allwinner,sun20i-d1-mbus"; + reg = <0x3102000 0x1000>, + <0x3103000 0x1000>; + reg-names = "mbus", "dram"; + interrupts = ; + clocks = <&ccu CLK_MBUS>, + <&ccu CLK_DRAM>, + <&ccu CLK_BUS_DRAM>; + clock-names = "mbus", "dram", "bus"; + dma-ranges = <0 0x40000000 0x80000000>; + #address-cells = <1>; + #size-cells = <1>; + #interconnect-cells = <1>; + }; + + mmc0: mmc@4020000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4020000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC0>; + reset-names = "ahb"; + cap-sd-highspeed; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc1: mmc@4021000 { + compatible = "allwinner,sun20i-d1-mmc"; + reg = <0x4021000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC1>; + reset-names = "ahb"; + cap-sd-highspeed; + max-frequency = <150000000>; + no-mmc; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + mmc2: mmc@4022000 { + compatible = "allwinner,sun20i-d1-emmc", + "allwinner,sun50i-a100-emmc"; + reg = <0x4022000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names = "ahb", "mmc"; + resets = <&ccu RST_BUS_MMC2>; + reset-names = "ahb"; + cap-mmc-highspeed; + max-frequency = <150000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + no-sd; + no-sdio; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x04025000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x04026000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + usb_otg: usb@4100000 { + compatible = "allwinner,sun20i-d1-musb", + "allwinner,sun8i-a33-musb"; + reg = <0x4100000 0x400>; + interrupts = ; + interrupt-names = "mc"; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + extcon = <&usbphy 0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + usbphy: phy@4100400 { + compatible = "allwinner,sun20i-d1-usb-phy"; + reg = <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names = "phy_ctrl", + "pmu0", + "pmu1"; + clocks = <&dcxo>, + <&dcxo>; + clock-names = "usb0_phy", + "usb1_phy"; + resets = <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names = "usb0_reset", + "usb1_reset"; + status = "disabled"; + #phy-cells = <1>; + }; + + ehci0: usb@4101000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4101000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci0: usb@4101400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4101400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets = <&ccu RST_BUS_OHCI0>; + phys = <&usbphy 0>; + phy-names = "usb"; + status = "disabled"; + }; + + ehci1: usb@4200000 { + compatible = "allwinner,sun20i-d1-ehci", + "generic-ehci"; + reg = <0x4200000 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + ohci1: usb@4200400 { + compatible = "allwinner,sun20i-d1-ohci", + "generic-ohci"; + reg = <0x4200400 0x100>; + interrupts = ; + clocks = <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets = <&ccu RST_BUS_OHCI1>; + phys = <&usbphy 1>; + phy-names = "usb"; + status = "disabled"; + }; + + emac: ethernet@4500000 { + compatible = "allwinner,sun20i-d1-emac", + "allwinner,sun50i-a64-emac"; + reg = <0x4500000 0x10000>; + interrupts = ; + interrupt-names = "macirq"; + clocks = <&ccu CLK_BUS_EMAC>; + clock-names = "stmmaceth"; + resets = <&ccu RST_BUS_EMAC>; + reset-names = "stmmaceth"; + syscon = <&syscon>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + display_clocks: clock-controller@5000000 { + compatible = "allwinner,sun20i-d1-de2-clk", + "allwinner,sun50i-h5-de2-clk"; + reg = <0x5000000 0x10000>; + clocks = <&ccu CLK_BUS_DE>, <&ccu CLK_DE>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_DE>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + mixer0: mixer@5100000 { + compatible = "allwinner,sun20i-d1-de2-mixer-0"; + reg = <0x5100000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER0>, + <&display_clocks CLK_MIXER0>; + clock-names = "bus", "mod"; + resets = <&display_clocks RST_MIXER0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer0_out: port@1 { + reg = <1>; + + mixer0_out_tcon_top_mixer0: endpoint { + remote-endpoint = <&tcon_top_mixer0_in_mixer0>; + }; + }; + }; + }; + + mixer1: mixer@5200000 { + compatible = "allwinner,sun20i-d1-de2-mixer-1"; + reg = <0x5200000 0x100000>; + clocks = <&display_clocks CLK_BUS_MIXER1>, + <&display_clocks CLK_MIXER1>; + clock-names = "bus", "mod"; + resets = <&display_clocks RST_MIXER1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + mixer1_out: port@1 { + reg = <1>; + + mixer1_out_tcon_top_mixer1: endpoint { + remote-endpoint = <&tcon_top_mixer1_in_mixer1>; + }; + }; + }; + }; + + dsi: dsi@5450000 { + compatible = "allwinner,sun20i-d1-mipi-dsi", + "allwinner,sun50i-a100-mipi-dsi"; + reg = <0x5450000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&tcon_top CLK_TCON_TOP_DSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + phys = <&dphy>; + phy-names = "dphy"; + status = "disabled"; + + port { + dsi_in_tcon_lcd0: endpoint { + remote-endpoint = <&tcon_lcd0_out_dsi>; + }; + }; + }; + + dphy: phy@5451000 { + compatible = "allwinner,sun20i-d1-mipi-dphy", + "allwinner,sun50i-a100-mipi-dphy"; + reg = <0x5451000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_MIPI_DSI>, + <&ccu CLK_MIPI_DSI>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_MIPI_DSI>; + #phy-cells = <0>; + }; + + tcon_top: tcon-top@5460000 { + compatible = "allwinner,sun20i-d1-tcon-top"; + reg = <0x5460000 0x1000>; + clocks = <&ccu CLK_BUS_DPSS_TOP>, + <&ccu CLK_TCON_TV>, + <&ccu CLK_TVE>, + <&ccu CLK_TCON_LCD0>; + clock-names = "bus", "tcon-tv0", "tve0", "dsi"; + clock-output-names = "tcon-top-tv0", "tcon-top-dsi"; + resets = <&ccu RST_BUS_DPSS_TOP>; + #clock-cells = <1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_in: port@0 { + reg = <0>; + + tcon_top_mixer0_in_mixer0: endpoint { + remote-endpoint = <&mixer0_out_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer0_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer0_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer0>; + }; + + tcon_top_mixer0_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer0>; + }; + }; + + tcon_top_mixer1_in: port@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_in_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&mixer1_out_tcon_top_mixer1>; + }; + }; + + tcon_top_mixer1_out: port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_top_mixer1_out_tcon_lcd0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_lcd0_in_tcon_top_mixer1>; + }; + + tcon_top_mixer1_out_tcon_tv0: endpoint@2 { + reg = <2>; + remote-endpoint = <&tcon_tv0_in_tcon_top_mixer1>; + }; + }; + + tcon_top_hdmi_in: port@4 { + reg = <4>; + + tcon_top_hdmi_in_tcon_tv0: endpoint { + remote-endpoint = <&tcon_tv0_out_tcon_top_hdmi>; + }; + }; + + tcon_top_hdmi_out: port@5 { + reg = <5>; + }; + }; + }; + + tcon_lcd0: lcd-controller@5461000 { + compatible = "allwinner,sun20i-d1-tcon-lcd"; + reg = <0x5461000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_LCD0>, + <&ccu CLK_TCON_LCD0>; + clock-names = "ahb", "tcon-ch0"; + clock-output-names = "tcon-pixel-clock"; + resets = <&ccu RST_BUS_TCON_LCD0>, + <&ccu RST_BUS_LVDS0>; + reset-names = "lcd", "lvds"; + #clock-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_lcd0>; + }; + + tcon_lcd0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_lcd0>; + }; + }; + + tcon_lcd0_out: port@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_lcd0_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_tcon_lcd0>; + }; + }; + }; + }; + + tcon_tv0: lcd-controller@5470000 { + compatible = "allwinner,sun20i-d1-tcon-tv"; + reg = <0x5470000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_TCON_TV>, + <&tcon_top CLK_TCON_TOP_TV0>; + clock-names = "ahb", "tcon-ch1"; + resets = <&ccu RST_BUS_TCON_TV>; + reset-names = "lcd"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in: port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + tcon_tv0_in_tcon_top_mixer0: endpoint@0 { + reg = <0>; + remote-endpoint = <&tcon_top_mixer0_out_tcon_tv0>; + }; + + tcon_tv0_in_tcon_top_mixer1: endpoint@1 { + reg = <1>; + remote-endpoint = <&tcon_top_mixer1_out_tcon_tv0>; + }; + }; + + tcon_tv0_out: port@1 { + reg = <1>; + + tcon_tv0_out_tcon_top_hdmi: endpoint { + remote-endpoint = <&tcon_top_hdmi_in_tcon_tv0>; + }; + }; + }; + }; + + ppu: power-controller@7001000 { + compatible = "allwinner,sun20i-d1-ppu"; + reg = <0x7001000 0x1000>; + clocks = <&r_ccu CLK_BUS_R_PPU>; + resets = <&r_ccu RST_BUS_R_PPU>; + #power-domain-cells = <1>; + }; + + r_ccu: clock-controller@7010000 { + compatible = "allwinner,sun20i-d1-r-ccu"; + reg = <0x7010000 0x400>; + clocks = <&dcxo>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_DIV3>; + clock-names = "hosc", "losc", "iosc", "pll-periph"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + rtc: rtc@7090000 { + compatible = "allwinner,sun20i-d1-rtc", + "allwinner,sun50i-r329-rtc"; + reg = <0x7090000 0x400>; + interrupts = ; + clocks = <&r_ccu CLK_BUS_R_RTC>, + <&dcxo>, + <&r_ccu CLK_R_AHB>; + clock-names = "bus", "hosc", "ahb"; + #clock-cells = <1>; + }; + }; +}; diff --git a/include/dt-bindings/clock/sun20i-d1-ccu.h b/include/dt-bindings/clock/sun20i-d1-ccu.h new file mode 100644 index 00000000000..fdbfb404f92 --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-ccu.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ + +#define CLK_PLL_CPUX 0 +#define CLK_PLL_DDR0 1 +#define CLK_PLL_PERIPH0_4X 2 +#define CLK_PLL_PERIPH0_2X 3 +#define CLK_PLL_PERIPH0_800M 4 +#define CLK_PLL_PERIPH0 5 +#define CLK_PLL_PERIPH0_DIV3 6 +#define CLK_PLL_VIDEO0_4X 7 +#define CLK_PLL_VIDEO0_2X 8 +#define CLK_PLL_VIDEO0 9 +#define CLK_PLL_VIDEO1_4X 10 +#define CLK_PLL_VIDEO1_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VE 13 +#define CLK_PLL_AUDIO0_4X 14 +#define CLK_PLL_AUDIO0_2X 15 +#define CLK_PLL_AUDIO0 16 +#define CLK_PLL_AUDIO1 17 +#define CLK_PLL_AUDIO1_DIV2 18 +#define CLK_PLL_AUDIO1_DIV5 19 +#define CLK_CPUX 20 +#define CLK_CPUX_AXI 21 +#define CLK_CPUX_APB 22 +#define CLK_PSI_AHB 23 +#define CLK_APB0 24 +#define CLK_APB1 25 +#define CLK_MBUS 26 +#define CLK_DE 27 +#define CLK_BUS_DE 28 +#define CLK_DI 29 +#define CLK_BUS_DI 30 +#define CLK_G2D 31 +#define CLK_BUS_G2D 32 +#define CLK_CE 33 +#define CLK_BUS_CE 34 +#define CLK_VE 35 +#define CLK_BUS_VE 36 +#define CLK_BUS_DMA 37 +#define CLK_BUS_MSGBOX0 38 +#define CLK_BUS_MSGBOX1 39 +#define CLK_BUS_MSGBOX2 40 +#define CLK_BUS_SPINLOCK 41 +#define CLK_BUS_HSTIMER 42 +#define CLK_AVS 43 +#define CLK_BUS_DBG 44 +#define CLK_BUS_PWM 45 +#define CLK_BUS_IOMMU 46 +#define CLK_DRAM 47 +#define CLK_MBUS_DMA 48 +#define CLK_MBUS_VE 49 +#define CLK_MBUS_CE 50 +#define CLK_MBUS_TVIN 51 +#define CLK_MBUS_CSI 52 +#define CLK_MBUS_G2D 53 +#define CLK_MBUS_RISCV 54 +#define CLK_BUS_DRAM 55 +#define CLK_MMC0 56 +#define CLK_MMC1 57 +#define CLK_MMC2 58 +#define CLK_BUS_MMC0 59 +#define CLK_BUS_MMC1 60 +#define CLK_BUS_MMC2 61 +#define CLK_BUS_UART0 62 +#define CLK_BUS_UART1 63 +#define CLK_BUS_UART2 64 +#define CLK_BUS_UART3 65 +#define CLK_BUS_UART4 66 +#define CLK_BUS_UART5 67 +#define CLK_BUS_I2C0 68 +#define CLK_BUS_I2C1 69 +#define CLK_BUS_I2C2 70 +#define CLK_BUS_I2C3 71 +#define CLK_SPI0 72 +#define CLK_SPI1 73 +#define CLK_BUS_SPI0 74 +#define CLK_BUS_SPI1 75 +#define CLK_EMAC_25M 76 +#define CLK_BUS_EMAC 77 +#define CLK_IR_TX 78 +#define CLK_BUS_IR_TX 79 +#define CLK_BUS_GPADC 80 +#define CLK_BUS_THS 81 +#define CLK_I2S0 82 +#define CLK_I2S1 83 +#define CLK_I2S2 84 +#define CLK_I2S2_ASRC 85 +#define CLK_BUS_I2S0 86 +#define CLK_BUS_I2S1 87 +#define CLK_BUS_I2S2 88 +#define CLK_SPDIF_TX 89 +#define CLK_SPDIF_RX 90 +#define CLK_BUS_SPDIF 91 +#define CLK_DMIC 92 +#define CLK_BUS_DMIC 93 +#define CLK_AUDIO_DAC 94 +#define CLK_AUDIO_ADC 95 +#define CLK_BUS_AUDIO 96 +#define CLK_USB_OHCI0 97 +#define CLK_USB_OHCI1 98 +#define CLK_BUS_OHCI0 99 +#define CLK_BUS_OHCI1 100 +#define CLK_BUS_EHCI0 101 +#define CLK_BUS_EHCI1 102 +#define CLK_BUS_OTG 103 +#define CLK_BUS_LRADC 104 +#define CLK_BUS_DPSS_TOP 105 +#define CLK_HDMI_24M 106 +#define CLK_HDMI_CEC_32K 107 +#define CLK_HDMI_CEC 108 +#define CLK_BUS_HDMI 109 +#define CLK_MIPI_DSI 110 +#define CLK_BUS_MIPI_DSI 111 +#define CLK_TCON_LCD0 112 +#define CLK_BUS_TCON_LCD0 113 +#define CLK_TCON_TV 114 +#define CLK_BUS_TCON_TV 115 +#define CLK_TVE 116 +#define CLK_BUS_TVE_TOP 117 +#define CLK_BUS_TVE 118 +#define CLK_TVD 119 +#define CLK_BUS_TVD_TOP 120 +#define CLK_BUS_TVD 121 +#define CLK_LEDC 122 +#define CLK_BUS_LEDC 123 +#define CLK_CSI_TOP 124 +#define CLK_CSI_MCLK 125 +#define CLK_BUS_CSI 126 +#define CLK_TPADC 127 +#define CLK_BUS_TPADC 128 +#define CLK_BUS_TZMA 129 +#define CLK_DSP 130 +#define CLK_BUS_DSP_CFG 131 +#define CLK_RISCV 132 +#define CLK_RISCV_AXI 133 +#define CLK_BUS_RISCV_CFG 134 +#define CLK_FANOUT_24M 135 +#define CLK_FANOUT_12M 136 +#define CLK_FANOUT_16M 137 +#define CLK_FANOUT_25M 138 +#define CLK_FANOUT_32K 139 +#define CLK_FANOUT_27M 140 +#define CLK_FANOUT_PCLK 141 +#define CLK_FANOUT0 142 +#define CLK_FANOUT1 143 +#define CLK_FANOUT2 144 +#define CLK_BUS_CAN0 145 +#define CLK_BUS_CAN1 146 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun20i-d1-r-ccu.h b/include/dt-bindings/clock/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..f95c170711e --- /dev/null +++ b/include/dt-bindings/clock/sun20i-d1-r-ccu.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ + +#define CLK_R_AHB 0 + +#define CLK_BUS_R_TIMER 2 +#define CLK_BUS_R_TWD 3 +#define CLK_BUS_R_PPU 4 +#define CLK_R_IR_RX 5 +#define CLK_BUS_R_IR_RX 6 +#define CLK_BUS_R_RTC 7 +#define CLK_BUS_R_CPUCFG 8 + +#endif /* _DT_BINDINGS_CLK_SUN20I_D1_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-ccu.h b/include/dt-bindings/reset/sun20i-d1-ccu.h new file mode 100644 index 00000000000..79e52aca591 --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-ccu.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2020 huangzhenwei@allwinnertech.com + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_DE 1 +#define RST_BUS_DI 2 +#define RST_BUS_G2D 3 +#define RST_BUS_CE 4 +#define RST_BUS_VE 5 +#define RST_BUS_DMA 6 +#define RST_BUS_MSGBOX0 7 +#define RST_BUS_MSGBOX1 8 +#define RST_BUS_MSGBOX2 9 +#define RST_BUS_SPINLOCK 10 +#define RST_BUS_HSTIMER 11 +#define RST_BUS_DBG 12 +#define RST_BUS_PWM 13 +#define RST_BUS_DRAM 14 +#define RST_BUS_MMC0 15 +#define RST_BUS_MMC1 16 +#define RST_BUS_MMC2 17 +#define RST_BUS_UART0 18 +#define RST_BUS_UART1 19 +#define RST_BUS_UART2 20 +#define RST_BUS_UART3 21 +#define RST_BUS_UART4 22 +#define RST_BUS_UART5 23 +#define RST_BUS_I2C0 24 +#define RST_BUS_I2C1 25 +#define RST_BUS_I2C2 26 +#define RST_BUS_I2C3 27 +#define RST_BUS_SPI0 28 +#define RST_BUS_SPI1 29 +#define RST_BUS_EMAC 30 +#define RST_BUS_IR_TX 31 +#define RST_BUS_GPADC 32 +#define RST_BUS_THS 33 +#define RST_BUS_I2S0 34 +#define RST_BUS_I2S1 35 +#define RST_BUS_I2S2 36 +#define RST_BUS_SPDIF 37 +#define RST_BUS_DMIC 38 +#define RST_BUS_AUDIO 39 +#define RST_USB_PHY0 40 +#define RST_USB_PHY1 41 +#define RST_BUS_OHCI0 42 +#define RST_BUS_OHCI1 43 +#define RST_BUS_EHCI0 44 +#define RST_BUS_EHCI1 45 +#define RST_BUS_OTG 46 +#define RST_BUS_LRADC 47 +#define RST_BUS_DPSS_TOP 48 +#define RST_BUS_HDMI_SUB 49 +#define RST_BUS_HDMI_MAIN 50 +#define RST_BUS_MIPI_DSI 51 +#define RST_BUS_TCON_LCD0 52 +#define RST_BUS_TCON_TV 53 +#define RST_BUS_LVDS0 54 +#define RST_BUS_TVE 55 +#define RST_BUS_TVE_TOP 56 +#define RST_BUS_TVD 57 +#define RST_BUS_TVD_TOP 58 +#define RST_BUS_LEDC 59 +#define RST_BUS_CSI 60 +#define RST_BUS_TPADC 61 +#define RST_DSP 62 +#define RST_BUS_DSP_CFG 63 +#define RST_BUS_DSP_DBG 64 +#define RST_BUS_RISCV_CFG 65 +#define RST_BUS_CAN0 66 +#define RST_BUS_CAN1 67 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun20i-d1-r-ccu.h b/include/dt-bindings/reset/sun20i-d1-r-ccu.h new file mode 100644 index 00000000000..e20babc990a --- /dev/null +++ b/include/dt-bindings/reset/sun20i-d1-r-ccu.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (C) 2021 Samuel Holland + */ + +#ifndef _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ +#define _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ + +#define RST_BUS_R_TIMER 0 +#define RST_BUS_R_TWD 1 +#define RST_BUS_R_PPU 2 +#define RST_BUS_R_IR_RX 3 +#define RST_BUS_R_RTC 4 +#define RST_BUS_R_CPUCFG 5 + +#endif /* _DT_BINDINGS_RST_SUN20I_D1_R_CCU_H_ */ -- cgit v1.3.1 From 207ed0a3ddcb23fe0a5e8f83b36e6f039270bc46 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 6 Sep 2022 10:36:38 +0100 Subject: pinctrl: sunxi: remove GPIO_EXTRA_HEADER U-Boot's generic GPIO_EXTRA_HEADER is a convenience symbol to allow code to more easily include platform specific GPIO headers. This should not be needed in a DM world anymore, since the generic GPIO framework handles that nicely. For Allwinner boards we still need to deal with non-DM GPIO in the SPL, but this should become the exception, not the rule. Make this more obvious by removing the definition of GPIO_EXTRA_HEADER, and just force every legacy user of platform specific GPIO to include the new sunxi_gpio.h header explicitly. Everyone doing so should feel ashamed and should find a way to avoid it from now on. Signed-off-by: Andre Przywara Tested-by: Samuel Holland --- arch/arm/Kconfig | 1 - arch/arm/include/asm/arch-sunxi/gpio.h | 196 --------------------------------- arch/arm/mach-sunxi/board.c | 1 + arch/arm/mach-sunxi/dram_suniv.c | 2 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 1 + board/sunxi/board.c | 1 + board/sunxi/chip.c | 2 +- drivers/gpio/axp_gpio.c | 1 + drivers/gpio/sunxi_gpio.c | 1 + drivers/i2c/sun6i_p2wi.c | 2 +- drivers/i2c/sun8i_rsb.c | 2 +- drivers/mmc/sunxi_mmc.c | 1 + drivers/pinctrl/sunxi/pinctrl-sunxi.c | 1 + drivers/video/hitachi_tx18d42vm_lcd.c | 1 + drivers/video/ssd2828.c | 1 - drivers/video/sunxi/sunxi_display.c | 1 + drivers/video/sunxi/sunxi_lcd.c | 1 + include/sunxi_gpio.h | 196 +++++++++++++++++++++++++++++++++ 18 files changed, 210 insertions(+), 202 deletions(-) delete mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h create mode 100644 include/sunxi_gpio.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index dcccbfea42a..d812685c984 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1135,7 +1135,6 @@ config ARCH_SUNXI select DM_MMC if MMC select DM_SCSI if SCSI select DM_SERIAL - select GPIO_EXTRA_HEADER select OF_BOARD_SETUP select OF_CONTROL select OF_SEPARATE diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h deleted file mode 100644 index e0fb5b5da63..00000000000 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * Definitions that are shared between the Allwinner pinctrl and GPIO drivers, - * also used by some non-DM SPL code directly. - */ - -#ifndef _SUNXI_GPIO_H -#define _SUNXI_GPIO_H - -#include -#include - -/* - * sunxi has 9 banks of gpio, they are: - * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 - * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 - * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 - */ - -#define SUNXI_GPIO_A 0 -#define SUNXI_GPIO_B 1 -#define SUNXI_GPIO_C 2 -#define SUNXI_GPIO_D 3 -#define SUNXI_GPIO_E 4 -#define SUNXI_GPIO_F 5 -#define SUNXI_GPIO_G 6 -#define SUNXI_GPIO_H 7 -#define SUNXI_GPIO_I 8 - -/* - * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) - * at a different register offset. - * - * sun6i has 2 banks: - * PL0 - PL8 | PM0 - PM7 - * - * sun8i has 1 bank: - * PL0 - PL11 - * - * sun9i has 3 banks: - * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 - */ -#define SUNXI_GPIO_L 11 -#define SUNXI_GPIO_M 12 -#define SUNXI_GPIO_N 13 - -#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 -#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 - -#define SUNXI_GPIOS_PER_BANK 32 -#define SUNXI_PINCTRL_BANK_SIZE 0x24 - -#define SUNXI_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) - -enum sunxi_gpio_number { - SUNXI_GPIO_A_START = 0, - SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), - SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), - SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), - SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), - SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), - SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), - SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), - SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), - SUNXI_GPIO_L_START = 352, - SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), - SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), - SUNXI_GPIO_AXP0_START = 1024, -}; - -/* SUNXI GPIO number definitions */ -#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) -#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) -#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) -#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) -#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) -#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) -#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) -#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) -#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) -#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) -#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) -#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) - -#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) - -/* GPIO pin function config */ -#define SUNXI_GPIO_INPUT 0 -#define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPIO_DISABLE 7 - -#define SUN8I_H3_GPA_UART0 2 -#define SUN8I_H3_GPA_UART2 2 - -#define SUN4I_GPB_PWM 2 -#define SUN4I_GPB_TWI0 2 -#define SUN4I_GPB_TWI1 2 -#define SUN5I_GPB_TWI1 2 -#define SUN8I_V3S_GPB_TWI0 2 -#define SUN4I_GPB_UART0 2 -#define SUN5I_GPB_UART0 2 -#define SUN8I_GPB_UART2 2 -#define SUN8I_A33_GPB_UART0 3 -#define SUN8I_A83T_GPB_UART0 2 -#define SUN8I_V3S_GPB_UART0 3 -#define SUN50I_GPB_UART0 4 - -#define SUNXI_GPC_NAND 2 -#define SUNXI_GPC_SPI0 3 -#define SUNXI_GPC_SDC2 3 -#define SUN6I_GPC_SDC3 4 -#define SUN50I_GPC_SPI0 4 -#define SUNIV_GPC_SPI0 2 - -#define SUNXI_GPD_LCD0 2 -#define SUNXI_GPD_LVDS0 3 - -#define SUNIV_GPE_UART0 5 - -#define SUNXI_GPF_SDC0 2 -#define SUNXI_GPF_UART0 4 -#define SUN8I_GPF_UART0 3 - -#define SUN4I_GPG_SDC1 4 -#define SUN5I_GPG_SDC1 2 -#define SUN6I_GPG_SDC1 2 -#define SUN8I_GPG_SDC1 2 -#define SUN8I_GPG_UART1 2 -#define SUN5I_GPG_UART1 4 - -#define SUN6I_GPH_PWM 2 -#define SUN8I_GPH_PWM 2 -#define SUN4I_GPH_SDC1 5 -#define SUN6I_GPH_TWI0 2 -#define SUN8I_GPH_TWI0 2 -#define SUN50I_GPH_TWI0 2 -#define SUN6I_GPH_TWI1 2 -#define SUN8I_GPH_TWI1 2 -#define SUN50I_GPH_TWI1 2 -#define SUN6I_GPH_UART0 2 -#define SUN9I_GPH_UART0 2 -#define SUN50I_H6_GPH_UART0 2 -#define SUN50I_H616_GPH_UART0 2 - -#define SUNXI_GPI_SDC3 2 - -#define SUN6I_GPL0_R_P2WI_SCK 3 -#define SUN6I_GPL1_R_P2WI_SDA 3 - -#define SUN8I_GPL_R_RSB 2 -#define SUN8I_H3_GPL_R_TWI 2 -#define SUN8I_A23_GPL_R_TWI 3 -#define SUN8I_GPL_R_UART 2 -#define SUN50I_GPL_R_TWI 2 -#define SUN50I_H616_GPL_R_TWI 3 - -#define SUN9I_GPN_R_RSB 3 - -/* GPIO pin pull-up/down config */ -#define SUNXI_GPIO_PULL_DISABLE 0 -#define SUNXI_GPIO_PULL_UP 1 -#define SUNXI_GPIO_PULL_DOWN 2 - -/* Virtual AXP0 GPIOs */ -#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 -#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 - -struct sunxi_gpio_plat { - void *regs; - char bank_name[3]; -}; - -/* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */ -void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); -void sunxi_gpio_set_cfgpin(u32 pin, u32 val); -int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); -int sunxi_gpio_get_cfgpin(u32 pin); -void sunxi_gpio_set_drv(u32 pin, u32 val); -void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); -void sunxi_gpio_set_pull(u32 pin, u32 val); -void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); -int sunxi_name_to_gpio(const char *name); - -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO -int axp_gpio_init(void); -#else -static inline int axp_gpio_init(void) { return 0; } -#endif - -#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 78597ad932c..4a1a0eacdba 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 3aa3ce76272..9e583e18553 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -13,10 +13,10 @@ #include #include #include -#include #include #include #include +#include #define SDR_T_CAS (0x2) #define SDR_T_RAS (0x8) diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c b/arch/arm/mach-sunxi/spl_spi_sunxi.c index 81159cfee61..c2410dd7bb1 100644 --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c @@ -13,6 +13,7 @@ #include #include #include +#include #ifdef CONFIG_SPL_OS_BOOT #error CONFIG_SPL_OS_BOOT is not supported yet diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 5cfb33468e5..7a1c708b9f2 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -38,6 +38,7 @@ #include #endif #include +#include #include #include #include diff --git a/board/sunxi/chip.c b/board/sunxi/chip.c index cde04bebe96..eeee6319e79 100644 --- a/board/sunxi/chip.c +++ b/board/sunxi/chip.c @@ -12,7 +12,7 @@ #include #include -#include +#include #include diff --git a/drivers/gpio/axp_gpio.c b/drivers/gpio/axp_gpio.c index 49672193ffc..af6631697f5 100644 --- a/drivers/gpio/axp_gpio.c +++ b/drivers/gpio/axp_gpio.c @@ -14,6 +14,7 @@ #include #include #include +#include static int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val); diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index d7f6a266e53..e335496581f 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -17,6 +17,7 @@ #include #include #include +#include /* * ======================================================================= diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index d221323295d..b8e07a533ca 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -20,10 +20,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include diff --git a/drivers/i2c/sun8i_rsb.c b/drivers/i2c/sun8i_rsb.c index 47fa05b6d1c..f36f2c7afac 100644 --- a/drivers/i2c/sun8i_rsb.c +++ b/drivers/i2c/sun8i_rsb.c @@ -14,10 +14,10 @@ #include #include #include +#include #include #include #include -#include #include #include diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 23bc7da917a..03e33753fcf 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -27,6 +27,7 @@ #include #include #include +#include #ifndef CCM_MMC_CTRL_MODE_SEL_NEW #define CCM_MMC_CTRL_MODE_SEL_NEW 0 diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 946447e9136..fc80fe50b14 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include diff --git a/drivers/video/hitachi_tx18d42vm_lcd.c b/drivers/video/hitachi_tx18d42vm_lcd.c index 87c4d27438a..95984fe3d3d 100644 --- a/drivers/video/hitachi_tx18d42vm_lcd.c +++ b/drivers/video/hitachi_tx18d42vm_lcd.c @@ -10,6 +10,7 @@ #include #include +#include #include /* diff --git a/drivers/video/ssd2828.c b/drivers/video/ssd2828.c index 4cdcbe7755a..948f5e74d0f 100644 --- a/drivers/video/ssd2828.c +++ b/drivers/video/ssd2828.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include diff --git a/drivers/video/sunxi/sunxi_display.c b/drivers/video/sunxi/sunxi_display.c index 9110a484821..8da44a1bb6d 100644 --- a/drivers/video/sunxi/sunxi_display.c +++ b/drivers/video/sunxi/sunxi_display.c @@ -31,6 +31,7 @@ #include #include #include +#include #include "../videomodes.h" #include "../anx9804.h" #include "../hitachi_tx18d42vm_lcd.h" diff --git a/drivers/video/sunxi/sunxi_lcd.c b/drivers/video/sunxi/sunxi_lcd.c index 8b9c3b2bfa9..7a01cc343ca 100644 --- a/drivers/video/sunxi/sunxi_lcd.c +++ b/drivers/video/sunxi/sunxi_lcd.c @@ -17,6 +17,7 @@ #include #include #include +#include struct sunxi_lcd_priv { struct display_timing timing; diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h new file mode 100644 index 00000000000..e0fb5b5da63 --- /dev/null +++ b/include/sunxi_gpio.h @@ -0,0 +1,196 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. + * Tom Cubie + * + * Definitions that are shared between the Allwinner pinctrl and GPIO drivers, + * also used by some non-DM SPL code directly. + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +#include +#include + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 + +/* + * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) + * at a different register offset. + * + * sun6i has 2 banks: + * PL0 - PL8 | PM0 - PM7 + * + * sun8i has 1 bank: + * PL0 - PL11 + * + * sun9i has 3 banks: + * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 + */ +#define SUNXI_GPIO_L 11 +#define SUNXI_GPIO_M 12 +#define SUNXI_GPIO_N 13 + +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340 +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 + +#define SUNXI_GPIOS_PER_BANK 32 +#define SUNXI_PINCTRL_BANK_SIZE 0x24 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), + SUNXI_GPIO_L_START = 352, + SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), + SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), + SUNXI_GPIO_AXP0_START = 1024, +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) +#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) +#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) +#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) + +#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 +#define SUNXI_GPIO_DISABLE 7 + +#define SUN8I_H3_GPA_UART0 2 +#define SUN8I_H3_GPA_UART2 2 + +#define SUN4I_GPB_PWM 2 +#define SUN4I_GPB_TWI0 2 +#define SUN4I_GPB_TWI1 2 +#define SUN5I_GPB_TWI1 2 +#define SUN8I_V3S_GPB_TWI0 2 +#define SUN4I_GPB_UART0 2 +#define SUN5I_GPB_UART0 2 +#define SUN8I_GPB_UART2 2 +#define SUN8I_A33_GPB_UART0 3 +#define SUN8I_A83T_GPB_UART0 2 +#define SUN8I_V3S_GPB_UART0 3 +#define SUN50I_GPB_UART0 4 + +#define SUNXI_GPC_NAND 2 +#define SUNXI_GPC_SPI0 3 +#define SUNXI_GPC_SDC2 3 +#define SUN6I_GPC_SDC3 4 +#define SUN50I_GPC_SPI0 4 +#define SUNIV_GPC_SPI0 2 + +#define SUNXI_GPD_LCD0 2 +#define SUNXI_GPD_LVDS0 3 + +#define SUNIV_GPE_UART0 5 + +#define SUNXI_GPF_SDC0 2 +#define SUNXI_GPF_UART0 4 +#define SUN8I_GPF_UART0 3 + +#define SUN4I_GPG_SDC1 4 +#define SUN5I_GPG_SDC1 2 +#define SUN6I_GPG_SDC1 2 +#define SUN8I_GPG_SDC1 2 +#define SUN8I_GPG_UART1 2 +#define SUN5I_GPG_UART1 4 + +#define SUN6I_GPH_PWM 2 +#define SUN8I_GPH_PWM 2 +#define SUN4I_GPH_SDC1 5 +#define SUN6I_GPH_TWI0 2 +#define SUN8I_GPH_TWI0 2 +#define SUN50I_GPH_TWI0 2 +#define SUN6I_GPH_TWI1 2 +#define SUN8I_GPH_TWI1 2 +#define SUN50I_GPH_TWI1 2 +#define SUN6I_GPH_UART0 2 +#define SUN9I_GPH_UART0 2 +#define SUN50I_H6_GPH_UART0 2 +#define SUN50I_H616_GPH_UART0 2 + +#define SUNXI_GPI_SDC3 2 + +#define SUN6I_GPL0_R_P2WI_SCK 3 +#define SUN6I_GPL1_R_P2WI_SDA 3 + +#define SUN8I_GPL_R_RSB 2 +#define SUN8I_H3_GPL_R_TWI 2 +#define SUN8I_A23_GPL_R_TWI 3 +#define SUN8I_GPL_R_UART 2 +#define SUN50I_GPL_R_TWI 2 +#define SUN50I_H616_GPL_R_TWI 3 + +#define SUN9I_GPN_R_RSB 3 + +/* GPIO pin pull-up/down config */ +#define SUNXI_GPIO_PULL_DISABLE 0 +#define SUNXI_GPIO_PULL_UP 1 +#define SUNXI_GPIO_PULL_DOWN 2 + +/* Virtual AXP0 GPIOs */ +#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" +#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 +#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 + +struct sunxi_gpio_plat { + void *regs; + char bank_name[3]; +}; + +/* prototypes for the non-DM GPIO/pinctrl functions, used in the SPL */ +void sunxi_gpio_set_cfgbank(void *bank_base, int pin_offset, u32 val); +void sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgbank(void *bank_base, int pin_offset); +int sunxi_gpio_get_cfgpin(u32 pin); +void sunxi_gpio_set_drv(u32 pin, u32 val); +void sunxi_gpio_set_drv_bank(void *bank_base, u32 pin_offset, u32 val); +void sunxi_gpio_set_pull(u32 pin, u32 val); +void sunxi_gpio_set_pull_bank(void *bank_base, int pin_offset, u32 val); +int sunxi_name_to_gpio(const char *name); + +#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO +int axp_gpio_init(void); +#else +static inline int axp_gpio_init(void) { return 0; } +#endif + +#endif /* _SUNXI_GPIO_H */ -- cgit v1.3.1 From 1da48c99de18490a69c467df6c4a71701ac47fb1 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 6 Sep 2022 11:50:54 +0100 Subject: pinctrl: sunxi: move PIO_BASE into sunxi_gpio.h On the Allwinner platform we were describing a quite comprehensive memory map in a per-SoC header unser arch/arm. In the old days that was used by every driver, but nowadays it should only be needed by SPL drivers (not using the DT). Many addresses in there were never used, and some are not needed anymore. To avoid a dependency on CPU specific headers in an arch specific directory, move the definition of the pinctroller MMIO base address into the sunxi_gpio.h header, because the SPL routines for GPIO should be the only one needing this address. This is a first step towards getting rid of cpu_sun[x]i.h completely, and allows to remove the inclusion of that file from the sunxi_gpio.h header. Signed-off-by: Andre Przywara --- arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 2 -- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 2 -- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 2 -- include/sunxi_gpio.h | 12 +++++++++++- 4 files changed, 11 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index f7ecc790dbf..d6fe51f24bc 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -91,7 +91,6 @@ #define SUNXI_CCM_BASE 0x01c20000 #define SUNXI_INTC_BASE 0x01c20400 -#define SUNXI_PIO_BASE 0x01c20800 #define SUNXI_TIMER_BASE 0x01c20c00 #ifndef CONFIG_SUNXI_GEN_SUN6I #define SUNXI_PWM_BASE 0x01c20e00 @@ -210,7 +209,6 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_R_TWI_BASE 0x01f02400 #define SUNXI_R_UART_BASE 0x01f02800 -#define SUNXI_R_PIO_BASE 0x01f02c00 #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index d9cf8ae0428..9b6bf843601 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -22,7 +22,6 @@ #define SUNXI_SIDC_BASE 0x03006000 #define SUNXI_SID_BASE 0x03006200 #define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PIO_BASE 0x0300B000 #define SUNXI_PSI_BASE 0x0300C000 #define SUNXI_GIC400_BASE 0x03020000 @@ -68,7 +67,6 @@ #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 #define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 9c2d11b5901..20025be2319 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -81,7 +81,6 @@ /* APB0 Module */ #define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) #define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) -#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) #define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) #define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) @@ -102,7 +101,6 @@ /* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) #define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) -#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) /* Misc. */ diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index e0fb5b5da63..c1fdf7ea1d7 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -12,7 +12,17 @@ #define _SUNXI_GPIO_H #include -#include + +#if defined(CONFIG_MACH_SUN9I) +#define SUNXI_PIO_BASE 0x06000800 +#define SUNXI_R_PIO_BASE 0x08002c00 +#elif defined(CONFIG_SUN50I_GEN_H6) +#define SUNXI_PIO_BASE 0x0300b000 +#define SUNXI_R_PIO_BASE 0x07022000 +#else +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_R_PIO_BASE 0x01f02c00 +#endif /* * sunxi has 9 banks of gpio, they are: -- cgit v1.3.1 From 452369cd0c636123321d021298b4bc35a34f4941 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 6 Sep 2022 12:12:50 +0100 Subject: pinctrl: sunxi: add new D1 pinctrl support For the first time since at least the Allwinner A10 SoCs, the D1 (and related cores) use a new pincontroller MMIO register layout, so we cannot use our hardcoded, fixed offsets anymore. Ideally this would all be handled by devicetree and DM drivers, but for the DT-less SPL we still need the legacy interfaces. Add a new Kconfig symbol to differenciate between the two generations of pincontrollers, and just use that to just switch some basic symbols. The rest is already abstracted enough, so works out of the box. Signed-off-by: Andre Przywara Reviewed-by: Sam Edwards Tested-by: Sam Edwards Tested-by: Samuel Holland --- drivers/gpio/Kconfig | 7 +++++++ drivers/gpio/sunxi_gpio.c | 17 +++++++++++++++-- include/sunxi_gpio.h | 10 ++++++++-- 3 files changed, 30 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 74baa98d3c1..ba42b0768e1 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -372,6 +372,13 @@ config SUNXI_GPIO help Support the GPIO device in Allwinner SoCs. +config SUNXI_NEW_PINCTRL + bool + depends on SUNXI_GPIO + ---help--- + The Allwinner D1 and other new SoCs use a different register map + for the GPIO block, which we need to know about in the SPL. + config XILINX_GPIO bool "Xilinx GPIO driver" depends on DM_GPIO diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index e335496581f..e4463a223f7 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -40,10 +40,23 @@ #define GPIO_DAT_REG_OFFSET 0x10 #define GPIO_DRV_REG_OFFSET 0x14 -#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) -#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) + +/* Newer SoCs use a slightly different register layout */ +#ifdef CONFIG_SUNXI_NEW_PINCTRL +/* pin drive strength: 4 bits per pin */ +#define GPIO_DRV_INDEX(pin) ((pin) / 8) +#define GPIO_DRV_OFFSET(pin) (((pin) % 8) * 4) + +#define GPIO_PULL_REG_OFFSET 0x24 + +#else /* older generation pin controllers */ +/* pin drive strength: 2 bits per pin */ +#define GPIO_DRV_INDEX(pin) ((pin) / 16) +#define GPIO_DRV_OFFSET(pin) (((pin) % 16) * 2) #define GPIO_PULL_REG_OFFSET 0x1c +#endif + #define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) #define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index c1fdf7ea1d7..30d8879dbd3 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -62,7 +62,6 @@ #define SUN50I_H6_GPIO_POW_MOD_VAL 0x348 #define SUNXI_GPIOS_PER_BANK 32 -#define SUNXI_PINCTRL_BANK_SIZE 0x24 #define SUNXI_GPIO_NEXT(__gpio) \ ((__gpio##_START) + SUNXI_GPIOS_PER_BANK) @@ -102,7 +101,6 @@ enum sunxi_gpio_number { /* GPIO pin function config */ #define SUNXI_GPIO_INPUT 0 #define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPIO_DISABLE 7 #define SUN8I_H3_GPA_UART0 2 #define SUN8I_H3_GPA_UART2 2 @@ -171,6 +169,14 @@ enum sunxi_gpio_number { #define SUN9I_GPN_R_RSB 3 +#ifdef CONFIG_SUNXI_NEW_PINCTRL + #define SUNXI_PINCTRL_BANK_SIZE 0x30 + #define SUNXI_GPIO_DISABLE 0xf +#else + #define SUNXI_PINCTRL_BANK_SIZE 0x24 + #define SUNXI_GPIO_DISABLE 0x7 +#endif + /* GPIO pin pull-up/down config */ #define SUNXI_GPIO_PULL_DISABLE 0 #define SUNXI_GPIO_PULL_UP 1 -- cgit v1.3.1 From 4a9e89a3e390bbff31aec25f9ec6d32e29e355f5 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Wed, 5 Oct 2022 17:54:19 +0100 Subject: sunxi: introduce NCAT2 generation model Allwinner seems to typically stick to a common MMIO memory map for several SoCs, but from time to time does some breaking changes, which also introduce new generations of some peripherals. The last time this happened with the H6, which apart from re-organising the base addresses also changed the clock controller significantly. We added a CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those traits. Now the Allwinner D1 changes the memory map again, and also extends the pincontroller, among other peripherals. To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol, this name is reportedly used in the Allwinner BSP code, and prevents us from inventing our own name. Add this new symbol to some guards that were already checking for the H6 generation, since many features are shared between the two (like the renovated clock controller). This paves the way to introduce a first user of this generation. Signed-off-by: Andre Przywara Tested-by: Samuel Holland --- arch/arm/include/asm/arch-sunxi/clock.h | 2 +- arch/arm/include/asm/arch-sunxi/cpu.h | 2 ++ arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 43 +++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- arch/arm/include/asm/arch-sunxi/timer.h | 2 +- arch/arm/mach-sunxi/Kconfig | 12 ++++++- arch/arm/mach-sunxi/Makefile | 1 + arch/arm/mach-sunxi/board.c | 22 +++++++----- arch/arm/mach-sunxi/clock_sun50i_h6.c | 7 ++-- common/spl/Kconfig | 2 +- drivers/i2c/mvtwsi.c | 3 +- drivers/mmc/sunxi_mmc.c | 7 ++-- include/sunxi_gpio.h | 3 ++ 14 files changed, 90 insertions(+), 20 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h (limited to 'include') diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 2cfd5407423..3d34261b0e5 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -16,7 +16,7 @@ /* clock control module regs definition */ #if defined(CONFIG_MACH_SUN8I_A83T) #include -#elif defined(CONFIG_SUN50I_GEN_H6) +#elif defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) #include #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV) diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index b08f2023748..768c6572d6b 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -10,6 +10,8 @@ #include #elif defined(CONFIG_SUN50I_GEN_H6) #include +#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#include #else #include #endif diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h new file mode 100644 index 00000000000..ca92c39927d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2022 Arm Limited + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_SUNXI_NCAT2_H +#define _SUNXI_CPU_SUNXI_NCAT2_H + +#define SUNXI_CCM_BASE 0x02001000 +#define SUNXI_TIMER_BASE 0x02050000 + +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_UART1_BASE 0x02500400 +#define SUNXI_UART2_BASE 0x02500800 +#define SUNXI_UART3_BASE 0x02500C00 +#define SUNXI_TWI0_BASE 0x02502000 +#define SUNXI_TWI1_BASE 0x02502400 +#define SUNXI_TWI2_BASE 0x02502800 +#define SUNXI_TWI3_BASE 0x02502C00 + +#define SUNXI_SRAMC_BASE 0x03000000 +/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ +#define SUNXI_SIDC_BASE 0x03006000 +#define SUNXI_SID_BASE 0x03006200 +#define SUNXI_GIC400_BASE 0x03020000 + +#define SUNXI_MMC0_BASE 0x04020000 +#define SUNXI_MMC1_BASE 0x04021000 +#define SUNXI_MMC2_BASE 0x04022000 + +#define SUNXI_R_CPUCFG_BASE 0x07000400 +#define SUNXI_PRCM_BASE 0x07010000 + +#define SUNXI_CPUCFG_BASE 0x09010000 + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +void sunxi_reset(void); +int sunxi_get_sid(unsigned int *sid); +#endif + +#endif /* _SUNXI_CPU_SUNXI_NCAT2_H */ diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h index 5daacf10eb1..8ed3e0459c9 100644 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -45,7 +45,7 @@ struct sunxi_mmc { u32 chda; /* 0x90 */ u32 cbda; /* 0x94 */ u32 res2[26]; -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) u32 res3[17]; u32 samp_dl; u32 res4[46]; diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h index 5106076f5e9..c5418cfd28d 100644 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ b/arch/arm/include/asm/arch-sunxi/prcm.h @@ -9,7 +9,7 @@ #define _SUNXI_PRCM_H /* prcm regs definition */ -#if defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) #include #else #include diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h index bb5626d893b..e17db8588e2 100644 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -76,7 +76,7 @@ struct sunxi_timer_reg { struct sunxi_tgp tgp[4]; u8 res5[8]; u32 cpu_cfg; -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) u8 res3[16]; struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ #endif diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index d3ed62add99..6ba9ed2bb2a 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -121,7 +121,7 @@ config AXP_PMIC_BUS config SUNXI_SRAM_ADDRESS hex default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5 - default 0x20000 if SUN50I_GEN_H6 + default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x0 ---help--- Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, @@ -183,6 +183,14 @@ config SUN50I_GEN_H6 Select this for sunxi SoCs which have H6 like peripherals, clocks and memory map. +config SUNXI_GEN_NCAT2 + bool + select MMC_SUNXI_HAS_NEW_MODE + select SUPPORT_SPL + ---help--- + Select this for sunxi SoCs which have D1 like peripherals, clocks + and memory map. + config SUNXI_DRAM_DW bool ---help--- @@ -804,6 +812,7 @@ config VIDEO_SUNXI depends on !MACH_SUN9I depends on !MACH_SUN50I depends on !SUN50I_GEN_H6 + depends on !SUNXI_GEN_NCAT2 select VIDEO select DISPLAY imply VIDEO_DT_SIMPLEFB @@ -1017,6 +1026,7 @@ config SPL_STACK_R_ADDR default 0x2fe00000 if MACH_SUN9I default 0x4fe00000 if MACH_SUN50I default 0x4fe00000 if SUN50I_GEN_H6 + default 0x4fe00000 if SUNXI_GEN_NCAT2 config SPL_SPI_SUNXI bool "Support for SPI Flash on Allwinner SoCs in SPL" diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile index 671211e9322..1d4c70ec352 100644 --- a/arch/arm/mach-sunxi/Makefile +++ b/arch/arm/mach-sunxi/Makefile @@ -25,6 +25,7 @@ obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o endif obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o gtbus_sun9i.o obj-$(CONFIG_SUN50I_GEN_H6) += clock_sun50i_h6.o +obj-$(CONFIG_SUNXI_GEN_NCAT2) += clock_sun50i_h6.o ifndef CONFIG_ARM64 obj-y += timer.o endif diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index 4a1a0eacdba..d572314f0da 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -176,13 +176,19 @@ static int gpio_init(void) #error Unsupported console port number. Please fix pin mux settings in board.c #endif -#ifdef CONFIG_SUN50I_GEN_H6 - /* Update PIO power bias configuration by copy hardware detected value */ - val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); - writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); - val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); - writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); -#endif + /* + * Update PIO power bias configuration by copying the hardware + * detected value. + */ + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUN50I_GEN_NCAT2)) { + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + } + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) { + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL); + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL); + } return 0; } @@ -481,7 +487,7 @@ void reset_cpu(void) /* sun5i sometimes gets stuck without this */ writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) #if defined(CONFIG_MACH_SUN50I_H6) /* WDOG is broken for some H6 rev. use the R_WDOG instead */ static const struct sunxi_wdog *wdog = diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c b/arch/arm/mach-sunxi/clock_sun50i_h6.c index 7926394cf76..767a39fa2ab 100644 --- a/arch/arm/mach-sunxi/clock_sun50i_h6.c +++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c @@ -18,8 +18,11 @@ void clock_init_safe(void) setbits_le32(&prcm->res_cal_ctrl, 2); } - clrbits_le32(&prcm->res_cal_ctrl, 1); - setbits_le32(&prcm->res_cal_ctrl, 1); + if (IS_ENABLED(CONFIG_MACH_SUN50I_H616) || + IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { + clrbits_le32(&prcm->res_cal_ctrl, 1); + setbits_le32(&prcm->res_cal_ctrl, 1); + } if (IS_ENABLED(CONFIG_MACH_SUN50I_H6)) { /* set key field for ldo enable */ diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 6bc4066fad7..f7c8ba511b3 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -265,7 +265,7 @@ config SPL_TEXT_BASE default 0x402F0400 if AM33XX default 0x40301350 if OMAP54XX default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I - default 0x20060 if SUN50I_GEN_H6 + default 0x20060 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x00060 if ARCH_SUNXI default 0xfffc0000 if ARCH_ZYNQMP default 0x0 diff --git a/drivers/i2c/mvtwsi.c b/drivers/i2c/mvtwsi.c index 14cdb0f6635..c38330f758a 100644 --- a/drivers/i2c/mvtwsi.c +++ b/drivers/i2c/mvtwsi.c @@ -124,7 +124,8 @@ enum mvtwsi_ctrl_register_fields { * on other platforms, it is a normal r/w bit, which is cleared by writing 0. */ -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || \ + defined(CONFIG_SUNXI_GEN_NCAT2) #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000008 #else #define MVTWSI_CONTROL_CLEAR_IFLG 0x00000000 diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 03e33753fcf..519ef602145 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -57,6 +57,7 @@ static bool sunxi_mmc_can_calibrate(void) return IS_ENABLED(CONFIG_MACH_SUN50I) || IS_ENABLED(CONFIG_MACH_SUN50I_H5) || IS_ENABLED(CONFIG_SUN50I_GEN_H6) || + IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2) || IS_ENABLED(CONFIG_MACH_SUN8I_R40); } @@ -191,7 +192,7 @@ static int mmc_config_clock(struct sunxi_mmc_priv *priv, struct mmc *mmc) rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; writel(rval, &priv->reg->clkcr); -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) +#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_SUN50I_GEN_H6) || defined(CONFIG_SUNXI_GEN_NCAT2) /* A64 supports calibration of delays on MMC controller and we * have to set delay of zero before starting calibration. * Allwinner BSP driver sets a delay only in the case of @@ -544,7 +545,7 @@ struct mmc *sunxi_mmc_init(int sdc_no) /* config ahb clock */ debug("init mmc %d clock and io\n", sdc_no); -#if !defined(CONFIG_SUN50I_GEN_H6) +#if !defined(CONFIG_SUN50I_GEN_H6) && !defined(CONFIG_SUNXI_GEN_NCAT2) setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MMC(sdc_no)); #ifdef CONFIG_SUNXI_GEN_SUN6I @@ -619,7 +620,7 @@ static unsigned get_mclk_offset(void) if (IS_ENABLED(CONFIG_MACH_SUN9I_A80)) return 0x410; - if (IS_ENABLED(CONFIG_SUN50I_GEN_H6)) + if (IS_ENABLED(CONFIG_SUN50I_GEN_H6) || IS_ENABLED(CONFIG_SUNXI_GEN_NCAT2)) return 0x830; return 0x88; diff --git a/include/sunxi_gpio.h b/include/sunxi_gpio.h index 30d8879dbd3..db3742c0397 100644 --- a/include/sunxi_gpio.h +++ b/include/sunxi_gpio.h @@ -19,6 +19,9 @@ #elif defined(CONFIG_SUN50I_GEN_H6) #define SUNXI_PIO_BASE 0x0300b000 #define SUNXI_R_PIO_BASE 0x07022000 +#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#define SUNXI_PIO_BASE 0x02000000 +#define SUNXI_R_PIO_BASE 0x07022000 #else #define SUNXI_PIO_BASE 0x01c20800 #define SUNXI_R_PIO_BASE 0x01f02c00 -- cgit v1.3.1 From beeace9ba1689e6eaba8d286f885a5f0e973b26e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 3 Jul 2022 00:14:24 +0100 Subject: sunxi: refactor serial base addresses to avoid asm/arch/cpu.h At the moment we have each SoC's memory map defined in its own cpu.h, which is included in include/configs/sunxi_common.h. This will be a problem with the introduction of Allwinner RISC-V support. Remove the inclusion of that header file from the common config header, instead move the required serial base addresses (for the SPL) into a separate header file. Then include the original cpu.h file only where we really need it, which is only under arch/arm now. This disentangles the architecture specific header files from the generic code. Signed-off-by: Andre Przywara --- arch/arm/cpu/armv7/sunxi/sram.c | 1 + arch/arm/cpu/armv8/fel_utils.S | 1 + arch/arm/include/asm/arch-sunxi/boot0.h | 2 ++ arch/arm/include/asm/arch-sunxi/clock.h | 1 + arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 15 ----------- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 5 ---- arch/arm/include/asm/arch-sunxi/cpu_sun9i.h | 7 ----- arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 4 --- arch/arm/include/asm/arch-sunxi/serial.h | 32 +++++++++++++++++++++++ arch/arm/mach-sunxi/gtbus_sun9i.c | 1 + arch/arm/mach-sunxi/timer.c | 1 + include/configs/sunxi-common.h | 2 +- 12 files changed, 40 insertions(+), 32 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/serial.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/sunxi/sram.c b/arch/arm/cpu/armv7/sunxi/sram.c index 28564c2846a..28ff6a1b7c2 100644 --- a/arch/arm/cpu/armv7/sunxi/sram.c +++ b/arch/arm/cpu/armv7/sunxi/sram.c @@ -12,6 +12,7 @@ #include #include #include +#include void sunxi_sram_init(void) { diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S index 2fe38a1a047..939869b9ffa 100644 --- a/arch/arm/cpu/armv8/fel_utils.S +++ b/arch/arm/cpu/armv8/fel_utils.S @@ -10,6 +10,7 @@ #include #include #include +#include /* * We don't overwrite save_boot_params() here, to save the FEL state upon diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h index 30f5680757a..cad25c50bc6 100644 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ b/arch/arm/include/asm/arch-sunxi/boot0.h @@ -3,6 +3,8 @@ * Configuration settings for the Allwinner A64 (sun50i) CPU */ +#include + #if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) /* reserve space for BOOT0 header information */ b reset diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h index 3d34261b0e5..fcc8966cb0b 100644 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -9,6 +9,7 @@ #define _SUNXI_CLOCK_H #include +#include #define CLK_GATE_OPEN 0x1 #define CLK_GATE_CLOSE 0x0 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h index d6fe51f24bc..3daee2f574a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h @@ -128,20 +128,6 @@ defined(CONFIG_MACH_SUN50I) #define SUNXI_CPUCFG_BASE 0x01c25c00 #endif -#ifdef CONFIG_MACH_SUNIV -#define SUNXI_UART0_BASE 0x01c25000 -#define SUNXI_UART1_BASE 0x01c25400 -#define SUNXI_UART2_BASE 0x01c25800 -#else -#define SUNXI_UART0_BASE 0x01c28000 -#define SUNXI_UART1_BASE 0x01c28400 -#define SUNXI_UART2_BASE 0x01c28800 -#endif -#define SUNXI_UART3_BASE 0x01c28c00 -#define SUNXI_UART4_BASE 0x01c29000 -#define SUNXI_UART5_BASE 0x01c29400 -#define SUNXI_UART6_BASE 0x01c29800 -#define SUNXI_UART7_BASE 0x01c29c00 #define SUNXI_PS2_0_BASE 0x01c2a000 #define SUNXI_PS2_1_BASE 0x01c2a400 @@ -208,7 +194,6 @@ defined(CONFIG_MACH_SUN50I) #endif #define SUNXI_R_TWI_BASE 0x01f02400 -#define SUNXI_R_UART_BASE 0x01f02800 #define SUN6I_P2WI_BASE 0x01f03400 #define SUNXI_RSB_BASE 0x01f03400 diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 9b6bf843601..15ee092d358 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -42,10 +42,6 @@ #define SUNXI_DRAM_PHY0_BASE 0x04800000 #endif -#define SUNXI_UART0_BASE 0x05000000 -#define SUNXI_UART1_BASE 0x05000400 -#define SUNXI_UART2_BASE 0x05000800 -#define SUNXI_UART3_BASE 0x05000C00 #define SUNXI_TWI0_BASE 0x05002000 #define SUNXI_TWI1_BASE 0x05002400 #define SUNXI_TWI2_BASE 0x05002800 @@ -67,7 +63,6 @@ #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 #define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h index 20025be2319..2bf2675d5c1 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h @@ -86,12 +86,6 @@ #define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) /* APB1 Module */ -#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) -#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) -#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) -#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) -#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) -#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) #define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) #define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) #define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) @@ -100,7 +94,6 @@ /* RCPUS Module */ #define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) -#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) #define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) /* Misc. */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h index ca92c39927d..908a582ae0f 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h @@ -10,10 +10,6 @@ #define SUNXI_CCM_BASE 0x02001000 #define SUNXI_TIMER_BASE 0x02050000 -#define SUNXI_UART0_BASE 0x02500000 -#define SUNXI_UART1_BASE 0x02500400 -#define SUNXI_UART2_BASE 0x02500800 -#define SUNXI_UART3_BASE 0x02500C00 #define SUNXI_TWI0_BASE 0x02502000 #define SUNXI_TWI1_BASE 0x02502400 #define SUNXI_TWI2_BASE 0x02502800 diff --git a/arch/arm/include/asm/arch-sunxi/serial.h b/arch/arm/include/asm/arch-sunxi/serial.h new file mode 100644 index 00000000000..9386287b65e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/serial.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * hardcoded UART base addresses for early SPL use + * + * Copyright (c) 2022 Arm Ltd. + */ + +#ifndef SUNXI_SERIAL_MEMMAP_H +#define SUNXI_SERIAL_MEMMAP_H + +#if defined(CONFIG_MACH_SUN9I) +#define SUNXI_UART0_BASE 0x07000000 +#define SUNXI_R_UART_BASE 0x08002800 +#elif defined(CONFIG_SUN50I_GEN_H6) +#define SUNXI_UART0_BASE 0x05000000 +#define SUNXI_R_UART_BASE 0x07080000 +#elif defined(CONFIG_MACH_SUNIV) +#define SUNXI_UART0_BASE 0x01c25000 +#define SUNXI_R_UART_BASE 0 +#elif defined(CONFIG_SUNXI_GEN_NCAT2) +#define SUNXI_UART0_BASE 0x02500000 +#define SUNXI_R_UART_BASE 0 // 0x07080000 (?> +#else +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_R_UART_BASE 0x01f02800 +#endif + +#define SUNXI_UART1_BASE (SUNXI_UART0_BASE + 0x400) +#define SUNXI_UART2_BASE (SUNXI_UART0_BASE + 0x800) +#define SUNXI_UART3_BASE (SUNXI_UART0_BASE + 0xc00) + +#endif /* SUNXI_SERIAL_MEMMAP_H */ diff --git a/arch/arm/mach-sunxi/gtbus_sun9i.c b/arch/arm/mach-sunxi/gtbus_sun9i.c index cf011c4cfa7..5624621b500 100644 --- a/arch/arm/mach-sunxi/gtbus_sun9i.c +++ b/arch/arm/mach-sunxi/gtbus_sun9i.c @@ -8,6 +8,7 @@ #include #include +#include #include #include diff --git a/arch/arm/mach-sunxi/timer.c b/arch/arm/mach-sunxi/timer.c index fc9d419a25e..9a6f6c06d8c 100644 --- a/arch/arm/mach-sunxi/timer.c +++ b/arch/arm/mach-sunxi/timer.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index d2d70f0fc23..b8ca77d031d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -12,7 +12,6 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H -#include #include /* Serial & console */ @@ -24,6 +23,7 @@ #define CFG_SYS_NS16550_CLK 24000000 #endif #if !CONFIG_IS_ENABLED(DM_SERIAL) +#include # define CFG_SYS_NS16550_COM1 SUNXI_UART0_BASE # define CFG_SYS_NS16550_COM2 SUNXI_UART1_BASE # define CFG_SYS_NS16550_COM3 SUNXI_UART2_BASE -- cgit v1.3.1