From a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Sat, 3 Aug 2024 10:43:23 +0200 Subject: clk: mediatek: mt7622: add missing clock MUX1_SEL Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to match the upstream clk ID order in preparation for OF_UPSTREAM. Signed-off-by: Christian Marangi --- include/dt-bindings/clock/mt7622-clk.h | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 569bfce0d05..0820fab0a22 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -120,12 +120,13 @@ /* INFRACFG */ -#define CLK_INFRA_DBGCLK_PD 0 -#define CLK_INFRA_AUDIO_PD 1 -#define CLK_INFRA_IRRX_PD 2 -#define CLK_INFRA_APXGPT_PD 3 -#define CLK_INFRA_PMIC_PD 4 -#define CLK_INFRA_TRNG 5 +#define CLK_INFRA_MUX1_SEL 0 +#define CLK_INFRA_DBGCLK_PD 1 +#define CLK_INFRA_AUDIO_PD 2 +#define CLK_INFRA_IRRX_PD 3 +#define CLK_INFRA_APXGPT_PD 4 +#define CLK_INFRA_PMIC_PD 5 +#define CLK_INFRA_TRNG 6 /* PERICFG */ -- cgit v1.3.1