From 8741c490f9028db16634031fdf86ef3866fc3fc5 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Mon, 9 Nov 2015 10:39:44 +0100 Subject: ARM: zynq: Choose boot image based on OF_SEPARATE macro OF_CONTROL is enabled by default for all Zynq boards. The difference between two boot images is done by OF_SEPARATE or OF_EMBED macros. Signed-off-by: Michal Simek Reviewed-by: Tom Rini --- include/configs/zynq-common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index 99a3d021ad5..f33a3bcc68a 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -331,7 +331,7 @@ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_FAT_SUPPORT -#ifdef CONFIG_OF_CONTROL +#ifdef CONFIG_OF_SEPARATE # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" #else # define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -- cgit v1.3.1 From 721aed79126ba954028137eabe71678523a8b157 Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Fri, 25 Sep 2015 23:46:08 -0700 Subject: net: phy: Add support for Texas Instruments DP83867 Code is taken from Linux kernel driver (v4.2). Signed-off-by: Edgar E. Iglesias Signed-off-by: Michal Simek Reviewed-by: Tom Rini Acked-by: Joe Hershberger --- drivers/net/phy/Makefile | 1 + drivers/net/phy/phy.c | 3 + drivers/net/phy/ti.c | 200 +++++++++++++++++++++++++++++++++++++++++++++++ include/phy.h | 1 + 4 files changed, 205 insertions(+) create mode 100644 drivers/net/phy/ti.c (limited to 'include') diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index d096db87a27..9e4d4927e67 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -24,4 +24,5 @@ obj-$(CONFIG_PHY_NATSEMI) += natsemi.o obj-$(CONFIG_PHY_REALTEK) += realtek.o obj-$(CONFIG_PHY_SMSC) += smsc.o obj-$(CONFIG_PHY_TERANETICS) += teranetics.o +obj-$(CONFIG_PHY_TI) += ti.o obj-$(CONFIG_PHY_VITESSE) += vitesse.o diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index d7364ffc34f..5633ec2402b 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -484,6 +484,9 @@ int phy_init(void) #ifdef CONFIG_PHY_TERANETICS phy_teranetics_init(); #endif +#ifdef CONFIG_PHY_TI + phy_ti_init(); +#endif #ifdef CONFIG_PHY_VITESSE phy_vitesse_init(); #endif diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c new file mode 100644 index 00000000000..541a57f9802 --- /dev/null +++ b/drivers/net/phy/ti.c @@ -0,0 +1,200 @@ +/* + * TI PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ +#include +#include + +/* TI DP83867 */ +#define DP83867_DEVADDR 0x1f + +#define MII_DP83867_PHYCTRL 0x10 +#define MII_DP83867_MICR 0x12 +#define DP83867_CTRL 0x1f + +/* Extended Registers */ +#define DP83867_RGMIICTL 0x0032 +#define DP83867_RGMIIDCTL 0x0086 + +#define DP83867_SW_RESET BIT(15) +#define DP83867_SW_RESTART BIT(14) + +/* MICR Interrupt bits */ +#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15) +#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14) +#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13) +#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12) +#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11) +#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10) +#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8) +#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4) +#define MII_DP83867_MICR_WOL_INT_EN BIT(3) +#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2) +#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1) +#define MII_DP83867_MICR_JABBER_INT_EN BIT(0) + +/* RGMIICTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1) +#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0) + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 + +/* RGMIIDCTL bits */ +#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 + +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ + +/* MMD Access Control register fields */ +#define MII_MMD_CTRL_DEVAD_MASK 0x1f /* Mask MMD DEVAD*/ +#define MII_MMD_CTRL_ADDR 0x0000 /* Address */ +#define MII_MMD_CTRL_NOINCR 0x4000 /* no post increment */ +#define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ +#define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ + +/** + * phy_read_mmd_indirect - reads data from the MMD registers + * @phydev: The PHY device bus + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * + * Description: it reads data from the MMD registers (clause 22 to access to + * clause 45) of the specified phy address. + * To read these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Read reg 14 // Read MMD data + */ +int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr) +{ + int value = -1; + + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Read the content of the MMD's selected register */ + value = phy_read(phydev, addr, MII_MMD_DATA); + return value; +} + +/** + * phy_write_mmd_indirect - writes data to the MMD registers + * @phydev: The PHY device + * @prtad: MMD Address + * @devad: MMD DEVAD + * @addr: PHY address on the MII bus + * @data: data to write in the MMD register + * + * Description: Write data from the MMD registers of the specified + * phy address. + * To write these registers we have: + * 1) Write reg 13 // DEVAD + * 2) Write reg 14 // MMD Address + * 3) Write reg 13 // MMD Data Command for MMD DEVAD + * 3) Write reg 14 // Write MMD data + */ +void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, + int devad, int addr, u32 data) +{ + /* Write the desired MMD Devad */ + phy_write(phydev, addr, MII_MMD_CTRL, devad); + + /* Write the desired MMD register address */ + phy_write(phydev, addr, MII_MMD_DATA, prtad); + + /* Select the Function : DATA with no post increment */ + phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); + + /* Write the data into MMD's selected register */ + phy_write(phydev, addr, MII_MMD_DATA, data); +} + +/** + * phy_interface_is_rgmii - Convenience function for testing if a PHY interface + * is RGMII (all variants) + * @phydev: the phy_device struct + */ +static inline bool phy_interface_is_rgmii(struct phy_device *phydev) +{ + return phydev->interface >= PHY_INTERFACE_MODE_RGMII && + phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; +} + +/* User setting - can be taken from DTS */ +#define RX_ID_DELAY 8 +#define TX_ID_DELAY 0xa +#define FIFO_DEPTH 1 + +static int dp83867_config(struct phy_device *phydev) +{ + unsigned int val, delay; + int ret; + + /* Restart the PHY. */ + val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); + phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, + val | DP83867_SW_RESTART); + + if (phy_interface_is_rgmii(phydev)) { + ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, + (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + if (ret) + return ret; + } + + if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && + (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) { + val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + val |= (DP83867_RGMII_TX_CLK_DELAY_EN | + DP83867_RGMII_RX_CLK_DELAY_EN); + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + val |= DP83867_RGMII_TX_CLK_DELAY_EN; + + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + val |= DP83867_RGMII_RX_CLK_DELAY_EN; + + phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, + DP83867_DEVADDR, phydev->addr, val); + + delay = (RX_ID_DELAY | + (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + + phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, + DP83867_DEVADDR, phydev->addr, delay); + } + + genphy_config_aneg(phydev); + return 0; +} + +static struct phy_driver DP83867_driver = { + .name = "TI DP83867", + .uid = 0x2000a231, + .mask = 0xfffffff0, + .features = PHY_GBIT_FEATURES, + .config = &dp83867_config, + .startup = &genphy_startup, + .shutdown = &genphy_shutdown, +}; + +int phy_ti_init(void) +{ + phy_register(&DP83867_driver); + return 0; +} diff --git a/include/phy.h b/include/phy.h index 3f826b66f71..66cf61bdfb9 100644 --- a/include/phy.h +++ b/include/phy.h @@ -251,6 +251,7 @@ int phy_natsemi_init(void); int phy_realtek_init(void); int phy_smsc_init(void); int phy_teranetics_init(void); +int phy_ti_init(void); int phy_vitesse_init(void); int board_phy_config(struct phy_device *phydev); -- cgit v1.3.1 From bf146325a3a802f5f2e6e17123080164109c6406 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 10 Nov 2015 10:48:05 +0100 Subject: ARM64: zynqmp: Enable TI phy by default Enable TI phy for Xilinx ZynqMP platform. Signed-off-by: Michal Simek --- include/configs/xilinx_zynqmp.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 36c11009fc3..574f788500b 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -182,6 +182,7 @@ # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN # define CONFIG_PHYLIB # define CONFIG_PHY_MARVELL +# define CONFIG_PHY_TI #endif /* I2C */ -- cgit v1.3.1 From 66eef1e780caf0bb3ecadf78582a29031c6279ce Mon Sep 17 00:00:00 2001 From: Nathan Rossi Date: Tue, 17 Nov 2015 22:56:56 +1000 Subject: tools: zynqimage: Add Xilinx Zynq boot header generation to mkimage As with other platforms vendors love to create their own boot header formats. Xilinx is no different and for the Zynq platform/SoC there exists the "boot.bin" which is read by the platforms bootrom. This format is described to a useful extent within the Xilinx Zynq TRM. This implementation adds support for the 'zynqimage' to mkimage. The implementation only considers the most common boot header which is un-encrypted and packed directly after the boot header itself (no XIP, etc.). However this implementation does take into consideration the other fields of the header for image dumping use cases (vector table and register initialization). Signed-off-by: Nathan Rossi Cc: Michal Simek Cc: Tom Rini Reviewed-by: Tom Rini Signed-off-by: Michal Simek --- common/image.c | 1 + include/image.h | 3 +- tools/Makefile | 1 + tools/zynqimage.c | 257 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 261 insertions(+), 1 deletion(-) create mode 100644 tools/zynqimage.c (limited to 'include') diff --git a/common/image.c b/common/image.c index 85c4f39cdf5..c36927fca8e 100644 --- a/common/image.c +++ b/common/image.c @@ -158,6 +158,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_RKIMAGE, "rkimage", "Rockchip Boot Image" }, { IH_TYPE_RKSD, "rksd", "Rockchip SD Boot Image" }, { IH_TYPE_RKSPI, "rkspi", "Rockchip SPI Boot Image" }, + { IH_TYPE_ZYNQIMAGE, "zynqimage", "Xilinx Zynq Boot Image" }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 08ae24a86b8..299d6d2a13d 100644 --- a/include/image.h +++ b/include/image.h @@ -248,8 +248,9 @@ struct lmb; #define IH_TYPE_RKIMAGE 23 /* Rockchip Boot Image */ #define IH_TYPE_RKSD 24 /* Rockchip SD card */ #define IH_TYPE_RKSPI 25 /* Rockchip SPI image */ +#define IH_TYPE_ZYNQIMAGE 26 /* Xilinx Zynq Boot Image */ -#define IH_TYPE_COUNT 26 /* Number of image types */ +#define IH_TYPE_COUNT 27 /* Number of image types */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 9082bda219f..9cfd80b6709 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -98,6 +98,7 @@ dumpimage-mkimage-objs := aisimage.o \ lib/sha256.o \ common/hash.o \ ublimage.o \ + zynqimage.o \ $(LIBFDT_OBJS) \ $(RSA_OBJS-y) diff --git a/tools/zynqimage.c b/tools/zynqimage.c new file mode 100644 index 00000000000..25f558d24c7 --- /dev/null +++ b/tools/zynqimage.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2015 Nathan Rossi + * + * SPDX-License-Identifier: GPL-2.0+ + * + * The following Boot Header format/structures and values are defined in the + * following documents: + * * Xilinx Zynq-7000 Technical Reference Manual (Section 6.3) + * * Xilinx Zynq-7000 Software Developers Guide (Appendix A.7 and A.8) + * + * Expected Header Size = 0x8C0 + * Forced as 'little' endian, 32-bit words + * + * 0x 0 - Interrupt Table (8 words) + * ... (Default value = 0xeafffffe) + * 0x 1f + * 0x 20 - Width Detection + * * DEFAULT_WIDTHDETECTION 0xaa995566 + * 0x 24 - Image Identifier + * * DEFAULT_IMAGEIDENTIFIER 0x584c4e58 + * 0x 28 - Encryption + * * 0x00000000 - None + * * 0xa5c3c5a3 - eFuse + * * 0x3a5c3c5a - bbRam + * 0x 2C - User Field + * 0x 30 - Image Offset + * 0x 34 - Image Size + * 0x 38 - Reserved (0x00000000) (according to spec) + * * FSBL defines this field for Image Destination Address. + * 0x 3C - Image Load + * 0x 40 - Image Stored Size + * 0x 44 - Reserved (0x00000000) (according to spec) + * * FSBL defines this field for QSPI configuration Data. + * 0x 48 - Checksum + * 0x 4c - Unused (21 words) + * ... + * 0x 9c + * 0x a0 - Register Initialization, 256 Address and Data word pairs + * * List is terminated with an address of 0xffffffff or + * ... * at the max number of entries + * 0x89c + * 0x8a0 - Unused (8 words) + * ... + * 0x8bf + * 0x8c0 - Data/Image starts here or above + */ + +#include "imagetool.h" +#include "mkimage.h" +#include + +#define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe)) +#define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) +#define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) +#define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) + +enum { + ENCRYPTION_EFUSE = 0xa5c3c5a3, + ENCRYPTION_BBRAM = 0x3a5c3c5a, + ENCRYPTION_NONE = 0x0, +}; + +struct zynq_reginit { + uint32_t address; + uint32_t data; +}; + +#define HEADER_INTERRUPT_VECTORS 8 +#define HEADER_REGINITS 256 + +struct zynq_header { + uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ + uint32_t width_detection; /* 0x20 */ + uint32_t image_identifier; /* 0x24 */ + uint32_t encryption; /* 0x28 */ + uint32_t user_field; /* 0x2c */ + uint32_t image_offset; /* 0x30 */ + uint32_t image_size; /* 0x34 */ + uint32_t __reserved1; /* 0x38 */ + uint32_t image_load; /* 0x3c */ + uint32_t image_stored_size; /* 0x40 */ + uint32_t __reserved2; /* 0x44 */ + uint32_t checksum; /* 0x48 */ + uint32_t __reserved3[21]; /* 0x4c */ + struct zynq_reginit register_init[HEADER_REGINITS]; /* 0xa0 */ + uint32_t __reserved4[8]; /* 0x8a0 */ +}; + +static struct zynq_header zynqimage_header; + +static uint32_t zynqimage_checksum(struct zynq_header *ptr) +{ + uint32_t checksum = 0; + + if (ptr == NULL) + return 0; + + checksum += le32_to_cpu(ptr->width_detection); + checksum += le32_to_cpu(ptr->image_identifier); + checksum += le32_to_cpu(ptr->encryption); + checksum += le32_to_cpu(ptr->user_field); + checksum += le32_to_cpu(ptr->image_offset); + checksum += le32_to_cpu(ptr->image_size); + checksum += le32_to_cpu(ptr->__reserved1); + checksum += le32_to_cpu(ptr->image_load); + checksum += le32_to_cpu(ptr->image_stored_size); + checksum += le32_to_cpu(ptr->__reserved2); + checksum = ~checksum; + + return cpu_to_le32(checksum); +} + +static void zynqimage_default_header(struct zynq_header *ptr) +{ + int i; + + if (ptr == NULL) + return; + + ptr->width_detection = HEADER_WIDTHDETECTION; + ptr->image_identifier = HEADER_IMAGEIDENTIFIER; + ptr->encryption = cpu_to_le32(ENCRYPTION_NONE); + + /* Setup not-supported/constant/reserved fields */ + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) + ptr->interrupt_vectors[i] = HEADER_INTERRUPT_DEFAULT; + + for (i = 0; i < HEADER_REGINITS; i++) { + ptr->register_init[i].address = HEADER_REGINIT_NULL; + ptr->register_init[i].data = HEADER_REGINIT_NULL; + } + + /* + * Certain reserved fields are required to be set to 0, ensure they are + * set as such. + */ + ptr->__reserved1 = 0x0; + ptr->__reserved2 = 0x0; +} + +/* mkimage glue functions */ +static int zynqimage_verify_header(unsigned char *ptr, int image_size, + struct image_tool_params *params) +{ + struct zynq_header *zynqhdr = (struct zynq_header *)ptr; + + if (image_size < sizeof(struct zynq_header)) + return -1; + + if (zynqhdr->width_detection != HEADER_WIDTHDETECTION) + return -1; + if (zynqhdr->image_identifier != HEADER_IMAGEIDENTIFIER) + return -1; + + if (zynqimage_checksum(zynqhdr) != zynqhdr->checksum) + return -1; + + return 0; +} + +static void zynqimage_print_header(const void *ptr) +{ + struct zynq_header *zynqhdr = (struct zynq_header *)ptr; + int i; + + printf("Image Type : Xilinx Zynq Boot Image support\n"); + printf("Image Offset : 0x%08x\n", le32_to_cpu(zynqhdr->image_offset)); + printf("Image Size : %lu bytes (%lu bytes packed)\n", + (unsigned long)le32_to_cpu(zynqhdr->image_size), + (unsigned long)le32_to_cpu(zynqhdr->image_stored_size)); + printf("Image Load : 0x%08x\n", le32_to_cpu(zynqhdr->image_load)); + printf("User Field : 0x%08x\n", le32_to_cpu(zynqhdr->user_field)); + printf("Checksum : 0x%08x\n", le32_to_cpu(zynqhdr->checksum)); + + for (i = 0; i < HEADER_INTERRUPT_VECTORS; i++) { + if (zynqhdr->interrupt_vectors[i] == HEADER_INTERRUPT_DEFAULT) + continue; + + printf("Modified Interrupt Vector Address [%d]: 0x%08x\n", i, + le32_to_cpu(zynqhdr->interrupt_vectors[i])); + } + + for (i = 0; i < HEADER_REGINITS; i++) { + if (zynqhdr->register_init[i].address == HEADER_REGINIT_NULL) + break; + + if (i == 0) + printf("Custom Register Initialization:\n"); + + printf(" @ 0x%08x -> 0x%08x\n", + le32_to_cpu(zynqhdr->register_init[i].address), + le32_to_cpu(zynqhdr->register_init[i].data)); + } +} + +static int zynqimage_check_params(struct image_tool_params *params) +{ + if (!params) + return 0; + + if (params->addr != 0x0) { + fprintf(stderr, "Error: Load Address cannot be specified.\n"); + return -1; + } + + /* + * If the entry point is specified ensure it is 64 byte aligned. + */ + if (params->eflag && (params->ep % 64 != 0)) { + fprintf(stderr, + "Error: Entry Point must be aligned to a 64-byte boundary.\n"); + return -1; + } + + return !((params->lflag || params->dflag) || + (params->dflag && params->eflag)); +} + +static int zynqimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_ZYNQIMAGE) + return EXIT_SUCCESS; + return EXIT_FAILURE; +} + +static void zynqimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct image_tool_params *params) +{ + struct zynq_header *zynqhdr = (struct zynq_header *)ptr; + zynqimage_default_header(zynqhdr); + + /* place image directly after header */ + zynqhdr->image_offset = + cpu_to_le32((uint32_t)sizeof(struct zynq_header)); + zynqhdr->image_size = cpu_to_le32((uint32_t)sbuf->st_size); + zynqhdr->image_stored_size = zynqhdr->image_size; + zynqhdr->image_load = 0x0; + if (params->eflag) + zynqhdr->image_load = cpu_to_le32((uint32_t)params->ep); + + zynqhdr->checksum = zynqimage_checksum(zynqhdr); +} + +U_BOOT_IMAGE_TYPE( + zynqimage, + "Xilinx Zynq Boot Image support", + sizeof(struct zynq_header), + (void *)&zynqimage_header, + zynqimage_check_params, + zynqimage_verify_header, + zynqimage_print_header, + zynqimage_set_header, + NULL, + zynqimage_check_image_types, + NULL, + NULL +); -- cgit v1.3.1 From f3bd72801aade1eb74e153bfa57c26f327571475 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Tue, 29 Sep 2015 01:27:13 +0200 Subject: zynq: sdhci: Define max clock by macro zc1571 with silicon can operate on 200MHz maximum frequency. Setup this frequency by default and fix setting for ep108. Signed-off-by: Michal Simek --- drivers/mmc/zynq_sdhci.c | 2 +- include/configs/xilinx_zynqmp.h | 3 +++ include/configs/xilinx_zynqmp_ep.h | 1 + include/configs/zynq-common.h | 1 + 4 files changed, 6 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index c69f5d4e2d4..e169b774932 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -29,7 +29,7 @@ int zynq_sdhci_init(phys_addr_t regbase) SDHCI_QUIRK_BROKEN_R1B; host->version = sdhci_readw(host, SDHCI_HOST_VERSION); - add_sdhci(host, 52000000, 52000000 >> 9); + add_sdhci(host, CONFIG_ZYNQ_SDHCI_MAX_FREQ, 52000000 >> 9); return 0; } diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 574f788500b..e990512083e 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -94,6 +94,9 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC +# ifndef CONFIG_ZYNQ_SDHCI_MAX_FREQ +# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 200000000 +# endif #endif #if defined(CONFIG_ZYNQ_SDHCI) diff --git a/include/configs/xilinx_zynqmp_ep.h b/include/configs/xilinx_zynqmp_ep.h index ed6023a7bfa..8bdb5c9c6d5 100644 --- a/include/configs/xilinx_zynqmp_ep.h +++ b/include/configs/xilinx_zynqmp_ep.h @@ -19,6 +19,7 @@ #define CONFIG_ZYNQ_GEM_PHY_ADDR0 7 #define CONFIG_ZYNQ_SDHCI0 +#define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #define CONFIG_ZYNQ_I2C0 #define CONFIG_SYS_I2C_ZYNQ #define CONFIG_ZYNQ_EEPROM diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index f33a3bcc68a..d10f1ddacaf 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -105,6 +105,7 @@ # define CONFIG_SDHCI # define CONFIG_ZYNQ_SDHCI # define CONFIG_CMD_MMC +# define CONFIG_ZYNQ_SDHCI_MAX_FREQ 52000000 #endif #ifdef CONFIG_ZYNQ_USB -- cgit v1.3.1