From e8c09d690be5bbaddd890859c2a00d9a6e6bd944 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:17 -0600
Subject: pci: Remove guard around compatibility functions

This prevents use of IS_ENABLED() in other files. Functions should be
visible in headers even if they are not available at link time.

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 include/pci.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'include')

diff --git a/include/pci.h b/include/pci.h
index 258c8f831ce..fed829727ce 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -840,7 +840,6 @@ extern void pci_mpc85xx_init (struct pci_controller *hose);
 extern void imx_pcie_remove(void);
 #endif
 
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 /**
  * pci_write_bar32() - Write the address of a BAR including control bits
  *
@@ -848,6 +847,8 @@ extern void imx_pcie_remove(void);
  * with devices which require hard-coded addresses, not part of the normal
  * PCI enumeration process.
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to use
  * @dev:	PCI device to update
  * @barnum:	BAR number (0-5)
@@ -859,6 +860,8 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
 /**
  * pci_read_bar32() - read the address of a bar
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to use
  * @dev:	PCI device to inspect
  * @barnum:	BAR number (0-5)
@@ -869,6 +872,8 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
 /**
  * pci_hose_find_devices() - Find devices by vendor/device ID
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to search
  * @busnum:	Bus number to search
  * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
@@ -879,7 +884,6 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
  */
 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
 				struct pci_device_id *ids, int *indexp);
-#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
 
 /* Access sizes for PCI reads and writes */
 enum pci_size_t {
-- 
cgit v1.3.1


From ae0998388630a00eb751364a3e7f094cdfcfc3e6 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:20 -0600
Subject: ppc: Drop CONFIG_SYS_PCI_SUBSYS_VENDORID

This is not used. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 include/configs/MPC8349EMDS.h       | 1 -
 include/configs/MPC8349EMDS_SDRAM.h | 1 -
 include/configs/MPC837XERDB.h       | 1 -
 include/configs/MPC8540ADS.h        | 1 -
 include/configs/MPC8560ADS.h        | 1 -
 scripts/config_whitelist.txt        | 1 -
 6 files changed, 6 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4dad6a58ff5..d6ae419456a 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -228,7 +228,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index f7c13d417f8..8ebca99d98b 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -283,7 +283,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index e16a5930ad8..0a136b4f92f 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -258,7 +258,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
 /*
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d843ba1ff78..ac9afa179a5 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -241,7 +241,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 464e7c72844..02aeb6f3d53 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -238,7 +238,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a6507edd9f2..274e6d85f5e 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -2936,7 +2936,6 @@ CONFIG_SYS_PCI_NR_INBOUND_WIN
 CONFIG_SYS_PCI_SLV_MEM_BUS
 CONFIG_SYS_PCI_SLV_MEM_LOCAL
 CONFIG_SYS_PCI_SLV_MEM_SIZE
-CONFIG_SYS_PCI_SUBSYS_VENDORID
 CONFIG_SYS_PCI_SYS_MEM_BUS
 CONFIG_SYS_PCI_SYS_MEM_PHYS
 CONFIG_SYS_PCI_SYS_MEM_SIZE
-- 
cgit v1.3.1


From 5ccee855f2106eba5a28d9a30f47d94f9ecc17eb Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:24 -0600
Subject: ppc: Drop DM_PCI from config files

Now that DM_PCI is always enabled we don't need to check it. Drop this
old code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 include/configs/MPC8548CDS.h   | 16 ----------------
 include/configs/P1010RDB.h     | 28 ----------------------------
 include/configs/P2041RDB.h     | 17 -----------------
 include/configs/T102xRDB.h     | 17 -----------------
 include/configs/T104xRDB.h     | 20 --------------------
 include/configs/T208xQDS.h     | 20 --------------------
 include/configs/T208xRDB.h     | 20 --------------------
 include/configs/T4240RDB.h     | 21 ---------------------
 include/configs/corenet_ds.h   | 21 ---------------------
 include/configs/p1_p2_rdb_pc.h | 24 ------------------------
 10 files changed, 204 deletions(-)

(limited to 'include')

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 32e19259cb2..d3e5da0c43a 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -370,23 +370,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #if defined(CONFIG_PCI)
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT		1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE	1
-#define CONFIG_SYS_PCIE1_NAME		"Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f5209e17964..b7e44d17373 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -150,34 +150,6 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCIE1_NAME		"mini PCIe Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
-#endif
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b5b159406a4..4ef061343c1 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -417,23 +417,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 1b4720db5c8..187304419e6 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -487,23 +487,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 57a0bf5287e..fb215bb05fb 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -537,26 +537,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b8d1693017e..f61b40fb3bd 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -486,26 +486,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index a04a49d0339..63cc5af2c6d 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -435,26 +435,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index aa185be7411..57a39fa970f 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -196,27 +196,6 @@
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 924093e6b05..c877f3c725e 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -430,27 +430,6 @@
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba5b649b971..54c82b4f335 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -529,30 +529,6 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
-- 
cgit v1.3.1


From 199056d1a1b8301b493adf469859fe38d9a77170 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:33 -0600
Subject: pci: Drop DM_PCI check from bios_emul

We don't need these checks anymore since when PCI is enabled, driver model
is always used.

Drop them.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 drivers/bios_emulator/atibios.c | 98 -----------------------------------------
 drivers/bios_emulator/bios.c    | 39 ----------------
 include/bios_emul.h             | 16 -------
 3 files changed, 153 deletions(-)

(limited to 'include')

diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 6c7cc24cbd9..9547470a2f7 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -230,19 +230,12 @@ This function executes the BIOS POST code on the controller. We assume that
 at this stage the controller has its I/O and memory space enabled and
 that all other controllers are in a disabled state.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
 			   int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
-			   int vesa_mode, struct vbe_mode_info *mode_info)
-#endif
 {
 	RMREGS regs;
 	RMSREGS sregs;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf;
-#endif
 
 	/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
 	 AH must contain the bus and AL must contain the devfn, encoded as
@@ -250,14 +243,9 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
 	 */
 	memset(&regs, 0, sizeof(regs));
 	memset(&sregs, 0, sizeof(sregs));
-#ifdef CONFIG_DM_PCI
 	bdf = dm_pci_get_bdf(pcidev);
 	regs.x.ax = (int)PCI_BUS(bdf) << 8 |
 			(int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
-#else
-	regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
-	    ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-#endif
 	/*Setup the X86 emulator for the VGA BIOS*/
 	BE_setVGA(vga_info);
 
@@ -300,28 +288,15 @@ NOTE: This function leaves the original memory aperture disabled by leaving
       it programmed to all 1's. It must be restored to the correct value
       later.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
-#else
-static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
-#endif
 {
 	u32 base, size;
 
 	for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
-#ifdef CONFIG_DM_PCI
 		dm_pci_read_config32(pcidev, *bar, &base);
-#else
-		pci_read_config_dword(pcidev, *bar, &base);
-#endif
 		if (!(base & 0x1)) {
-#ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF);
 			dm_pci_read_config32(pcidev, *bar, &size);
-#else
-			pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
-			pci_read_config_dword(pcidev, *bar, &size);
-#endif
 			size = ~(size & ~0xFF) + 1;
 			if (size >= MAX_BIOSLEN)
 				return base & ~0xFF;
@@ -344,19 +319,11 @@ necessary).
 Anyway to fix this we change all I/O mapped base registers and
 chop off the top bits.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
-#else
-static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
-#endif
 {
 	if ((*base & 0x1) && (*base > 0xFFFE)) {
 		*base &= 0xFFFF;
-#ifdef CONFIG_DM_PCI
 		dm_pci_write_config32(pcidev, reg, *base);
-#else
-		pci_write_config_dword(pcidev, reg, *base);
-#endif
 
 	}
 }
@@ -371,30 +338,18 @@ Pointers to the mapped BIOS image
 REMARKS:
 Maps a pointer to the BIOS image on the graphics card on the PCI bus.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 void *PCI_mapBIOSImage(struct udevice *pcidev)
-#else
-void *PCI_mapBIOSImage(pci_dev_t pcidev)
-#endif
 {
 	u32 BIOSImageBus;
 	int BIOSImageBAR;
 	u8 *BIOSImage;
 
 	/*Save PCI BAR registers that might get changed*/
-#ifdef CONFIG_DM_PCI
 	dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#else
-	pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#endif
 
 	/*Fix up I/O base registers to less than 64K */
 	if(saveBaseAddress14 != 0)
@@ -413,21 +368,12 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev)
 		return NULL;
 	}
 
-#ifdef CONFIG_DM_PCI
 	BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus,
 				       PCI_REGION_MEM, 0, MAP_NOCACHE);
 
 	/*Change the PCI BAR registers to map it onto the bus.*/
 	dm_pci_write_config32(pcidev, BIOSImageBAR, 0);
 	dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#else
-	BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
-				    PCI_REGION_MEM, 0, MAP_NOCACHE);
-
-	/*Change the PCI BAR registers to map it onto the bus.*/
-	pci_write_config_dword(pcidev, BIOSImageBAR, 0);
-	pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#endif
 	udelay(1);
 
 	/*Check that the BIOS image is valid. If not fail, or return the
@@ -447,7 +393,6 @@ pcidev	- PCI device info for the video card on the bus
 REMARKS:
 Unmaps the BIOS image for the device and restores framebuffer mappings
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
 {
 	dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
@@ -456,16 +401,6 @@ void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
 	dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
 	dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
 }
-#else
-void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
-{
-	pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
-}
-#endif
 
 /****************************************************************************
 PARAMETERS:
@@ -479,22 +414,14 @@ REMARKS:
 Loads and POST's the display controllers BIOS, directly from the BIOS
 image we can extract over the PCI bus.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static int PCI_postController(struct udevice *pcidev, uchar *bios_rom,
 			      int bios_len, BE_VGAInfo *vga_info,
 			      int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-			      BE_VGAInfo *vga_info, int vesa_mode,
-			      struct vbe_mode_info *mode_info)
-#endif
 {
 	u32 bios_image_len;
 	uchar *mapped_bios;
 	uchar *copy_of_bios;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf;
-#endif
 
 	if (bios_rom) {
 		copy_of_bios = bios_rom;
@@ -522,16 +449,10 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
 	}
 
 	/*Save information in vga_info structure*/
-#ifdef CONFIG_DM_PCI
 	bdf = dm_pci_get_bdf(pcidev);
 	vga_info->function = PCI_FUNC(bdf);
 	vga_info->device = PCI_DEV(bdf);
 	vga_info->bus = PCI_BUS(bdf);
-#else
-	vga_info->function = PCI_FUNC(pcidev);
-	vga_info->device = PCI_DEV(pcidev);
-	vga_info->bus = PCI_BUS(pcidev);
-#endif
 	vga_info->pcidev = pcidev;
 	vga_info->BIOSImage = copy_of_bios;
 	vga_info->BIOSImageLen = bios_image_len;
@@ -549,22 +470,13 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
 	return true;
 }
 
-#ifdef CONFIG_DM_PCI
 int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop)
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
-#endif
 {
 	BE_VGAInfo *VGAInfo;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf = dm_pci_get_bdf(pcidev);
 
 	printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
 	       PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf));
-#else
-	printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
-	       PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-#endif
 	/*Initialise the x86 BIOS emulator*/
 	if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
 		printf("videoboot: Out of memory!\n");
@@ -582,15 +494,9 @@ void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
 	X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
 }
 
-#ifdef CONFIG_DM_PCI
 int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len,
 		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
 		struct vbe_mode_info *mode_info)
-#else
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
-		struct vbe_mode_info *mode_info)
-#endif
 {
 	/*Post all the display controller BIOS'es*/
 	if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
@@ -623,12 +529,8 @@ REMARKS:
 Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
 and the X86 BIOS emulator module.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
 		      int clean_up)
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
-#endif
 {
 	BE_VGAInfo *VGAInfo;
 	int ret;
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index 77c7f94bc63..9596a1fdd3e 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -185,21 +185,12 @@ static void X86API int1A(int unused)
 	case 0xB103:		/* Find PCI class code */
 		M.x86.R_AH = DEVICE_NOT_FOUND;
 #ifdef __KERNEL__
-#ifdef CONFIG_DM_PCI
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
 				    &interface);
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
 				    &subclass);
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev,
 				    PCI_CLASS_DEVICE + 1, &baseclass);
-#else
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
-				     &interface);
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
-				     &subclass);
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev,
-				     PCI_CLASS_DEVICE + 1, &baseclass);
-#endif
 		if (M.x86.R_CL == interface && M.x86.R_CH == subclass
 		    && (u8) (M.x86.R_ECX >> 16) == baseclass) {
 #else
@@ -218,13 +209,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
 					    &M.x86.R_CL);
-# else
-			pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
-					     &M.x86.R_CL);
-# endif
 #else
 			M.x86.R_CL =
 			    (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
@@ -238,13 +224,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
 					     &M.x86.R_CX);
-# else
-			pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
-					     &M.x86.R_CX);
-# endif
 #else
 			M.x86.R_CX =
 			    (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
@@ -258,13 +239,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config32(_BE_env.vgaInfo.pcidev,
 					     M.x86.R_DI, &M.x86.R_ECX);
-# else
-			pci_read_config_dword(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, &M.x86.R_ECX);
-# endif
 #else
 			M.x86.R_ECX =
 			    (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
@@ -278,13 +254,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
 					     M.x86.R_DI, M.x86.R_CL);
-# else
-			pci_write_config_byte(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, M.x86.R_CL);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
 				      _BE_env.vgaInfo.pciInfo);
@@ -297,13 +268,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
 					      M.x86.R_DI, M.x86.R_CX);
-# else
-			pci_write_config_word(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, M.x86.R_CX);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
 				      _BE_env.vgaInfo.pciInfo);
@@ -316,13 +282,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
 					      M.x86.R_DI, M.x86.R_ECX);
-# else
-			pci_write_config_dword(_BE_env.vgaInfo.pcidev,
-					       M.x86.R_DI, M.x86.R_ECX);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
 				      _BE_env.vgaInfo.pciInfo);
diff --git a/include/bios_emul.h b/include/bios_emul.h
index 158e0f223d8..72410dc7948 100644
--- a/include/bios_emul.h
+++ b/include/bios_emul.h
@@ -30,11 +30,7 @@ typedef struct {
 	int bus;
 	u32 VendorID;
 	u32 DeviceID;
-#ifdef CONFIG_DM_PCI
 	struct udevice *pcidev;
-#else
-	pci_dev_t pcidev;
-#endif
 	void *BIOSImage;
 	u32 BIOSImageLen;
 	u8 LowMem[1536];
@@ -42,12 +38,8 @@ typedef struct {
 
 struct vbe_mode_info;
 
-#ifdef CONFIG_DM_PCI
 int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
 		      int clean_up);
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
-#endif
 
 /* Run a BIOS ROM natively (only supported on x86 machines) */
 void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
@@ -65,18 +57,10 @@ void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
 
 void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
 
-#ifdef CONFIG_DM_PCI
 int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
 
 int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
 		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
 		struct vbe_mode_info *mode_info);
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
-
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
-		struct vbe_mode_info *mode_info);
-#endif
 
 #endif
-- 
cgit v1.3.1


From 63814a69864ec5b2b8e85aace86ec1270e755c09 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:35 -0600
Subject: pci: imx: Drop DM_PCI check from cpu driver

We don't need this check anymore since when PCI is enabled, driver model
is always used.

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 arch/arm/mach-imx/cpu.c | 4 ----
 include/pci.h           | 4 ----
 2 files changed, 8 deletions(-)

(limited to 'include')

diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 423b7153522..8eb05c8dd67 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -283,10 +283,6 @@ u32 get_ahb_clk(void)
 
 void arch_preboot_os(void)
 {
-#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
-	imx_pcie_remove();
-#endif
-
 #if defined(CONFIG_IMX_AHCI)
 	struct udevice *dev;
 	int rc;
diff --git a/include/pci.h b/include/pci.h
index fed829727ce..4d771133b2a 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -836,10 +836,6 @@ int pci_last_busno(void);
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
 
-#ifdef CONFIG_PCIE_IMX
-extern void imx_pcie_remove(void);
-#endif
-
 /**
  * pci_write_bar32() - Write the address of a BAR including control bits
  *
-- 
cgit v1.3.1


From e15ba6802912a30da0de92c20dbe574f25a96d21 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:38 -0600
Subject: distro_bootcmd: Update DM_PCI check

Now that driver model is always used, check for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Update logic, reword]
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 include/config_distro_bootcmd.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index e70423f25dd..750e9e04e8f 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -265,7 +265,7 @@
 	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
 #endif
 
-#if defined(CONFIG_DM_PCI)
+#if defined(CONFIG_PCI)
 #define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
 #define BOOTENV_SHARED_PCI \
 	"boot_pci_enum=pci enum\0"
-- 
cgit v1.3.1


From 23cd8a63a036234fc9142015bf40b15d7ce27655 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:39 -0600
Subject: pci: Drop pci_init_board()

With the conversion to driver model, this is not needed now. Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 board/cavium/thunderx/thunderx.c     |   7 ---
 board/freescale/mpc8349emds/pci.c    |  73 -----------------------
 board/freescale/mpc837xerdb/Makefile |   1 -
 board/freescale/mpc837xerdb/pci.c    | 109 -----------------------------------
 board/xes/common/fsl_8xxx_pci.c      |  50 ----------------
 include/init.h                       |   3 -
 6 files changed, 243 deletions(-)
 delete mode 100644 board/freescale/mpc837xerdb/pci.c

(limited to 'include')

diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index a7dc5c6aeb6..a8f8c785584 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -123,10 +123,3 @@ int board_eth_init(struct bd_info *bis)
 
 	return rc;
 }
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	printf("DEBUG: PCI Init TODO *****\n");
-}
-#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 3ddbe717756..8c76c46d420 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -115,77 +115,4 @@ void pib_init(void)
 	i2c_set_bus_num(orig_i2c_bus);
 }
 
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
-	pci_ctrl->pitar0 = 0x0;
-	pci_ctrl->pibar0 = 0x0;
-	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar1  = 0x0;
-	pci_ctrl->pibar1  = 0x0;
-	pci_ctrl->piebar1 = 0x0;
-	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar2  = 0x0;
-	pci_ctrl->pibar2  = 0x0;
-	pci_ctrl->piebar2 = 0x0;
-	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
 #endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
index c683b017b55..4661e4cf232 100644
--- a/board/freescale/mpc837xerdb/Makefile
+++ b/board/freescale/mpc837xerdb/Makefile
@@ -4,4 +4,3 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-y += mpc837xerdb.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
deleted file mode 100644
index dccf8c5551b..00000000000
--- a/board/freescale/mpc837xerdb/pci.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-
-	/* Enable all 5 PCI_CLK_OUTPUTS */
-	clk->occr |= 0xf8000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* There is no PEX in MPC8379 parts. */
-	if (PARTID_NO_E(spridr) == SPR_8379)
-		return;
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 157aa32826a..c1fce7d3313 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -14,56 +14,6 @@
 #include <linux/libfdt.h>
 #include <fdt_support.h>
 
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-void pci_init_board(void)
-{
-	int first_free_busno = 0;
-
-#ifdef CONFIG_PCI1
-	int pcie_ep;
-	struct fsl_pci_info pci_info;
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 devdisr = in_be32(&gur->devdisr);
-	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
-	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
-	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
-	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
-	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
-			pci_32 ? 32 : 64,
-			pcix ? "PCIX" : "PCI",
-			pci_spd_norm ? ">=" : "<=",
-			pcix ? freq * 2 : freq,
-			pcie_ep ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter");
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI1: disabled\n");
-	}
-#elif defined CONFIG_ARCH_MPC8548
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	/* PCI1 not present on MPC8572 */
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_pci_setup(void *blob, struct bd_info *bd)
 {
diff --git a/include/init.h b/include/init.h
index fd51d7f9667..c781789e367 100644
--- a/include/init.h
+++ b/include/init.h
@@ -297,9 +297,6 @@ int board_late_init(void);
 int board_postclk_init(void); /* after clocks/timebase, before env/serial */
 int board_early_init_r(void);
 
-/* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */
-void pci_init_board(void);
-
 /**
  * arch_initr_trap() - Init traps
  *
-- 
cgit v1.3.1


From 4a753fbcee6db23a7d6eada12000f55df0f88df1 Mon Sep 17 00:00:00 2001
From: Simon Glass <sjg@chromium.org>
Date: Sun, 1 Aug 2021 18:54:42 -0600
Subject: ppc: Drop t4qds and b4860qds references

These boards have been removed. Drop the config file and other references.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 .azure-pipelines.yml             |   4 +-
 doc/board/freescale/b4860qds.rst | 453 ---------------------------------------
 doc/board/freescale/index.rst    |   1 -
 include/configs/t4qds.h          | 240 ---------------------
 4 files changed, 2 insertions(+), 696 deletions(-)
 delete mode 100644 doc/board/freescale/b4860qds.rst
 delete mode 100644 include/configs/t4qds.h

(limited to 'include')

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 0cf73025f7d..15507a73576 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -413,11 +413,11 @@ jobs:
         non_fsl_ppc:
           BUILDMAN: "powerpc -x freescale"
         mpc85xx_freescale:
-          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
         t208xrdb_corenet_ds:
           BUILDMAN: "t208xrdb corenet_ds"
         fsl_ppc:
-          BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
+          BUILDMAN: "mpc83xx&freescale"
         t102x:
           BUILDMAN: "t102*"
         p1_p2_rdb_pc:
diff --git a/doc/board/freescale/b4860qds.rst b/doc/board/freescale/b4860qds.rst
deleted file mode 100644
index de14d857b91..00000000000
--- a/doc/board/freescale/b4860qds.rst
+++ /dev/null
@@ -1,453 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-B4860QDS
-========
-
-The B4860QDS is a Freescale reference board that hosts the B4860 SoC
-(and variants).
-
-B4860 Overview
---------------
-The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
-StarCore and Power Architecture® cores. It targets the broadband wireless
-infrastructure and builds upon the proven success of the existing multicore
-DSPs and Power CPUs. It is designed to bolster the rapidly changing and
-expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
-
-The B4860 is a highly-integrated StarCore and Power Architecture processor that
-contains:
-
-* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
-  clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
-  for wireless base station applications
-* Four dual-thread e6500 Power Architecture processors organized in one
-  cluster-each core runs up to 1.8 GHz
-* Two DDR3/3L controllers for high-speed, industry-standard memory interface
-  each runs at up to 1866.67 MHz
-* MAPLE-B3 hardware acceleration-for forward error correction schemes including
-  Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
-  equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
-  FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
-  acceleration
-* CoreNet fabric that fully supports coherency using MESI protocol between the
-  e6500 cores, SC3900 FVP cores, memories and external interfaces.
-  CoreNet fabric interconnect runs at 667 MHz and supports coherent and
-  non-coherent out of order transactions with prioritization and bandwidth
-  allocation amongst CoreNet endpoints.
-* Data Path Acceleration Architecture, which includes the following:
-
-     * Frame Manager (FMan), which supports in-line packet parsing and general
-       classification to enable policing and QoS-based packet distribution
-     * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
-       of queue management, task management, load distribution, flow ordering,
-       buffer management, and allocation tasks from the cores
-     * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
-       IPsec, SSL, and 802.16
-     * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
-       and outbound). Supports types 5, 6 (outbound only)
-
-* Large internal cache memory with snooping and stashing capabilities for
-  bandwidth saving and high utilization of processor elements. The 9856-Kbyte
-  internal memory space includes the following:
-
-     * 32 Kbyte L1 ICache per e6500/SC3900 core
-     * 32 Kbyte L1 DCache per e6500/SC3900 core
-     * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
-     * 2048 Kbyte unified L2 cache for the e6500 cluster
-     * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
-
-* Sixteen 10-GHz SerDes lanes serving:
-
-     * Two Serial RapidIO interfaces
-     * Each supports up to 4 lanes and a total of up to 8 lanes
-
-* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
-  glue-less antenna connection
-* Two 10-Gbit Ethernet controllers (10GEC)
-* Six 1G/2.5-Gbit Ethernet controllers for network communications
-* PCI Express controller
-* Debug (Aurora)
-* Two OCeaN DMAs
-* Various system peripherals
-* 182 32-bit timers
-
-B4860QDS Overview
------------------
-- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
-  ECC, 4 GB of memory in two ranks of 2 GB.
-- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
-  ECC, 2 GB of memory. Single rank.
-- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
-  16x16 switch VSC3316
-- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
-  8x8 switch VSC3308
-- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
-  B4860 UART port is available over USB-to-UART translator USB2SER or over
-  RS232 flat cable.
-- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
-  copper connectors for Stand-alone mode and to the 1000Base-X over AMC
-  MicroTCA connector ports 0 and 2 for AMC mode.
-- The B4860 configuration may be loaded from nine bits coded reset configuration
-  reset source. The RCW source is set by appropriate DIP-switches.
-- 16-bit NOR Flash / PROMJet
-- QIXIS 8-bit NOR Flash Emulator
-- 8-bit NAND Flash
-- 24-bit SPI Flash
-- Long address I2C EEPROM
-- Available debug interfaces are:
-
-     - On-board eCWTAP controller with ETH and USB I/F
-     - JTAG/COP 16-pin header for any external TAP controller
-     - External JTAG source over AMC to support B2B configuration
-     - 70-pin Aurora debug connector
-
-- QIXIS (FPGA) logic:
-     - 2 KB internal memory space including
-
-- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
-  DDRCLK1,2 and RTCCLK.
-- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
-  frequency - total four refclk, including CPRI clock scheme.
-
-
-B4420 Personality
------------------
-
-B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
-and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
-and reduced target frequencies.
-
-Key differences between B4860 and B4420
----------------------------------------
-
-B4420 has:
-
-1. Less e6500 cores: 1 cluster with 2 e6500 cores
-2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
-3. Single DDRC
-4. 2X 4 lane serdes
-5. 3 SGMII interfaces
-6. no sRIO
-7. no 10G
-
-B4860QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
-   SW1	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
-   SW2	ON	ON	ON	ON	ON	ON	OFF	OFF
-   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
-   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
-	SW1 [1.1] = 0
-	SW2 [1.1] = 1
-	SW3 [1:4] = 0001
-
-NOR boot::
-
-	SW1 [1.1] = 1
-	SW2 [1.1] = 0
-	SW3 [1:4] = 1000
-
-B4420QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
-   SW1	OFF[0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
-   SW2	ON	OFF	ON	OFF	ON	ON	OFF	OFF
-   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
-   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
-	SW1 [1.1] = 0
-	SW2 [1.1] = 1
-	SW3 [1:4] = 0001
-
-NOR boot::
-
-	SW1 [1.1] = 1
-	SW2 [1.1] = 0
-	SW3 [1:4] = 1000
-
-Memory map on B4860QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-=============   =============   =============== =======
-Start Address	End Address	Description	Size
-=============   =============   =============== =======
-0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
-0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
-0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
-0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
-0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
-0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
-0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
-0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
-0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
-0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
-0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
-0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
-0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
-0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
-0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
-0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
-0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
-0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
-0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
-0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
-0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
-0x0_8000_0000 	0x0_FFFF_FFFF	DDRC1		2 GB
-0x0_0000_0000 	0x0_7FFF_FFFF	DDRC2	  	2 GB
-=============   =============   =============== =======
-
-Memory map on B4420QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-=============   =============   =============== =======
-Start Address	End Address	Description	Size
-=============   =============   =============== =======
-0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
-0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
-0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
-0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
-0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
-0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
-0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
-0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
-0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
-0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
-0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
-0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
-0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
-0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
-0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
-0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
-0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
-0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
-0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
-0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
-0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
-0x0_0000_0000 	0x0_FFFF_FFFF	DDRC1		4 GB
-=============   =============   =============== =======
-
-NOR Flash memory Map on B4860 and B4420QDS
-------------------------------------------
-
-=============   =============   ==============================  =========
- Start		 End		Definition			Size
-=============   =============   ==============================  =========
-0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
-0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
-0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
-0xEF300000	0xEFEFFFFF	rootfs (alternate bank)		12MB
-0xEE800000	0xEE8FFFFF	device tree (alternate bank)	1MB
-0xEE020000	0xEE6FFFFF	Linux.uImage (alternate bank)	6MB+896KB
-0xEE000000	0xEE01FFFF	RCW (alternate bank)		128KB
-0xEDF40000	0xEDFFFFFF	U-Boot (alternate bank)		768KB
-0xEDF20000	0xEDF3FFFF	U-Boot env (alternate bank)	128KB
-0xEDF00000	0xEDF1FFFF	FMAN ucode (alternate bank)	128KB
-0xED300000	0xEDEFFFFF	rootfs (current bank)		12MB
-0xEC800000	0xEC8FFFFF	device tree (current bank)	1MB
-0xEC020000	0xEC6FFFFF	Linux.uImage (current bank)	6MB+896KB
-0xEC000000	0xEC01FFFF	RCW (current bank)		128KB
-=============   =============   ==============================  =========
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to both B4860QDS and B4420QDS.
-
-U-Boot environment variable hwconfig
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The default hwconfig is:
-
-.. code-block:: none
-
-   hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
-
-Note: For USB gadget set "dr_mode=peripheral"
-
-FMAN Ucode versions
-^^^^^^^^^^^^^^^^^^^
-
-fsl_fman_ucode_B4860_106_3_6.bin
-
-Switching to alternate bank
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Commands for switching to alternate bank.
-
-1. To change from vbank0 to vbank2
-
-.. code-block:: none
-
-   => qixis_reset altbank (it will boot using vbank2)
-
-2. To change from vbank2 to vbank0
-
-.. code-block:: none
-
-   => qixis reset (it will boot using vbank0)
-
-To change personality of board
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-For changing personality from B4860 to B4420
-
-1. Boot from vbank0
-2. Flash vbank2 with b4420 rcw and U-Boot
-3. Give following commands to uboot prompt
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30;
-   => mw.b ffdf0010 0x00;
-   => mw.b ffdf0062 0x02;
-   => mw.b ffdf0050 0x02;
-   => mw.b ffdf0010 0x30;
-   => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-To change from NOR to NAND boot give following command on uboot prompt
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30
-   => mw.b ffdf0010 0x00
-   => mw.b 0xffdf0050 0x08
-   => mw.b 0xffdf0060 0x82
-   => mw.b ffdf0061 0x00
-   => mw.b ffdf0010 0x30
-   => reset
-
-To change from NAND to NOR boot give following command on uboot prompt:
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30
-   => mw.b ffdf0010 0x00
-   => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
-   => mw.b 0xffdf0060 0x12
-   => mw.b ffdf0061 0x01
-   => mw.b ffdf0010 0x30
-   => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Ethernet interfaces for B4860QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
-* 0x2a, 0xb2 (serdes1, serdes2)
-
-When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
-SGMII on SGMII riser card.
-
-Under U-Boot these network interfaces are recognized as::
-
-   FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
-
-On Linux the interfaces are renamed as::
-
-   eth2 -> fm1-gb2
-   eth3 -> fm1-gb3
-   eth4 -> fm1-gb4
-   eth5 -> fm1-gb5
-
-RCW and Ethernet interfaces for B4420QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x18, 0x9e (serdes1, serdes2)
-
-Under U-Boot these network interfaces are recognized as::
-
-   FM1@DTSEC3, FM1@DTSEC4 and  e1000#0.
-
-On Linux the interfaces are renamed as::
-
-   eth2 -> fm1-gb2
-   eth3 -> fm1-gb3
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework during  boot:
-
-+----------------------------------------------+
-|Area        | Address                         |
-+----------------------------------------------+
-|Secure boot | 0xFFFC0000 (32KB)               |
-|headers     |                                 |
-+----------------------------------------------+
-|GD, BD      | 0xFFFC8000 (4KB)                |
-+----------------------------------------------+
-|ENV         | 0xFFFC9000 (8KB)                |
-+----------------------------------------------+
-|HEAP        | 0xFFFCB000 (30KB)               |
-+----------------------------------------------+
-|STACK       | 0xFFFD8000 (22KB)               |
-+----------------------------------------------+
-|U-Boot SPL  | 0xFFFD8000 (160KB)              |
-+----------------------------------------------+
-
-NAND Flash memory Map on B4860 and B4420QDS
--------------------------------------------
-
-=============   =============   =============================   =====
-Start		End		Definition			Size
-=============   =============   =============================   =====
-0x000000	0x0FFFFF	U-Boot                          1MB
-0x140000	0x15FFFF	U-Boot env                      128KB
-0x1A0000	0x1BFFFF	FMAN Ucode                      128KB
-=============   =============   =============================   =====
diff --git a/doc/board/freescale/index.rst b/doc/board/freescale/index.rst
index 313cf409a69..bddc6c6c2c7 100644
--- a/doc/board/freescale/index.rst
+++ b/doc/board/freescale/index.rst
@@ -6,7 +6,6 @@ Freescale
 .. toctree::
    :maxdepth: 2
 
-   b4860qds
    imx8mm_evk
    imx8mn_evk
    imx8mp_evk
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
deleted file mode 100644
index b62ddc7075b..00000000000
--- a/include/configs/t4qds.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * Corenet DS style board configuration file
- */
-#ifndef __T4QDS_H
-#define __T4QDS_H
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB			/* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/*
- *  Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
-#define CONFIG_SYS_L3_SIZE		(512 << 10)
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4
-
-#define CONFIG_DDR_SPD
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE	0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME		"FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-#define CONFIG_HVBOOT				\
- "setenv bootargs config-addr=0x60000000; "	\
- "bootm 0x01000000 - 0x00f00000"
-
-#endif	/* __CONFIG_H */
-- 
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