From 0693923cd240f5d401be0a53cddcf0fb1d9ad9d3 Mon Sep 17 00:00:00 2001 From: Albert Aribaud Date: Mon, 11 Oct 2010 13:13:29 +0200 Subject: edminiv2: add support for ELF relocations Signed-off-by: Albert Aribaud --- include/configs/edminiv2.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h index ccfc66053b5..43e5e870f00 100644 --- a/include/configs/edminiv2.h +++ b/include/configs/edminiv2.h @@ -223,4 +223,9 @@ #define CONFIG_SYS_RESET_ADDRESS 0xffff0000 #define CONFIG_SYS_MAXARGS 16 +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* _CONFIG_EDMINIV2_H */ -- cgit v1.3.1 From 9710504d200599a6e7e7ac0046adca43cfccaf0f Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 11 Oct 2010 14:08:14 +0200 Subject: arm926ejs, tx25: add support for ELF relocations Signed-off-by: Heiko Schocher --- arch/arm/config.mk | 2 ++ arch/arm/cpu/arm926ejs/start.S | 8 ++++---- board/karo/tx25/config.mk | 2 +- include/configs/tx25.h | 2 +- nand_spl/board/karo/tx25/u-boot.lds | 13 +++++++++++++ 5 files changed, 21 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 0be47d3c42e..21c1e33e674 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -70,5 +70,7 @@ LDSCRIPT := $(SRCTREE)/$(CPUDIR)/u-boot.lds ifndef CONFIG_SYS_ARM_WITHOUT_RELOC # needed for relocation +ifndef CONFIG_NAND_SPL PLATFORM_LDFLAGS += -pie endif +endif diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 49ca839a431..e882487c25a 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -279,10 +279,10 @@ clbss_l:str r2, [r0] /* clear loop... */ */ #ifdef CONFIG_NAND_SPL ldr r0, _nand_boot_ofs - adr r1, _start - add pc, r0, r1 -_nand_boot_ofs - : .word nand_boot - _start + mov pc, r0 + +_nand_boot_ofs: + .word nand_boot #else ldr r0, _board_init_r_ofs adr r1, _start diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk index 51ca1ab0f0d..8be6466b5a8 100644 --- a/board/karo/tx25/config.mk +++ b/board/karo/tx25/config.mk @@ -1,5 +1,5 @@ ifdef CONFIG_NAND_SPL TEXT_BASE = 0x810c0000 else -TEXT_BASE = 0x81fc0000 +TEXT_BASE = 0x81200000 endif diff --git a/include/configs/tx25.h b/include/configs/tx25.h index bcc8140df0d..996afa3b070 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -41,7 +41,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000) +#define CONFIG_SYS_NAND_U_BOOT_DST (0x81200000) #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index c5725575355..5f95c874f6e 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -53,6 +53,11 @@ SECTIONS *(.data.rel.ro) } + . = ALIGN(4); + __rel_dyn_start = .; + __rel_dyn_end = .; + __dynsym_start = .; + __got_start = .; . = ALIGN(4); .got : { *(.got) } @@ -67,4 +72,12 @@ SECTIONS __bss_start = .; .bss : { *(.bss) } _end = .; + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } } -- cgit v1.3.1 From ff9f475d5d46da7e4acf523a61aef65638765670 Mon Sep 17 00:00:00 2001 From: Jason Liu Date: Mon, 18 Oct 2010 11:09:26 +0800 Subject: MX5: rename mx51 to mx5 Rename mx51 to mx5 in order to support more mx51 like-style SOCs such as MX53 and the followings. Signed-off-by: Jason Liu --- arch/arm/cpu/armv7/mx5/Makefile | 48 +++ arch/arm/cpu/armv7/mx5/clock.c | 294 +++++++++++++++++++ arch/arm/cpu/armv7/mx5/iomux.c | 166 +++++++++++ arch/arm/cpu/armv7/mx5/lowlevel_init.S | 291 +++++++++++++++++++ arch/arm/cpu/armv7/mx5/soc.c | 120 ++++++++ arch/arm/cpu/armv7/mx5/speed.c | 39 +++ arch/arm/cpu/armv7/mx5/timer.c | 119 ++++++++ arch/arm/cpu/armv7/mx5/u-boot.lds | 73 +++++ arch/arm/cpu/armv7/mx51/Makefile | 48 --- arch/arm/cpu/armv7/mx51/clock.c | 294 ------------------- arch/arm/cpu/armv7/mx51/iomux.c | 166 ----------- arch/arm/cpu/armv7/mx51/lowlevel_init.S | 291 ------------------- arch/arm/cpu/armv7/mx51/soc.c | 114 -------- arch/arm/cpu/armv7/mx51/speed.c | 39 --- arch/arm/cpu/armv7/mx51/timer.c | 119 -------- arch/arm/cpu/armv7/mx51/u-boot.lds | 73 ----- arch/arm/include/asm/arch-mx5/asm-offsets.h | 50 ++++ arch/arm/include/asm/arch-mx5/clock.h | 43 +++ arch/arm/include/asm/arch-mx5/crm_regs.h | 192 ++++++++++++ arch/arm/include/asm/arch-mx5/imx-regs.h | 279 ++++++++++++++++++ arch/arm/include/asm/arch-mx5/iomux.h | 193 +++++++++++++ arch/arm/include/asm/arch-mx5/mx5x_pins.h | 418 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx5/sys_proto.h | 31 ++ arch/arm/include/asm/arch-mx51/asm-offsets.h | 50 ---- arch/arm/include/asm/arch-mx51/clock.h | 43 --- arch/arm/include/asm/arch-mx51/crm_regs.h | 192 ------------ arch/arm/include/asm/arch-mx51/imx-regs.h | 279 ------------------ arch/arm/include/asm/arch-mx51/iomux.h | 193 ------------- arch/arm/include/asm/arch-mx51/mx51_pins.h | 418 --------------------------- arch/arm/include/asm/arch-mx51/sys_proto.h | 31 -- board/freescale/mx51evk/mx51evk.c | 2 +- board/ttcontrol/vision2/vision2.c | 2 +- boards.cfg | 4 +- include/configs/mx51evk.h | 4 +- include/configs/vision2.h | 4 +- 35 files changed, 2364 insertions(+), 2358 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx5/Makefile create mode 100644 arch/arm/cpu/armv7/mx5/clock.c create mode 100644 arch/arm/cpu/armv7/mx5/iomux.c create mode 100644 arch/arm/cpu/armv7/mx5/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/mx5/soc.c create mode 100644 arch/arm/cpu/armv7/mx5/speed.c create mode 100644 arch/arm/cpu/armv7/mx5/timer.c create mode 100644 arch/arm/cpu/armv7/mx5/u-boot.lds delete mode 100644 arch/arm/cpu/armv7/mx51/Makefile delete mode 100644 arch/arm/cpu/armv7/mx51/clock.c delete mode 100644 arch/arm/cpu/armv7/mx51/iomux.c delete mode 100644 arch/arm/cpu/armv7/mx51/lowlevel_init.S delete mode 100644 arch/arm/cpu/armv7/mx51/soc.c delete mode 100644 arch/arm/cpu/armv7/mx51/speed.c delete mode 100644 arch/arm/cpu/armv7/mx51/timer.c delete mode 100644 arch/arm/cpu/armv7/mx51/u-boot.lds create mode 100644 arch/arm/include/asm/arch-mx5/asm-offsets.h create mode 100644 arch/arm/include/asm/arch-mx5/clock.h create mode 100644 arch/arm/include/asm/arch-mx5/crm_regs.h create mode 100644 arch/arm/include/asm/arch-mx5/imx-regs.h create mode 100644 arch/arm/include/asm/arch-mx5/iomux.h create mode 100644 arch/arm/include/asm/arch-mx5/mx5x_pins.h create mode 100644 arch/arm/include/asm/arch-mx5/sys_proto.h delete mode 100644 arch/arm/include/asm/arch-mx51/asm-offsets.h delete mode 100644 arch/arm/include/asm/arch-mx51/clock.h delete mode 100644 arch/arm/include/asm/arch-mx51/crm_regs.h delete mode 100644 arch/arm/include/asm/arch-mx51/imx-regs.h delete mode 100644 arch/arm/include/asm/arch-mx51/iomux.h delete mode 100644 arch/arm/include/asm/arch-mx51/mx51_pins.h delete mode 100644 arch/arm/include/asm/arch-mx51/sys_proto.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/mx5/Makefile b/arch/arm/cpu/armv7/mx5/Makefile new file mode 100644 index 00000000000..7cfaa2c1305 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = soc.o clock.o iomux.o timer.o speed.o +SOBJS = lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c new file mode 100644 index 00000000000..00f649cf487 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -0,0 +1,294 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +enum pll_clocks { + PLL1_CLOCK = 0, + PLL2_CLOCK, + PLL3_CLOCK, + PLL_CLOCKS, +}; + +struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { + [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, + [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, + [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, +}; + +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + +/* + * Calculate the frequency of this pll. + */ +static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq) +{ + u32 mfi, mfn, mfd, pd; + + mfn = __raw_readl(&pll->mfn); + mfd = __raw_readl(&pll->mfd) + 1; + mfi = __raw_readl(&pll->op); + pd = (mfi & 0xF) + 1; + mfi = (mfi >> 4) & 0xF; + mfi = (mfi >= 5) ? mfi : 5; + + return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; +} + +/* + * Get mcu main rate + */ +u32 get_mcu_main_clk(void) +{ + u32 reg, freq; + + reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >> + MXC_CCM_CACRR_ARM_PODF_OFFSET; + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + return freq / (reg + 1); +} + +/* + * Get the rate of peripheral's root clock. + */ +static u32 get_periph_clk(void) +{ + u32 reg; + + reg = __raw_readl(&mxc_ccm->cbcdr); + if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) + return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK); + reg = __raw_readl(&mxc_ccm->cbcmr); + switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + case 1: + return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); + default: + return 0; + } + /* NOTREACHED */ +} + +/* + * Get the rate of ipg clock. + */ +static u32 get_ipg_clk(void) +{ + u32 ahb_podf, ipg_podf; + + ahb_podf = __raw_readl(&mxc_ccm->cbcdr); + ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> + MXC_CCM_CBCDR_IPG_PODF_OFFSET; + ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> + MXC_CCM_CBCDR_AHB_PODF_OFFSET; + return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); +} + +/* + * Get the rate of ipg_per clock. + */ +static u32 get_ipg_per_clk(void) +{ + u32 pred1, pred2, podf; + + if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) + return get_ipg_clk(); + /* Fixme: not handle what about lpm*/ + podf = __raw_readl(&mxc_ccm->cbcdr); + pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; + pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> + MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; + podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> + MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; + + return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); +} + +/* + * Get the rate of uart clk. + */ +static u32 get_uart_clk(void) +{ + unsigned int freq, reg, pred, podf; + + reg = __raw_readl(&mxc_ccm->cscmr1); + switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> + MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { + case 0x0: + freq = decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_SYS_MX5_HCLK); + break; + case 0x1: + freq = decode_pll(mxc_plls[PLL2_CLOCK], + CONFIG_SYS_MX5_HCLK); + break; + case 0x2: + freq = decode_pll(mxc_plls[PLL3_CLOCK], + CONFIG_SYS_MX5_HCLK); + break; + default: + return 66500000; + } + + reg = __raw_readl(&mxc_ccm->cscdr1); + + pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; + + podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> + MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; + freq /= (pred + 1) * (podf + 1); + + return freq; +} + +/* + * This function returns the low power audio clock. + */ +u32 get_lp_apm(void) +{ + u32 ret_val = 0; + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + + if (((ccsr >> 9) & 1) == 0) + ret_val = CONFIG_SYS_MX5_HCLK; + else + ret_val = ((32768 * 1024)); + + return ret_val; +} + +/* + * get cspi clock rate. + */ +u32 imx_get_cspiclk(void) +{ + u32 ret_val = 0, pdf, pre_pdf, clk_sel; + u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); + u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2); + + pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; + pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ + >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; + clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ + >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; + + switch (clk_sel) { + case 0: + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_SYS_MX5_HCLK) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case 1: + ret_val = decode_pll(mxc_plls[PLL2_CLOCK], + CONFIG_SYS_MX5_HCLK) / + ((pre_pdf + 1) * (pdf + 1)); + break; + case 2: + ret_val = decode_pll(mxc_plls[PLL3_CLOCK], + CONFIG_SYS_MX5_HCLK) / + ((pre_pdf + 1) * (pdf + 1)); + break; + default: + ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); + break; + } + + return ret_val; +} + +/* + * The API of get mxc clockes. + */ +unsigned int mxc_get_clock(enum mxc_clock clk) +{ + switch (clk) { + case MXC_ARM_CLK: + return get_mcu_main_clk(); + case MXC_AHB_CLK: + break; + case MXC_IPG_CLK: + return get_ipg_clk(); + case MXC_IPG_PERCLK: + return get_ipg_per_clk(); + case MXC_UART_CLK: + return get_uart_clk(); + case MXC_CSPI_CLK: + return imx_get_cspiclk(); + case MXC_FEC_CLK: + return decode_pll(mxc_plls[PLL1_CLOCK], + CONFIG_SYS_MX5_HCLK); + default: + break; + } + return -1; +} + +u32 imx_get_uartclk(void) +{ + return get_uart_clk(); +} + + +u32 imx_get_fecclk(void) +{ + return mxc_get_clock(MXC_IPG_CLK); +} + +/* + * Dump some core clockes. + */ +int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + u32 freq; + + freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + printf("pll1: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK); + printf("pll2: %dMHz\n", freq / 1000000); + freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK); + printf("pll3: %dMHz\n", freq / 1000000); + printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); + printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); + + return 0; +} + +/***************************************************/ + +U_BOOT_CMD( + clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks, + "display clocks\n", + "" +); diff --git a/arch/arm/cpu/armv7/mx5/iomux.c b/arch/arm/cpu/armv7/mx5/iomux.c new file mode 100644 index 00000000000..e8928d5fde4 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/iomux.c @@ -0,0 +1,166 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +/* IOMUX register (base) addresses */ +enum iomux_reg_addr { + IOMUXGPR0 = IOMUXC_BASE_ADDR, + IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, + IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, + IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, + IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, + IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, +}; + +#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) + +/* Get the iomux register address of this pin */ +static inline u32 get_mux_reg(iomux_pin_name_t pin) +{ + u32 mux_reg = PIN_TO_IOMUX_MUX(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + /* + * Fixup register address: + * i.MX51 TO1 has offset with the register + * which is define as TO2. + */ + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (mux_reg >= 0x2FC) + mux_reg += 8; + else if (mux_reg >= 0x130) + mux_reg += 0xC; + } + mux_reg += IOMUXSW_MUX_CTL; + return mux_reg; +} + +/* Get the pad register address of this pin */ +static inline u32 get_pad_reg(iomux_pin_name_t pin) +{ + u32 pad_reg = PIN_TO_IOMUX_PAD(pin); + + if (is_soc_rev(CHIP_REV_2_0) < 0) { + /* + * Fixup register address: + * i.MX51 TO1 has offset with the register + * which is define as TO2. + */ + if ((pin == MX51_PIN_NANDF_RB5) || + (pin == MX51_PIN_NANDF_RB6) || + (pin == MX51_PIN_NANDF_RB7)) + ; /* Do nothing */ + else if (pad_reg == 0x4D0 - PAD_I_START) + pad_reg += 0x4C; + else if (pad_reg == 0x860 - PAD_I_START) + pad_reg += 0x9C; + else if (pad_reg >= 0x804 - PAD_I_START) + pad_reg += 0xB0; + else if (pad_reg >= 0x7FC - PAD_I_START) + pad_reg += 0xB4; + else if (pad_reg >= 0x4E4 - PAD_I_START) + pad_reg += 0xCC; + else + pad_reg += 8; + } + pad_reg += IOMUXSW_PAD_CTL; + return pad_reg; +} + +/* Get the last iomux register address */ +static inline u32 get_mux_end(void) +{ + if (is_soc_rev(CHIP_REV_2_0) < 0) + return IOMUXC_BASE_ADDR + (0x3F8 - 4); + else + return IOMUXC_BASE_ADDR + (0x3F0 - 4); +} + +/* + * This function is used to configure a pin through the IOMUX module. + * @param pin a pin number as defined in iomux_pin_name_t + * @param cfg an output function as defined in iomux_pin_cfg_t + * + * @return 0 if successful; Non-zero otherwise + */ +static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + u32 mux_reg = get_mux_reg(pin); + + if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) + return ; + if (cfg == IOMUX_CONFIG_GPIO) + writel(PIN_TO_ALT_GPIO(pin), mux_reg); + else + writel(cfg, mux_reg); +} + +/* + * Request ownership for an IO pin. This function has to be the first one + * being called before that pin is used. The caller has to check the + * return value to make sure it returns 0. + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + * + */ +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ + iomux_config_mux(pin, cfg); +} + +/* + * Release ownership for an IO pin + * + * @param pin a name defined by iomux_pin_name_t + * @param cfg an input function as defined in iomux_pin_cfg_t + */ +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) +{ +} + +/* + * This function configures the pad value for a IOMUX pin. + * + * @param pin a pin number as defined in iomux_pin_name_t + * @param config the ORed value of elements defined in iomux_pad_config_t + */ +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) +{ + u32 pad_reg = get_pad_reg(pin); + writel(config, pad_reg); +} + +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) +{ + u32 pad_reg = get_pad_reg(pin); + return readl(pad_reg); +} diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S new file mode 100644 index 00000000000..783c81f72a7 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -0,0 +1,291 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* + * L2CC Cache setup/invalidation/disable + */ +.macro init_l2cc + /* explicitly disable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + bic r0, r0, #0x2 + mcr 15, 0, r0, c1, c0, 1 + + /* reconfigure L2 cache aux control reg */ + mov r0, #0xC0 /* tag RAM */ + add r0, r0, #0x4 /* data RAM */ + orr r0, r0, #(1 << 24) /* disable write allocate delay */ + orr r0, r0, #(1 << 23) /* disable write allocate combine */ + orr r0, r0, #(1 << 22) /* disable write allocate */ + + cmp r3, #0x10 /* r3 contains the silicon rev */ + + /* disable write combine for TO 2 and lower revs */ + orrls r0, r0, #(1 << 25) + + mcr 15, 1, r0, c9, c0, 2 +.endm /* init_l2cc */ + +/* AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =AIPS1_BASE_ADDR + ldr r1, =0x77777777 + str r1, [r0, #0x0] + str r1, [r0, #0x4] + ldr r0, =AIPS2_BASE_ADDR + str r1, [r0, #0x0] + str r1, [r0, #0x4] + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ +.endm /* init_aips */ + +/* M4IF setup */ +.macro init_m4if + /* VPU and IPU given higher priority (0x4) + * IPU accesses with ID=0x1 given highest priority (=0xA) + */ + ldr r0, =M4IF_BASE_ADDR + + ldr r1, =0x00000203 + str r1, [r0, #0x40] + + ldr r1, =0x0 + str r1, [r0, #0x44] + + ldr r1, =0x00120125 + str r1, [r0, #0x9C] + + ldr r1, =0x001901A3 + str r1, [r0, #0x48] + +.endm /* init_m4if */ + +.macro setup_pll pll, freq + ldr r2, =\pll + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ + mov r1, #0x2 + str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ + + str r3, [r2, #PLL_DP_OP] + str r3, [r2, #PLL_DP_HFS_OP] + + str r4, [r2, #PLL_DP_MFD] + str r4, [r2, #PLL_DP_HFS_MFD] + + str r5, [r2, #PLL_DP_MFN] + str r5, [r2, #PLL_DP_HFS_MFN] + + ldr r1, =0x00001232 + str r1, [r2, #PLL_DP_CTL] +1: ldr r1, [r2, #PLL_DP_CTL] + ands r1, r1, #0x1 + beq 1b +.endm + +.macro init_clock + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + ldr r1, =0x0 + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x00000300 + str r1, [r0, #CLKCTL_CCGR6] + + /* Disable IPU and HSC dividers */ + mov r1, #0x60000 + str r1, [r0, #CLKCTL_CCDR] + + /* Make sure to switch the DDR away from PLL 1 */ + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + mov r3, #DP_OP_800 + mov r4, #DP_MFD_800 + mov r5, #DP_MFN_800 + setup_pll PLL1_BASE_ADDR + + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL3_BASE_ADDR + + /* Switch peripheral to PLL 3 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x000010C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + ldr r1, =0x13239145 + str r1, [r0, #CLKCTL_CBCDR] + mov r3, #DP_OP_665 + mov r4, #DP_MFD_665 + mov r5, #DP_MFN_665 + setup_pll PLL2_BASE_ADDR + + /* Switch peripheral to PLL2 */ + ldr r0, =CCM_BASE_ADDR + ldr r1, =0x19239145 + str r1, [r0, #CLKCTL_CBCDR] + ldr r1, =0x000020C0 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + + mov r3, #DP_OP_216 + mov r4, #DP_MFD_216 + mov r5, #DP_MFN_216 + setup_pll PLL3_BASE_ADDR + + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + + /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 + movls r1, #0x1 + movhi r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + mov r1, #0 + str r1, [r0, #CLKCTL_CCSR] + + /* setup the rest */ + /* Use lp_apm (24MHz) source for perclk */ + ldr r1, =0x000020C2 + orr r1,r1,#CONFIG_SYS_DDR_CLKSEL + str r1, [r0, #CLKCTL_CBCMR] + /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ + ldr r1, =CONFIG_SYS_CLKTL_CBCDR + str r1, [r0, #CLKCTL_CBCDR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + + /* Use PLL 2 for UART's, get 66.5MHz from it */ + ldr r1, =0xA5A2A020 + str r1, [r0, #CLKCTL_CSCMR1] + ldr r1, =0x00C30321 + str r1, [r0, #CLKCTL_CSCDR1] + + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + mov r1, #0x0 + str r1, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +.endm + +.macro setup_wdog + ldr r0, =WDOG1_BASE_ADDR + mov r1, #0x30 + strh r1, [r0] +.endm + +.section ".text.init", "x" + +.globl lowlevel_init +lowlevel_init: + ldr r0, =GPIO1_BASE_ADDR + ldr r1, [r0, #0x0] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x0] + ldr r1, [r0, #0x4] + orr r1, r1, #(1 << 23) + str r1, [r0, #0x4] + +#ifdef ENABLE_IMPRECISE_ABORT + mrs r1, spsr /* save old spsr */ + mrs r0, cpsr /* read out the cpsr */ + bic r0, r0, #0x100 /* clear the A bit */ + msr spsr, r0 /* update spsr */ + add lr, pc, #0x8 /* update lr */ + movs pc, lr /* update cpsr */ + nop + nop + nop + nop + msr spsr, r1 /* restore old spsr */ +#endif + + init_l2cc + + init_aips + + init_m4if + + init_clock + + /* r12 saved upper lr*/ + mov pc,lr + +/* Board level setting value */ +DDR_PERCHARGE_CMD: .word 0x04008008 +DDR_REFRESH_CMD: .word 0x00008010 +DDR_LMR1_W: .word 0x00338018 +DDR_LMR_CMD: .word 0xB2220000 +DDR_TIMING_W: .word 0xB02567A9 +DDR_MISC_W: .word 0x000A0104 diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c new file mode 100644 index 00000000000..7c7a565665f --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +#ifdef CONFIG_FSL_ESDHC +#include +#endif + +#if defined(CONFIG_MX51) +#define CPU_TYPE 0x51000 +#else +#error "CPU_TYPE not defined" +#endif + +u32 get_cpu_rev(void) +{ + int system_rev = CPU_TYPE; + int reg = __raw_readl(ROM_SI_REV); + + switch (reg) { + case 0x02: + system_rev |= CHIP_REV_1_1; + break; + case 0x10: + if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) + system_rev |= CHIP_REV_2_5; + else + system_rev |= CHIP_REV_2_0; + break; + case 0x20: + system_rev |= CHIP_REV_3_0; + break; + return system_rev; + default: + system_rev |= CHIP_REV_1_0; + break; + } + return system_rev; +} + + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", + (cpurev & 0xFF000) >> 12, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + return 0; +} +#endif + +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +#if defined(CONFIG_FEC_MXC) +extern int fecmxc_initialize(bd_t *bis); +#endif + +int cpu_eth_init(bd_t *bis) +{ + int rc = -ENODEV; + +#if defined(CONFIG_FEC_MXC) + rc = fecmxc_initialize(bis); +#endif + + return rc; +} + +/* + * Initializes on-chip MMC controllers. + * to override, implement board_mmc_init() + */ +int cpu_mmc_init(bd_t *bis) +{ +#ifdef CONFIG_FSL_ESDHC + return fsl_esdhc_mmc_init(bis); +#else + return 0; +#endif +} + + +void reset_cpu(ulong addr) +{ + __raw_writew(4, WDOG1_BASE_ADDR); +} diff --git a/arch/arm/cpu/armv7/mx5/speed.c b/arch/arm/cpu/armv7/mx5/speed.c new file mode 100644 index 00000000000..a444def7eb8 --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/speed.c @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +int get_clocks(void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FSL_ESDHC + gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); +#endif + return 0; +} diff --git a/arch/arm/cpu/armv7/mx5/timer.c b/arch/arm/cpu/armv7/mx5/timer.c new file mode 100644 index 00000000000..3044fcf1e9b --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/timer.c @@ -0,0 +1,119 @@ +/* + * (C) Copyright 2007 + * Sascha Hauer, Pengutronix + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +/* General purpose timers registers */ +struct mxc_gpt { + unsigned int control; + unsigned int prescaler; + unsigned int status; + unsigned int nouse[6]; + unsigned int counter; +}; + +static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; + +/* General purpose timers bitfields */ +#define GPTCR_SWR (1<<15) /* Software reset */ +#define GPTCR_FRR (1<<9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ +#define GPTCR_TEN (1) /* Timer enable */ + +static ulong timestamp; +static ulong lastinc; + +int timer_init(void) +{ + int i; + + /* setup GP Timer 1 */ + __raw_writel(GPTCR_SWR, &cur_gpt->control); + + /* We have no udelay by now */ + for (i = 0; i < 100; i++) + __raw_writel(0, &cur_gpt->control); + + __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ + + /* Freerun Mode, PERCLK1 input */ + i = __raw_readl(&cur_gpt->control); + __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); + reset_timer_masked(); + return 0; +} + +void reset_timer(void) +{ + reset_timer_masked(); +} + +void reset_timer_masked(void) +{ + ulong val = __raw_readl(&cur_gpt->counter); + lastinc = val / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ); + timestamp = 0; +} + +ulong get_timer_masked(void) +{ + ulong val = __raw_readl(&cur_gpt->counter); + val /= (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ); + if (val >= lastinc) + timestamp += (val - lastinc); + else + timestamp += ((0xFFFFFFFF / (CONFIG_SYS_MX5_CLK32 / CONFIG_SYS_HZ)) + - lastinc) + val; + lastinc = val; + return timestamp; +} + +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer(ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND preserve advance timestamp value */ +void __udelay(unsigned long usec) +{ + unsigned long now, start, tmo; + tmo = usec * (CONFIG_SYS_MX5_CLK32 / 1000) / 1000; + + if (!tmo) + tmo = 1; + + now = start = readl(&cur_gpt->counter); + + while ((now - start) < tmo) + now = readl(&cur_gpt->counter); + +} diff --git a/arch/arm/cpu/armv7/mx5/u-boot.lds b/arch/arm/cpu/armv7/mx5/u-boot.lds new file mode 100644 index 00000000000..55d6599b41c --- /dev/null +++ b/arch/arm/cpu/armv7/mx5/u-boot.lds @@ -0,0 +1,73 @@ +/* + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + arch/arm/cpu/armv7/start.o + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + + __got_start = .; + . = ALIGN(4); + .got : { *(.got) } + __got_end = .; + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/arch/arm/cpu/armv7/mx51/Makefile b/arch/arm/cpu/armv7/mx51/Makefile deleted file mode 100644 index 7cfaa2c1305..00000000000 --- a/arch/arm/cpu/armv7/mx51/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2009 Freescale Semiconductor, Inc. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = soc.o clock.o iomux.o timer.o speed.o -SOBJS = lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/arch/arm/cpu/armv7/mx51/clock.c b/arch/arm/cpu/armv7/mx51/clock.c deleted file mode 100644 index a27227de313..00000000000 --- a/arch/arm/cpu/armv7/mx51/clock.c +++ /dev/null @@ -1,294 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -enum pll_clocks { - PLL1_CLOCK = 0, - PLL2_CLOCK, - PLL3_CLOCK, - PLL_CLOCKS, -}; - -struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { - [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR, - [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR, - [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR, -}; - -struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - -/* - * Calculate the frequency of this pll. - */ -static u32 decode_pll(struct mxc_pll_reg *pll, u32 infreq) -{ - u32 mfi, mfn, mfd, pd; - - mfn = __raw_readl(&pll->mfn); - mfd = __raw_readl(&pll->mfd) + 1; - mfi = __raw_readl(&pll->op); - pd = (mfi & 0xF) + 1; - mfi = (mfi >> 4) & 0xF; - mfi = (mfi >= 5) ? mfi : 5; - - return ((4 * (infreq / 1000) * (mfi * mfd + mfn)) / (mfd * pd)) * 1000; -} - -/* - * Get mcu main rate - */ -u32 get_mcu_main_clk(void) -{ - u32 reg, freq; - - reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >> - MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); - return freq / (reg + 1); -} - -/* - * Get the rate of peripheral's root clock. - */ -static u32 get_periph_clk(void) -{ - u32 reg; - - reg = __raw_readl(&mxc_ccm->cbcdr); - if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL)) - return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); - reg = __raw_readl(&mxc_ccm->cbcmr); - switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> - MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { - case 0: - return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); - case 1: - return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); - default: - return 0; - } - /* NOTREACHED */ -} - -/* - * Get the rate of ipg clock. - */ -static u32 get_ipg_clk(void) -{ - u32 ahb_podf, ipg_podf; - - ahb_podf = __raw_readl(&mxc_ccm->cbcdr); - ipg_podf = (ahb_podf & MXC_CCM_CBCDR_IPG_PODF_MASK) >> - MXC_CCM_CBCDR_IPG_PODF_OFFSET; - ahb_podf = (ahb_podf & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET; - return get_periph_clk() / ((ahb_podf + 1) * (ipg_podf + 1)); -} - -/* - * Get the rate of ipg_per clock. - */ -static u32 get_ipg_per_clk(void) -{ - u32 pred1, pred2, podf; - - if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL) - return get_ipg_clk(); - /* Fixme: not handle what about lpm*/ - podf = __raw_readl(&mxc_ccm->cbcdr); - pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET; - pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> - MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET; - podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> - MXC_CCM_CBCDR_PERCLK_PODF_OFFSET; - - return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1)); -} - -/* - * Get the rate of uart clk. - */ -static u32 get_uart_clk(void) -{ - unsigned int freq, reg, pred, podf; - - reg = __raw_readl(&mxc_ccm->cscmr1); - switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >> - MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) { - case 0x0: - freq = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ); - break; - case 0x1: - freq = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_MX51_HCLK_FREQ); - break; - case 0x2: - freq = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_MX51_HCLK_FREQ); - break; - default: - return 66500000; - } - - reg = __raw_readl(&mxc_ccm->cscdr1); - - pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET; - - podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET; - freq /= (pred + 1) * (podf + 1); - - return freq; -} - -/* - * This function returns the low power audio clock. - */ -u32 get_lp_apm(void) -{ - u32 ret_val = 0; - u32 ccsr = __raw_readl(&mxc_ccm->ccsr); - - if (((ccsr >> 9) & 1) == 0) - ret_val = CONFIG_MX51_HCLK_FREQ; - else - ret_val = ((32768 * 1024)); - - return ret_val; -} - -/* - * get cspi clock rate. - */ -u32 imx_get_cspiclk(void) -{ - u32 ret_val = 0, pdf, pre_pdf, clk_sel; - u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); - u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2); - - pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \ - >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET; - pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \ - >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET; - clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \ - >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET; - - switch (clk_sel) { - case 0: - ret_val = decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case 1: - ret_val = decode_pll(mxc_plls[PLL2_CLOCK], - CONFIG_MX51_HCLK_FREQ) / - ((pre_pdf + 1) * (pdf + 1)); - break; - case 2: - ret_val = decode_pll(mxc_plls[PLL3_CLOCK], - CONFIG_MX51_HCLK_FREQ) / - ((pre_pdf + 1) * (pdf + 1)); - break; - default: - ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1)); - break; - } - - return ret_val; -} - -/* - * The API of get mxc clockes. - */ -unsigned int mxc_get_clock(enum mxc_clock clk) -{ - switch (clk) { - case MXC_ARM_CLK: - return get_mcu_main_clk(); - case MXC_AHB_CLK: - break; - case MXC_IPG_CLK: - return get_ipg_clk(); - case MXC_IPG_PERCLK: - return get_ipg_per_clk(); - case MXC_UART_CLK: - return get_uart_clk(); - case MXC_CSPI_CLK: - return imx_get_cspiclk(); - case MXC_FEC_CLK: - return decode_pll(mxc_plls[PLL1_CLOCK], - CONFIG_MX51_HCLK_FREQ); - default: - break; - } - return -1; -} - -u32 imx_get_uartclk(void) -{ - return get_uart_clk(); -} - - -u32 imx_get_fecclk(void) -{ - return mxc_get_clock(MXC_IPG_CLK); -} - -/* - * Dump some core clockes. - */ -int do_mx51_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 freq; - - freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll1: %dMHz\n", freq / 1000000); - freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll2: %dMHz\n", freq / 1000000); - freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_MX51_HCLK_FREQ); - printf("mx51 pll3: %dMHz\n", freq / 1000000); - printf("ipg clock : %dHz\n", mxc_get_clock(MXC_IPG_CLK)); - printf("ipg per clock : %dHz\n", mxc_get_clock(MXC_IPG_PERCLK)); - - return 0; -} - -/***************************************************/ - -U_BOOT_CMD( - clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx51_showclocks, - "display mx51 clocks\n", - "" -); diff --git a/arch/arm/cpu/armv7/mx51/iomux.c b/arch/arm/cpu/armv7/mx51/iomux.c deleted file mode 100644 index 62b2954be99..00000000000 --- a/arch/arm/cpu/armv7/mx51/iomux.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include - -/* IOMUX register (base) addresses */ -enum iomux_reg_addr { - IOMUXGPR0 = IOMUXC_BASE_ADDR, - IOMUXGPR1 = IOMUXC_BASE_ADDR + 0x004, - IOMUXSW_MUX_CTL = IOMUXC_BASE_ADDR, - IOMUXSW_MUX_END = IOMUXC_BASE_ADDR + MUX_I_END, - IOMUXSW_PAD_CTL = IOMUXC_BASE_ADDR + PAD_I_START, - IOMUXSW_INPUT_CTL = IOMUXC_BASE_ADDR, -}; - -#define MUX_PIN_NUM_MAX (((MUX_I_END - MUX_I_START) >> 2) + 1) - -/* Get the iomux register address of this pin */ -static inline u32 get_mux_reg(iomux_pin_name_t pin) -{ - u32 mux_reg = PIN_TO_IOMUX_MUX(pin); - - if (is_soc_rev(CHIP_REV_2_0) < 0) { - /* - * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. - */ - if ((pin == MX51_PIN_NANDF_RB5) || - (pin == MX51_PIN_NANDF_RB6) || - (pin == MX51_PIN_NANDF_RB7)) - ; /* Do nothing */ - else if (mux_reg >= 0x2FC) - mux_reg += 8; - else if (mux_reg >= 0x130) - mux_reg += 0xC; - } - mux_reg += IOMUXSW_MUX_CTL; - return mux_reg; -} - -/* Get the pad register address of this pin */ -static inline u32 get_pad_reg(iomux_pin_name_t pin) -{ - u32 pad_reg = PIN_TO_IOMUX_PAD(pin); - - if (is_soc_rev(CHIP_REV_2_0) < 0) { - /* - * Fixup register address: - * i.MX51 TO1 has offset with the register - * which is define as TO2. - */ - if ((pin == MX51_PIN_NANDF_RB5) || - (pin == MX51_PIN_NANDF_RB6) || - (pin == MX51_PIN_NANDF_RB7)) - ; /* Do nothing */ - else if (pad_reg == 0x4D0 - PAD_I_START) - pad_reg += 0x4C; - else if (pad_reg == 0x860 - PAD_I_START) - pad_reg += 0x9C; - else if (pad_reg >= 0x804 - PAD_I_START) - pad_reg += 0xB0; - else if (pad_reg >= 0x7FC - PAD_I_START) - pad_reg += 0xB4; - else if (pad_reg >= 0x4E4 - PAD_I_START) - pad_reg += 0xCC; - else - pad_reg += 8; - } - pad_reg += IOMUXSW_PAD_CTL; - return pad_reg; -} - -/* Get the last iomux register address */ -static inline u32 get_mux_end(void) -{ - if (is_soc_rev(CHIP_REV_2_0) < 0) - return IOMUXC_BASE_ADDR + (0x3F8 - 4); - else - return IOMUXC_BASE_ADDR + (0x3F0 - 4); -} - -/* - * This function is used to configure a pin through the IOMUX module. - * @param pin a pin number as defined in iomux_pin_name_t - * @param cfg an output function as defined in iomux_pin_cfg_t - * - * @return 0 if successful; Non-zero otherwise - */ -static void iomux_config_mux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) -{ - u32 mux_reg = get_mux_reg(pin); - - if ((mux_reg > get_mux_end()) || (mux_reg < IOMUXSW_MUX_CTL)) - return ; - if (cfg == IOMUX_CONFIG_GPIO) - writel(PIN_TO_ALT_GPIO(pin), mux_reg); - else - writel(cfg, mux_reg); -} - -/* - * Request ownership for an IO pin. This function has to be the first one - * being called before that pin is used. The caller has to check the - * return value to make sure it returns 0. - * - * @param pin a name defined by iomux_pin_name_t - * @param cfg an input function as defined in iomux_pin_cfg_t - * - */ -void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) -{ - iomux_config_mux(pin, cfg); -} - -/* - * Release ownership for an IO pin - * - * @param pin a name defined by iomux_pin_name_t - * @param cfg an input function as defined in iomux_pin_cfg_t - */ -void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t cfg) -{ -} - -/* - * This function configures the pad value for a IOMUX pin. - * - * @param pin a pin number as defined in iomux_pin_name_t - * @param config the ORed value of elements defined in iomux_pad_config_t - */ -void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config) -{ - u32 pad_reg = get_pad_reg(pin); - writel(config, pad_reg); -} - -unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin) -{ - u32 pad_reg = get_pad_reg(pin); - return readl(pad_reg); -} diff --git a/arch/arm/cpu/armv7/mx51/lowlevel_init.S b/arch/arm/cpu/armv7/mx51/lowlevel_init.S deleted file mode 100644 index 783c81f72a7..00000000000 --- a/arch/arm/cpu/armv7/mx51/lowlevel_init.S +++ /dev/null @@ -1,291 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* - * L2CC Cache setup/invalidation/disable - */ -.macro init_l2cc - /* explicitly disable L2 cache */ - mrc 15, 0, r0, c1, c0, 1 - bic r0, r0, #0x2 - mcr 15, 0, r0, c1, c0, 1 - - /* reconfigure L2 cache aux control reg */ - mov r0, #0xC0 /* tag RAM */ - add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ - - cmp r3, #0x10 /* r3 contains the silicon rev */ - - /* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) - - mcr 15, 1, r0, c9, c0, 2 -.endm /* init_l2cc */ - -/* AIPS setup - Only setup MPROTx registers. - * The PACR default values are good.*/ -.macro init_aips - /* - * Set all MPROTx to be non-bufferable, trusted for R/W, - * not forced to user-mode. - */ - ldr r0, =AIPS1_BASE_ADDR - ldr r1, =0x77777777 - str r1, [r0, #0x0] - str r1, [r0, #0x4] - ldr r0, =AIPS2_BASE_ADDR - str r1, [r0, #0x0] - str r1, [r0, #0x4] - /* - * Clear the on and off peripheral modules Supervisor Protect bit - * for SDMA to access them. Did not change the AIPS control registers - * (offset 0x20) access type - */ -.endm /* init_aips */ - -/* M4IF setup */ -.macro init_m4if - /* VPU and IPU given higher priority (0x4) - * IPU accesses with ID=0x1 given highest priority (=0xA) - */ - ldr r0, =M4IF_BASE_ADDR - - ldr r1, =0x00000203 - str r1, [r0, #0x40] - - ldr r1, =0x0 - str r1, [r0, #0x44] - - ldr r1, =0x00120125 - str r1, [r0, #0x9C] - - ldr r1, =0x001901A3 - str r1, [r0, #0x48] - -.endm /* init_m4if */ - -.macro setup_pll pll, freq - ldr r2, =\pll - ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */ - mov r1, #0x2 - str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */ - - str r3, [r2, #PLL_DP_OP] - str r3, [r2, #PLL_DP_HFS_OP] - - str r4, [r2, #PLL_DP_MFD] - str r4, [r2, #PLL_DP_HFS_MFD] - - str r5, [r2, #PLL_DP_MFN] - str r5, [r2, #PLL_DP_HFS_MFN] - - ldr r1, =0x00001232 - str r1, [r2, #PLL_DP_CTL] -1: ldr r1, [r2, #PLL_DP_CTL] - ands r1, r1, #0x1 - beq 1b -.endm - -.macro init_clock - ldr r0, =CCM_BASE_ADDR - - /* Gate of clocks to the peripherals first */ - ldr r1, =0x3FFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - ldr r1, =0x0 - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - - ldr r1, =0x00030000 - str r1, [r0, #CLKCTL_CCGR4] - ldr r1, =0x00FFF030 - str r1, [r0, #CLKCTL_CCGR5] - ldr r1, =0x00000300 - str r1, [r0, #CLKCTL_CCGR6] - - /* Disable IPU and HSC dividers */ - mov r1, #0x60000 - str r1, [r0, #CLKCTL_CCDR] - - /* Make sure to switch the DDR away from PLL 1 */ - ldr r1, =0x19239145 - str r1, [r0, #CLKCTL_CBCDR] - /* make sure divider effective */ -1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b - - /* Switch ARM to step clock */ - mov r1, #0x4 - str r1, [r0, #CLKCTL_CCSR] - mov r3, #DP_OP_800 - mov r4, #DP_MFD_800 - mov r5, #DP_MFN_800 - setup_pll PLL1_BASE_ADDR - - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL3_BASE_ADDR - - /* Switch peripheral to PLL 3 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x000010C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL - str r1, [r0, #CLKCTL_CBCMR] - ldr r1, =0x13239145 - str r1, [r0, #CLKCTL_CBCDR] - mov r3, #DP_OP_665 - mov r4, #DP_MFD_665 - mov r5, #DP_MFN_665 - setup_pll PLL2_BASE_ADDR - - /* Switch peripheral to PLL2 */ - ldr r0, =CCM_BASE_ADDR - ldr r1, =0x19239145 - str r1, [r0, #CLKCTL_CBCDR] - ldr r1, =0x000020C0 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL - str r1, [r0, #CLKCTL_CBCMR] - - mov r3, #DP_OP_216 - mov r4, #DP_MFD_216 - mov r5, #DP_MFN_216 - setup_pll PLL3_BASE_ADDR - - - /* Set the platform clock dividers */ - ldr r0, =ARM_BASE_ADDR - ldr r1, =0x00000725 - str r1, [r0, #0x14] - - ldr r0, =CCM_BASE_ADDR - - /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ - ldr r1, =0x0 - ldr r3, [r1, #ROM_SI_REV] - cmp r3, #0x10 - movls r1, #0x1 - movhi r1, #0 - str r1, [r0, #CLKCTL_CACRR] - - /* Switch ARM back to PLL 1 */ - mov r1, #0 - str r1, [r0, #CLKCTL_CCSR] - - /* setup the rest */ - /* Use lp_apm (24MHz) source for perclk */ - ldr r1, =0x000020C2 - orr r1,r1,#CONFIG_SYS_DDR_CLKSEL - str r1, [r0, #CLKCTL_CBCMR] - /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ - ldr r1, =CONFIG_SYS_CLKTL_CBCDR - str r1, [r0, #CLKCTL_CBCDR] - - /* Restore the default values in the Gate registers */ - ldr r1, =0xFFFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - str r1, [r0, #CLKCTL_CCGR1] - str r1, [r0, #CLKCTL_CCGR2] - str r1, [r0, #CLKCTL_CCGR3] - str r1, [r0, #CLKCTL_CCGR4] - str r1, [r0, #CLKCTL_CCGR5] - str r1, [r0, #CLKCTL_CCGR6] - - /* Use PLL 2 for UART's, get 66.5MHz from it */ - ldr r1, =0xA5A2A020 - str r1, [r0, #CLKCTL_CSCMR1] - ldr r1, =0x00C30321 - str r1, [r0, #CLKCTL_CSCDR1] - - /* make sure divider effective */ -1: ldr r1, [r0, #CLKCTL_CDHIPR] - cmp r1, #0x0 - bne 1b - - mov r1, #0x0 - str r1, [r0, #CLKCTL_CCDR] - - /* for cko - for ARM div by 8 */ - mov r1, #0x000A0000 - add r1, r1, #0x00000F0 - str r1, [r0, #CLKCTL_CCOSR] -.endm - -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - -.section ".text.init", "x" - -.globl lowlevel_init -lowlevel_init: - ldr r0, =GPIO1_BASE_ADDR - ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) - str r1, [r0, #0x0] - ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) - str r1, [r0, #0x4] - -#ifdef ENABLE_IMPRECISE_ABORT - mrs r1, spsr /* save old spsr */ - mrs r0, cpsr /* read out the cpsr */ - bic r0, r0, #0x100 /* clear the A bit */ - msr spsr, r0 /* update spsr */ - add lr, pc, #0x8 /* update lr */ - movs pc, lr /* update cpsr */ - nop - nop - nop - nop - msr spsr, r1 /* restore old spsr */ -#endif - - init_l2cc - - init_aips - - init_m4if - - init_clock - - /* r12 saved upper lr*/ - mov pc,lr - -/* Board level setting value */ -DDR_PERCHARGE_CMD: .word 0x04008008 -DDR_REFRESH_CMD: .word 0x00008010 -DDR_LMR1_W: .word 0x00338018 -DDR_LMR_CMD: .word 0xB2220000 -DDR_TIMING_W: .word 0xB02567A9 -DDR_MISC_W: .word 0x000A0104 diff --git a/arch/arm/cpu/armv7/mx51/soc.c b/arch/arm/cpu/armv7/mx51/soc.c deleted file mode 100644 index f22ebe96c86..00000000000 --- a/arch/arm/cpu/armv7/mx51/soc.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -#ifdef CONFIG_FSL_ESDHC -#include -#endif - -u32 get_cpu_rev(void) -{ - int reg; - int system_rev; - - reg = __raw_readl(ROM_SI_REV); - switch (reg) { - case 0x02: - system_rev = 0x51000 | CHIP_REV_1_1; - break; - case 0x10: - if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) - system_rev = 0x51000 | CHIP_REV_2_5; - else - system_rev = 0x51000 | CHIP_REV_2_0; - break; - case 0x20: - system_rev = 0x51000 | CHIP_REV_3_0; - break; - return system_rev; - default: - system_rev = 0x51000 | CHIP_REV_1_0; - break; - } - return system_rev; -} - - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 cpurev; - - cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX51 family rev%d.%d at %d MHz\n", - (cpurev & 0xF0) >> 4, - (cpurev & 0x0F) >> 4, - mxc_get_clock(MXC_ARM_CLK) / 1000000); - return 0; -} -#endif - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -#if defined(CONFIG_FEC_MXC) -extern int fecmxc_initialize(bd_t *bis); -#endif - -int cpu_eth_init(bd_t *bis) -{ - int rc = -ENODEV; - -#if defined(CONFIG_FEC_MXC) - rc = fecmxc_initialize(bis); -#endif - - return rc; -} - -/* - * Initializes on-chip MMC controllers. - * to override, implement board_mmc_init() - */ -int cpu_mmc_init(bd_t *bis) -{ -#ifdef CONFIG_FSL_ESDHC - return fsl_esdhc_mmc_init(bis); -#else - return 0; -#endif -} - - -void reset_cpu(ulong addr) -{ - __raw_writew(4, WDOG1_BASE_ADDR); -} diff --git a/arch/arm/cpu/armv7/mx51/speed.c b/arch/arm/cpu/armv7/mx51/speed.c deleted file mode 100644 index a444def7eb8..00000000000 --- a/arch/arm/cpu/armv7/mx51/speed.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * (C) Copyright 2000-2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -int get_clocks(void) -{ - DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_FSL_ESDHC - gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK); -#endif - return 0; -} diff --git a/arch/arm/cpu/armv7/mx51/timer.c b/arch/arm/cpu/armv7/mx51/timer.c deleted file mode 100644 index 110edbfa85e..00000000000 --- a/arch/arm/cpu/armv7/mx51/timer.c +++ /dev/null @@ -1,119 +0,0 @@ -/* - * (C) Copyright 2007 - * Sascha Hauer, Pengutronix - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include - -/* General purpose timers registers */ -struct mxc_gpt { - unsigned int control; - unsigned int prescaler; - unsigned int status; - unsigned int nouse[6]; - unsigned int counter; -}; - -static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR; - -/* General purpose timers bitfields */ -#define GPTCR_SWR (1<<15) /* Software reset */ -#define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ -#define GPTCR_TEN (1) /* Timer enable */ - -static ulong timestamp; -static ulong lastinc; - -int timer_init(void) -{ - int i; - - /* setup GP Timer 1 */ - __raw_writel(GPTCR_SWR, &cur_gpt->control); - - /* We have no udelay by now */ - for (i = 0; i < 100; i++) - __raw_writel(0, &cur_gpt->control); - - __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */ - - /* Freerun Mode, PERCLK1 input */ - i = __raw_readl(&cur_gpt->control); - __raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control); - reset_timer_masked(); - return 0; -} - -void reset_timer(void) -{ - reset_timer_masked(); -} - -void reset_timer_masked(void) -{ - ulong val = __raw_readl(&cur_gpt->counter); - lastinc = val / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); - timestamp = 0; -} - -ulong get_timer_masked(void) -{ - ulong val = __raw_readl(&cur_gpt->counter); - val /= (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ); - if (val >= lastinc) - timestamp += (val - lastinc); - else - timestamp += ((0xFFFFFFFF / (CONFIG_MX51_CLK32 / CONFIG_SYS_HZ)) - - lastinc) + val; - lastinc = val; - return timestamp; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void set_timer(ulong t) -{ - timestamp = t; -} - -/* delay x useconds AND preserve advance timestamp value */ -void __udelay(unsigned long usec) -{ - unsigned long now, start, tmo; - tmo = usec * (CONFIG_MX51_CLK32 / 1000) / 1000; - - if (!tmo) - tmo = 1; - - now = start = readl(&cur_gpt->counter); - - while ((now - start) < tmo) - now = readl(&cur_gpt->counter); - -} diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds deleted file mode 100644 index 55d6599b41c..00000000000 --- a/arch/arm/cpu/armv7/mx51/u-boot.lds +++ /dev/null @@ -1,73 +0,0 @@ -/* - * January 2004 - Changed to support H4 device - * Copyright (c) 2004 Texas Instruments - * - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - arch/arm/cpu/armv7/start.o - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { - *(.data) - __datarel_start = .; - *(.data.rel) - __datarelrolocal_start = .; - *(.data.rel.ro.local) - __datarellocal_start = .; - *(.data.rel.local) - __datarelro_start = .; - *(.data.rel.ro) - } - - __got_start = .; - . = ALIGN(4); - .got : { *(.got) } - __got_end = .; - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/arch/arm/include/asm/arch-mx5/asm-offsets.h b/arch/arm/include/asm/arch-mx5/asm-offsets.h new file mode 100644 index 00000000000..afd27283af1 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/asm-offsets.h @@ -0,0 +1,50 @@ +/* + * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S + * + * These should be auto-generated + */ +/* CCM */ +#define CLKCTL_CCR 0x00 +#define CLKCTL_CCDR 0x04 +#define CLKCTL_CSR 0x08 +#define CLKCTL_CCSR 0x0C +#define CLKCTL_CACRR 0x10 +#define CLKCTL_CBCDR 0x14 +#define CLKCTL_CBCMR 0x18 +#define CLKCTL_CSCMR1 0x1C +#define CLKCTL_CSCMR2 0x20 +#define CLKCTL_CSCDR1 0x24 +#define CLKCTL_CS1CDR 0x28 +#define CLKCTL_CS2CDR 0x2C +#define CLKCTL_CDCDR 0x30 +#define CLKCTL_CHSCCDR 0x34 +#define CLKCTL_CSCDR2 0x38 +#define CLKCTL_CSCDR3 0x3C +#define CLKCTL_CSCDR4 0x40 +#define CLKCTL_CWDR 0x44 +#define CLKCTL_CDHIPR 0x48 +#define CLKCTL_CDCR 0x4C +#define CLKCTL_CTOR 0x50 +#define CLKCTL_CLPCR 0x54 +#define CLKCTL_CISR 0x58 +#define CLKCTL_CIMR 0x5C +#define CLKCTL_CCOSR 0x60 +#define CLKCTL_CGPR 0x64 +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6C +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7C +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CMEOR 0x84 + +/* DPLL */ +#define PLL_DP_CTL 0x00 +#define PLL_DP_CONFIG 0x04 +#define PLL_DP_OP 0x08 +#define PLL_DP_MFD 0x0C +#define PLL_DP_MFN 0x10 +#define PLL_DP_HFS_OP 0x1C +#define PLL_DP_HFS_MFD 0x20 +#define PLL_DP_HFS_MFN 0x24 diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h new file mode 100644 index 00000000000..1f8a537a56b --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -0,0 +1,43 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK_H +#define __ASM_ARCH_CLOCK_H + +enum mxc_clock { + MXC_ARM_CLK = 0, + MXC_AHB_CLK, + MXC_IPG_CLK, + MXC_IPG_PERCLK, + MXC_UART_CLK, + MXC_CSPI_CLK, + MXC_FEC_CLK, +}; + +unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); + +u32 imx_get_uartclk(void); +u32 imx_get_fecclk(void); +unsigned int mxc_get_clock(enum mxc_clock clk); + +#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h new file mode 100644 index 00000000000..14aa231a5b0 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ +#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ + +#define MXC_CCM_BASE CCM_BASE_ADDR + +/* DPLL register mapping structure */ +struct mxc_pll_reg { + u32 ctrl; + u32 config; + u32 op; + u32 mfd; + u32 mfn; + u32 mfn_minus; + u32 mfn_plus; + u32 hfs_op; + u32 hfs_mfd; + u32 hfs_mfn; + u32 mfn_togc; + u32 destat; +}; + +/* Register maping of CCM*/ +struct mxc_ccm_reg { + u32 ccr; /* 0x0000 */ + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; /* 0x0010*/ + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; /* 0x0020 */ + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; /* 0x0030 */ + u32 chscdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; /* 0x0040 */ + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; /* 0x0050 */ + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; /* 0x0060 */ + u32 cgpr; + u32 CCGR0; + u32 CCGR1; + u32 CCGR2; /* 0x0070 */ + u32 CCGR3; + u32 CCGR4; + u32 CCGR5; + u32 CCGR6; /* 0x0080 */ + u32 cmeor; +}; + +/* Define the bits in register CACRR */ +#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 +#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 + +/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) +#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 +#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 +#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 +#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 +#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) +#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 +#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) +#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 +#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 +#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 + +/* Define the bits in register CSCMR1 */ +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 +#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 +#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 +#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) +#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 +#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 +#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 +#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) +#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 +#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) +#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 +#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) +#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 +#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 +#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) +#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 + +/* Define the bits in register CSCDR2 */ +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 +#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 +#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 +#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 +#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F + +/* Define the bits in register CBCMR */ +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 +#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 +#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 +#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 +#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) +#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 +#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) +#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) + +/* Define the bits in register CSCDR1 */ +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 +#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 +#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 +#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 +#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 + +#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h new file mode 100644 index 00000000000..3ddda401f31 --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -0,0 +1,279 @@ +/* + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MXC_MX51_H__ +#define __ASM_ARCH_MXC_MX51_H__ + +/* + * IRAM + */ +#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ +/* + * Graphics Memory of GPU + */ +#define GPU_BASE_ADDR 0x20000000 +#define GPU_CTRL_BASE_ADDR 0x30000000 +#define IPU_CTRL_BASE_ADDR 0x40000000 +/* + * Debug + */ +#define DEBUG_BASE_ADDR 0x60000000 +#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) +#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) +#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) +#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) +#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) +#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) +#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) +#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) + +/* + * SPBA global module enabled #0 + */ +#define SPBA0_BASE_ADDR 0x70000000 + +#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) +#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) +#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) +#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) +#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) +#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) +#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) +#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) +#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) +#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) + +/* + * AIPS 1 + */ +#define AIPS1_BASE_ADDR 0x73F00000 + +#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) +#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) +#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) +#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) +#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) +#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) +#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) +#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) +#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) +#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) +#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) +#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) +#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) +#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) +#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) +#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) +#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) +#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) +#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) +#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) + +/* + * AIPS 2 + */ +#define AIPS2_BASE_ADDR 0x83F00000 + +#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) +#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) +#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) +#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) +#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) +#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) +#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) +#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) +#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) +#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) +#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) +#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) +#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) +#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) +#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) +#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) +#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) +#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) +#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) +#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) +#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) +#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) +#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) +#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) +#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) +#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) +#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) +#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) +#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) + +#define TZIC_BASE_ADDR 0x8FFFC000 + +/* + * Memory regions and CS + */ +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define CS0_BASE_ADDR 0xB0000000 +#define CS1_BASE_ADDR 0xB8000000 +#define CS2_BASE_ADDR 0xC0000000 +#define CS3_BASE_ADDR 0xC8000000 +#define CS4_BASE_ADDR 0xCC000000 +#define CS5_BASE_ADDR 0xCE000000 + +/* + * NFC + */ +#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ + +/*! + * Number of GPIO port as defined in the IC Spec + */ +#define GPIO_PORT_NUM 4 +/*! + * Number of GPIO pins per port + */ +#define GPIO_NUM_PIN 32 + +#define IIM_SREV 0x24 +#define ROM_SI_REV 0x48 + +#define NFC_BUF_SIZE 0x1000 + +/* M4IF */ +#define M4IF_FBPM0 0x40 +#define M4IF_FIDBP 0x48 + +/* Assuming 24MHz input clock with doubler ON */ +/* MFI PDF */ +#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_850 (48 - 1) +#define DP_MFN_850 41 + +#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) +#define DP_MFD_800 (3 - 1) +#define DP_MFN_800 1 + +#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) +#define DP_MFD_700 (24 - 1) +#define DP_MFN_700 7 + +#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_665 (96 - 1) +#define DP_MFN_665 89 + +#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_532 (24 - 1) +#define DP_MFN_532 13 + +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) +#define DP_MFD_216 (4 - 1) +#define DP_MFN_216 3 + +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 + +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 + +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) +#include + +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + +struct clkctl { + u32 ccr; + u32 ccdr; + u32 csr; + u32 ccsr; + u32 cacrr; + u32 cbcdr; + u32 cbcmr; + u32 cscmr1; + u32 cscmr2; + u32 cscdr1; + u32 cs1cdr; + u32 cs2cdr; + u32 cdcdr; + u32 chsccdr; + u32 cscdr2; + u32 cscdr3; + u32 cscdr4; + u32 cwdr; + u32 cdhipr; + u32 cdcr; + u32 ctor; + u32 clpcr; + u32 cisr; + u32 cimr; + u32 ccosr; + u32 cgpr; + u32 ccgr0; + u32 ccgr1; + u32 ccgr2; + u32 ccgr3; + u32 ccgr4; + u32 ccgr5; + u32 ccgr6; + u32 cmeor; +}; + +/* WEIM registers */ +struct weim { + u32 csgcr1; + u32 csgcr2; + u32 csrcr1; + u32 csrcr2; + u32 cswcr1; + u32 cswcr2; +}; + +/* GPIO Registers */ +struct gpio_regs { + u32 gpio_dr; + u32 gpio_dir; + u32 gpio_psr; +}; + +/* System Reset Controller (SRC) */ +struct src { + u32 scr; + u32 sbmr; + u32 srsr; + u32 reserved1[2]; + u32 sisr; + u32 simr; +}; +#endif /* __ASSEMBLER__*/ + +#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/iomux.h b/arch/arm/include/asm/arch-mx5/iomux.h new file mode 100644 index 00000000000..0d91a24c84e --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/iomux.h @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __MACH_MX5_IOMUX_H__ +#define __MACH_MX5_IOMUX_H__ + +#include +#include +#include +#include + +typedef unsigned int iomux_pin_name_t; + +/* various IOMUX output functions */ +typedef enum iomux_config { + IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ + IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ + IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ + IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ + IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ + IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ + IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ + IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ + IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ + IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ +} iomux_pin_cfg_t; + +/* various IOMUX pad functions */ +typedef enum iomux_pad_config { + PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */ + PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */ + PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */ + PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */ + PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */ + PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */ + PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */ + PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */ + PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */ + PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */ + PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */ + PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */ + PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */ + PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */ + PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */ + PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */ + PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */ + PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ + PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ + PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ + PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ + PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ +} iomux_pad_config_t; + +/* various IOMUX input select register index */ +typedef enum iomux_input_select { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, + MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, + /* TO2 */ + MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, + MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, + MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_CRS_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, + /* TO2 */ + MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, + /* TO2 */ + MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, + MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, + + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, + MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, + MUX_INPUT_NUM_MUX, +} iomux_input_select_t; + +/* various IOMUX input functions */ +typedef enum iomux_input_config { + INPUT_CTL_PATH0 = 0x0, + INPUT_CTL_PATH1, + INPUT_CTL_PATH2, + INPUT_CTL_PATH3, + INPUT_CTL_PATH4, + INPUT_CTL_PATH5, + INPUT_CTL_PATH6, + INPUT_CTL_PATH7, +} iomux_input_config_t; + +void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); +void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); +void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); +unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); +void mxc_iomux_set_input(iomux_input_select_t input, u32 config); + +#endif /* __MACH_MX5_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/mx5x_pins.h b/arch/arm/include/asm/arch-mx5/mx5x_pins.h new file mode 100644 index 00000000000..a564fce982b --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/mx5x_pins.h @@ -0,0 +1,418 @@ +/* + * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_MX5_MX5X_PINS_H__ +#define __ASM_ARCH_MX5_MX5X_PINS_H__ + +#ifndef __ASSEMBLY__ + +/* + * In order to identify pins more effectively, each mux-controlled pin's + * enumerated value is constructed in the following way: + * + * ------------------------------------------------------------------- + * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 + * ------------------------------------------------------------------- + * IO_P | IO_I | GPIO_I | PAD_I | MUX_I + * ------------------------------------------------------------------- + * + * Bit 0 to 9 contains MUX_I used to identify the register + * offset (0-based. base is IOMUX_module_base) defined in the Section + * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The + * similar field definitions are used for the pad control register. + * The IOMUX controller can be split in two parts. At the begeinning, + * there is the register definitions for the multiplexing each pin. + * Then there is a set of registers (PAD_I) to configure each pin + * (pullup, pulldown, etc). + * PAD_I defines the offset of the pad register for each pin. + * GPIO_I defines, if available, the number of gpio that can be + * connected to that pad + * IO_I defines the multiplexer mode required to set the pad in gpio mode + * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs + * + * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: + * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) + * It means the mux control register is at register offset 0x28. The pad control + * register offset is: 0x250 and also occupy the least significant bits + * within the register. + */ + +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * MUX control register offset + */ +#define MUX_I 0 +/*! + * Starting bit position within each entry of \b iomux_pins to represent the + * PAD control register offset + */ +#define PAD_I 10 +/*! + * Starting bit position within each entry of \b iomux_pins to represent which + * mux mode is for GPIO (0-based) + */ +#define GPIO_I 21 + +#define MUX_IO_P 29 +#define MUX_IO_I 24 +#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ + GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ + ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) +#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) +#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) +#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) + +#define NON_GPIO_PORT 0x7 +#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) +#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) +#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) + +#define NON_MUX_I PIN_TO_MUX_MASK +#define MUX_I_START 0x001C +#define PAD_I_START 0x3F0 +#define INPUT_CTL_START 0x8C4 +#define INPUT_CTL_START_TO1 0x928 +#define MUX_I_END (PAD_I_START - 4) + +#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ + _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) + +#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) +#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) +#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) +#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) + +/* + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), + MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), + MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), + MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), + MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), + MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), + MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), + MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), + MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), + MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), + MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), + MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), + MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), + MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), + MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), + MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), + MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), + MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), + MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), + MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), + MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), + MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), + MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), + MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), + MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), + MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), + MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), + MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), + MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), + MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), + MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), + MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), + MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), + MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), + MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), + MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), + MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), + MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), + MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), + MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), + MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), + MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), + MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), + MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), + MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), + MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), + MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), + MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), + MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), + MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), + MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), + MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), + MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), + MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), + MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), + MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), + MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), + MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), + MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), + MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), + MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), + MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), + MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), + MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), + MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), + MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), + MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), + MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), + MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), + MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, + MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), + MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), + MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), + MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), + MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), + MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), + MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), + MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), + MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), + MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), + MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), + MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), + MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), + MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), + MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), + MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), + MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), + MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), + MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), + MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), + MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), + MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), + MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), + MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), + MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), + MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), + MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), + MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), + MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), + MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), + MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), + MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), + MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), + MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), + MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), + MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), + MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), + MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), + MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), + MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), + MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), + MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), + MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), + MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), + MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), + MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), + MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), + MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), + MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), + MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), + MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), + MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), + MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), + MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), + MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), + MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), + MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), + MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), + MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), + MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), + MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), + MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), + MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), + MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), + MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), + MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), + MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), + MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), + MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), + MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), + MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), + MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), + MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), + MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), + MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), + MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), + MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), + MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), + MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), + MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), + MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), + MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), + MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), + MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), + MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), + MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), + MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), + MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), + MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), + MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), + MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), + MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), + MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), + MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), + MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), + MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), + MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), + MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), + MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), + MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), + MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), + MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), + MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), + MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), + MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), + MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), + MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), + MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), + MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), + MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), + MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), + MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), + MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), + MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), + MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), + MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), + MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), + MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), + MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), + MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), + MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), + MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), + MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), + MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), + MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), + MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), + MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), + MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), + MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), + MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), + MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), + MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), + MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), + MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), + MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), + MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), + MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), + MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), + MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), + MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), + MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), + MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), + MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), + MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), + MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), + MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), + MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), + MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), + MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), + MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), + MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), + MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), + MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), + MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), + MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), + MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), + MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), + MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), + MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), + MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), + MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), + MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), + MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), + MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), + MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), + MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), + MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), + MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), + MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), + MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), + MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), + MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), + MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), + MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), + MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), + MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), + MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), + MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), + MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), + MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), + MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), + MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), + + /* The following are PADS used for drive strength */ + + MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), + MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), + MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), + MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), + MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), + MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), + MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), + MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), + MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), + MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), + MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), + MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), + MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), + MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), + MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), + MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), + MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), + MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), + MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), + MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), + MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), + MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), + MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), + MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), + MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), + MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), + MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), + MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), + MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), + MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), + MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), + MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), + MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), + MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), + MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), + MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), + MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), + MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), + MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), + MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), + MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MX5_MX5X_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h new file mode 100644 index 00000000000..f687503cada --- /dev/null +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2009 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +u32 get_cpu_rev(void); +#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) +void sdelay(unsigned long); + +#endif diff --git a/arch/arm/include/asm/arch-mx51/asm-offsets.h b/arch/arm/include/asm/arch-mx51/asm-offsets.h deleted file mode 100644 index afd27283af1..00000000000 --- a/arch/arm/include/asm/arch-mx51/asm-offsets.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * needed for arch/arm/cpu/armv7/mx51/lowlevel_init.S - * - * These should be auto-generated - */ -/* CCM */ -#define CLKCTL_CCR 0x00 -#define CLKCTL_CCDR 0x04 -#define CLKCTL_CSR 0x08 -#define CLKCTL_CCSR 0x0C -#define CLKCTL_CACRR 0x10 -#define CLKCTL_CBCDR 0x14 -#define CLKCTL_CBCMR 0x18 -#define CLKCTL_CSCMR1 0x1C -#define CLKCTL_CSCMR2 0x20 -#define CLKCTL_CSCDR1 0x24 -#define CLKCTL_CS1CDR 0x28 -#define CLKCTL_CS2CDR 0x2C -#define CLKCTL_CDCDR 0x30 -#define CLKCTL_CHSCCDR 0x34 -#define CLKCTL_CSCDR2 0x38 -#define CLKCTL_CSCDR3 0x3C -#define CLKCTL_CSCDR4 0x40 -#define CLKCTL_CWDR 0x44 -#define CLKCTL_CDHIPR 0x48 -#define CLKCTL_CDCR 0x4C -#define CLKCTL_CTOR 0x50 -#define CLKCTL_CLPCR 0x54 -#define CLKCTL_CISR 0x58 -#define CLKCTL_CIMR 0x5C -#define CLKCTL_CCOSR 0x60 -#define CLKCTL_CGPR 0x64 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6C -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7C -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CMEOR 0x84 - -/* DPLL */ -#define PLL_DP_CTL 0x00 -#define PLL_DP_CONFIG 0x04 -#define PLL_DP_OP 0x08 -#define PLL_DP_MFD 0x0C -#define PLL_DP_MFN 0x10 -#define PLL_DP_HFS_OP 0x1C -#define PLL_DP_HFS_MFD 0x20 -#define PLL_DP_HFS_MFN 0x24 diff --git a/arch/arm/include/asm/arch-mx51/clock.h b/arch/arm/include/asm/arch-mx51/clock.h deleted file mode 100644 index 1f8a537a56b..00000000000 --- a/arch/arm/include/asm/arch-mx51/clock.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_IPG_PERCLK, - MXC_UART_CLK, - MXC_CSPI_CLK, - MXC_FEC_CLK, -}; - -unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); - -u32 imx_get_uartclk(void); -u32 imx_get_fecclk(void); -unsigned int mxc_get_clock(enum mxc_clock clk); - -#endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx51/crm_regs.h b/arch/arm/include/asm/arch-mx51/crm_regs.h deleted file mode 100644 index 14aa231a5b0..00000000000 --- a/arch/arm/include/asm/arch-mx51/crm_regs.h +++ /dev/null @@ -1,192 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -#define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ - -#define MXC_CCM_BASE CCM_BASE_ADDR - -/* DPLL register mapping structure */ -struct mxc_pll_reg { - u32 ctrl; - u32 config; - u32 op; - u32 mfd; - u32 mfn; - u32 mfn_minus; - u32 mfn_plus; - u32 hfs_op; - u32 hfs_mfd; - u32 hfs_mfn; - u32 mfn_togc; - u32 destat; -}; - -/* Register maping of CCM*/ -struct mxc_ccm_reg { - u32 ccr; /* 0x0000 */ - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; /* 0x0010*/ - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; /* 0x0020 */ - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; /* 0x0030 */ - u32 chscdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; /* 0x0040 */ - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; /* 0x0050 */ - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; /* 0x0060 */ - u32 cgpr; - u32 CCGR0; - u32 CCGR1; - u32 CCGR2; /* 0x0070 */ - u32 CCGR3; - u32 CCGR4; - u32 CCGR5; - u32 CCGR6; /* 0x0080 */ - u32 cmeor; -}; - -/* Define the bits in register CACRR */ -#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 - -/* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) -#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) -#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22 -#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) -#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19) -#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16) -#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13 -#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13) -#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) -#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) -#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6 -#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6) -#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3 -#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3) -#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0 -#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7 - -/* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30 -#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30) -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28 -#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28) -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26 -#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26) -#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24 -#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24) -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22 -#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22) -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20 -#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20) -#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19) -#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16 -#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11) -#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10) -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8 -#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7) -#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6) -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4 -#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2 -#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2) -#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1 - -/* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25 -#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25) -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19) -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9 -#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9) -#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6 -#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6) -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0 -#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F - -/* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12 -#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12) -#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10 -#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10) -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8) -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6 -#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6) -#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) -#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) -#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) - -/* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22) -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16) -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14 -#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14) -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11 -#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3 -#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3) -#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7 - -#endif /* __ARCH_ARM_MACH_MX51_CRM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/imx-regs.h b/arch/arm/include/asm/arch-mx51/imx-regs.h deleted file mode 100644 index 3ddda401f31..00000000000 --- a/arch/arm/include/asm/arch-mx51/imx-regs.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_MX51_H__ -#define __ASM_ARCH_MXC_MX51_H__ - -/* - * IRAM - */ -#define IRAM_BASE_ADDR 0x1FFE8000 /* internal ram */ -/* - * Graphics Memory of GPU - */ -#define GPU_BASE_ADDR 0x20000000 -#define GPU_CTRL_BASE_ADDR 0x30000000 -#define IPU_CTRL_BASE_ADDR 0x40000000 -/* - * Debug - */ -#define DEBUG_BASE_ADDR 0x60000000 -#define ETB_BASE_ADDR (DEBUG_BASE_ADDR + 0x00001000) -#define ETM_BASE_ADDR (DEBUG_BASE_ADDR + 0x00002000) -#define TPIU_BASE_ADDR (DEBUG_BASE_ADDR + 0x00003000) -#define CTI0_BASE_ADDR (DEBUG_BASE_ADDR + 0x00004000) -#define CTI1_BASE_ADDR (DEBUG_BASE_ADDR + 0x00005000) -#define CTI2_BASE_ADDR (DEBUG_BASE_ADDR + 0x00006000) -#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) -#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) - -/* - * SPBA global module enabled #0 - */ -#define SPBA0_BASE_ADDR 0x70000000 - -#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) -#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) -#define UART3_BASE_ADDR (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) -#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) -#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) -#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) -#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000) -#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000) -#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000) -#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000) -#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000) - -/* - * AIPS 1 - */ -#define AIPS1_BASE_ADDR 0x73F00000 - -#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000) -#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000) -#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000) -#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000) -#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000) -#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000) -#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000) -#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000) -#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000) -#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000) -#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000) -#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000) -#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000) -#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000) -#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000) -#define UART1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000BC000) -#define UART2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000C0000) -#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000) -#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000) -#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) - -/* - * AIPS 2 - */ -#define AIPS2_BASE_ADDR 0x83F00000 - -#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000) -#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000) -#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000) -#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000) -#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) -#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) -#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) -#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) -#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) -#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) -#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000) -#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000) -#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000) -#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000) -#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000) -#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000) -#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000) -#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000) -#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000) -#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000) -#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) -#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) -#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00) -#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000) -#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000) -#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000) -#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000) -#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000) -#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000) -#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000) -#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) - -#define TZIC_BASE_ADDR 0x8FFFC000 - -/* - * Memory regions and CS - */ -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define CS0_BASE_ADDR 0xB0000000 -#define CS1_BASE_ADDR 0xB8000000 -#define CS2_BASE_ADDR 0xC0000000 -#define CS3_BASE_ADDR 0xC8000000 -#define CS4_BASE_ADDR 0xCC000000 -#define CS5_BASE_ADDR 0xCE000000 - -/* - * NFC - */ -#define NFC_BASE_ADDR_AXI 0xCFFF0000 /* NAND flash AXI */ - -/*! - * Number of GPIO port as defined in the IC Spec - */ -#define GPIO_PORT_NUM 4 -/*! - * Number of GPIO pins per port - */ -#define GPIO_NUM_PIN 32 - -#define IIM_SREV 0x24 -#define ROM_SI_REV 0x48 - -#define NFC_BUF_SIZE 0x1000 - -/* M4IF */ -#define M4IF_FBPM0 0x40 -#define M4IF_FIDBP 0x48 - -/* Assuming 24MHz input clock with doubler ON */ -/* MFI PDF */ -#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_850 (48 - 1) -#define DP_MFN_850 41 - -#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0)) -#define DP_MFD_800 (3 - 1) -#define DP_MFN_800 1 - -#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0)) -#define DP_MFD_700 (24 - 1) -#define DP_MFN_700 7 - -#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0)) -#define DP_MFD_665 (96 - 1) -#define DP_MFN_665 89 - -#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) -#define DP_MFD_532 (24 - 1) -#define DP_MFN_532 13 - -#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) -#define DP_MFD_400 (3 - 1) -#define DP_MFN_400 1 - -#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) -#define DP_MFD_216 (4 - 1) -#define DP_MFN_216 3 - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 - -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 - -#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) -#include - -#define __REG(x) (*((volatile u32 *)(x))) -#define __REG16(x) (*((volatile u16 *)(x))) -#define __REG8(x) (*((volatile u8 *)(x))) - -struct clkctl { - u32 ccr; - u32 ccdr; - u32 csr; - u32 ccsr; - u32 cacrr; - u32 cbcdr; - u32 cbcmr; - u32 cscmr1; - u32 cscmr2; - u32 cscdr1; - u32 cs1cdr; - u32 cs2cdr; - u32 cdcdr; - u32 chsccdr; - u32 cscdr2; - u32 cscdr3; - u32 cscdr4; - u32 cwdr; - u32 cdhipr; - u32 cdcr; - u32 ctor; - u32 clpcr; - u32 cisr; - u32 cimr; - u32 ccosr; - u32 cgpr; - u32 ccgr0; - u32 ccgr1; - u32 ccgr2; - u32 ccgr3; - u32 ccgr4; - u32 ccgr5; - u32 ccgr6; - u32 cmeor; -}; - -/* WEIM registers */ -struct weim { - u32 csgcr1; - u32 csgcr2; - u32 csrcr1; - u32 csrcr2; - u32 cswcr1; - u32 cswcr2; -}; - -/* GPIO Registers */ -struct gpio_regs { - u32 gpio_dr; - u32 gpio_dir; - u32 gpio_psr; -}; - -/* System Reset Controller (SRC) */ -struct src { - u32 scr; - u32 sbmr; - u32 srsr; - u32 reserved1[2]; - u32 sisr; - u32 simr; -}; -#endif /* __ASSEMBLER__*/ - -#endif /* __ASM_ARCH_MXC_MX51_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/iomux.h b/arch/arm/include/asm/arch-mx51/iomux.h deleted file mode 100644 index a41c387c7cd..00000000000 --- a/arch/arm/include/asm/arch-mx51/iomux.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MACH_MX51_IOMUX_H__ -#define __MACH_MX51_IOMUX_H__ - -#include -#include -#include -#include - -typedef unsigned int iomux_pin_name_t; - -/* various IOMUX output functions */ -typedef enum iomux_config { - IOMUX_CONFIG_ALT0, /*!< used as alternate function 0 */ - IOMUX_CONFIG_ALT1, /*!< used as alternate function 1 */ - IOMUX_CONFIG_ALT2, /*!< used as alternate function 2 */ - IOMUX_CONFIG_ALT3, /*!< used as alternate function 3 */ - IOMUX_CONFIG_ALT4, /*!< used as alternate function 4 */ - IOMUX_CONFIG_ALT5, /*!< used as alternate function 5 */ - IOMUX_CONFIG_ALT6, /*!< used as alternate function 6 */ - IOMUX_CONFIG_ALT7, /*!< used as alternate function 7 */ - IOMUX_CONFIG_GPIO, /*!< added to help user use GPIO mode */ - IOMUX_CONFIG_SION = 0x1 << 4, /*!< used as LOOPBACK:MUX SION bit */ -} iomux_pin_cfg_t; - -/* various IOMUX pad functions */ -typedef enum iomux_pad_config { - PAD_CTL_SRE_SLOW = 0x0 << 0, /* Slow slew rate */ - PAD_CTL_SRE_FAST = 0x1 << 0, /* Fast slew rate */ - PAD_CTL_DRV_LOW = 0x0 << 1, /* Low drive strength */ - PAD_CTL_DRV_MEDIUM = 0x1 << 1, /* Medium drive strength */ - PAD_CTL_DRV_HIGH = 0x2 << 1, /* High drive strength */ - PAD_CTL_DRV_MAX = 0x3 << 1, /* Max drive strength */ - PAD_CTL_ODE_OPENDRAIN_NONE = 0x0 << 3, /* Opendrain disable */ - PAD_CTL_ODE_OPENDRAIN_ENABLE = 0x1 << 3,/* Opendrain enable */ - PAD_CTL_100K_PD = 0x0 << 4, /* 100Kohm pulldown */ - PAD_CTL_47K_PU = 0x1 << 4, /* 47Kohm pullup */ - PAD_CTL_100K_PU = 0x2 << 4, /* 100Kohm pullup */ - PAD_CTL_22K_PU = 0x3 << 4, /* 22Kohm pullup */ - PAD_CTL_PUE_KEEPER = 0x0 << 6, /* enable pulldown */ - PAD_CTL_PUE_PULL = 0x1 << 6, /* enable pullup */ - PAD_CTL_PKE_NONE = 0x0 << 7, /* Disable pullup/pulldown */ - PAD_CTL_PKE_ENABLE = 0x1 << 7, /* Enable pullup/pulldown */ - PAD_CTL_HYS_NONE = 0x0 << 8, /* Hysteresis disabled */ - PAD_CTL_HYS_ENABLE = 0x1 << 8, /* Hysteresis enabled */ - PAD_CTL_DDR_INPUT_CMOS = 0x0 << 9,/* DDR input CMOS */ - PAD_CTL_DDR_INPUT_DDR = 0x1 << 9,/* DDR input DDR */ - PAD_CTL_DRV_VOT_LOW = 0x0 << 13, /* Low voltage mode */ - PAD_CTL_DRV_VOT_HIGH = 0x1 << 13,/* High voltage mode */ -} iomux_pad_config_t; - -/* various IOMUX input select register index */ -typedef enum iomux_input_select { - MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, - MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, - MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_RXFS_AMX_SELECT, - MUX_IN_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT, - MUX_IN_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT, - MUX_IN_CCM_IPP_DI_CLK_SELECT_INPUT, - /* TO2 */ - MUX_IN_CCM_IPP_DI1_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, - MUX_IN_CSPI_IPP_CSPI_CLK_IN_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MISO_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_MOSI_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_2_SELECT_INPUT, - MUX_IN_CSPI_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_DPLLIP1_L1T_TOG_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_ECSPI2_IPP_IND_SS_B_1_SELECT_INPUT, - MUX_IN_ECSPI2_IPP_IND_SS_B_3_SELECT_INPUT, - MUX_IN_EMI_IPP_IND_RDY_INT_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT0_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT1_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT2_IN_SELECT_INPUT, - MUX_IN_ESDHC3_IPP_DAT3_IN_SELECT_INPUT, - MUX_IN_FEC_FEC_COL_SELECT_INPUT, - MUX_IN_FEC_FEC_CRS_SELECT_INPUT, - MUX_IN_FEC_FEC_MDI_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_2_SELECT_INPUT, - MUX_IN_FEC_FEC_RDATA_3_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, - MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, - MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_1_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_2_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, - MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, - /* TO2 */ - MUX_IN_GPIO3_IPP_IND_G_IN_12_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS1_DATA_EN_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_IPP_IND_SENS2_DATA_EN_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_VSYNC_SELECT_INPUT, - /* TO2 */ - MUX_IN_HSC_MIPI_MIX_PAR_DI_WAIT_SELECT_INPUT, - MUX_IN_HSC_MIPI_MIX_PAR_SISG_TRIG_SELECT_INPUT, - MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_0_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_IPU_IPP_DI_1_IND_DISPB_SD_D_SELECT_INPUT, - - MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, - MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, - MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_CLK_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_0_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_1_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_2_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_3_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_4_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_5_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_6_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DATA_7_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_DIR_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_NXT_SELECT_INPUT, - MUX_IN_USBOH3_IPP_IND_UH3_STP_SELECT_INPUT, - MUX_INPUT_NUM_MUX, -} iomux_input_select_t; - -/* various IOMUX input functions */ -typedef enum iomux_input_config { - INPUT_CTL_PATH0 = 0x0, - INPUT_CTL_PATH1, - INPUT_CTL_PATH2, - INPUT_CTL_PATH3, - INPUT_CTL_PATH4, - INPUT_CTL_PATH5, - INPUT_CTL_PATH6, - INPUT_CTL_PATH7, -} iomux_input_config_t; - -void mxc_request_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); -void mxc_free_iomux(iomux_pin_name_t pin, iomux_pin_cfg_t config); -void mxc_iomux_set_pad(iomux_pin_name_t pin, u32 config); -unsigned int mxc_iomux_get_pad(iomux_pin_name_t pin); -void mxc_iomux_set_input(iomux_input_select_t input, u32 config); - -#endif /* __MACH_MX51_IOMUX_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/mx51_pins.h b/arch/arm/include/asm/arch-mx51/mx51_pins.h deleted file mode 100644 index b44ff252bfe..00000000000 --- a/arch/arm/include/asm/arch-mx51/mx51_pins.h +++ /dev/null @@ -1,418 +0,0 @@ -/* - * (C) Copyright 2008-2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_ARCH_MXC_MX51_PINS_H__ -#define __ASM_ARCH_MXC_MX51_PINS_H__ - -#ifndef __ASSEMBLY__ - -/* - * In order to identify pins more effectively, each mux-controlled pin's - * enumerated value is constructed in the following way: - * - * ------------------------------------------------------------------- - * 31-29 | 28 - 24 | 23 - 21 | 20 - 10| 9 - 0 - * ------------------------------------------------------------------- - * IO_P | IO_I | GPIO_I | PAD_I | MUX_I - * ------------------------------------------------------------------- - * - * Bit 0 to 9 contains MUX_I used to identify the register - * offset (0-based. base is IOMUX_module_base) defined in the Section - * "sw_pad_ctl & sw_mux_ctl details" of the IC Spec. The - * similar field definitions are used for the pad control register. - * The IOMUX controller can be split in two parts. At the begeinning, - * there is the register definitions for the multiplexing each pin. - * Then there is a set of registers (PAD_I) to configure each pin - * (pullup, pulldown, etc). - * PAD_I defines the offset of the pad register for each pin. - * GPIO_I defines, if available, the number of gpio that can be - * connected to that pad - * IO_I defines the multiplexer mode required to set the pad in gpio mode - * IO_P defines the gpio structure (gpio1..gpio4) the pad belongs - * - * For example, the MX51_PIN_ETM_D0 is defined in the enumeration: - * ( (0x28 - MUX_I_START) << MUX_I)|( (0x250 - PAD_I_START) << PAD_I) - * It means the mux control register is at register offset 0x28. The pad control - * register offset is: 0x250 and also occupy the least significant bits - * within the register. - */ - -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * MUX control register offset - */ -#define MUX_I 0 -/*! - * Starting bit position within each entry of \b iomux_pins to represent the - * PAD control register offset - */ -#define PAD_I 10 -/*! - * Starting bit position within each entry of \b iomux_pins to represent which - * mux mode is for GPIO (0-based) - */ -#define GPIO_I 21 - -#define MUX_IO_P 29 -#define MUX_IO_I 24 -#define IOMUX_TO_GPIO(pin) ((((unsigned int)pin >> MUX_IO_P) * \ - GPIO_NUM_PIN) + ((pin >> MUX_IO_I) &\ - ((1 << (MUX_IO_P - MUX_IO_I)) - 1))) -#define IOMUX_TO_IRQ(pin) (MXC_GPIO_INT_BASE + IOMUX_TO_GPIO(pin)) -#define GPIO_TO_PORT(n) (n / GPIO_NUM_PIN) -#define GPIO_TO_INDEX(n) (n % GPIO_NUM_PIN) - -#define NON_GPIO_PORT 0x7 -#define PIN_TO_MUX_MASK ((1 << (PAD_I - MUX_I)) - 1) -#define PIN_TO_PAD_MASK ((1 << (GPIO_I - PAD_I)) - 1) -#define PIN_TO_ALT_GPIO_MASK ((1 << (MUX_IO_I - GPIO_I)) - 1) - -#define NON_MUX_I PIN_TO_MUX_MASK -#define MUX_I_START 0x001C -#define PAD_I_START 0x3F0 -#define INPUT_CTL_START 0x8C4 -#define INPUT_CTL_START_TO1 0x928 -#define MUX_I_END (PAD_I_START - 4) - -#define _MXC_BUILD_PIN(gp, gi, ga, mi, pi) \ - (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ - ((mi) << MUX_I) | \ - ((pi - PAD_I_START) << PAD_I) | \ - ((ga) << GPIO_I)) - -#define _MXC_BUILD_GPIO_PIN(gp, gi, ga, mi, pi) \ - _MXC_BUILD_PIN(gp, gi, ga, mi, pi) - -#define _MXC_BUILD_NON_GPIO_PIN(mi, pi) \ - _MXC_BUILD_PIN(NON_GPIO_PORT, 0, 0, mi, pi) - -#define PIN_TO_IOMUX_MUX(pin) ((pin >> MUX_I) & PIN_TO_MUX_MASK) -#define PIN_TO_IOMUX_PAD(pin) ((pin >> PAD_I) & PIN_TO_PAD_MASK) -#define PIN_TO_ALT_GPIO(pin) ((pin >> GPIO_I) & PIN_TO_ALT_GPIO_MASK) -#define PIN_TO_IOMUX_INDEX(pin) (PIN_TO_IOMUX_MUX(pin) >> 2) - -/* - * This enumeration is constructed based on the Section - * "sw_pad_ctl & sw_mux_ctl details" of the MX51 IC Spec. Each enumerated - * value is constructed based on the rules described above. - */ -enum iomux_pins { - MX51_PIN_EIM_DA0 = _MXC_BUILD_NON_GPIO_PIN(0x1C, 0x7A8), - MX51_PIN_EIM_DA1 = _MXC_BUILD_NON_GPIO_PIN(0x20, 0x7A8), - MX51_PIN_EIM_DA2 = _MXC_BUILD_NON_GPIO_PIN(0x24, 0x7A8), - MX51_PIN_EIM_DA3 = _MXC_BUILD_NON_GPIO_PIN(0x28, 0x7A8), - MX51_PIN_EIM_DA4 = _MXC_BUILD_NON_GPIO_PIN(0x2C, 0x7AC), - MX51_PIN_EIM_DA5 = _MXC_BUILD_NON_GPIO_PIN(0x30, 0x7AC), - MX51_PIN_EIM_DA6 = _MXC_BUILD_NON_GPIO_PIN(0x34, 0x7AC), - MX51_PIN_EIM_DA7 = _MXC_BUILD_NON_GPIO_PIN(0x38, 0x7AC), - MX51_PIN_EIM_DA8 = _MXC_BUILD_NON_GPIO_PIN(0x3C, 0x7B0), - MX51_PIN_EIM_DA9 = _MXC_BUILD_NON_GPIO_PIN(0x40, 0x7B0), - MX51_PIN_EIM_DA10 = _MXC_BUILD_NON_GPIO_PIN(0x44, 0x7B0), - MX51_PIN_EIM_DA11 = _MXC_BUILD_NON_GPIO_PIN(0x48, 0x7B0), - MX51_PIN_EIM_DA12 = _MXC_BUILD_NON_GPIO_PIN(0x4C, 0x7BC), - MX51_PIN_EIM_DA13 = _MXC_BUILD_NON_GPIO_PIN(0x50, 0x7BC), - MX51_PIN_EIM_DA14 = _MXC_BUILD_NON_GPIO_PIN(0x54, 0x7BC), - MX51_PIN_EIM_DA15 = _MXC_BUILD_NON_GPIO_PIN(0x58, 0x7BC), - MX51_PIN_EIM_D16 = _MXC_BUILD_GPIO_PIN(1, 0, 1, 0x5C, 0x3F0), - MX51_PIN_EIM_D17 = _MXC_BUILD_GPIO_PIN(1, 1, 1, 0x60, 0x3F4), - MX51_PIN_EIM_D18 = _MXC_BUILD_GPIO_PIN(1, 2, 1, 0x64, 0x3F8), - MX51_PIN_EIM_D19 = _MXC_BUILD_GPIO_PIN(1, 3, 1, 0x68, 0x3FC), - MX51_PIN_EIM_D20 = _MXC_BUILD_GPIO_PIN(1, 4, 1, 0x6C, 0x400), - MX51_PIN_EIM_D21 = _MXC_BUILD_GPIO_PIN(1, 5, 1, 0x70, 0x404), - MX51_PIN_EIM_D22 = _MXC_BUILD_GPIO_PIN(1, 6, 1, 0x74, 0x408), - MX51_PIN_EIM_D23 = _MXC_BUILD_GPIO_PIN(1, 7, 1, 0x78, 0x40C), - MX51_PIN_EIM_D24 = _MXC_BUILD_GPIO_PIN(1, 8, 1, 0x7C, 0x410), - MX51_PIN_EIM_D25 = _MXC_BUILD_NON_GPIO_PIN(0x80, 0x414), - MX51_PIN_EIM_D26 = _MXC_BUILD_NON_GPIO_PIN(0x84, 0x418), - MX51_PIN_EIM_D27 = _MXC_BUILD_GPIO_PIN(1, 9, 1, 0x88, 0x41C), - MX51_PIN_EIM_D28 = _MXC_BUILD_NON_GPIO_PIN(0x8C, 0x420), - MX51_PIN_EIM_D29 = _MXC_BUILD_NON_GPIO_PIN(0x90, 0x424), - MX51_PIN_EIM_D30 = _MXC_BUILD_NON_GPIO_PIN(0x94, 0x428), - MX51_PIN_EIM_D31 = _MXC_BUILD_NON_GPIO_PIN(0x98, 0x42C), - MX51_PIN_EIM_A16 = _MXC_BUILD_GPIO_PIN(1, 10, 1, 0x9C, 0x430), - MX51_PIN_EIM_A17 = _MXC_BUILD_GPIO_PIN(1, 11, 1, 0xA0, 0x434), - MX51_PIN_EIM_A18 = _MXC_BUILD_GPIO_PIN(1, 12, 1, 0xA4, 0x438), - MX51_PIN_EIM_A19 = _MXC_BUILD_GPIO_PIN(1, 13, 1, 0xA8, 0x43C), - MX51_PIN_EIM_A20 = _MXC_BUILD_GPIO_PIN(1, 14, 1, 0xAC, 0x440), - MX51_PIN_EIM_A21 = _MXC_BUILD_GPIO_PIN(1, 15, 1, 0xB0, 0x444), - MX51_PIN_EIM_A22 = _MXC_BUILD_GPIO_PIN(1, 16, 1, 0xB4, 0x448), - MX51_PIN_EIM_A23 = _MXC_BUILD_GPIO_PIN(1, 17, 1, 0xB8, 0x44C), - MX51_PIN_EIM_A24 = _MXC_BUILD_GPIO_PIN(1, 18, 1, 0xBC, 0x450), - MX51_PIN_EIM_A25 = _MXC_BUILD_GPIO_PIN(1, 19, 1, 0xC0, 0x454), - MX51_PIN_EIM_A26 = _MXC_BUILD_GPIO_PIN(1, 20, 1, 0xC4, 0x458), - MX51_PIN_EIM_A27 = _MXC_BUILD_GPIO_PIN(1, 21, 1, 0xC8, 0x45C), - MX51_PIN_EIM_EB0 = _MXC_BUILD_NON_GPIO_PIN(0xCC, 0x460), - MX51_PIN_EIM_EB1 = _MXC_BUILD_NON_GPIO_PIN(0xD0, 0x464), - MX51_PIN_EIM_EB2 = _MXC_BUILD_GPIO_PIN(1, 22, 1, 0xD4, 0x468), - MX51_PIN_EIM_EB3 = _MXC_BUILD_GPIO_PIN(1, 23, 1, 0xD8, 0x46C), - MX51_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN(1, 24, 1, 0xDC, 0x470), - MX51_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN(1, 25, 1, 0xE0, 0x474), - MX51_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN(1, 26, 1, 0xE4, 0x478), - MX51_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN(1, 27, 1, 0xE8, 0x47C), - MX51_PIN_EIM_CS3 = _MXC_BUILD_GPIO_PIN(1, 28, 1, 0xEC, 0x480), - MX51_PIN_EIM_CS4 = _MXC_BUILD_GPIO_PIN(1, 29, 1, 0xF0, 0x484), - MX51_PIN_EIM_CS5 = _MXC_BUILD_GPIO_PIN(1, 30, 1, 0xF4, 0x488), - MX51_PIN_EIM_DTACK = _MXC_BUILD_GPIO_PIN(1, 31, 1, 0xF8, 0x48C), - MX51_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN(2, 1, 1, 0xFC, 0x494), - MX51_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN(2, 2, 1, 0x100, 0x4A0), - MX51_PIN_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0x104, 0x4D0), - MX51_PIN_NANDF_WE_B = _MXC_BUILD_GPIO_PIN(2, 3, 3, 0x108, 0x4E4), - MX51_PIN_NANDF_RE_B = _MXC_BUILD_GPIO_PIN(2, 4, 3, 0x10C, 0x4E8), - MX51_PIN_NANDF_ALE = _MXC_BUILD_GPIO_PIN(2, 5, 3, 0x110, 0x4EC), - MX51_PIN_NANDF_CLE = _MXC_BUILD_GPIO_PIN(2, 6, 3, 0x114, 0x4F0), - MX51_PIN_NANDF_WP_B = _MXC_BUILD_GPIO_PIN(2, 7, 3, 0x118, 0x4F4), - MX51_PIN_NANDF_RB0 = _MXC_BUILD_GPIO_PIN(2, 8, 3, 0x11C, 0x4F8), - MX51_PIN_NANDF_RB1 = _MXC_BUILD_GPIO_PIN(2, 9, 3, 0x120, 0x4FC), - MX51_PIN_NANDF_RB2 = _MXC_BUILD_GPIO_PIN(2, 10, 3, 0x124, 0x500), - MX51_PIN_NANDF_RB3 = _MXC_BUILD_GPIO_PIN(2, 11, 3, 0x128, 0x504), - MX51_PIN_GPIO_NAND = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x12C, 0x514), - MX51_PIN_NANDF_RB4 = MX51_PIN_GPIO_NAND, - MX51_PIN_NANDF_RB5 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x130, 0x5D8), - MX51_PIN_NANDF_RB6 = _MXC_BUILD_GPIO_PIN(2, 14, 3, 0x134, 0x5DC), - MX51_PIN_NANDF_RB7 = _MXC_BUILD_GPIO_PIN(2, 15, 3, 0x138, 0x5E0), - MX51_PIN_NANDF_CS0 = _MXC_BUILD_GPIO_PIN(2, 16, 3, 0x130, 0x518), - MX51_PIN_NANDF_CS1 = _MXC_BUILD_GPIO_PIN(2, 17, 3, 0x134, 0x51C), - MX51_PIN_NANDF_CS2 = _MXC_BUILD_GPIO_PIN(2, 18, 3, 0x138, 0x520), - MX51_PIN_NANDF_CS3 = _MXC_BUILD_GPIO_PIN(2, 19, 3, 0x13C, 0x524), - MX51_PIN_NANDF_CS4 = _MXC_BUILD_GPIO_PIN(2, 20, 3, 0x140, 0x528), - MX51_PIN_NANDF_CS5 = _MXC_BUILD_GPIO_PIN(2, 21, 3, 0x144, 0x52C), - MX51_PIN_NANDF_CS6 = _MXC_BUILD_GPIO_PIN(2, 22, 3, 0x148, 0x530), - MX51_PIN_NANDF_CS7 = _MXC_BUILD_GPIO_PIN(2, 23, 3, 0x14C, 0x534), - MX51_PIN_NANDF_RDY_INT = _MXC_BUILD_GPIO_PIN(2, 24, 3, 0x150, 0x538), - MX51_PIN_NANDF_D15 = _MXC_BUILD_GPIO_PIN(2, 25, 3, 0x154, 0x53C), - MX51_PIN_NANDF_D14 = _MXC_BUILD_GPIO_PIN(2, 26, 3, 0x158, 0x540), - MX51_PIN_NANDF_D13 = _MXC_BUILD_GPIO_PIN(2, 27, 3, 0x15C, 0x544), - MX51_PIN_NANDF_D12 = _MXC_BUILD_GPIO_PIN(2, 28, 3, 0x160, 0x548), - MX51_PIN_NANDF_D11 = _MXC_BUILD_GPIO_PIN(2, 29, 3, 0x164, 0x54C), - MX51_PIN_NANDF_D10 = _MXC_BUILD_GPIO_PIN(2, 30, 3, 0x168, 0x550), - MX51_PIN_NANDF_D9 = _MXC_BUILD_GPIO_PIN(2, 31, 3, 0x16C, 0x554), - MX51_PIN_NANDF_D8 = _MXC_BUILD_GPIO_PIN(3, 0, 3, 0x170, 0x558), - MX51_PIN_NANDF_D7 = _MXC_BUILD_GPIO_PIN(3, 1, 3, 0x174, 0x55C), - MX51_PIN_NANDF_D6 = _MXC_BUILD_GPIO_PIN(3, 2, 3, 0x178, 0x560), - MX51_PIN_NANDF_D5 = _MXC_BUILD_GPIO_PIN(3, 3, 3, 0x17C, 0x564), - MX51_PIN_NANDF_D4 = _MXC_BUILD_GPIO_PIN(3, 4, 3, 0x180, 0x568), - MX51_PIN_NANDF_D3 = _MXC_BUILD_GPIO_PIN(3, 5, 3, 0x184, 0x56C), - MX51_PIN_NANDF_D2 = _MXC_BUILD_GPIO_PIN(3, 6, 3, 0x188, 0x570), - MX51_PIN_NANDF_D1 = _MXC_BUILD_GPIO_PIN(3, 7, 3, 0x18C, 0x574), - MX51_PIN_NANDF_D0 = _MXC_BUILD_GPIO_PIN(3, 8, 3, 0x190, 0x578), - MX51_PIN_CSI1_D8 = _MXC_BUILD_GPIO_PIN(2, 12, 3, 0x194, 0x57C), - MX51_PIN_CSI1_D9 = _MXC_BUILD_GPIO_PIN(2, 13, 3, 0x198, 0x580), - MX51_PIN_CSI1_D10 = _MXC_BUILD_NON_GPIO_PIN(0x19C, 0x584), - MX51_PIN_CSI1_D11 = _MXC_BUILD_NON_GPIO_PIN(0x1A0, 0x588), - MX51_PIN_CSI1_D12 = _MXC_BUILD_NON_GPIO_PIN(0x1A4, 0x58C), - MX51_PIN_CSI1_D13 = _MXC_BUILD_NON_GPIO_PIN(0x1A8, 0x590), - MX51_PIN_CSI1_D14 = _MXC_BUILD_NON_GPIO_PIN(0x1AC, 0x594), - MX51_PIN_CSI1_D15 = _MXC_BUILD_NON_GPIO_PIN(0x1B0, 0x598), - MX51_PIN_CSI1_D16 = _MXC_BUILD_NON_GPIO_PIN(0x1B4, 0x59C), - MX51_PIN_CSI1_D17 = _MXC_BUILD_NON_GPIO_PIN(0x1B8, 0x5A0), - MX51_PIN_CSI1_D18 = _MXC_BUILD_NON_GPIO_PIN(0x1BC, 0x5A4), - MX51_PIN_CSI1_D19 = _MXC_BUILD_NON_GPIO_PIN(0x1C0, 0x5A8), - MX51_PIN_CSI1_VSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C4, 0x5AC), - MX51_PIN_CSI1_HSYNC = _MXC_BUILD_NON_GPIO_PIN(0x1C8, 0x5B0), - MX51_PIN_CSI1_PIXCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B4), - MX51_PIN_CSI1_MCLK = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x5B8), - MX51_PIN_CSI1_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x860), - MX51_PIN_CSI2_D12 = _MXC_BUILD_GPIO_PIN(3, 9, 3, 0x1CC, 0x5BC), - MX51_PIN_CSI2_D13 = _MXC_BUILD_GPIO_PIN(3, 10, 3, 0x1D0, 0x5C0), - MX51_PIN_CSI2_D14 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1D4, 0x5C4), - MX51_PIN_CSI2_D15 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1D8, 0x5C8), - MX51_PIN_CSI2_D16 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1DC, 0x5CC), - MX51_PIN_CSI2_D17 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E0, 0x5D0), - MX51_PIN_CSI2_D18 = _MXC_BUILD_GPIO_PIN(3, 11, 3, 0x1E4, 0x5D4), - MX51_PIN_CSI2_D19 = _MXC_BUILD_GPIO_PIN(3, 12, 3, 0x1E8, 0x5D8), - MX51_PIN_CSI2_VSYNC = _MXC_BUILD_GPIO_PIN(3, 13, 3, 0x1EC, 0x5DC), - MX51_PIN_CSI2_HSYNC = _MXC_BUILD_GPIO_PIN(3, 14, 3, 0x1F0, 0x5E0), - MX51_PIN_CSI2_PIXCLK = _MXC_BUILD_GPIO_PIN(3, 15, 3, 0x1F4, 0x5E4), - MX51_PIN_CSI2_PKE0 = _MXC_BUILD_NON_GPIO_PIN(NON_MUX_I, 0x81C), - MX51_PIN_I2C1_CLK = _MXC_BUILD_GPIO_PIN(3, 16, 3, 0x1F8, 0x5E8), - MX51_PIN_I2C1_DAT = _MXC_BUILD_GPIO_PIN(3, 17, 3, 0x1FC, 0x5EC), - MX51_PIN_AUD3_BB_TXD = _MXC_BUILD_GPIO_PIN(3, 18, 3, 0x200, 0x5F0), - MX51_PIN_AUD3_BB_RXD = _MXC_BUILD_GPIO_PIN(3, 19, 3, 0x204, 0x5F4), - MX51_PIN_AUD3_BB_CK = _MXC_BUILD_GPIO_PIN(3, 20, 3, 0x208, 0x5F8), - MX51_PIN_AUD3_BB_FS = _MXC_BUILD_GPIO_PIN(3, 21, 3, 0x20C, 0x5FC), - MX51_PIN_CSPI1_MOSI = _MXC_BUILD_GPIO_PIN(3, 22, 3, 0x210, 0x600), - MX51_PIN_CSPI1_MISO = _MXC_BUILD_GPIO_PIN(3, 23, 3, 0x214, 0x604), - MX51_PIN_CSPI1_SS0 = _MXC_BUILD_GPIO_PIN(3, 24, 3, 0x218, 0x608), - MX51_PIN_CSPI1_SS1 = _MXC_BUILD_GPIO_PIN(3, 25, 3, 0x21C, 0x60C), - MX51_PIN_CSPI1_RDY = _MXC_BUILD_GPIO_PIN(3, 26, 3, 0x220, 0x610), - MX51_PIN_CSPI1_SCLK = _MXC_BUILD_GPIO_PIN(3, 27, 3, 0x224, 0x614), - MX51_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN(3, 28, 3, 0x228, 0x618), - MX51_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN(3, 29, 3, 0x22C, 0x61C), - MX51_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN(3, 30, 3, 0x230, 0x620), - MX51_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN(3, 31, 3, 0x234, 0x624), - MX51_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN(0, 20, 3, 0x238, 0x628), - MX51_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN(0, 21, 3, 0x23C, 0x62C), - MX51_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN(0, 22, 3, 0x240, 0x630), - MX51_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN(0, 23, 3, 0x244, 0x634), - MX51_PIN_OWIRE_LINE = _MXC_BUILD_GPIO_PIN(0, 24, 3, 0x248, 0x638), - MX51_PIN_KEY_ROW0 = _MXC_BUILD_NON_GPIO_PIN(0x24C, 0x63C), - MX51_PIN_KEY_ROW1 = _MXC_BUILD_NON_GPIO_PIN(0x250, 0x640), - MX51_PIN_KEY_ROW2 = _MXC_BUILD_NON_GPIO_PIN(0x254, 0x644), - MX51_PIN_KEY_ROW3 = _MXC_BUILD_NON_GPIO_PIN(0x258, 0x648), - MX51_PIN_KEY_COL0 = _MXC_BUILD_NON_GPIO_PIN(0x25C, 0x64C), - MX51_PIN_KEY_COL1 = _MXC_BUILD_NON_GPIO_PIN(0x260, 0x650), - MX51_PIN_KEY_COL2 = _MXC_BUILD_NON_GPIO_PIN(0x264, 0x654), - MX51_PIN_KEY_COL3 = _MXC_BUILD_NON_GPIO_PIN(0x268, 0x658), - MX51_PIN_KEY_COL4 = _MXC_BUILD_NON_GPIO_PIN(0x26C, 0x65C), - MX51_PIN_KEY_COL5 = _MXC_BUILD_NON_GPIO_PIN(0x270, 0x660), - MX51_PIN_USBH1_CLK = _MXC_BUILD_GPIO_PIN(0, 25, 2, 0x278, 0x678), - MX51_PIN_USBH1_DIR = _MXC_BUILD_GPIO_PIN(0, 26, 2, 0x27C, 0x67C), - MX51_PIN_USBH1_STP = _MXC_BUILD_GPIO_PIN(0, 27, 2, 0x280, 0x680), - MX51_PIN_USBH1_NXT = _MXC_BUILD_GPIO_PIN(0, 28, 2, 0x284, 0x684), - MX51_PIN_USBH1_DATA0 = _MXC_BUILD_GPIO_PIN(0, 11, 2, 0x288, 0x688), - MX51_PIN_USBH1_DATA1 = _MXC_BUILD_GPIO_PIN(0, 12, 2, 0x28C, 0x68C), - MX51_PIN_USBH1_DATA2 = _MXC_BUILD_GPIO_PIN(0, 13, 2, 0x290, 0x690), - MX51_PIN_USBH1_DATA3 = _MXC_BUILD_GPIO_PIN(0, 14, 2, 0x294, 0x694), - MX51_PIN_USBH1_DATA4 = _MXC_BUILD_GPIO_PIN(0, 15, 2, 0x298, 0x698), - MX51_PIN_USBH1_DATA5 = _MXC_BUILD_GPIO_PIN(0, 16, 2, 0x29C, 0x69C), - MX51_PIN_USBH1_DATA6 = _MXC_BUILD_GPIO_PIN(0, 17, 2, 0x2A0, 0x6A0), - MX51_PIN_USBH1_DATA7 = _MXC_BUILD_GPIO_PIN(0, 18, 2, 0x2A4, 0x6A4), - MX51_PIN_DI1_PIN11 = _MXC_BUILD_GPIO_PIN(2, 0, 4, 0x2A8, 0x6A8), - MX51_PIN_DI1_PIN12 = _MXC_BUILD_GPIO_PIN(2, 1, 4, 0x2AC, 0x6AC), - MX51_PIN_DI1_PIN13 = _MXC_BUILD_GPIO_PIN(2, 2, 4, 0x2B0, 0x6B0), - MX51_PIN_DI1_D0_CS = _MXC_BUILD_GPIO_PIN(2, 3, 4, 0x2B4, 0x6B4), - MX51_PIN_DI1_D1_CS = _MXC_BUILD_GPIO_PIN(2, 4, 4, 0x2B8, 0x6B8), - MX51_PIN_DISPB2_SER_DIN = _MXC_BUILD_GPIO_PIN(2, 5, 4, 0x2BC, 0x6BC), - MX51_PIN_DISPB2_SER_DIO = _MXC_BUILD_GPIO_PIN(2, 6, 4, 0x2C0, 0x6C0), - MX51_PIN_DISPB2_SER_CLK = _MXC_BUILD_GPIO_PIN(2, 7, 4, 0x2C4, 0x6C4), - MX51_PIN_DISPB2_SER_RS = _MXC_BUILD_GPIO_PIN(2, 8, 4, 0x2C8, 0x6C8), - MX51_PIN_DISP1_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x2CC, 0x6CC), - MX51_PIN_DISP1_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x2D0, 0x6D0), - MX51_PIN_DISP1_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x2D4, 0x6D4), - MX51_PIN_DISP1_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x2D8, 0x6D8), - MX51_PIN_DISP1_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x2DC, 0x6DC), - MX51_PIN_DISP1_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x2E0, 0x6E0), - MX51_PIN_DISP1_DAT6 = _MXC_BUILD_NON_GPIO_PIN(0x2E4, 0x6E4), - MX51_PIN_DISP1_DAT7 = _MXC_BUILD_NON_GPIO_PIN(0x2E8, 0x6E8), - MX51_PIN_DISP1_DAT8 = _MXC_BUILD_NON_GPIO_PIN(0x2EC, 0x6EC), - MX51_PIN_DISP1_DAT9 = _MXC_BUILD_NON_GPIO_PIN(0x2F0, 0x6F0), - MX51_PIN_DISP1_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x2F4, 0x6F4), - MX51_PIN_DISP1_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x2F8, 0x6F8), - MX51_PIN_DISP1_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x2FC, 0x6FC), - MX51_PIN_DISP1_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x300, 0x700), - MX51_PIN_DISP1_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x304, 0x704), - MX51_PIN_DISP1_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x308, 0x708), - MX51_PIN_DISP1_DAT16 = _MXC_BUILD_NON_GPIO_PIN(0x30C, 0x70C), - MX51_PIN_DISP1_DAT17 = _MXC_BUILD_NON_GPIO_PIN(0x310, 0x710), - MX51_PIN_DISP1_DAT18 = _MXC_BUILD_NON_GPIO_PIN(0x314, 0x714), - MX51_PIN_DISP1_DAT19 = _MXC_BUILD_NON_GPIO_PIN(0x318, 0x718), - MX51_PIN_DISP1_DAT20 = _MXC_BUILD_NON_GPIO_PIN(0x31C, 0x71C), - MX51_PIN_DISP1_DAT21 = _MXC_BUILD_NON_GPIO_PIN(0x320, 0x720), - MX51_PIN_DISP1_DAT22 = _MXC_BUILD_NON_GPIO_PIN(0x324, 0x724), - MX51_PIN_DISP1_DAT23 = _MXC_BUILD_NON_GPIO_PIN(0x328, 0x728), - MX51_PIN_DI1_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x32C, 0x72C), - MX51_PIN_DI1_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x330, 0x734), - MX51_PIN_DI_GP1 = _MXC_BUILD_NON_GPIO_PIN(0x334, 0x73C), - MX51_PIN_DI_GP2 = _MXC_BUILD_NON_GPIO_PIN(0x338, 0x740), - MX51_PIN_DI_GP3 = _MXC_BUILD_NON_GPIO_PIN(0x33C, 0x744), - MX51_PIN_DI2_PIN4 = _MXC_BUILD_NON_GPIO_PIN(0x340, 0x748), - MX51_PIN_DI2_PIN2 = _MXC_BUILD_NON_GPIO_PIN(0x344, 0x74C), - MX51_PIN_DI2_PIN3 = _MXC_BUILD_NON_GPIO_PIN(0x348, 0x750), - MX51_PIN_DI2_DISP_CLK = _MXC_BUILD_NON_GPIO_PIN(0x34C, 0x754), - MX51_PIN_DI_GP4 = _MXC_BUILD_NON_GPIO_PIN(0x350, 0x758), - MX51_PIN_DISP2_DAT0 = _MXC_BUILD_NON_GPIO_PIN(0x354, 0x75C), - MX51_PIN_DISP2_DAT1 = _MXC_BUILD_NON_GPIO_PIN(0x358, 0x760), - MX51_PIN_DISP2_DAT2 = _MXC_BUILD_NON_GPIO_PIN(0x35C, 0x764), - MX51_PIN_DISP2_DAT3 = _MXC_BUILD_NON_GPIO_PIN(0x360, 0x768), - MX51_PIN_DISP2_DAT4 = _MXC_BUILD_NON_GPIO_PIN(0x364, 0x76C), - MX51_PIN_DISP2_DAT5 = _MXC_BUILD_NON_GPIO_PIN(0x368, 0x770), - MX51_PIN_DISP2_DAT6 = _MXC_BUILD_GPIO_PIN(0, 19, 5, 0x36C, 0x774), - MX51_PIN_DISP2_DAT7 = _MXC_BUILD_GPIO_PIN(0, 29, 5, 0x370, 0x778), - MX51_PIN_DISP2_DAT8 = _MXC_BUILD_GPIO_PIN(0, 30, 5, 0x374, 0x77C), - MX51_PIN_DISP2_DAT9 = _MXC_BUILD_GPIO_PIN(0, 31, 5, 0x378, 0x780), - MX51_PIN_DISP2_DAT10 = _MXC_BUILD_NON_GPIO_PIN(0x37C, 0x784), - MX51_PIN_DISP2_DAT11 = _MXC_BUILD_NON_GPIO_PIN(0x380, 0x788), - MX51_PIN_DISP2_DAT12 = _MXC_BUILD_NON_GPIO_PIN(0x384, 0x78C), - MX51_PIN_DISP2_DAT13 = _MXC_BUILD_NON_GPIO_PIN(0x388, 0x790), - MX51_PIN_DISP2_DAT14 = _MXC_BUILD_NON_GPIO_PIN(0x38C, 0x794), - MX51_PIN_DISP2_DAT15 = _MXC_BUILD_NON_GPIO_PIN(0x390, 0x798), - MX51_PIN_SD1_CMD = _MXC_BUILD_NON_GPIO_PIN(0x394, 0x79C), - MX51_PIN_SD1_CLK = _MXC_BUILD_NON_GPIO_PIN(0x398, 0x7A0), - MX51_PIN_SD1_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x39C, 0x7A4), - MX51_PIN_SD1_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3A0, 0x7A8), - MX51_PIN_SD1_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3A4, 0x7AC), - MX51_PIN_SD1_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3A8, 0x7B0), - MX51_PIN_GPIO1_0 = _MXC_BUILD_GPIO_PIN(0, 0, 1, 0x3AC, 0x7B4), - MX51_PIN_GPIO1_1 = _MXC_BUILD_GPIO_PIN(0, 1, 1, 0x3B0, 0x7B8), - MX51_PIN_SD2_CMD = _MXC_BUILD_NON_GPIO_PIN(0x3B4, 0x7BC), - MX51_PIN_SD2_CLK = _MXC_BUILD_NON_GPIO_PIN(0x3B8, 0x7C0), - MX51_PIN_SD2_DATA0 = _MXC_BUILD_NON_GPIO_PIN(0x3BC, 0x7C4), - MX51_PIN_SD2_DATA1 = _MXC_BUILD_NON_GPIO_PIN(0x3C0, 0x7C8), - MX51_PIN_SD2_DATA2 = _MXC_BUILD_NON_GPIO_PIN(0x3C4, 0x7CC), - MX51_PIN_SD2_DATA3 = _MXC_BUILD_NON_GPIO_PIN(0x3C8, 0x7D0), - MX51_PIN_GPIO1_2 = _MXC_BUILD_GPIO_PIN(0, 2, 0, 0x3CC, 0x7D4), - MX51_PIN_GPIO1_3 = _MXC_BUILD_GPIO_PIN(0, 3, 0, 0x3D0, 0x7D8), - MX51_PIN_PMIC_INT_REQ = _MXC_BUILD_NON_GPIO_PIN(0x3D4, 0x7FC), - MX51_PIN_GPIO1_4 = _MXC_BUILD_GPIO_PIN(0, 4, 0, 0x3D8, 0x804), - MX51_PIN_GPIO1_5 = _MXC_BUILD_GPIO_PIN(0, 5, 0, 0x3DC, 0x808), - MX51_PIN_GPIO1_6 = _MXC_BUILD_GPIO_PIN(0, 6, 0, 0x3E0, 0x80C), - MX51_PIN_GPIO1_7 = _MXC_BUILD_GPIO_PIN(0, 7, 0, 0x3E4, 0x810), - MX51_PIN_GPIO1_8 = _MXC_BUILD_GPIO_PIN(0, 8, 0, 0x3E8, 0x814), - MX51_PIN_GPIO1_9 = _MXC_BUILD_GPIO_PIN(0, 9, 0, 0x3EC, 0x818), - - /* The following are PADS used for drive strength */ - - MX51_PIN_CTL_GRP_DDRPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x820), - MX51_PIN_CTL_GRP_PKEDDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x838), - MX51_PIN_CTL_GRP_PKEADDR = _MXC_BUILD_NON_GPIO_PIN(0, 0x890), - MX51_PIN_CTL_GRP_DDRAPKS = _MXC_BUILD_NON_GPIO_PIN(0, 0x87C), - MX51_PIN_CTL_GRP_DDRAPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x84C), - MX51_PIN_CTL_GRP_DDRPUS = _MXC_BUILD_NON_GPIO_PIN(0, 0x884), - MX51_PIN_CTL_GRP_HYSDDR0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x85C), - MX51_PIN_CTL_GRP_HYSDDR1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x864), - MX51_PIN_CTL_GRP_HYSDDR2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x86C), - MX51_PIN_CTL_GRP_HYSDDR3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x874), - MX51_PIN_CTL_GRP_DDR_SR_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x878), - MX51_PIN_CTL_GRP_DDR_SR_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x880), - MX51_PIN_CTL_GRP_DDR_SR_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x88C), - MX51_PIN_CTL_GRP_DDR_SR_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x89C), - MX51_PIN_CTL_GRP_DRAM_B0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A4), - MX51_PIN_CTL_GRP_DRAM_B1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8AC), - MX51_PIN_CTL_GRP_DRAM_B2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B8), - MX51_PIN_CTL_GRP_DRAM_B4 = _MXC_BUILD_NON_GPIO_PIN(0, 0x82C), - MX51_PIN_CTL_GRP_INMODE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8A0), - MX51_PIN_CTL_GRP_DDR_SR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B0), - MX51_PIN_CTL_GRP_EMI_DS5 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8B4), - MX51_PIN_CTL_GRP_DDR_SR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x8BC), - MX51_PIN_CTL_GRP_DDR_A0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x83C), - MX51_PIN_CTL_GRP_DDR_A1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x848), - MX51_PIN_CTL_GRP_DISP_PKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x868), - MX51_PIN_CTL_DRAM_RAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A4), - MX51_PIN_CTL_DRAM_CAS = _MXC_BUILD_NON_GPIO_PIN(0, 0x4A8), - MX51_PIN_CTL_DRAM_SDWE = _MXC_BUILD_NON_GPIO_PIN(0, 0x4Ac), - MX51_PIN_CTL_DRAM_SDCKE0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B0), - MX51_PIN_CTL_DRAM_SDCKE1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B4), - MX51_PIN_CTL_DRAM_SDCLK = _MXC_BUILD_NON_GPIO_PIN(0, 0x4B8), - MX51_PIN_CTL_DRAM_SDQS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4BC), - MX51_PIN_CTL_DRAM_SDQS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C0), - MX51_PIN_CTL_DRAM_SDQS2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C4), - MX51_PIN_CTL_DRAM_SDQS3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4C8), - MX51_PIN_CTL_DRAM_CS0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4CC), - MX51_PIN_CTL_DRAM_CS1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D0), - MX51_PIN_CTL_DRAM_DQM0 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D4), - MX51_PIN_CTL_DRAM_DQM1 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4D8), - MX51_PIN_CTL_DRAM_DQM2 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4DC), - MX51_PIN_CTL_DRAM_DQM3 = _MXC_BUILD_NON_GPIO_PIN(0, 0x4E0), -}; - -#endif /* __ASSEMBLY__ */ -#endif /* __ASM_ARCH_MXC_MX51_PINS_H__ */ diff --git a/arch/arm/include/asm/arch-mx51/sys_proto.h b/arch/arm/include/asm/arch-mx51/sys_proto.h deleted file mode 100644 index f687503cada..00000000000 --- a/arch/arm/include/asm/arch-mx51/sys_proto.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2009 - * Stefano Babic, DENX Software Engineering, sbabic@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -u32 get_cpu_rev(void); -#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev) -void sdelay(unsigned long); - -#endif diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 84386e6c8ff..c8d7d3964e3 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index c991ee271ec..ce4cb78e981 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -26,7 +26,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/boards.cfg b/boards.cfg index 4c736802760..884d9bacb63 100644 --- a/boards.cfg +++ b/boards.cfg @@ -46,8 +46,8 @@ pm9263 arm arm926ejs - ronetix at91 jadecpu arm arm926ejs jadecpu syteco mb86r0x suen3 arm arm926ejs km_arm keymile kirkwood rd6281a arm arm926ejs - Marvell kirkwood -mx51evk arm armv7 mx51evk freescale mx51 -vision2 arm armv7 vision2 ttcontrol mx51 +mx51evk arm armv7 mx51evk freescale mx5 +vision2 arm armv7 vision2 ttcontrol mx5 actux1 arm ixp actux2 arm ixp actux3 arm ixp diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 8864f3ab780..61654732706 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -30,8 +30,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_SKIP_RELOCATE_UBOOT -#define CONFIG_MX51_HCLK_FREQ 24000000 /* RedBoot says 26MHz */ -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 44a6f8be696..a2ecbe50d63 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -29,8 +29,8 @@ #define CONFIG_MX51 /* in a mx51 */ #define CONFIG_L2_OFF -#define CONFIG_MX51_HCLK_FREQ 24000000 -#define CONFIG_MX51_CLK32 32768 +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.3.1 From a6bd9e83abc811d5cade88cb5e7caf93b4f7abe1 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 13 Oct 2010 13:57:33 -0600 Subject: FDT: Add fixup support for multiple banks of memory Add fdt_fixup_memory_banks and reimplement fdt_fixup_memory using it. Tested on OMAP3 beagle board with two banks of memory. Signed-off-by: John Rigby CC: Jerry Van Baren Acked-by: Gerald Van Baren --- common/fdt_support.c | 86 +++++++++++++++++++++++++++------------------------ include/fdt_support.h | 1 + 2 files changed, 47 insertions(+), 40 deletions(-) (limited to 'include') diff --git a/common/fdt_support.c b/common/fdt_support.c index b8a3dc969b6..90e909795b0 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -362,10 +362,40 @@ void do_fixup_by_compat_u32(void *fdt, const char *compat, do_fixup_by_compat(fdt, compat, prop, &val, 4, create); } -int fdt_fixup_memory(void *blob, u64 start, u64 size) +/* + * Get cells len in bytes + * if #NNNN-cells property is 2 then len is 8 + * otherwise len is 4 + */ +static int get_cells_len(void *blob, char *nr_cells_name) +{ + const u32 *cell; + + cell = fdt_getprop(blob, 0, nr_cells_name, NULL); + if (cell && *cell == 2) + return 8; + + return 4; +} + +/* + * Write a 4 or 8 byte big endian cell + */ +static void write_cell(u8 *addr, u64 val, int size) { - int err, nodeoffset, len = 0; - u8 tmp[16]; + int shift = (size - 1) * 8; + while (size-- > 0) { + *addr++ = (val >> shift) & 0xff; + shift -= 8; + } +} + +int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks) +{ + int err, nodeoffset; + int addr_cell_len, size_cell_len, len; + u8 tmp[banks * 8]; + int bank; const u32 *addrcell, *sizecell; err = fdt_check_header(blob); @@ -391,44 +421,15 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) return err; } - addrcell = fdt_getprop(blob, 0, "#address-cells", NULL); - /* use shifts and mask to ensure endianness */ - if ((addrcell) && (*addrcell == 2)) { - tmp[0] = (start >> 56) & 0xff; - tmp[1] = (start >> 48) & 0xff; - tmp[2] = (start >> 40) & 0xff; - tmp[3] = (start >> 32) & 0xff; - tmp[4] = (start >> 24) & 0xff; - tmp[5] = (start >> 16) & 0xff; - tmp[6] = (start >> 8) & 0xff; - tmp[7] = (start ) & 0xff; - len = 8; - } else { - tmp[0] = (start >> 24) & 0xff; - tmp[1] = (start >> 16) & 0xff; - tmp[2] = (start >> 8) & 0xff; - tmp[3] = (start ) & 0xff; - len = 4; - } + addr_cell_len = get_cells_len(blob, "#address-cells"); + size_cell_len = get_cells_len(blob, "#size-cells"); - sizecell = fdt_getprop(blob, 0, "#size-cells", NULL); - /* use shifts and mask to ensure endianness */ - if ((sizecell) && (*sizecell == 2)) { - tmp[0+len] = (size >> 56) & 0xff; - tmp[1+len] = (size >> 48) & 0xff; - tmp[2+len] = (size >> 40) & 0xff; - tmp[3+len] = (size >> 32) & 0xff; - tmp[4+len] = (size >> 24) & 0xff; - tmp[5+len] = (size >> 16) & 0xff; - tmp[6+len] = (size >> 8) & 0xff; - tmp[7+len] = (size ) & 0xff; - len += 8; - } else { - tmp[0+len] = (size >> 24) & 0xff; - tmp[1+len] = (size >> 16) & 0xff; - tmp[2+len] = (size >> 8) & 0xff; - tmp[3+len] = (size ) & 0xff; - len += 4; + for (bank = 0, len = 0; bank < banks; bank++) { + write_cell(tmp + len, start[bank], addr_cell_len); + len += addr_cell_len; + + write_cell(tmp + len, size[bank], size_cell_len); + len += size_cell_len; } err = fdt_setprop(blob, nodeoffset, "reg", tmp, len); @@ -440,6 +441,11 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) return 0; } +int fdt_fixup_memory(void *blob, u64 start, u64 size) +{ + return fdt_fixup_memory_banks(blob, &start, &size, 1); +} + void fdt_fixup_ethernet(void *fdt) { int node, i, j; diff --git a/include/fdt_support.h b/include/fdt_support.h index deb5dda5c76..ce6817b6d34 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -48,6 +48,7 @@ void do_fixup_by_compat(void *fdt, const char *compat, void do_fixup_by_compat_u32(void *fdt, const char *compat, const char *prop, u32 val, int create); int fdt_fixup_memory(void *blob, u64 start, u64 size); +int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks); void fdt_fixup_ethernet(void *fdt); int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); -- cgit v1.3.1 From fca43cc8018327cbe13e943932fbf75772275192 Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 13 Oct 2010 13:57:35 -0600 Subject: boot: change some arch ifdefs to feature ifdefs The routines boot_ramdisk_high, boot_get_cmdline and boot_get_kbd are currently enabled by various combinations of CONFIG_M68K, CONFIG_POWERPC and CONFIG_SPARC. Use CONFIG_SYS_BOOT_ defines instead. CONFIG_SYS_BOOT_RAMDISK_HIGH CONFIG_SYS_BOOT_GET_CMDLINE CONFIG_SYS_BOOT_GET_KBD Define these as appropriate in arch/include/asm/config.h files. Signed-off-by: John Rigby Acked-by: Wolfgang Denk --- README | 13 +++++++++++++ arch/m68k/include/asm/config.h | 3 +++ arch/powerpc/include/asm/config.h | 3 +++ arch/sparc/include/asm/config.h | 1 + common/cmd_bootm.c | 4 ++-- common/image.c | 10 ++++++---- include/image.h | 9 ++++++--- 7 files changed, 34 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/README b/README index a52f3bf9a83..a507a1f434b 100644 --- a/README +++ b/README @@ -2275,6 +2275,19 @@ Configuration Settings: all data for the Linux kernel must be between "bootm_low" and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. +- CONFIG_SYS_BOOT_RAMDISK_HIGH: + Enable initrd_high functionality. If defined then the + initrd_high feature is enabled and the bootm ramdisk subcommand + is enabled. + +- CONFIG_SYS_BOOT_GET_CMDLINE: + Enables allocating and saving kernel cmdline in space between + "bootm_low" and "bootm_low" + BOOTMAPSZ. + +- CONFIG_SYS_BOOT_GET_KBD: + Enables allocating and saving a kernel copy of the bd_info in + space between "bootm_low" and "bootm_low" + BOOTMAPSZ. + - CONFIG_SYS_MAX_FLASH_BANKS: Max number of Flash memory banks diff --git a/arch/m68k/include/asm/config.h b/arch/m68k/include/asm/config.h index 36438be112f..ec2cc16beba 100644 --- a/arch/m68k/include/asm/config.h +++ b/arch/m68k/include/asm/config.h @@ -22,5 +22,8 @@ #define _ASM_CONFIG_H_ #define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define CONFIG_SYS_BOOT_GET_CMDLINE +#define CONFIG_SYS_BOOT_GET_KBD #endif diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index d0986570e29..a1942ca2bd9 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -22,6 +22,9 @@ #define _ASM_CONFIG_H_ #define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH +#define CONFIG_SYS_BOOT_GET_CMDLINE +#define CONFIG_SYS_BOOT_GET_KBD #ifndef CONFIG_MAX_MEM_MAPPED #if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx) diff --git a/arch/sparc/include/asm/config.h b/arch/sparc/include/asm/config.h index 36438be112f..6ddc3494c6b 100644 --- a/arch/sparc/include/asm/config.h +++ b/arch/sparc/include/asm/config.h @@ -22,5 +22,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_LMB +#define CONFIG_SYS_BOOT_RAMDISK_HIGH #endif diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 25bc39ceb7c..ce3c77c6157 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -472,7 +472,7 @@ static int bootm_start_standalone(ulong iflag, int argc, char * const argv[]) static cmd_tbl_t cmd_bootm_sub[] = { U_BOOT_CMD_MKENT(start, 0, 1, (void *)BOOTM_STATE_START, "", ""), U_BOOT_CMD_MKENT(loados, 0, 1, (void *)BOOTM_STATE_LOADOS, "", ""), -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH U_BOOT_CMD_MKENT(ramdisk, 0, 1, (void *)BOOTM_STATE_RAMDISK, "", ""), #endif #ifdef CONFIG_OF_LIBFDT @@ -528,7 +528,7 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv lmb_reserve(&images.lmb, images.os.load, (load_end - images.os.load)); break; -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH case BOOTM_STATE_RAMDISK: { ulong rd_len = images.rd_end - images.rd_start; diff --git a/common/image.c b/common/image.c index dda302566f0..385464d3eb0 100644 --- a/common/image.c +++ b/common/image.c @@ -992,7 +992,7 @@ int boot_get_ramdisk (int argc, char * const argv[], bootm_headers_t *images, return 0; } -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH /** * boot_ramdisk_high - relocate init ramdisk * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -1081,7 +1081,7 @@ int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, error: return -1; } -#endif /* defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_SPARC) */ +#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ #ifdef CONFIG_OF_LIBFDT static void fdt_error (const char *msg) @@ -1588,7 +1588,7 @@ error: } #endif /* CONFIG_OF_LIBFDT */ -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE /** * boot_get_cmdline - allocate and initialize kernel cmdline * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -1630,7 +1630,9 @@ int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, return 0; } +#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ +#ifdef CONFIG_SYS_BOOT_GET_KBD /** * boot_get_kbd - allocate and initialize kernel copy of board info * @lmb: pointer to lmb handle, will be used for memory mgmt @@ -1663,7 +1665,7 @@ int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base) return 0; } -#endif /* CONFIG_PPC || CONFIG_M68K */ +#endif /* CONFIG_SYS_BOOT_GET_KBD */ #endif /* !USE_HOSTCC */ #if defined(CONFIG_FIT) diff --git a/include/image.h b/include/image.h index 18a9f0e964d..49d62805c33 100644 --- a/include/image.h +++ b/include/image.h @@ -340,14 +340,17 @@ int boot_relocate_fdt (struct lmb *lmb, ulong bootmap_base, char **of_flat_tree, ulong *of_size); #endif -#if defined(CONFIG_PPC) || defined(CONFIG_M68K) +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH int boot_ramdisk_high (struct lmb *lmb, ulong rd_data, ulong rd_len, ulong *initrd_start, ulong *initrd_end); - +#endif /* CONFIG_SYS_BOOT_RAMDISK_HIGH */ +#ifdef CONFIG_SYS_BOOT_GET_CMDLINE int boot_get_cmdline (struct lmb *lmb, ulong *cmd_start, ulong *cmd_end, ulong bootmap_base); +#endif /* CONFIG_SYS_BOOT_GET_CMDLINE */ +#ifdef CONFIG_SYS_BOOT_GET_KBD int boot_get_kbd (struct lmb *lmb, bd_t **kbd, ulong bootmap_base); -#endif /* CONFIG_PPC || CONFIG_M68K */ +#endif /* CONFIG_SYS_BOOT_GET_KBD */ #endif /* !USE_HOSTCC */ /*******************************************************************/ -- cgit v1.3.1 From b485556be51d1edae0a2c0065e2f572ca42a1eee Mon Sep 17 00:00:00 2001 From: John Rigby Date: Wed, 13 Oct 2010 13:57:37 -0600 Subject: ARM: enable device tree for beagle For testing ARM device tree support Signed-off-by: John Rigby Acked-by: Wolfgang Denk --- include/configs/omap3_beagle.h | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'include') diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index bbb1073a76c..900dbd3f7a0 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -55,6 +55,15 @@ #undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R +#define CONFIG_OF_LIBFDT 1 +/* + * The early kernel mapping on ARM currently only maps from the base of DRAM + * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. + * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, + * so that leaves DRAM base to DRAM base + 0x4000 available. + */ +#define CONFIG_SYS_BOOTMAPSZ 0x4000 + #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 -- cgit v1.3.1 From 68a75d0b544fb8e7efb85bed1597285f61186cef Mon Sep 17 00:00:00 2001 From: Magnus Lilja Date: Sat, 16 Oct 2010 19:47:06 +0200 Subject: i.MX31: Fix Litekit board to use new ARM relocation support. Tested on hardware. Boots Linux nicely. Signed-off-by: Magnus Lilja --- board/logicpd/imx31_litekit/config.mk | 2 +- board/logicpd/imx31_litekit/imx31_litekit.c | 10 ++++++++-- include/configs/imx31_litekit.h | 7 +++++++ 3 files changed, 16 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/logicpd/imx31_litekit/config.mk b/board/logicpd/imx31_litekit/config.mk index d34dc02d96a..a12c1824bf8 100644 --- a/board/logicpd/imx31_litekit/config.mk +++ b/board/logicpd/imx31_litekit/config.mk @@ -1 +1 @@ -TEXT_BASE = 0x87f00000 +TEXT_BASE = 0xa0000000 diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c index 2ac622dbbe3..a07ba0efc7e 100644 --- a/board/logicpd/imx31_litekit/imx31_litekit.c +++ b/board/logicpd/imx31_litekit/imx31_litekit.c @@ -31,12 +31,18 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->ram_size = PHYS_SDRAM_1_SIZE; return 0; } +void +dram_init_banksize (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + int board_init (void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 88c62d11e1b..94252371bc3 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -147,6 +147,13 @@ #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE CSD0_BASE +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + /*----------------------------------------------------------------------- * FLASH and environment organization */ -- cgit v1.3.1 From b952c24adeb7bfdb09f60d5d1f49fa86a2686c1c Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 19 Oct 2010 11:10:06 +0200 Subject: QONG: fix and update board config file Fix flash memory map and other updates for QONG board: - adjust/fix "kernel_addr" settings - adjust/fix mtdparts NOR flash settings - add mtdparts NAND flash mapping - sort command list - enable "setexpr" command - enable ext2 support - delete bogus comment Signed-off-by: Wolfgang Denk Cc: Stefano Babic --- include/configs/qong.h | 32 ++++++++++++++------------------ 1 file changed, 14 insertions(+), 18 deletions(-) (limited to 'include') diff --git a/include/configs/qong.h b/include/configs/qong.h index f26ced1d7f3..426d90d7dea 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -102,6 +102,7 @@ #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #endif /* CONFIG_CMD_USB */ @@ -124,25 +125,16 @@ #include #define CONFIG_CMD_CACHE -#define CONFIG_CMD_PING +#define CONFIG_CMD_DATE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_NET #define CONFIG_CMD_MII #define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR #define CONFIG_CMD_SPI -#define CONFIG_CMD_DATE -#define BOARD_LATE_INIT -/* - * You can compile in a MAC address and your custom net settings by using - * the following syntax. - * - * #define CONFIG_ETHADDR xx:xx:xx:xx:xx:xx - * #define CONFIG_SERVERIP - * #define CONFIG_IPADDR - * #define CONFIG_GATEWAYIP - * #define CONFIG_NETMASK - */ +#define BOARD_LATE_INIT #define CONFIG_BOOTDELAY 5 @@ -164,7 +156,7 @@ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ "addmisc=setenv bootargs ${bootargs}\0" \ "uboot_addr=A0000000\0" \ - "kernel_addr=A00A0000\0" \ + "kernel_addr=A00C0000\0" \ "ramdisk_addr=A0300000\0" \ "u-boot=qong/u-boot.bin\0" \ "kernel_addr_r=80800000\0" \ @@ -296,10 +288,14 @@ extern int qong_nand_rdy(void *chip); #define CONFIG_LZO #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=physmap-flash.0" +#define MTDIDS_DEFAULT "nor0=physmap-flash.0," \ + "nand0=gen_nand" #define MTDPARTS_DEFAULT \ - "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ - "128k(env2),2432k(kernel),13m(ramdisk),-(user)" + "mtdparts=physmap-flash.0:" \ + "512k(U-Boot),128k(env1),128k(env2)," \ + "2304k(kernel),13m(ramdisk),-(user);" \ + "gen_nand:" \ + "128m(nand)" /* additions for new relocation code, must be added to all boards */ #define CONFIG_SYS_SDRAM_BASE 0x80000000 -- cgit v1.3.1 From 99fa97e955f642deedb9f2de38e0215a8b3a40ac Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 18 Oct 2010 22:58:29 +0200 Subject: at91rm9200ek: convert to at91 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch removes some functionality from at91rm9200ek board but the remaining functionality does now work with newer at91 code and arm-relocation. Currently missing features are: - dataflash booting (due to missing HW for testing) - MMC/SD-Card - first stage bootloader support is completely removed (not needed for NOR) Cause this board was (some days ago) reference for all at91rm9200 based boards this should be a good starting point to convert all remaining at91rm9200 borads to at91 code. Aside from that this is a good base to get some drivers between at91sam/at91rm/avr32 merged. Signed-off-by: Andreas Bießmann Signed-off-by: Reinhard Meyer --- MAINTAINERS | 4 + board/atmel/at91rm9200ek/Makefile | 5 - board/atmel/at91rm9200ek/at91rm9200ek.c | 60 ++----- board/atmel/at91rm9200ek/config.mk | 3 +- board/atmel/at91rm9200ek/led.c | 58 ++++--- board/atmel/at91rm9200ek/misc.c | 50 ------ board/atmel/at91rm9200ek/mux.c | 38 ----- board/atmel/at91rm9200ek/partition.c | 38 ----- boards.cfg | 2 +- include/configs/at91rm9200ek.h | 275 +++++++++----------------------- 10 files changed, 124 insertions(+), 409 deletions(-) delete mode 100644 board/atmel/at91rm9200ek/misc.c delete mode 100644 board/atmel/at91rm9200ek/mux.c delete mode 100644 board/atmel/at91rm9200ek/partition.c (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 5108c547bf2..4db587a708d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -573,6 +573,10 @@ Rishi Bhattacharya omap5912osk ARM926EJS +Andreas Bießmann + + at91rm9200ek at91rm9200 + Cliff Brake pxa255_idp xscale diff --git a/board/atmel/at91rm9200ek/Makefile b/board/atmel/at91rm9200ek/Makefile index 500ce720f35..96a0f055ac0 100644 --- a/board/atmel/at91rm9200ek/Makefile +++ b/board/atmel/at91rm9200ek/Makefile @@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o COBJS-y += led.o -COBJS-y += misc.o -ifdef CONFIG_HAS_DATAFLASH -COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o -COBJS-y += partition.o -endif SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/atmel/at91rm9200ek/at91rm9200ek.c b/board/atmel/at91rm9200ek/at91rm9200ek.c index 570a09a0741..d242583e37f 100644 --- a/board/atmel/at91rm9200ek/at91rm9200ek.c +++ b/board/atmel/at91rm9200ek/at91rm9200ek.c @@ -1,4 +1,8 @@ /* + * (C) Copyright 2010 Andreas Bießmann + * + * derived from previous work + * * (C) Copyright 2002 * Sysgo Real-Time Solutions, GmbH * Marius Groeger @@ -23,78 +27,44 @@ */ #include -#include #include -#include +#include +#include +#include #include -#if defined(CONFIG_DRIVER_ETHER) -#include -#include -#endif DECLARE_GLOBAL_DATA_PTR; /* ------------------------------------------------------------------------- */ -/* - * Miscelaneous platform dependent initialisations - */ - -int board_init (void) +int board_init(void) { - /* Enable Ctrlc */ - console_init_f (); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; /* * Correct IRDA resistor problem * Set PA23_TXD in Output */ - writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER); - - /* - * memory and cpu-speed are setup before relocation - * so we do _nothing_ here - */ + writel(AT91_PMX_AA_TXD2, &pio->pioa.oer); /* arch number of AT91RM9200EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; return 0; } int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } -#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET) -/* - * Name: - * at91rm9200_GetPhyInterface - * Description: - * Initialise the interface functions to the PHY - * Arguments: - * None - * Return value: - * None - */ -void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops) -{ - p_phyops->Init = dm9161_InitPhy; - p_phyops->IsPhyConnected = dm9161_IsPhyConnected; - p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed; - p_phyops->AutoNegotiate = dm9161_AutoNegotiate; -} -#endif - #ifdef CONFIG_DRIVER_AT91EMAC int board_eth_init(bd_t *bis) { - int rc = 0; - rc = at91emac_register(bis, 0); - return rc; + return at91emac_register(bis, (u32) AT91_EMAC_BASE); } #endif diff --git a/board/atmel/at91rm9200ek/config.mk b/board/atmel/at91rm9200ek/config.mk index 207769233ee..c7323fe4776 100644 --- a/board/atmel/at91rm9200ek/config.mk +++ b/board/atmel/at91rm9200ek/config.mk @@ -1 +1,2 @@ -CONFIG_SYS_TEXT_BASE = 0x21f00000 +# currently only NOR flash booting is supported +CONFIG_SYS_TEXT_BASE = 0x10000000 diff --git a/board/atmel/at91rm9200ek/led.c b/board/atmel/at91rm9200ek/led.c index 9464952211b..8d512e0329c 100644 --- a/board/atmel/at91rm9200ek/led.c +++ b/board/atmel/at91rm9200ek/led.c @@ -3,6 +3,9 @@ * Atmel Nordic AB * Ulf Samuelsson * + * (C) Copyright 2010 + * Andreas Bießmann + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,67 +26,62 @@ */ #include -#include -#include +#include +#include -#define GREEN_LED AT91C_PIO_PB0 -#define YELLOW_LED AT91C_PIO_PB1 -#define RED_LED AT91C_PIO_PB2 +/* bit mask in PIO port B */ +#define GREEN_LED (1<<0) +#define YELLOW_LED (1<<1) +#define RED_LED (1<<2) void green_LED_on(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(GREEN_LED, PIOB->PIO_CODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(GREEN_LED, &pio->piob.codr); } void yellow_LED_on(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(YELLOW_LED, PIOB->PIO_CODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(YELLOW_LED, &pio->piob.codr); } void red_LED_on(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(RED_LED, PIOB->PIO_CODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(RED_LED, &pio->piob.codr); } void green_LED_off(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(GREEN_LED, PIOB->PIO_SODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(GREEN_LED, &pio->piob.sodr); } void yellow_LED_off(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(YELLOW_LED, PIOB->PIO_SODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(YELLOW_LED, &pio->piob.sodr); } void red_LED_off(void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - - writel(RED_LED, PIOB->PIO_SODR); + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; + writel(RED_LED, &pio->piob.sodr); } - void coloured_LED_init (void) { - AT91PS_PIO PIOB = AT91C_BASE_PIOB; - AT91PS_PMC PMC = AT91C_BASE_PMC; + at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE; + at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE; /* Enable PIOB clock */ - writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER); + writel(1 << AT91_ID_PIOB, &pmc->pcer); + /* Disable peripherals on LEDs */ - writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER); + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per); /* Enable pins as outputs */ - writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER); + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer); /* Turn all LEDs OFF */ - writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR); + writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr); } diff --git a/board/atmel/at91rm9200ek/misc.c b/board/atmel/at91rm9200ek/misc.c deleted file mode 100644 index 81de32f79f6..00000000000 --- a/board/atmel/at91rm9200ek/misc.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include - -int board_late_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - - /* Fix Ethernet Initialization Bug when starting Linux from U-Boot */ - eth_init(gd->bd); - return 0; -} - - -/* checks if addr is in RAM */ -int addr2ram(ulong addr) -{ - int result = 0; - - if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE))) - result = 1; - - return result; -} diff --git a/board/atmel/at91rm9200ek/mux.c b/board/atmel/at91rm9200ek/mux.c deleted file mode 100644 index bdd44e8cf73..00000000000 --- a/board/atmel/at91rm9200ek/mux.c +++ /dev/null @@ -1,38 +0,0 @@ -#include -#include -#include -#include -#include - -int AT91F_GetMuxStatus(void) -{ - /* Set in PIO mode */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER); - /* Configure in output */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER); - - if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO) - return 1; - - return 0; -} - -void AT91F_SelectMMC(void) -{ - /* Set in PIO mode */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER); - /* Configure in output */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER); - /* Set Output */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR); -} - -void AT91F_SelectSPI(void) -{ - /* Set in PIO mode */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER); - /* Configure in output */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER); - /* Clear Output */ - writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR); -} diff --git a/board/atmel/at91rm9200ek/partition.c b/board/atmel/at91rm9200ek/partition.c deleted file mode 100644 index 990cbcff12f..00000000000 --- a/board/atmel/at91rm9200ek/partition.c +++ /dev/null @@ -1,38 +0,0 @@ -/* - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ -#include -#include -#include -#include - -AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; - -struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */ - {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3} -}; - -/*define the area offsets*/ -dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { - {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"}, - {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"}, - {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"}, - {0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"}, - {0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"}, -}; diff --git a/boards.cfg b/boards.cfg index 3a965e9dc52..62c50755225 100644 --- a/boards.cfg +++ b/boards.cfg @@ -344,7 +344,7 @@ modnet50 arm arm720t lpc2292sodimm arm arm720t - - lpc2292 eb_cpux9k2 arm arm920t - BuS at91 at91rm9200dk arm arm920t - atmel at91rm9200 -at91rm9200ek arm arm920t - atmel at91rm9200 +at91rm9200ek arm arm920t - atmel at91 sbc2410x arm arm920t - - s3c24x0 smdk2400 arm arm920t - samsung s3c24x0 smdk2410 arm arm920t - samsung s3c24x0 diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 145c3c37dac..6b2dd63b47d 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -1,4 +1,8 @@ /* + * Copyright (C) 2010 Andreas Bießmann + * + * based on previous work by + * * Ulf Samuelsson * Rick Bronson * @@ -23,40 +27,52 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __AT91RM9200EK_CONFIG_H__ +#define __AT91RM9200EK_CONFIG_H__ -#define CONFIG_AT91_LEGACY +#include -/* ARM asynchronous clock */ -/* - * from 18.432 MHz crystal - * (18432000 / 4 * 39) - */ -#define AT91C_MAIN_CLOCK 179712000 /* - * peripheral clock - * (AT91C_MASTER_CLOCK / 3) + * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz + * AT91C_MAIN_CLOCK is the frequency of PLLA output + * AT91C_MASTER_CLOCK is the peripherial clock + * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely + * set in arch/arm/cpu/arm920t/at91/timer.c) + * CONFIG_SYS_HZ is the tick rate for timer tc0 */ -#define AT91C_MASTER_CLOCK 59904000 +#define AT91C_XTAL_CLOCK 18432000 +#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) +#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) +#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) +#define CONFIG_SYS_HZ 1000 -#define AT91_SLOW_CLOCK 32768 /* slow clock */ +/* CPU configuration */ +#define CONFIG_ARM920T +#define CONFIG_AT91RM9200 +#define CONFIG_AT91RM9200EK +#define CONFIG_CPUAT91 +#define USE_920T_MMU -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */ -#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */ -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ -#define USE_920T_MMU 1 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Memory Configuration + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE SZ_32M -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END \ + (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) /* * LowLevel Init */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1 +#define CONFIG_SYS_USE_MAIN_OSCILLATOR /* flash */ #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ @@ -73,50 +89,26 @@ #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 #define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */ +#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ +#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ #define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ #define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ #define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#else -#define CONFIG_SKIP_RELOCATE_UBOOT #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */ -#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33 - -/* - * Memory Configuration - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144) - /* * Hardware drivers */ - /* - * UART Configuration - * - * define one of these to choose the DBGU, - * USART0 or USART1 as console + * Choose a USART for serial console + * CONFIG_DBGU is DBGU unit on J10 + * CONFIG_USART1 is USART1 on J14 */ #define CONFIG_AT91RM9200_USART #define CONFIG_DBGU -#undef CONFIG_USART0 -#undef CONFIG_USART1 -/* don't include RTS/CTS flow control support */ -#undef CONFIG_HWFLOW -/* disable modem initialization stuff */ -#undef CONFIG_MODEM_SUPPORT #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } #define CONFIG_BAUDRATE 115200 @@ -130,156 +122,60 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MII #define CONFIG_CMD_PING - -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_IMI #undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_LOADS - -#include /* needed for port definitions */ -/* Options for MMC/SD Card */ -#define CONFIG_DOS_PARTITION 1 -#undef CONFIG_MMC -#define CONFIG_SYS_MMC_BASE 0xFFFB4000 -#define CONFIG_SYS_MMC_BLOCKSIZE 512 /* * Network Driver Setting */ -#define CONFIG_NET_MULTI 1 -#ifdef CONFIG_NET_MULTI -#define CONFIG_DRIVER_AT91EMAC 1 -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#else -#define CONFIG_DRIVER_ETHER 1 -#endif -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91C_USE_RMII - -/* - * AC Characteristics - * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns - */ -#define DATAFLASH_TCSS (0xC << 16) -#define DATAFLASH_TCHS (0x1 << 24) - -#if defined(CONFIG_HAS_DATAFLASH) -#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) -#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 -#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384 -/* Logical adress for CS0 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 -/* Logical adress for CS3 */ -#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 -#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1 -#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22 -#endif +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_AT91EMAC +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_RMII +#define CONFIG_MII /* * NOR Flash */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define PHYS_FLASH_SIZE 0x800000 /* 8MB */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE +#define PHYS_FLASH_SIZE SZ_8M +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_FLASH_PROTECTION /* * Environment Settings */ -#ifdef CONFIG_ENV_IS_IN_DATAFLASH -/* - * Datasflash Environment Settings - */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) -/* 8 * 1056 really , but start.s is not OK with this*/ -#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_IS_IN_FLASH -#else -/* - * NOR Flash Environment Settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -/* - * between boot.bin and u-boot.bin.gz - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ -#else /* * after u-boot.bin */ #define CONFIG_ENV_ADDR \ (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */ +#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */ /* The following #defines are needed to get flash environment right */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN \ - (CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE) -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#endif /* CONFIG_ENV_IS_IN_DATAFLASH */ +#define CONFIG_SYS_MONITOR_LEN SZ_256K /* * Boot option */ #define CONFIG_BOOTDELAY 3 -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -/* boot.bin, env, u-boot.bin.gz */ -#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000) -#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */ -#else -/* u-boot.bin */ -#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */ -#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ -#define CONFIG_ENV_OVERWRITE 1 - -/* - * USB Config - */ -#define CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 - -#undef CONFIG_SYS_USB_OHCI_BOARD_INIT -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * I2C - */ -#define CONFIG_HARD_I2C - -#ifdef CONFIG_HARD_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_SPEED 0 /* not used */ -#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ -#endif +/* default load address */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M +#define CONFIG_ENV_OVERWRITE /* * Shell Settings */ -#define CONFIG_CMDLINE_EDITING 1 -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_AUTO_COMPLETE 1 -#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT "U-Boot> " #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ @@ -288,41 +184,18 @@ #define CONFIG_SYS_PBSIZE \ (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#ifndef __ASSEMBLY__ -/*----------------------------------------------------------------------- - * Board specific extension for bd_info - * - * This structure is embedded in the global bd_info (bd_t) structure - * and can be used by the board specific code (eg board/...) - */ - -struct bd_info_ext { - /* helper variable for board environment handling - * - * env_crc_valid == 0 => uninitialised - * env_crc_valid > 0 => environment crc in flash is valid - * env_crc_valid < 0 => environment crc in flash is invalid - */ - int env_crc_valid; -}; -#endif - -#define CONFIG_SYS_HZ 1000 -/* - * AT91C_TC0_CMR is implicitly set to - * AT91C_TC_TIMER_DIV1_CLOCK - */ -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \ - , 0x1000) +#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ + SZ_4K) /* size in bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */ -#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/ -#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/ -#endif +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ + - CONFIG_SYS_GBL_DATA_SIZE) + +#define CONFIG_STACKSIZE SZ_32K /* regular stack */ +#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/ +#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/ +#endif /* __AT91RM9200EK_CONFIG_H__ */ -- cgit v1.3.1 From 3b83522bcf99bb4cdf1b792f391e3b93b6ed5ce5 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Mon, 18 Oct 2010 22:58:31 +0200 Subject: at91rm9200ek: enbable USB support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch enables USB for at91rm9200ek board. Signed-off-by: Andreas Bießmann Signed-off-by: Reinhard Meyer --- include/configs/at91rm9200ek.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'include') diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index 6b2dd63b47d..b386057c0ef 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -122,6 +122,7 @@ #define CONFIG_CMD_FAT #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_USB #undef CONFIG_CMD_FPGA /* @@ -145,6 +146,20 @@ #define CONFIG_SYS_MAX_FLASH_SECT 256 #define CONFIG_SYS_FLASH_PROTECTION +/* + * USB Config + */ +#define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_OHCI_NEW 1 +#define CONFIG_USB_KEYBOARD 1 +#define CONFIG_USB_STORAGE 1 +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 +#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 + /* * Environment Settings */ -- cgit v1.3.1 From 3ba8bf7c6d6c09b9823b08b03d2d155907313238 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 9 Sep 2010 09:50:39 +0200 Subject: PXA: pxa-regs.h cleanup Signed-off-by: Marek Vasut --- arch/arm/cpu/pxa/cpu.c | 28 +- arch/arm/cpu/pxa/i2c.c | 69 +- arch/arm/cpu/pxa/pxafb.c | 64 +- arch/arm/cpu/pxa/timer.c | 7 +- arch/arm/cpu/pxa/usb.c | 61 +- arch/arm/include/asm/arch-pxa/hardware.h | 61 +- arch/arm/include/asm/arch-pxa/pxa-regs.h | 2688 ++++++++++++++++-------------- board/colibri_pxa270/colibri_pxa270.c | 33 +- board/cradle/cradle.c | 5 +- board/cradle/lowlevel_init.S | 4 +- board/csb226/csb226.c | 13 +- board/delta/delta.c | 37 +- board/delta/nand.c | 110 +- board/innokom/innokom.c | 14 +- board/pxa255_idp/pxa_idp.c | 27 +- board/trizepsiv/conxs.c | 33 +- board/vpac270/vpac270.c | 37 +- board/wepep250/wepep250.c | 11 +- board/zipitz2/zipitz2.c | 33 +- board/zylonite/nand.c | 110 +- drivers/mmc/pxa_mmc.c | 98 +- drivers/serial/serial_pxa.c | 94 +- include/configs/cradle.h | 2 - include/configs/delta.h | 1 + include/configs/zylonite.h | 1 + 25 files changed, 1911 insertions(+), 1730 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/pxa/cpu.c b/arch/arm/cpu/pxa/cpu.c index 800d120e718..330d013c6d6 100644 --- a/arch/arm/cpu/pxa/cpu.c +++ b/arch/arm/cpu/pxa/cpu.c @@ -30,10 +30,11 @@ * CPU specific code */ -#include -#include #include +#include #include +#include +#include static void cache_flush(void); @@ -71,17 +72,22 @@ void set_GPIO_mode(int gpio_mode) { int gpio = gpio_mode & GPIO_MD_MASK_NR; int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8; - int gafr; + int val; + + /* This below changes direction setting of GPIO "gpio" */ + val = readl(GPDR(gpio)); if (gpio_mode & GPIO_MD_MASK_DIR) - { - GPDR(gpio) |= GPIO_bit(gpio); - } + val |= GPIO_bit(gpio); else - { - GPDR(gpio) &= ~GPIO_bit(gpio); - } - gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2)); - GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2)); + val &= ~GPIO_bit(gpio); + + writel(val, GPDR(gpio)); + + /* This below updates only AF of GPIO "gpio" */ + val = readl(GAFR(gpio)); + val &= ~(0x3 << (((gpio) & 0xf) * 2)); + val |= fn << (((gpio) & 0xf) * 2); + writel(val, GAFR(gpio)); } #endif /* CONFIG_CPU_MONAHANS */ diff --git a/arch/arm/cpu/pxa/i2c.c b/arch/arm/cpu/pxa/i2c.c index 6b72ba13a09..7aa49ae4a00 100644 --- a/arch/arm/cpu/pxa/i2c.c +++ b/arch/arm/cpu/pxa/i2c.c @@ -33,6 +33,7 @@ /* FIXME: this file is PXA255 specific! What about other XScales? */ #include +#include #ifdef CONFIG_HARD_I2C @@ -93,19 +94,21 @@ struct i2c_msg { static void i2c_reset( void ) { - ICR &= ~ICR_IUE; /* disable unit */ - ICR |= ICR_UR; /* reset the unit */ + writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ + writel(readl(ICR) | ICR_UR, ICR); /* reset the unit */ udelay(100); - ICR &= ~ICR_IUE; /* disable unit */ + writel(readl(ICR) & ~ICR_IUE, ICR); /* disable unit */ #ifdef CONFIG_CPU_MONAHANS - CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ + /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ + writel(readl(CKENB) | (CKENB_4_I2C), CKENB); #else /* CONFIG_CPU_MONAHANS */ - CKEN |= CKEN14_I2C; /* set the global I2C clock on */ + /* set the global I2C clock on */ + writel(readl(CKEN) | CKEN14_I2C, CKEN); #endif - ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ - ICR = I2C_ICR_INIT; /* set control register values */ - ISR = I2C_ISR_INIT; /* set clear interrupt bits */ - ICR |= ICR_IUE; /* enable unit */ + writel(I2C_PXA_SLAVE_ADDR, ISAR); /* set our slave address */ + writel(I2C_ICR_INIT, ICR); /* set control reg values */ + writel(I2C_ISR_INIT, ISR); /* set clear interrupt bits */ + writel(readl(ICR) | ICR_IUE, ICR); /* enable unit */ udelay(100); } @@ -159,22 +162,26 @@ int i2c_transfer(struct i2c_msg *msg) goto transfer_error_bus_busy; /* start transmission */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - IDBR = msg->data; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; + writel(readl(ICR) & ~ICR_START, ICR); + writel(readl(ICR) & ~ICR_STOP, ICR); + writel(msg->data, IDBR); + if (msg->condition == I2C_COND_START) + writel(readl(ICR) | ICR_START, ICR); + if (msg->condition == I2C_COND_STOP) + writel(readl(ICR) | ICR_STOP, ICR); + if (msg->acknack == I2C_ACKNAK_SENDNAK) + writel(readl(ICR) | ICR_ACKNAK, ICR); + if (msg->acknack == I2C_ACKNAK_SENDACK) + writel(readl(ICR) & ~ICR_ACKNAK, ICR); + writel(readl(ICR) & ~ICR_ALDIE, ICR); + writel(readl(ICR) | ICR_TB, ICR); /* transmit register empty? */ if (!i2c_isr_set_cleared(ISR_ITE,0)) goto transfer_error_transmit_timeout; /* clear 'transmit empty' state */ - ISR |= ISR_ITE; + writel(readl(ISR) | ISR_ITE, ISR); /* wait for ACK from slave */ if (msg->acknack == I2C_ACKNAK_WAITACK) @@ -189,23 +196,27 @@ int i2c_transfer(struct i2c_msg *msg) goto transfer_error_bus_busy; /* start receive */ - ICR &= ~ICR_START; - ICR &= ~ICR_STOP; - if (msg->condition == I2C_COND_START) ICR |= ICR_START; - if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; - if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; - if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; - ICR &= ~ICR_ALDIE; - ICR |= ICR_TB; + writel(readl(ICR) & ~ICR_START, ICR); + writel(readl(ICR) & ~ICR_STOP, ICR); + if (msg->condition == I2C_COND_START) + writel(readl(ICR) | ICR_START, ICR); + if (msg->condition == I2C_COND_STOP) + writel(readl(ICR) | ICR_STOP, ICR); + if (msg->acknack == I2C_ACKNAK_SENDNAK) + writel(readl(ICR) | ICR_ACKNAK, ICR); + if (msg->acknack == I2C_ACKNAK_SENDACK) + writel(readl(ICR) & ~ICR_ACKNAK, ICR); + writel(readl(ICR) & ~ICR_ALDIE, ICR); + writel(readl(ICR) | ICR_TB, ICR); /* receive register full? */ if (!i2c_isr_set_cleared(ISR_IRF,0)) goto transfer_error_receive_timeout; - msg->data = IDBR; + msg->data = readl(IDBR); /* clear 'receive empty' state */ - ISR |= ISR_IRF; + writel(readl(ISR) | ISR_IRF, ISR); break; diff --git a/arch/arm/cpu/pxa/pxafb.c b/arch/arm/cpu/pxa/pxafb.c index 50e9cc0b225..cb004b2624a 100644 --- a/arch/arm/cpu/pxa/pxafb.c +++ b/arch/arm/cpu/pxa/pxafb.c @@ -35,6 +35,7 @@ #include #include #include +#include /* #define DEBUG */ @@ -377,12 +378,14 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 4 bit data\n"); /* bits 58-61 */ - GPDR1 |= (0xf << 26); - GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR1) | (0xf << 26), GPDR1); + writel((readl(GAFR1_U) & ~(0xff << 20)) | (0xaa << 20), + GAFR1_U); /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); } /* 8 bit interface */ @@ -391,15 +394,17 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 8 bit data\n"); /* bits 58-65 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= (0x3); + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | (0x3), GPDR2); - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & ~0xf) | (0xa); + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & ~0xf) | (0xa), GAFR2_L); /* bits 74-77 */ - GPDR2 |= (0xf << 10); - GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20); + writel(readl(GPDR2) | (0xf << 10), GPDR2); + writel((readl(GAFR2_L) & ~(0xff << 20)) | (0xaa << 20), + GAFR2_L); } /* 16 bit interface */ @@ -407,11 +412,12 @@ static void pxafb_setup_gpio (vidinfo_t *vid) { debug("Setting GPIO for 16 bit data\n"); /* bits 58-77 */ - GPDR1 |= (0x3f << 26); - GPDR2 |= 0x00003fff; + writel(readl(GPDR1) | (0x3f << 26), GPDR1); + writel(readl(GPDR2) | 0x00003fff, GPDR2); - GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20); - GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa; + writel((readl(GAFR1_U) & ~(0xfff << 20)) | (0xaaa << 20), + GAFR1_U); + writel((readl(GAFR2_L) & 0xf0000000) | 0x0aaaaaaa, GAFR2_L); } else { @@ -425,26 +431,26 @@ static void pxafb_enable_controller (vidinfo_t *vid) debug("Enabling LCD controller\n"); /* Sequence from 11.7.10 */ - LCCR3 = vid->pxa.reg_lccr3; - LCCR2 = vid->pxa.reg_lccr2; - LCCR1 = vid->pxa.reg_lccr1; - LCCR0 = vid->pxa.reg_lccr0 & ~LCCR0_ENB; - FDADR0 = vid->pxa.fdadr0; - FDADR1 = vid->pxa.fdadr1; - LCCR0 |= LCCR0_ENB; + writel(vid->pxa.reg_lccr3, LCCR3); + writel(vid->pxa.reg_lccr2, LCCR2); + writel(vid->pxa.reg_lccr1, LCCR1); + writel(vid->pxa.reg_lccr0 & ~LCCR0_ENB, LCCR0); + writel(vid->pxa.fdadr0, FDADR0); + writel(vid->pxa.fdadr1, FDADR1); + writel(readl(LCCR0) | LCCR0_ENB, LCCR0); #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_1_LCD; + writel(readl(CKENA) | CKENA_1_LCD, CKENA); #else - CKEN |= CKEN16_LCD; + writel(readl(CKEN) | CKEN16_LCD, CKEN); #endif - debug("FDADR0 = 0x%08x\n", (unsigned int)FDADR0); - debug("FDADR1 = 0x%08x\n", (unsigned int)FDADR1); - debug("LCCR0 = 0x%08x\n", (unsigned int)LCCR0); - debug("LCCR1 = 0x%08x\n", (unsigned int)LCCR1); - debug("LCCR2 = 0x%08x\n", (unsigned int)LCCR2); - debug("LCCR3 = 0x%08x\n", (unsigned int)LCCR3); + debug("FDADR0 = 0x%08x\n", readl(FDADR0)); + debug("FDADR1 = 0x%08x\n", readl(FDADR1)); + debug("LCCR0 = 0x%08x\n", readl(LCCR0)); + debug("LCCR1 = 0x%08x\n", readl(LCCR1)); + debug("LCCR2 = 0x%08x\n", readl(LCCR2)); + debug("LCCR3 = 0x%08x\n", readl(LCCR3)); } static int pxafb_init (vidinfo_t *vid) diff --git a/arch/arm/cpu/pxa/timer.c b/arch/arm/cpu/pxa/timer.c index 8d0f82679b0..ec950c79660 100644 --- a/arch/arm/cpu/pxa/timer.c +++ b/arch/arm/cpu/pxa/timer.c @@ -26,8 +26,9 @@ * MA 02111-1307 USA */ -#include #include +#include +#include #include #ifdef CONFIG_USE_IRQ @@ -86,7 +87,7 @@ void __udelay (unsigned long usec) void reset_timer_masked (void) { - OSCR = 0; + writel(0, OSCR); } ulong get_timer_masked (void) @@ -113,7 +114,7 @@ void udelay_masked (unsigned long usec) */ unsigned long long get_ticks(void) { - return OSCR; + return readl(OSCR); } /* diff --git a/arch/arm/cpu/pxa/usb.c b/arch/arm/cpu/pxa/usb.c index bd718a6fff8..0311d5e9978 100644 --- a/arch/arm/cpu/pxa/usb.c +++ b/arch/arm/cpu/pxa/usb.c @@ -27,86 +27,79 @@ # if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) #include +#include #include int usb_cpu_init(void) { #if defined(CONFIG_CPU_MONAHANS) /* Enable USB host clock. */ - CKENA |= (CKENA_2_USBHOST | CKENA_20_UDC); + writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); udelay(100); #endif #if defined(CONFIG_PXA27X) /* Enable USB host clock. */ - CKEN |= CKEN10_USBHOST; + writel(readl(CKEN) | CKEN10_USBHOST, CKEN); #endif #if defined(CONFIG_CPU_MONAHANS) /* Configure Port 2 for Host (USB Client Registers) */ - UP2OCR = 0x3000c; + writel(0x3000c, UP2OCR); #endif - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); wait_ms(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCHR |= UHCHR_FSBIR; - while (UHCHR & UHCHR_FSBIR) + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + while (readl(UHCHR) & UHCHR_FSBIR) udelay(1); #if defined(CONFIG_CPU_MONAHANS) - UHCHR &= ~UHCHR_SSEP0; + writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR &= ~UHCHR_SSEP2; + writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); #endif - UHCHR &= ~UHCHR_SSEP1; - UHCHR &= ~UHCHR_SSE; + writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); return 0; } int usb_cpu_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | UHCHR_FHR, UHCCOMS); udelay(10); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + writel(readl(UHCHR) | UHCHR_SSEP0, UHCHR); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + writel(readl(UHCHR) | UHCHR_SSEP2, UHCHR); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; - - return 0; -} - -int usb_cpu_init_fail(void) -{ - UHCHR |= UHCHR_FHR; - udelay(11); - UHCHR &= ~UHCHR_FHR; - - UHCCOMS |= 1; - udelay(10); + writel(readl(UHCHR) | UHCHR_SSEP1 | UHCHR_SSE, UHCHR); #if defined(CONFIG_CPU_MONAHANS) - UHCHR |= UHCHR_SSEP0; + /* Disable USB host clock. */ + writel(readl(CKENA) & ~(CKENA_2_USBHOST | CKENA_20_UDC), CKENA); + udelay(100); #endif #if defined(CONFIG_PXA27X) - UHCHR |= UHCHR_SSEP2; + /* Disable USB host clock. */ + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); #endif - UHCHR |= UHCHR_SSEP1; - UHCHR |= UHCHR_SSE; return 0; } +int usb_cpu_init_fail(void) +{ + return usb_cpu_stop(); +} + # endif /* defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) */ #endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */ diff --git a/arch/arm/include/asm/arch-pxa/hardware.h b/arch/arm/include/asm/arch-pxa/hardware.h index c8c479a1869..44b800f6816 100644 --- a/arch/arm/include/asm/arch-pxa/hardware.h +++ b/arch/arm/include/asm/arch-pxa/hardware.h @@ -21,6 +21,19 @@ #include #include +/* + * Define CONFIG_CPU_MONAHANS in case some CPU of the PXA3xx family is selected. + * PXA300/310/320 all have distinct register mappings in some cases, that's why + * the exact CPU has to be selected. CONFIG_CPU_MONAHANS is a helper for common + * drivers and compatibility glue with old source then. + */ +#ifndef CONFIG_CPU_MONAHANS +#if defined(CONFIG_CPU_PXA300) || \ + defined(CONFIG_CPU_PXA310) || \ + defined(CONFIG_CPU_PXA320) +#define CONFIG_CPU_MONAHANS +#endif +#endif /* * These are statically mapped PCMCIA IO space for designs using it as a @@ -51,54 +64,6 @@ * 0x48000000 - 0x49ffffff <--> 0xfc000000 - 0xfdffffff */ -/* FIXME: Only this does work for u-boot... find out why... [RS] */ -#define UBOOT_REG_FIX 1 - -#ifndef UBOOT_REG_FIX -#ifndef __ASSEMBLY__ - -#define io_p2v(x) ( ((x) | 0xbe000000) ^ (~((x) >> 1) & 0x06000000) ) -#define io_v2p( x ) ( ((x) & 0x41ffffff) ^ ( ((x) & 0x06000000) << 1) ) - -/* - * This __REG() version gives the same results as the one above, except - * that we are fooling gcc somehow so it generates far better and smaller - * assembly code for access to contigous registers. It's a shame that gcc - * doesn't guess this by itself. - */ -#include -typedef struct { volatile u32 offset[4096]; } __regbase; -# define __REGP(x) ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2] -# define __REG(x) __REGP(io_p2v(x)) -#endif - -/* Let's kick gcc's ass again... */ -# define __REG2(x,y) \ - ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ - : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) - -# define __PREG(x) (io_v2p((u32)&(x))) - -#else - -# define __REG(x) io_p2v(x) -# define __PREG(x) io_v2p(x) - -# undef io_p2v -# undef __REG -# ifndef __ASSEMBLY__ -# define io_p2v(PhAdd) (PhAdd) -# define __REG(x) (*((volatile u32 *)io_p2v(x))) -# define __REG2(x,y) (*(volatile u32 *)((u32)&__REG(x) + (y))) -# else -# define __REG(x) (x) -# ifdef CONFIG_CPU_MONAHANS /* Hack to make this work with mona's pxa-regs.h */ -# define __REG_2(x) (x) -# define __REG_3(x) (x) -# endif -# endif -#endif /* UBOOT_REG_FIX */ - #include "pxa-regs.h" #ifndef __ASSEMBLY__ diff --git a/arch/arm/include/asm/arch-pxa/pxa-regs.h b/arch/arm/include/asm/arch-pxa/pxa-regs.h index d442fb0652e..65a387f9fc9 100644 --- a/arch/arm/include/asm/arch-pxa/pxa-regs.h +++ b/arch/arm/include/asm/arch-pxa/pxa-regs.h @@ -93,42 +93,42 @@ typedef void (*ExcpHndlr) (void) ; /* * DMA Controller */ -#define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */ -#define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */ -#define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */ -#define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */ -#define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */ -#define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */ -#define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */ -#define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */ -#define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */ -#define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */ -#define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */ -#define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */ -#define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */ -#define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */ -#define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */ -#define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */ -#ifdef CONFIG_CPU_MONAHANS -#define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */ -#define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */ -#define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */ -#define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */ -#define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */ -#define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */ -#define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */ -#define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */ -#define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */ -#define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */ -#define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */ -#define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */ -#define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */ -#define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */ -#define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */ -#define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */ -#endif /* CONFIG_CPU_MONAHANS */ - -#define DCSR(x) __REG2(0x40000000, (x) << 2) +#define DCSR0 0x40000000 /* DMA Control / Status Register for Channel 0 */ +#define DCSR1 0x40000004 /* DMA Control / Status Register for Channel 1 */ +#define DCSR2 0x40000008 /* DMA Control / Status Register for Channel 2 */ +#define DCSR3 0x4000000c /* DMA Control / Status Register for Channel 3 */ +#define DCSR4 0x40000010 /* DMA Control / Status Register for Channel 4 */ +#define DCSR5 0x40000014 /* DMA Control / Status Register for Channel 5 */ +#define DCSR6 0x40000018 /* DMA Control / Status Register for Channel 6 */ +#define DCSR7 0x4000001c /* DMA Control / Status Register for Channel 7 */ +#define DCSR8 0x40000020 /* DMA Control / Status Register for Channel 8 */ +#define DCSR9 0x40000024 /* DMA Control / Status Register for Channel 9 */ +#define DCSR10 0x40000028 /* DMA Control / Status Register for Channel 10 */ +#define DCSR11 0x4000002c /* DMA Control / Status Register for Channel 11 */ +#define DCSR12 0x40000030 /* DMA Control / Status Register for Channel 12 */ +#define DCSR13 0x40000034 /* DMA Control / Status Register for Channel 13 */ +#define DCSR14 0x40000038 /* DMA Control / Status Register for Channel 14 */ +#define DCSR15 0x4000003c /* DMA Control / Status Register for Channel 15 */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define DCSR16 0x40000040 /* DMA Control / Status Register for Channel 16 */ +#define DCSR17 0x40000044 /* DMA Control / Status Register for Channel 17 */ +#define DCSR18 0x40000048 /* DMA Control / Status Register for Channel 18 */ +#define DCSR19 0x4000004c /* DMA Control / Status Register for Channel 19 */ +#define DCSR20 0x40000050 /* DMA Control / Status Register for Channel 20 */ +#define DCSR21 0x40000054 /* DMA Control / Status Register for Channel 21 */ +#define DCSR22 0x40000058 /* DMA Control / Status Register for Channel 22 */ +#define DCSR23 0x4000005c /* DMA Control / Status Register for Channel 23 */ +#define DCSR24 0x40000060 /* DMA Control / Status Register for Channel 24 */ +#define DCSR25 0x40000064 /* DMA Control / Status Register for Channel 25 */ +#define DCSR26 0x40000068 /* DMA Control / Status Register for Channel 26 */ +#define DCSR27 0x4000006c /* DMA Control / Status Register for Channel 27 */ +#define DCSR28 0x40000070 /* DMA Control / Status Register for Channel 28 */ +#define DCSR29 0x40000074 /* DMA Control / Status Register for Channel 29 */ +#define DCSR30 0x40000078 /* DMA Control / Status Register for Channel 30 */ +#define DCSR31 0x4000007c /* DMA Control / Status Register for Channel 31 */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +#define DCSR(x) (0x40000000 | ((x) << 2)) #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */ #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */ @@ -150,52 +150,52 @@ typedef void (*ExcpHndlr) (void) ; #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */ #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */ -#define DINT __REG(0x400000f0) /* DMA Interrupt Register */ - -#define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */ -#define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */ -#define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */ -#define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */ -#define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */ -#define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */ -#define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */ -#define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */ -#define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */ -#define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */ -#define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */ -#define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */ -#define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */ -#define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */ -#define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */ -#define DRCMR15 __REG(0x4000013c) /* Reserved */ -#define DRCMR16 __REG(0x40000140) /* Reserved */ -#define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */ -#define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */ -#define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */ -#define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */ -#define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */ -#define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */ -#define DRCMR23 __REG(0x4000015c) /* Reserved */ -#define DRCMR24 __REG(0x40000160) /* Reserved */ -#define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */ -#define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */ -#define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */ -#define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */ -#define DRCMR29 __REG(0x40000174) /* Reserved */ -#define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */ -#define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */ -#define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */ -#define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */ -#define DRCMR34 __REG(0x40000188) /* Reserved */ -#define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */ -#define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */ -#define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */ -#define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */ -#define DRCMR39 __REG(0x4000019C) /* Reserved */ - -#define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */ -#define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */ -#define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */ +#define DINT 0x400000f0 /* DMA Interrupt Register */ + +#define DRCMR0 0x40000100 /* Request to Channel Map Register for DREQ 0 */ +#define DRCMR1 0x40000104 /* Request to Channel Map Register for DREQ 1 */ +#define DRCMR2 0x40000108 /* Request to Channel Map Register for I2S receive Request */ +#define DRCMR3 0x4000010c /* Request to Channel Map Register for I2S transmit Request */ +#define DRCMR4 0x40000110 /* Request to Channel Map Register for BTUART receive Request */ +#define DRCMR5 0x40000114 /* Request to Channel Map Register for BTUART transmit Request. */ +#define DRCMR6 0x40000118 /* Request to Channel Map Register for FFUART receive Request */ +#define DRCMR7 0x4000011c /* Request to Channel Map Register for FFUART transmit Request */ +#define DRCMR8 0x40000120 /* Request to Channel Map Register for AC97 microphone Request */ +#define DRCMR9 0x40000124 /* Request to Channel Map Register for AC97 modem receive Request */ +#define DRCMR10 0x40000128 /* Request to Channel Map Register for AC97 modem transmit Request */ +#define DRCMR11 0x4000012c /* Request to Channel Map Register for AC97 audio receive Request */ +#define DRCMR12 0x40000130 /* Request to Channel Map Register for AC97 audio transmit Request */ +#define DRCMR13 0x40000134 /* Request to Channel Map Register for SSP receive Request */ +#define DRCMR14 0x40000138 /* Request to Channel Map Register for SSP transmit Request */ +#define DRCMR15 0x4000013c /* Reserved */ +#define DRCMR16 0x40000140 /* Reserved */ +#define DRCMR17 0x40000144 /* Request to Channel Map Register for ICP receive Request */ +#define DRCMR18 0x40000148 /* Request to Channel Map Register for ICP transmit Request */ +#define DRCMR19 0x4000014c /* Request to Channel Map Register for STUART receive Request */ +#define DRCMR20 0x40000150 /* Request to Channel Map Register for STUART transmit Request */ +#define DRCMR21 0x40000154 /* Request to Channel Map Register for MMC receive Request */ +#define DRCMR22 0x40000158 /* Request to Channel Map Register for MMC transmit Request */ +#define DRCMR23 0x4000015c /* Reserved */ +#define DRCMR24 0x40000160 /* Reserved */ +#define DRCMR25 0x40000164 /* Request to Channel Map Register for USB endpoint 1 Request */ +#define DRCMR26 0x40000168 /* Request to Channel Map Register for USB endpoint 2 Request */ +#define DRCMR27 0x4000016C /* Request to Channel Map Register for USB endpoint 3 Request */ +#define DRCMR28 0x40000170 /* Request to Channel Map Register for USB endpoint 4 Request */ +#define DRCMR29 0x40000174 /* Reserved */ +#define DRCMR30 0x40000178 /* Request to Channel Map Register for USB endpoint 6 Request */ +#define DRCMR31 0x4000017C /* Request to Channel Map Register for USB endpoint 7 Request */ +#define DRCMR32 0x40000180 /* Request to Channel Map Register for USB endpoint 8 Request */ +#define DRCMR33 0x40000184 /* Request to Channel Map Register for USB endpoint 9 Request */ +#define DRCMR34 0x40000188 /* Reserved */ +#define DRCMR35 0x4000018C /* Request to Channel Map Register for USB endpoint 11 Request */ +#define DRCMR36 0x40000190 /* Request to Channel Map Register for USB endpoint 12 Request */ +#define DRCMR37 0x40000194 /* Request to Channel Map Register for USB endpoint 13 Request */ +#define DRCMR38 0x40000198 /* Request to Channel Map Register for USB endpoint 14 Request */ +#define DRCMR39 0x4000019C /* Reserved */ + +#define DRCMR68 0x40001110 /* Request to Channel Map Register for Camera FIFO 0 Request */ +#define DRCMR69 0x40001114 /* Request to Channel Map Register for Camera FIFO 1 Request */ +#define DRCMR70 0x40001118 /* Request to Channel Map Register for Camera FIFO 2 Request */ #define DRCMRRXSADR DRCMR2 #define DRCMRTXSADR DRCMR3 @@ -220,75 +220,75 @@ typedef void (*ExcpHndlr) (void) ; #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */ #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */ -#define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */ -#define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */ -#define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */ -#define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */ -#define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */ -#define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */ -#define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */ -#define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */ -#define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */ -#define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */ -#define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */ -#define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */ -#define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */ -#define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */ -#define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */ -#define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */ -#define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */ -#define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */ -#define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */ -#define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */ -#define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */ -#define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */ -#define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */ -#define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */ -#define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */ -#define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */ -#define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */ -#define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */ -#define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */ -#define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */ -#define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */ -#define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */ -#define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */ -#define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */ -#define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */ -#define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */ -#define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */ -#define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */ -#define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */ -#define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */ -#define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */ -#define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */ -#define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */ -#define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */ -#define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */ -#define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */ -#define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */ -#define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */ -#define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */ -#define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */ -#define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */ -#define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */ -#define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */ -#define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */ -#define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */ -#define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */ -#define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */ -#define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */ -#define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */ -#define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */ -#define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */ -#define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */ -#define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */ -#define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */ - -#define DDADR(x) __REG2(0x40000200, (x) << 4) -#define DSADR(x) __REG2(0x40000204, (x) << 4) -#define DTADR(x) __REG2(0x40000208, (x) << 4) -#define DCMD(x) __REG2(0x4000020c, (x) << 4) +#define DDADR0 0x40000200 /* DMA Descriptor Address Register Channel 0 */ +#define DSADR0 0x40000204 /* DMA Source Address Register Channel 0 */ +#define DTADR0 0x40000208 /* DMA Target Address Register Channel 0 */ +#define DCMD0 0x4000020c /* DMA Command Address Register Channel 0 */ +#define DDADR1 0x40000210 /* DMA Descriptor Address Register Channel 1 */ +#define DSADR1 0x40000214 /* DMA Source Address Register Channel 1 */ +#define DTADR1 0x40000218 /* DMA Target Address Register Channel 1 */ +#define DCMD1 0x4000021c /* DMA Command Address Register Channel 1 */ +#define DDADR2 0x40000220 /* DMA Descriptor Address Register Channel 2 */ +#define DSADR2 0x40000224 /* DMA Source Address Register Channel 2 */ +#define DTADR2 0x40000228 /* DMA Target Address Register Channel 2 */ +#define DCMD2 0x4000022c /* DMA Command Address Register Channel 2 */ +#define DDADR3 0x40000230 /* DMA Descriptor Address Register Channel 3 */ +#define DSADR3 0x40000234 /* DMA Source Address Register Channel 3 */ +#define DTADR3 0x40000238 /* DMA Target Address Register Channel 3 */ +#define DCMD3 0x4000023c /* DMA Command Address Register Channel 3 */ +#define DDADR4 0x40000240 /* DMA Descriptor Address Register Channel 4 */ +#define DSADR4 0x40000244 /* DMA Source Address Register Channel 4 */ +#define DTADR4 0x40000248 /* DMA Target Address Register Channel 4 */ +#define DCMD4 0x4000024c /* DMA Command Address Register Channel 4 */ +#define DDADR5 0x40000250 /* DMA Descriptor Address Register Channel 5 */ +#define DSADR5 0x40000254 /* DMA Source Address Register Channel 5 */ +#define DTADR5 0x40000258 /* DMA Target Address Register Channel 5 */ +#define DCMD5 0x4000025c /* DMA Command Address Register Channel 5 */ +#define DDADR6 0x40000260 /* DMA Descriptor Address Register Channel 6 */ +#define DSADR6 0x40000264 /* DMA Source Address Register Channel 6 */ +#define DTADR6 0x40000268 /* DMA Target Address Register Channel 6 */ +#define DCMD6 0x4000026c /* DMA Command Address Register Channel 6 */ +#define DDADR7 0x40000270 /* DMA Descriptor Address Register Channel 7 */ +#define DSADR7 0x40000274 /* DMA Source Address Register Channel 7 */ +#define DTADR7 0x40000278 /* DMA Target Address Register Channel 7 */ +#define DCMD7 0x4000027c /* DMA Command Address Register Channel 7 */ +#define DDADR8 0x40000280 /* DMA Descriptor Address Register Channel 8 */ +#define DSADR8 0x40000284 /* DMA Source Address Register Channel 8 */ +#define DTADR8 0x40000288 /* DMA Target Address Register Channel 8 */ +#define DCMD8 0x4000028c /* DMA Command Address Register Channel 8 */ +#define DDADR9 0x40000290 /* DMA Descriptor Address Register Channel 9 */ +#define DSADR9 0x40000294 /* DMA Source Address Register Channel 9 */ +#define DTADR9 0x40000298 /* DMA Target Address Register Channel 9 */ +#define DCMD9 0x4000029c /* DMA Command Address Register Channel 9 */ +#define DDADR10 0x400002a0 /* DMA Descriptor Address Register Channel 10 */ +#define DSADR10 0x400002a4 /* DMA Source Address Register Channel 10 */ +#define DTADR10 0x400002a8 /* DMA Target Address Register Channel 10 */ +#define DCMD10 0x400002ac /* DMA Command Address Register Channel 10 */ +#define DDADR11 0x400002b0 /* DMA Descriptor Address Register Channel 11 */ +#define DSADR11 0x400002b4 /* DMA Source Address Register Channel 11 */ +#define DTADR11 0x400002b8 /* DMA Target Address Register Channel 11 */ +#define DCMD11 0x400002bc /* DMA Command Address Register Channel 11 */ +#define DDADR12 0x400002c0 /* DMA Descriptor Address Register Channel 12 */ +#define DSADR12 0x400002c4 /* DMA Source Address Register Channel 12 */ +#define DTADR12 0x400002c8 /* DMA Target Address Register Channel 12 */ +#define DCMD12 0x400002cc /* DMA Command Address Register Channel 12 */ +#define DDADR13 0x400002d0 /* DMA Descriptor Address Register Channel 13 */ +#define DSADR13 0x400002d4 /* DMA Source Address Register Channel 13 */ +#define DTADR13 0x400002d8 /* DMA Target Address Register Channel 13 */ +#define DCMD13 0x400002dc /* DMA Command Address Register Channel 13 */ +#define DDADR14 0x400002e0 /* DMA Descriptor Address Register Channel 14 */ +#define DSADR14 0x400002e4 /* DMA Source Address Register Channel 14 */ +#define DTADR14 0x400002e8 /* DMA Target Address Register Channel 14 */ +#define DCMD14 0x400002ec /* DMA Command Address Register Channel 14 */ +#define DDADR15 0x400002f0 /* DMA Descriptor Address Register Channel 15 */ +#define DSADR15 0x400002f4 /* DMA Source Address Register Channel 15 */ +#define DTADR15 0x400002f8 /* DMA Target Address Register Channel 15 */ +#define DCMD15 0x400002fc /* DMA Command Address Register Channel 15 */ + +#define DDADR(x) (0x40000200 | ((x) << 4)) +#define DSADR(x) (0x40000204 | ((x) << 4)) +#define DTADR(x) (0x40000208 | ((x) << 4)) +#define DCMD(x) (0x4000020c | ((x) << 4)) #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */ #define DDADR_STOP (1 << 0) /* Stop (read / write) */ @@ -313,56 +313,57 @@ typedef void (*ExcpHndlr) (void) ; #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4) #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4) +/******************************************************************************/ /* * UARTs */ /* Full Function UART (FFUART) */ #define FFUART FFRBR -#define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */ -#define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */ -#define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */ -#define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */ -#define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */ -#define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */ -#define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */ -#define FFLSR __REG(0x40100014) /* Line Status Register (read only) */ -#define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */ -#define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */ -#define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */ -#define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */ +#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */ +#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */ +#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */ +#define FFFCR 0x40100008 /* FIFO Control Register (write only) */ +#define FFLCR 0x4010000C /* Line Control Register (read/write) */ +#define FFMCR 0x40100010 /* Modem Control Register (read/write) */ +#define FFLSR 0x40100014 /* Line Status Register (read only) */ +#define FFMSR 0x40100018 /* Modem Status Register (read only) */ +#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */ +#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */ +#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Bluetooth UART (BTUART) */ #define BTUART BTRBR -#define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */ -#define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */ -#define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */ -#define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */ -#define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */ -#define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */ -#define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */ -#define BTLSR __REG(0x40200014) /* Line Status Register (read only) */ -#define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */ -#define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */ -#define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */ -#define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */ +#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */ +#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */ +#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */ +#define BTFCR 0x40200008 /* FIFO Control Register (write only) */ +#define BTLCR 0x4020000C /* Line Control Register (read/write) */ +#define BTMCR 0x40200010 /* Modem Control Register (read/write) */ +#define BTLSR 0x40200014 /* Line Status Register (read only) */ +#define BTMSR 0x40200018 /* Modem Status Register (read only) */ +#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */ +#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */ +#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ /* Standard UART (STUART) */ #define STUART STRBR -#define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */ -#define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */ -#define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */ -#define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */ -#define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */ -#define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */ -#define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */ -#define STLSR __REG(0x40700014) /* Line Status Register (read only) */ -#define STMSR __REG(0x40700018) /* Reserved */ -#define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */ -#define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */ -#define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */ -#define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */ +#define STRBR 0x40700000 /* Receive Buffer Register (read only) */ +#define STTHR 0x40700000 /* Transmit Holding Register (write only) */ +#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */ +#define STIIR 0x40700008 /* Interrupt ID Register (read only) */ +#define STFCR 0x40700008 /* FIFO Control Register (write only) */ +#define STLCR 0x4070000C /* Line Control Register (read/write) */ +#define STMCR 0x40700010 /* Modem Control Register (read/write) */ +#define STLSR 0x40700014 /* Line Status Register (read only) */ +#define STMSR 0x40700018 /* Reserved */ +#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */ +#define STISR 0x40700020 /* Infrared Selection Register (read/write) */ +#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */ +#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */ #define IER_DMAE (1 << 7) /* DMA Requests Enable */ #define IER_UUE (1 << 6) /* UART Unit Enable */ @@ -408,7 +409,7 @@ typedef void (*ExcpHndlr) (void) ; #define LSR_OE (1 << 1) /* Overrun Error */ #define LSR_DR (1 << 0) /* Data Ready */ -#define MCR_LOOP (1 << 4) */ +#define MCR_LOOP (1 << 4) /* */ #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ #define MCR_RTS (1 << 1) /* Request to Send */ @@ -423,6 +424,7 @@ typedef void (*ExcpHndlr) (void) ; #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */ #define MSR_DCTS (1 << 0) /* Delta Clear To Send */ +/******************************************************************************/ /* * IrSR (Infrared Selection Register) */ @@ -456,17 +458,25 @@ typedef void (*ExcpHndlr) (void) ; /* * I2C registers */ -#define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */ -#define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */ -#define ICR __REG(0x40301690) /* I2C Control Register - ICR */ -#define ISR __REG(0x40301698) /* I2C Status Register - ISR */ -#define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ - -#define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */ -#define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */ -#define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */ -#define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */ -#define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */ +#define IBMR 0x40301680 /* I2C Bus Monitor Register - IBMR */ +#define IDBR 0x40301688 /* I2C Data Buffer Register - IDBR */ +#define ICR 0x40301690 /* I2C Control Register - ICR */ +#define ISR 0x40301698 /* I2C Status Register - ISR */ +#define ISAR 0x403016A0 /* I2C Slave Address Register - ISAR */ + +#ifdef CONFIG_CPU_MONAHANS +#define PWRIBMR 0x40f500C0 /* Power I2C Bus Monitor Register-IBMR */ +#define PWRIDBR 0x40f500C4 /* Power I2C Data Buffer Register-IDBR */ +#define PWRICR 0x40f500C8 /* Power I2C Control Register - ICR */ +#define PWRISR 0x40f500CC /* Power I2C Status Register - ISR */ +#define PWRISAR 0x40f500D0 /* Power I2C Slave Address Register-ISAR */ +#else +#define PWRIBMR 0x40f00180 /* Power I2C Bus Monitor Register-IBMR */ +#define PWRIDBR 0x40f00188 /* Power I2C Data Buffer Register-IDBR */ +#define PWRICR 0x40f00190 /* Power I2C Control Register - ICR */ +#define PWRISR 0x40f00198 /* Power I2C Status Register - ISR */ +#define PWRISAR 0x40f001A0 /* Power I2C Slave Address Register-ISAR */ +#endif /* ----- Control register bits ---------------------------------------- */ @@ -507,28 +517,27 @@ typedef void (*ExcpHndlr) (void) ; /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these * short defines because there is too much chance of namespace collision */ -/*#define SACR0 __REG(0x40400000) / Global Control Register */ -/*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */ -/*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ -/*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */ -/*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */ -/*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */ -/*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */ - +#define SACR0 0x40400000 /* Global Control Register */ +#define SACR1 0x40400004 /* Serial Audio I 2 S/MSB-Justified Control Register */ +#define SASR0 0x4040000C /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */ +#define SAIMR 0x40400014 /* Serial Audio Interrupt Mask Register */ +#define SAICR 0x40400018 /* Serial Audio Interrupt Clear Register */ +#define SADIV 0x40400060 /* Audio Clock Divider Register. */ +#define SADR 0x40400080 /* Serial Audio Data Register (TX and RX FIFO access Register). */ /* * AC97 Controller registers */ -#define POCR __REG(0x40500000) /* PCM Out Control Register */ +#define POCR 0x40500000 /* PCM Out Control Register */ #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define PICR __REG(0x40500004) /* PCM In Control Register */ +#define PICR 0x40500004 /* PCM In Control Register */ #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define MCCR __REG(0x40500008) /* Mic In Control Register */ +#define MCCR 0x40500008 /* Mic In Control Register */ #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ -#define GCR __REG(0x4050000C) /* Global Control Register */ +#define GCR 0x4050000C /* Global Control Register */ #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ @@ -540,16 +549,16 @@ typedef void (*ExcpHndlr) (void) ; #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ -#define POSR __REG(0x40500010) /* PCM Out Status Register */ +#define POSR 0x40500010 /* PCM Out Status Register */ #define POSR_FIFOE (1 << 4) /* FIFO error */ -#define PISR __REG(0x40500014) /* PCM In Status Register */ +#define PISR 0x40500014 /* PCM In Status Register */ #define PISR_FIFOE (1 << 4) /* FIFO error */ -#define MCSR __REG(0x40500018) /* Mic In Status Register */ +#define MCSR 0x40500018 /* Mic In Status Register */ #define MCSR_FIFOE (1 << 4) /* FIFO error */ -#define GSR __REG(0x4050001C) /* Global Status Register */ +#define GSR 0x4050001C /* Global Status Register */ #define GSR_CDONE (1 << 19) /* Command Done */ #define GSR_SDONE (1 << 18) /* Status Done */ #define GSR_RDCS (1 << 15) /* Read Completion Status */ @@ -567,38 +576,38 @@ typedef void (*ExcpHndlr) (void) ; #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ -#define CAR __REG(0x40500020) /* CODEC Access Register */ +#define CAR 0x40500020 /* CODEC Access Register */ #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ -#define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ -#define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ +#define PCDR 0x40500040 /* PCM FIFO Data Register */ +#define MCDR 0x40500060 /* Mic-in FIFO Data Register */ -#define MOCR __REG(0x40500100) /* Modem Out Control Register */ +#define MOCR 0x40500100 /* Modem Out Control Register */ #define MOCR_FEIE (1 << 3) /* FIFO Error */ -#define MICR __REG(0x40500108) /* Modem In Control Register */ +#define MICR 0x40500108 /* Modem In Control Register */ #define MICR_FEIE (1 << 3) /* FIFO Error */ -#define MOSR __REG(0x40500110) /* Modem Out Status Register */ +#define MOSR 0x40500110 /* Modem Out Status Register */ #define MOSR_FIFOE (1 << 4) /* FIFO error */ -#define MISR __REG(0x40500118) /* Modem In Status Register */ +#define MISR 0x40500118 /* Modem In Status Register */ #define MISR_FIFOE (1 << 4) /* FIFO error */ -#define MODR __REG(0x40500140) /* Modem FIFO Data Register */ +#define MODR 0x40500140 /* Modem FIFO Data Register */ -#define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ -#define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ -#define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ -#define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ +#define PAC_REG_BASE 0x40500200 /* Primary Audio Codec */ +#define SAC_REG_BASE 0x40500300 /* Secondary Audio Codec */ +#define PMC_REG_BASE 0x40500400 /* Primary Modem Codec */ +#define SMC_REG_BASE 0x40500500 /* Secondary Modem Codec */ /* * USB Device Controller */ -#ifdef CONFIG_PXA27X +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) -#define UDCCR __REG(0x40600000) /* UDC Control Register */ +#define UDCCR 0x40600000 /* UDC Control Register */ #define UDCCR_UDE (1 << 0) /* UDC enable */ #define UDCCR_UDA (1 << 1) /* UDC active */ #define UDCCR_RSM (1 << 2) /* Device resume */ @@ -623,7 +632,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */ #define UDCCR_AAISN_S 5 -#define UDCCS0 __REG(0x40600100) /* UDC Endpoint 0 Control/Status Register */ +#define UDCCS0 0x40600100 /* UDC Endpoint 0 Control/Status Register */ #define UDCCS0_OPR (1 << 0) /* OUT packet ready */ #define UDCCS0_IPR (1 << 1) /* IN packet ready */ #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ @@ -634,9 +643,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS0_SA (1 << 7) /* Setup active */ /* Bulk IN - Endpoint 1,6,11 */ -#define UDCCS1 __REG(0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */ -#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ -#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ +#define UDCCS1 0x40600104 /* UDC Endpoint 1 (IN) Control/Status Register */ +#define UDCCS6 0x40600028 /* UDC Endpoint 6 (IN) Control/Status Register */ +#define UDCCS11 0x4060003C /* UDC Endpoint 11 (IN) Control/Status Register */ #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ @@ -647,9 +656,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ /* Bulk OUT - Endpoint 2,7,12 */ -#define UDCCS2 __REG(0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */ -#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ -#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ +#define UDCCS2 0x40600108 /* UDC Endpoint 2 (OUT) Control/Status Register */ +#define UDCCS7 0x4060002C /* UDC Endpoint 7 (OUT) Control/Status Register */ +#define UDCCS12 0x40600040 /* UDC Endpoint 12 (OUT) Control/Status Register */ #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ @@ -660,9 +669,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ /* Isochronous IN - Endpoint 3,8,13 */ -#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ -#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ -#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ +#define UDCCS3 0x4060001C /* UDC Endpoint 3 (IN) Control/Status Register */ +#define UDCCS8 0x40600030 /* UDC Endpoint 8 (IN) Control/Status Register */ +#define UDCCS13 0x40600044 /* UDC Endpoint 13 (IN) Control/Status Register */ #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ @@ -671,9 +680,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ /* Isochronous OUT - Endpoint 4,9,14 */ -#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ -#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ -#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ +#define UDCCS4 0x40600020 /* UDC Endpoint 4 (OUT) Control/Status Register */ +#define UDCCS9 0x40600034 /* UDC Endpoint 9 (OUT) Control/Status Register */ +#define UDCCS14 0x40600048 /* UDC Endpoint 14 (OUT) Control/Status Register */ #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ @@ -683,9 +692,9 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ /* Interrupt IN - Endpoint 5,10,15 */ -#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ -#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ -#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ +#define UDCCS5 0x40600024 /* UDC Endpoint 5 (Interrupt) Control/Status Register */ +#define UDCCS10 0x40600038 /* UDC Endpoint 10 (Interrupt) Control/Status Register */ +#define UDCCS15 0x4060004C /* UDC Endpoint 15 (Interrupt) Control/Status Register */ #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ @@ -695,32 +704,32 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCS_INT_FST (1 << 5) /* Force stall */ #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ -#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ -#define UFNRL __REG(0x40600014) /* UDC Frame Number Register Low */ -#define UBCR2 __REG(0x40600208) /* UDC Byte Count Reg 2 */ -#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */ -#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */ -#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */ -#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */ -#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */ -#define UDDR0 __REG(0x40600300) /* UDC Endpoint 0 Data Register */ -#define UDDR1 __REG(0x40600304) /* UDC Endpoint 1 Data Register */ -#define UDDR2 __REG(0x40600308) /* UDC Endpoint 2 Data Register */ -#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */ -#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */ -#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */ -#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */ -#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */ -#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */ -#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */ -#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */ -#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */ -#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */ -#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ -#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ -#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ - -#define UICR0 __REG(0x40600004) /* UDC Interrupt Control Register 0 */ +#define UFNRH 0x40600060 /* UDC Frame Number Register High */ +#define UFNRL 0x40600014 /* UDC Frame Number Register Low */ +#define UBCR2 0x40600208 /* UDC Byte Count Reg 2 */ +#define UBCR4 0x4060006c /* UDC Byte Count Reg 4 */ +#define UBCR7 0x40600070 /* UDC Byte Count Reg 7 */ +#define UBCR9 0x40600074 /* UDC Byte Count Reg 9 */ +#define UBCR12 0x40600078 /* UDC Byte Count Reg 12 */ +#define UBCR14 0x4060007c /* UDC Byte Count Reg 14 */ +#define UDDR0 0x40600300 /* UDC Endpoint 0 Data Register */ +#define UDDR1 0x40600304 /* UDC Endpoint 1 Data Register */ +#define UDDR2 0x40600308 /* UDC Endpoint 2 Data Register */ +#define UDDR3 0x40600200 /* UDC Endpoint 3 Data Register */ +#define UDDR4 0x40600400 /* UDC Endpoint 4 Data Register */ +#define UDDR5 0x406000A0 /* UDC Endpoint 5 Data Register */ +#define UDDR6 0x40600600 /* UDC Endpoint 6 Data Register */ +#define UDDR7 0x40600680 /* UDC Endpoint 7 Data Register */ +#define UDDR8 0x40600700 /* UDC Endpoint 8 Data Register */ +#define UDDR9 0x40600900 /* UDC Endpoint 9 Data Register */ +#define UDDR10 0x406000C0 /* UDC Endpoint 10 Data Register */ +#define UDDR11 0x40600B00 /* UDC Endpoint 11 Data Register */ +#define UDDR12 0x40600B80 /* UDC Endpoint 12 Data Register */ +#define UDDR13 0x40600C00 /* UDC Endpoint 13 Data Register */ +#define UDDR14 0x40600E00 /* UDC Endpoint 14 Data Register */ +#define UDDR15 0x406000E0 /* UDC Endpoint 15 Data Register */ + +#define UICR0 0x40600004 /* UDC Interrupt Control Register 0 */ #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ @@ -731,7 +740,7 @@ typedef void (*ExcpHndlr) (void) ; #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ -#define UICR1 __REG(0x40600008) /* UDC Interrupt Control Register 1 */ +#define UICR1 0x40600008 /* UDC Interrupt Control Register 1 */ #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ @@ -742,7 +751,7 @@ typedef void (*ExcpHndlr) (void) ; #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ -#define USIR0 __REG(0x4060000C) /* UDC Status Interrupt Register 0 */ +#define USIR0 0x4060000C /* UDC Status Interrupt Register 0 */ #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ #define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */ @@ -753,7 +762,7 @@ typedef void (*ExcpHndlr) (void) ; #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ -#define USIR1 __REG(0x40600010) /* UDC Status Interrupt Register 1 */ +#define USIR1 0x40600010 /* UDC Status Interrupt Register 1 */ #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ @@ -765,8 +774,8 @@ typedef void (*ExcpHndlr) (void) ; #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ -#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */ -#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */ +#define UDCICR0 0x40600004 /* UDC Interrupt Control Register0 */ +#define UDCICR1 0x40600008 /* UDC Interrupt Control Register1 */ #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */ #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */ @@ -777,8 +786,8 @@ typedef void (*ExcpHndlr) (void) ; #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */ #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */ -#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */ -#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */ +#define UDCISR0 0x4060000C /* UDC Interrupt Status Register 0 */ +#define UDCISR1 0x40600010 /* UDC Interrupt Status Register 1 */ #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2)) #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */ #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */ @@ -787,8 +796,8 @@ typedef void (*ExcpHndlr) (void) ; #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */ -#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */ -#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */ +#define UDCFNR 0x40600014 /* UDC Frame Number Register */ +#define UDCOTGICR 0x40600018 /* UDC On-The-Go interrupt control */ #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */ #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */ #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */ @@ -804,7 +813,7 @@ typedef void (*ExcpHndlr) (void) ; #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */ #define UDCCSN(x) __REG2(0x40600100, (x) << 2) -#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ +#define UDCCSR0 0x40600100 /* UDC Control/Status register - Endpoint 0 */ #define UDCCSR0_SA (1 << 7) /* Setup Active */ #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */ @@ -815,29 +824,29 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */ #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */ -#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */ -#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */ -#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */ -#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */ -#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */ -#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */ -#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */ -#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */ -#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */ -#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */ -#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */ -#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */ -#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */ -#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */ -#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */ -#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */ -#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */ -#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */ -#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */ -#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */ -#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */ -#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ -#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */ +#define UDCCSRA 0x40600104 /* UDC Control/Status register - Endpoint A */ +#define UDCCSRB 0x40600108 /* UDC Control/Status register - Endpoint B */ +#define UDCCSRC 0x4060010C /* UDC Control/Status register - Endpoint C */ +#define UDCCSRD 0x40600110 /* UDC Control/Status register - Endpoint D */ +#define UDCCSRE 0x40600114 /* UDC Control/Status register - Endpoint E */ +#define UDCCSRF 0x40600118 /* UDC Control/Status register - Endpoint F */ +#define UDCCSRG 0x4060011C /* UDC Control/Status register - Endpoint G */ +#define UDCCSRH 0x40600120 /* UDC Control/Status register - Endpoint H */ +#define UDCCSRI 0x40600124 /* UDC Control/Status register - Endpoint I */ +#define UDCCSRJ 0x40600128 /* UDC Control/Status register - Endpoint J */ +#define UDCCSRK 0x4060012C /* UDC Control/Status register - Endpoint K */ +#define UDCCSRL 0x40600130 /* UDC Control/Status register - Endpoint L */ +#define UDCCSRM 0x40600134 /* UDC Control/Status register - Endpoint M */ +#define UDCCSRN 0x40600138 /* UDC Control/Status register - Endpoint N */ +#define UDCCSRP 0x4060013C /* UDC Control/Status register - Endpoint P */ +#define UDCCSRQ 0x40600140 /* UDC Control/Status register - Endpoint Q */ +#define UDCCSRR 0x40600144 /* UDC Control/Status register - Endpoint R */ +#define UDCCSRS 0x40600148 /* UDC Control/Status register - Endpoint S */ +#define UDCCSRT 0x4060014C /* UDC Control/Status register - Endpoint T */ +#define UDCCSRU 0x40600150 /* UDC Control/Status register - Endpoint U */ +#define UDCCSRV 0x40600154 /* UDC Control/Status register - Endpoint V */ +#define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ +#define UDCCSRX 0x4060015C /* UDC Control/Status register - Endpoint X */ #define UDCCSR_DPE (1 << 9) /* Data Packet Error */ #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */ @@ -852,81 +861,81 @@ typedef void (*ExcpHndlr) (void) ; #define UDCCSR_FS (1 << 0) /* FIFO needs service */ #define UDCBCN(x) __REG2(0x40600200, (x)<<2) -#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */ -#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */ -#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */ -#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */ -#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */ -#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */ -#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */ -#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */ -#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */ -#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */ -#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */ -#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */ -#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */ -#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */ -#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */ -#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */ -#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */ -#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */ -#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */ -#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */ -#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */ -#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */ -#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */ -#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */ +#define UDCBCR0 0x40600200 /* Byte Count Register - EP0 */ +#define UDCBCRA 0x40600204 /* Byte Count Register - EPA */ +#define UDCBCRB 0x40600208 /* Byte Count Register - EPB */ +#define UDCBCRC 0x4060020C /* Byte Count Register - EPC */ +#define UDCBCRD 0x40600210 /* Byte Count Register - EPD */ +#define UDCBCRE 0x40600214 /* Byte Count Register - EPE */ +#define UDCBCRF 0x40600218 /* Byte Count Register - EPF */ +#define UDCBCRG 0x4060021C /* Byte Count Register - EPG */ +#define UDCBCRH 0x40600220 /* Byte Count Register - EPH */ +#define UDCBCRI 0x40600224 /* Byte Count Register - EPI */ +#define UDCBCRJ 0x40600228 /* Byte Count Register - EPJ */ +#define UDCBCRK 0x4060022C /* Byte Count Register - EPK */ +#define UDCBCRL 0x40600230 /* Byte Count Register - EPL */ +#define UDCBCRM 0x40600234 /* Byte Count Register - EPM */ +#define UDCBCRN 0x40600238 /* Byte Count Register - EPN */ +#define UDCBCRP 0x4060023C /* Byte Count Register - EPP */ +#define UDCBCRQ 0x40600240 /* Byte Count Register - EPQ */ +#define UDCBCRR 0x40600244 /* Byte Count Register - EPR */ +#define UDCBCRS 0x40600248 /* Byte Count Register - EPS */ +#define UDCBCRT 0x4060024C /* Byte Count Register - EPT */ +#define UDCBCRU 0x40600250 /* Byte Count Register - EPU */ +#define UDCBCRV 0x40600254 /* Byte Count Register - EPV */ +#define UDCBCRW 0x40600258 /* Byte Count Register - EPW */ +#define UDCBCRX 0x4060025C /* Byte Count Register - EPX */ #define UDCDN(x) __REG2(0x40600300, (x)<<2) -#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */ -#define UDCDRA __REG(0x40600304) /* Data Register - EPA */ -#define UDCDRB __REG(0x40600308) /* Data Register - EPB */ -#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */ -#define UDCDRD __REG(0x40600310) /* Data Register - EPD */ -#define UDCDRE __REG(0x40600314) /* Data Register - EPE */ -#define UDCDRF __REG(0x40600318) /* Data Register - EPF */ -#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */ -#define UDCDRH __REG(0x40600320) /* Data Register - EPH */ -#define UDCDRI __REG(0x40600324) /* Data Register - EPI */ -#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */ -#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */ -#define UDCDRL __REG(0x40600330) /* Data Register - EPL */ -#define UDCDRM __REG(0x40600334) /* Data Register - EPM */ -#define UDCDRN __REG(0x40600338) /* Data Register - EPN */ -#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */ -#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */ -#define UDCDRR __REG(0x40600344) /* Data Register - EPR */ -#define UDCDRS __REG(0x40600348) /* Data Register - EPS */ -#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */ -#define UDCDRU __REG(0x40600350) /* Data Register - EPU */ -#define UDCDRV __REG(0x40600354) /* Data Register - EPV */ -#define UDCDRW __REG(0x40600358) /* Data Register - EPW */ -#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */ +#define UDCDR0 0x40600300 /* Data Register - EP0 */ +#define UDCDRA 0x40600304 /* Data Register - EPA */ +#define UDCDRB 0x40600308 /* Data Register - EPB */ +#define UDCDRC 0x4060030C /* Data Register - EPC */ +#define UDCDRD 0x40600310 /* Data Register - EPD */ +#define UDCDRE 0x40600314 /* Data Register - EPE */ +#define UDCDRF 0x40600318 /* Data Register - EPF */ +#define UDCDRG 0x4060031C /* Data Register - EPG */ +#define UDCDRH 0x40600320 /* Data Register - EPH */ +#define UDCDRI 0x40600324 /* Data Register - EPI */ +#define UDCDRJ 0x40600328 /* Data Register - EPJ */ +#define UDCDRK 0x4060032C /* Data Register - EPK */ +#define UDCDRL 0x40600330 /* Data Register - EPL */ +#define UDCDRM 0x40600334 /* Data Register - EPM */ +#define UDCDRN 0x40600338 /* Data Register - EPN */ +#define UDCDRP 0x4060033C /* Data Register - EPP */ +#define UDCDRQ 0x40600340 /* Data Register - EPQ */ +#define UDCDRR 0x40600344 /* Data Register - EPR */ +#define UDCDRS 0x40600348 /* Data Register - EPS */ +#define UDCDRT 0x4060034C /* Data Register - EPT */ +#define UDCDRU 0x40600350 /* Data Register - EPU */ +#define UDCDRV 0x40600354 /* Data Register - EPV */ +#define UDCDRW 0x40600358 /* Data Register - EPW */ +#define UDCDRX 0x4060035C /* Data Register - EPX */ #define UDCCN(x) __REG2(0x40600400, (x)<<2) -#define UDCCRA __REG(0x40600404) /* Configuration register EPA */ -#define UDCCRB __REG(0x40600408) /* Configuration register EPB */ -#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */ -#define UDCCRD __REG(0x40600410) /* Configuration register EPD */ -#define UDCCRE __REG(0x40600414) /* Configuration register EPE */ -#define UDCCRF __REG(0x40600418) /* Configuration register EPF */ -#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */ -#define UDCCRH __REG(0x40600420) /* Configuration register EPH */ -#define UDCCRI __REG(0x40600424) /* Configuration register EPI */ -#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */ -#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */ -#define UDCCRL __REG(0x40600430) /* Configuration register EPL */ -#define UDCCRM __REG(0x40600434) /* Configuration register EPM */ -#define UDCCRN __REG(0x40600438) /* Configuration register EPN */ -#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */ -#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */ -#define UDCCRR __REG(0x40600444) /* Configuration register EPR */ -#define UDCCRS __REG(0x40600448) /* Configuration register EPS */ -#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */ -#define UDCCRU __REG(0x40600450) /* Configuration register EPU */ -#define UDCCRV __REG(0x40600454) /* Configuration register EPV */ -#define UDCCRW __REG(0x40600458) /* Configuration register EPW */ -#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */ +#define UDCCRA 0x40600404 /* Configuration register EPA */ +#define UDCCRB 0x40600408 /* Configuration register EPB */ +#define UDCCRC 0x4060040C /* Configuration register EPC */ +#define UDCCRD 0x40600410 /* Configuration register EPD */ +#define UDCCRE 0x40600414 /* Configuration register EPE */ +#define UDCCRF 0x40600418 /* Configuration register EPF */ +#define UDCCRG 0x4060041C /* Configuration register EPG */ +#define UDCCRH 0x40600420 /* Configuration register EPH */ +#define UDCCRI 0x40600424 /* Configuration register EPI */ +#define UDCCRJ 0x40600428 /* Configuration register EPJ */ +#define UDCCRK 0x4060042C /* Configuration register EPK */ +#define UDCCRL 0x40600430 /* Configuration register EPL */ +#define UDCCRM 0x40600434 /* Configuration register EPM */ +#define UDCCRN 0x40600438 /* Configuration register EPN */ +#define UDCCRP 0x4060043C /* Configuration register EPP */ +#define UDCCRQ 0x40600440 /* Configuration register EPQ */ +#define UDCCRR 0x40600444 /* Configuration register EPR */ +#define UDCCRS 0x40600448 /* Configuration register EPS */ +#define UDCCRT 0x4060044C /* Configuration register EPT */ +#define UDCCRU 0x40600450 /* Configuration register EPU */ +#define UDCCRV 0x40600454 /* Configuration register EPV */ +#define UDCCRW 0x40600458 /* Configuration register EPW */ +#define UDCCRX 0x4060045C /* Configuration register EPX */ #define UDCCONR_CN (0x03 << 25) /* Configuration Number */ #define UDCCONR_CN_S (25) @@ -959,38 +968,39 @@ typedef void (*ExcpHndlr) (void) ; #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +/******************************************************************************/ /* * USB Host Controller */ #define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */ -#define UHCREV __REG(0x4C000000) -#define UHCHCON __REG(0x4C000004) -#define UHCCOMS __REG(0x4C000008) -#define UHCINTS __REG(0x4C00000C) -#define UHCINTE __REG(0x4C000010) -#define UHCINTD __REG(0x4C000014) -#define UHCHCCA __REG(0x4C000018) -#define UHCPCED __REG(0x4C00001C) -#define UHCCHED __REG(0x4C000020) -#define UHCCCED __REG(0x4C000024) -#define UHCBHED __REG(0x4C000028) -#define UHCBCED __REG(0x4C00002C) -#define UHCDHEAD __REG(0x4C000030) -#define UHCFMI __REG(0x4C000034) -#define UHCFMR __REG(0x4C000038) -#define UHCFMN __REG(0x4C00003C) -#define UHCPERS __REG(0x4C000040) -#define UHCLST __REG(0x4C000044) -#define UHCRHDA __REG(0x4C000048) -#define UHCRHDB __REG(0x4C00004C) -#define UHCRHS __REG(0x4C000050) -#define UHCRHPS1 __REG(0x4C000054) -#define UHCRHPS2 __REG(0x4C000058) -#define UHCRHPS3 __REG(0x4C00005C) -#define UHCSTAT __REG(0x4C000060) -#define UHCHR __REG(0x4C000064) -#define UHCHIE __REG(0x4C000068) -#define UHCHIT __REG(0x4C00006C) +#define UHCREV 0x4C000000 +#define UHCHCON 0x4C000004 +#define UHCCOMS 0x4C000008 +#define UHCINTS 0x4C00000C +#define UHCINTE 0x4C000010 +#define UHCINTD 0x4C000014 +#define UHCHCCA 0x4C000018 +#define UHCPCED 0x4C00001C +#define UHCCHED 0x4C000020 +#define UHCCCED 0x4C000024 +#define UHCBHED 0x4C000028 +#define UHCBCED 0x4C00002C +#define UHCDHEAD 0x4C000030 +#define UHCFMI 0x4C000034 +#define UHCFMR 0x4C000038 +#define UHCFMN 0x4C00003C +#define UHCPERS 0x4C000040 +#define UHCLST 0x4C000044 +#define UHCRHDA 0x4C000048 +#define UHCRHDB 0x4C00004C +#define UHCRHS 0x4C000050 +#define UHCRHPS1 0x4C000054 +#define UHCRHPS2 0x4C000058 +#define UHCRHPS3 0x4C00005C +#define UHCSTAT 0x4C000060 +#define UHCHR 0x4C000064 +#define UHCHIE 0x4C000068 +#define UHCHIT 0x4C00006C #define UHCHR_FSBIR (1<<0) #define UHCHR_FHR (1<<1) @@ -1011,9 +1021,7 @@ typedef void (*ExcpHndlr) (void) ; #define UHCHIE_HBAIE (1<<8) #define UHCHIE_RWIE (1<<7) -#if defined(CONFIG_CPU_MONAHANS) || defined(CONFIG_PXA27X) -#define UP2OCR __REG(0x40600020) -#endif +#define UP2OCR 0x40600020 #define UP2OCR_HXOE (1<<17) #define UP2OCR_HXS (1<<16) @@ -1029,36 +1037,37 @@ typedef void (*ExcpHndlr) (void) ; #define UP2OCR_CPVPE (1<<1) #define UP2OCR_CPVEN (1<<0) -#endif +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ +/******************************************************************************/ /* * Fast Infrared Communication Port */ -#define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */ -#define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */ -#define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */ -#define ICDR __REG(0x4080000c) /* ICP Data Register */ -#define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */ -#define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */ +#define ICCR0 0x40800000 /* ICP Control Register 0 */ +#define ICCR1 0x40800004 /* ICP Control Register 1 */ +#define ICCR2 0x40800008 /* ICP Control Register 2 */ +#define ICDR 0x4080000c /* ICP Data Register */ +#define ICSR0 0x40800014 /* ICP Status Register 0 */ +#define ICSR1 0x40800018 /* ICP Status Register 1 */ /* * Real Time Clock */ -#define RCNR __REG(0x40900000) /* RTC Count Register */ -#define RTAR __REG(0x40900004) /* RTC Alarm Register */ -#define RTSR __REG(0x40900008) /* RTC Status Register */ -#define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ -#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */ -#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */ -#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ -#define RDCR __REG(0x40900010) /* RTC Day Count Register. */ -#define RYCR __REG(0x40900014) /* RTC Year Count Register. */ -#define SWCR __REG(0x40900028) /* Stopwatch Count Register */ -#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */ +#define RCNR 0x40900000 /* RTC Count Register */ +#define RTAR 0x40900004 /* RTC Alarm Register */ +#define RTSR 0x40900008 /* RTC Status Register */ +#define RTTR 0x4090000C /* RTC Timer Trim Register */ +#define RDAR1 0x40900018 /* Wristwatch Day Alarm Reg 1 */ +#define RDAR2 0x40900020 /* Wristwatch Day Alarm Reg 2 */ +#define RYAR1 0x4090001C /* Wristwatch Year Alarm Reg 1 */ +#define RYAR2 0x40900024 /* Wristwatch Year Alarm Reg 2 */ +#define SWAR1 0x4090002C /* Stopwatch Alarm Register 1 */ +#define SWAR2 0x40900030 /* Stopwatch Alarm Register 2 */ +#define PIAR 0x40900038 /* Periodic Interrupt Alarm Register */ +#define RDCR 0x40900010 /* RTC Day Count Register. */ +#define RYCR 0x40900014 /* RTC Year Count Register. */ +#define SWCR 0x40900028 /* Stopwatch Count Register */ +#define RTCPICR 0x40900034 /* Periodic Interrupt Counter Register */ #define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ #define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ @@ -1068,48 +1077,48 @@ typedef void (*ExcpHndlr) (void) ; #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ #define RTSR_AL (1 << 0) /* RTC alarm detected */ +/******************************************************************************/ /* * OS Timer & Match Registers */ -#define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */ -#define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */ -#define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */ -#define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */ -#define OSCR __REG(0x40A00010) /* OS Timer Counter Register */ -#define OSSR __REG(0x40A00014) /* OS Timer Status Register */ -#define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */ -#define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */ +#define OSMR0 0x40A00000 /* OS Timer Match Register 0 */ +#define OSMR1 0x40A00004 /* OS Timer Match Register 1 */ +#define OSMR2 0x40A00008 /* OS Timer Match Register 2 */ +#define OSMR3 0x40A0000C /* OS Timer Match Register 3 */ +#define OSCR 0x40A00010 /* OS Timer Counter Register */ +#define OSSR 0x40A00014 /* OS Timer Status Register */ +#define OWER 0x40A00018 /* OS Timer Watchdog Enable Register */ +#define OIER 0x40A0001C /* OS Timer Interrupt Enable Register */ -#ifdef CONFIG_CPU_MONAHANS -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */ -#define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */ -#define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */ -#define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */ -#define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */ -#define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */ -#define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */ -#define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */ - -#define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */ -#define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */ -#define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */ -#define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */ -#define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */ -#define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */ -#define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */ -#define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */ - -#define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */ -#define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */ -#define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */ -#define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */ -#define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */ -#define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */ -#define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */ -#define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */ - -#define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */ -#endif /* CONFIG_CPU_MONAHANS */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define OSCR4 0x40A00040 /* OS Timer Counter Register 4 */ +#define OSCR5 0x40A00044 /* OS Timer Counter Register 5 */ +#define OSCR6 0x40A00048 /* OS Timer Counter Register 6 */ +#define OSCR7 0x40A0004C /* OS Timer Counter Register 7 */ +#define OSCR8 0x40A00050 /* OS Timer Counter Register 8 */ +#define OSCR9 0x40A00054 /* OS Timer Counter Register 9 */ +#define OSCR10 0x40A00058 /* OS Timer Counter Register 10 */ +#define OSCR11 0x40A0005C /* OS Timer Counter Register 11 */ + +#define OSMR4 0x40A00080 /* OS Timer Match Register 4 */ +#define OSMR5 0x40A00084 /* OS Timer Match Register 5 */ +#define OSMR6 0x40A00088 /* OS Timer Match Register 6 */ +#define OSMR7 0x40A0008C /* OS Timer Match Register 7 */ +#define OSMR8 0x40A00090 /* OS Timer Match Register 8 */ +#define OSMR9 0x40A00094 /* OS Timer Match Register 9 */ +#define OSMR10 0x40A00098 /* OS Timer Match Register 10 */ +#define OSMR11 0x40A0009C /* OS Timer Match Register 11 */ + +#define OMCR4 0x40A000C0 /* OS Match Control Register 4 */ +#define OMCR5 0x40A000C4 /* OS Match Control Register 5 */ +#define OMCR6 0x40A000C8 /* OS Match Control Register 6 */ +#define OMCR7 0x40A000CC /* OS Match Control Register 7 */ +#define OMCR8 0x40A000D0 /* OS Match Control Register 8 */ +#define OMCR9 0x40A000D4 /* OS Match Control Register 9 */ +#define OMCR10 0x40A000D8 /* OS Match Control Register 10 */ +#define OMCR11 0x40A000DC /* OS Match Control Register 11 */ + +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ #define OSSR_M4 (1 << 4) /* Match status channel 4 */ #define OSSR_M3 (1 << 3) /* Match status channel 3 */ @@ -1125,321 +1134,696 @@ typedef void (*ExcpHndlr) (void) ; #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */ #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */ +#define OSCR_CLK_FREQ 3250 + +/******************************************************************************/ /* - * Pulse Width Modulator + * Core Clock */ -#define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */ -#define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */ -#define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */ -#define PWM_CTRL1 __REG(0x40C00000) /* PWM 1 Control Register */ -#define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */ -#define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */ +#if defined(CONFIG_CPU_MONAHANS) +#define ACCR 0x41340000 /* Application Subsystem Clock Configuration Register */ +#define ACSR 0x41340004 /* Application Subsystem Clock Status Register */ +#define AICSR 0x41340008 /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA 0x4134000C /* A Clock Enable Register */ +#define CKENB 0x41340010 /* B Clock Enable Register */ +#define AC97_DIV 0x41340014 /* AC97 clock divisor value register */ + +#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ +#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ +#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ +#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ +#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ +#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ +#define ACCR_XPDIS (1 << 31) +#define ACCR_SPDIS (1 << 30) +#define ACCR_13MEND1 (1 << 27) +#define ACCR_D0CS (1 << 26) +#define ACCR_13MEND2 (1 << 21) +#define ACCR_PCCE (1 << 11) + +#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ +#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ +#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ +#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ +#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ +#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ +#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ +#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ +#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ +#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ +#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ +#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ +#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ +#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ +#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ +#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ +#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ +#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ +#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ +#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ +#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ +#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ +#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ +#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ +#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ +#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ +#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ +#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ + +#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ +#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ +#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ +#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ +#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ +#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ +#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ + +#else /* if defined CONFIG_CPU_MONAHANS */ + +#define CCCR 0x41300000 /* Core Clock Configuration Register */ +#define CKEN 0x41300004 /* Clock Enable Register */ +#define OSCC 0x41300008 /* Oscillator Configuration Register */ +#define CCSR 0x4130000C /* Core Clock Status Register */ + +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controler */ +#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ +#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ +#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ +#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ + +#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ +#if !defined(CONFIG_PXA27X) +#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ +#endif +#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ + +#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ +#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ +#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ +#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ +#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ +#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ +#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ +#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ +#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ +#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ +#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ +#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ +#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ +#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ +#if defined(CONFIG_PXA27X) +#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ +#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ +#endif +#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ +#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ +#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ +#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ +#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ +#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ +#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ +#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ + +#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ +#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ + +#if !defined(CONFIG_PXA27X) +#define CCCR_L09 (0x1F) +#define CCCR_L27 (0x1) +#define CCCR_L32 (0x2) +#define CCCR_L36 (0x3) +#define CCCR_L40 (0x4) +#define CCCR_L45 (0x5) + +#define CCCR_M1 (0x1 << 5) +#define CCCR_M2 (0x2 << 5) +#define CCCR_M4 (0x3 << 5) -#define PWM_CTRL2 __REG(0x40B00010) /* PWM 2 Control Register */ -#define PWM_PWDUTY2 __REG(0x40B00014) /* PWM 2 Duty Cycle Register */ -#define PWM_PERVAL2 __REG(0x40B00018) /* PWM 2 Period Control Register */ +#define CCCR_N10 (0x2 << 7) +#define CCCR_N15 (0x3 << 7) +#define CCCR_N20 (0x4 << 7) +#define CCCR_N25 (0x5 << 7) +#define CCCR_N30 (0x6 << 7) +#endif -#define PWM_CTRL3 __REG(0x40C00010) /* PWM 3 Control Register */ -#define PWM_PWDUTY3 __REG(0x40C00014) /* PWM 3 Duty Cycle Register */ -#define PWM_PERVAL3 __REG(0x40C00018) /* PWM 3 Period Control Register */ +#endif /* CONFIG_CPU_MONAHANS */ +/******************************************************************************/ /* - * Interrupt Controller + * Pulse Width Modulator */ -#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */ -#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */ -#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */ -#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */ -#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */ -#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */ +#define PWM_CTRL0 0x40B00000 /* PWM 0 Control Register */ +#define PWM_PWDUTY0 0x40B00004 /* PWM 0 Duty Cycle Register */ +#define PWM_PERVAL0 0x40B00008 /* PWM 0 Period Control Register */ -#ifdef CONFIG_CPU_MONAHANS -#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ -/* Missing: 32 Interrupt priority registers - * These are the same as beneath for PXA27x: maybe can be merged if - * GPIO Stuff is same too. +#define PWM_CTRL1 0x40C00000 /* PWM 1 Control Register */ +#define PWM_PWDUTY1 0x40C00004 /* PWM 1 Duty Cycle Register */ +#define PWM_PERVAL1 0x40C00008 /* PWM 1 Period Control Register */ + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define PWM_CTRL2 0x40B00010 /* PWM 2 Control Register */ +#define PWM_PWDUTY2 0x40B00014 /* PWM 2 Duty Cycle Register */ +#define PWM_PERVAL2 0x40B00018 /* PWM 2 Period Control Register */ + +#define PWM_CTRL3 0x40C00010 /* PWM 3 Control Register */ +#define PWM_PWDUTY3 0x40C00014 /* PWM 3 Duty Cycle Register */ +#define PWM_PERVAL3 0x40C00018 /* PWM 3 Period Control Register */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +/* + * Interrupt Controller */ -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ -/* Missing: 2 Interrupt priority registers */ -#endif /* CONFIG_CPU_MONAHANS */ +#define ICIP 0x40D00000 /* Interrupt Controller IRQ Pending Register */ +#define ICMR 0x40D00004 /* Interrupt Controller Mask Register */ +#define ICLR 0x40D00008 /* Interrupt Controller Level Register */ +#define ICFP 0x40D0000C /* Interrupt Controller FIQ Pending Register */ +#define ICPR 0x40D00010 /* Interrupt Controller Pending Register */ +#define ICCR 0x40D00014 /* Interrupt Controller Control Register */ +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define ICHP 0x40D00018 /* Interrupt Controller Highest Priority Register */ +#define ICIP2 0x40D0009C /* Interrupt Controller IRQ Pending Register 2 */ +#define ICMR2 0x40D000A0 /* Interrupt Controller Mask Register 2 */ +#define ICLR2 0x40D000A4 /* Interrupt Controller Level Register 2 */ +#define ICFP2 0x40D000A8 /* Interrupt Controller FIQ Pending Register 2 */ +#define ICPR2 0x40D000AC /* Interrupt Controller Pending Register 2 */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ + +/******************************************************************************/ /* * General Purpose I/O */ -#define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ -#define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ -#define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ +#define GPLR0 0x40E00000 /* GPIO Pin-Level Register GPIO<31:0> */ +#define GPLR1 0x40E00004 /* GPIO Pin-Level Register GPIO<63:32> */ +#define GPLR2 0x40E00008 /* GPIO Pin-Level Register GPIO<80:64> */ -#define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */ -#define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */ -#define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */ +#define GPDR0 0x40E0000C /* GPIO Pin Direction Register GPIO<31:0> */ +#define GPDR1 0x40E00010 /* GPIO Pin Direction Register GPIO<63:32> */ +#define GPDR2 0x40E00014 /* GPIO Pin Direction Register GPIO<80:64> */ -#define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */ -#define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */ -#define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */ +#define GPSR0 0x40E00018 /* GPIO Pin Output Set Register GPIO<31:0> */ +#define GPSR1 0x40E0001C /* GPIO Pin Output Set Register GPIO<63:32> */ +#define GPSR2 0x40E00020 /* GPIO Pin Output Set Register GPIO<80:64> */ -#define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */ -#define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */ -#define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */ +#define GPCR0 0x40E00024 /* GPIO Pin Output Clear Register GPIO<31:0> */ +#define GPCR1 0x40E00028 /* GPIO Pin Output Clear Register GPIO <63:32> */ +#define GPCR2 0x40E0002C /* GPIO Pin Output Clear Register GPIO <80:64> */ -#define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */ -#define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */ -#define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */ +#define GRER0 0x40E00030 /* GPIO Rising-Edge Detect Register GPIO<31:0> */ +#define GRER1 0x40E00034 /* GPIO Rising-Edge Detect Register GPIO<63:32> */ +#define GRER2 0x40E00038 /* GPIO Rising-Edge Detect Register GPIO<80:64> */ -#define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */ -#define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */ +#define GFER0 0x40E0003C /* GPIO Falling-Edge Detect Register GPIO<31:0> */ +#define GFER1 0x40E00040 /* GPIO Falling-Edge Detect Register GPIO<63:32> */ +#define GFER2 0x40E00044 /* GPIO Falling-Edge Detect Register GPIO<80:64> */ -#define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */ -#define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */ -#define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */ +#define GEDR0 0x40E00048 /* GPIO Edge Detect Status Register GPIO<31:0> */ +#define GEDR1 0x40E0004C /* GPIO Edge Detect Status Register GPIO<63:32> */ +#define GEDR2 0x40E00050 /* GPIO Edge Detect Status Register GPIO<80:64> */ + +#define GAFR0_L 0x40E00054 /* GPIO Alternate Function Select Register GPIO<15:0> */ +#define GAFR0_U 0x40E00058 /* GPIO Alternate Function Select Register GPIO<31:16> */ +#define GAFR1_L 0x40E0005C /* GPIO Alternate Function Select Register GPIO<47:32> */ +#define GAFR1_U 0x40E00060 /* GPIO Alternate Function Select Register GPIO<63:48> */ +#define GAFR2_L 0x40E00064 /* GPIO Alternate Function Select Register GPIO<79:64> */ +#define GAFR2_U 0x40E00068 /* GPIO Alternate Function Select Register GPIO 80 */ + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR3 0x40E00100 /* GPIO Pin-Level Register GPIO<127:96> */ +#define GPDR3 0x40E0010C /* GPIO Pin Direction Register GPIO<127:96> */ +#define GPSR3 0x40E00118 /* GPIO Pin Output Set Register GPIO<127:96> */ +#define GPCR3 0x40E00124 /* GPIO Pin Output Clear Register GPIO<127:96> */ +#define GRER3 0x40E00130 /* GPIO Rising-Edge Detect Register GPIO<127:96> */ +#define GFER3 0x40E0013C /* GPIO Falling-Edge Detect Register GPIO<127:96> */ +#define GEDR3 0x40E00148 /* GPIO Edge Detect Status Register GPIO<127:96> */ +#define GAFR3_L 0x40E0006C /* GPIO Alternate Function Select Register GPIO<111:96> */ +#define GAFR3_U 0x40E00070 /* GPIO Alternate Function Select Register GPIO<127:112> */ +#endif /* CONFIG_PXA27X || CONFIG_CPU_MONAHANS */ #ifdef CONFIG_CPU_MONAHANS -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -#define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */ -#define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */ -#define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */ -#define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */ - -#define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */ -#define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */ -#define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */ -#define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ - -#define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ -#define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ - -#define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ -#define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ - -#define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ -#define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ - -#define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ -#define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ - -#define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3) -#define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3) - -/* Multi-funktion Pin Registers, uncomplete, only: - * - GPIO - * - Data Flash DF_* pins defined. +#define GSDR0 0x40E00400 /* Bit-wise Set of GPDR[31:0] */ +#define GSDR1 0x40E00404 /* Bit-wise Set of GPDR[63:32] */ +#define GSDR2 0x40E00408 /* Bit-wise Set of GPDR[95:64] */ +#define GSDR3 0x40E0040C /* Bit-wise Set of GPDR[127:96] */ + +#define GCDR0 0x40E00420 /* Bit-wise Clear of GPDR[31:0] */ +#define GCDR1 0x40E00424 /* Bit-wise Clear of GPDR[63:32] */ +#define GCDR2 0x40E00428 /* Bit-wise Clear of GPDR[95:64] */ +#define GCDR3 0x40E0042C /* Bit-wise Clear of GPDR[127:96] */ + +#define GSRER0 0x40E00440 /* Set Rising Edge Det. Enable [31:0] */ +#define GSRER1 0x40E00444 /* Set Rising Edge Det. Enable [63:32] */ +#define GSRER2 0x40E00448 /* Set Rising Edge Det. Enable [95:64] */ +#define GSRER3 0x40E0044C /* Set Rising Edge Det. Enable [127:96] */ + +#define GCRER0 0x40E00460 /* Clear Rising Edge Det. Enable [31:0] */ +#define GCRER1 0x40E00464 /* Clear Rising Edge Det. Enable [63:32] */ +#define GCRER2 0x40E00468 /* Clear Rising Edge Det. Enable [95:64] */ +#define GCRER3 0x40E0046C /* Clear Rising Edge Det. Enable[127:96] */ + +#define GSFER0 0x40E00480 /* Set Falling Edge Det. Enable [31:0] */ +#define GSFER1 0x40E00484 /* Set Falling Edge Det. Enable [63:32] */ +#define GSFER2 0x40E00488 /* Set Falling Edge Det. Enable [95:64] */ +#define GSFER3 0x40E0048C /* Set Falling Edge Det. Enable[127:96] */ + +#define GCFER0 0x40E004A0 /* Clr Falling Edge Det. Enable [31:0] */ +#define GCFER1 0x40E004A4 /* Clr Falling Edge Det. Enable [63:32] */ +#define GCFER2 0x40E004A8 /* Clr Falling Edge Det. Enable [95:64] */ +#define GCFER3 0x40E004AC /* Clr Falling Edge Det. Enable[127:96] */ + +#define GSDR(x) (0x40E00400 | ((x) & 0x60) >> 3) +#define GCDR(x) (0x40E00420 | ((x) & 0x60) >> 3) +#endif + +#define _GPLR(x) (0x40E00000 + (((x) & 0x60) >> 3)) +#define _GPDR(x) (0x40E0000C + (((x) & 0x60) >> 3)) +#define _GPSR(x) (0x40E00018 + (((x) & 0x60) >> 3)) +#define _GPCR(x) (0x40E00024 + (((x) & 0x60) >> 3)) +#define _GRER(x) (0x40E00030 + (((x) & 0x60) >> 3)) +#define _GFER(x) (0x40E0003C + (((x) & 0x60) >> 3)) +#define _GEDR(x) (0x40E00048 + (((x) & 0x60) >> 3)) +#define _GAFR(x) (0x40E00054 + (((x) & 0x70) >> 2)) + +#if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) +#define GPLR(x) (((((x) & 0x7f) < 96) ? _GPLR(x) : GPLR3)) +#define GPDR(x) (((((x) & 0x7f) < 96) ? _GPDR(x) : GPDR3)) +#define GPSR(x) (((((x) & 0x7f) < 96) ? _GPSR(x) : GPSR3)) +#define GPCR(x) (((((x) & 0x7f) < 96) ? _GPCR(x) : GPCR3)) +#define GRER(x) (((((x) & 0x7f) < 96) ? _GRER(x) : GRER3)) +#define GFER(x) (((((x) & 0x7f) < 96) ? _GFER(x) : GFER3)) +#define GEDR(x) (((((x) & 0x7f) < 96) ? _GEDR(x) : GEDR3)) +#define GAFR(x) (((((x) & 0x7f) < 96) ? _GAFR(x) : \ + ((((x) & 0x7f) < 112) ? GAFR3_L : GAFR3_U))) +#else +#define GPLR(x) _GPLR(x) +#define GPDR(x) _GPDR(x) +#define GPSR(x) _GPSR(x) +#define GPCR(x) _GPCR(x) +#define GRER(x) _GRER(x) +#define GFER(x) _GFER(x) +#define GEDR(x) _GEDR(x) +#define GAFR(x) _GAFR(x) +#endif + +#define GPIO_bit(x) (1 << ((x) & 0x1f)) + +/******************************************************************************/ +/* + * Multi-function Pin Registers: */ -#define GPIO0 __REG(0x40e10124) -#define GPIO1 __REG(0x40e10128) -#define GPIO2 __REG(0x40e1012c) -#define GPIO3 __REG(0x40e10130) -#define GPIO4 __REG(0x40e10134) -#define nXCVREN __REG(0x40e10138) - -#define DF_CLE_NOE __REG(0x40e10204) -#define DF_ALE_WE1 __REG(0x40e10208) - -#define DF_SCLK_E __REG(0x40e10210) -#define nBE0 __REG(0x40e10214) -#define nBE1 __REG(0x40e10218) -#define DF_ALE_WE2 __REG(0x40e1021c) -#define DF_INT_RnB __REG(0x40e10220) -#define DF_nCS0 __REG(0x40e10224) -#define DF_nCS1 __REG(0x40e10228) -#define DF_nWE __REG(0x40e1022c) -#define DF_nRE __REG(0x40e10230) -#define nLUA __REG(0x40e10234) -#define nLLA __REG(0x40e10238) -#define DF_ADDR0 __REG(0x40e1023c) -#define DF_ADDR1 __REG(0x40e10240) -#define DF_ADDR2 __REG(0x40e10244) -#define DF_ADDR3 __REG(0x40e10248) -#define DF_IO0 __REG(0x40e1024c) -#define DF_IO8 __REG(0x40e10250) -#define DF_IO1 __REG(0x40e10254) -#define DF_IO9 __REG(0x40e10258) -#define DF_IO2 __REG(0x40e1025c) -#define DF_IO10 __REG(0x40e10260) -#define DF_IO3 __REG(0x40e10264) -#define DF_IO11 __REG(0x40e10268) -#define DF_IO4 __REG(0x40e1026c) -#define DF_IO12 __REG(0x40e10270) -#define DF_IO5 __REG(0x40e10274) -#define DF_IO13 __REG(0x40e10278) -#define DF_IO6 __REG(0x40e1027c) -#define DF_IO14 __REG(0x40e10280) -#define DF_IO7 __REG(0x40e10284) -#define DF_IO15 __REG(0x40e10288) - -#define GPIO5 __REG(0x40e1028c) -#define GPIO6 __REG(0x40e10290) -#define GPIO7 __REG(0x40e10294) -#define GPIO8 __REG(0x40e10298) -#define GPIO9 __REG(0x40e1029c) - -#define GPIO11 __REG(0x40e102a0) -#define GPIO12 __REG(0x40e102a4) -#define GPIO13 __REG(0x40e102a8) -#define GPIO14 __REG(0x40e102ac) -#define GPIO15 __REG(0x40e102b0) -#define GPIO16 __REG(0x40e102b4) -#define GPIO17 __REG(0x40e102b8) -#define GPIO18 __REG(0x40e102bc) -#define GPIO19 __REG(0x40e102c0) -#define GPIO20 __REG(0x40e102c4) -#define GPIO21 __REG(0x40e102c8) -#define GPIO22 __REG(0x40e102cc) -#define GPIO23 __REG(0x40e102d0) -#define GPIO24 __REG(0x40e102d4) -#define GPIO25 __REG(0x40e102d8) -#define GPIO26 __REG(0x40e102dc) - -#define GPIO27 __REG(0x40e10400) -#define GPIO28 __REG(0x40e10404) -#define GPIO29 __REG(0x40e10408) -#define GPIO30 __REG(0x40e1040c) -#define GPIO31 __REG(0x40e10410) -#define GPIO32 __REG(0x40e10414) -#define GPIO33 __REG(0x40e10418) -#define GPIO34 __REG(0x40e1041c) -#define GPIO35 __REG(0x40e10420) -#define GPIO36 __REG(0x40e10424) -#define GPIO37 __REG(0x40e10428) -#define GPIO38 __REG(0x40e1042c) -#define GPIO39 __REG(0x40e10430) -#define GPIO40 __REG(0x40e10434) -#define GPIO41 __REG(0x40e10438) -#define GPIO42 __REG(0x40e1043c) -#define GPIO43 __REG(0x40e10440) -#define GPIO44 __REG(0x40e10444) -#define GPIO45 __REG(0x40e10448) -#define GPIO46 __REG(0x40e1044c) -#define GPIO47 __REG(0x40e10450) -#define GPIO48 __REG(0x40e10454) - -#define GPIO10 __REG(0x40e10458) - -#define GPIO49 __REG(0x40e1045c) -#define GPIO50 __REG(0x40e10460) -#define GPIO51 __REG(0x40e10464) -#define GPIO52 __REG(0x40e10468) -#define GPIO53 __REG(0x40e1046c) -#define GPIO54 __REG(0x40e10470) -#define GPIO55 __REG(0x40e10474) -#define GPIO56 __REG(0x40e10478) -#define GPIO57 __REG(0x40e1047c) -#define GPIO58 __REG(0x40e10480) -#define GPIO59 __REG(0x40e10484) -#define GPIO60 __REG(0x40e10488) -#define GPIO61 __REG(0x40e1048c) -#define GPIO62 __REG(0x40e10490) - -#define GPIO6_2 __REG(0x40e10494) -#define GPIO7_2 __REG(0x40e10498) -#define GPIO8_2 __REG(0x40e1049c) -#define GPIO9_2 __REG(0x40e104a0) -#define GPIO10_2 __REG(0x40e104a4) -#define GPIO11_2 __REG(0x40e104a8) -#define GPIO12_2 __REG(0x40e104ac) -#define GPIO13_2 __REG(0x40e104b0) - -#define GPIO63 __REG(0x40e104b4) -#define GPIO64 __REG(0x40e104b8) -#define GPIO65 __REG(0x40e104bc) -#define GPIO66 __REG(0x40e104c0) -#define GPIO67 __REG(0x40e104c4) -#define GPIO68 __REG(0x40e104c8) -#define GPIO69 __REG(0x40e104cc) -#define GPIO70 __REG(0x40e104d0) -#define GPIO71 __REG(0x40e104d4) -#define GPIO72 __REG(0x40e104d8) -#define GPIO73 __REG(0x40e104dc) - -#define GPIO14_2 __REG(0x40e104e0) -#define GPIO15_2 __REG(0x40e104e4) -#define GPIO16_2 __REG(0x40e104e8) -#define GPIO17_2 __REG(0x40e104ec) - -#define GPIO74 __REG(0x40e104f0) -#define GPIO75 __REG(0x40e104f4) -#define GPIO76 __REG(0x40e104f8) -#define GPIO77 __REG(0x40e104fc) -#define GPIO78 __REG(0x40e10500) -#define GPIO79 __REG(0x40e10504) -#define GPIO80 __REG(0x40e10508) -#define GPIO81 __REG(0x40e1050c) -#define GPIO82 __REG(0x40e10510) -#define GPIO83 __REG(0x40e10514) -#define GPIO84 __REG(0x40e10518) -#define GPIO85 __REG(0x40e1051c) -#define GPIO86 __REG(0x40e10520) -#define GPIO87 __REG(0x40e10524) -#define GPIO88 __REG(0x40e10528) -#define GPIO89 __REG(0x40e1052c) -#define GPIO90 __REG(0x40e10530) -#define GPIO91 __REG(0x40e10534) -#define GPIO92 __REG(0x40e10538) -#define GPIO93 __REG(0x40e1053c) -#define GPIO94 __REG(0x40e10540) -#define GPIO95 __REG(0x40e10544) -#define GPIO96 __REG(0x40e10548) -#define GPIO97 __REG(0x40e1054c) -#define GPIO98 __REG(0x40e10550) - -#define GPIO99 __REG(0x40e10600) -#define GPIO100 __REG(0x40e10604) -#define GPIO101 __REG(0x40e10608) -#define GPIO102 __REG(0x40e1060c) -#define GPIO103 __REG(0x40e10610) -#define GPIO104 __REG(0x40e10614) -#define GPIO105 __REG(0x40e10618) -#define GPIO106 __REG(0x40e1061c) -#define GPIO107 __REG(0x40e10620) -#define GPIO108 __REG(0x40e10624) -#define GPIO109 __REG(0x40e10628) -#define GPIO110 __REG(0x40e1062c) -#define GPIO111 __REG(0x40e10630) -#define GPIO112 __REG(0x40e10634) - -#define GPIO113 __REG(0x40e10638) -#define GPIO114 __REG(0x40e1063c) -#define GPIO115 __REG(0x40e10640) -#define GPIO116 __REG(0x40e10644) -#define GPIO117 __REG(0x40e10648) -#define GPIO118 __REG(0x40e1064c) -#define GPIO119 __REG(0x40e10650) -#define GPIO120 __REG(0x40e10654) -#define GPIO121 __REG(0x40e10658) -#define GPIO122 __REG(0x40e1065c) -#define GPIO123 __REG(0x40e10660) -#define GPIO124 __REG(0x40e10664) -#define GPIO125 __REG(0x40e10668) -#define GPIO126 __REG(0x40e1066c) -#define GPIO127 __REG(0x40e10670) - -#define GPIO0_2 __REG(0x40e10674) -#define GPIO1_2 __REG(0x40e10678) -#define GPIO2_2 __REG(0x40e1067c) -#define GPIO3_2 __REG(0x40e10680) -#define GPIO4_2 __REG(0x40e10684) -#define GPIO5_2 __REG(0x40e10688) +/* PXA320 */ +#if defined(CONFIG_CPU_PXA320) +#define DF_IO0 0x40e1024c +#define DF_IO1 0x40e10254 +#define DF_IO2 0x40e1025c +#define DF_IO3 0x40e10264 +#define DF_IO4 0x40e1026c +#define DF_IO5 0x40e10274 +#define DF_IO6 0x40e1027c +#define DF_IO7 0x40e10284 +#define DF_IO8 0x40e10250 +#define DF_IO9 0x40e10258 +#define DF_IO10 0x40e10260 +#define DF_IO11 0x40e10268 +#define DF_IO12 0x40e10270 +#define DF_IO13 0x40e10278 +#define DF_IO14 0x40e10280 +#define DF_IO15 0x40e10288 +#define DF_CLE_nOE 0x40e10204 +#define DF_ALE_nWE1 0x40e10208 +#define DF_ALE_nWE2 0x40e1021c +#define DF_SCLK_E 0x40e10210 +#define DF_nCS0 0x40e10224 +#define DF_nCS1 0x40e10228 +#define nBE0 0x40e10214 +#define nBE1 0x40e10218 +#define nLUA 0x40e10234 +#define nLLA 0x40e10238 +#define DF_ADDR0 0x40e1023c +#define DF_ADDR1 0x40e10240 +#define DF_ADDR2 0x40e10244 +#define DF_ADDR3 0x40e10248 +#define DF_INT_RnB 0x40e10220 +#define DF_nCS0 0x40e10224 +#define DF_nCS1 0x40e10228 +#define DF_nWE 0x40e1022c +#define DF_nRE 0x40e10230 + +#define nXCVREN 0x40e10138 + +#define GPIO0 0x40e10124 +#define GPIO1 0x40e10128 +#define GPIO2 0x40e1012c +#define GPIO3 0x40e10130 +#define GPIO4 0x40e10134 +#define GPIO5 0x40e1028c +#define GPIO6 0x40e10290 +#define GPIO7 0x40e10294 +#define GPIO8 0x40e10298 +#define GPIO9 0x40e1029c +#define GPIO10 0x40e10458 +#define GPIO11 0x40e102a0 +#define GPIO12 0x40e102a4 +#define GPIO13 0x40e102a8 +#define GPIO14 0x40e102ac +#define GPIO15 0x40e102b0 +#define GPIO16 0x40e102b4 +#define GPIO17 0x40e102b8 +#define GPIO18 0x40e102bc +#define GPIO19 0x40e102c0 +#define GPIO20 0x40e102c4 +#define GPIO21 0x40e102c8 +#define GPIO22 0x40e102cc +#define GPIO23 0x40e102d0 +#define GPIO24 0x40e102d4 +#define GPIO25 0x40e102d8 +#define GPIO26 0x40e102dc + +#define GPIO27 0x40e10400 +#define GPIO28 0x40e10404 +#define GPIO29 0x40e10408 +#define GPIO30 0x40e1040c +#define GPIO31 0x40e10410 +#define GPIO32 0x40e10414 +#define GPIO33 0x40e10418 +#define GPIO34 0x40e1041c +#define GPIO35 0x40e10420 +#define GPIO36 0x40e10424 +#define GPIO37 0x40e10428 +#define GPIO38 0x40e1042c +#define GPIO39 0x40e10430 +#define GPIO40 0x40e10434 +#define GPIO41 0x40e10438 +#define GPIO42 0x40e1043c +#define GPIO43 0x40e10440 +#define GPIO44 0x40e10444 +#define GPIO45 0x40e10448 +#define GPIO46 0x40e1044c +#define GPIO47 0x40e10450 +#define GPIO48 0x40e10454 +#define GPIO49 0x40e1045c +#define GPIO50 0x40e10460 +#define GPIO51 0x40e10464 +#define GPIO52 0x40e10468 +#define GPIO53 0x40e1046c +#define GPIO54 0x40e10470 +#define GPIO55 0x40e10474 +#define GPIO56 0x40e10478 +#define GPIO57 0x40e1047c +#define GPIO58 0x40e10480 +#define GPIO59 0x40e10484 +#define GPIO60 0x40e10488 +#define GPIO61 0x40e1048c +#define GPIO62 0x40e10490 + +#define GPIO6_2 0x40e10494 +#define GPIO7_2 0x40e10498 +#define GPIO8_2 0x40e1049c +#define GPIO9_2 0x40e104a0 +#define GPIO10_2 0x40e104a4 +#define GPIO11_2 0x40e104a8 +#define GPIO12_2 0x40e104ac +#define GPIO13_2 0x40e104b0 + +#define GPIO63 0x40e104b4 +#define GPIO64 0x40e104b8 +#define GPIO65 0x40e104bc +#define GPIO66 0x40e104c0 +#define GPIO67 0x40e104c4 +#define GPIO68 0x40e104c8 +#define GPIO69 0x40e104cc +#define GPIO70 0x40e104d0 +#define GPIO71 0x40e104d4 +#define GPIO72 0x40e104d8 +#define GPIO73 0x40e104dc + +#define GPIO14_2 0x40e104e0 +#define GPIO15_2 0x40e104e4 +#define GPIO16_2 0x40e104e8 +#define GPIO17_2 0x40e104ec + +#define GPIO74 0x40e104f0 +#define GPIO75 0x40e104f4 +#define GPIO76 0x40e104f8 +#define GPIO77 0x40e104fc +#define GPIO78 0x40e10500 +#define GPIO79 0x40e10504 +#define GPIO80 0x40e10508 +#define GPIO81 0x40e1050c +#define GPIO82 0x40e10510 +#define GPIO83 0x40e10514 +#define GPIO84 0x40e10518 +#define GPIO85 0x40e1051c +#define GPIO86 0x40e10520 +#define GPIO87 0x40e10524 +#define GPIO88 0x40e10528 +#define GPIO89 0x40e1052c +#define GPIO90 0x40e10530 +#define GPIO91 0x40e10534 +#define GPIO92 0x40e10538 +#define GPIO93 0x40e1053c +#define GPIO94 0x40e10540 +#define GPIO95 0x40e10544 +#define GPIO96 0x40e10548 +#define GPIO97 0x40e1054c +#define GPIO98 0x40e10550 + +#define GPIO99 0x40e10600 +#define GPIO100 0x40e10604 +#define GPIO101 0x40e10608 +#define GPIO102 0x40e1060c +#define GPIO103 0x40e10610 +#define GPIO104 0x40e10614 +#define GPIO105 0x40e10618 +#define GPIO106 0x40e1061c +#define GPIO107 0x40e10620 +#define GPIO108 0x40e10624 +#define GPIO109 0x40e10628 +#define GPIO110 0x40e1062c +#define GPIO111 0x40e10630 +#define GPIO112 0x40e10634 + +#define GPIO113 0x40e10638 +#define GPIO114 0x40e1063c +#define GPIO115 0x40e10640 +#define GPIO116 0x40e10644 +#define GPIO117 0x40e10648 +#define GPIO118 0x40e1064c +#define GPIO119 0x40e10650 +#define GPIO120 0x40e10654 +#define GPIO121 0x40e10658 +#define GPIO122 0x40e1065c +#define GPIO123 0x40e10660 +#define GPIO124 0x40e10664 +#define GPIO125 0x40e10668 +#define GPIO126 0x40e1066c +#define GPIO127 0x40e10670 + +#define GPIO0_2 0x40e10674 +#define GPIO1_2 0x40e10678 +#define GPIO2_2 0x40e1067c +#define GPIO3_2 0x40e10680 +#define GPIO4_2 0x40e10684 +#define GPIO5_2 0x40e10688 + +/* PXA300 and PXA310 */ +#elif defined(CONFIG_CPU_PXA300) || defined(CONFIG_CPU_PXA310) +#define DF_IO0 0x40e10220 +#define DF_IO1 0x40e10228 +#define DF_IO2 0x40e10230 +#define DF_IO3 0x40e10238 +#define DF_IO4 0x40e10258 +#define DF_IO5 0x40e10260 +#define DF_IO7 0x40e10270 +#define DF_IO6 0x40e10268 +#define DF_IO8 0x40e10224 +#define DF_IO9 0x40e1022c +#define DF_IO10 0x40e10234 +#define DF_IO11 0x40e1023c +#define DF_IO12 0x40e1025c +#define DF_IO13 0x40e10264 +#define DF_IO14 0x40e1026c +#define DF_IO15 0x40e10274 +#define DF_CLE_NOE 0x40e10240 +#define DF_ALE_nWE 0x40e1020c +#define DF_SCLK_E 0x40e10250 +#define nCS0 0x40e100c4 +#define nCS1 0x40e100c0 +#define nBE0 0x40e10204 +#define nBE1 0x40e10208 +#define nLUA 0x40e10244 +#define nLLA 0x40e10254 +#define DF_ADDR0 0x40e10210 +#define DF_ADDR1 0x40e10214 +#define DF_ADDR2 0x40e10218 +#define DF_ADDR3 0x40e1021c +#define DF_INT_RnB 0x40e100c8 +#define DF_nCS0 0x40e10248 +#define DF_nCS1 0x40e10278 +#define DF_nWE 0x40e100cc +#define DF_nRE 0x40e10200 + +#define GPIO0 0x40e100b4 +#define GPIO1 0x40e100b8 +#define GPIO2 0x40e100bc +#define GPIO3 0x40e1027c +#define GPIO4 0x40e10280 + +#define GPIO5 0x40e10284 +#define GPIO6 0x40e10288 +#define GPIO7 0x40e1028c +#define GPIO8 0x40e10290 +#define GPIO9 0x40e10294 +#define GPIO10 0x40e10298 +#define GPIO11 0x40e1029c +#define GPIO12 0x40e102a0 +#define GPIO13 0x40e102a4 +#define GPIO14 0x40e102a8 +#define GPIO15 0x40e102ac +#define GPIO16 0x40e102b0 +#define GPIO17 0x40e102b4 +#define GPIO18 0x40e102b8 +#define GPIO19 0x40e102bc +#define GPIO20 0x40e102c0 +#define GPIO21 0x40e102c4 +#define GPIO22 0x40e102c8 +#define GPIO23 0x40e102cc +#define GPIO24 0x40e102d0 +#define GPIO25 0x40e102d4 +#define GPIO26 0x40e102d8 + +#define GPIO27 0x40e10400 +#define GPIO28 0x40e10404 +#define GPIO29 0x40e10408 +#define ULPI_STP 0x40e1040c +#define ULPI_NXT 0x40e10410 +#define ULPI_DIR 0x40e10414 +#define GPIO30 0x40e10418 +#define GPIO31 0x40e1041c +#define GPIO32 0x40e10420 +#define GPIO33 0x40e10424 +#define GPIO34 0x40e10428 +#define GPIO35 0x40e1042c +#define GPIO36 0x40e10430 +#define GPIO37 0x40e10434 +#define GPIO38 0x40e10438 +#define GPIO39 0x40e1043c +#define GPIO40 0x40e10440 +#define GPIO41 0x40e10444 +#define GPIO42 0x40e10448 +#define GPIO43 0x40e1044c +#define GPIO44 0x40e10450 +#define GPIO45 0x40e10454 +#define GPIO46 0x40e10458 +#define GPIO47 0x40e1045c +#define GPIO48 0x40e10460 + +#define GPIO49 0x40e10464 +#define GPIO50 0x40e10468 +#define GPIO51 0x40e1046c +#define GPIO52 0x40e10470 +#define GPIO53 0x40e10474 +#define GPIO54 0x40e10478 +#define GPIO55 0x40e1047c +#define GPIO56 0x40e10480 +#define GPIO57 0x40e10484 +#define GPIO58 0x40e10488 +#define GPIO59 0x40e1048c +#define GPIO60 0x40e10490 +#define GPIO61 0x40e10494 +#define GPIO62 0x40e10498 +#define GPIO63 0x40e1049c +#define GPIO64 0x40e104a0 +#define GPIO65 0x40e104a4 +#define GPIO66 0x40e104a8 +#define GPIO67 0x40e104ac +#define GPIO68 0x40e104b0 +#define GPIO69 0x40e104b4 +#define GPIO70 0x40e104b8 +#define GPIO71 0x40e104bc +#define GPIO72 0x40e104c0 +#define GPIO73 0x40e104c4 +#define GPIO74 0x40e104c8 +#define GPIO75 0x40e104cc +#define GPIO76 0x40e104d0 +#define GPIO77 0x40e104d4 +#define GPIO78 0x40e104d8 +#define GPIO79 0x40e104dc +#define GPIO80 0x40e104e0 +#define GPIO81 0x40e104e4 +#define GPIO82 0x40e104e8 +#define GPIO83 0x40e104ec +#define GPIO84 0x40e104f0 +#define GPIO85 0x40e104f4 +#define GPIO86 0x40e104f8 +#define GPIO87 0x40e104fc +#define GPIO88 0x40e10500 +#define GPIO89 0x40e10504 +#define GPIO90 0x40e10508 +#define GPIO91 0x40e1050c +#define GPIO92 0x40e10510 +#define GPIO93 0x40e10514 +#define GPIO94 0x40e10518 +#define GPIO95 0x40e1051c +#define GPIO96 0x40e10520 +#define GPIO97 0x40e10524 +#define GPIO98 0x40e10528 + +#define GPIO99 0x40e10600 +#define GPIO100 0x40e10604 +#define GPIO101 0x40e10608 +#define GPIO102 0x40e1060c +#define GPIO103 0x40e10610 +#define GPIO104 0x40e10614 +#define GPIO105 0x40e10618 +#define GPIO106 0x40e1061c +#define GPIO107 0x40e10620 +#define GPIO108 0x40e10624 +#define GPIO109 0x40e10628 +#define GPIO110 0x40e1062c +#define GPIO111 0x40e10630 +#define GPIO112 0x40e10634 + +#define GPIO113 0x40e10638 +#define GPIO114 0x40e1063c +#define GPIO115 0x40e10640 +#define GPIO116 0x40e10644 +#define GPIO117 0x40e10648 +#define GPIO118 0x40e1064c +#define GPIO119 0x40e10650 +#define GPIO120 0x40e10654 +#define GPIO121 0x40e10658 +#define GPIO122 0x40e1065c +#define GPIO123 0x40e10660 +#define GPIO124 0x40e10664 +#define GPIO125 0x40e10668 +#define GPIO126 0x40e1066c +#define GPIO127 0x40e10670 + +#define GPIO0_2 0x40e10674 +#define GPIO1_2 0x40e10678 +#define GPIO2_2 0x40e102dc +#define GPIO3_2 0x40e102e0 +#define GPIO4_2 0x40e102e4 +#define GPIO5_2 0x40e102e8 +#define GPIO6_2 0x40e102ec + +#ifndef CONFIG_CPU_PXA300 /* PXA310 only */ +#define GPIO7_2 0x40e1052c +#define GPIO8_2 0x40e10530 +#define GPIO9_2 0x40e10534 +#define GPIO10_2 0x40e10538 +#endif +#endif +#ifdef CONFIG_CPU_MONAHANS /* MFPR Bit Definitions, see 4-10, Vol. 1 */ #define PULL_SEL 0x8000 #define PULLUP_EN 0x4000 @@ -1470,62 +1854,8 @@ typedef void (*ExcpHndlr) (void) ; #define AF_SEL_6 0x6 /* Alternate function 6 */ #define AF_SEL_7 0x7 /* Alternate function 7 */ - -#else /* CONFIG_CPU_MONAHANS */ - -#define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */ -#define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */ -#define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */ -#define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */ -#define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */ -#define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */ #endif /* CONFIG_CPU_MONAHANS */ -/* More handy macros. The argument is a literal GPIO number. */ - -#define GPIO_bit(x) (1 << ((x) & 0x1f)) - -#ifdef CONFIG_PXA27X - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -#define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3)) -#define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3)) -#define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3)) -#define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3)) -#define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3)) -#define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3)) -#define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) -#define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ - ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) - -#endif - /* GPIO alternate function assignments */ #define GPIO1_RST 1 /* reset */ @@ -1732,63 +2062,63 @@ typedef void (*ExcpHndlr) (void) ; */ #ifdef CONFIG_CPU_MONAHANS -#define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */ -#define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */ -#define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */ -#define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */ -#define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */ -#define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */ -#define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */ -#define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */ -#define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */ -#define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */ -#define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */ -#define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */ -#define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */ -#define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */ - -#define PMCR __REG(0x40F50000) /* Power Manager Control Register */ -#define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */ -#define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */ -#define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */ -#define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */ -#define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */ -#define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */ -#define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */ -#define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */ -#define PCMD(x) __REG(0x40F50110 + x*4) -#define PCMD0 __REG(0x40F50110 + 0 * 4) -#define PCMD1 __REG(0x40F50110 + 1 * 4) -#define PCMD2 __REG(0x40F50110 + 2 * 4) -#define PCMD3 __REG(0x40F50110 + 3 * 4) -#define PCMD4 __REG(0x40F50110 + 4 * 4) -#define PCMD5 __REG(0x40F50110 + 5 * 4) -#define PCMD6 __REG(0x40F50110 + 6 * 4) -#define PCMD7 __REG(0x40F50110 + 7 * 4) -#define PCMD8 __REG(0x40F50110 + 8 * 4) -#define PCMD9 __REG(0x40F50110 + 9 * 4) -#define PCMD10 __REG(0x40F50110 + 10 * 4) -#define PCMD11 __REG(0x40F50110 + 11 * 4) -#define PCMD12 __REG(0x40F50110 + 12 * 4) -#define PCMD13 __REG(0x40F50110 + 13 * 4) -#define PCMD14 __REG(0x40F50110 + 14 * 4) -#define PCMD15 __REG(0x40F50110 + 15 * 4) -#define PCMD16 __REG(0x40F50110 + 16 * 4) -#define PCMD17 __REG(0x40F50110 + 17 * 4) -#define PCMD18 __REG(0x40F50110 + 18 * 4) -#define PCMD19 __REG(0x40F50110 + 19 * 4) -#define PCMD20 __REG(0x40F50110 + 20 * 4) -#define PCMD21 __REG(0x40F50110 + 21 * 4) -#define PCMD22 __REG(0x40F50110 + 22 * 4) -#define PCMD23 __REG(0x40F50110 + 23 * 4) -#define PCMD24 __REG(0x40F50110 + 24 * 4) -#define PCMD25 __REG(0x40F50110 + 25 * 4) -#define PCMD26 __REG(0x40F50110 + 26 * 4) -#define PCMD27 __REG(0x40F50110 + 27 * 4) -#define PCMD28 __REG(0x40F50110 + 28 * 4) -#define PCMD29 __REG(0x40F50110 + 29 * 4) -#define PCMD30 __REG(0x40F50110 + 30 * 4) -#define PCMD31 __REG(0x40F50110 + 31 * 4) +#define ASCR 0x40F40000 /* Application Subsystem Power Status/Control Register */ +#define ARSR 0x40F40004 /* Application Subsystem Reset Status Register */ +#define AD3ER 0x40F40008 /* Application Subsystem D3 state Wakeup Enable Register */ +#define AD3SR 0x40F4000C /* Application Subsystem D3 state Wakeup Status Register */ +#define AD2D0ER 0x40F40010 /* Application Subsystem D2 to D0 state Wakeup Enable Register */ +#define AD2D0SR 0x40F40014 /* Application Subsystem D2 to D0 state Wakeup Status Register */ +#define AD2D1ER 0x40F40018 /* Application Subsystem D2 to D1 state Wakeup Enable Register */ +#define AD2D1SR 0x40F4001C /* Application Subsystem D2 to D1 state Wakeup Status Register */ +#define AD1D0ER 0x40F40020 /* Application Subsystem D1 to D0 state Wakeup Enable Register */ +#define AD1D0SR 0x40F40024 /* Application Subsystem D1 to D0 state Wakeup Status Register */ +#define ASDCNT 0x40F40028 /* Application Subsystem SRAM Drowsy Count Register */ +#define AD3R 0x40F40030 /* Application Subsystem D3 State Configuration Register */ +#define AD2R 0x40F40034 /* Application Subsystem D2 State Configuration Register */ +#define AD1R 0x40F40038 /* Application Subsystem D1 State Configuration Register */ + +#define PMCR 0x40F50000 /* Power Manager Control Register */ +#define PSR 0x40F50004 /* Power Manager S2 Status Register */ +#define PSPR 0x40F50008 /* Power Manager Scratch Pad Register */ +#define PCFR 0x40F5000C /* Power Manager General Configuration Register */ +#define PWER 0x40F50010 /* Power Manager Wake-up Enable Register */ +#define PWSR 0x40F50014 /* Power Manager Wake-up Status Register */ +#define PECR 0x40F50018 /* Power Manager EXT_WAKEUP[1:0] Control Register */ +#define DCDCSR 0x40F50080 /* DC-DC Controller Status Register */ +#define PVCR 0x40F50100 /* Power Manager Voltage Change Control Register */ +#define PCMD(x) (0x40F50110 + x*4) +#define PCMD0 (0x40F50110 + 0 * 4) +#define PCMD1 (0x40F50110 + 1 * 4) +#define PCMD2 (0x40F50110 + 2 * 4) +#define PCMD3 (0x40F50110 + 3 * 4) +#define PCMD4 (0x40F50110 + 4 * 4) +#define PCMD5 (0x40F50110 + 5 * 4) +#define PCMD6 (0x40F50110 + 6 * 4) +#define PCMD7 (0x40F50110 + 7 * 4) +#define PCMD8 (0x40F50110 + 8 * 4) +#define PCMD9 (0x40F50110 + 9 * 4) +#define PCMD10 (0x40F50110 + 10 * 4) +#define PCMD11 (0x40F50110 + 11 * 4) +#define PCMD12 (0x40F50110 + 12 * 4) +#define PCMD13 (0x40F50110 + 13 * 4) +#define PCMD14 (0x40F50110 + 14 * 4) +#define PCMD15 (0x40F50110 + 15 * 4) +#define PCMD16 (0x40F50110 + 16 * 4) +#define PCMD17 (0x40F50110 + 17 * 4) +#define PCMD18 (0x40F50110 + 18 * 4) +#define PCMD19 (0x40F50110 + 19 * 4) +#define PCMD20 (0x40F50110 + 20 * 4) +#define PCMD21 (0x40F50110 + 21 * 4) +#define PCMD22 (0x40F50110 + 22 * 4) +#define PCMD23 (0x40F50110 + 23 * 4) +#define PCMD24 (0x40F50110 + 24 * 4) +#define PCMD25 (0x40F50110 + 25 * 4) +#define PCMD26 (0x40F50110 + 26 * 4) +#define PCMD27 (0x40F50110 + 27 * 4) +#define PCMD28 (0x40F50110 + 28 * 4) +#define PCMD29 (0x40F50110 + 29 * 4) +#define PCMD30 (0x40F50110 + 30 * 4) +#define PCMD31 (0x40F50110 + 31 * 4) #define PCMD_MBC (1<<12) #define PCMD_DCE (1<<11) @@ -1798,64 +2128,64 @@ typedef void (*ExcpHndlr) (void) ; #define PVCR_FVC (0x1 << 28) #define PVCR_VCSA (0x1<<14) #define PVCR_CommandDelay (0xf80) -#define PVCR_ReadPointer (0x01f00000) +#define PVCR_ReadPointer 0x01f00000 #define PVCR_SlaveAddress (0x7f) #else /* ifdef CONFIG_CPU_MONAHANS */ -#define PMCR __REG(0x40F00000) /* Power Manager Control Register */ -#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */ -#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */ -#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */ -#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */ -#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */ -#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */ -#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */ -#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */ -#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */ -#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ -#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */ -#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ - -#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */ -#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */ -#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */ -#define PCMD(x) __REG(0x40F00080 + x*4) -#define PCMD0 __REG(0x40F00080 + 0 * 4) -#define PCMD1 __REG(0x40F00080 + 1 * 4) -#define PCMD2 __REG(0x40F00080 + 2 * 4) -#define PCMD3 __REG(0x40F00080 + 3 * 4) -#define PCMD4 __REG(0x40F00080 + 4 * 4) -#define PCMD5 __REG(0x40F00080 + 5 * 4) -#define PCMD6 __REG(0x40F00080 + 6 * 4) -#define PCMD7 __REG(0x40F00080 + 7 * 4) -#define PCMD8 __REG(0x40F00080 + 8 * 4) -#define PCMD9 __REG(0x40F00080 + 9 * 4) -#define PCMD10 __REG(0x40F00080 + 10 * 4) -#define PCMD11 __REG(0x40F00080 + 11 * 4) -#define PCMD12 __REG(0x40F00080 + 12 * 4) -#define PCMD13 __REG(0x40F00080 + 13 * 4) -#define PCMD14 __REG(0x40F00080 + 14 * 4) -#define PCMD15 __REG(0x40F00080 + 15 * 4) -#define PCMD16 __REG(0x40F00080 + 16 * 4) -#define PCMD17 __REG(0x40F00080 + 17 * 4) -#define PCMD18 __REG(0x40F00080 + 18 * 4) -#define PCMD19 __REG(0x40F00080 + 19 * 4) -#define PCMD20 __REG(0x40F00080 + 20 * 4) -#define PCMD21 __REG(0x40F00080 + 21 * 4) -#define PCMD22 __REG(0x40F00080 + 22 * 4) -#define PCMD23 __REG(0x40F00080 + 23 * 4) -#define PCMD24 __REG(0x40F00080 + 24 * 4) -#define PCMD25 __REG(0x40F00080 + 25 * 4) -#define PCMD26 __REG(0x40F00080 + 26 * 4) -#define PCMD27 __REG(0x40F00080 + 27 * 4) -#define PCMD28 __REG(0x40F00080 + 28 * 4) -#define PCMD29 __REG(0x40F00080 + 29 * 4) -#define PCMD30 __REG(0x40F00080 + 30 * 4) -#define PCMD31 __REG(0x40F00080 + 31 * 4) +#define PMCR 0x40F00000 /* Power Manager Control Register */ +#define PSSR 0x40F00004 /* Power Manager Sleep Status Register */ +#define PSPR 0x40F00008 /* Power Manager Scratch Pad Register */ +#define PWER 0x40F0000C /* Power Manager Wake-up Enable Register */ +#define PRER 0x40F00010 /* Power Manager GPIO Rising-Edge Detect Enable Register */ +#define PFER 0x40F00014 /* Power Manager GPIO Falling-Edge Detect Enable Register */ +#define PEDR 0x40F00018 /* Power Manager GPIO Edge Detect Status Register */ +#define PCFR 0x40F0001C /* Power Manager General Configuration Register */ +#define PGSR0 0x40F00020 /* Power Manager GPIO Sleep State Register for GP[31-0] */ +#define PGSR1 0x40F00024 /* Power Manager GPIO Sleep State Register for GP[63-32] */ +#define PGSR2 0x40F00028 /* Power Manager GPIO Sleep State Register for GP[84-64] */ +#define PGSR3 0x40F0002C /* Power Manager GPIO Sleep State Register for GP[118-96] */ +#define RCSR 0x40F00030 /* Reset Controller Status Register */ + +#define PSLR 0x40F00034 /* Power Manager Sleep Config Register */ +#define PSTR 0x40F00038 /* Power Manager Standby Config Register */ +#define PSNR 0x40F0003C /* Power Manager Sense Config Register */ +#define PVCR 0x40F00040 /* Power Manager VoltageControl Register */ +#define PKWR 0x40F00050 /* Power Manager KB Wake-up Enable Reg */ +#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Register */ +#define PCMD(x) (0x40F00080 + x*4) +#define PCMD0 (0x40F00080 + 0 * 4) +#define PCMD1 (0x40F00080 + 1 * 4) +#define PCMD2 (0x40F00080 + 2 * 4) +#define PCMD3 (0x40F00080 + 3 * 4) +#define PCMD4 (0x40F00080 + 4 * 4) +#define PCMD5 (0x40F00080 + 5 * 4) +#define PCMD6 (0x40F00080 + 6 * 4) +#define PCMD7 (0x40F00080 + 7 * 4) +#define PCMD8 (0x40F00080 + 8 * 4) +#define PCMD9 (0x40F00080 + 9 * 4) +#define PCMD10 (0x40F00080 + 10 * 4) +#define PCMD11 (0x40F00080 + 11 * 4) +#define PCMD12 (0x40F00080 + 12 * 4) +#define PCMD13 (0x40F00080 + 13 * 4) +#define PCMD14 (0x40F00080 + 14 * 4) +#define PCMD15 (0x40F00080 + 15 * 4) +#define PCMD16 (0x40F00080 + 16 * 4) +#define PCMD17 (0x40F00080 + 17 * 4) +#define PCMD18 (0x40F00080 + 18 * 4) +#define PCMD19 (0x40F00080 + 19 * 4) +#define PCMD20 (0x40F00080 + 20 * 4) +#define PCMD21 (0x40F00080 + 21 * 4) +#define PCMD22 (0x40F00080 + 22 * 4) +#define PCMD23 (0x40F00080 + 23 * 4) +#define PCMD24 (0x40F00080 + 24 * 4) +#define PCMD25 (0x40F00080 + 25 * 4) +#define PCMD26 (0x40F00080 + 26 * 4) +#define PCMD27 (0x40F00080 + 27 * 4) +#define PCMD28 (0x40F00080 + 28 * 4) +#define PCMD29 (0x40F00080 + 29 * 4) +#define PCMD30 (0x40F00080 + 30 * 4) +#define PCMD31 (0x40F00080 + 31 * 4) #define PCMD_MBC (1<<12) #define PCMD_DCE (1<<11) @@ -1891,183 +2221,58 @@ typedef void (*ExcpHndlr) (void) ; /* * SSP Serial Port Registers */ -#define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */ -#define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */ -#define SSSR __REG(0x41000008) /* SSP Status Register */ -#define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */ -#define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ +#define SSCR0 0x41000000 /* SSP Control Register 0 */ +#define SSCR1 0x41000004 /* SSP Control Register 1 */ +#define SSSR 0x41000008 /* SSP Status Register */ +#define SSITR 0x4100000C /* SSP Interrupt Test Register */ +#define SSDR 0x41000010 /* (Write / Read) SSP Data Write Register/SSP Data Read Register */ /* * MultiMediaCard (MMC) controller */ -#define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ -#define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ -#define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ -#define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ -#define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ -#define MMC_RESTO __REG(0x41100014) /* Expected response time out */ -#define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ -#define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ -#define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ -#define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ -#define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ -#define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ -#define MMC_CMD __REG(0x41100030) /* Index of current command */ -#define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ -#define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ -#define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ -#define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ -#define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ - -/* - * Core Clock - */ - -#if defined(CONFIG_CPU_MONAHANS) -#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ -#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ -#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ -#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ -#define CKENB __REG(0x41340010) /* B Clock Enable Register */ -#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ - -#define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */ -#define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */ -#define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */ -#define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */ -#define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */ -#define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */ -#define ACCR_XPDIS (1 << 31) -#define ACCR_SPDIS (1 << 30) -#define ACCR_13MEND1 (1 << 27) -#define ACCR_D0CS (1 << 26) -#define ACCR_13MEND2 (1 << 21) -#define ACCR_PCCE (1 << 11) - -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ -#define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ -#define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ -#define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ -#define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */ -#define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ -#define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ -#define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ -#define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ -#define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ -#define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ - -#define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */ -#define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */ -#define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */ -#define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */ -#define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */ -#define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */ - -#else /* if defined CONFIG_CPU_MONAHANS */ - -#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */ -#define CKEN __REG(0x41300004) /* Clock Enable Register */ -#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */ - -#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */ -#if !defined(CONFIG_PXA27X) -#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */ -#endif -#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */ - -#define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */ -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */ -#define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */ -#define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */ -#define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */ -#define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */ -#define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */ -#define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */ -#define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */ -#if defined(CONFIG_PXA27X) -#define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */ -#define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */ -#endif -#define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */ -#define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */ -#define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */ -#define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */ -#define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */ -#define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */ -#define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */ -#define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */ - -#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ -#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ - -#if !defined(CONFIG_PXA27X) -#define CCCR_L09 (0x1F) -#define CCCR_L27 (0x1) -#define CCCR_L32 (0x2) -#define CCCR_L36 (0x3) -#define CCCR_L40 (0x4) -#define CCCR_L45 (0x5) - -#define CCCR_M1 (0x1 << 5) -#define CCCR_M2 (0x2 << 5) -#define CCCR_M4 (0x3 << 5) - -#define CCCR_N10 (0x2 << 7) -#define CCCR_N15 (0x3 << 7) -#define CCCR_N20 (0x4 << 7) -#define CCCR_N25 (0x5 << 7) -#define CCCR_N30 (0x6 << 7) -#endif +#define MMC_STRPCL 0x41100000 /* Control to start and stop MMC clock */ +#define MMC_STAT 0x41100004 /* MMC Status Register (read only) */ +#define MMC_CLKRT 0x41100008 /* MMC clock rate */ +#define MMC_SPI 0x4110000c /* SPI mode control bits */ +#define MMC_CMDAT 0x41100010 /* Command/response/data sequence control */ +#define MMC_RESTO 0x41100014 /* Expected response time out */ +#define MMC_RDTO 0x41100018 /* Expected data read time out */ +#define MMC_BLKLEN 0x4110001c /* Block length of data transaction */ +#define MMC_NOB 0x41100020 /* Number of blocks, for block mode */ +#define MMC_PRTBUF 0x41100024 /* Partial MMC_TXFIFO FIFO written */ +#define MMC_I_MASK 0x41100028 /* Interrupt Mask */ +#define MMC_I_REG 0x4110002c /* Interrupt Register (read only) */ +#define MMC_CMD 0x41100030 /* Index of current command */ +#define MMC_ARGH 0x41100034 /* MSW part of the current command argument */ +#define MMC_ARGL 0x41100038 /* LSW part of the current command argument */ +#define MMC_RES 0x4110003c /* Response FIFO (read only) */ +#define MMC_RXFIFO 0x41100040 /* Receive FIFO (read only) */ +#define MMC_TXFIFO 0x41100044 /* Transmit FIFO (write only) */ -#endif /* CONFIG_CPU_MONAHANS */ /* * LCD */ -#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */ -#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */ -#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */ -#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */ -#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */ -#define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */ -#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */ -#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */ -#define TMEDCR __REG(0x44000044) /* TMED Control Register */ - -#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */ -#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */ -#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */ -#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */ -#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */ -#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */ -#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */ -#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */ +#define LCCR0 0x44000000 /* LCD Controller Control Register 0 */ +#define LCCR1 0x44000004 /* LCD Controller Control Register 1 */ +#define LCCR2 0x44000008 /* LCD Controller Control Register 2 */ +#define LCCR3 0x4400000C /* LCD Controller Control Register 3 */ +#define DFBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ +#define DFBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ +#define LCSR0 0x44000038 /* LCD Controller Status Register */ +#define LCSR1 0x44000034 /* LCD Controller Status Register */ +#define LIIDR 0x4400003C /* LCD Controller Interrupt ID Register */ +#define TMEDRGBR 0x44000040 /* TMED RGB Seed Register */ +#define TMEDCR 0x44000044 /* TMED Control Register */ + +#define FDADR0 0x44000200 /* DMA Channel 0 Frame Descriptor Address Register */ +#define FSADR0 0x44000204 /* DMA Channel 0 Frame Source Address Register */ +#define FIDR0 0x44000208 /* DMA Channel 0 Frame ID Register */ +#define LDCMD0 0x4400020C /* DMA Channel 0 Command Register */ +#define FDADR1 0x44000210 /* DMA Channel 1 Frame Descriptor Address Register */ +#define FSADR1 0x44000214 /* DMA Channel 1 Frame Source Address Register */ +#define FIDR1 0x44000218 /* DMA Channel 1 Frame ID Register */ +#define LDCMD1 0x4400021C /* DMA Channel 1 Command Register */ #define LCCR0_ENB (1 << 0) /* LCD Controller enable */ #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */ @@ -2135,22 +2340,12 @@ typedef void (*ExcpHndlr) (void) ; /* [0..255 Tln] */ \ ((Tln) << FShft (LCCR2_BFW)) -#if 0 -#define LCCR3_PCD (0xff) /* Pixel clock divisor */ -#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ -#define LCCR3_ACB_S 8 -#endif - #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ #define LCCR3_API_S 16 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ #define LCCR3_PCP (1 << 22) /* pixel clock polarity */ #define LCCR3_OEP (1 << 23) /* output enable polarity */ -#if 0 -#define LCCR3_BPP (7 << 24) /* bits per pixel */ -#define LCCR3_BPP_S 24 -#endif #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ #define LCCR3_PDFOR_0 (0 << 30) @@ -2231,46 +2426,49 @@ typedef void (*ExcpHndlr) (void) ; */ #ifdef CONFIG_CPU_MONAHANS + +/* PXA3xx */ + /* Static Memory Controller Registers */ -#define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */ -#define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */ -#define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */ -#define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */ -#define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */ -#define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */ -#define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */ -#define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */ -#define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */ -#define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */ -#define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */ +#define MSC0 0x4A000008 /* Static Memory Control Register 0 */ +#define MSC1 0x4A00000C /* Static Memory Control Register 1 */ +#define MECR 0x4A000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXCNFG 0x4A00001C /* Synchronous Static Memory Control Register */ +#define MCMEM0 0x4A000028 /* Card interface Common Memory Space Socket 0 Timing */ +#define MCATT0 0x4A000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCIO0 0x4A000038 /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MEMCLKCFG 0x4A000068 /* SCLK speed configuration */ +#define CSADRCFG0 0x4A000080 /* Address Configuration for chip select 0 */ +#define CSADRCFG1 0x4A000084 /* Address Configuration for chip select 1 */ +#define CSADRCFG2 0x4A000088 /* Address Configuration for chip select 2 */ +#define CSADRCFG3 0x4A00008C /* Address Configuration for chip select 3 */ +#define CSADRCFG_P 0x4A000090 /* Address Configuration for pcmcia card interface */ +#define CSMSADRCFG 0x4A0000A0 /* Master Address Configuration Register */ +#define CLK_RET_DEL 0x4A0000B0 /* Delay line and mux selects for return data latching for sync. flash */ +#define ADV_RET_DEL 0x4A0000B4 /* Delay line and mux selects for return data latching for sync. flash */ /* Dynamic Memory Controller Registers */ -#define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */ -#define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */ -#define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */ -#define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */ -#define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ -#define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */ -#define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */ -#define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */ -#define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */ -#define EMPI __REG_2(0x48100090) /* EMPI Control Register */ -#define RCOMP __REG_2(0x48100100) -#define PAD_MA __REG_2(0x48100110) -#define PAD_MDMSB __REG_2(0x48100114) -#define PAD_MDLSB __REG_2(0x48100118) -#define PAD_DMEM __REG_2(0x4810011c) -#define PAD_SDCLK __REG_2(0x48100120) -#define PAD_SDCS __REG_2(0x48100124) -#define PAD_SMEM __REG_2(0x48100128) -#define PAD_SCLK __REG_2(0x4810012C) -#define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */ +#define MDCNFG 0x48100000 /* SDRAM Configuration Register 0 */ +#define MDREFR 0x48100004 /* SDRAM Refresh Control Register */ +#define FLYCNFG 0x48100020 /* Fly-by DMA DVAL[1:0] polarities */ +#define MDMRS 0x48100040 /* MRS value to be written to SDRAM */ +#define DDR_SCAL 0x48100050 /* Software Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_HCAL 0x48100060 /* Hardware Delay Line Calibration/Configuration for external DDR memory. */ +#define DDR_WCAL 0x48100068 /* DDR Write Strobe Calibration Register */ +#define DMCIER 0x48100070 /* Dynamic MC Interrupt Enable Register. */ +#define DMCISR 0x48100078 /* Dynamic MC Interrupt Status Register. */ +#define DDR_DLS 0x48100080 /* DDR Delay Line Value Status register for external DDR memory. */ +#define EMPI 0x48100090 /* EMPI Control Register */ +#define RCOMP 0x48100100 +#define PAD_MA 0x48100110 +#define PAD_MDMSB 0x48100114 +#define PAD_MDLSB 0x48100118 +#define PAD_DMEM 0x4810011c +#define PAD_SDCLK 0x48100120 +#define PAD_SDCS 0x48100124 +#define PAD_SMEM 0x48100128 +#define PAD_SCLK 0x4810012C +#define TAI 0x48100F00 /* TAI Tavor Address Isolation Register */ /* Some frequently used bits */ #define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */ @@ -2298,19 +2496,19 @@ typedef void (*ExcpHndlr) (void) ; /* Data Flash Controller Registers */ -#define NDCR __REG(0x43100000) /* Data Flash Control register */ -#define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ -/* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ -#define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ -/* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ -#define NDSR __REG(0x43100014) /* Data Controller Status Register */ -#define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */ -#define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */ -#define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */ -#define NDDB __REG(0x43100040) /* Data Controller Data Buffer */ -#define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */ -#define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */ -#define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */ +#define NDCR 0x43100000 /* Data Flash Control register */ +#define NDTR0CS0 0x43100004 /* Data Controller Timing Parameter 0 Register for ND_nCS0 */ +/* #define NDTR0CS1 0x43100008 /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */ +#define NDTR1CS0 0x4310000C /* Data Controller Timing Parameter 1 Register for ND_nCS0 */ +/* #define NDTR1CS1 0x43100010 /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */ +#define NDSR 0x43100014 /* Data Controller Status Register */ +#define NDPCR 0x43100018 /* Data Controller Page Count Register */ +#define NDBDR0 0x4310001C /* Data Controller Bad Block Register 0 */ +#define NDBDR1 0x43100020 /* Data Controller Bad Block Register 1 */ +#define NDDB 0x43100040 /* Data Controller Data Buffer */ +#define NDCB0 0x43100048 /* Data Controller Command Buffer0 */ +#define NDCB1 0x4310004C /* Data Controller Command Buffer1 */ +#define NDCB2 0x43100050 /* Data Controller Command Buffer2 */ #define NDCR_SPARE_EN (0x1<<31) #define NDCR_ECC_EN (0x1<<30) @@ -2386,7 +2584,9 @@ typedef void (*ExcpHndlr) (void) ; #else /* CONFIG_CPU_MONAHANS */ -#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ +/* PXA2xx */ + +#define MEMC_BASE 0x48000000 /* Base of Memory Controller */ #define MDCNFG_OFFSET 0x0 #define MDREFR_OFFSET 0x4 #define MSC0_OFFSET 0x8 @@ -2405,29 +2605,30 @@ typedef void (*ExcpHndlr) (void) ; #define MCIO1_OFFSET 0x3C #define MDMRS_OFFSET 0x40 -#define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ +#define MDCNFG 0x48000000 /* SDRAM Configuration Register 0 */ #define MDCNFG_DE0 0x00000001 #define MDCNFG_DE1 0x00000002 #define MDCNFG_DE2 0x00010000 #define MDCNFG_DE3 0x00020000 #define MDCNFG_DWID0 0x00000004 -#define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ -#define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ -#define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ -#define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */ -#define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ -#define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */ -#define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */ -#define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */ -#define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */ -#define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */ -#define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */ -#define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */ -#define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */ -#define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */ -#define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ -#define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ +#define MDREFR 0x48000004 /* SDRAM Refresh Control Register */ +#define MSC0 0x48000008 /* Static Memory Control Register 0 */ +#define MSC1 0x4800000C /* Static Memory Control Register 1 */ +#define MSC2 0x48000010 /* Static Memory Control Register 2 */ +#define MECR 0x48000014 /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */ +#define SXLCR 0x48000018 /* LCR value to be written to SDRAM-Timing Synchronous Flash */ +#define SXCNFG 0x4800001C /* Synchronous Static Memory Control Register */ +#define FLYCNFG 0x48000020 +#define SXMRS 0x48000024 /* MRS value to be written to Synchronous Flash or SMROM */ +#define MCMEM0 0x48000028 /* Card interface Common Memory Space Socket 0 Timing */ +#define MCMEM1 0x4800002C /* Card interface Common Memory Space Socket 1 Timing */ +#define MCATT0 0x48000030 /* Card interface Attribute Space Socket 0 Timing Configuration */ +#define MCATT1 0x48000034 /* Card interface Attribute Space Socket 1 Timing Configuration */ +#define MCIO0 0x48000038 /* Card interface I/O Space Socket 0 Timing Configuration */ +#define MCIO1 0x4800003C /* Card interface I/O Space Socket 1 Timing Configuration */ +#define MDMRS 0x48000040 /* MRS value to be written to SDRAM */ +#define BOOT_DEF 0x48000044 /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ #define MDREFR_ALTREFA (1 << 31) /* Exiting Alternate Bus Master Mode Refresh Control */ #define MDREFR_ALTREFB (1 << 30) /* Entering Alternate Bus Master Mode Refresh Control */ @@ -2448,7 +2649,7 @@ typedef void (*ExcpHndlr) (void) ; #if defined(CONFIG_PXA27X) -#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */ +#define ARB_CNTRL 0x48000048 /* Arbiter Control Register */ #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */ #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */ @@ -2460,80 +2661,41 @@ typedef void (*ExcpHndlr) (void) ; #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */ #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */ -#endif /* CONFIG_CPU_MONAHANS */ - -/* Interrupt Controller */ - -#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ -#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ -#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ -#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */ -#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */ - -/* General Purpose I/O */ - -#define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */ -#define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */ -#define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */ -#define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */ -#define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */ -#define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */ -#define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */ -#define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */ -#define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */ - -/* Core Clock */ - -#define CCSR __REG(0x4130000C) /* Core Clock Status Register */ - -#define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */ -#define CKEN22_MEMC (1 << 22) /* Memory Controler */ -#define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */ -#define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */ -#define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */ -#define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */ -#define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */ -#define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */ -#define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */ -#define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */ - -/* Memory controller */ - -#define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */ +#endif /* CONFIG_PXA27X */ /* LCD registers */ -#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */ -#define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */ -#define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */ -#define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */ -#define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */ -#define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */ -#define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */ -#define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */ -#define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */ -#define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */ -#define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */ -#define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */ -#define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */ -#define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */ -#define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */ -#define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */ -#define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */ -#define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */ -#define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */ -#define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */ -#define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */ -#define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */ -#define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */ - -#define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */ -#define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */ -#define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */ -#define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */ -#define CCR __REG(0x44000090) /* Cursor Control Register */ - -#define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */ -#define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */ +#define LCCR4 0x44000010 /* LCD Controller Control Register 4 */ +#define LCCR5 0x44000014 /* LCD Controller Control Register 5 */ +#define FBR0 0x44000020 /* DMA Channel 0 Frame Branch Register */ +#define FBR1 0x44000024 /* DMA Channel 1 Frame Branch Register */ +#define FBR2 0x44000028 /* DMA Channel 2 Frame Branch Register */ +#define FBR3 0x4400002C /* DMA Channel 3 Frame Branch Register */ +#define FBR4 0x44000030 /* DMA Channel 4 Frame Branch Register */ +#define FDADR2 0x44000220 /* DMA Channel 2 Frame Descriptor Address Register */ +#define FSADR2 0x44000224 /* DMA Channel 2 Frame Source Address Register */ +#define FIDR2 0x44000228 /* DMA Channel 2 Frame ID Register */ +#define LDCMD2 0x4400022C /* DMA Channel 2 Command Register */ +#define FDADR3 0x44000230 /* DMA Channel 3 Frame Descriptor Address Register */ +#define FSADR3 0x44000234 /* DMA Channel 3 Frame Source Address Register */ +#define FIDR3 0x44000238 /* DMA Channel 3 Frame ID Register */ +#define LDCMD3 0x4400023C /* DMA Channel 3 Command Register */ +#define FDADR4 0x44000240 /* DMA Channel 4 Frame Descriptor Address Register */ +#define FSADR4 0x44000244 /* DMA Channel 4 Frame Source Address Register */ +#define FIDR4 0x44000248 /* DMA Channel 4 Frame ID Register */ +#define LDCMD4 0x4400024C /* DMA Channel 4 Command Register */ +#define FDADR5 0x44000250 /* DMA Channel 5 Frame Descriptor Address Register */ +#define FSADR5 0x44000254 /* DMA Channel 5 Frame Source Address Register */ +#define FIDR5 0x44000258 /* DMA Channel 5 Frame ID Register */ +#define LDCMD5 0x4400025C /* DMA Channel 5 Command Register */ + +#define OVL1C1 0x44000050 /* Overlay 1 Control Register 1 */ +#define OVL1C2 0x44000060 /* Overlay 1 Control Register 2 */ +#define OVL2C1 0x44000070 /* Overlay 2 Control Register 1 */ +#define OVL2C2 0x44000080 /* Overlay 2 Control Register 2 */ +#define CCR 0x44000090 /* Cursor Control Register */ + +#define FBR5 0x44000110 /* DMA Channel 5 Frame Branch Register */ +#define FBR6 0x44000114 /* DMA Channel 6 Frame Branch Register */ #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */ #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */ @@ -2572,16 +2734,16 @@ typedef void (*ExcpHndlr) (void) ; /* Keypad controller */ -#define KPC __REG(0x41500000) /* Keypad Interface Control register */ -#define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */ -#define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */ -#define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */ -#define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */ -#define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ -#define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ -#define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ -#define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ -#define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */ +#define KPC 0x41500000 /* Keypad Interface Control register */ +#define KPDK 0x41500008 /* Keypad Interface Direct Key register */ +#define KPREC 0x41500010 /* Keypad Intefcace Rotary Encoder register */ +#define KPMK 0x41500018 /* Keypad Intefcace Matrix Key register */ +#define KPAS 0x41500020 /* Keypad Interface Automatic Scan register */ +#define KPASMKP0 0x41500028 /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */ +#define KPASMKP1 0x41500030 /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */ +#define KPASMKP2 0x41500038 /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */ +#define KPASMKP3 0x41500040 /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */ +#define KPKDI 0x41500048 /* Keypad Interface Key Debounce Interval register */ #define KPC_AS (0x1 << 30) /* Automatic Scan bit */ #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */ @@ -2623,15 +2785,15 @@ typedef void (*ExcpHndlr) (void) ; #define KPASMKPx_SO (0x1 << 31) #define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR __REG(0x40F00034) -#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ -#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ +#define PSLR 0x40F00034 +#define PSTR 0x40F00038 /* Power Manager Standby Configuration Reg */ +#define PSNR 0x40F0003C /* Power Manager Sense Configuration Reg */ +#define PVCR 0x40F00040 /* Power Manager Voltage Change Control Reg */ +#define PKWR 0x40F00050 /* Power Manager KB Wake-Up Enable Reg */ +#define PKSR 0x40F00054 /* Power Manager KB Level-Detect Status Reg */ +#define OSMR4 0x40A00080 /* */ +#define OSCR4 0x40A00040 /* OS Timer Counter Register */ +#define OMCR4 0x40A000C0 /* */ #endif /* CONFIG_PXA27X */ diff --git a/board/colibri_pxa270/colibri_pxa270.c b/board/colibri_pxa270/colibri_pxa270.c index 84ec38e4a22..8aa7067c732 100644 --- a/board/colibri_pxa270/colibri_pxa270.c +++ b/board/colibri_pxa270/colibri_pxa270.c @@ -22,6 +22,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -65,28 +66,30 @@ int dram_init (void) #ifdef CONFIG_CMD_USB int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); while (UHCHR & UHCHR_FSBIR); - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(0x200); - UHCRHDA |= 0x100; + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); /* enable port 2 */ - UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); return 0; } @@ -98,14 +101,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c index 21eb6550db6..c4a93f91b76 100644 --- a/board/cradle/cradle.c +++ b/board/cradle/cradle.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -92,8 +93,8 @@ set_led (int led, int color) int shift = led * 2; unsigned long mask = 0x3 << shift; - CRADLE_LED_CLR_REG = mask; /* clear bits */ - CRADLE_LED_SET_REG = (color << shift); /* set bits */ + writel(mask, GPCR2); /* clear bits */ + writel((color << shift), GPSR2); /* set bits */ udelay (5000); } diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S index 6b5cfb922b5..39964b64757 100644 --- a/board/cradle/lowlevel_init.S +++ b/board/cradle/lowlevel_init.S @@ -34,10 +34,10 @@ DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE .endm .macro SET_LED val - ldr r6, =CRADLE_LED_CLR_REG + ldr r6, =GPCR2 ldr r7, =0 str r7, [r6] - ldr r6, =CRADLE_LED_SET_REG + ldr r6, =GPSR2 ldr r7, =\val str r7, [r6] .endm diff --git a/board/csb226/csb226.c b/board/csb226/csb226.c index 0a6c13dd29b..6eed9ad676f 100644 --- a/board/csb226/csb226.c +++ b/board/csb226/csb226.c @@ -26,6 +26,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -108,23 +109,23 @@ void csb226_set_led(int led, int state) switch(led) { case 0: if (state==1) { - GPCR0 |= CSB226_USER_LED0; + writel(readl(GPCR0) | CSB226_USER_LED0, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED0; + writel(readl(GPSR0) | CSB226_USER_LED0, GPSR0); } break; case 1: if (state==1) { - GPCR0 |= CSB226_USER_LED1; + writel(readl(GPCR0) | CSB226_USER_LED1, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED1; + writel(readl(GPSR0) | CSB226_USER_LED1, GPSR0); } break; case 2: if (state==1) { - GPCR0 |= CSB226_USER_LED2; + writel(readl(GPCR0) | CSB226_USER_LED2, GPCR0); } else if (state==0) { - GPSR0 |= CSB226_USER_LED2; + writel(readl(GPSR0) | CSB226_USER_LED2, GPSR0); } break; } diff --git a/board/delta/delta.c b/board/delta/delta.c index 68c39d23ce1..df23076a646 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -110,7 +111,7 @@ static uchar kbd_command_prefix[] = "key_cmd"; static void get_pressed_keys(uchar *s) { unsigned long val; - val = GPLR3; + val = readl(GPLR3); if(val & (1<<31)) *s++ = KEYBD_KP_DKIN0; @@ -124,18 +125,18 @@ static void get_pressed_keys(uchar *s) static void keys_init() { - CKENB |= CKENB_7_GPIO; + writel(readl(CKENB) | CKENB_7_GPIO, CKENB); udelay(100); /* Configure GPIOs */ - GPIO127 = 0xa840; /* KP_DKIN0 */ - GPIO114 = 0xa840; /* KP_DKIN1 */ - GPIO125 = 0xa840; /* KP_DKIN2 */ - GPIO118 = 0xa840; /* KP_DKIN5 */ + writel(0xa840, GPIO127); /* KP_DKIN0 */ + writel(0xa840, GPIO114); /* KP_DKIN1 */ + writel(0xa840, GPIO125); /* KP_DKIN2 */ + writel(0xa840, GPIO118); /* KP_DKIN5 */ /* Configure GPIOs as inputs */ - GPDR3 &= ~(1<<31 | 1<<18 | 1<<29 | 1<<22); - GCDR3 = (1<<31 | 1<<18 | 1<<29 | 1<<22); + writel(readl(GPDR3) & ~(1<<31 | 1<<18 | 1<<29 | 1<<22), GPDR3); + writel((1<<31 | 1<<18 | 1<<29 | 1<<22), GCDR3); udelay(100); } @@ -283,11 +284,11 @@ int dram_init (void) void i2c_init_board() { - CKENB |= (CKENB_4_I2C); + writel(readl(CKENB) | (CKENB_4_I2C), CKENB); /* setup I2C GPIO's */ - GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ - GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ + writel(0x801, GPIO32); /* SCL = Alt. Fkt. 1 */ + writel(0x801, GPIO33); /* SDA = Alt. Fkt. 1 */ } /* initialize the DA9030 Power Controller */ @@ -295,20 +296,20 @@ static void init_DA9030() { uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; - CKENB |= CKENB_7_GPIO; + writel(readl(CKENB) | CKENB_7_GPIO, CKENB); udelay(100); /* Rising Edge on EXTON to reset DA9030 */ - GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */ - GPDR0 |= (1<<17); /* GPIO17 is output */ - GSDR0 = (1<<17); - GPCR0 = (1<<17); /* drive GPIO17 low */ - GPSR0 = (1<<17); /* drive GPIO17 high */ + writel(0x8800, GPIO17); /* configure GPIO17, no pullup, -down */ + writel(readl(GPDR0) | (1<<17), GPDR0); /* GPIO17 is output */ + writel((1<<17), GSDR0); + writel((1<<17), GPCR0); /* drive GPIO17 low */ + writel((1<<17), GPSR0); /* drive GPIO17 high */ #if CONFIG_SYS_DA9030_EXTON_DELAY udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY); /* wait for DA9030 */ #endif - GPCR0 = (1<<17); /* drive GPIO17 low */ + writel((1<<17), GPCR0); /* drive GPIO17 low */ /* reset the watchdog and go active (0xec) */ val = (SYS_CONTROL_A_HWRES_ENABLE | diff --git a/board/delta/nand.c b/board/delta/nand.c index 85a6ba291a0..119a587a8d2 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -26,6 +26,7 @@ #include #include +#include #ifdef CONFIG_SYS_DFC_DEBUG1 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args) @@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) if(bytes_multi) { for(i=0; i>(8 * bytes_read++)); @@ -181,7 +182,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) /* calculate delta between OSCR values start and now */ static unsigned long get_delta(unsigned long start) { - unsigned long cur = OSCR; + unsigned long cur = readl(OSCR); if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); @@ -192,7 +193,7 @@ static unsigned long get_delta(unsigned long start) /* delay function, this doesn't belong here */ static void wait_us(unsigned long us) { - unsigned long start = OSCR; + unsigned long start = readl(OSCR); us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000); while (get_delta(start) < us) { @@ -202,14 +203,14 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { - NDCR &= ~NDCR_ND_RUN; + writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR); wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ static unsigned long dfc_wait_event(unsigned long event) { - unsigned long ndsr, timeout, start = OSCR; + unsigned long ndsr, timeout, start = readl(OSCR); if(!event) return 0xff000000; @@ -221,9 +222,9 @@ static unsigned long dfc_wait_event(unsigned long event) * OSCR_CLK_FREQ, 1000); while(1) { - ndsr = NDSR; + ndsr = readl(NDSR); if(ndsr & event) { - NDSR |= event; + writel(readl(NDSR) | event, NDSR); break; } if(get_delta(start) > timeout) { @@ -243,11 +244,11 @@ static void dfc_new_cmd(void) while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ - NDSR = 0xFFF; + writel(0xfff, NDSR); /* set NDCR[NDRUN] */ - if(!(NDCR & NDCR_ND_RUN)) - NDCR |= NDCR_ND_RUN; + if (!(readl(NDCR) & NDCR_ND_RUN)) + writel(readl(NDCR) | NDCR_ND_RUN, NDCR); status = dfc_wait_event(NDSR_WRCMDREQ); @@ -357,9 +358,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, } write_cmd: - NDCB0 = ndcb0; - NDCB0 = ndcb1; - NDCB0 = ndcb2; + writel(ndcb0, NDCB0); + writel(ndcb1, NDCB0); + writel(ndcb2, NDCB0); /* wait_event: */ dfc_wait_event(event); @@ -372,36 +373,36 @@ static void dfc_gpio_init(void) DFC_DEBUG2("Setting up DFC GPIO's.\n"); /* no idea what is done here, see zylonite.c */ - GPIO4 = 0x1; - - DF_ALE_WE1 = 0x00000001; - DF_ALE_WE2 = 0x00000001; - DF_nCS0 = 0x00000001; - DF_nCS1 = 0x00000001; - DF_nWE = 0x00000001; - DF_nRE = 0x00000001; - DF_IO0 = 0x00000001; - DF_IO8 = 0x00000001; - DF_IO1 = 0x00000001; - DF_IO9 = 0x00000001; - DF_IO2 = 0x00000001; - DF_IO10 = 0x00000001; - DF_IO3 = 0x00000001; - DF_IO11 = 0x00000001; - DF_IO4 = 0x00000001; - DF_IO12 = 0x00000001; - DF_IO5 = 0x00000001; - DF_IO13 = 0x00000001; - DF_IO6 = 0x00000001; - DF_IO14 = 0x00000001; - DF_IO7 = 0x00000001; - DF_IO15 = 0x00000001; - - DF_nWE = 0x1901; - DF_nRE = 0x1901; - DF_CLE_NOE = 0x1900; - DF_ALE_WE1 = 0x1901; - DF_INT_RnB = 0x1900; + writel(0x1, GPIO4); + + writel(0x00000001, DF_ALE_nWE1); + writel(0x00000001, DF_ALE_nWE2); + writel(0x00000001, DF_nCS0); + writel(0x00000001, DF_nCS1); + writel(0x00000001, DF_nWE); + writel(0x00000001, DF_nRE); + writel(0x00000001, DF_IO0); + writel(0x00000001, DF_IO8); + writel(0x00000001, DF_IO1); + writel(0x00000001, DF_IO9); + writel(0x00000001, DF_IO2); + writel(0x00000001, DF_IO10); + writel(0x00000001, DF_IO3); + writel(0x00000001, DF_IO11); + writel(0x00000001, DF_IO4); + writel(0x00000001, DF_IO12); + writel(0x00000001, DF_IO5); + writel(0x00000001, DF_IO13); + writel(0x00000001, DF_IO6); + writel(0x00000001, DF_IO14); + writel(0x00000001, DF_IO7); + writel(0x00000001, DF_IO15); + + writel(0x1901, DF_nWE); + writel(0x1901, DF_nRE); + writel(0x1900, DF_CLE_nOE); + writel(0x1901, DF_ALE_nWE1); + writel(0x1900, DF_INT_RnB); } /* @@ -430,7 +431,7 @@ int board_nand_init(struct nand_chip *nand) dfc_gpio_init(); /* turn on the NAND Controller Clock (104 MHz @ D0) */ - CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA); #undef CONFIG_SYS_TIMING_TIGHT #ifndef CONFIG_SYS_TIMING_TIGHT @@ -485,17 +486,19 @@ int board_nand_init(struct nand_chip *nand) tRP_high = 0; } - NDTR0CS0 = (tCH << 19) | + writel((tCH << 19) | (tCS << 16) | (tWH << 11) | (tWP << 8) | (tRP_high << 6) | (tRH << 3) | - (tRP << 0); + (tRP << 0), + NDTR0CS0); - NDTR1CS0 = (tR << 16) | + writel((tR << 16) | (tWHR << 4) | - (tAR << 0); + (tAR << 0), + NDTR1CS0); /* If it doesn't work (unlikely) think about: * - ecc enable @@ -512,7 +515,7 @@ int board_nand_init(struct nand_chip *nand) */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - NDCR = (NDCR_SPARE_EN | /* use the spare area */ + writel(NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ (2 << 16) | /* read id count = 7 ???? mk@tbd */ @@ -528,7 +531,8 @@ int board_nand_init(struct nand_chip *nand) NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ - NDCR_WRCMDREQM); /* write command request ir masked */ + NDCR_WRCMDREQM, /* write command request ir masked */ + NDCR); /* wait 10 us due to cmd buffer clear reset */ diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index 3412f10d3fd..2c5112521be 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -27,6 +27,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -48,20 +49,21 @@ int i2c_init_board(void) /* disable I2C controller first, otherwhise it thinks we want to */ /* talk to the slave port... */ - icr = ICR; ICR &= ~(ICR_SCLE | ICR_IUE); + icr = readl(ICR); + writel(readl(ICR) & ~(ICR_SCLE | ICR_IUE), ICR); /* set gpio pin low _before_ we change direction to output */ - GPCR(70) = GPIO_bit(70); + writel(GPIO_bit(70), GPCR(70)); /* now toggle between output=low and high-impedance */ for (i = 0; i < 20; i++) { - GPDR(70) |= GPIO_bit(70); /* output */ + writel(readl(GPDR(70)) | GPIO_bit(70), GPDR(70)); /* output */ udelay(10); - GPDR(70) &= ~GPIO_bit(70); /* input */ + writel(readl(GPDR(70)) & ~GPIO_bit(70), GPDR(70)); /* input */ udelay(10); } - ICR = icr; + writel(icr, ICR); return 0; } @@ -76,7 +78,7 @@ int misc_init_r(void) char *str; /* determine if the software update key is pressed during startup */ - if (GPLR0 & 0x00000800) { + if (readl(GPLR0) & 0x00000800) { printf("using bootcmd_normal (sw-update button not pressed)\n"); str = getenv("bootcmd_normal"); } else { diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index a54a95dca90..4ab8bd494f6 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -33,6 +33,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -56,14 +57,14 @@ int board_init (void) /* set PWM for LCD */ /* a value that works is 60Hz, 77% duty cycle */ - CKEN |= CKEN0_PWM0; - PWM_CTRL0 = 0x3f; - PWM_PERVAL0 = 0x3ff; - PWM_PWDUTY0 = 792; + writel(readl(CKEN) | CKEN0_PWM0, CKEN); + writel(0x3f, PWM_CTRL0); + writel(0x3ff, PWM_PERVAL0); + writel(792, PWM_PWDUTY0); /* clear reset to AC97 codec */ - CKEN |= CKEN2_AC97; - GCR = GCR_COLD_RST; + writel(readl(CKEN) | CKEN2_AC97, CKEN); + writel(GCR_COLD_RST, GCR); /* enable LCD backlight */ /* *(volatile unsigned int *)(PXA_CS5_PHYS + 0x03C00030) = 0x7; */ @@ -102,11 +103,11 @@ int dram_init (void) void delay_c(void) { /* reset OSCR to 0 */ - OSCR = 0; - while(OSCR > 0x10000) + writel(0, OSCR); + while (readl(OSCR) > 0x10000) ; - while(OSCR < 0xd4000) + while (readl(OSCR) < 0xd4000) ; } @@ -114,12 +115,12 @@ void blink_c(void) { int led_bit = (1<<10); - GPDR0 = led_bit; - GPCR0 = led_bit; + writel(led_bit, GPDR0); + writel(led_bit, GPCR0); delay_c(); - GPSR0 = led_bit; + writel(led_bit, GPSR0); delay_c(); - GPCR0 = led_bit; + writel(led_bit, GPCR0); } int do_idpcmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) diff --git a/board/trizepsiv/conxs.c b/board/trizepsiv/conxs.c index 8c1145629f1..7fac73d2395 100644 --- a/board/trizepsiv/conxs.c +++ b/board/trizepsiv/conxs.c @@ -34,6 +34,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -57,25 +58,27 @@ extern struct serial_device serial_stuart_device; int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (readl(UHCHR) & UHCHR_FSBIR) + ; - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(RH_A_NPS); - UHCRHDA |= RH_A_PSM; + writel(readl(UHCRHDA) & ~(RH_A_NPS), UHCRHDA); + writel(readl(UHCRHDA) | RH_A_PSM, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); return 0; } @@ -87,14 +90,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 18e47e2212b..f7922980c8b 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -31,6 +31,8 @@ #include #include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -75,28 +77,31 @@ int dram_init (void) int usb_board_init(void) { - UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) & - ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE); + writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); - UHCHR |= UHCHR_FSBIR; + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); - while (UHCHR & UHCHR_FSBIR); + while (readl(UHCHR) & UHCHR_FSBIR) + ; - UHCHR &= ~UHCHR_SSE; - UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE); + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); /* Clear any OTG Pin Hold */ - if (PSSR & PSSR_OTGPH) - PSSR |= PSSR_OTGPH; + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); - UHCRHDA &= ~(0x200); - UHCRHDA |= 0x100; + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); /* Set port power control mask bits, only 3 ports. */ - UHCRHDB |= (0x7<<17); + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); /* enable port 2 */ - UP2OCR |= UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE; + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); return 0; } @@ -108,14 +113,14 @@ void usb_board_init_fail(void) void usb_board_stop(void) { - UHCHR |= UHCHR_FHR; + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); udelay(11); - UHCHR &= ~UHCHR_FHR; + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); - UHCCOMS |= 1; + writel(readl(UHCCOMS) | 1, UHCCOMS); udelay(10); - CKEN &= ~CKEN10_USBHOST; + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); return; } diff --git a/board/wepep250/wepep250.c b/board/wepep250/wepep250.c index fe4b6a91d20..6e41ea6d01e 100644 --- a/board/wepep250/wepep250.c +++ b/board/wepep250/wepep250.c @@ -22,6 +22,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -33,13 +34,13 @@ int board_init (void) * Setup GPIO stuff to get serial working */ #if defined( CONFIG_FFUART ) - GPDR1 = 0x80; - GAFR1_L = 0x8010; + writel(0x80, GPDR1); + writel(0x8010, GAFR1_L); #elif defined( CONFIG_BTUART ) - GPDR1 = 0x800; - GAFR1_L = 0x900000; + writel(0x800, GPDR1); + writel(0x900000, GAFR1_L); #endif - PSSR = 0x20; + writel(0x20, PSSR); return 0; } diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index 14d1d763b1e..f7edc4c8cab 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -28,6 +28,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -129,24 +130,24 @@ void zipitz2_spi_sda(int set) { /* GPIO 13 */ if (set) - GPSR0 = (1 << 13); + writel((1 << 13), GPSR0); else - GPCR0 = (1 << 13); + writel((1 << 13), GPCR0); } void zipitz2_spi_scl(int set) { /* GPIO 22 */ if (set) - GPCR0 = (1 << 22); + writel((1 << 22), GPCR0); else - GPSR0 = (1 << 22); + writel((1 << 22), GPSR0); } unsigned char zipitz2_spi_read(void) { /* GPIO 40 */ - return !!(GPLR1 & (1 << 8)); + return !!(readl(GPLR1) & (1 << 8)); } int spi_cs_is_valid(unsigned int bus, unsigned int cs) @@ -158,13 +159,13 @@ int spi_cs_is_valid(unsigned int bus, unsigned int cs) void spi_cs_activate(struct spi_slave *slave) { /* GPIO 88 low */ - GPCR2 = (1 << 24); + writel((1 << 24), GPCR2); } void spi_cs_deactivate(struct spi_slave *slave) { /* GPIO 88 high */ - GPSR2 = (1 << 24); + writel((1 << 24), GPSR2); } @@ -176,20 +177,20 @@ void lcd_start(void) unsigned char dummy[3] = { 0, 0, 0 }; /* PWM2 AF */ - GAFR0_L |= 0x00800000; + writel(readl(GAFR0_L) | 0x00800000, GAFR0_L); /* Enable clock to all PWM */ - CKEN |= 0x3; + writel(readl(CKEN) | 0x3, CKEN); /* Configure PWM2 */ - PWM_CTRL2 = 0x4f; - PWM_PWDUTY2 = 0x2ff; - PWM_PERVAL2 = 792; + writel(0x4f, PWM_CTRL2); + writel(0x2ff, PWM_PWDUTY2); + writel(792, PWM_PERVAL2); /* Toggle the reset pin to reset the LCD */ - GPSR0 = (1 << 19); + writel((1 << 19), GPSR0); udelay(100000); - GPCR0 = (1 << 19); + writel((1 << 19), GPCR0); udelay(20000); - GPSR0 = (1 << 19); + writel((1 << 19), GPSR0); udelay(20000); /* Program the LCD init sequence */ @@ -208,6 +209,6 @@ void lcd_start(void) udelay(lcd_data[i].mdelay * 1000); } - GPSR0 = (1 << 11); + writel((1 << 11), GPSR0); } #endif diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c index 7cad1ac049c..71d18a6f5f8 100644 --- a/board/zylonite/nand.c +++ b/board/zylonite/nand.c @@ -21,6 +21,7 @@ */ #include +#include #if defined(CONFIG_CMD_NAND) @@ -95,7 +96,7 @@ static void dfc_write_buf(struct mtd_info *mtd, const u_char *buf, int len) if(bytes_multi) { for(i=0; i>(8 * bytes_read++)); @@ -186,7 +187,7 @@ static u_char dfc_read_byte(struct mtd_info *mtd) /* calculate delta between OSCR values start and now */ static unsigned long get_delta(unsigned long start) { - unsigned long cur = OSCR; + unsigned long cur = readl(OSCR); if(cur < start) /* OSCR overflowed */ return (cur + (start^0xffffffff)); @@ -197,7 +198,7 @@ static unsigned long get_delta(unsigned long start) /* delay function, this doesn't belong here */ static void wait_us(unsigned long us) { - unsigned long start = OSCR; + unsigned long start = readl(OSCR); us = DIV_ROUND_UP(us * OSCR_CLK_FREQ, 1000); while (get_delta(start) < us) { @@ -207,14 +208,14 @@ static void wait_us(unsigned long us) static void dfc_clear_nddb(void) { - NDCR &= ~NDCR_ND_RUN; + writel(readl(NDCR) & ~NDCR_ND_RUN, NDCR); wait_us(CONFIG_SYS_NAND_OTHER_TO); } /* wait_event with timeout */ static unsigned long dfc_wait_event(unsigned long event) { - unsigned long ndsr, timeout, start = OSCR; + unsigned long ndsr, timeout, start = readl(OSCR); if(!event) return 0xff000000; @@ -226,9 +227,9 @@ static unsigned long dfc_wait_event(unsigned long event) * OSCR_CLK_FREQ, 1000); while(1) { - ndsr = NDSR; + ndsr = readl(NDSR); if(ndsr & event) { - NDSR |= event; + writel(readl(NDSR) | event, NDSR); break; } if(get_delta(start) > timeout) { @@ -248,11 +249,11 @@ static void dfc_new_cmd(void) while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) { /* Clear NDSR */ - NDSR = 0xFFF; + writel(0xFFF, NDSR); /* set NDCR[NDRUN] */ - if(!(NDCR & NDCR_ND_RUN)) - NDCR |= NDCR_ND_RUN; + if (!(readl(NDCR) & NDCR_ND_RUN)) + writel(readl(NDCR) | NDCR_ND_RUN, NDCR); status = dfc_wait_event(NDSR_WRCMDREQ); @@ -362,9 +363,9 @@ static void dfc_cmdfunc(struct mtd_info *mtd, unsigned command, } write_cmd: - NDCB0 = ndcb0; - NDCB0 = ndcb1; - NDCB0 = ndcb2; + writel(ndcb0, NDCB0); + writel(ndcb1, NDCB0); + writel(ndcb2, NDCB0); /* wait_event: */ dfc_wait_event(event); @@ -377,36 +378,36 @@ static void dfc_gpio_init(void) DFC_DEBUG2("Setting up DFC GPIO's.\n"); /* no idea what is done here, see zylonite.c */ - GPIO4 = 0x1; - - DF_ALE_WE1 = 0x00000001; - DF_ALE_WE2 = 0x00000001; - DF_nCS0 = 0x00000001; - DF_nCS1 = 0x00000001; - DF_nWE = 0x00000001; - DF_nRE = 0x00000001; - DF_IO0 = 0x00000001; - DF_IO8 = 0x00000001; - DF_IO1 = 0x00000001; - DF_IO9 = 0x00000001; - DF_IO2 = 0x00000001; - DF_IO10 = 0x00000001; - DF_IO3 = 0x00000001; - DF_IO11 = 0x00000001; - DF_IO4 = 0x00000001; - DF_IO12 = 0x00000001; - DF_IO5 = 0x00000001; - DF_IO13 = 0x00000001; - DF_IO6 = 0x00000001; - DF_IO14 = 0x00000001; - DF_IO7 = 0x00000001; - DF_IO15 = 0x00000001; - - DF_nWE = 0x1901; - DF_nRE = 0x1901; - DF_CLE_NOE = 0x1900; - DF_ALE_WE1 = 0x1901; - DF_INT_RnB = 0x1900; + writel(0x1, GPIO4); + + writel(0x00000001, DF_ALE_nWE1); + writel(0x00000001, DF_ALE_nWE2); + writel(0x00000001, DF_nCS0); + writel(0x00000001, DF_nCS1); + writel(0x00000001, DF_nWE); + writel(0x00000001, DF_nRE); + writel(0x00000001, DF_IO0); + writel(0x00000001, DF_IO8); + writel(0x00000001, DF_IO1); + writel(0x00000001, DF_IO9); + writel(0x00000001, DF_IO2); + writel(0x00000001, DF_IO10); + writel(0x00000001, DF_IO3); + writel(0x00000001, DF_IO11); + writel(0x00000001, DF_IO4); + writel(0x00000001, DF_IO12); + writel(0x00000001, DF_IO5); + writel(0x00000001, DF_IO13); + writel(0x00000001, DF_IO6); + writel(0x00000001, DF_IO14); + writel(0x00000001, DF_IO7); + writel(0x00000001, DF_IO15); + + writel(0x1901, DF_nWE); + writel(0x1901, DF_nRE); + writel(0x1900, DF_CLE_nOE); + writel(0x1901, DF_ALE_nWE1); + writel(0x1900, DF_INT_RnB); } /* @@ -435,7 +436,7 @@ int board_nand_init(struct nand_chip *nand) dfc_gpio_init(); /* turn on the NAND Controller Clock (104 MHz @ D0) */ - CKENA |= (CKENA_4_NAND | CKENA_9_SMC); + writel(readl(CKENA) | (CKENA_4_NAND | CKENA_9_SMC), CKENA); #undef CONFIG_SYS_TIMING_TIGHT #ifndef CONFIG_SYS_TIMING_TIGHT @@ -490,17 +491,19 @@ int board_nand_init(struct nand_chip *nand) tRP_high = 0; } - NDTR0CS0 = (tCH << 19) | + writel((tCH << 19) | (tCS << 16) | (tWH << 11) | (tWP << 8) | (tRP_high << 6) | (tRH << 3) | - (tRP << 0); + (tRP << 0), + NDTR0CS0); - NDTR1CS0 = (tR << 16) | + writel((tR << 16) | (tWHR << 4) | - (tAR << 0); + (tAR << 0), + NDTR1CS0); /* If it doesn't work (unlikely) think about: * - ecc enable @@ -517,7 +520,7 @@ int board_nand_init(struct nand_chip *nand) */ /* NDCR_NCSX | /\* Chip select busy don't care *\/ */ - NDCR = (NDCR_SPARE_EN | /* use the spare area */ + writel(NDCR_SPARE_EN | /* use the spare area */ NDCR_DWIDTH_C | /* 16bit DFC data bus width */ NDCR_DWIDTH_M | /* 16 bit Flash device data bus width */ (2 << 16) | /* read id count = 7 ???? mk@tbd */ @@ -533,7 +536,8 @@ int board_nand_init(struct nand_chip *nand) NDCR_SBERRM | /* single bit error ir masked */ NDCR_WRDREQM | /* write data request ir masked */ NDCR_RDDREQM | /* read data request ir masked */ - NDCR_WRCMDREQM); /* write command request ir masked */ + NDCR_WRCMDREQM, /* write command request ir masked */ + NDCR); /* wait 10 us due to cmd buffer clear reset */ diff --git a/drivers/mmc/pxa_mmc.c b/drivers/mmc/pxa_mmc.c index 87769033bbc..48e21ef7a59 100644 --- a/drivers/mmc/pxa_mmc.c +++ b/drivers/mmc/pxa_mmc.c @@ -27,6 +27,7 @@ #include #include #include +#include #include "pxa_mmc.h" @@ -59,18 +60,20 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) debug("mmc_cmd %u 0x%04x 0x%04x 0x%04x\n", cmd, argh, argl, cmdat | wide); - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_I_MASK = ~MMC_I_MASK_CLK_IS_OFF; - while (!(MMC_I_REG & MMC_I_REG_CLK_IS_OFF)) ; - MMC_CMD = cmd; - MMC_ARGH = argh; - MMC_ARGL = argl; - MMC_CMDAT = cmdat | wide; - MMC_I_MASK = ~MMC_I_MASK_END_CMD_RES; - MMC_STRPCL = MMC_STRPCL_START_CLK; - while (!(MMC_I_REG & MMC_I_REG_END_CMD_RES)) ; - - status = MMC_STAT; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(~MMC_I_MASK_CLK_IS_OFF, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_CLK_IS_OFF)) + ; + writel(cmd, MMC_CMD); + writel(argh, MMC_ARGH); + writel(argl, MMC_ARGL); + writel(cmdat | wide, MMC_CMDAT); + writel(~MMC_I_MASK_END_CMD_RES, MMC_I_MASK); + writel(MMC_STRPCL_START_CLK, MMC_STRPCL); + while (!(readl(MMC_I_REG) & MMC_I_REG_END_CMD_RES)) + ; + + status = readl(MMC_STAT); debug("MMC status 0x%08x\n", status); if (status & MMC_STAT_TIME_OUT_RESPONSE) { return 0; @@ -80,10 +83,10 @@ mmc_cmd(ushort cmd, ushort argh, ushort argl, ushort cmdat) * Did I mention this is Sick. We always need to * discard the upper 8 bits of the first 16-bit word. */ - a = (MMC_RES & 0xffff); + a = (readl(MMC_RES) & 0xffff); for (i = 0; i < 4; i++) { - b = (MMC_RES & 0xffff); - c = (MMC_RES & 0xffff); + b = (readl(MMC_RES) & 0xffff); + c = (readl(MMC_RES) & 0xffff); resp[i] = (a << 24) | (b << 8) | (c >> 8); a = c; debug("MMC resp[%d] = %#08x\n", i, resp[i]); @@ -115,37 +118,38 @@ mmc_block_read(uchar * dst, ulong src, ulong len) /* send read command */ argh = src >> 16; argl = src & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_RDTO = 0xffff; - MMC_NOB = 1; - MMC_BLKLEN = len; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(0xffff, MMC_RDTO); + writel(1, MMC_NOB); + writel(len, MMC_BLKLEN); mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); - MMC_I_MASK = ~MMC_I_MASK_RXFIFO_RD_REQ; + writel(~MMC_I_MASK_RXFIFO_RD_REQ, MMC_I_MASK); while (len) { - if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { + if (readl(MMC_I_REG) & MMC_I_REG_RXFIFO_RD_REQ) { #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) int i; for (i = min(len, 32); i; i--) { - *dst++ = *((volatile uchar *)&MMC_RXFIFO); + *dst++ = readb(MMC_RXFIFO); len--; } #else - *dst++ = MMC_RXFIFO; + *dst++ = readb(MMC_RXFIFO); len--; #endif } - status = MMC_STAT; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; } } - MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; - status = MMC_STAT; + writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) + ; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; @@ -176,37 +180,39 @@ mmc_block_write(ulong dst, uchar * src, int len) /* send write command */ argh = dst >> 16; argl = dst & 0xffff; - MMC_STRPCL = MMC_STRPCL_STOP_CLK; - MMC_NOB = 1; - MMC_BLKLEN = len; + writel(MMC_STRPCL_STOP_CLK, MMC_STRPCL); + writel(1, MMC_NOB); + writel(len, MMC_BLKLEN); mmc_cmd(MMC_CMD_WRITE_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_WRITE | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); - MMC_I_MASK = ~MMC_I_MASK_TXFIFO_WR_REQ; + writel(~MMC_I_MASK_TXFIFO_WR_REQ, MMC_I_MASK); while (len) { - if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { + if (readl(MMC_I_REG) & MMC_I_REG_TXFIFO_WR_REQ) { int i, bytes = min(32, len); for (i = 0; i < bytes; i++) { - MMC_TXFIFO = *src++; + writel(*src++, MMC_TXFIFO); } if (bytes < 32) { - MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL; + writel(MMC_PRTBUF_BUF_PART_FULL, MMC_PRTBUF); } len -= bytes; } - status = MMC_STAT; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; } } - MMC_I_MASK = ~MMC_I_MASK_DATA_TRAN_DONE; - while (!(MMC_I_REG & MMC_I_REG_DATA_TRAN_DONE)) ; - MMC_I_MASK = ~MMC_I_MASK_PRG_DONE; - while (!(MMC_I_REG & MMC_I_REG_PRG_DONE)) ; - status = MMC_STAT; + writel(~MMC_I_MASK_DATA_TRAN_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_DATA_TRAN_DONE)) + ; + writel(~MMC_I_MASK_PRG_DONE, MMC_I_MASK); + while (!(readl(MMC_I_REG) & MMC_I_REG_PRG_DONE)) + ; + status = readl(MMC_STAT); if (status & MMC_STAT_ERRORS) { printf("MMC_STAT error %lx\n", status); return -1; @@ -559,13 +565,13 @@ mmc_legacy_init(int verbose) set_GPIO_mode(GPIO8_MMCCS0_MD); #endif #ifdef CONFIG_CPU_MONAHANS /* pxa3xx */ - CKENA |= CKENA_12_MMC0 | CKENA_13_MMC1; + writel(readl(CKENA) | CKENA_12_MMC0 | CKENA_13_MMC1, CKENA); #else /* pxa2xx */ - CKEN |= CKEN12_MMC; /* enable MMC unit clock */ + writel(readl(CKEN) | CKEN12_MMC, CKEN); /* enable MMC unit clock */ #endif - MMC_CLKRT = MMC_CLKRT_0_3125MHZ; - MMC_RESTO = MMC_RES_TO_MAX; - MMC_SPI = MMC_SPI_DISABLE; + writel(MMC_CLKRT_0_3125MHZ, MMC_CLKRT); + writel(MMC_RES_TO_MAX, MMC_RESTO); + writel(MMC_SPI_DISABLE, MMC_SPI); /* reset */ mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); @@ -624,7 +630,7 @@ mmc_legacy_init(int verbose) mmc_decode_cid(cid_resp); } - MMC_CLKRT = 0; /* 20 MHz */ + writel(0, MMC_CLKRT); /* 20 MHz */ resp = mmc_cmd(MMC_CMD_SELECT_CARD, rca, 0, MMC_CMDAT_R1); #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS) diff --git a/drivers/serial/serial_pxa.c b/drivers/serial/serial_pxa.c index b74e43957ff..e4579801f2d 100644 --- a/drivers/serial/serial_pxa.c +++ b/drivers/serial/serial_pxa.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -73,60 +74,60 @@ void pxa_setbrg_dev (unsigned int uart_index) switch (uart_index) { case FFUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_22_FFUART; + writel(readl(CKENA) | CKENA_22_FFUART, CKENA); #else - CKEN |= CKEN6_FFUART; + writel(readl(CKEN) | CKEN6_FFUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - FFIER = 0; /* Disable for now */ - FFFCR = 0; /* No fifos enabled */ + writel(0, FFIER); /* Disable for now */ + writel(0, FFFCR); /* No fifos enabled */ /* set baud rate */ - FFLCR = LCR_WLS0 | LCR_WLS1 | LCR_DLAB; - FFDLL = quot & 0xff; - FFDLH = quot >> 8; - FFLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR); + writel(quot & 0xff, FFDLL); + writel(quot >> 8, FFDLH); + writel(LCR_WLS0 | LCR_WLS1, FFLCR); - FFIER = IER_UUE; /* Enable FFUART */ + writel(IER_UUE, FFIER); /* Enable FFUART */ break; case BTUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_21_BTUART; + writel(readl(CKENA) | CKENA_21_BTUART, CKENA); #else - CKEN |= CKEN7_BTUART; + writel(readl(CKEN) | CKEN7_BTUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - BTIER = 0; - BTFCR = 0; + writel(0, BTIER); + writel(0, BTFCR); /* set baud rate */ - BTLCR = LCR_DLAB; - BTDLL = quot & 0xff; - BTDLH = quot >> 8; - BTLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_DLAB, BTLCR); + writel(quot & 0xff, BTDLL); + writel(quot >> 8, BTDLH); + writel(LCR_WLS0 | LCR_WLS1, BTLCR); - BTIER = IER_UUE; /* Enable BFUART */ + writel(IER_UUE, BTIER); /* Enable BFUART */ break; case STUART_INDEX: #ifdef CONFIG_CPU_MONAHANS - CKENA |= CKENA_23_STUART; + writel(readl(CKENA) | CKENA_23_STUART, CKENA); #else - CKEN |= CKEN5_STUART; + writel(readl(CKEN) | CKEN5_STUART, CKEN); #endif /* CONFIG_CPU_MONAHANS */ - STIER = 0; - STFCR = 0; + writel(0, STIER); + writel(0, STFCR); /* set baud rate */ - STLCR = LCR_DLAB; - STDLL = quot & 0xff; - STDLH = quot >> 8; - STLCR = LCR_WLS0 | LCR_WLS1; + writel(LCR_DLAB, STLCR); + writel(quot & 0xff, STDLL); + writel(quot >> 8, STDLH); + writel(LCR_WLS0 | LCR_WLS1, STLCR); - STIER = IER_UUE; /* Enable STUART */ + writel(IER_UUE, STIER); /* Enable STUART */ break; default: @@ -156,21 +157,21 @@ void pxa_putc_dev (unsigned int uart_index,const char c) switch (uart_index) { case FFUART_INDEX: /* wait for room in the tx FIFO on FFUART */ - while ((FFLSR & LSR_TEMT) == 0) + while ((readl(FFLSR) & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - FFTHR = c; + writel(c, FFTHR); break; case BTUART_INDEX: - while ((BTLSR & LSR_TEMT ) == 0 ) + while ((readl(BTLSR) & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - BTTHR = c; + writel(c, BTTHR); break; case STUART_INDEX: - while ((STLSR & LSR_TEMT ) == 0 ) + while ((readl(STLSR) & LSR_TEMT) == 0) WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - STTHR = c; + writel(c, STTHR); break; } @@ -188,11 +189,11 @@ int pxa_tstc_dev (unsigned int uart_index) { switch (uart_index) { case FFUART_INDEX: - return FFLSR & LSR_DR; + return readl(FFLSR) & LSR_DR; case BTUART_INDEX: - return BTLSR & LSR_DR; + return readl(BTLSR) & LSR_DR; case STUART_INDEX: - return STLSR & LSR_DR; + return readl(STLSR) & LSR_DR; } return -1; } @@ -206,18 +207,21 @@ int pxa_getc_dev (unsigned int uart_index) { switch (uart_index) { case FFUART_INDEX: - while (!(FFLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) FFRBR & 0xff; + while (!(readl(FFLSR) & LSR_DR)) + /* Reset HW Watchdog, if needed */ + WATCHDOG_RESET(); + return (char) readl(FFRBR) & 0xff; case BTUART_INDEX: - while (!(BTLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) BTRBR & 0xff; + while (!(readl(BTLSR) & LSR_DR)) + /* Reset HW Watchdog, if needed */ + WATCHDOG_RESET(); + return (char) readl(BTRBR) & 0xff; case STUART_INDEX: - while (!(STLSR & LSR_DR)) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ - return (char) STRBR & 0xff; + while (!(readl(STLSR) & LSR_DR)) + /* Reset HW Watchdog, if needed */ + WATCHDOG_RESET(); + return (char) readl(STRBR) & 0xff; } return -1; } diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 200b61e0c7f..998e1792085 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -339,8 +339,6 @@ #define LED_IRDA1 2 #define LED_IRDA2 4 #define LED_IRDA3 6 -#define CRADLE_LED_SET_REG GPSR2 -#define CRADLE_LED_CLR_REG GPCR2 /* SuperIO defines */ #define CRADLE_SIO_INDEX 0x2e diff --git a/include/configs/delta.h b/include/configs/delta.h index 9c46c5bdbc3..d930fb4b2b1 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -28,6 +28,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_DELTA 1 /* Delta board */ /* #define CONFIG_LCD 1 */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index d0fc13888ec..c8aa0461f6a 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -35,6 +35,7 @@ * (easy to change) */ #define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ +#define CONFIG_CPU_PXA320 #define CONFIG_ZYLONITE 1 /* Zylonite board */ /* #define CONFIG_LCD 1 */ -- cgit v1.3.1 From aaa2a2fc9b81e0619da85244f5e9193a0a60003a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 18 Jul 2010 05:23:19 +0200 Subject: PXA: Palm Tungsten|C Support This patch adds support for the Palm Tungsten|C PXA255 board. The support includes: - LCD - MMC - UART - NOR Signed-off-by: Marek Vasut --- MAINTAINERS | 4 + board/palmtc/Makefile | 49 +++++++++ board/palmtc/config.mk | 1 + board/palmtc/lowlevel_init.S | 39 +++++++ board/palmtc/palmtc.c | 59 +++++++++++ board/palmtc/u-boot.lds | 56 ++++++++++ boards.cfg | 1 + include/configs/palmtc.h | 245 +++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 454 insertions(+) create mode 100644 board/palmtc/Makefile create mode 100644 board/palmtc/config.mk create mode 100644 board/palmtc/lowlevel_init.S create mode 100644 board/palmtc/palmtc.c create mode 100644 board/palmtc/u-boot.lds create mode 100644 include/configs/palmtc.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 4db587a708d..18cc6872c0b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -809,6 +809,10 @@ Greg Ungerer cm4116 ks8695p cm4148 ks8695p +Marek Vasut + + palmtc xscale + Hugo Villeneuve SFFSDR ARM926EJS diff --git a/board/palmtc/Makefile b/board/palmtc/Makefile new file mode 100644 index 00000000000..20ac4e154c1 --- /dev/null +++ b/board/palmtc/Makefile @@ -0,0 +1,49 @@ +# +# Palm Tungsten|C Support +# +# Copyright (C) 2009-2010 Marek Vasut +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := palmtc.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/palmtc/config.mk b/board/palmtc/config.mk new file mode 100644 index 00000000000..1d650acd993 --- /dev/null +++ b/board/palmtc/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/palmtc/lowlevel_init.S b/board/palmtc/lowlevel_init.S new file mode 100644 index 00000000000..74050dc70cb --- /dev/null +++ b/board/palmtc/lowlevel_init.S @@ -0,0 +1,39 @@ +/* + * Palm Tungsten|C Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup + + mov pc, lr diff --git a/board/palmtc/palmtc.c b/board/palmtc/palmtc.c new file mode 100644 index 00000000000..04cb33e6a89 --- /dev/null +++ b/board/palmtc/palmtc.c @@ -0,0 +1,59 @@ +/* + * Palm Tungsten|C Support + * + * Copyright (C) 2009-2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* Arch number of Palm Tungsten|C */ + gd->bd->bi_arch_number = MACH_TYPE_PALMTC; + + /* Adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Set PWM for LCD */ + writel(0x5f, PWM_CTRL1); + writel(0x3ff, PWM_PERVAL1); + writel(892, PWM_PWDUTY1); + + return 0; +} + +struct serial_device *default_serial_console(void) +{ + return &serial_ffuart_device; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + return 0; +} diff --git a/board/palmtc/u-boot.lds b/board/palmtc/u-boot.lds new file mode 100644 index 00000000000..fb4358beeab --- /dev/null +++ b/board/palmtc/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/boards.cfg b/boards.cfg index 1145bc88d69..7b863db9352 100644 --- a/boards.cfg +++ b/boards.cfg @@ -59,6 +59,7 @@ csb226 arm pxa delta arm pxa innokom arm pxa lubbock arm pxa +palmtc arm pxa pleb2 arm pxa xaeniax arm pxa xm250 arm pxa diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h new file mode 100644 index 00000000000..f4fc9cd50d9 --- /dev/null +++ b/include/configs/palmtc.h @@ -0,0 +1,245 @@ +/* + * Palm Tungsten|C configuration file + * + * Copyright (C) 2009-2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA250 1 /* Intel PXA255 CPU */ +#define CONFIG_PALMTC 1 /* Palm Tungsten|C board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x80000; " \ + "fi; " +#define CONFIG_BOOTARGS \ + "console=tty0 console=ttyS0,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + * STUART - the lower serial port on Colibri board + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#define CONFIG_CMD_MMC +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_ACX517AKN +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3686400 /* Timer @ 3686400 Hz */ +#define CONFIG_SYS_CPUSPEED 0x161 /* 400MHz;L=1 M=3 T=1 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 64 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x4000 +#define CONFIG_ENV_ADDR 0x40000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00011004 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5000008 +#define CONFIG_SYS_GAFR1_L_VAL 0x60888050 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50aaa +#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPDR0_VAL 0xcfff8140 +#define CONFIG_SYS_GPDR1_VAL 0xfcbfbef3 +#define CONFIG_SYS_GPDR2_VAL 0x0001ffff +#define CONFIG_SYS_GPSR0_VAL 0x00010f8f +#define CONFIG_SYS_GPSR1_VAL 0x00bf5de5 +#define CONFIG_SYS_GPSR2_VAL 0x03fe0800 + +#define CONFIG_SYS_PSSR_VAL PSSR_RDH + +/* Clock setup: + * CKEN[1] - PWM1 ; CKEN[6] - FFUART + * CKEN[12] - MMC ; CKEN[16] - LCD + */ +#define CONFIG_SYS_CKEN 0x00011042 +#define CONFIG_SYS_CCCR 0x00000161 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x800092c2 +#define CONFIG_SYS_MSC1_VAL 0x80008000 +#define CONFIG_SYS_MSC2_VAL 0x80008000 +#define CONFIG_SYS_MDCNFG_VAL 0x00001ac9 +#define CONFIG_SYS_MDREFR_VAL 0x00118018 +#define CONFIG_SYS_MDMRS_VAL 0x00220032 +#define CONFIG_SYS_FLYCNFG_VAL 0x01fe01fe +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00010504 +#define CONFIG_SYS_MCMEM1_VAL 0x00010504 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00010504 +#define CONFIG_SYS_MCIO0_VAL 0x00010e04 +#define CONFIG_SYS_MCIO1_VAL 0x00010e04 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From 6375dadab39991cca679b186f2949ccde5dac174 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 19 Jul 2010 11:23:07 +0200 Subject: PXA: Add initial Palm LifeDrive support Signed-off-by: Marek Vasut --- MAINTAINERS | 1 + board/palmld/Makefile | 49 ++++++++ board/palmld/config.mk | 1 + board/palmld/lowlevel_init.S | 45 +++++++ board/palmld/palmld.c | 69 +++++++++++ board/palmld/u-boot.lds | 56 +++++++++ boards.cfg | 1 + include/configs/palmld.h | 273 +++++++++++++++++++++++++++++++++++++++++++ 8 files changed, 495 insertions(+) create mode 100644 board/palmld/Makefile create mode 100644 board/palmld/config.mk create mode 100644 board/palmld/lowlevel_init.S create mode 100644 board/palmld/palmld.c create mode 100644 board/palmld/u-boot.lds create mode 100644 include/configs/palmld.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 18cc6872c0b..1de7a0d2493 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -811,6 +811,7 @@ Greg Ungerer Marek Vasut + palmld xscale palmtc xscale Hugo Villeneuve diff --git a/board/palmld/Makefile b/board/palmld/Makefile new file mode 100644 index 00000000000..bcb014db62d --- /dev/null +++ b/board/palmld/Makefile @@ -0,0 +1,49 @@ +# +# Palm LifeDrive Support +# +# Copyright (C) 2010 Marek Vasut +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := palmld.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/palmld/config.mk b/board/palmld/config.mk new file mode 100644 index 00000000000..1d650acd993 --- /dev/null +++ b/board/palmld/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/palmld/lowlevel_init.S b/board/palmld/lowlevel_init.S new file mode 100644 index 00000000000..e3382ee2f24 --- /dev/null +++ b/board/palmld/lowlevel_init.S @@ -0,0 +1,45 @@ +/* + * Palm LifeDrive Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + + /* Enable GPIO reset */ + ldr r0, =PCFR + mov r1, #0x30 + str r1, [r0] + + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup + + mov pc, lr diff --git a/board/palmld/palmld.c b/board/palmld/palmld.c new file mode 100644 index 00000000000..4f0087ea27b --- /dev/null +++ b/board/palmld/palmld.c @@ -0,0 +1,69 @@ +/* + * Palm LifeDrive Support + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* arch number of Lubbock-Board */ + gd->bd->bi_arch_number = MACH_TYPE_PALMLD; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Set PWM for LCD */ + writel(0x7, PWM_CTRL0); + writel(0x16c, PWM_PERVAL0); + writel(0x11a, PWM_PWDUTY0); + + return 0; +} + +struct serial_device *default_serial_console(void) +{ + return &serial_ffuart_device; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/palmld/u-boot.lds b/board/palmld/u-boot.lds new file mode 100644 index 00000000000..fb4358beeab --- /dev/null +++ b/board/palmld/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/boards.cfg b/boards.cfg index 7b863db9352..75643c92fb8 100644 --- a/boards.cfg +++ b/boards.cfg @@ -59,6 +59,7 @@ csb226 arm pxa delta arm pxa innokom arm pxa lubbock arm pxa +palmld arm pxa palmtc arm pxa pleb2 arm pxa xaeniax arm pxa diff --git a/include/configs/palmld.h b/include/configs/palmld.h new file mode 100644 index 00000000000..affc116b9f0 --- /dev/null +++ b/include/configs/palmld.h @@ -0,0 +1,273 @@ +/* + * Palm LifeDrive configuration file + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_PALMLD 1 /* Palm LifeDrive board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if mmcinfo && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "source 0xa0000000; " \ + "else " \ + "bootm 0x0x60000; " \ + "fi; " +#define CONFIG_BOOTARGS "console=tty0 console=ttyS0,9600" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_FFUART 1 +#define CONFIG_BAUDRATE 9600 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#define CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_MMC +#define CONFIG_CMD_IDE +#define CONFIG_LCD + +/* + * MMC Card Configuration + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_DOS_PARTITION +#endif + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_LQ038J7DH53 +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x210 /* 416MHz ; N=2,L=16 */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00080000 /* 512 KB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 + +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x4000 + +/* + * IDE + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_LBA48 +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +#define __io + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0x10 +#define CONFIG_SYS_ATA_REG_OFFSET 0x10 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x10 + +#define CONFIG_SYS_ATA_STRIDE 1 +#endif + +/* + * GPIO settings + */ +#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5180012 +#define CONFIG_SYS_GAFR1_L_VAL 0x69988056 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa580aa +#define CONFIG_SYS_GAFR2_L_VAL 0x6aaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01040001 +#define CONFIG_SYS_GAFR3_L_VAL 0x540a950c +#define CONFIG_SYS_GAFR3_U_VAL 0x00000009 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0xc26b0000 +#define CONFIG_SYS_GPDR1_VAL 0xfcdfaa93 +#define CONFIG_SYS_GPDR2_VAL 0x7bbaffff +#define CONFIG_SYS_GPDR3_VAL 0x006ff38d +#define CONFIG_SYS_GPSR0_VAL 0x0d9e45ee +#define CONFIG_SYS_GPSR1_VAL 0x03affdae +#define CONFIG_SYS_GPSR2_VAL 0x07554000 +#define CONFIG_SYS_GPSR3_VAL 0x01bc0785 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x01ffffff +#define CONFIG_SYS_CCCR 0x02000210 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff844c8 +#define CONFIG_SYS_MSC1_VAL 0x7ff86ab4 +#define CONFIG_SYS_MSC2_VAL 0x7ff87ff8 +#define CONFIG_SYS_MDCNFG_VAL 0x0B880acd +#define CONFIG_SYS_MDREFR_VAL 0x201fa031 +#define CONFIG_SYS_MDMRS_VAL 0x00320032 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000003 +#define CONFIG_SYS_MCMEM0_VAL 0x0001c391 +#define CONFIG_SYS_MCMEM1_VAL 0x0001c391 +#define CONFIG_SYS_MCATT0_VAL 0x0001c391 +#define CONFIG_SYS_MCATT1_VAL 0x0001c391 +#define CONFIG_SYS_MCIO0_VAL 0x00014611 +#define CONFIG_SYS_MCIO1_VAL 0x0001c391 + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From f905432c04c54ef169b4ffe6dd310ddf72a67c86 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 22 Jul 2010 16:51:52 +0200 Subject: PXA: Voipac270 improvements 128MB NOR module support. Define __io to get harddrive working. Fix saving of environment into OneNAND. Boot from harddrive when possible. Add missing MAINTAINERS entry. Signed-off-by: Marek Vasut --- MAINTAINERS | 1 + MAKEALL | 3 +- Makefile | 7 ++- board/vpac270/Makefile | 7 +-- board/vpac270/lowlevel_init.S | 1 - board/vpac270/vpac270.c | 44 +++++++----------- include/configs/vpac270.h | 106 ++++++++++++++++++++++++------------------ 7 files changed, 88 insertions(+), 81 deletions(-) (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 1de7a0d2493..303e955c6d2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -813,6 +813,7 @@ Marek Vasut palmld xscale palmtc xscale + vpac270 xscale Hugo Villeneuve diff --git a/MAKEALL b/MAKEALL index c1f3842aad4..01eb1536cfb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -471,7 +471,8 @@ LIST_at91=" \ LIST_pxa="$(boards_by_cpu pxa) polaris \ trizepsiv \ - vpac270_nor \ + vpac270_nor_128M\ + vpac270_nor_256M\ vpac270_onenand \ " diff --git a/Makefile b/Makefile index 30a564d3cbd..d18a973a244 100644 --- a/Makefile +++ b/Makefile @@ -1018,13 +1018,18 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv -vpac270_nor_config \ +vpac270_nor_256M_config \ +vpac270_nor_128M_config \ vpac270_onenand_config : unconfig @mkdir -p $(obj)include @if [ "$(findstring onenand,$@)" ] ; then \ echo "#define CONFIG_ONENAND_U_BOOT" \ >>$(obj)include/config.h ; \ fi; + @if [ "$(findstring 256M,$@)" ] ; then \ + echo "#define CONFIG_256M_U_BOOT" \ + >>$(obj)include/config.h ; \ + fi; @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270 ######################################################################### diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index c6f4c7c36f4..f5014fc2534 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -1,10 +1,7 @@ - # -# (C) Copyright 2000 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# Voipac PXA270 Support # -# See file CREDITS for list of people who contributed to this -# project. +# Copyright (C) 2010 Marek Vasut # # This program is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S index ec0d12c8545..c40d12fa140 100644 --- a/board/vpac270/lowlevel_init.S +++ b/board/vpac270/lowlevel_init.S @@ -3,7 +3,6 @@ * * Copyright (C) 2010 Marek Vasut * - * * See file CREDITS for list of people who contributed to this * project. * diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index f7922980c8b..1557d1baf05 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -1,16 +1,7 @@ /* - * (C) Copyright 2004 - * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net + * Voipac PXA270 Support * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * See file CREDITS for list of people who contributed to this - * project. + * Copyright (C) 2010 Marek Vasut * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -36,26 +27,15 @@ DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ - /* * Miscelaneous platform dependent initialisations */ -extern struct serial_device serial_ffuart_device; -extern struct serial_device serial_btuart_device; -extern struct serial_device serial_stuart_device; - -struct serial_device *default_serial_console (void) -{ - return &serial_ffuart_device; -} - -int board_init (void) +int board_init(void) { /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ - /* arch number of vpac270 */ + /* Arch number of vpac270 */ gd->bd->bi_arch_number = MACH_TYPE_VPAC270; /* adress of boot parameters */ @@ -64,17 +44,24 @@ int board_init (void) return 0; } -int dram_init (void) +struct serial_device *default_serial_console(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + return &serial_ffuart_device; +} +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#ifdef CONFIG_256M_U_BOOT + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +#endif return 0; } +#ifdef CONFIG_CMD_USB int usb_board_init(void) { writel((UHCHR | UHCHR_PCPL | UHCHR_PSPL) & @@ -124,6 +111,7 @@ void usb_board_stop(void) return; } +#endif #ifdef CONFIG_DRIVER_DM9000 int board_eth_init(bd_t *bis) diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index d3e22d9018d..694a8f92c46 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -10,7 +10,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -19,8 +19,8 @@ * MA 02111-1307 USA */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __CONFIG_H +#define __CONFIG_H /* * High Level Board Configuration Options @@ -28,20 +28,13 @@ #define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ #define CONFIG_VPAC270 1 /* Voipac PXA270 board */ -#undef BOARD_LATE_INIT -#undef CONFIG_SKIP_RELOCATE_UBOOT -#undef CONFIG_USE_IRQ -#undef CONFIG_SKIP_LOWLEVEL_INIT - /* * Environment settings */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 -#define CONFIG_ENV_OVERWRITE /* override default environment */ - #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ @@ -49,6 +42,9 @@ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ + "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ "bootm 0x40000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP @@ -97,9 +93,9 @@ #define CONFIG_NET_MULTI 1 #define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) +#define CONFIG_DM9000_BASE 0x08000300 /* CS2 */ +#define DM9000_IO (CONFIG_DM9000_BASE) +#define DM9000_DATA (CONFIG_DM9000_BASE + 4) #define CONFIG_NET_RETRY_COUNT 10 #define CONFIG_BOOTP_BOOTFILESIZE @@ -116,6 +112,7 @@ #define CONFIG_PXA_MMC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 #define CONFIG_DOS_PARTITION #endif @@ -123,8 +120,8 @@ * KGDB */ #ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /* @@ -133,16 +130,17 @@ #define CONFIG_SYS_HUSH_PARSER 1 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LONGHELP #ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "$ " #else -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " #endif -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_DEVICE_NULLDEV 1 /* @@ -150,12 +148,10 @@ */ #undef CONFIG_SYS_CLKS_IN_HZ #define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ -#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */ +#define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* * Stack sizes - * - * The stack sizes are set up in start.S using the settings below */ #define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ @@ -166,17 +162,24 @@ /* * DRAM Map */ -#define CONFIG_NR_DRAM_BANKS 2 /* We have 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 2 /* 2 banks of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ + +#ifdef CONFIG_256M_U_BOOT #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ +#else +#define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ +#endif -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) @@ -185,14 +188,22 @@ */ #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#ifdef CONFIG_256M_U_BOOT #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ +#endif #define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#else +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#endif #define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) #define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) @@ -200,25 +211,26 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 #define CONFIG_SYS_FLASH_PROTECTION 1 -#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE 0x4000 #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ONENAND_BASE 0x00000000 + #define CONFIG_ENV_IS_IN_ONENAND 1 +#define CONFIG_ENV_SECT_SIZE 0x20000 #else /* No flash */ #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_BASE 0x0 #define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SIZE 0x4000 /* * IDE @@ -230,15 +242,15 @@ #define __io -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 +#define CONFIG_SYS_ATA_BASE_ADDR 0x0c000000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 -#define CONFIG_SYS_ATA_REG_OFFSET 0x120 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 +#define CONFIG_SYS_ATA_DATA_OFFSET 0x120 +#define CONFIG_SYS_ATA_REG_OFFSET 0x120 +#define CONFIG_SYS_ATA_ALT_OFFSET 0x120 #define CONFIG_SYS_ATA_STRIDE 2 #endif @@ -284,7 +296,11 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 +#ifdef CONFIG_256M_U_BOOT #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 +#else +#define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 +#endif #define CONFIG_SYS_MDREFR_VAL 0x201fe01e #define CONFIG_SYS_MDMRS_VAL 0x00000000 #define CONFIG_SYS_FLYCNFG_VAL 0x00000000 @@ -306,13 +322,13 @@ * LCD */ #ifdef CONFIG_LCD -#define CONFIG_VOIPAC_LCD +#define CONFIG_VOIPAC_LCD #endif /* * USB */ -#ifdef CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_BOARD_INIT -- cgit v1.3.1 From 10da95a13af7266cf1e6332e7abc37c0d5682b43 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 26 Jul 2010 06:30:25 +0200 Subject: PXA: Balloon3 board support The following hardware is currently supported: - UART - USB Host - FPGA Signed-off-by: Marek Vasut --- MAINTAINERS | 1 + board/balloon3/Makefile | 49 ++++++++ board/balloon3/balloon3.c | 228 ++++++++++++++++++++++++++++++++++ board/balloon3/config.mk | 1 + board/balloon3/lowlevel_init.S | 36 ++++++ board/balloon3/u-boot.lds | 55 +++++++++ boards.cfg | 1 + include/configs/balloon3.h | 269 +++++++++++++++++++++++++++++++++++++++++ 8 files changed, 640 insertions(+) create mode 100644 board/balloon3/Makefile create mode 100644 board/balloon3/balloon3.c create mode 100644 board/balloon3/config.mk create mode 100644 board/balloon3/lowlevel_init.S create mode 100644 board/balloon3/u-boot.lds create mode 100644 include/configs/balloon3.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 303e955c6d2..3dea70ab5e5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -811,6 +811,7 @@ Greg Ungerer Marek Vasut + balloon3 xscale palmld xscale palmtc xscale vpac270 xscale diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile new file mode 100644 index 00000000000..3928e1f0662 --- /dev/null +++ b/board/balloon3/Makefile @@ -0,0 +1,49 @@ +# +# Balloon3 Support +# +# Copyright (C) 2010 Marek Vasut +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := balloon3.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c new file mode 100644 index 00000000000..2d6eabee738 --- /dev/null +++ b/board/balloon3/balloon3.c @@ -0,0 +1,228 @@ +/* + * Balloon3 Support + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +void balloon3_init_fpga(void); + +/* + * Miscelaneous platform dependent initialisations + */ + +int board_init(void) +{ + /* arch number of vpac270 */ + gd->bd->bi_arch_number = MACH_TYPE_BALLOON3; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + /* Init the FPGA */ + balloon3_init_fpga(); + + return 0; +} + +struct serial_device *default_serial_console(void) +{ + return &serial_stuart_device; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + + return 0; +} + +#ifdef CONFIG_CMD_USB +int usb_board_init(void) +{ + writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & + ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), + UHCHR); + + writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); + + while (readl(UHCHR) & UHCHR_FSBIR) + ; + + writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); + writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); + + /* Clear any OTG Pin Hold */ + if (readl(PSSR) & PSSR_OTGPH) + writel(readl(PSSR) | PSSR_OTGPH, PSSR); + + writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); + writel(readl(UHCRHDA) | 0x100, UHCRHDA); + + /* Set port power control mask bits, only 3 ports. */ + writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); + + /* enable port 2 */ + writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | + UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); + + return 0; +} + +void usb_board_init_fail(void) +{ + return; +} + +void usb_board_stop(void) +{ + writel(readl(UHCHR) | UHCHR_FHR, UHCHR); + udelay(11); + writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); + + writel(readl(UHCCOMS) | 1, UHCCOMS); + udelay(10); + + writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); + + return; +} +#endif + +#if defined(CONFIG_FPGA) +/* Toggle GPIO103 and GPIO104 -- PROGB and RDnWR */ +int fpga_pgm_fn(int nassert, int nflush, int cookie) +{ + if (nassert) + writel(0x80, GPCR3); + else + writel(0x80, GPSR3); + if (nflush) + writel(0x100, GPCR3); + else + writel(0x100, GPSR3); + return nassert; +} + +/* Check GPIO83 -- INITB */ +int fpga_init_fn(int cookie) +{ + return !(readl(GPLR2) & 0x80000); +} + +/* Check GPIO84 -- BUSY */ +int fpga_busy_fn(int cookie) +{ + return !(readl(GPLR2) & 0x100000); +} + +/* Check GPIO111 -- DONE */ +int fpga_done_fn(int cookie) +{ + return readl(GPLR3) & 0x8000; +} + +/* Configure GPIO104 as GPIO and deassert it */ +int fpga_pre_config_fn(int cookie) +{ + writel(readl(GAFR3_L) & ~0x30000, GAFR3_L); + writel(0x100, GPCR3); + return 0; +} + +/* Configure GPIO104 as nSKTSEL */ +int fpga_post_config_fn(int cookie) +{ + writel(readl(GAFR3_L) | 0x10000, GAFR3_L); + return 0; +} + +/* Toggle RDnWR */ +int fpga_wr_fn(int nassert_write, int flush, int cookie) +{ + udelay(1000); + + if (nassert_write) + writel(0x100, GPCR3); + else + writel(0x100, GPSR3); + + return nassert_write; +} + +/* Write program to the FPGA */ +int fpga_wdata_fn(uchar data, int flush, int cookie) +{ + writeb(data, 0x10f00000); + return 0; +} + +/* Toggle Clock pin -- NO-OP */ +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + return assert_clk; +} + +/* Toggle ChipSelect pin -- NO-OP */ +int fpga_cs_fn(int assert_clk, int flush, int cookie) +{ + return assert_clk; +} + +Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_init_fn, + NULL, /* err */ + fpga_done_fn, + fpga_clk_fn, + fpga_cs_fn, + fpga_wr_fn, + NULL, /* rdata */ + fpga_wdata_fn, + fpga_busy_fn, + NULL, /* abort */ + fpga_post_config_fn, +}; + +Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel, + (void *)&balloon3_fpga_fns, 0); + +/* Initialize the FPGA */ +void balloon3_init_fpga(void) +{ + fpga_init(); + fpga_add(fpga_xilinx, &fpga); +} +#else +void balloon3_init_fpga(void) {} +#endif /* CONFIG_FPGA */ diff --git a/board/balloon3/config.mk b/board/balloon3/config.mk new file mode 100644 index 00000000000..1d650acd993 --- /dev/null +++ b/board/balloon3/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0xa1000000 diff --git a/board/balloon3/lowlevel_init.S b/board/balloon3/lowlevel_init.S new file mode 100644 index 00000000000..d7b5be66256 --- /dev/null +++ b/board/balloon3/lowlevel_init.S @@ -0,0 +1,36 @@ +/* + * Balloon3 Lowlevel Hardware Initialization + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include + +.globl lowlevel_init +lowlevel_init: + pxa_gpio_setup + pxa_wait_ticks 0x8000 + pxa_mem_setup + pxa_wakeup + pxa_intr_setup + pxa_clock_setup + + mov pc, lr diff --git a/board/balloon3/u-boot.lds b/board/balloon3/u-boot.lds new file mode 100644 index 00000000000..58c371df06b --- /dev/null +++ b/board/balloon3/u-boot.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/boards.cfg b/boards.cfg index 75643c92fb8..4dba72e9f90 100644 --- a/boards.cfg +++ b/boards.cfg @@ -53,6 +53,7 @@ actux2 arm ixp actux3 arm ixp actux4 arm ixp ixdp425 arm ixp +balloon3 arm pxa cerf250 arm pxa cradle arm pxa csb226 arm pxa diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h new file mode 100644 index 00000000000..9066a243043 --- /dev/null +++ b/include/configs/balloon3.h @@ -0,0 +1,269 @@ +/* + * Balloon3 configuration file + * + * Copyright (C) 2010 Marek Vasut + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Board Configuration Options + */ +#define CONFIG_PXA27X 1 /* Marvell PXA270 CPU */ +#define CONFIG_BALLOON3 1 /* Balloon3 board */ + +/* + * Environment settings + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_SYS_MALLOC_LEN (128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +#define CONFIG_BOOTCOMMAND \ + "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ + "bootm 0xa4000000; " \ + "fi; " \ + "bootm 0x40000;" +#define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" +#define CONFIG_TIMESTAMP +#define CONFIG_BOOTDELAY 2 /* Autoboot delay */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS + +#define CONFIG_LZMA /* LZMA compression support */ + +/* + * Serial Console Configuration + */ +#define CONFIG_PXA_SERIAL +#define CONFIG_STUART 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Bootloader Components Configuration + */ +#include + +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_ENV +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_USB +#define CONFIG_CMD_FPGA +#undef CONFIG_LCD + +/* + * KGDB + */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* kgdb serial port speed */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * HUSH Shell Configuration + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " +#else +#define CONFIG_SYS_PROMPT "=> " +#endif +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +/* + * Clock Configuration + */ +#undef CONFIG_SYS_CLKS_IN_HZ +#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ + +/* + * Stack sizes + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * DRAM Map + */ +#define CONFIG_NR_DRAM_BANKS 3 /* 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_2 0xb0000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ +#define PHYS_SDRAM_3 0x80000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_3_SIZE 0x08000000 /* 128 MB */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ +#define CONFIG_SYS_DRAM_SIZE 0x18000000 /* 384 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 + +/* + * NOR FLASH + */ +#ifdef CONFIG_CMD_FLASH +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */ +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_PROTECTION +#define CONFIG_ENV_IS_IN_FLASH +#else +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_ENV_IS_NOWHERE +#endif + +#define CONFIG_SYS_MONITOR_BASE 0x000000 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR 0x40000 +#define CONFIG_ENV_SECT_SIZE 0x10000 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x307dc7fd +#define CONFIG_SYS_GPSR1_VAL 0x03cffa4e +#define CONFIG_SYS_GPSR2_VAL 0x7131c000 +#define CONFIG_SYS_GPSR3_VAL 0x01e1f3ff + +#define CONFIG_SYS_GPCR0_VAL 0x0 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPCR3_VAL 0x0 + +#define CONFIG_SYS_GPDR0_VAL 0xc0f98e02 +#define CONFIG_SYS_GPDR1_VAL 0xfcffa8b7 +#define CONFIG_SYS_GPDR2_VAL 0x22e3ffff +#define CONFIG_SYS_GPDR3_VAL 0x000201fe + +#define CONFIG_SYS_GAFR0_L_VAL 0x96c00000 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5e5459b +#define CONFIG_SYS_GAFR1_L_VAL 0x699b759a +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5a5aa +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x01f9a6aa +#define CONFIG_SYS_GAFR3_L_VAL 0x54510003 +#define CONFIG_SYS_GAFR3_U_VAL 0x00001599 + +#define CONFIG_SYS_PSSR_VAL 0x30 + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0xffffffff +#define CONFIG_SYS_CCCR 0x00000290 + +/* + * Memory settings + */ +#define CONFIG_SYS_MSC0_VAL 0x7ff07ff8 +#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0 +#define CONFIG_SYS_MSC2_VAL 0x74a42491 +#define CONFIG_SYS_MDCNFG_VAL 0x89d309d3 +#define CONFIG_SYS_MDREFR_VAL 0x001d8018 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 +#define CONFIG_SYS_MEM_BUF_IMP 0x0f + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000000 +#define CONFIG_SYS_MCMEM0_VAL 0x00014307 +#define CONFIG_SYS_MCMEM1_VAL 0x00014307 +#define CONFIG_SYS_MCATT0_VAL 0x0001c787 +#define CONFIG_SYS_MCATT1_VAL 0x0001c787 +#define CONFIG_SYS_MCIO0_VAL 0x0001430f +#define CONFIG_SYS_MCIO1_VAL 0x0001430f + +/* + * LCD + */ +#ifdef CONFIG_LCD +#define CONFIG_BALLOON3LCD +#define CONFIG_VIDEO_LOGO +#define CONFIG_CMD_BMP +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) +#endif + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_BOARD_INIT +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4C000000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "balloon3" +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#endif + +/* + * FPGA + */ +#ifdef CONFIG_CMD_FPGA +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_SYS_FPGA_PROG_FEEDBACK +#define CONFIG_SYS_FPGA_WAIT 1000 +#define CONFIG_MAX_FPGA_DEVICES 1 +#endif + +#endif /* __CONFIG_H */ -- cgit v1.3.1 From b2b67baca318d7f3a5940c5a07f924601fa4c885 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Thu, 26 Aug 2010 23:24:18 +0400 Subject: PXA: cleanup vpac270 config and set CONFIG_SYS_HZ to 1000 * CONFIG_SYS_CLKS_IN_HZ is not used anywhere, so removing it * CONFIG_SYS_HZ is set to 1000 on most architectures, so it seems to be the safe default Signed-off-by: Mikhail Kshevetskiy --- include/configs/vpac270.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 694a8f92c46..4c18d3a788e 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -146,8 +146,7 @@ /* * Clock Configuration */ -#undef CONFIG_SYS_CLKS_IN_HZ -#define CONFIG_SYS_HZ 3250000 /* Timer @ 3250000 Hz */ +#define CONFIG_SYS_HZ 1000 /* Timer @ 3250000 Hz */ #define CONFIG_SYS_CPUSPEED 0x190 /* 312MHz */ /* -- cgit v1.3.1 From 11934fbf520a02e3ddff95607c60e79efad7dab1 Mon Sep 17 00:00:00 2001 From: Mikhail Kshevetskiy Date: Thu, 26 Aug 2010 23:24:19 +0400 Subject: PXA: fix environment sector size, kernel and environment location for vpac270 Define ENV_ADDR as MONITOR_BASE + MONITOR_LEN. Fix environment sector size (NOR: 32Kb for first four sectors and 128Kb for other; OneNAND: 128Kb). Last but not least: we have MONITOR_LEN = 0x40000 and one sector for environment (size = 0x20000), so the kernel may start from 0x00060000 only. Signed-off-by: Mikhail Kshevetskiy --- include/configs/vpac270.h | 25 +++++++++++++++++-------- 1 file changed, 17 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 4c18d3a788e..b8440a12418 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -45,7 +45,7 @@ "if ide reset && fatload ide 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ - "bootm 0x40000;" + "bootm 0x60000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS0,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ @@ -185,6 +185,12 @@ /* * NOR FLASH */ +#define CONFIG_SYS_MONITOR_BASE 0x0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x4000 + #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ @@ -211,7 +217,16 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE 0x4000 + +/* + * The first four sectors of the NOR flash are 0x8000 bytes big, the rest of the + * flash consists of 0x20000 bytes big sectors. + */ +#if (CONFIG_ENV_ADDR <= 0x18000) +#define CONFIG_ENV_SECT_SIZE 0x8000 +#else +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif #elif defined(CONFIG_CMD_ONENAND) /* OneNAND */ #define CONFIG_SYS_NO_FLASH @@ -225,12 +240,6 @@ #define CONFIG_SYS_ENV_IS_NOWHERE #endif -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -#define CONFIG_ENV_ADDR 0x40000 -#define CONFIG_ENV_SIZE 0x4000 - /* * IDE */ -- cgit v1.3.1 From 6ef6eb91cda895de3366068fc2caf25328786f4d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 23 Sep 2010 09:46:57 +0200 Subject: PXA: Add necessary information for RELOC Signed-off-by: Marek Vasut --- board/vpac270/vpac270.c | 11 ++++++++++- include/configs/balloon3.h | 3 +++ include/configs/cerf250.h | 3 +++ include/configs/colibri_pxa270.h | 3 +++ include/configs/cradle.h | 3 +++ include/configs/csb226.h | 3 +++ include/configs/delta.h | 3 +++ include/configs/innokom.h | 3 +++ include/configs/lubbock.h | 3 +++ include/configs/palmld.h | 3 +++ include/configs/palmtc.h | 3 +++ include/configs/pleb2.h | 3 +++ include/configs/pxa255_idp.h | 3 +++ include/configs/trizepsiv.h | 3 +++ include/configs/vpac270.h | 3 +++ include/configs/wepep250.h | 4 ++++ include/configs/xaeniax.h | 3 +++ include/configs/xm250.h | 3 +++ include/configs/xsengine.h | 3 +++ include/configs/zipitz2.h | 3 +++ include/configs/zylonite.h | 2 ++ 21 files changed, 70 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 1557d1baf05..f91ff97b2c4 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -49,7 +49,17 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } + int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; +#ifdef CONFIG_256M_U_BOOT + gd->ram_size += PHYS_SDRAM_2_SIZE; +#endif + return 0; +} + +void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; @@ -58,7 +68,6 @@ int dram_init(void) gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; #endif - return 0; } #ifdef CONFIG_CMD_USB diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 9066a243043..5e2a2851f12 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -130,6 +130,9 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index 477b94aa619..98b69e37127 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -161,6 +161,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h index 277ff67bf0b..5f457f80deb 100644 --- a/include/configs/colibri_pxa270.h +++ b/include/configs/colibri_pxa270.h @@ -169,6 +169,9 @@ #define CONFIG_SYS_LOAD_ADDR (0xa1000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/cradle.h b/include/configs/cradle.h index 998e1792085..d1c1a48e0c9 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -145,6 +145,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/csb226.h b/include/configs/csb226.h index 0661d65aba4..ae05734a09e 100644 --- a/include/configs/csb226.h +++ b/include/configs/csb226.h @@ -181,6 +181,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + # if 0 /* FIXME: switch to _documented_ registers */ /* diff --git a/include/configs/delta.h b/include/configs/delta.h index d930fb4b2b1..d53acbfebcf 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -218,6 +218,9 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NAND Flash */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index 9cb0d42eac7..007ccebf436 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -192,6 +192,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * JFFS2 partitions * diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h index 0a6921044c7..3a99ec25c4b 100644 --- a/include/configs/lubbock.h +++ b/include/configs/lubbock.h @@ -176,6 +176,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #define FPGA_REGS_BASE_PHYSICAL 0x08000000 /* diff --git a/include/configs/palmld.h b/include/configs/palmld.h index affc116b9f0..926728b15f4 100644 --- a/include/configs/palmld.h +++ b/include/configs/palmld.h @@ -154,6 +154,9 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h index f4fc9cd50d9..fe87648ac60 100644 --- a/include/configs/palmtc.h +++ b/include/configs/palmtc.h @@ -155,6 +155,9 @@ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h index 9e694118c5d..3b6e60afe9f 100644 --- a/include/configs/pleb2.h +++ b/include/configs/pleb2.h @@ -179,6 +179,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 6c1defc9ae8..4581674ed3a 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -292,6 +292,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h index fa5aae8a5c5..474349537bd 100644 --- a/include/configs/trizepsiv.h +++ b/include/configs/trizepsiv.h @@ -212,6 +212,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * GPIO settings */ diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index b8440a12418..1bcd2f3e049 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -181,6 +181,9 @@ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1) /* * NOR FLASH diff --git a/include/configs/wepep250.h b/include/configs/wepep250.h index 9a20cce457b..a961a27922c 100644 --- a/include/configs/wepep250.h +++ b/include/configs/wepep250.h @@ -183,6 +183,10 @@ #define CONFIG_ENV_ADDR 0x20000 /* absolute address for now */ #define CONFIG_ENV_SIZE 0x2000 +#define PHYS_SDRAM_1 WEP_SDRAM_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + #undef CONFIG_ENV_OVERWRITE /* env is not writable now */ /* diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 1329f0f3d85..67d4106d6f1 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -167,6 +167,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index cd56ce72e7c..2ff9a2813ad 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -174,6 +174,9 @@ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * FLASH and environment organization */ diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index f68461bb227..9606b5316bf 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -53,6 +53,9 @@ #define CONFIG_SYS_DRAM_BASE 0xa0000000 #define CONFIG_SYS_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* FLASH organization */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index a5a873ba3cf..642c5753bbb 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -175,6 +175,9 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) + /* * NOR FLASH */ diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index c8aa0461f6a..c33ca2de918 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -190,6 +190,8 @@ #undef CONFIG_SYS_SKIP_DRAM_SCRUB +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) /* * NAND Flash -- cgit v1.3.1 From 720a650caa510bf8e941f8da247fc572958f3c3d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 28 Sep 2010 15:50:49 +0200 Subject: PXA: Fix vpac270 for Reloc Signed-off-by: Marek Vasut --- board/vpac270/Makefile | 10 ++++------ board/vpac270/config.mk | 1 - board/vpac270/lowlevel_init.S | 39 --------------------------------------- board/vpac270/vpac270.c | 10 ++++++---- include/configs/vpac270.h | 6 +++--- 5 files changed, 13 insertions(+), 53 deletions(-) delete mode 100644 board/vpac270/config.mk delete mode 100644 board/vpac270/lowlevel_init.S (limited to 'include') diff --git a/board/vpac270/Makefile b/board/vpac270/Makefile index f5014fc2534..c3599178da7 100644 --- a/board/vpac270/Makefile +++ b/board/vpac270/Makefile @@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := vpac270.o -SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: - rm -f $(SOBJS) $(OBJS) + rm -f $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/vpac270/config.mk b/board/vpac270/config.mk deleted file mode 100644 index 0f10662ce38..00000000000 --- a/board/vpac270/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0xa1000000 diff --git a/board/vpac270/lowlevel_init.S b/board/vpac270/lowlevel_init.S deleted file mode 100644 index c40d12fa140..00000000000 --- a/board/vpac270/lowlevel_init.S +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Voipac PXA270 Lowlevel Hardware Initialization - * - * Copyright (C) 2010 Marek Vasut - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - pxa_gpio_setup - pxa_wait_ticks 0x8000 - pxa_mem_setup - pxa_wakeup - pxa_intr_setup - pxa_clock_setup - - mov pc, lr diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index f91ff97b2c4..91d85800bbf 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -32,6 +32,10 @@ DECLARE_GLOBAL_DATA_PTR; */ int board_init(void) { + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ @@ -49,13 +53,11 @@ struct serial_device *default_serial_console(void) return &serial_ffuart_device; } - +extern void pxa_dram_init(void); int dram_init(void) { + pxa_dram_init(); gd->ram_size = PHYS_SDRAM_1_SIZE; -#ifdef CONFIG_256M_U_BOOT - gd->ram_size += PHYS_SDRAM_2_SIZE; -#endif return 0; } diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 1bcd2f3e049..1923a177a11 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -34,7 +34,7 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ @@ -51,7 +51,7 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -183,7 +183,7 @@ #define CONFIG_SYS_LOAD_ADDR (0x5c000000) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_GBL_DATA_SIZE + CONFIG_STACKSIZE + PHYS_SDRAM_1) + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) /* * NOR FLASH -- cgit v1.3.1 From 24e84c3dcbfc732888fecc502b7b560b4e372876 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 30 Sep 2010 12:22:38 +0200 Subject: PXA: Fix ZipitZ2 for Reloc Signed-off-by: Marek Vasut --- board/zipitz2/Makefile | 10 ++++------ board/zipitz2/config.mk | 1 - board/zipitz2/lowlevel_init.S | 40 ---------------------------------------- board/zipitz2/zipitz2.c | 24 ++++++++++++------------ include/configs/zipitz2.h | 9 +++++---- 5 files changed, 21 insertions(+), 63 deletions(-) delete mode 100644 board/zipitz2/config.mk delete mode 100644 board/zipitz2/lowlevel_init.S (limited to 'include') diff --git a/board/zipitz2/Makefile b/board/zipitz2/Makefile index 267383550ac..8d452de63cb 100644 --- a/board/zipitz2/Makefile +++ b/board/zipitz2/Makefile @@ -29,17 +29,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := zipitz2.o -SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: - rm -f $(SOBJS) $(OBJS) + rm -f $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/zipitz2/config.mk b/board/zipitz2/config.mk deleted file mode 100644 index 0f10662ce38..00000000000 --- a/board/zipitz2/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0xa1000000 diff --git a/board/zipitz2/lowlevel_init.S b/board/zipitz2/lowlevel_init.S deleted file mode 100644 index 82a52e84c48..00000000000 --- a/board/zipitz2/lowlevel_init.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Aeronix Zipit Z2 Lowlevel Hardware Initialization - * - * Copyright (C) 2010 Marek Vasut - * - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - pxa_gpio_setup - pxa_wait_ticks 0x8000 - pxa_mem_setup - pxa_wakeup - pxa_intr_setup - pxa_clock_setup - - mov pc, lr diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index f7edc4c8cab..9e6a0d51c4e 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -44,10 +44,11 @@ inline void lcd_start(void) {}; int board_init (void) { - /* memory and cpu-speed are setup before relocation */ - /* so we do _nothing_ here */ + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); - /* arch number of Lubbock-Board */ + /* arch number of Z2 */ gd->bd->bi_arch_number = MACH_TYPE_ZIPIT2; /* adress of boot parameters */ @@ -59,24 +60,23 @@ int board_init (void) return 0; } -int board_late_init(void) +struct serial_device *default_serial_console (void) { - setenv("stdout", "serial"); - setenv("stderr", "serial"); - return 0; + return &serial_stuart_device; } -struct serial_device *default_serial_console (void) +extern void pxa_dram_init(void); +int dram_init(void) { - return &serial_stuart_device; + pxa_dram_init(); + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; } -int dram_init (void) +void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; } #ifdef CONFIG_CMD_SPI diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 642c5753bbb..ce65d1f1c6e 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -41,8 +41,9 @@ #define CONFIG_ENV_ADDR 0x40000 #define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_STACKSIZE) +#define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 512 +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ @@ -56,7 +57,7 @@ #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -176,7 +177,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048) /* * NOR FLASH @@ -221,7 +222,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_GPCR3_VAL 0x00000000 #define CONFIG_SYS_GPDR0_VAL 0xdafcee00 #define CONFIG_SYS_GPDR1_VAL 0xffa3aaab -#define CONFIG_SYS_GPDR2_VAL 0x8fe1ffff +#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff #define CONFIG_SYS_GPDR3_VAL 0x001b1f8a #define CONFIG_SYS_GPSR0_VAL 0x06080400 #define CONFIG_SYS_GPSR1_VAL 0x007f0000 -- cgit v1.3.1 From 20ae5193e325ad005ca9e15377838e0763069658 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 3 Oct 2010 01:05:55 +0200 Subject: PXA: Fix Balloon3 for Reloc Signed-off-by: Marek Vasut --- board/balloon3/Makefile | 10 +++----- board/balloon3/balloon3.c | 14 +++++++++-- board/balloon3/config.mk | 1 - board/balloon3/lowlevel_init.S | 36 --------------------------- board/balloon3/u-boot.lds | 55 ------------------------------------------ include/configs/balloon3.h | 10 +++++--- 6 files changed, 22 insertions(+), 104 deletions(-) delete mode 100644 board/balloon3/config.mk delete mode 100644 board/balloon3/lowlevel_init.S delete mode 100644 board/balloon3/u-boot.lds (limited to 'include') diff --git a/board/balloon3/Makefile b/board/balloon3/Makefile index 3928e1f0662..7db615e943b 100644 --- a/board/balloon3/Makefile +++ b/board/balloon3/Makefile @@ -24,17 +24,15 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS := balloon3.o -SOBJS := lowlevel_init.o -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) clean: - rm -f $(SOBJS) $(OBJS) + rm -f $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/balloon3/balloon3.c b/board/balloon3/balloon3.c index 2d6eabee738..26e34e99d7d 100644 --- a/board/balloon3/balloon3.c +++ b/board/balloon3/balloon3.c @@ -36,6 +36,10 @@ void balloon3_init_fpga(void); int board_init(void) { + /* We have RAM, disable cache */ + dcache_disable(); + icache_disable(); + /* arch number of vpac270 */ gd->bd->bi_arch_number = MACH_TYPE_BALLOON3; @@ -53,7 +57,15 @@ struct serial_device *default_serial_console(void) return &serial_stuart_device; } +extern void pxa_dram_init(void); int dram_init(void) +{ + pxa_dram_init(); + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[1].start = PHYS_SDRAM_2; @@ -62,8 +74,6 @@ int dram_init(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; - - return 0; } #ifdef CONFIG_CMD_USB diff --git a/board/balloon3/config.mk b/board/balloon3/config.mk deleted file mode 100644 index 1d650acd993..00000000000 --- a/board/balloon3/config.mk +++ /dev/null @@ -1 +0,0 @@ -TEXT_BASE = 0xa1000000 diff --git a/board/balloon3/lowlevel_init.S b/board/balloon3/lowlevel_init.S deleted file mode 100644 index d7b5be66256..00000000000 --- a/board/balloon3/lowlevel_init.S +++ /dev/null @@ -1,36 +0,0 @@ -/* - * Balloon3 Lowlevel Hardware Initialization - * - * Copyright (C) 2010 Marek Vasut - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include - -.globl lowlevel_init -lowlevel_init: - pxa_gpio_setup - pxa_wait_ticks 0x8000 - pxa_mem_setup - pxa_wakeup - pxa_intr_setup - pxa_clock_setup - - mov pc, lr diff --git a/board/balloon3/u-boot.lds b/board/balloon3/u-boot.lds deleted file mode 100644 index 58c371df06b..00000000000 --- a/board/balloon3/u-boot.lds +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - cpu/pxa/start.o (.text) - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata) } - - . = ALIGN(4); - .data : { *(.data) } - - . = ALIGN(4); - .got : { *(.got) } - - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - . = ALIGN(4); - __bss_start = .; - .bss : { *(.bss) } - _end = .; -} diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h index 5e2a2851f12..ae60f2eb3c1 100644 --- a/include/configs/balloon3.h +++ b/include/configs/balloon3.h @@ -34,18 +34,19 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_SYS_MALLOC_LEN (128*1024) #define CONFIG_SYS_GBL_DATA_SIZE 128 - +#define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ + "fpga load 0x0 0x50000 0x62638; " \ "if usb reset && fatload usb 0 0xa4000000 uImage; then " \ "bootm 0xa4000000; " \ "fi; " \ - "bootm 0x40000;" + "bootm 0xd0000;" #define CONFIG_BOOTARGS "console=tty0 console=ttyS2,115200" #define CONFIG_TIMESTAMP #define CONFIG_BOOTDELAY 2 /* Autoboot delay */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS - +#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_LZMA /* LZMA compression support */ /* @@ -131,7 +132,8 @@ #define CONFIG_SYS_LOAD_ADDR 0xa1000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_SP_ADDR \ + (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) /* * NOR FLASH -- cgit v1.3.1 From 451a0c39ae8553cb7f1ae3385211c0c17d391465 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 16 Oct 2010 21:32:11 +0200 Subject: PXA: Fix vpac270 OneNAND booter NOTE: The modification in Makefile will be superseded by a pending patch! Signed-off-by: Marek Vasut --- Makefile | 2 ++ include/configs/vpac270.h | 3 ++- onenand_ipl/board/vpac270/Makefile | 5 +++-- 3 files changed, 7 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index d18a973a244..25e8fc83e09 100644 --- a/Makefile +++ b/Makefile @@ -1025,6 +1025,8 @@ vpac270_onenand_config : unconfig @if [ "$(findstring onenand,$@)" ] ; then \ echo "#define CONFIG_ONENAND_U_BOOT" \ >>$(obj)include/config.h ; \ + echo "#define CONFIG_256M_U_BOOT" \ + >>$(obj)include/config.h ; \ fi; @if [ "$(findstring 256M,$@)" ] ; then \ echo "#define CONFIG_256M_U_BOOT" \ diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index 1923a177a11..fc680fcd83c 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -180,7 +180,8 @@ #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR (0x5c000000) +#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 +#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000) #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR \ (PHYS_SDRAM_1 + CONFIG_SYS_GBL_DATA_SIZE + 2048) diff --git a/onenand_ipl/board/vpac270/Makefile b/onenand_ipl/board/vpac270/Makefile index ac7a8f05e6c..a86bc00864c 100644 --- a/onenand_ipl/board/vpac270/Makefile +++ b/onenand_ipl/board/vpac270/Makefile @@ -1,5 +1,6 @@ -IPL =onenand_ipl + include $(TOPDIR)/config.mk +include $(TOPDIR)/board/$(BOARDDIR)/config.mk LDSCRIPT= $(TOPDIR)/onenand_ipl/board/$(BOARDDIR)/u-boot.onenand.lds LDFLAGS = -Bstatic -T $(onenandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(PLATFORM_LDFLAGS) @@ -25,7 +26,7 @@ ALL = $(onenandobj)onenand-ipl $(onenandobj)onenand-ipl.bin $(onenandobj)onenand all: $(obj).depend $(ALL) $(onenandobj)onenand-ipl-2k.bin: $(onenandobj)onenand-ipl - $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x5c040400 -O binary $< $@ + $(OBJCOPY) ${OBJCFLAGS} --pad-to=0x0800 -O binary $< $@ $(onenandobj)onenand-ipl.bin: $(onenandobj)onenand-ipl $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ -- cgit v1.3.1 From f97e9c65b3906cd656c14ed0fd35eae0c1649857 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 3 Oct 2010 18:27:36 +0200 Subject: Build: PXA: Fix Vpac270 build variants Signed-off-by: Marek Vasut --- MAKEALL | 3 --- Makefile | 16 ---------------- board/vpac270/vpac270.c | 2 +- boards.cfg | 3 +++ include/configs/vpac270.h | 12 ++++++------ 5 files changed, 10 insertions(+), 26 deletions(-) (limited to 'include') diff --git a/MAKEALL b/MAKEALL index 01eb1536cfb..5eb857082c7 100755 --- a/MAKEALL +++ b/MAKEALL @@ -471,9 +471,6 @@ LIST_at91=" \ LIST_pxa="$(boards_by_cpu pxa) polaris \ trizepsiv \ - vpac270_nor_128M\ - vpac270_nor_256M\ - vpac270_onenand \ " LIST_ixp="$(boards_by_cpu ixp) diff --git a/Makefile b/Makefile index 25e8fc83e09..8078d71d93a 100644 --- a/Makefile +++ b/Makefile @@ -1018,22 +1018,6 @@ trizepsiv_config : unconfig fi; @$(MKCONFIG) -n $@ -a trizepsiv arm pxa trizepsiv -vpac270_nor_256M_config \ -vpac270_nor_128M_config \ -vpac270_onenand_config : unconfig - @mkdir -p $(obj)include - @if [ "$(findstring onenand,$@)" ] ; then \ - echo "#define CONFIG_ONENAND_U_BOOT" \ - >>$(obj)include/config.h ; \ - echo "#define CONFIG_256M_U_BOOT" \ - >>$(obj)include/config.h ; \ - fi; - @if [ "$(findstring 256M,$@)" ] ; then \ - echo "#define CONFIG_256M_U_BOOT" \ - >>$(obj)include/config.h ; \ - fi; - @$(MKCONFIG) -n $@ -a vpac270 arm pxa vpac270 - ######################################################################### ## ARM1136 Systems ######################################################################### diff --git a/board/vpac270/vpac270.c b/board/vpac270/vpac270.c index 91d85800bbf..43bbdff70e2 100644 --- a/board/vpac270/vpac270.c +++ b/board/vpac270/vpac270.c @@ -66,7 +66,7 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; #endif diff --git a/boards.cfg b/boards.cfg index 4dba72e9f90..9717ed32b70 100644 --- a/boards.cfg +++ b/boards.cfg @@ -63,6 +63,9 @@ lubbock arm pxa palmld arm pxa palmtc arm pxa pleb2 arm pxa +vpac270_nor_128 arm pxa vpac270 - - vpac270:NOR,RAM_128M +vpac270_nor_256 arm pxa vpac270 - - vpac270:NOR,RAM_256M +vpac270_ond_256 arm pxa vpac270 - - vpac270:ONENAND,RAM_256M xaeniax arm pxa xm250 arm pxa zipitz2 arm pxa diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h index fc680fcd83c..c9d9c69cda8 100644 --- a/include/configs/vpac270.h +++ b/include/configs/vpac270.h @@ -75,7 +75,7 @@ #undef CONFIG_LCD #define CONFIG_CMD_IDE -#ifdef CONFIG_ONENAND_U_BOOT +#ifdef CONFIG_ONENAND #undef CONFIG_CMD_FLASH #define CONFIG_CMD_ONENAND #else @@ -165,13 +165,13 @@ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_SDRAM_2 0x80000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ #endif #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_DRAM_SIZE 0x10000000 /* 256 MB DRAM */ #else #define CONFIG_SYS_DRAM_SIZE 0x08000000 /* 128 MB DRAM */ @@ -198,7 +198,7 @@ #if defined(CONFIG_CMD_FLASH) /* NOR */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define PHYS_FLASH_2 0x02000000 /* Flash Bank #2 */ #endif @@ -206,7 +206,7 @@ #define CONFIG_FLASH_CFI_DRIVER 1 #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MAX_FLASH_BANKS 2 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } #else @@ -308,7 +308,7 @@ #define CONFIG_SYS_MSC0_VAL 0x3ffc95fa #define CONFIG_SYS_MSC1_VAL 0x02ccf974 #define CONFIG_SYS_MSC2_VAL 0x00000000 -#ifdef CONFIG_256M_U_BOOT +#ifdef CONFIG_RAM_256M #define CONFIG_SYS_MDCNFG_VAL 0x8ad30ad3 #else #define CONFIG_SYS_MDCNFG_VAL 0x88000ad3 -- cgit v1.3.1 From cebcf7da2106d1294c71528b8e2f3532818ef989 Mon Sep 17 00:00:00 2001 From: Jens Scharsig Date: Tue, 19 Oct 2010 19:37:15 +0200 Subject: update board EB+CPUx9K2 * update to support arm reloaction * unnecessary environment variables removed Signed-off-by: Jens Scharsig --- board/BuS/eb_cpux9k2/config.mk | 1 - board/BuS/eb_cpux9k2/cpux9k2.c | 7 +++---- include/configs/eb_cpux9k2.h | 23 ++++++++--------------- 3 files changed, 11 insertions(+), 20 deletions(-) delete mode 100644 board/BuS/eb_cpux9k2/config.mk (limited to 'include') diff --git a/board/BuS/eb_cpux9k2/config.mk b/board/BuS/eb_cpux9k2/config.mk deleted file mode 100644 index e554a450073..00000000000 --- a/board/BuS/eb_cpux9k2/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x23f00000 diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index bbceaf37ae7..fe62a0fcafa 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -66,7 +66,7 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_EB_CPUX9K2; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_STATUS_LED status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); @@ -134,9 +134,8 @@ void reset_phy(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = - get_ram_size((volatile long *) PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); return 0; } diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index 4ff4a85cb52..8d8af93792f 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -42,7 +42,7 @@ #define CONFIG_MISC_INIT_R /*--------------------------------------------------------------------------*/ - +#define CONFIG_SYS_TEXT_BASE 0x00000000 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */ @@ -98,12 +98,14 @@ */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00204000 /* use internal SRAM */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - PHYS_SDRAM_SIZE - 0x00400000 - \ + CONFIG_SYS_SDRAM_SIZE - 0x00400000 - \ CONFIG_SYS_MALLOC_LEN) #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* PIOC as D16/D31 */ @@ -249,6 +251,7 @@ /* FLASH organization */ /* NOR-FLASH */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_FLASH_CFI_DRIVER 1 @@ -396,16 +399,6 @@ "nandboot=run bootargsdefaults;" \ "set bootargs $(bootargs) root=initramfs boot=nand " \ ";bootm $(kerneladdr)\0" \ - "uu=run update_uboot\0" \ - "ur=run update_root;run nk\0" \ - "nk=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=local " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ - "nn=run bootargsdefaults;set bootargs $(bootargs) root=initramfs " \ - "boot=nand " \ - ";echo $(bootargs)" \ - ";dhcp uImage_cpux9k2;bootm\0" \ " " /*--------------------------------------------------------------------------*/ -- cgit v1.3.1