From b62b55ba4b2d1cabd6bb0943685c3115f6ee8bd3 Mon Sep 17 00:00:00 2001
From: Ryan Chen <ryan_chen@aspeedtech.com>
Date: Fri, 12 Jun 2026 17:43:09 +0800
Subject: arm: aspeed: add ASPEED AST2700 SoC family support

Add initial support for the ASPEED AST2700, an arm64 (Cortex-A35)
Baseboard Management Controller (BMC) SoC. AST2700 is Aspeed's 8th
generation BMC and uses a dual-die architecture: SoC0 (the "CPU"
die) hosts the four Cortex-A35 cores and its own SCU at 0x12c02000,
while SoC1 (the "IO" die) hosts the peripherals and its own SCU at
0x14c02000.

This commit adds:
  - ASPEED_AST2700 Kconfig option and the ast2700 mach subdir
    (mach Makefile, ast2700/Kconfig, board/aspeed/evb_ast2700/*)
  - arm64 MMU map covering the SoC device window and the DRAM
    region at 0x4_0000_0000 (up to 8 GiB)
  - lowlevel_init.S for early CPU bring-up
  - cpu-info: print SoC ID (AST2700/2720/2750 A0/A1/A2 variants)
    and reset cause (cold reset, EXT reset, WDT reset)
  - board_common: dram_init via UCLASS_RAM, AHBC timeout init
  - platform: env_get_location() that selects SPI/eMMC based on
    the IO-die HW strap; arch_misc_init() that exposes
    ${boot_device} and ${verify} to the boot script
  - SCU0/SCU1 register layout header (scu_ast2700.h)
  - configs/evb-ast2700_defconfig and include/configs/evb_ast2700.h
    for the AST2700 EVB board

The defconfig depends on ast2700-evb.dts, which is introduced in
a subsequent patch; this commit must be applied with the
remaining series for evb-ast2700_defconfig to build.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 include/configs/evb_ast2700.h | 58 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 include/configs/evb_ast2700.h

(limited to 'include')

diff --git a/include/configs/evb_ast2700.h b/include/configs/evb_ast2700.h
new file mode 100644
index 00000000000..6b73eddc1af
--- /dev/null
+++ b/include/configs/evb_ast2700.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) ASPEED Technology Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/aspeed-common.h>
+
+/* Extra ENV for Boot Command */
+#define STR_HELPER(n)	#n
+#define STR(n)		STR_HELPER(n)
+
+#define CFG_SYS_UBOOT_BASE		CONFIG_TEXT_BASE
+
+#define CFG_EXTRA_ENV_SETTINGS \
+	"bootspi=fdt addr ${fdtspiaddr} && "				\
+		"fdt header get fitsize totalsize && "			\
+		"cp.b ${fdtspiaddr} ${loadaddr} ${fitsize} && "		\
+		"bootm ${loadaddr}; "					\
+		"echo Error loading kernel FIT image\0"			\
+	"loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0"			\
+	"bootside=a\0"							\
+	"rootfs=rofs-a\0"						\
+	"setmmcargs=setenv bootargs ${bootargs} "			\
+		"rootwait root=PARTLABEL=${rootfs}\0"			\
+	"boota=setenv bootpart 2; setenv rootfs rofs-a; "		\
+		"run setmmcargs; "					\
+		"ext4load mmc 0:${bootpart} ${loadaddr} fitImage && "	\
+		"bootm ${loadaddr}; "					\
+		"echo Error loading kernel FIT image\0"			\
+	"bootb=setenv bootpart 3; setenv rootfs rofs-b; "		\
+		"run setmmcargs; "					\
+		"ext4load mmc 0:${bootpart} ${loadaddr} fitImage && "	\
+		"bootm ${loadaddr}; "					\
+		"echo Error loading kernel FIT image\0"			\
+	"bootmmc=if test \"${bootside}\" = \"b\"; "			\
+		"then run bootb; run boota; "				\
+		"else run boota; run bootb; fi\0"			\
+	"setufsargs=setenv bootargs ${bootargs} "			\
+		"rootwait root=PARTLABEL=${rootfs}\0"			\
+	"ufsboota=setenv bootpart 2; setenv rootfs rofs-a; "		\
+		"run setufsargs; "					\
+		"ext4load scsi 0:${bootpart} ${loadaddr} fitImage && "	\
+		"bootm ${loadaddr}; "					\
+		"echo Error loading kernel FIT image\0"			\
+	"ufsbootb=setenv bootpart 3; setenv rootfs rofs-b; "		\
+		"run setufsargs; "					\
+		"ext4load scsi 0:${bootpart} ${loadaddr} fitImage && "	\
+		"bootm ${loadaddr}; "					\
+		"echo Error loading kernel FIT image\0"			\
+	"bootufs=if test \"${bootside}\" = \"b\"; "			\
+		"then run ufsbootb; run ufsboota; "			\
+		"else run ufsboota; run ufsbootb; fi\0"			\
+	"verify=no\0"							\
+	""
+#endif	/* __CONFIG_H */
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