From 6c5052716e252d8ccbf161042b5a167fb1090030 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 22 Oct 2015 19:13:26 -0700 Subject: x86: Rename CONFIG_SYS_NUM_IRQS to SYS_NUM_IRQS CONFIG_SYS_NUM_IRQS is actually not something we can configure, but an architecture defined number of ISA IRQs. Move it from x86-common.h to asm/interrupt.h and rename it to SYS_NUM_IRQS. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/x86-common.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index faadab83ce6..2e90ef509d0 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -157,7 +157,6 @@ #define CONFIG_SYS_X86_TSC_TIMER #define CONFIG_SYS_PCAT_INTERRUPTS #define CONFIG_SYS_PCAT_TIMER -#define CONFIG_SYS_NUM_IRQS 16 #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -- cgit v1.3.1 From da3fe247591e17dead357f05f69124c54aa13a01 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 22 Oct 2015 19:13:30 -0700 Subject: x86: Rename pcat_ to i8254 and i8259 accordingly Rename pcat_timer.c to i8254.c and pcat_interrupts.c to i8259.c, to match their header file names (i8254.h and i8259.h). Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/interrupts.c | 2 +- arch/x86/include/asm/u-boot-x86.h | 2 +- arch/x86/lib/Makefile | 4 +- arch/x86/lib/i8254.c | 37 +++++++++++ arch/x86/lib/i8259.c | 129 ++++++++++++++++++++++++++++++++++++++ arch/x86/lib/pcat_interrupts.c | 129 -------------------------------------- arch/x86/lib/pcat_timer.c | 37 ----------- arch/x86/lib/tsc_timer.c | 6 +- include/configs/x86-common.h | 4 +- 9 files changed, 175 insertions(+), 175 deletions(-) create mode 100644 arch/x86/lib/i8254.c create mode 100644 arch/x86/lib/i8259.c delete mode 100644 arch/x86/lib/pcat_interrupts.c delete mode 100644 arch/x86/lib/pcat_timer.c (limited to 'include') diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index addd26e4e62..b00ddc0cb48 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -252,7 +252,7 @@ int interrupt_init(void) /* Just in case... */ disable_interrupts(); -#ifdef CONFIG_SYS_PCAT_INTERRUPTS +#ifdef CONFIG_I8259_PIC /* Initialize the master/slave i8259 pic */ i8259_init(); #endif diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 1c459d5ae34..dbf8e95c1b3 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -29,7 +29,7 @@ typedef void (timer_fnc_t) (void); int register_timer_isr (timer_fnc_t *isr_func); unsigned long get_tbclk_mhz(void); void timer_set_base(uint64_t base); -int pcat_timer_init(void); +int i8254_init(void); /* cpu/.../interrupts.c */ int cpu_init_interrupts(void); diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 2f82a21aff1..d676e2c14f2 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -19,8 +19,8 @@ obj-y += lpc-uclass.o obj-y += mpspec.o obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o obj-y += cmd_mtrr.o -obj-$(CONFIG_SYS_PCAT_INTERRUPTS) += pcat_interrupts.o -obj-$(CONFIG_SYS_PCAT_TIMER) += pcat_timer.o +obj-$(CONFIG_I8259_PIC) += i8259.o +obj-$(CONFIG_I8254_TIMER) += i8254.o ifndef CONFIG_DM_PCI obj-$(CONFIG_PCI) += pci_type1.o endif diff --git a/arch/x86/lib/i8254.c b/arch/x86/lib/i8254.c new file mode 100644 index 00000000000..46a42452893 --- /dev/null +++ b/arch/x86/lib/i8254.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define TIMER1_VALUE 18 /* 15.6us */ +#define TIMER2_VALUE 0x0a8e /* 440Hz */ + +int i8254_init(void) +{ + /* + * Initialize counter 1, used to refresh request signal. + * This is required for legacy purpose as some codes like + * vgabios utilizes counter 1 to provide delay functionality. + */ + outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2, + PIT_BASE + PIT_COMMAND); + outb(TIMER1_VALUE, PIT_BASE + PIT_T1); + + /* + * Initialize counter 2, used to drive the speaker. + * To start a beep, set both bit0 and bit1 of port 0x61. + * To stop it, clear both bit0 and bit1 of port 0x61. + */ + outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, + PIT_BASE + PIT_COMMAND); + outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); + outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); + + return 0; +} diff --git a/arch/x86/lib/i8259.c b/arch/x86/lib/i8259.c new file mode 100644 index 00000000000..b9d06140d43 --- /dev/null +++ b/arch/x86/lib/i8259.c @@ -0,0 +1,129 @@ +/* + * (C) Copyright 2009 + * Graeme Russ, + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file provides the interrupt handling functionality for systems + * based on the standard PC/AT architecture using two cascaded i8259 + * Programmable Interrupt Controllers. + */ + +#include +#include +#include +#include +#include + +int i8259_init(void) +{ + u8 i; + + /* Mask all interrupts */ + outb(0xff, MASTER_PIC + IMR); + outb(0xff, SLAVE_PIC + IMR); + + /* + * Master PIC + * Place master PIC interrupts at INT20 + */ + outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1); + outb(0x20, MASTER_PIC + ICW2); + outb(IR2, MASTER_PIC + ICW3); + outb(ICW4_PM, MASTER_PIC + ICW4); + + for (i = 0; i < 8; i++) + outb(OCW2_SEOI | i, MASTER_PIC + OCW2); + + /* + * Slave PIC + * Place slave PIC interrupts at INT28 + */ + outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1); + outb(0x28, SLAVE_PIC + ICW2); + outb(0x02, SLAVE_PIC + ICW3); + outb(ICW4_PM, SLAVE_PIC + ICW4); + + for (i = 0; i < 8; i++) + outb(OCW2_SEOI | i, SLAVE_PIC + OCW2); + + /* + * Enable cascaded interrupts by unmasking the cascade IRQ pin of + * the master PIC + */ + unmask_irq(2); + + /* Interrupt 9 should be level triggered (SCI). The OS might do this */ + configure_irq_trigger(9, true); + + return 0; +} + +void mask_irq(int irq) +{ + int imr_port; + + if (irq >= SYS_NUM_IRQS) + return; + + if (irq > 7) + imr_port = SLAVE_PIC + IMR; + else + imr_port = MASTER_PIC + IMR; + + outb(inb(imr_port) | (1 << (irq & 7)), imr_port); +} + +void unmask_irq(int irq) +{ + int imr_port; + + if (irq >= SYS_NUM_IRQS) + return; + + if (irq > 7) + imr_port = SLAVE_PIC + IMR; + else + imr_port = MASTER_PIC + IMR; + + outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port); +} + +void specific_eoi(int irq) +{ + if (irq >= SYS_NUM_IRQS) + return; + + if (irq > 7) { + /* + * IRQ is on the slave - Issue a corresponding EOI to the + * slave PIC and an EOI for IRQ2 (the cascade interrupt) + * on the master PIC + */ + outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2); + irq = SEOI_IR2; + } + + outb(OCW2_SEOI | irq, MASTER_PIC + OCW2); +} + +void configure_irq_trigger(int int_num, bool is_level_triggered) +{ + u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); + + debug("%s: current interrupts are 0x%x\n", __func__, int_bits); + if (is_level_triggered) + int_bits |= (1 << int_num); + else + int_bits &= ~(1 << int_num); + + /* Write new values */ + debug("%s: try to set interrupts 0x%x\n", __func__, int_bits); + outb((u8)(int_bits & 0xff), ELCR1); + outb((u8)(int_bits >> 8), ELCR2); +} diff --git a/arch/x86/lib/pcat_interrupts.c b/arch/x86/lib/pcat_interrupts.c deleted file mode 100644 index b9d06140d43..00000000000 --- a/arch/x86/lib/pcat_interrupts.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2009 - * Graeme Russ, - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file provides the interrupt handling functionality for systems - * based on the standard PC/AT architecture using two cascaded i8259 - * Programmable Interrupt Controllers. - */ - -#include -#include -#include -#include -#include - -int i8259_init(void) -{ - u8 i; - - /* Mask all interrupts */ - outb(0xff, MASTER_PIC + IMR); - outb(0xff, SLAVE_PIC + IMR); - - /* - * Master PIC - * Place master PIC interrupts at INT20 - */ - outb(ICW1_SEL | ICW1_EICW4, MASTER_PIC + ICW1); - outb(0x20, MASTER_PIC + ICW2); - outb(IR2, MASTER_PIC + ICW3); - outb(ICW4_PM, MASTER_PIC + ICW4); - - for (i = 0; i < 8; i++) - outb(OCW2_SEOI | i, MASTER_PIC + OCW2); - - /* - * Slave PIC - * Place slave PIC interrupts at INT28 - */ - outb(ICW1_SEL | ICW1_EICW4, SLAVE_PIC + ICW1); - outb(0x28, SLAVE_PIC + ICW2); - outb(0x02, SLAVE_PIC + ICW3); - outb(ICW4_PM, SLAVE_PIC + ICW4); - - for (i = 0; i < 8; i++) - outb(OCW2_SEOI | i, SLAVE_PIC + OCW2); - - /* - * Enable cascaded interrupts by unmasking the cascade IRQ pin of - * the master PIC - */ - unmask_irq(2); - - /* Interrupt 9 should be level triggered (SCI). The OS might do this */ - configure_irq_trigger(9, true); - - return 0; -} - -void mask_irq(int irq) -{ - int imr_port; - - if (irq >= SYS_NUM_IRQS) - return; - - if (irq > 7) - imr_port = SLAVE_PIC + IMR; - else - imr_port = MASTER_PIC + IMR; - - outb(inb(imr_port) | (1 << (irq & 7)), imr_port); -} - -void unmask_irq(int irq) -{ - int imr_port; - - if (irq >= SYS_NUM_IRQS) - return; - - if (irq > 7) - imr_port = SLAVE_PIC + IMR; - else - imr_port = MASTER_PIC + IMR; - - outb(inb(imr_port) & ~(1 << (irq & 7)), imr_port); -} - -void specific_eoi(int irq) -{ - if (irq >= SYS_NUM_IRQS) - return; - - if (irq > 7) { - /* - * IRQ is on the slave - Issue a corresponding EOI to the - * slave PIC and an EOI for IRQ2 (the cascade interrupt) - * on the master PIC - */ - outb(OCW2_SEOI | (irq & 7), SLAVE_PIC + OCW2); - irq = SEOI_IR2; - } - - outb(OCW2_SEOI | irq, MASTER_PIC + OCW2); -} - -void configure_irq_trigger(int int_num, bool is_level_triggered) -{ - u16 int_bits = inb(ELCR1) | (((u16)inb(ELCR2)) << 8); - - debug("%s: current interrupts are 0x%x\n", __func__, int_bits); - if (is_level_triggered) - int_bits |= (1 << int_num); - else - int_bits &= ~(1 << int_num); - - /* Write new values */ - debug("%s: try to set interrupts 0x%x\n", __func__, int_bits); - outb((u8)(int_bits & 0xff), ELCR1); - outb((u8)(int_bits >> 8), ELCR2); -} diff --git a/arch/x86/lib/pcat_timer.c b/arch/x86/lib/pcat_timer.c deleted file mode 100644 index 347cdda9f6b..00000000000 --- a/arch/x86/lib/pcat_timer.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define TIMER1_VALUE 18 /* 15.6us */ -#define TIMER2_VALUE 0x0a8e /* 440Hz */ - -int pcat_timer_init(void) -{ - /* - * Initialize counter 1, used to refresh request signal. - * This is required for legacy purpose as some codes like - * vgabios utilizes counter 1 to provide delay functionality. - */ - outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2, - PIT_BASE + PIT_COMMAND); - outb(TIMER1_VALUE, PIT_BASE + PIT_T1); - - /* - * Initialize counter 2, used to drive the speaker. - * To start a beep, set both bit0 and bit1 of port 0x61. - * To stop it, clear both bit0 and bit1 of port 0x61. - */ - outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, - PIT_BASE + PIT_COMMAND); - outb(TIMER2_VALUE & 0xff, PIT_BASE + PIT_T2); - outb(TIMER2_VALUE >> 8, PIT_BASE + PIT_T2); - - return 0; -} diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index 0df1af238c1..e02b918843b 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -368,9 +368,9 @@ void __udelay(unsigned long usec) int timer_init(void) { -#ifdef CONFIG_SYS_PCAT_TIMER - /* Set up the PCAT timer if required */ - pcat_timer_init(); +#ifdef CONFIG_I8254_TIMER + /* Set up the i8254 timer if required */ + i8254_init(); #endif return 0; diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 2e90ef509d0..58d2f427dee 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -155,8 +155,8 @@ */ #define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_SYS_PCAT_INTERRUPTS -#define CONFIG_SYS_PCAT_TIMER +#define CONFIG_I8259_PIC +#define CONFIG_I8254_TIMER #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -- cgit v1.3.1 From 1eb39a509354ae3c199c739bfb2d3a0d442e2cac Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Thu, 22 Oct 2015 19:13:31 -0700 Subject: x86: Move CONFIG_8259_PIC and CONFIG_8254_TIMER to Kconfig Add Kconfig options for 8259 and 8254. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/Kconfig | 15 +++++++++++++++ include/configs/x86-common.h | 2 -- 2 files changed, 15 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index f92082d4766..8914be34e68 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -420,6 +420,21 @@ config PCIE_ECAM_SIZE so a default 0x10000000 size covers all of the 256 buses which is the maximum number of PCI buses as defined by the PCI specification. +config I8259_PIC + bool + default y + help + Intel 8259 ISA compatible chipset incorporates two 8259 (master and + slave) interrupt controllers. Include this to have U-Boot set up + the interrupt correctly. + +config I8254_TIMER + bool + default y + help + Intel 8254 timer contains three counters which have fixed uses. + Include this to have U-Boot set up the timer correctly. + source "arch/x86/lib/efi/Kconfig" endmenu diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 58d2f427dee..ab9fa0b0821 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -155,8 +155,6 @@ */ #define CONFIG_SYS_X86_TSC_TIMER -#define CONFIG_I8259_PIC -#define CONFIG_I8254_TIMER #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -- cgit v1.3.1 From 487485956b1f980e8147283069a7af920f25a52c Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Nov 2015 02:04:49 -0800 Subject: x86: qemu: Move chipset-specific codes from pci.c to qemu.c Move chipset-specific codes such as PAM init, PCIe ECAM and MP table from pci.c to qemu.c, to prepare for DM PCI conversion. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/pci.c | 72 ---------------------------------------- arch/x86/cpu/qemu/qemu.c | 82 ++++++++++++++++++++++++++++++++++++++++++++++ include/configs/qemu-x86.h | 2 ++ 3 files changed, 84 insertions(+), 72 deletions(-) (limited to 'include') diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c index 8515d106e34..d50ab752d39 100644 --- a/arch/x86/cpu/qemu/pci.c +++ b/arch/x86/cpu/qemu/pci.c @@ -6,14 +6,9 @@ #include #include -#include -#include -#include DECLARE_GLOBAL_DATA_PTR; -static bool i440fx; - void board_pci_setup_hose(struct pci_controller *hose) { hose->first_busno = 0; @@ -50,72 +45,5 @@ void board_pci_setup_hose(struct pci_controller *hose) int board_pci_post_scan(struct pci_controller *hose) { - u16 device, xbcs; - int pam, i; - - /* - * i440FX and Q35 chipset have different PAM register offset, but with - * the same bitfield layout. Here we determine the offset based on its - * PCI device ID. - */ - device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); - i440fx = (device == PCI_DEVICE_ID_INTEL_82441); - pam = i440fx ? I440FX_PAM : Q35_PAM; - - /* - * Initialize Programmable Attribute Map (PAM) Registers - * - * Configure legacy segments C/D/E/F to system RAM - */ - for (i = 0; i < PAM_NUM; i++) - x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); - - if (i440fx) { - /* - * Enable legacy IDE I/O ports decode - * - * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. - * However Linux ata_piix driver does sanity check on these two - * registers to see whether legacy ports decode is turned on. - * This is to make Linux ata_piix driver happy. - */ - x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); - x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); - - /* Enable I/O APIC */ - xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); - xbcs |= APIC_EN; - x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); - } else { - /* Configure PCIe ECAM base address */ - x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, - CONFIG_PCIE_ECAM_BASE | BAR_EN); - } - return 0; } - -#ifdef CONFIG_GENERATE_MP_TABLE -int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) -{ - u8 irq; - - if (i440fx) { - /* - * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not - * connected to I/O APIC INTPIN#16-19. Instead they are routed - * to an irq number controled by the PIRQ routing register. - */ - irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), - PCI_INTERRUPT_LINE); - } else { - /* - * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. - * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. - */ - irq = pirq < 8 ? pirq + 16 : pirq + 12; - } - - return irq; -} -#endif diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 7c03e0295be..84fb082077d 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -6,8 +6,58 @@ #include #include +#include #include #include +#include +#include + +static bool i440fx; + +static void qemu_chipset_init(void) +{ + u16 device, xbcs; + int pam, i; + + /* + * i440FX and Q35 chipset have different PAM register offset, but with + * the same bitfield layout. Here we determine the offset based on its + * PCI device ID. + */ + device = x86_pci_read_config16(PCI_BDF(0, 0, 0), PCI_DEVICE_ID); + i440fx = (device == PCI_DEVICE_ID_INTEL_82441); + pam = i440fx ? I440FX_PAM : Q35_PAM; + + /* + * Initialize Programmable Attribute Map (PAM) Registers + * + * Configure legacy segments C/D/E/F to system RAM + */ + for (i = 0; i < PAM_NUM; i++) + x86_pci_write_config8(PCI_BDF(0, 0, 0), pam + i, PAM_RW); + + if (i440fx) { + /* + * Enable legacy IDE I/O ports decode + * + * Note: QEMU always decode legacy IDE I/O port on PIIX chipset. + * However Linux ata_piix driver does sanity check on these two + * registers to see whether legacy ports decode is turned on. + * This is to make Linux ata_piix driver happy. + */ + x86_pci_write_config16(PIIX_IDE, IDE0_TIM, IDE_DECODE_EN); + x86_pci_write_config16(PIIX_IDE, IDE1_TIM, IDE_DECODE_EN); + + /* Enable I/O APIC */ + xbcs = x86_pci_read_config16(PIIX_ISA, XBCS); + xbcs |= APIC_EN; + x86_pci_write_config16(PIIX_ISA, XBCS, xbcs); + } else { + /* Configure PCIe ECAM base address */ + x86_pci_write_config32(PCI_BDF(0, 0, 0), PCIEX_BAR, + CONFIG_PCIE_ECAM_BASE | BAR_EN); + } +} int arch_cpu_init(void) { @@ -39,7 +89,39 @@ void reset_cpu(ulong addr) x86_full_reset(); } +int arch_early_init_r(void) +{ + qemu_chipset_init(); + + return 0; +} + int arch_misc_init(void) { return pirq_init(); } + +#ifdef CONFIG_GENERATE_MP_TABLE +int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq) +{ + u8 irq; + + if (i440fx) { + /* + * Not like most x86 platforms, the PIRQ[A-D] on PIIX3 are not + * connected to I/O APIC INTPIN#16-19. Instead they are routed + * to an irq number controled by the PIRQ routing register. + */ + irq = x86_pci_read_config8(PCI_BDF(bus, dev, func), + PCI_INTERRUPT_LINE); + } else { + /* + * ICH9's PIRQ[A-H] are not consecutive numbers from 0 to 7. + * PIRQ[A-D] still maps to [0-3] but PIRQ[E-H] maps to [8-11]. + */ + irq = pirq < 8 ? pirq + 16 : pirq + 12; + } + + return irq; +} +#endif diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 1b544c119e7..ac090328363 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -15,6 +15,7 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_ARCH_MISC_INIT +#define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_PCI_MEM_BUS 0xc0000000 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS @@ -28,6 +29,7 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xe000 +#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ -- cgit v1.3.1 From aedefb6f79b4c1aaca25a01ac60f58af5e9e1436 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Nov 2015 02:04:50 -0800 Subject: x86: qemu: Convert to use driver model pci Move to driver model for pci on QEMU. Signed-off-by: Bin Meng Acked-by: Simon Glass --- arch/x86/cpu/qemu/Makefile | 1 - arch/x86/cpu/qemu/pci.c | 49 ---------------------------------------------- configs/qemu-x86_defconfig | 1 + include/configs/qemu-x86.h | 12 ------------ 4 files changed, 1 insertion(+), 62 deletions(-) delete mode 100644 arch/x86/cpu/qemu/pci.c (limited to 'include') diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index 1c00d1de077..3f3958aa8e1 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -9,4 +9,3 @@ obj-y += car.o dram.o endif obj-y += qemu.o obj-$(CONFIG_GENERATE_ACPI_TABLE) += acpi.o dsdt.o -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/qemu/pci.c b/arch/x86/cpu/qemu/pci.c deleted file mode 100644 index d50ab752d39..00000000000 --- a/arch/x86/cpu/qemu/pci.c +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (C) 2015, Bin Meng - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -void board_pci_setup_hose(struct pci_controller *hose) -{ - hose->first_busno = 0; - hose->last_busno = 0; - - /* PCI memory space */ - pci_set_region(hose->regions + 0, - CONFIG_PCI_MEM_BUS, - CONFIG_PCI_MEM_PHYS, - CONFIG_PCI_MEM_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 1, - CONFIG_PCI_IO_BUS, - CONFIG_PCI_IO_PHYS, - CONFIG_PCI_IO_SIZE, - PCI_REGION_IO); - - pci_set_region(hose->regions + 2, - CONFIG_PCI_PREF_BUS, - CONFIG_PCI_PREF_PHYS, - CONFIG_PCI_PREF_SIZE, - PCI_REGION_PREFETCH); - - pci_set_region(hose->regions + 3, - 0, - 0, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); - - hose->region_count = 4; -} - -int board_pci_post_scan(struct pci_controller *hose) -{ - return 0; -} diff --git a/configs/qemu-x86_defconfig b/configs/qemu-x86_defconfig index f4cc86250dc..62ac76e94bc 100644 --- a/configs/qemu-x86_defconfig +++ b/configs/qemu-x86_defconfig @@ -17,6 +17,7 @@ CONFIG_CPU=y CONFIG_SPI_FLASH=y CONFIG_NETDEVICES=y CONFIG_E1000=y +CONFIG_DM_PCI=y CONFIG_DM_RTC=y CONFIG_VIDEO_VESA=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index ac090328363..32b22711da9 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -17,18 +17,6 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_PCI_MEM_BUS 0xc0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x2000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xe000 - #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP -- cgit v1.3.1 From 74514c18b444129c844797ee16b08d065917c4cc Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Nov 2015 02:04:53 -0800 Subject: x86: crownbay: Remove unused PCI region address macros These are leftover when converted to use driver model pci. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/crownbay.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'include') diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 7f91ffffa56..184169dbdff 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,18 +20,6 @@ #define CONFIG_SMSC_LPC47M -#define CONFIG_PCI_MEM_BUS 0x40000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x80000000 - -#define CONFIG_PCI_PREF_BUS 0xc0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x20000000 - -#define CONFIG_PCI_IO_BUS 0x2000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xe000 - #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP -- cgit v1.3.1 From 6d41027fe2e734aa1e15fabc1523417b3b871691 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 6 Nov 2015 02:04:55 -0800 Subject: x86: Remove CONFIG_SYS_EARLY_PCI_INIT CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver model, PCI enumeration is automatically triggered. Signed-off-by: Bin Meng Acked-by: Simon Glass --- include/configs/bayleybay.h | 1 - include/configs/crownbay.h | 1 - include/configs/galileo.h | 1 - include/configs/minnowmax.h | 1 - include/configs/qemu-x86.h | 1 - include/configs/som-6896.h | 1 - include/configs/x86-chromebook.h | 1 - 7 files changed, 7 deletions(-) (limited to 'include') diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index 1ba2998d545..b102c689e27 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_MONITOR_LEN (1 << 20) #define CONFIG_ARCH_MISC_INIT -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 184169dbdff..54a2905c1d6 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -20,7 +20,6 @@ #define CONFIG_SMSC_LPC47M -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga,usbkbd\0" \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index ba6c8f172bd..eb16a5eacac 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -21,7 +21,6 @@ /* ns16550 UART is memory-mapped in Quark SoC */ #undef CONFIG_SYS_NS16550_PORT_MAPPED -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 53d86a2778d..a20552e74ee 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -19,7 +19,6 @@ #define CONFIG_SMSC_LPC47M -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_RTL8169 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index 32b22711da9..ecb385c0b33 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -17,7 +17,6 @@ #define CONFIG_ARCH_MISC_INIT #define CONFIG_ARCH_EARLY_INIT_R -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,vga\0" \ diff --git a/include/configs/som-6896.h b/include/configs/som-6896.h index 300e9dfc399..43a9623f04a 100644 --- a/include/configs/som-6896.h +++ b/include/configs/som-6896.h @@ -20,7 +20,6 @@ #define CONFIG_SCSI_DEV_LIST \ {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_AHCI} -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define VIDEO_IO_OFFSET 0 diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 2be885079e9..b0aa875f5e1 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -35,7 +35,6 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0xefff -#define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_PCI_PNP #define CONFIG_BIOSEMU -- cgit v1.3.1