From dfaf6a57974f5b4bcdc2a2a347b192573ffb5135 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Wed, 12 Aug 2020 11:55:46 +0200 Subject: CONFIG_NR_DRAM_BANKS: Remove unreferenced code as its always defined MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since commit 86cf1c82850f ("configs: Migrate CONFIG_NR_DRAM_BANKS") & commit 999a772d9f24 ("Kconfig: Migrate CONFIG_NR_DRAM_BANKS"), CONFIG_NR_DRAM_BANKS is always defined with a value (4 is default). It makes no sense to still carry code that is guarded with "#ifndef CONFIG_NR_DRAM_BANKS" (and similar). This patch removes all these unreferenced code paths. Signed-off-by: Stefan Roese Reviewed-by: Pali Rohár Reviewed-by: Andy Shevchenko Reviewed-by: Bin Meng --- include/asm-generic/u-boot.h | 2 -- include/handoff.h | 2 -- 2 files changed, 4 deletions(-) (limited to 'include') diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 62e61d41cc9..99d3fe33ad9 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -70,12 +70,10 @@ struct bd_info { #endif ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ -#ifdef CONFIG_NR_DRAM_BANKS struct { /* RAM configuration */ phys_addr_t start; phys_size_t size; } bi_dram[CONFIG_NR_DRAM_BANKS]; -#endif /* CONFIG_NR_DRAM_BANKS */ }; #endif /* __ASSEMBLY__ */ diff --git a/include/handoff.h b/include/handoff.h index 75d19b1f6e5..070a79c1b97 100644 --- a/include/handoff.h +++ b/include/handoff.h @@ -20,12 +20,10 @@ struct spl_handoff { struct arch_spl_handoff arch; u64 ram_size; -#ifdef CONFIG_NR_DRAM_BANKS struct { u64 start; u64 size; } ram_bank[CONFIG_NR_DRAM_BANKS]; -#endif }; void handoff_save_dram(struct spl_handoff *ho); -- cgit v1.3.1 From bac9da46c57511e574aa7e763e17fdd6f55db5bb Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Thu, 13 Aug 2020 07:05:46 +0200 Subject: asm-generic/u-boot.h: Remove bi_memstart & bi_memsize from bd_info bi_memstart & bi_memsize are now not referenced any more. This patch removes their definitions from the bd_info struct. Signed-off-by: Stefan Roese Reviewed-by: Simon Glass --- include/asm-generic/u-boot.h | 2 -- 1 file changed, 2 deletions(-) (limited to 'include') diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index 99d3fe33ad9..637de0c4558 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -27,8 +27,6 @@ #include struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ unsigned long bi_flashstart; /* start of FLASH memory */ unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ -- cgit v1.3.1 From 186879cdb22fd7569dae7f425711bed82a707bb4 Mon Sep 17 00:00:00 2001 From: Trac Hoang Date: Thu, 20 Aug 2020 20:41:04 +0530 Subject: cmd: broadcom: add bnxt boot command Chimp is a core in Broadcom netxtream controller (bnxt). Add command to load binary to chimp and boot bnxt. Signed-off-by: Trac Hoang Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- cmd/broadcom/Makefile | 4 ++++ cmd/broadcom/chimp_boot.c | 37 +++++++++++++++++++++++++++++++++++++ include/broadcom/chimp.h | 6 ++++++ 3 files changed, 47 insertions(+) create mode 100644 cmd/broadcom/Makefile create mode 100644 cmd/broadcom/chimp_boot.c (limited to 'include') diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile new file mode 100644 index 00000000000..22ccf2f3343 --- /dev/null +++ b/cmd/broadcom/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright 2020 Broadcom + +obj-y += chimp_boot.o diff --git a/cmd/broadcom/chimp_boot.c b/cmd/broadcom/chimp_boot.c new file mode 100644 index 00000000000..16f2b612c4d --- /dev/null +++ b/cmd/broadcom/chimp_boot.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Broadcom + */ + +#include +#include +#include + +static int do_chimp_fastboot_secure(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + u32 health = 0; + + if (chimp_health_status_optee(&health)) { + pr_err("Chimp health command fail\n"); + return CMD_RET_FAILURE; + } + + if (health == BCM_CHIMP_RUNNIG_GOOD) { + printf("skip fastboot...\n"); + return CMD_RET_SUCCESS; + } + + if (chimp_fastboot_optee()) { + pr_err("Failed to load secure ChiMP image\n"); + return CMD_RET_FAILURE; + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD + (chimp_ld_secure, 1, 0, do_chimp_fastboot_secure, + "Invoke chimp fw load via optee", + "chimp_ld_secure\n" +); diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h index 7f641529139..73bb1c21e9d 100644 --- a/include/broadcom/chimp.h +++ b/include/broadcom/chimp.h @@ -9,6 +9,12 @@ #include +/* + * Chimp binary has health status like initialization complete, + * crash or running fine + */ +#define BCM_CHIMP_RUNNIG_GOOD 0x8000 + /** * chimp_fastboot_optee() - api to load bnxt firmware * -- cgit v1.3.1 From a09ca687e7719ef0767f3febb8980725da800eb8 Mon Sep 17 00:00:00 2001 From: Bharat Kumar Reddy Gooty Date: Thu, 20 Aug 2020 20:41:06 +0530 Subject: cmd: broadcom: add command for chimp handshake Add command for chimp handshake. Handshake is used to know chimp is loaded and booted successfully. Signed-off-by: Bharat Kumar Reddy Gooty Signed-off-by: Rayagonda Kokatanur Reviewed-by: Simon Glass --- cmd/broadcom/Makefile | 1 + cmd/broadcom/chimp_handshake.c | 33 +++++++++++++++++++++++++++++++++ include/broadcom/chimp.h | 6 ++++++ 3 files changed, 40 insertions(+) create mode 100644 cmd/broadcom/chimp_handshake.c (limited to 'include') diff --git a/cmd/broadcom/Makefile b/cmd/broadcom/Makefile index 6cdece1a3a4..62268d98d0d 100644 --- a/cmd/broadcom/Makefile +++ b/cmd/broadcom/Makefile @@ -3,3 +3,4 @@ obj-y += chimp_boot.o obj-y += nitro_image_load.o +obj-y += chimp_handshake.o diff --git a/cmd/broadcom/chimp_handshake.c b/cmd/broadcom/chimp_handshake.c new file mode 100644 index 00000000000..a90a73a6d74 --- /dev/null +++ b/cmd/broadcom/chimp_handshake.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2020 Broadcom + */ + +#include +#include +#include + +/* This command should be called after loading the nitro binaries */ +static int do_chimp_hs(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + int ret = CMD_RET_USAGE; + u32 hstatus; + + /* Returns 1, if handshake call is success */ + if (chimp_handshake_status_optee(0, &hstatus)) + ret = CMD_RET_SUCCESS; + + if (hstatus == CHIMP_HANDSHAKE_SUCCESS) + printf("ChiMP Handshake successful\n"); + else + printf("ERROR: ChiMP Handshake status 0x%x\n", hstatus); + + return ret; +} + +U_BOOT_CMD + (chimp_hs, 1, 1, do_chimp_hs, + "Verify the Chimp handshake", + "chimp_hs\n" +); diff --git a/include/broadcom/chimp.h b/include/broadcom/chimp.h index 73bb1c21e9d..738f73eefd3 100644 --- a/include/broadcom/chimp.h +++ b/include/broadcom/chimp.h @@ -15,6 +15,12 @@ */ #define BCM_CHIMP_RUNNIG_GOOD 0x8000 +enum { + CHIMP_HANDSHAKE_SUCCESS = 0, + CHIMP_HANDSHAKE_WAIT_ERROR, + CHIMP_HANDSHAKE_WAIT_TIMEOUT, +}; + /** * chimp_fastboot_optee() - api to load bnxt firmware * -- cgit v1.3.1 From 15b87feb2b7923ef679e9da3f956e7a836fbaa40 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:03 +0800 Subject: cosmetic: aspeed: ast2500: Rename clock header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the ast2500-scu.h to aspeed-clock.h. Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang Reviewed-by: Cédric Le Goater --- arch/arm/dts/ast2500-u-boot.dtsi | 2 +- arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 2 +- drivers/clk/aspeed/clk_ast2500.c | 2 +- include/dt-bindings/clock/aspeed-clock.h | 30 ++++++++++++++++++++++++++++ include/dt-bindings/clock/ast2500-scu.h | 30 ---------------------------- 5 files changed, 33 insertions(+), 33 deletions(-) create mode 100644 include/dt-bindings/clock/aspeed-clock.h delete mode 100644 include/dt-bindings/clock/ast2500-scu.h (limited to 'include') diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 8ac42157455..3b119e4ace6 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,4 +1,4 @@ -#include +#include #include #include "ast2500.dtsi" diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c index a3adaa8a999..8536a70a19d 100644 --- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c +++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include /* These configuration parameters are taken from Aspeed SDK */ #define DDR4_MR46_MODE 0x08000000 diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index d1940f18849..392fe76b27a 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h new file mode 100644 index 00000000000..4803abe9f62 --- /dev/null +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2016 Google Inc. + */ + +/* Core Clocks */ +#define PLL_HPLL 1 +#define PLL_DPLL 2 +#define PLL_D2PLL 3 +#define PLL_MPLL 4 +#define ARMCLK 5 + + +/* Bus Clocks, derived from core clocks */ +#define BCLK_PCLK 101 +#define BCLK_LHCLK 102 +#define BCLK_MACCLK 103 +#define BCLK_SDCLK 104 +#define BCLK_ARMCLK 105 + +#define MCLK_DDR 201 + +/* Special clocks */ +#define PCLK_UART1 501 +#define PCLK_UART2 502 +#define PCLK_UART3 503 +#define PCLK_UART4 504 +#define PCLK_UART5 505 +#define PCLK_MAC1 506 +#define PCLK_MAC2 507 diff --git a/include/dt-bindings/clock/ast2500-scu.h b/include/dt-bindings/clock/ast2500-scu.h deleted file mode 100644 index 4803abe9f62..00000000000 --- a/include/dt-bindings/clock/ast2500-scu.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Google Inc. - */ - -/* Core Clocks */ -#define PLL_HPLL 1 -#define PLL_DPLL 2 -#define PLL_D2PLL 3 -#define PLL_MPLL 4 -#define ARMCLK 5 - - -/* Bus Clocks, derived from core clocks */ -#define BCLK_PCLK 101 -#define BCLK_LHCLK 102 -#define BCLK_MACCLK 103 -#define BCLK_SDCLK 104 -#define BCLK_ARMCLK 105 - -#define MCLK_DDR 201 - -/* Special clocks */ -#define PCLK_UART1 501 -#define PCLK_UART2 502 -#define PCLK_UART3 503 -#define PCLK_UART4 504 -#define PCLK_UART5 505 -#define PCLK_MAC1 506 -#define PCLK_MAC2 507 -- cgit v1.3.1 From c39c9a94cba01d9fbbe359a8922d2ae85061a4e1 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:04 +0800 Subject: clock:aspeed: Sync with Linux kernel clock header define v2: modify title description aspeed:clock -> clock:aspeed Use kernel include/dt-bindings/clock/aspeed-clock.h define for clock driver. Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang --- arch/arm/dts/ast2500-u-boot.dtsi | 20 +++++----- drivers/clk/aspeed/clk_ast2500.c | 38 +++++++++--------- include/dt-bindings/clock/aspeed-clock.h | 68 +++++++++++++++++++------------- 3 files changed, 68 insertions(+), 58 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 3b119e4ace6..29b08f16ac6 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -25,7 +25,7 @@ reg = <0x1e6e0000 0x174 0x1e6e0200 0x1d4 >; #reset-cells = <1>; - clocks = <&scu PLL_MPLL>; + clocks = <&scu ASPEED_CLK_MPLL>; resets = <&rst AST_RESET_SDRAM>; }; @@ -39,7 +39,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740100>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; @@ -47,7 +47,7 @@ compatible = "aspeed,ast2500-sdhci"; reg = <0x1e740200>; #reset-cells = <1>; - clocks = <&scu BCLK_SDCLK>; + clocks = <&scu ASPEED_CLK_SDIO>; resets = <&rst AST_RESET_SDIO>; }; }; @@ -56,23 +56,23 @@ }; &uart1 { - clocks = <&scu PCLK_UART1>; + clocks = <&scu ASPEED_CLK_GATE_UART1CLK>; }; &uart2 { - clocks = <&scu PCLK_UART2>; + clocks = <&scu ASPEED_CLK_GATE_UART2CLK>; }; &uart3 { - clocks = <&scu PCLK_UART3>; + clocks = <&scu ASPEED_CLK_GATE_UART3CLK>; }; &uart4 { - clocks = <&scu PCLK_UART4>; + clocks = <&scu ASPEED_CLK_GATE_UART4CLK>; }; &uart5 { - clocks = <&scu PCLK_UART5>; + clocks = <&scu ASPEED_CLK_GATE_UART5CLK>; }; &timer { @@ -80,9 +80,9 @@ }; &mac0 { - clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; &mac1 { - clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>; + clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>; }; diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c index 392fe76b27a..aab7d14deb7 100644 --- a/drivers/clk/aspeed/clk_ast2500.c +++ b/drivers/clk/aspeed/clk_ast2500.c @@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) ulong rate; switch (clk->id) { - case PLL_HPLL: - case ARMCLK: + case ASPEED_CLK_HPLL: /* * This ignores dynamic/static slowdown of ARMCLK and may * be inaccurate. @@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = ast2500_get_hpll_rate(clkin, readl(&priv->scu->h_pll_param)); break; - case MCLK_DDR: + case ASPEED_CLK_MPLL: rate = ast2500_get_mpll_rate(clkin, readl(&priv->scu->m_pll_param)); break; - case BCLK_PCLK: + case ASPEED_CLK_APB: { ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) & SCU_PCLK_DIV_MASK) @@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; - case BCLK_SDCLK: + case ASPEED_CLK_SDIO: { ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1) & SCU_SDCLK_DIV_MASK) @@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk) rate = rate / apb_div; } break; - case PCLK_UART1: + case ASPEED_CLK_GATE_UART1CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 1); break; - case PCLK_UART2: + case ASPEED_CLK_GATE_UART2CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 2); break; - case PCLK_UART3: + case ASPEED_CLK_GATE_UART3CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 3); break; - case PCLK_UART4: + case ASPEED_CLK_GATE_UART4CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 4); break; - case PCLK_UART5: + case ASPEED_CLK_GATE_UART5CLK: rate = ast2500_get_uart_clk_rate(priv->scu, 5); break; default: @@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate) ulong new_rate; switch (clk->id) { - case PLL_MPLL: - case MCLK_DDR: + case ASPEED_CLK_MPLL: new_rate = ast2500_configure_ddr(priv->scu, rate); break; - case PLL_D2PLL: + case ASPEED_CLK_D2PLL: new_rate = ast2500_configure_d2pll(priv->scu, rate); break; default: @@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk) struct ast2500_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case BCLK_SDCLK: + case ASPEED_CLK_SDIO: if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) { ast_scu_unlock(priv->scu); @@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk) * configured based on whether RGMII or RMII mode has been selected * through hardware strapping. */ - case PCLK_MAC1: + case ASPEED_CLK_GATE_MAC1CLK: ast2500_configure_mac(priv->scu, 1); break; - case PCLK_MAC2: + case ASPEED_CLK_GATE_MAC2CLK: ast2500_configure_mac(priv->scu, 2); break; - case PLL_D2PLL: + case ASPEED_CLK_D2PLL: ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE); break; default: @@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev) { struct ast2500_clk_priv *priv = dev_get_priv(dev); - priv->scu = dev_read_addr_ptr(dev); - if (!priv->scu) - return -EINVAL; + priv->scu = devfdt_get_addr_ptr(dev); + if (IS_ERR(priv->scu)) + return PTR_ERR(priv->scu); return 0; } diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index 4803abe9f62..e6599deeb9f 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,30 +1,42 @@ /* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Google Inc. - */ -/* Core Clocks */ -#define PLL_HPLL 1 -#define PLL_DPLL 2 -#define PLL_D2PLL 3 -#define PLL_MPLL 4 -#define ARMCLK 5 - - -/* Bus Clocks, derived from core clocks */ -#define BCLK_PCLK 101 -#define BCLK_LHCLK 102 -#define BCLK_MACCLK 103 -#define BCLK_SDCLK 104 -#define BCLK_ARMCLK 105 - -#define MCLK_DDR 201 - -/* Special clocks */ -#define PCLK_UART1 501 -#define PCLK_UART2 502 -#define PCLK_UART3 503 -#define PCLK_UART4 504 -#define PCLK_UART5 505 -#define PCLK_MAC1 506 -#define PCLK_MAC2 507 +#define ASPEED_CLK_GATE_ECLK 0 +#define ASPEED_CLK_GATE_GCLK 1 +#define ASPEED_CLK_GATE_MCLK 2 +#define ASPEED_CLK_GATE_VCLK 3 +#define ASPEED_CLK_GATE_BCLK 4 +#define ASPEED_CLK_GATE_DCLK 5 +#define ASPEED_CLK_GATE_REFCLK 6 +#define ASPEED_CLK_GATE_USBPORT2CLK 7 +#define ASPEED_CLK_GATE_LCLK 8 +#define ASPEED_CLK_GATE_USBUHCICLK 9 +#define ASPEED_CLK_GATE_D1CLK 10 +#define ASPEED_CLK_GATE_YCLK 11 +#define ASPEED_CLK_GATE_USBPORT1CLK 12 +#define ASPEED_CLK_GATE_UART1CLK 13 +#define ASPEED_CLK_GATE_UART2CLK 14 +#define ASPEED_CLK_GATE_UART5CLK 15 +#define ASPEED_CLK_GATE_ESPICLK 16 +#define ASPEED_CLK_GATE_MAC1CLK 17 +#define ASPEED_CLK_GATE_MAC2CLK 18 +#define ASPEED_CLK_GATE_RSACLK 19 +#define ASPEED_CLK_GATE_UART3CLK 20 +#define ASPEED_CLK_GATE_UART4CLK 21 +#define ASPEED_CLK_GATE_SDCLK 22 +#define ASPEED_CLK_GATE_LHCCLK 23 +#define ASPEED_CLK_HPLL 24 +#define ASPEED_CLK_AHB 25 +#define ASPEED_CLK_APB 26 +#define ASPEED_CLK_UART 27 +#define ASPEED_CLK_SDIO 28 +#define ASPEED_CLK_ECLK 29 +#define ASPEED_CLK_ECLK_MUX 30 +#define ASPEED_CLK_LHCLK 31 +#define ASPEED_CLK_MAC 32 +#define ASPEED_CLK_BCLK 33 +#define ASPEED_CLK_MPLL 34 +#define ASPEED_CLK_24M 35 +#define ASPEED_CLK_MAC1RCLK 36 +#define ASPEED_CLK_MAC2RCLK 37 +#define ASPEED_CLK_DPLL 38 +#define ASPEED_CLK_D2PLL 39 -- cgit v1.3.1 From 654ae299ec509084c22e646ae269e1baa2583793 Mon Sep 17 00:00:00 2001 From: Ryan Chen Date: Mon, 31 Aug 2020 14:03:05 +0800 Subject: cosmetic: aspeed: Modify for SPDX-License Modify SPDX-License for furture patch warning Signed-off-by: Ryan Chen Reviewed-by: Chia-Wei, Wang --- arch/arm/dts/ast2500-u-boot.dtsi | 1 + include/dt-bindings/clock/aspeed-clock.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi index 29b08f16ac6..51a5244766c 100644 --- a/arch/arm/dts/ast2500-u-boot.dtsi +++ b/arch/arm/dts/ast2500-u-boot.dtsi @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 #include #include diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h index e6599deeb9f..a1aa8c07ce8 100644 --- a/include/dt-bindings/clock/aspeed-clock.h +++ b/include/dt-bindings/clock/aspeed-clock.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ +// SPDX-License-Identifier: GPL-2.0 #define ASPEED_CLK_GATE_ECLK 0 #define ASPEED_CLK_GATE_GCLK 1 -- cgit v1.3.1 From a5fc58734fbc8b6f61b7716df3367d4607c168c4 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 1 Sep 2020 19:22:54 +0200 Subject: dt-bindings: clock: import Qualcomm IPQ4019 bindings Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by: Robert Marko Cc: Luka Perkov --- MAINTAINERS | 1 + include/dt-bindings/clock/qcom,ipq4019-gcc.h | 96 ++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,ipq4019-gcc.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 73e728871b5..80e6e54e256 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -237,6 +237,7 @@ M: Luka Kovacic M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ +F: include/dt-bindings/clock/qcom,ipq4019-gcc.h ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese diff --git a/include/dt-bindings/clock/qcom,ipq4019-gcc.h b/include/dt-bindings/clock/qcom,ipq4019-gcc.h new file mode 100644 index 00000000000..7130e222e41 --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq4019-gcc.h @@ -0,0 +1,96 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_CLK_IPQ4019_H__ +#define __QCOM_CLK_IPQ4019_H__ + +#define GCC_DUMMY_CLK 0 +#define AUDIO_CLK_SRC 1 +#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 +#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 +#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 +#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 +#define BLSP1_UART1_APPS_CLK_SRC 6 +#define BLSP1_UART2_APPS_CLK_SRC 7 +#define GCC_USB3_MOCK_UTMI_CLK_SRC 8 +#define GCC_APPS_CLK_SRC 9 +#define GCC_APPS_AHB_CLK_SRC 10 +#define GP1_CLK_SRC 11 +#define GP2_CLK_SRC 12 +#define GP3_CLK_SRC 13 +#define SDCC1_APPS_CLK_SRC 14 +#define FEPHY_125M_DLY_CLK_SRC 15 +#define WCSS2G_CLK_SRC 16 +#define WCSS5G_CLK_SRC 17 +#define GCC_APSS_AHB_CLK 18 +#define GCC_AUDIO_AHB_CLK 19 +#define GCC_AUDIO_PWM_CLK 20 +#define GCC_BLSP1_AHB_CLK 21 +#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 +#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 +#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 +#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 +#define GCC_BLSP1_UART1_APPS_CLK 26 +#define GCC_BLSP1_UART2_APPS_CLK 27 +#define GCC_DCD_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP2_CLK 30 +#define GCC_GP3_CLK 31 +#define GCC_BOOT_ROM_AHB_CLK 32 +#define GCC_CRYPTO_AHB_CLK 33 +#define GCC_CRYPTO_AXI_CLK 34 +#define GCC_CRYPTO_CLK 35 +#define GCC_ESS_CLK 36 +#define GCC_IMEM_AXI_CLK 37 +#define GCC_IMEM_CFG_AHB_CLK 38 +#define GCC_PCIE_AHB_CLK 39 +#define GCC_PCIE_AXI_M_CLK 40 +#define GCC_PCIE_AXI_S_CLK 41 +#define GCC_PCNOC_AHB_CLK 42 +#define GCC_PRNG_AHB_CLK 43 +#define GCC_QPIC_AHB_CLK 44 +#define GCC_QPIC_CLK 45 +#define GCC_SDCC1_AHB_CLK 46 +#define GCC_SDCC1_APPS_CLK 47 +#define GCC_SNOC_PCNOC_AHB_CLK 48 +#define GCC_SYS_NOC_125M_CLK 49 +#define GCC_SYS_NOC_AXI_CLK 50 +#define GCC_TCSR_AHB_CLK 51 +#define GCC_TLMM_AHB_CLK 52 +#define GCC_USB2_MASTER_CLK 53 +#define GCC_USB2_SLEEP_CLK 54 +#define GCC_USB2_MOCK_UTMI_CLK 55 +#define GCC_USB3_MASTER_CLK 56 +#define GCC_USB3_SLEEP_CLK 57 +#define GCC_USB3_MOCK_UTMI_CLK 58 +#define GCC_WCSS2G_CLK 59 +#define GCC_WCSS2G_REF_CLK 60 +#define GCC_WCSS2G_RTC_CLK 61 +#define GCC_WCSS5G_CLK 62 +#define GCC_WCSS5G_REF_CLK 63 +#define GCC_WCSS5G_RTC_CLK 64 +#define GCC_APSS_DDRPLL_VCO 65 +#define GCC_SDCC_PLLDIV_CLK 66 +#define GCC_FEPLL_VCO 67 +#define GCC_FEPLL125_CLK 68 +#define GCC_FEPLL125DLY_CLK 69 +#define GCC_FEPLL200_CLK 70 +#define GCC_FEPLL500_CLK 71 +#define GCC_FEPLL_WCSS2G_CLK 72 +#define GCC_FEPLL_WCSS5G_CLK 73 +#define GCC_APSS_CPU_PLLDIV_CLK 74 +#define GCC_PCNOC_AHB_CLK_SRC 75 + +#endif -- cgit v1.3.1 From f8d3d4d14aabee4e8959524629f72d62b6706ec0 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Thu, 13 Aug 2020 14:56:19 +0530 Subject: configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot Add memory mapped address location of U-Boot images in HyperFlash boot mode. Signed-off-by: Vignesh Raghavendra --- include/configs/j721e_evm.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index c8a76037ff0..a5708933789 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -23,8 +23,10 @@ #if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) +#define CONFIG_SYS_UBOOT_BASE 0x50280000 /* Image load address in RAM for DFU boot*/ #else +#define CONFIG_SYS_UBOOT_BASE 0x50080000 /* * Maximum size in memory allocated to the SPL BSS. Keep it as tight as * possible (to allow the build to go through), as this directly affects -- cgit v1.3.1 From 3c195299a8601aef15bd24572791f02340ed690a Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 17 Aug 2020 16:57:35 -0500 Subject: configs: j721e_evm: Add Main R5FSS1 Core1 to default rproc boot list The default rproc list currently used by A72 U-Boot to boot various remote processors include the Main R5FSS0 (Split-mode) Core1, Main R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster is configured for Split mode by default in the dts now, so add the Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This core is now booted after the Main R5FSS1 Core0 and before the DSPs. The order of the rprocs to boot can always be changed at runtime if desired by overwriting the 'rproc_fw_binaries' environment variable at U-boot prompt. Note that the R5FSS Core1 cannot be booted before its associated Core0. Signed-off-by: Suman Anna --- include/configs/j721e_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index a5708933789..2eaa0585014 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -117,6 +117,7 @@ #define DEFAULT_RPROCS "" \ "3 /lib/firmware/j7-main-r5f0_1-fw " \ "4 /lib/firmware/j7-main-r5f1_0-fw " \ + "5 /lib/firmware/j7-main-r5f1_1-fw " \ "6 /lib/firmware/j7-c66_0-fw " \ "7 /lib/firmware/j7-c66_1-fw " \ "8 /lib/firmware/j7-c71_0-fw " -- cgit v1.3.1 From a9e5caf59661180424fbc4ad4736c77549bd5354 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 17 Aug 2020 16:57:36 -0500 Subject: env: ti: j721e-evm: Limit scope of rproc env variables used by R5 SPL The commit 316c927135d6 ("include: configs: j721e_evm: Add env variables for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' to the generic environment, but these are only needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main R5FSS0 Core0 on J721E SoCs. These are not really needed for A72 U-Boot, so limit the scope of these variables only to R5 SPL. While at this, also fix the loadaddr variable values to include the hex prefix like with other such env variables. Cc: Keerthy Signed-off-by: Suman Anna --- include/configs/j721e_evm.h | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 2eaa0585014..15c34e19bf8 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -83,16 +83,23 @@ "uuid_disk=${uuid_gpt_disk};" \ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" +#ifdef CONFIG_SYS_K3_SPL_ATF +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "addr_mainr5f0_0load=0x88000000\0" \ + "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ + "addr_mcur5f0_0load=0x89000000\0" \ + "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" +#else +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC "" +#endif /* CONFIG_SYS_K3_SPL_ATF */ + /* U-Boot MMC-specific configuration */ #define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ "boot=mmc\0" \ "mmcdev=1\0" \ "bootpart=1:2\0" \ "bootdir=/boot\0" \ - "addr_mainr5f0_0load=88000000\0" \ - "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ - "addr_mcur5f0_0load=89000000\0" \ - "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" \ + EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ "rd_spec=-\0" \ "init_mmc=run args_all args_mmc\0" \ "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ -- cgit v1.3.1 From c091bb049973ae73cb8d63b1bb4cf04047cd27da Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Mon, 17 Aug 2020 18:15:12 -0500 Subject: env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200 The J7200 SoCs have different number of remote processors, but reuse the same environment settings as the J721E SoCs. The current env variable rproc_fw_binaries is geared towards J721E SoCs and is incorrect for J7200 SoCs. Please see the logic originally added in commit 0b4ab9c9a754 ("env: ti: j721e-evm: Add support to boot rprocs including R5Fs and DSPs"). Fix this by defining the DEFAULT_RPROCS macro appropriately using the corresponding TARGET_EVM Kconfig symbol. This macro is used by the 'rproc_fw_binaries' env variable in the common remoteproc env header file k3_rproc.h. The list of R5F cores to be started before loading and booting the Linux kernel are as follows, and mainly comprises of the Main R5FSS0 cores in this order: Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw The MCU R5FSS0 is in LockStep mode and is expected to be booted by R5 SPL, so it is not included in the list. The order of rprocs to boot cannot be really modified as only the Main R5FSS0 cores are involved and Core0 has to be booted first always before the corresponding Core1. Signed-off-by: Suman Anna --- include/configs/j721e_evm.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 15c34e19bf8..9988c43641a 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -2,7 +2,7 @@ /* * Configuration header file for K3 J721E EVM * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ + * Copyright (C) 2018-2020 Texas Instruments Incorporated - https://www.ti.com/ * Lokesh Vutla */ @@ -118,9 +118,14 @@ "${bootdir}/${name_fit}\0" \ "partitions=" PARTS_DEFAULT +/* Set the default list of remote processors to boot */ +#if defined(CONFIG_TARGET_J721E_A72_EVM) || defined(CONFIG_TARGET_J7200_A72_EVM) #ifdef DEFAULT_RPROCS #undef DEFAULT_RPROCS #endif +#endif + +#ifdef CONFIG_TARGET_J721E_A72_EVM #define DEFAULT_RPROCS "" \ "3 /lib/firmware/j7-main-r5f0_1-fw " \ "4 /lib/firmware/j7-main-r5f1_0-fw " \ @@ -128,6 +133,13 @@ "6 /lib/firmware/j7-c66_0-fw " \ "7 /lib/firmware/j7-c66_1-fw " \ "8 /lib/firmware/j7-c71_0-fw " +#endif /* CONFIG_TARGET_J721E_A72_EVM */ + +#ifdef CONFIG_TARGET_J7200_A72_EVM +#define DEFAULT_RPROCS "" \ + "2 /lib/firmware/j7200-main-r5f0_0-fw " \ + "3 /lib/firmware/j7200-main-r5f0_1-fw " +#endif /* CONFIG_TARGET_J7200_A72_EVM */ /* set default dfu_bufsiz to 128KB (sector size of OSPI) */ #define EXTRA_ENV_DFUARGS \ -- cgit v1.3.1 From 615d10f736e850c073a17b2f64fd08c7f5b32fe2 Mon Sep 17 00:00:00 2001 From: Suman Anna Date: Tue, 18 Aug 2020 14:09:43 -0500 Subject: env: ti: j721e-evm: Update R5 SPL rproc env variables for J7200 The R5 SPL on J7200 SoCs will be limited to booting just the MCU R5FSS0 R5F core in LockStep-mode at present, so add the two required environment variables 'addr_mcur5f0_0load' and 'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot logic. The firmware name used is also different from that on J721E SoCs. Signed-off-by: Suman Anna --- include/configs/j721e_evm.h | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'include') diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h index 9988c43641a..1b47e18b2f9 100644 --- a/include/configs/j721e_evm.h +++ b/include/configs/j721e_evm.h @@ -84,11 +84,17 @@ "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" #ifdef CONFIG_SYS_K3_SPL_ATF +#if defined(CONFIG_TARGET_J721E_R5_EVM) #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ "addr_mainr5f0_0load=0x88000000\0" \ "name_mainr5f0_0fw=/lib/firmware/j7-main-r5f0_0-fw\0" \ "addr_mcur5f0_0load=0x89000000\0" \ "name_mcur5f0_0fw=/lib/firmware/j7-mcu-r5f0_0-fw\0" +#elif defined(CONFIG_TARGET_J7200_R5_EVM) +#define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC \ + "addr_mcur5f0_0load=0x89000000\0" \ + "name_mcur5f0_0fw=/lib/firmware/j7200-mcu-r5f0_0-fw\0" +#endif /* CONFIG_TARGET_J721E_R5_EVM */ #else #define EXTRA_ENV_R5_SPL_RPROC_FW_ARGS_MMC "" #endif /* CONFIG_SYS_K3_SPL_ATF */ -- cgit v1.3.1 From 42b7aebe4ab47d7d981572d15d9bba999007b2ac Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Mon, 24 Aug 2020 21:00:32 +0300 Subject: ti: Use devtype=mmc instead of setenv devtype mmc If devtype variable is setted via setenv, then the following devtype=X style is ignored. Currently, many u-boot commands use devtype variable in the latter manner: mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from another devtype. Signed-off-by: Matwey V. Kornilov --- include/environment/ti/mmc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/environment/ti/mmc.h b/include/environment/ti/mmc.h index 1c8e49a8b3d..b86c8dc7a4f 100644 --- a/include/environment/ti/mmc.h +++ b/include/environment/ti/mmc.h @@ -57,7 +57,7 @@ "fi;\0" \ "mmcboot=mmc dev ${mmcdev}; " \ "devnum=${mmcdev}; " \ - "setenv devtype mmc; " \ + "devtype=mmc; " \ "if mmc rescan; then " \ "echo SD/MMC found on device ${mmcdev};" \ "if run loadimage; then " \ -- cgit v1.3.1 From 8c444c184c36dfa314a2a500349785f58c8a8d24 Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Mon, 24 Aug 2020 21:00:33 +0300 Subject: am335x_evm: Allow booting from usb-storage device Signed-off-by: Matwey V. Kornilov --- include/configs/am335x_evm.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 9c4ef369c5c..103c0461374 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -66,6 +66,12 @@ #define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ #devtypel #instance " " +#if CONFIG_IS_ENABLED(CMD_USB) +# define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +# define BOOT_TARGET_USB(func) +#endif + #if CONFIG_IS_ENABLED(CMD_PXE) # define BOOT_TARGET_PXE(func) func(PXE, pxe, na) #else @@ -84,6 +90,7 @@ func(MMC, mmc, 1) \ func(LEGACY_MMC, legacy_mmc, 1) \ func(NAND, nand, 0) \ + BOOT_TARGET_USB(func) \ BOOT_TARGET_PXE(func) \ BOOT_TARGET_DHCP(func) -- cgit v1.3.1 From 41cf3cb39ddbb8a0b892781388e1054653d33ed1 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Mon, 14 Sep 2020 12:11:15 +0530 Subject: arm: mach-omap2: am33xx: Add device structure for spi Add platform data and a device structure for the spi device present on am335x-icev2. This requires moving all omap3_spi platform data structures and symbols to an omap3_spi.h so that the board file can access them. Signed-off-by: Faiz Abbas --- arch/arm/mach-omap2/am33xx/board.c | 18 +++++++++ drivers/spi/omap3_spi.c | 70 +--------------------------------- include/configs/am335x_evm.h | 2 - include/omap3_spi.h | 78 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 71 deletions(-) create mode 100644 include/omap3_spi.h (limited to 'include') diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index a7b56b6bb3d..2888390d240 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -49,6 +50,12 @@ #define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC #define AM43XX_RDWRLVLFULL_START 0x80000000 +/* SPI flash. */ +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +#define AM33XX_SPI0_BASE 0x48030000 +#define AM33XX_SPI0_OFFSET (AM33XX_SPI0_BASE + OMAP4_MCSPI_REG_OFFSET) +#endif + DECLARE_GLOBAL_DATA_PTR; int dram_init(void) @@ -142,6 +149,17 @@ U_BOOT_DEVICES(am33xx_gpios) = { #endif }; #endif +#if CONFIG_IS_ENABLED(DM_SPI) && !CONFIG_IS_ENABLED(OF_CONTROL) +static const struct omap3_spi_plat omap3_spi_pdata = { + .regs = (struct mcspi *)AM33XX_SPI0_OFFSET, + .pin_dir = MCSPI_PINDIR_D0_IN_D1_OUT, +}; + +U_BOOT_DEVICE(am33xx_spi) = { + .name = "omap3_spi", + .platdata = &omap3_spi_pdata, +}; +#endif #endif #if !CONFIG_IS_ENABLED(DM_GPIO) diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index fbf9575851a..fb1cf360fcd 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -22,82 +22,14 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; -#define OMAP4_MCSPI_REG_OFFSET 0x100 - struct omap2_mcspi_platform_config { unsigned int regs_offset; }; -/* per-register bitmasks */ -#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) -#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) -#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) -#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) - -#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) - -#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) -#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) -#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) - -#define OMAP3_MCSPI_CHCONF_PHA BIT(0) -#define OMAP3_MCSPI_CHCONF_POL BIT(1) -#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) -#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) -#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) -#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) -#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) -#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) -#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) -#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) -#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) -#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) -#define OMAP3_MCSPI_CHCONF_IS BIT(18) -#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) -#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) - -#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) -#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) -#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) - -#define OMAP3_MCSPI_CHCTRL_EN BIT(0) -#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) - -#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) -#define MCSPI_PINDIR_D0_IN_D1_OUT 0 -#define MCSPI_PINDIR_D0_OUT_D1_IN 1 - -#define OMAP3_MCSPI_MAX_FREQ 48000000 -#define SPI_WAIT_TIMEOUT 10 - -/* OMAP3 McSPI registers */ -struct mcspi_channel { - unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ - unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ - unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ - unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ - unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ -}; - -struct mcspi { - unsigned char res1[0x10]; - unsigned int sysconfig; /* 0x10 */ - unsigned int sysstatus; /* 0x14 */ - unsigned int irqstatus; /* 0x18 */ - unsigned int irqenable; /* 0x1C */ - unsigned int wakeupenable; /* 0x20 */ - unsigned int syst; /* 0x24 */ - unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; - /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ - /* channel1: 0x40 - 0x50, bus 0 & 1 */ - /* channel2: 0x54 - 0x64, bus 0 & 1 */ - /* channel3: 0x68 - 0x78, bus 0 */ -}; - struct omap3_spi_priv { struct mcspi *regs; unsigned int cs; diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 103c0461374..5af90d932d5 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -287,8 +287,6 @@ #define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #endif -/* SPI flash. */ - /* Network. */ /* Enable Atheros phy driver */ diff --git a/include/omap3_spi.h b/include/omap3_spi.h new file mode 100644 index 00000000000..cae37705830 --- /dev/null +++ b/include/omap3_spi.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef __OMAP3_SPI_H_ +#define __OMAP3_SPI_H_ + +/* per-register bitmasks */ +#define OMAP3_MCSPI_SYSCONFIG_SMARTIDLE (2 << 3) +#define OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP BIT(2) +#define OMAP3_MCSPI_SYSCONFIG_AUTOIDLE BIT(0) +#define OMAP3_MCSPI_SYSCONFIG_SOFTRESET BIT(1) + +#define OMAP3_MCSPI_SYSSTATUS_RESETDONE BIT(0) + +#define OMAP3_MCSPI_MODULCTRL_SINGLE BIT(0) +#define OMAP3_MCSPI_MODULCTRL_MS BIT(2) +#define OMAP3_MCSPI_MODULCTRL_STEST BIT(3) + +#define OMAP3_MCSPI_CHCONF_PHA BIT(0) +#define OMAP3_MCSPI_CHCONF_POL BIT(1) +#define OMAP3_MCSPI_CHCONF_CLKD_MASK GENMASK(5, 2) +#define OMAP3_MCSPI_CHCONF_EPOL BIT(6) +#define OMAP3_MCSPI_CHCONF_WL_MASK GENMASK(11, 7) +#define OMAP3_MCSPI_CHCONF_TRM_RX_ONLY BIT(12) +#define OMAP3_MCSPI_CHCONF_TRM_TX_ONLY BIT(13) +#define OMAP3_MCSPI_CHCONF_TRM_MASK GENMASK(13, 12) +#define OMAP3_MCSPI_CHCONF_DMAW BIT(14) +#define OMAP3_MCSPI_CHCONF_DMAR BIT(15) +#define OMAP3_MCSPI_CHCONF_DPE0 BIT(16) +#define OMAP3_MCSPI_CHCONF_DPE1 BIT(17) +#define OMAP3_MCSPI_CHCONF_IS BIT(18) +#define OMAP3_MCSPI_CHCONF_TURBO BIT(19) +#define OMAP3_MCSPI_CHCONF_FORCE BIT(20) + +#define OMAP3_MCSPI_CHSTAT_RXS BIT(0) +#define OMAP3_MCSPI_CHSTAT_TXS BIT(1) +#define OMAP3_MCSPI_CHSTAT_EOT BIT(2) + +#define OMAP3_MCSPI_CHCTRL_EN BIT(0) +#define OMAP3_MCSPI_CHCTRL_DIS (0 << 0) + +#define OMAP3_MCSPI_WAKEUPENABLE_WKEN BIT(0) +#define MCSPI_PINDIR_D0_IN_D1_OUT 0 +#define MCSPI_PINDIR_D0_OUT_D1_IN 1 + +#define OMAP3_MCSPI_MAX_FREQ 48000000 +#define SPI_WAIT_TIMEOUT 10 + +#define OMAP4_MCSPI_REG_OFFSET 0x100 + +/* OMAP3 McSPI registers */ +struct mcspi_channel { + unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ + unsigned int chstat; /* 0x30, 0x44, 0x58, 0x6C */ + unsigned int chctrl; /* 0x34, 0x48, 0x5C, 0x70 */ + unsigned int tx; /* 0x38, 0x4C, 0x60, 0x74 */ + unsigned int rx; /* 0x3C, 0x50, 0x64, 0x78 */ +}; + +struct mcspi { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned int irqstatus; /* 0x18 */ + unsigned int irqenable; /* 0x1C */ + unsigned int wakeupenable; /* 0x20 */ + unsigned int syst; /* 0x24 */ + unsigned int modulctrl; /* 0x28 */ + struct mcspi_channel channel[4]; + /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ + /* channel1: 0x40 - 0x50, bus 0 & 1 */ + /* channel2: 0x54 - 0x64, bus 0 & 1 */ + /* channel3: 0x68 - 0x78, bus 0 */ +}; + +struct omap3_spi_plat { + struct mcspi *regs; + unsigned int pin_dir:1; +}; +#endif -- cgit v1.3.1 From 5990b059516c233bf845ad510decd6a44ba9864b Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 3 Feb 2020 10:23:53 +0100 Subject: powerpc, qe: add DTS support for parallel I/O ports add DM support for parallel I/O ports on QUICC Engine Block Signed-off-by: Heiko Schocher Patch-cc: Mario Six Patch-cc: Qiang Zhao Patch-cc: Holger Brunck Series-changes: 2 - remove RFC - fixed Codingstyle errors, therefore new patch powerpc, mpc83xx: fix codingstyle issues for qe_io.c - moved DM part to drivers/pinctrl Commit-notes: Open questions / discussion: - I let the old none DM based implementation in code so boards should work with old implementation. This should be removed if all boards are converted to DM/DTS. - Unfortunately linux DTS does not use "pinctrl-" properties, instead "pio-handle" properties. Even worser old U-Boot code initializes all pins defined in "const qe_iop_conf_t qe_iop_conf_tab[]" table in board code. As linux does the same I decided to also scan through all subnodes containing "pio-map" property and initialize them too. The proper solution would be to check for "pio-handle" when a device is probed. END --- arch/powerpc/cpu/mpc83xx/Makefile | 2 + arch/powerpc/cpu/mpc83xx/cpu_init.c | 8 ++ arch/powerpc/cpu/mpc83xx/qe_io.c | 83 ++++++++---- drivers/pinctrl/Kconfig | 7 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-qe-io.c | 255 ++++++++++++++++++++++++++++++++++++ include/fsl_qe.h | 3 + 7 files changed, 334 insertions(+), 25 deletions(-) create mode 100644 drivers/pinctrl/pinctrl-qe-io.c (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/Makefile b/arch/powerpc/cpu/mpc83xx/Makefile index 304029977e5..aeb42b109d0 100644 --- a/arch/powerpc/cpu/mpc83xx/Makefile +++ b/arch/powerpc/cpu/mpc83xx/Makefile @@ -27,7 +27,9 @@ obj-y += cpu_init.o obj-y += speed.o obj-y += interrupts.o obj-y += ecc.o +ifndef CONFIG_PINCTRL obj-$(CONFIG_QE) += qe_io.o +endif obj-$(CONFIG_FSL_SERDES) += serdes.o ifndef CONFIG_ARCH_MPC8308 obj-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index b21b0b03249..840f907acb8 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -14,6 +14,9 @@ #include #endif #include +#ifdef CONFIG_QE +#include +#endif #include "lblaw/lblaw.h" #include "elbc/elbc.h" @@ -28,6 +31,7 @@ extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); +#if !defined(CONFIG_PINCTRL) static void config_qe_ioports(void) { u8 port, pin; @@ -44,6 +48,7 @@ static void config_qe_ioports(void) } } #endif +#endif /* * Breathe some life into the CPU... @@ -190,10 +195,13 @@ void cpu_init_f (volatile immap_t * im) __raw_writel(CONFIG_SYS_OBIR, &im->sysconf.obir); #endif +#if !defined(CONFIG_PINCTRL) #ifdef CONFIG_QE /* Config QE ioports */ config_qe_ioports(); #endif +#endif + /* Set up preliminary BR/OR regs */ init_early_memctl_regs(); diff --git a/arch/powerpc/cpu/mpc83xx/qe_io.c b/arch/powerpc/cpu/mpc83xx/qe_io.c index 1079ae128ae..52360703a7d 100644 --- a/arch/powerpc/cpu/mpc83xx/qe_io.c +++ b/arch/powerpc/cpu/mpc83xx/qe_io.c @@ -12,24 +12,35 @@ #include #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) + +/** qe_cfg_iopin configure one io pin setting + * + * @par_io: pointer to parallel I/O base + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir, + int open_drain, int assign) { - u32 2bit_mask; - u32 2bit_dir; - u32 2bit_assign; - u32 1bit_mask; - u32 tmp_val; - immap_t *im; - qepio83xx_t *par_io; - int offset; + u32 dbit_mask; + u32 dbit_dir; + u32 dbit_asgn; + u32 bit_mask; + u32 tmp_val; + int offset; - im = (immap_t *)CONFIG_SYS_IMMR; - par_io = (qepio83xx_t *)&im->qepio; offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2); /* Calculate pin location and 2bit mask and dir */ - 2bit_mask = (u32)(0x3 << offset); - 2bit_dir = (u32)(dir << offset); + dbit_mask = (u32)(0x3 << offset); + dbit_dir = (u32)(dir << offset); /* Setup the direction */ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? @@ -37,35 +48,57 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) in_be32(&par_io->ioport[port].dir1); if (pin > (NUM_OF_PINS / 2) - 1) { - out_be32(&par_io->ioport[port].dir2, ~2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir2, 2bit_dir | tmp_val); + out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val); } else { - out_be32(&par_io->ioport[port].dir1, ~2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].dir1, 2bit_dir | tmp_val); + out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val); } /* Calculate pin location for 1bit mask */ - 1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1))); + bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1))); /* Setup the open drain */ tmp_val = in_be32(&par_io->ioport[port].podr); if (open_drain) - out_be32(&par_io->ioport[port].podr, 1bit_mask | tmp_val); + out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val); else - out_be32(&par_io->ioport[port].podr, ~1bit_mask & tmp_val); + out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val); /* Setup the assignment */ tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? in_be32(&par_io->ioport[port].ppar2) : in_be32(&par_io->ioport[port].ppar1); - 2bit_assign = (u32)(assign << offset); + dbit_asgn = (u32)(assign << offset); /* Clear and set 2 bits mask */ if (pin > (NUM_OF_PINS / 2) - 1) { - out_be32(&par_io->ioport[port].ppar2, ~2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar2, 2bit_assign | tmp_val); + out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val); } else { - out_be32(&par_io->ioport[port].ppar1, ~2bit_mask & tmp_val); - out_be32(&par_io->ioport[port].ppar1, 2bit_assign | tmp_val); + out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val); } } + +#if !defined(CONFIG_PINCTRL) +/** qe_config_iopin configure one io pin setting + * + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); +} +#endif diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index cdbccfd285a..048583f39b0 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -205,6 +205,13 @@ config PINCTRL_QCA953X the GPIO definitions and pin control functions for each available multiplex function. +config PINCTRL_QE + bool "QE based pinctrl driver, like on mpc83xx" + depends on DM + help + This option is to enable the QE pinctrl driver for QE based io + controller. + config PINCTRL_ROCKCHIP_RV1108 bool "Rockchip rv1108 pin control driver" depends on DM diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 92cff1b100d..507dd3a926c 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_MTK) += mediatek/ obj-$(CONFIG_PINCTRL_MSCC) += mscc/ obj-$(CONFIG_ARCH_MVEBU) += mvebu/ obj-$(CONFIG_ARCH_NEXELL) += nexell/ +obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o diff --git a/drivers/pinctrl/pinctrl-qe-io.c b/drivers/pinctrl/pinctrl-qe-io.c new file mode 100644 index 00000000000..85521eabd40 --- /dev/null +++ b/drivers/pinctrl/pinctrl-qe-io.c @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2006 Freescale Semiconductor, Inc. + * + * Dave Liu + * based on source code of Shlomi Gridish + */ + +#include +#include +#include +#include + +#if defined(CONFIG_PINCTRL) +#include +#include +#include +#include + +/** + * struct qe_io_platdata + * + * @base: Base register address + * @num_par_io_ports number of io ports + */ +struct qe_io_platdata { + qepio83xx_t *base; + u32 num_io_ports; +}; +#endif + +#define NUM_OF_PINS 32 + +/** qe_cfg_iopin configure one io pin setting + * + * @par_io: pointer to parallel I/O base + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +static void qe_cfg_iopin(qepio83xx_t *par_io, u8 port, u8 pin, int dir, + int open_drain, int assign) +{ + u32 dbit_mask; + u32 dbit_dir; + u32 dbit_asgn; + u32 bit_mask; + u32 tmp_val; + int offset; + + offset = (NUM_OF_PINS - (pin % (NUM_OF_PINS / 2) + 1) * 2); + + /* Calculate pin location and 2bit mask and dir */ + dbit_mask = (u32)(0x3 << offset); + dbit_dir = (u32)(dir << offset); + + /* Setup the direction */ + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? + in_be32(&par_io->ioport[port].dir2) : + in_be32(&par_io->ioport[port].dir1); + + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].dir2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir2, dbit_dir | tmp_val); + } else { + out_be32(&par_io->ioport[port].dir1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].dir1, dbit_dir | tmp_val); + } + + /* Calculate pin location for 1bit mask */ + bit_mask = (u32)(1 << (NUM_OF_PINS - (pin + 1))); + + /* Setup the open drain */ + tmp_val = in_be32(&par_io->ioport[port].podr); + if (open_drain) + out_be32(&par_io->ioport[port].podr, bit_mask | tmp_val); + else + out_be32(&par_io->ioport[port].podr, ~bit_mask & tmp_val); + + /* Setup the assignment */ + tmp_val = (pin > (NUM_OF_PINS / 2) - 1) ? + in_be32(&par_io->ioport[port].ppar2) : + in_be32(&par_io->ioport[port].ppar1); + dbit_asgn = (u32)(assign << offset); + + /* Clear and set 2 bits mask */ + if (pin > (NUM_OF_PINS / 2) - 1) { + out_be32(&par_io->ioport[port].ppar2, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar2, dbit_asgn | tmp_val); + } else { + out_be32(&par_io->ioport[port].ppar1, ~dbit_mask & tmp_val); + out_be32(&par_io->ioport[port].ppar1, dbit_asgn | tmp_val); + } +} + +#if !defined(CONFIG_PINCTRL) +/** qe_config_iopin configure one io pin setting + * + * @port: io pin port + * @pin: io pin number which get configured + * @dir: direction of io pin 2 bits valid + * 00 = pin disabled + * 01 = output + * 10 = input + * 11 = pin is I/O + * @open_drain: is pin open drain + * @assign: pin assignment registers select the function of the pin + */ +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + qepio83xx_t *par_io = (qepio83xx_t *)&im->qepio; + + qe_cfg_iopin(par_io, port, pin, dir, open_drain, assign); +} +#else +static int qe_io_ofdata_to_platdata(struct udevice *dev) +{ + struct qe_io_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->base = (qepio83xx_t *)addr; + if (dev_read_u32(dev, "num-ports", &plat->num_io_ports)) + return -EINVAL; + + return 0; +} + +/** + * par_io_of_config_node config + * @dev: pointer to pinctrl device + * @pio: ofnode of pinconfig property + */ +static int par_io_of_config_node(struct udevice *dev, ofnode pio) +{ + struct qe_io_platdata *plat = dev->platdata; + qepio83xx_t *par_io = plat->base; + const unsigned int *pio_map; + int pio_map_len; + + pio_map = ofnode_get_property(pio, "pio-map", &pio_map_len); + if (!pio_map) + return -ENOENT; + + pio_map_len /= sizeof(unsigned int); + if ((pio_map_len % 6) != 0) { + dev_err(dev, "%s: pio-map format wrong!\n", __func__); + return -EINVAL; + } + + while (pio_map_len > 0) { + /* + * column pio_map[5] from linux (has_irq) not + * supported in u-boot yet. + */ + qe_cfg_iopin(par_io, (u8)pio_map[0], (u8)pio_map[1], + (int)pio_map[2], (int)pio_map[3], + (int)pio_map[4]); + pio_map += 6; + pio_map_len -= 6; + } + return 0; +} + +int par_io_of_config(struct udevice *dev) +{ + u32 phandle; + ofnode pio; + int err; + + err = ofnode_read_u32(dev_ofnode(dev), "pio-handle", &phandle); + if (err) { + dev_err(dev, "%s: pio-handle not available\n", __func__); + return err; + } + + pio = ofnode_get_by_phandle(phandle); + if (!ofnode_valid(pio)) { + dev_err(dev, "%s: unable to find node\n", __func__); + return -EINVAL; + } + + /* To Do: find pinctrl device and pass it */ + return par_io_of_config_node(NULL, pio); +} + +/* + * This is not nice! + * pinsettings should work with "pinctrl-" properties. + * Unfortunately on mpc83xx powerpc linux device trees + * devices handle this with "pio-handle" properties ... + * + * Even worser, old board code inits all par_io + * pins in one step, if U-Boot uses the device + * or not. So init all par_io definitions here too + * as linux does this also. + */ +static void config_qe_ioports(struct udevice *dev) +{ + ofnode ofn; + + for (ofn = dev_read_first_subnode(dev); ofnode_valid(ofn); + ofn = dev_read_next_subnode(ofn)) { + /* + * ignore errors here, as may the subnode + * has no pio-handle + */ + par_io_of_config_node(dev, ofn); + } +} + +static int par_io_pinctrl_probe(struct udevice *dev) +{ + config_qe_ioports(dev); + + return 0; +} + +static int par_io_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + return 0; +} + +const struct pinctrl_ops par_io_pinctrl_ops = { + .set_state = par_io_pinctrl_set_state, +}; + +static const struct udevice_id par_io_pinctrl_match[] = { + { .compatible = "fsl,mpc8360-par_io"}, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(par_io_pinctrl) = { + .name = "par-io-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(par_io_pinctrl_match), + .probe = par_io_pinctrl_probe, + .ofdata_to_platdata = qe_io_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct qe_io_platdata), + .ops = &par_io_pinctrl_ops, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .flags = DM_FLAG_PRE_RELOC, +#endif +}; +#endif diff --git a/include/fsl_qe.h b/include/fsl_qe.h index 6e44cbdb562..1c6941347f7 100644 --- a/include/fsl_qe.h +++ b/include/fsl_qe.h @@ -296,4 +296,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr); #endif +#if defined(CONFIG_PINCTRL) +int par_io_of_config(struct udevice *dev); +#endif #endif /* __QE_H__ */ -- cgit v1.3.1 From 7bdfe8592956439743cad3c2d3ff5f24c4dd5aa9 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Mon, 3 Feb 2020 07:43:57 +0100 Subject: mpc83xx, keymile boards: enable DM_ETH and add DTS enable DTS support for keymile mpc83xx based boards. get rid of compile warning: ===================== WARNING ====================== This board does not use CONFIG_DM_ETH (Driver Model for Ethernet drivers). Please update the board to use CONFIG_DM_ETH before the v2020.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== Therefore done: - add DTS for all mpc83xx based boards from keymile mainly they are not mainlined to linux. - add u-boot specific dtsi - add stdout-path - add missing ucc4 par_io definitions, which were in board code, but not in linux DTS - remove not used ethernet nodes Signed-off-by: Heiko Schocher Patch-cc: Mario Six Patch-cc: Qiang Zhao Series-to: u-boot Series-version: 3 Series-changes: 3 - rebase patchset to current mainline commit c0192950df - update defconfig files Series-changes: 2 - add patch which fixes Codingstyle errors in drivers/qe - add patch which converts the mpc83xx based boards from keymile to DM_ETH Cover-letter: powerpc, mpc83xx: add DM_ETH support This patch series adds DM ethernet support for mpc83xx based keymile boards. Travis build: END --- arch/powerpc/cpu/mpc83xx/Kconfig | 8 + arch/powerpc/dts/Makefile | 8 + arch/powerpc/dts/km8309-uboot.dtsi | 33 +++ arch/powerpc/dts/km8321-uboot.dtsi | 67 +++++ arch/powerpc/dts/km8321.dtsi | 220 ++++++++++++++++ arch/powerpc/dts/km836x-uboot.dtsi | 61 +++++ arch/powerpc/dts/km836x.dtsi | 182 +++++++++++++ arch/powerpc/dts/kmcoge5ne-uboot.dtsi | 22 ++ arch/powerpc/dts/kmcoge5ne.dts | 320 +++++++++++++++++++++++ arch/powerpc/dts/kmeter1-uboot.dtsi | 42 +++ arch/powerpc/dts/kmeter1.dts | 480 ++++++++++++++++++++++++++++++++++ arch/powerpc/dts/kmopti2.dts | 161 ++++++++++++ arch/powerpc/dts/kmsupc5.dts | 139 ++++++++++ arch/powerpc/dts/kmsupm5.dts | 129 +++++++++ arch/powerpc/dts/kmtegr1.dts | 392 +++++++++++++++++++++++++++ arch/powerpc/dts/kmtepr2.dts | 142 ++++++++++ arch/powerpc/dts/kmtuge1.dts | 100 +++++++ arch/powerpc/dts/kmtuxa1.dts | 100 +++++++ board/keymile/km83xx/Kconfig | 17 ++ board/keymile/km83xx/MAINTAINERS | 23 +- board/keymile/km83xx/km83xx.c | 64 ----- configs/kmcoge5ne_defconfig | 11 +- configs/kmeter1_defconfig | 10 +- configs/kmopti2_defconfig | 11 +- configs/kmsupx5_defconfig | 10 +- configs/kmtegr1_defconfig | 12 +- configs/kmtepr2_defconfig | 10 +- configs/tuge1_defconfig | 10 +- configs/tuxx1_defconfig | 11 +- include/configs/km/km-mpc832x.h | 14 - include/configs/km/km-mpc8360.h | 14 - include/configs/km/km-mpc83xx.h | 10 - 32 files changed, 2694 insertions(+), 139 deletions(-) create mode 100644 arch/powerpc/dts/km8309-uboot.dtsi create mode 100644 arch/powerpc/dts/km8321-uboot.dtsi create mode 100644 arch/powerpc/dts/km8321.dtsi create mode 100644 arch/powerpc/dts/km836x-uboot.dtsi create mode 100644 arch/powerpc/dts/km836x.dtsi create mode 100644 arch/powerpc/dts/kmcoge5ne-uboot.dtsi create mode 100644 arch/powerpc/dts/kmcoge5ne.dts create mode 100644 arch/powerpc/dts/kmeter1-uboot.dtsi create mode 100644 arch/powerpc/dts/kmeter1.dts create mode 100644 arch/powerpc/dts/kmopti2.dts create mode 100644 arch/powerpc/dts/kmsupc5.dts create mode 100644 arch/powerpc/dts/kmsupm5.dts create mode 100644 arch/powerpc/dts/kmtegr1.dts create mode 100644 arch/powerpc/dts/kmtepr2.dts create mode 100644 arch/powerpc/dts/kmtuge1.dts create mode 100644 arch/powerpc/dts/kmtuxa1.dts (limited to 'include') diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig index 18808da37dd..2bae08e2786 100644 --- a/arch/powerpc/cpu/mpc83xx/Kconfig +++ b/arch/powerpc/cpu/mpc83xx/Kconfig @@ -101,34 +101,42 @@ config TARGET_IDS8313 config TARGET_KMETER1 bool "Support kmeter1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMCOGE5NE bool "Support kmcoge5ne" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEGR1 bool "Support kmtegr1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUXX1 bool "Support tuxx1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMSUPX5 bool "Support kmsupx5" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TUGE1 bool "Support tuge1" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMOPTI2 bool "Support kmopti2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_KMTEPR2 bool "Support kmtepr2" select VENDOR_KM + select KM_ENABLE_FULL_DM_DTS_SUPPORT config TARGET_TQM834X bool "Support TQM834x" diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile index 7eb005f4501..266d345f720 100644 --- a/arch/powerpc/dts/Makefile +++ b/arch/powerpc/dts/Makefile @@ -1,5 +1,11 @@ # SPDX-License-Identifier: GPL-2.0+ +dtb-$(CONFIG_TARGET_KMCOGE5NE) += kmcoge5ne.dtb +dtb-$(CONFIG_TARGET_KMETER1) += kmeter1.dtb +dtb-$(CONFIG_TARGET_KMOPTI2) += kmopti2.dtb +dtb-$(CONFIG_TARGET_KMSUPX5) += kmsupc5.dtb kmsupm5.dtb +dtb-$(CONFIG_TARGET_KMTEGR1) += kmtegr1.dtb +dtb-$(CONFIG_TARGET_KMTEPR2) += kmtepr2.dtb dtb-$(CONFIG_TARGET_MPC8548CDS) += mpc8548cds.dtb mpc8548cds_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PA) += p1010rdb-pa.dtb p1010rdb-pa_36b.dtb dtb-$(CONFIG_TARGET_P1010RDB_PB) += p1010rdb-pb.dtb p1010rdb-pb_36b.dtb @@ -16,6 +22,8 @@ dtb-$(CONFIG_TARGET_T1042D4RDB) += t1042d4rdb.dtb dtb-$(CONFIG_TARGET_T2080QDS) += t2080qds.dtb dtb-$(CONFIG_TARGET_T2080RDB) += t2080rdb.dtb dtb-$(CONFIG_TARGET_T4240RDB) += t4240rdb.dtb +dtb-$(CONFIG_TARGET_TUGE1) += kmtuge1.dtb +dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb diff --git a/arch/powerpc/dts/km8309-uboot.dtsi b/arch/powerpc/dts/km8309-uboot.dtsi new file mode 100644 index 00000000000..c44ce7d8dcd --- /dev/null +++ b/arch/powerpc/dts/km8309-uboot.dtsi @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8309 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8309@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km8321-uboot.dtsi b/arch/powerpc/dts/km8321-uboot.dtsi new file mode 100644 index 00000000000..348826057a8 --- /dev/null +++ b/arch/powerpc/dts/km8321-uboot.dtsi @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA 8321 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8321@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&enet_piggy2 { + status = "okay"; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&serial0 { + clock-frequency = <132000000>; + u-boot,dm-pre-reloc; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + compatible = "fsl,mpc8360-par_io"; + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/powerpc/dts/km8321.dtsi b/arch/powerpc/dts/km8321.dtsi new file mode 100644 index 00000000000..e49361359d8 --- /dev/null +++ b/arch/powerpc/dts/km8321.dtsi @@ -0,0 +1,220 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km8321 common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8321@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <528000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8321@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8321-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8321-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_d: gpio-controller@48 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1448 0x18>; + gpio-controller; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + mdio: mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@00 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8321-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km8321-uboot.dtsi" diff --git a/arch/powerpc/dts/km836x-uboot.dtsi b/arch/powerpc/dts/km836x-uboot.dtsi new file mode 100644 index 00000000000..ac5339eff65 --- /dev/null +++ b/arch/powerpc/dts/km836x-uboot.dtsi @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/ { + cpus { + u-boot,dm-pre-reloc; + PowerPC,8360@0 { + u-boot,dm-pre-reloc; + }; + }; + + chosen { + stdout-path = &serial0; + }; +}; + +&qe { + compatible = "fsl,qe", "simple-bus"; +}; + +&soc { + u-boot,dm-pre-reloc; + + par_io@1400 { + u-boot,dm-pre-reloc; + + serial_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@0 { + u-boot,dm-pre-reloc; + }; + ucc_pin@1 { + u-boot,dm-pre-reloc; + }; + ucc_pin@3 { + u-boot,dm-pre-reloc; + }; + ucc_pin@4 { + u-boot,dm-pre-reloc; + }; + ucc_pin@5 { + u-boot,dm-pre-reloc; + }; + ucc_pin@6 { + u-boot,dm-pre-reloc; + }; + ucc_pin@7 { + u-boot,dm-pre-reloc; + }; + }; +}; + +&serial0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/powerpc/dts/km836x.dtsi b/arch/powerpc/dts/km836x.dtsi new file mode 100644 index 00000000000..a8c83fc7e37 --- /dev/null +++ b/arch/powerpc/dts/km836x.dtsi @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA km836x common ports Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8360@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; /* 32 bytes */ + i-cache-line-size = <32>; /* 32 bytes */ + d-cache-size = <32768>; /* L1, 32K */ + i-cache-size = <32768>; /* L1, 32K */ + timebase-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + clock-frequency = <0>; /* Filled in by U-Boot */ + }; + }; + + memory { + device_type = "memory"; + reg = <0 0>; /* Filled in by U-Boot */ + }; + + soc: soc8360@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "fsl,mpc8360-immr", "simple-bus"; + ranges = <0x0 0xe0000000 0x00200000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <0>;/* Filled in by U-Boot */ + + /* power management control module*/ + pmc: power@b00 { + compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; + reg = <0xb00 0x100 0xa00 0x100>; + interrupts = <80 0x8>; + interrupt-parent = <&ipic>; + }; + + i2c0: i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <100000>; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + serial1: serial@4600 { + cell-index = <1>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4600 0x100>; + clock-frequency = <133333333>; + interrupts = <10 0x8>; + interrupt-parent = <&ipic>; + status = "disabled"; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + }; + + par_io: par_io@1400 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0x1400 0x100>; + ranges; + compatible = "fsl,mpc8360-par_io"; + device_type = "par_io"; + num-ports = <7>; + + qe_pio_c: gpio-controller@30 { + #gpio-cells = <2>; + compatible = "fsl,mpc8360-qe-pario-bank", + "fsl,mpc8323-qe-pario-bank"; + reg = <0x1430 0x18>; + gpio-controller; + }; + }; + + qe: qe@100000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe"; + ranges = <0x0 0x100000 0x100000>; + reg = <0x100000 0x480>; + clock-frequency = <0>; /* Filled in by U-Boot */ + brg-frequency = <0>; /* Filled in by U-Boot */ + bus-frequency = <0>; /* Filled in by U-Boot */ + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x0000c000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0xc000>; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = < + 32 0x8 /* ucc1 */ + 33 0x8 /* ucc2 */ + 34 0x8 /* ucc3 */ + 35 0x8 /* ucc4 */ + 40 0x8 /* ucc1 */ + >; + interrupt-parent = <&ipic>; + }; + + spi0: spi@4c0 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x4c0 0x40>; + interrupts = <2>; + interrupt-parent = <&qeic>; + mode = "qe"; + #address-cells = <1>; + #size-cells = <0>; + pio-handle = <&pio_spi>; + }; + + bootcount@0x1bff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x1bff8 0x08>; + }; + }; + }; + + localbus: localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + }; +}; + +#include "km836x-uboot.dtsi" diff --git a/arch/powerpc/dts/kmcoge5ne-uboot.dtsi b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi new file mode 100644 index 00000000000..6a5e74f434b --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne-uboot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmcoge5ne U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + }; +}; + +&enet_switch { + status = "disabled"; +}; + +&enet_mate { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmcoge5ne.dts b/arch/powerpc/dts/kmcoge5ne.dts new file mode 100644 index 00000000000..467e5bd9d27 --- /dev/null +++ b/arch/powerpc/dts/kmcoge5ne.dts @@ -0,0 +1,320 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMCOGE5ne Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "kmcoge5ne"; + compatible = "ABB,kmcoge5ne"; + + aliases { + ethernet0 = &enet_admin; + ethernet1 = &enet_mate; + ethernet2 = &enet_switch; + serial0 = &serial0; + }; +}; + +&soc { + /* brg for hdlc clk */ + brg@0 { + compatible = "fsl,mpc-brg"; + brg-name = "brg16"; + brg-frequency = <20000000>; /* 20 MHz */ + pio-handle = <&pio_brg>; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the fan unit */ + fanu-ivm@50 { + label = "FANUV"; + compatible = "dummy"; + reg = <0x50>; + }; + + /* fan unit (GPIOs and so on) */ + fanu@20 { + label = "FANUV_CTRL"; + compatible = "dummy"; + reg = <0x20>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + backplane@50 { + label = "BP_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { /* RGMII mng-switch */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 0 3 1 0 1 0 /* TxD0 (PA3, in, f1) */ + 0 4 1 0 1 0 /* TxD1 (PA4, in, f1) */ + 0 5 1 0 1 0 /* TxD2 (PA5, in, f1) */ + 0 6 1 0 1 0 /* TxD3 (PA6, in, f1) */ + 0 9 2 0 1 0 /* RxD0 (PA9, out, f1) */ + 0 10 2 0 1 0 /* RxD1 (PA10, out, f1) */ + 0 11 2 0 1 0 /* RxD2 (PA11, out, f1) */ + 0 12 2 0 1 0 /* RxD3 (PA12, out, f1) */ + 0 7 1 0 1 0 /* TX_EN (PA7, in, f1) */ + 0 15 2 0 1 0 /* RX_DV (PA15, out, f1) */ + 0 0 2 0 1 0 /* RX_CLK (PA0, out, f1) */ + 2 9 1 0 3 0 /* GTX_CLK (CLK10) */ + 2 8 2 0 1 0 /* GTX125 (CLK9) */ + >; + }; + + pio_ucc4: ucc_pin@3 { /* RMII, admin front port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { /* RMII, mate backplane port */ + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO (PA1, bi, f2) */ + 0 2 1 0 1 0 /* MDC (PA2, in, f1) */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3) */ + 4 29 3 0 3 0 /* SPI_MISO (PE29, out, f3) */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3) */ + >; + }; + + pio_brg: brg_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 25 1 0 1 0 /* BRG (PC25, out, f1) */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* mng-switch port (UCC1, MDIO 0x10, RGMII) */ + enet_switch: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + /*id=0, full-dup, 1G, no-pause, no-asym_p*/ + fixed-link = <0 1 1000 0 0>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* admin and debug port (UCC4, MDIO 0x00, RMII) */ + enet_admin: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_admin>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* mate backplane port (UCC5, MDIO 0x08, RMII) */ + enet_mate: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_mate>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* admin front port (UCC4, MDIO 0x00, RMII) */ + phy_admin: ethernet-phy@00 { + reg = <0x0>; + }; + + /* mate bp port (UCC5, MDIO 0x08, RMII) */ + phy_mate: ethernet-phy@08 { + reg = <0x08>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 3 0 0xa0000000 0x10000000 + 4 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmcoge5ne-uboot.dtsi" diff --git a/arch/powerpc/dts/kmeter1-uboot.dtsi b/arch/powerpc/dts/kmeter1-uboot.dtsi new file mode 100644 index 00000000000..898fa7dc7a8 --- /dev/null +++ b/arch/powerpc/dts/kmeter1-uboot.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA kmeter1 U-Boot specific Device Tree Source parts + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/ { + aliases { + /delete-property/ ethernet1; + /delete-property/ ethernet2; + /delete-property/ ethernet3; + /delete-property/ ethernet4; + /delete-property/ ethernet5; + /delete-property/ ethernet6; + }; +}; + +&enet_estar1 { + status = "disabled"; +}; + +&enet_estar2 { + status = "disabled"; +}; + +&enet_eth1 { + status = "disabled"; +}; + +&enet_eth2 { + status = "disabled"; +}; + +&enet_eth3 { + status = "disabled"; +}; + +&enet_eth4 { + status = "disabled"; +}; diff --git a/arch/powerpc/dts/kmeter1.dts b/arch/powerpc/dts/kmeter1.dts new file mode 100644 index 00000000000..f1f79952abe --- /dev/null +++ b/arch/powerpc/dts/kmeter1.dts @@ -0,0 +1,480 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA KMETER1 Device Tree Source + * + * 2008-2011 DENX Software Engineering GmbH + * Copyright (C) 2020 Heiko Schocher + */ + +/dts-v1/; + +#include "km836x.dtsi" + +/ { + model = "KMETER1"; + compatible = "ABB,KMETER1"; + + aliases { + ethernet0 = &enet_piggy2; + ethernet1 = &enet_estar1; + ethernet2 = &enet_estar2; + ethernet3 = &enet_eth1; + ethernet4 = &enet_eth2; + ethernet5 = &enet_eth3; + ethernet6 = &enet_eth4; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "Top"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "Control"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "Power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "Front"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + }; +}; + +&serial0 { + status = "okay"; +}; + +&par_io { + pio_ucc1: ucc_pin@0 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 3 1 0 1 0 /* TxD0 */ + 0 4 1 0 1 0 /* TxD1 */ + 0 5 1 0 1 0 /* TxD2 */ + 0 6 1 0 1 0 /* TxD3 */ + 0 9 2 0 1 0 /* RxD0 */ + 0 10 2 0 1 0 /* RxD1 */ + 0 11 2 0 1 0 /* RxD2 */ + 0 12 2 0 1 0 /* RxD3 */ + 0 7 1 0 1 0 /* TX_EN */ + 0 8 1 0 1 0 /* TX_ER */ + 0 15 2 0 1 0 /* RX_DV */ + 0 16 2 0 1 0 /* RX_ER */ + 0 0 2 0 1 0 /* RX_CLK */ + 2 9 1 0 3 0 /* GTX_CLK - CLK10 */ + 2 8 2 0 1 0 /* GTX125 - CLK9 */ + >; + }; + + pio_ucc2: ucc_pin@1 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 0 17 1 0 1 0 /* TxD0 */ + 0 18 1 0 1 0 /* TxD1 */ + 0 19 1 0 1 0 /* TxD2 */ + 0 20 1 0 1 0 /* TxD3 */ + 0 23 2 0 1 0 /* RxD0 */ + 0 24 2 0 1 0 /* RxD1 */ + 0 25 2 0 1 0 /* RxD2 */ + 0 26 2 0 1 0 /* RxD3 */ + 0 21 1 0 1 0 /* TX_EN */ + 0 22 1 0 1 0 /* TX_ER */ + 0 29 2 0 1 0 /* RX_DV */ + 0 30 2 0 1 0 /* RX_ER */ + 0 31 2 0 1 0 /* RX_CLK */ + 2 2 1 0 2 0 /* GTX_CLK - CLK3 */ + 2 3 2 0 1 0 /* GTX125 - CLK4 */ + >; + }; + + pio_ucc4: ucc_pin@3 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */ + 1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */ + 1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */ + 1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */ + 1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */ + 1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */ + 1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */ + + 2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_ucc5: ucc_pin@4 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */ + 3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */ + 3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */ + 3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */ + 3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */ + 3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */ + 3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */ + >; + }; + + pio_ucc6: ucc_pin@5 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */ + 3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */ + 3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */ + 3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */ + 3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */ + 3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */ + 3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */ + >; + }; + + pio_ucc7: ucc_pin@6 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */ + 4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */ + 4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */ + 4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */ + 4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */ + 4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */ + 4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */ + >; + }; + + pio_ucc8: ucc_pin@7 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 0 1 3 0 2 0 /* MDIO */ + 0 2 1 0 1 0 /* MDC */ + + 4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */ + 4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */ + 4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */ + 4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */ + 4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */ + 4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */ + 4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */ + + 2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 4 28 3 0 3 0 /* SPI_MOSI (PE28, out, f3 */ + 4 30 3 0 3 0 /* SPI_CLK (PE30, out, f3 */ + >; + }; + + /* UCC3 as HDLC controller for ICN */ + pio5: ucc_pin@02 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 1 0 1 0 1 0 /* TxD0 */ + 1 6 2 0 1 0 /* RxD0 */ + 1 12 2 0 1 0 /* CTS */ + 2 11 2 0 1 0 /* TX-CLK12 */ + >; + }; + + pio_tdm: tdm_pin@00 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + /* TDMa */ + 0 8 3 0 2 0 /* RxD0 (PA8, bi, f2) */ + 0 13 3 0 2 0 /* TxD0 (PA13, bi, f2) */ + 0 14 2 0 2 0 /* RSync0 (PA14, in, f2) */ + 2 7 2 0 1 0 /* RxClk8 (PC7, in, f1) */ + /* TDMb */ + 0 27 3 0 2 0 /* RxD1 (PA27, bi, f2) */ + 0 22 3 0 2 0 /* TxD1 (PA22, bi, f2) */ + 0 28 2 0 2 0 /* RSync1 (PA28, in, f2) */ + 2 1 2 0 1 0 /* RxClk2 (PC1, in, f1) */ + /* TDMc */ + 1 5 3 0 2 0 /* RxD2 (PB5, bi, f2) */ + 1 8 3 0 2 0 /* TxD2 (PB8, bi, f2) */ + 1 2 2 0 3 0 /* RSync2 (PB2, in, f3) */ + 2 6 2 0 1 0 /* RxClk7 (PC6, in, f1) */ + /* TDMd */ + 1 22 3 0 2 0 /* RxD3 (PB22, bi, f2) */ + 1 19 3 0 1 0 /* TxD3 (PB19, bi, f1) */ + 1 16 2 0 2 0 /* RSync3 (PB16, in, f2) */ + 2 13 2 0 1 0 /* RxClk14 (PC13, in, f1) */ + /* TDMe */ + 3 8 3 0 2 0 /* RxD4 (PD8, bi, f2) */ + 3 5 3 0 2 0 /* TxD4 (PD5, bi, f2) */ + 3 2 2 0 2 0 /* RSync4 (PD2 , in, f2) */ + 2 22 2 0 1 0 /* RxClk23 (PC22, in, f1) */ + /* TDMf */ + 3 19 3 0 2 0 /* RxD5 (PD19, bi, f2) */ + 3 22 3 0 2 0 /* TxD5 (PD22, bi, f2) */ + 3 16 2 0 1 0 /* RSync5 (PD16, in, f1) */ + 2 17 2 0 1 0 /* RxClk18 (PC17, in, f1) */ + /* TDMg */ + 4 8 3 0 2 0 /* RxD6 (PE8, bi, f2) */ + 4 5 3 0 2 0 /* TxD6 (PE5, bi, f2) */ + 4 2 2 0 1 0 /* RSync6 (PE2, in, f1) */ + 2 19 2 0 1 0 /* RxClk20 (PC19, in, f1) */ + /* TDMh */ + 4 19 3 0 2 0 /* RxD7 (PE19, bi, f2) */ + 4 22 3 0 3 0 /* TxD7 (PE22, bi, f3) */ + 4 16 2 0 2 0 /* RSync7 (PE16, in, f2) */ + 2 21 2 0 1 0 /* RxClk22 (PC21, in, f1) */ + /* RxTxClk0/1 */ + 2 0 2 0 1 0 /* Clk1 (PC0, in, f1) */ + 2 23 2 0 1 0 /* Clk24 (PC23, in, f1) */ + /* RxTxSync0/1 */ + 2 10 2 0 1 0 /* Clk11 (PC10, in, f1) */ + 2 20 2 0 1 0>; /* Clk21 (PC20, in, f1) */ + }; +}; + +&qe { + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + enet_estar1: ucc@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk9"; + phy-handle = <&phy_estar1>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc1>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + enet_estar2: ucc@3000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <2>; + reg = <0x3000 0x200>; + interrupts = <33>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk4"; + phy-handle = <&phy_estar2>; + phy-connection-type = "rgmii-id"; + pio-handle = <&pio_ucc2>; + }; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + enet_piggy2: ucc@3200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <4>; + reg = <0x3200 0x200>; + interrupts = <35>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk17"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc4>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + enet_eth1: ucc@2400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <5>; + reg = <0x2400 0x200>; + interrupts = <40>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth1>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc5>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + enet_eth2: ucc@3400 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <6>; + reg = <0x3400 0x200>; + interrupts = <41>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth2>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc6>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + enet_eth3: ucc@2600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <7>; + reg = <0x2600 0x200>; + interrupts = <42>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth3>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc7>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + enet_eth4: ucc@3600 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <8>; + reg = <0x3600 0x200>; + interrupts = <43>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk16"; + phy-handle = <&phy_eth4>; + phy-connection-type = "rmii"; + pio-handle = <&pio_ucc8>; + }; + + mdio@3320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3320 0x18>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC4, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + }; + + /* Eth-1 (UCC5, MDIO 0x08, RMII) */ + phy_eth1: ethernet-phy@8 { + reg = <0x08>; + }; + + /* Eth-2 (UCC6, MDIO 0x09, RMII) */ + phy_eth2: ethernet-phy@9 { + reg = <0x09>; + }; + + /* Eth-3 (UCC7, MDIO 0x0a, RMII) */ + phy_eth3: ethernet-phy@a { + reg = <0x0a>; + }; + + /* Eth-4 (UCC8, MDIO 0x0b, RMII) */ + phy_eth4: ethernet-phy@b { + reg = <0x0b>; + }; + + /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */ + phy_estar1: ethernet-phy@10 { + interrupt-parent = <&ipic>; + interrupts = <17 0x8>; + reg = <0x10>; + }; + + /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */ + phy_estar2: ethernet-phy@11 { + interrupt-parent = <&ipic>; + interrupts = <18 0x8>; + reg = <0x11>; + }; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */ + 1 0 0xe8000000 0x01000000 /* LB 1 */ + 3 0 0xa0000000 0x10000000>; /* LB 3 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0 0x04000000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xC0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xE0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; + +#include "kmeter1-uboot.dtsi" diff --git a/arch/powerpc/dts/kmopti2.dts b/arch/powerpc/dts/kmopti2.dts new file mode 100644 index 00000000000..23e31872dd5 --- /dev/null +++ b/arch/powerpc/dts/kmopti2.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA OPTI2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMOPTI2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 PAXE */ + 3 0 0xb0000000 0x10000000>; /* LB 3 OPI2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupc5.dts b/arch/powerpc/dts/kmsupc5.dts new file mode 100644 index 00000000000..60ca0d3324f --- /dev/null +++ b/arch/powerpc/dts/kmsupc5.dts @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPC5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPC5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + /* UCC4_RMII_CLK (CLK17) */ + 3 10 2 0 3 0 + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + * port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&spi0 { + pio-handle = <&pio_spi>; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmsupm5.dts b/arch/powerpc/dts/kmsupm5.dts new file mode 100644 index 00000000000..1cd11c33449 --- /dev/null +++ b/arch/powerpc/dts/kmsupm5.dts @@ -0,0 +1,129 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA SUPM5 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "SUPM5"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 0 3 0 1 0 /* SPI_MOSI (PD0, bi, f3) */ + 3 1 3 0 1 0 /* SPI_MISO (PD1, bi, f3) */ + 3 2 3 0 1 0 /* SPI_CLK (PD2, bi, f3) */ + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 LPXF */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtegr1.dts b/arch/powerpc/dts/kmtegr1.dts new file mode 100644 index 00000000000..c9b21cf5002 --- /dev/null +++ b/arch/powerpc/dts/kmtegr1.dts @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEGR1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +/ { + model = "KMTEGR1"; + compatible = "ABB,kmpbec8309"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_zynq; + ethernet1 = &enet_piggy2; + serial0 = &serial0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + PowerPC,8309@0 { + device_type = "cpu"; + reg = <0x0>; + d-cache-line-size = <32>; // 32 bytes + i-cache-line-size = <32>; // 32 bytes + d-cache-size = <16384>; // L1, 16K + i-cache-size = <16384>; // L1, 16K + timebase-frequency = <66000000>; + bus-frequency = <264000000>; + clock-frequency = <264000000>; + }; + }; + + memory { + device_type = "memory"; + reg = <0x00000000 0x10000000>; + }; + + soc: soc8309@e0000000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "soc"; + compatible = "simple-bus"; + ranges = <0x0 0xe0000000 0x00100000>; + reg = <0xe0000000 0x00000200>; + bus-frequency = <264000000>; + + i2c@3000 { + #address-cells = <1>; + #size-cells = <0>; + cell-index = <0>; + compatible = "fsl,mpc8313-i2c","fsl-i2c"; + reg = <0x3000 0x100>; + interrupts = <14 0x8>; + interrupt-parent = <&ipic>; + clock-frequency = <400000>; + + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* + * Inventory EEPROM of the + * unit itself + */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@48 { + label = "front"; + compatible = "national,lm75"; + reg = <0x48>; + }; + + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + + temp@4b { + label = "bottom"; + compatible = "national,lm75"; + reg = <0x4b>; + }; + }; + + i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + }; + }; + }; + + serial0: serial@4500 { + cell-index = <0>; + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550"; + reg = <0x4500 0x100>; + clock-frequency = <264000000>; + interrupts = <9 0x8>; + interrupt-parent = <&ipic>; + }; + + dma@82a8 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,mpc8309-dma", "fsl,elo-dma"; + reg = <0x82a8 4>; + ranges = <0 0x8100 0x1a8>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + cell-index = <0>; + dma-channel@0 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@80 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x80 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@100 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x100 0x80>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + dma-channel@180 { + compatible = "fsl,mpc8309-dma-channel", + "fsl,elo-dma-channel"; + reg = <0x180 0x28>; + interrupt-parent = <&ipic>; + interrupts = <71 8>; + }; + }; + + ipic: pic@700 { + #address-cells = <0>; + #interrupt-cells = <2>; + compatible = "fsl,pq2pro-pic", "fsl,ipic"; + interrupt-controller; + reg = <0x700 0x100>; + device_type = "ipic"; + }; + + gpio1: gpio-controller@c00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xc00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio-controller@d00 { + #gpio-cells = <2>; + compatible = "fsl,mpc8309-gpio", "fsl,mpc8349-gpio"; + reg = <0xd00 0x100>; + interrupts = <75 0x8>; + interrupt-parent = <&ipic>; + gpio-controller; + interrupt-controller; + #interrupt-cells = <2>; + }; + + spi@7000 { + cell-index = <0>; + compatible = "fsl,spi"; + reg = <0x7000 0x1000>; + interrupts = <16 0x8>; + interrupt-parent = <&ipic>; + mode = "cpu"; + #address-cells = <1>; + #size-cells = <0>; + + /* GPIO_15 chipselect for ZYNQ flash */ + gpios = <&gpio1 15 0>; + + zynq_flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spansion,m25p80"; + reg = <0>; + spi-max-frequency = <4000000>; + m25p,fast-read; + partition@0 { + label = "bootloader"; + reg = <0x0 0x01000000>; + }; + }; + }; + }; + + qe: qe@e0100000 { + #address-cells = <1>; + #size-cells = <1>; + device_type = "qe"; + compatible = "fsl,qe"; + ranges = <0x0 0xe0100000 0x00100000>; + reg = <0xe0100000 0x480>; + brg-frequency = <0>; + bus-frequency = <396000000>; + fsl,qe-num-snums = <32>; + + muram@10000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,qe-muram", "fsl,cpm-muram"; + ranges = <0x0 0x00010000 0x00004000>; + + data-only@0 { + compatible = "fsl,qe-muram-data", + "fsl,cpm-muram-data"; + reg = <0x0 0x4000>; + }; + }; + + /* ZYNQ (UCC1, MDIO 0x10, MII) */ + enet_zynq: ethernet@2000 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <1>; + reg = <0x2000 0x200>; + interrupts = <32>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + /*id=0, full-dup, 100M, no-pause, no-asym_p*/ + fixed-link = <0 1 100 0 0>; + rx-clock-name = "clk9"; + tx-clock-name = "clk10"; + phy-connection-type = "mii"; + }; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + enet_piggy2: ucc@2200 { + device_type = "network"; + compatible = "ucc_geth"; + cell-index = <3>; + reg = <0x2200 0x200>; + interrupts = <34>; + interrupt-parent = <&qeic>; + local-mac-address = [ 00 00 00 00 00 00 ]; + rx-clock-name = "none"; + tx-clock-name = "clk12"; + phy-handle = <&phy_piggy2>; + phy-connection-type = "rmii"; + }; + + mdio@2320 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2320 0x38>; + compatible = "fsl,ucc-mdio"; + + /* Piggy2 (UCC3, MDIO 0x00, RMII) */ + phy_piggy2: ethernet-phy@0 { + reg = <0x0>; + device_type = "ethernet-phy"; + }; + + /* Explicitly set the tbi-phy to a non-zero address + * so that it does not conflict with phy_piggy2 that + * is unfortunately at address 0 + */ + tbi1: tbi-phy@1 { + reg = <0x1>; + device_type = "tbi-phy"; + }; + }; + + qeic: interrupt-controller@80 { + interrupt-controller; + compatible = "fsl,qe-ic"; + #address-cells = <0>; + #interrupt-cells = <1>; + reg = <0x80 0x80>; + big-endian; + interrupts = <32 8 33 8>; + interrupt-parent = <&ipic>; + }; + bootcount@0x13ff8 { + device_type = "bootcount"; + compatible = "u-boot,bootcount"; + reg = <0x13ff8 0x08>; + }; + + }; + localbus@e0005000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "fsl,mpc8309-localbus", "fsl,pq2pro-localbus", + "simple-bus"; + reg = <0xe0005000 0xd8>; + ranges = <0 0 0xf0000000 0x04000000 + 1 0 0xe8000000 0x01000000 + 2 0 0xe0000000 0x10000000 + 3 0 0xb0000000 0x10000000>; + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + nornand = "nor"; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xc0000>; + }; + partition@c0000 { /* 256KB */ + label = "qe-fw"; + reg = <0xc0000 0x40000>; + }; + partition@100000 { /* 128KB */ + label = "env"; + reg = <0x100000 0x20000>; + }; + partition@120000 { /* 128KB */ + label = "envred"; + reg = <0x120000 0x20000>; + }; + partition@140000 { /* 64256KB */ + label = "ubi0"; + reg = <0x140000 0x3EC0000>; + }; + }; + }; +}; + +#include "km8309-uboot.dtsi" diff --git a/arch/powerpc/dts/kmtepr2.dts b/arch/powerpc/dts/kmtepr2.dts new file mode 100644 index 00000000000..5a272ec6cbe --- /dev/null +++ b/arch/powerpc/dts/kmtepr2.dts @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TEPR2 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "KMTEPR2"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&i2c0 { + mux@70 { + compatible = "nxp,pca9547"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + /* Inventory EEPROM of the unit itself */ + ivm@50 { + label = "MAIN_CTRL"; + compatible = "dummy"; + reg = <0x50>; + }; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + /* Temperature sensors */ + temp@49 { + label = "board"; + compatible = "national,lm75"; + reg = <0x49>; + }; + + temp@4a { + label = "power"; + compatible = "national,lm75"; + reg = <0x4a>; + }; + }; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 NVSRAM */ + 3 0 0xb0000000 0x10000000>; /* LB 3 TEP2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + use-advanced-sector-protection; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuge1.dts b/arch/powerpc/dts/kmtuge1.dts new file mode 100644 index 00000000000..8a7b5a42cba --- /dev/null +++ b/arch/powerpc/dts/kmtuge1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUGE1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUGE1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000>; /* LB 2 PAXI */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/arch/powerpc/dts/kmtuxa1.dts b/arch/powerpc/dts/kmtuxa1.dts new file mode 100644 index 00000000000..c2681c5efbc --- /dev/null +++ b/arch/powerpc/dts/kmtuxa1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * ABB PGGA TUXA1 Device Tree Source + * + * Copyright (C) 2020 Heiko Schocher + * + */ + +/dts-v1/; + +#include "km8321.dtsi" + +/ { + model = "TUXA1"; + compatible = "ABB,kmpbec8321"; + #address-cells = <1>; + #size-cells = <1>; + + aliases { + ethernet0 = &enet_piggy2; + serial0 = &serial0; + }; +}; + +&par_io { + /* UCC5 as HDLC controller for ICN */ + pio_ucc5: ucc_pin@04 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 2 0 1 0 2 0 /* TxD0 */ + 2 8 2 0 2 0 /* RxD0 */ + 2 29 2 0 2 0 /* CTS */ + 3 30 2 0 1 0 /* ICN CLK */ + >; + }; + + /* UCC4 Piggy Ethernet */ + pio_ucc4: ucc_pin@03 { + pio-map = < + /* port pin dir open_drain assignment has_irq */ + 3 4 3 0 2 0 /* MDIO */ + 3 5 1 0 2 0 /* MDC */ + + 1 18 1 0 1 0 /* TxD0 */ + 1 19 1 0 1 0 /* TxD1 */ + 1 22 2 0 1 0 /* RxD0 */ + 1 23 2 0 1 0 /* RxD1 */ + 1 26 2 0 1 0 /* RX_ER */ + 1 28 2 0 1 0 /* RX_DV */ + 1 30 1 0 1 0 /* TX_EN */ + 1 31 2 0 1 0 /* CRS */ + 3 10 2 0 3 0 /* UCC4_RMII_CLK (CLK17) */ + >; + }; + + pio_spi: spi_pin@01 { + pio-map = < + /* + *port pin dir open_drain assignment has_irq + * SPI_MOSI (PD0, bi, f3) + */ + 3 0 3 0 1 0 + /* SPI_MISO (PD1, bi, f3) */ + 3 1 3 0 1 0 + /* SPI_CLK (PD2, bi, f3) */ + 3 2 3 0 1 0 + >; + }; +}; + +&localbus { + ranges = <0 0 0xf0000000 0x04000000 /* LB 0 Flash (boot) */ + 1 0 0xe8000000 0x01000000 /* LB 1 PRIO1 and Piggy */ + 2 0 0xa0000000 0x10000000 /* LB 2 LPXF */ + 3 0 0xb0000000 0x10000000>; /* LB 3 PINC2 */ + + flash@0,0 { + compatible = "cfi-flash"; + reg = <0 0x00000000 0x04000000>; + bank-width = <2>; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { /* 768KB */ + label = "u-boot"; + reg = <0 0xC0000>; + }; + partition@c0000 { /* 128KB */ + label = "env"; + reg = <0xc0000 0x20000>; + }; + partition@e0000 { /* 128KB */ + label = "envred"; + reg = <0xe0000 0x20000>; + }; + partition@100000 { /* 64512KB */ + label = "ubi0"; + reg = <0x100000 0x3F00000>; + }; + }; +}; diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig index 94075ce70f4..bbafabdcb2c 100644 --- a/board/keymile/km83xx/Kconfig +++ b/board/keymile/km83xx/Kconfig @@ -1,3 +1,20 @@ +menu "KM 83xx Options" + depends on MPC83xx + +config KM_ENABLE_FULL_DM_DTS_SUPPORT + bool "enable full DM/DTS support for KM 83xx boards" + default y + select CMD_DM + select DM + select DM_ETH + select DM_MDIO + select DM_SERIAL + select OF_CONTROL + select PINCTRL + select PINCTRL_QE + select PHYLIB +endmenu + if TARGET_KMETER1 config SYS_BOARD diff --git a/board/keymile/km83xx/MAINTAINERS b/board/keymile/km83xx/MAINTAINERS index d9483c75adb..9268719a74b 100644 --- a/board/keymile/km83xx/MAINTAINERS +++ b/board/keymile/km83xx/MAINTAINERS @@ -1,5 +1,6 @@ KM83XX BOARD M: Holger Brunck +M: Heiko Schocher S: Maintained F: board/keymile/km83xx/ F: include/configs/km8360.h @@ -7,12 +8,24 @@ F: configs/kmcoge5ne_defconfig F: configs/kmeter1_defconfig F: include/configs/tuxx1.h F: configs/kmopti2_defconfig +F: configs/kmsupx5_defconfig F: configs/kmtepr2_defconfig F: configs/kmtegr1_defconfig F: configs/tuge1_defconfig F: configs/tuxx1_defconfig - -KMSUPX5 BOARD -M: Heiko Schocher -S: Maintained -F: configs/kmsupx5_defconfig +F: arch/powerpc/dts/km8309-uboot.dtsi +F: arch/powerpc/dts/km8321-uboot.dtsi +F: arch/powerpc/dts/km8321.dtsi +F: arch/powerpc/dts/km836x-uboot.dtsi +F: arch/powerpc/dts/km836x.dtsi +F: arch/powerpc/dts/kmcoge5ne-uboot.dtsi +F: arch/powerpc/dts/kmcoge5ne.dts +F: arch/powerpc/dts/kmeter1-uboot.dtsi +F: arch/powerpc/dts/kmeter1.dts +F: arch/powerpc/dts/kmopti2.dts +F: arch/powerpc/dts/kmsupc5.dts +F: arch/powerpc/dts/kmsupm5.dts +F: arch/powerpc/dts/kmtegr1.dts +F: arch/powerpc/dts/kmtepr2.dts +F: arch/powerpc/dts/kmtuge1.dts +F: arch/powerpc/dts/kmtuxa1.dts diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 0aad452dde6..86697159405 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -36,70 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; -const qe_iop_conf_t qe_iop_conf_tab[] = { - /* port pin dir open_drain assign */ -#if defined(CONFIG_ARCH_MPC8360) - /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */ - {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */ - - /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ -#elif !defined(CONFIG_ARCH_MPC8309) - /* Local Bus */ - {0, 16, 1, 0, 3}, /* LA00 */ - {0, 17, 1, 0, 3}, /* LA01 */ - {0, 18, 1, 0, 3}, /* LA02 */ - {0, 19, 1, 0, 3}, /* LA03 */ - {0, 20, 1, 0, 3}, /* LA04 */ - {0, 21, 1, 0, 3}, /* LA05 */ - {0, 22, 1, 0, 3}, /* LA06 */ - {0, 23, 1, 0, 3}, /* LA07 */ - {0, 24, 1, 0, 3}, /* LA08 */ - {0, 25, 1, 0, 3}, /* LA09 */ - {0, 26, 1, 0, 3}, /* LA10 */ - {0, 27, 1, 0, 3}, /* LA11 */ - {0, 28, 1, 0, 3}, /* LA12 */ - {0, 29, 1, 0, 3}, /* LA13 */ - {0, 30, 1, 0, 3}, /* LA14 */ - {0, 31, 1, 0, 3}, /* LA15 */ - - /* MDIO */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ - - /* UCC4 - UEC */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 26, 2, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {1, 30, 1, 0, 1}, /* TxEN */ - {1, 31, 2, 0, 1}, /* CRS */ - {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */ -#endif - - /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, -}; - static int piggy_present(void) { struct km_bec_fpga __iomem *base = diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 733e7f32288..1be9e1cf84c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmcoge5ne" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMCOGE5NE=y @@ -156,7 +156,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -173,6 +172,7 @@ CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y CONFIG_CMD_NAND=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -186,8 +186,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -197,8 +198,10 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y CONFIG_BCH=y -CONFIG_OF_LIBFDT=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index ecaeb5d49e6..f24b7aafc05 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth2" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE011BFF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmeter1" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMETER1=y @@ -120,7 +120,6 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -136,6 +135,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -149,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -159,7 +160,8 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 302fdefe5f0..b74ea4b46c5 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmopti2" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMOPTI2=y @@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -155,6 +154,7 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y CONFIG_CMD_EEPROM=y CONFIG_CMD_I2C=y +# CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -168,8 +168,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -178,7 +179,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 222a7008c8e..bf613a63302 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmsupm5" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMSUPX5=y @@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig index 58674c64a52..8fb46996ce7 100644 --- a/configs/kmtegr1_defconfig +++ b/configs/kmtegr1_defconfig @@ -4,8 +4,8 @@ CONFIG_KM_DEF_NETDEV="eth1" CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmtegr1" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEGR1=y @@ -118,7 +118,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_SYS_EXTRA_OPTIONS="KMTEGR1" @@ -150,8 +149,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF0100000 CONFIG_ENV_ADDR_REDUND=0xF0120000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -161,9 +161,13 @@ CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y CONFIG_MTD_RAW_NAND=y +CONFIG_PHY_SMSC=y +CONFIG_PHY_FIXED=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y CONFIG_SYS_NS16550=y CONFIG_BCH=y -CONFIG_OF_LIBFDT=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 36d02e151ef..3f94db68962 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmtepr2" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_KMTEPR2=y @@ -139,7 +139,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -168,8 +167,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -178,7 +178,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 13a40516934..7a46f9ce185 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmtuge1" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_TUGE1=y @@ -119,7 +119,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -148,8 +147,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -158,7 +158,9 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 343e11a3bbb..ada9b0cdb3e 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -3,8 +3,8 @@ CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_BOOTCOUNT_BOOTLIMIT=3 -CONFIG_SYS_BOOTCOUNT_ADDR=0xE0113FF8 CONFIG_SYS_CLK_FREQ=66000000 +CONFIG_DEFAULT_DEVICE_TREE="kmtuxa1" CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y CONFIG_TARGET_TUXX1=y @@ -141,7 +141,6 @@ CONFIG_ACR_APARK_MASTER=y CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y -# CONFIG_SYS_MALLOC_F is not set CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_MISC_INIT_R=y @@ -170,8 +169,9 @@ CONFIG_ENV_OVERWRITE=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR=0xF00C0000 CONFIG_ENV_ADDR_REDUND=0xF00E0000 -CONFIG_DM=y CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_DM_BOOTCOUNT=y +CONFIG_BOOTCOUNT_MEM=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y @@ -180,7 +180,10 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y CONFIG_FLASH_CFI_MTD=y CONFIG_SYS_FLASH_PROTECTION=y CONFIG_SYS_FLASH_CFI=y +CONFIG_PHY_SMSC=y +CONFIG_DM_ETH_PHY=y +CONFIG_QE_UEC=y # CONFIG_PCI is not set +# CONFIG_PINCTRL_FULL is not set CONFIG_QE=y CONFIG_SYS_NS16550=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h index d7186ab9198..22dfb5da67b 100644 --- a/include/configs/km/km-mpc832x.h +++ b/include/configs/km/km-mpc832x.h @@ -10,20 +10,6 @@ #define CONFIG_SYS_CLK_FREQ 66000000 #define CONFIG_83XX_PCICLK 66000000 -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 - /* * System IO Config */ diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h index bdbb8bf6b59..798b1269605 100644 --- a/include/configs/km/km-mpc8360.h +++ b/include/configs/km/km-mpc8360.h @@ -6,20 +6,6 @@ * High Level Configuration Options */ -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 - /* * System IO Setup */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 7c7f2d4ec01..7aacd37c8a7 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -61,16 +61,6 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_NUM_I2C_BUSES 4 -- cgit v1.3.1 From 8ef7df5df39edbeb1367409cc340646810d2369b Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 10 Sep 2020 16:00:02 +0200 Subject: reset: Add IPQ40xx reset controller driver On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko Cc: Luka Perkov --- MAINTAINERS | 2 + drivers/reset/Kconfig | 8 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-ipq4019.c | 173 +++++++++++++++++++++++++ include/dt-bindings/reset/qcom,ipq4019-reset.h | 92 +++++++++++++ 5 files changed, 276 insertions(+) create mode 100644 drivers/reset/reset-ipq4019.c create mode 100644 include/dt-bindings/reset/qcom,ipq4019-reset.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 80e6e54e256..fcad3e45f30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -238,6 +238,8 @@ M: Luka Perkov S: Maintained F: arch/arm/mach-ipq40xx/ F: include/dt-bindings/clock/qcom,ipq4019-gcc.h +F: include/dt-bindings/reset/qcom,ipq4019-reset.h +F: drivers/reset/reset-ipq4019.c ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K M: Stefan Roese diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 253902ff574..3fdfe4a6cb0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -148,6 +148,14 @@ config RESET_IMX7 help Support for reset controller on i.MX7/8 SoCs. +config RESET_IPQ419 + bool "Reset driver for Qualcomm IPQ40xx SoCs" + depends on DM_RESET && ARCH_IPQ40XX + default y + help + Support for reset controller on Qualcomm + IPQ40xx SoCs. + config RESET_SIFIVE bool "Reset Driver for SiFive SoC's" depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540 diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 3c7f066ae39..5176da58853 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o +obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o diff --git a/drivers/reset/reset-ipq4019.c b/drivers/reset/reset-ipq4019.c new file mode 100644 index 00000000000..f216db4ce5c --- /dev/null +++ b/drivers/reset/reset-ipq4019.c @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2020 Sartura Ltd. + * + * Author: Robert Marko + * + * Based on Linux driver + */ + +#include +#include +#include +#include +#include +#include +#include + +struct ipq4019_reset_priv { + phys_addr_t base; +}; + +struct qcom_reset_map { + unsigned int reg; + u8 bit; +}; + +static const struct qcom_reset_map gcc_ipq4019_resets[] = { + [WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 }, + [WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 }, + [WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 }, + [WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 }, + [WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 }, + [WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 }, + [WIFI1_CPU_INIT_RESET] = { 0x20008, 5 }, + [WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 }, + [WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 }, + [WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 }, + [WIFI1_CORE_WARM_RESET] = { 0x20008, 1 }, + [WIFI1_CORE_COLD_RESET] = { 0x20008, 0 }, + [USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 }, + [USB3_HSPHY_POR_ARES] = { 0x1e038, 4 }, + [USB3_HSPHY_S_ARES] = { 0x1e038, 2 }, + [USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 }, + [USB2_HSPHY_S_ARES] = { 0x1e01c, 2 }, + [PCIE_PHY_AHB_ARES] = { 0x1d010, 11 }, + [PCIE_AHB_ARES] = { 0x1d010, 10 }, + [PCIE_PWR_ARES] = { 0x1d010, 9 }, + [PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 }, + [PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 }, + [PCIE_PHY_ARES] = { 0x1d010, 6 }, + [PCIE_PARF_XPU_ARES] = { 0x1d010, 5 }, + [PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 }, + [PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 }, + [PCIE_PIPE_ARES] = { 0x1d010, 2 }, + [PCIE_AXI_S_ARES] = { 0x1d010, 1 }, + [PCIE_AXI_M_ARES] = { 0x1d010, 0 }, + [ESS_RESET] = { 0x12008, 0}, + [GCC_BLSP1_BCR] = {0x01000, 0}, + [GCC_BLSP1_QUP1_BCR] = {0x02000, 0}, + [GCC_BLSP1_UART1_BCR] = {0x02038, 0}, + [GCC_BLSP1_QUP2_BCR] = {0x03008, 0}, + [GCC_BLSP1_UART2_BCR] = {0x03028, 0}, + [GCC_BIMC_BCR] = {0x04000, 0}, + [GCC_TLMM_BCR] = {0x05000, 0}, + [GCC_IMEM_BCR] = {0x0E000, 0}, + [GCC_ESS_BCR] = {0x12008, 0}, + [GCC_PRNG_BCR] = {0x13000, 0}, + [GCC_BOOT_ROM_BCR] = {0x13008, 0}, + [GCC_CRYPTO_BCR] = {0x16000, 0}, + [GCC_SDCC1_BCR] = {0x18000, 0}, + [GCC_SEC_CTRL_BCR] = {0x1A000, 0}, + [GCC_AUDIO_BCR] = {0x1B008, 0}, + [GCC_QPIC_BCR] = {0x1C000, 0}, + [GCC_PCIE_BCR] = {0x1D000, 0}, + [GCC_USB2_BCR] = {0x1E008, 0}, + [GCC_USB2_PHY_BCR] = {0x1E018, 0}, + [GCC_USB3_BCR] = {0x1E024, 0}, + [GCC_USB3_PHY_BCR] = {0x1E034, 0}, + [GCC_SYSTEM_NOC_BCR] = {0x21000, 0}, + [GCC_PCNOC_BCR] = {0x2102C, 0}, + [GCC_DCD_BCR] = {0x21038, 0}, + [GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0}, + [GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0}, + [GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0}, + [GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0}, + [GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0}, + [GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0}, + [GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0}, + [GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0}, + [GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0}, + [GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0}, + [GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0}, + [GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0}, + [GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0}, + [GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0}, + [GCC_TCSR_BCR] = {0x22000, 0}, + [GCC_MPM_BCR] = {0x24000, 0}, + [GCC_SPDM_BCR] = {0x25000, 0}, +}; + +static int ipq4019_reset_assert(struct reset_ctl *rst) +{ + struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); + const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; + const struct qcom_reset_map *map; + u32 value; + + map = &reset_map[rst->id]; + + value = readl(priv->base + map->reg); + value |= BIT(map->bit); + writel(value, priv->base + map->reg); + + return 0; +} + +static int ipq4019_reset_deassert(struct reset_ctl *rst) +{ + struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev); + const struct qcom_reset_map *reset_map = gcc_ipq4019_resets; + const struct qcom_reset_map *map; + u32 value; + + map = &reset_map[rst->id]; + + value = readl(priv->base + map->reg); + value &= ~BIT(map->bit); + writel(value, priv->base + map->reg); + + return 0; +} + +static int ipq4019_reset_free(struct reset_ctl *rst) +{ + return 0; +} + +static int ipq4019_reset_request(struct reset_ctl *rst) +{ + return 0; +} + +static const struct reset_ops ipq4019_reset_ops = { + .request = ipq4019_reset_request, + .rfree = ipq4019_reset_free, + .rst_assert = ipq4019_reset_assert, + .rst_deassert = ipq4019_reset_deassert, +}; + +static const struct udevice_id ipq4019_reset_ids[] = { + { .compatible = "qcom,gcc-reset-ipq4019" }, + { } +}; + +static int ipq4019_reset_probe(struct udevice *dev) +{ + struct ipq4019_reset_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(ipq4019_reset) = { + .name = "ipq4019_reset", + .id = UCLASS_RESET, + .of_match = ipq4019_reset_ids, + .ops = &ipq4019_reset_ops, + .probe = ipq4019_reset_probe, + .priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv), +}; diff --git a/include/dt-bindings/reset/qcom,ipq4019-reset.h b/include/dt-bindings/reset/qcom,ipq4019-reset.h new file mode 100644 index 00000000000..ed047d7402d --- /dev/null +++ b/include/dt-bindings/reset/qcom,ipq4019-reset.h @@ -0,0 +1,92 @@ +/* Copyright (c) 2015 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ +#ifndef __QCOM_RESET_IPQ4019_H__ +#define __QCOM_RESET_IPQ4019_H__ + +#define WIFI0_CPU_INIT_RESET 0 +#define WIFI0_RADIO_SRIF_RESET 1 +#define WIFI0_RADIO_WARM_RESET 2 +#define WIFI0_RADIO_COLD_RESET 3 +#define WIFI0_CORE_WARM_RESET 4 +#define WIFI0_CORE_COLD_RESET 5 +#define WIFI1_CPU_INIT_RESET 6 +#define WIFI1_RADIO_SRIF_RESET 7 +#define WIFI1_RADIO_WARM_RESET 8 +#define WIFI1_RADIO_COLD_RESET 9 +#define WIFI1_CORE_WARM_RESET 10 +#define WIFI1_CORE_COLD_RESET 11 +#define USB3_UNIPHY_PHY_ARES 12 +#define USB3_HSPHY_POR_ARES 13 +#define USB3_HSPHY_S_ARES 14 +#define USB2_HSPHY_POR_ARES 15 +#define USB2_HSPHY_S_ARES 16 +#define PCIE_PHY_AHB_ARES 17 +#define PCIE_AHB_ARES 18 +#define PCIE_PWR_ARES 19 +#define PCIE_PIPE_STICKY_ARES 20 +#define PCIE_AXI_M_STICKY_ARES 21 +#define PCIE_PHY_ARES 22 +#define PCIE_PARF_XPU_ARES 23 +#define PCIE_AXI_S_XPU_ARES 24 +#define PCIE_AXI_M_VMIDMT_ARES 25 +#define PCIE_PIPE_ARES 26 +#define PCIE_AXI_S_ARES 27 +#define PCIE_AXI_M_ARES 28 +#define ESS_RESET 29 +#define GCC_BLSP1_BCR 30 +#define GCC_BLSP1_QUP1_BCR 31 +#define GCC_BLSP1_UART1_BCR 32 +#define GCC_BLSP1_QUP2_BCR 33 +#define GCC_BLSP1_UART2_BCR 34 +#define GCC_BIMC_BCR 35 +#define GCC_TLMM_BCR 36 +#define GCC_IMEM_BCR 37 +#define GCC_ESS_BCR 38 +#define GCC_PRNG_BCR 39 +#define GCC_BOOT_ROM_BCR 40 +#define GCC_CRYPTO_BCR 41 +#define GCC_SDCC1_BCR 42 +#define GCC_SEC_CTRL_BCR 43 +#define GCC_AUDIO_BCR 44 +#define GCC_QPIC_BCR 45 +#define GCC_PCIE_BCR 46 +#define GCC_USB2_BCR 47 +#define GCC_USB2_PHY_BCR 48 +#define GCC_USB3_BCR 49 +#define GCC_USB3_PHY_BCR 50 +#define GCC_SYSTEM_NOC_BCR 51 +#define GCC_PCNOC_BCR 52 +#define GCC_DCD_BCR 53 +#define GCC_SNOC_BUS_TIMEOUT0_BCR 54 +#define GCC_SNOC_BUS_TIMEOUT1_BCR 55 +#define GCC_SNOC_BUS_TIMEOUT2_BCR 56 +#define GCC_SNOC_BUS_TIMEOUT3_BCR 57 +#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 +#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 +#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 +#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 +#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 +#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 +#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 +#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 +#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 +#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 +#define GCC_TCSR_BCR 68 +#define GCC_QDSS_BCR 69 +#define GCC_MPM_BCR 70 +#define GCC_SPDM_BCR 71 + +#endif -- cgit v1.3.1 From cfecbaf4e768991056a88d3a7a3daf4b4baf8038 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 7 Sep 2020 17:46:33 +0300 Subject: dm: core: add support for device re-parenting In common clock framework the relation b/w parent and child clocks is determined based on the udevice parent/child information. A clock parent could be changed based on devices needs. In case this is happen the functionalities for clock who's parent is changed are broken. Add a function that reparent a device. This will be used in clk-uclass.c to reparent a clock device. Signed-off-by: Claudiu Beznea Reviewed-by: Simon Glass --- drivers/core/device.c | 22 ++++++ include/dm/device-internal.h | 9 +++ test/dm/core.c | 160 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 191 insertions(+) (limited to 'include') diff --git a/drivers/core/device.c b/drivers/core/device.c index 355dbd147a9..e90d70101c2 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -276,6 +276,28 @@ int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, return ret; } +int device_reparent(struct udevice *dev, struct udevice *new_parent) +{ + struct udevice *pos, *n; + + assert(dev); + assert(new_parent); + + list_for_each_entry_safe(pos, n, &dev->parent->child_head, + sibling_node) { + if (pos->driver != dev->driver) + continue; + + list_del(&dev->sibling_node); + list_add_tail(&dev->sibling_node, &new_parent->child_head); + dev->parent = new_parent; + + break; + } + + return 0; +} + static void *alloc_priv(int size, uint flags) { void *priv; diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index 5145fb4e145..1dcc22f6891 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -83,6 +83,15 @@ int device_bind_with_driver_data(struct udevice *parent, int device_bind_by_name(struct udevice *parent, bool pre_reloc_only, struct driver_info *info, struct udevice **devp); +/** + * device_reparent: reparent the device to a new parent + * + * @dev: pointer to device to be reparented + * @new_parent: pointer to new parent device + * @return 0 if OK, -ve on error + */ +int device_reparent(struct udevice *dev, struct udevice *new_parent); + /** * device_ofdata_to_platdata() - Read platform data for a device * diff --git a/test/dm/core.c b/test/dm/core.c index 8ed5bf73705..6f380a574cf 100644 --- a/test/dm/core.c +++ b/test/dm/core.c @@ -643,6 +643,166 @@ static int dm_test_children(struct unit_test_state *uts) } DM_TEST(dm_test_children, 0); +static int dm_test_device_reparent(struct unit_test_state *uts) +{ + struct dm_test_state *dms = uts->priv; + struct udevice *top[NODE_COUNT]; + struct udevice *child[NODE_COUNT]; + struct udevice *grandchild[NODE_COUNT]; + struct udevice *dev; + int total; + int ret; + int i; + + /* We don't care about the numbering for this test */ + dms->skip_post_probe = 1; + + ut_assert(NODE_COUNT > 5); + + /* First create 10 top-level children */ + ut_assertok(create_children(uts, dms->root, NODE_COUNT, 0, top)); + + /* Now a few have their own children */ + ut_assertok(create_children(uts, top[2], NODE_COUNT, 2, NULL)); + ut_assertok(create_children(uts, top[5], NODE_COUNT, 5, child)); + + /* And grandchildren */ + for (i = 0; i < NODE_COUNT; i++) + ut_assertok(create_children(uts, child[i], NODE_COUNT, 50 * i, + i == 2 ? grandchild : NULL)); + + /* Check total number of devices */ + total = NODE_COUNT * (3 + NODE_COUNT); + ut_asserteq(total, dm_testdrv_op_count[DM_TEST_OP_BIND]); + + /* Probe everything */ + for (i = 0; i < total; i++) + ut_assertok(uclass_get_device(UCLASS_TEST, i, &dev)); + + /* Re-parent top-level children with no grandchildren. */ + ut_assertok(device_reparent(top[3], top[0])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_reparent(top[4], top[0])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + /* Re-parent top-level children with grandchildren. */ + ut_assertok(device_reparent(top[2], top[0])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_reparent(top[5], top[2])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + /* Re-parent grandchildren. */ + ut_assertok(device_reparent(grandchild[0], top[1])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_reparent(grandchild[1], top[1])); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + /* Remove re-pareneted devices. */ + ut_assertok(device_remove(top[3], DM_REMOVE_NORMAL)); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_remove(top[4], DM_REMOVE_NORMAL)); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_remove(top[5], DM_REMOVE_NORMAL)); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_remove(top[2], DM_REMOVE_NORMAL)); + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_remove(grandchild[0], DM_REMOVE_NORMAL)); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + ut_assertok(device_remove(grandchild[1], DM_REMOVE_NORMAL)); + /* try to get devices */ + for (ret = uclass_find_first_device(UCLASS_TEST, &dev); + dev; + ret = uclass_find_next_device(&dev)) { + ut_assert(!ret); + ut_assertnonnull(dev); + } + + /* Try the same with unbind */ + ut_assertok(device_unbind(top[3])); + ut_assertok(device_unbind(top[4])); + ut_assertok(device_unbind(top[5])); + ut_assertok(device_unbind(top[2])); + + ut_assertok(device_unbind(grandchild[0])); + ut_assertok(device_unbind(grandchild[1])); + + return 0; +} +DM_TEST(dm_test_device_reparent, 0); + /* Test that pre-relocation devices work as expected */ static int dm_test_pre_reloc(struct unit_test_state *uts) { -- cgit v1.3.1 From 643966a8fa620b763ad2c20c4d328aaefa23901d Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Mon, 7 Sep 2020 17:46:37 +0300 Subject: clk: at91: add pre-requisite headers for AT91 clock architecture Add pre-requisite headers for AT91 clock architecture. These are based on already present files on Linux and will be used by following commits for AT91 CCF clock drivers. Signed-off-by: Claudiu Beznea --- include/dt-bindings/clk/at91.h | 22 ++++ include/linux/clk/at91_pmc.h | 247 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 269 insertions(+) create mode 100644 include/dt-bindings/clk/at91.h create mode 100644 include/linux/clk/at91_pmc.h (limited to 'include') diff --git a/include/dt-bindings/clk/at91.h b/include/dt-bindings/clk/at91.h new file mode 100644 index 00000000000..e30756b2804 --- /dev/null +++ b/include/dt-bindings/clk/at91.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * This header provides constants for AT91 pmc status. + * The constants defined in this header are being used in dts and PMC code. + * + * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries + * + * Author: Claudiu Beznea + * + * Based on include/dt-bindings/clock/at91.h on Linux. + */ + +#ifndef _DT_BINDINGS_CLK_AT91_H +#define _DT_BINDINGS_CLK_AT91_H + +#define PMC_TYPE_CORE 1 +#define PMC_TYPE_SYSTEM 2 +#define PMC_TYPE_PERIPHERAL 3 +#define PMC_TYPE_GCK 4 +#define PMC_TYPE_SLOW 5 + +#endif diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h new file mode 100644 index 00000000000..ee39e72e2b3 --- /dev/null +++ b/include/linux/clk/at91_pmc.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Power Management Controller (PMC) - System peripherals registers. + * + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) SAN People + * + * Based on AT91RM9200 datasheet revision E. + * Based on include/linux/clk/at91_pmc.h on Linux. + */ + +#ifndef AT91_PMC_H_ +#define AT91_PMC_H_ + +#define AT91_PMC_V1 (1) /* PMC version 1 */ +#define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */ + +#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ +#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ + +#define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ +#define AT91_PMC_PCK (1 << 0) /* Processor Clock */ +#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ +#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ +#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ +#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ +#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ +#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ +#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ +#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ + +#define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ +#define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */ +#define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ +#define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ + +#define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */ + +#define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ +#define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ +#define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ + +#define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ +#define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */ +#define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */ +#define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ +#define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ + +#define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ +#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ +#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ +#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ +#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ + +#define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ +#define AT91_PMC_PLL_UPDT_ID_MSK (0xf) +#define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ +#define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ +#define AT91_PMC_PLL_UPDT_STUPTIM(n) ((n) << 16) /* Startup time */ +#define AT91_PMC_PMM_UPDT_STUPTIM_MSK (0xff << 16) + +#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ +#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ +#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ +#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ +#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ +#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ +#define AT91_PMC_KEY_MASK (0xff << 16) +#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ +#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ +#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ + +#define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ +#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ +#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ + +#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ +#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ +#define AT91_PMC_DIV (0xff << 0) /* Divider */ +#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ +#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ +#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ +#define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) +#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ +#define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) +#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ +#define AT91_PMC_USBDIV_1 (0 << 28) +#define AT91_PMC_USBDIV_2 (1 << 28) +#define AT91_PMC_USBDIV_4 (2 << 28) +#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ + +#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ + +#define AT91_PMC_MCKR 0x30 /* Master Clock Register */ +#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ +#define AT91_PMC_CSS_SLOW (0 << 0) +#define AT91_PMC_CSS_MAIN (1 << 0) +#define AT91_PMC_CSS_PLLA (2 << 0) +#define AT91_PMC_CSS_PLLB (3 << 0) +#define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ +#define PMC_PRES_OFFSET 2 +#define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ +#define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) +#define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) +#define PMC_ALT_PRES_OFFSET 4 +#define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ +#define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) +#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ +#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ +#define AT91RM9200_PMC_MDIV_2 (1 << 8) +#define AT91RM9200_PMC_MDIV_3 (2 << 8) +#define AT91RM9200_PMC_MDIV_4 (3 << 8) +#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ +#define AT91SAM9_PMC_MDIV_2 (1 << 8) +#define AT91SAM9_PMC_MDIV_4 (2 << 8) +#define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ +#define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ +#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ +#define AT91_PMC_PDIV_1 (0 << 12) +#define AT91_PMC_PDIV_2 (1 << 12) +#define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ +#define AT91_PMC_PLLADIV2_OFF (0 << 12) +#define AT91_PMC_PLLADIV2_ON (1 << 12) +#define AT91_PMC_H32MXDIV BIT(24) + +#define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ + +#define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ +#define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ +#define AT91_PMC_USBS_PLLA (0 << 0) +#define AT91_PMC_USBS_UPLL (1 << 0) +#define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ +#define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ +#define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) +#define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) + +#define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ +#define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ +#define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ +#define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) + +#define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ +#define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ +#define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ +#define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ +#define AT91_PMC_CSSMCK_CSS (0 << 8) +#define AT91_PMC_CSSMCK_MCK (1 << 8) + +#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ +#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ +#define AT91_PMC_SR 0x68 /* Status Register */ +#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ +#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ +#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ +#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ +#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ +#define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ +#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ +#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ +#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ +#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ +#define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ +#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ +#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ +#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ +#define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ +#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ + +#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ +#define AT91_PMC_FSTT(n) BIT(n) +#define AT91_PMC_RTTAL BIT(16) +#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ +#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ +#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ +#define AT91_PMC_LPM BIT(20) /* Low-power Mode */ +#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ +#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ + +#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ + +#define AT91_PMC_FS_INPUT_MASK 0x7ff + +#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ + +#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ +#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ +#define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ +#define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ + +#define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ +#define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ +#define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ + +#define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */ + +#define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ +#define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ +#define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ + +#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ +#define AT91_PMC_PCR_PID_MASK 0x3f +#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ +#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) +#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ +#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ + +#define AT91_PMC_AUDIO_PLL0 0x14c +#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) +#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) +#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) +#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) +#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 +#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 +#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) + +#define AT91_PMC_AUDIO_PLL1 0x150 +#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff +#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 +#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) +#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) + +#endif -- cgit v1.3.1 From dc447b6b3fef1b145014519f607bb9722455bc16 Mon Sep 17 00:00:00 2001 From: Walter Lozano Date: Wed, 29 Jul 2020 13:17:31 -0300 Subject: core: improve of_match_ptr with OF_PLATDATA Currently of_match_ptr is used to avoid referencing compatible strings when OF_CONTROL is not enabled. This behaviour could be improved by taking into account also OF_PLATDATA, as when this configuration is enabled the compatible strings are not used at all. Signed-off-by: Walter Lozano Reviewed-by: Simon Glass --- include/dm/device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/dm/device.h b/include/dm/device.h index 953706cf525..ac3b6c1b8a0 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -197,7 +197,7 @@ struct udevice_id { ulong data; }; -#if CONFIG_IS_ENABLED(OF_CONTROL) +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) #define of_match_ptr(_ptr) (_ptr) #else #define of_match_ptr(_ptr) NULL -- cgit v1.3.1 From ccaa5747bdeae4261199dd7e80771e4de1c550ca Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Thu, 10 Sep 2020 10:49:59 +0200 Subject: fdtdec: optionally add property no-map to created reserved memory node Add boolean input argument @no_map to helper function fdtdec_add_reserved_memory() to add or not "no-map" property for an added reserved memory node. Property no-map is used by the Linux kernel to not not map memory in its static memory mapping. It is needed for example for the| consistency of system non-cached memory and to prevent speculative accesses to some firewalled memory. No functional change. A later change will update to OPTEE library to add no-map property to OP-TEE reserved memory nodes. Signed-off-by: Etienne Carriere Signed-off-by: Patrice Chotard Reviewed-by: Simon Glass --- arch/riscv/lib/fdt_fixup.c | 2 +- include/fdtdec.h | 5 +++-- lib/fdtdec.c | 10 ++++++++-- lib/optee/optee.c | 2 +- test/dm/fdtdec.c | 6 +++--- 5 files changed, 16 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 5b2420243fc..d02062fd5bd 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -75,7 +75,7 @@ int riscv_fdt_copy_resv_mem_node(const void *src, void *dst) pmp_mem.start = addr; pmp_mem.end = addr + size - 1; err = fdtdec_add_reserved_memory(dst, basename, &pmp_mem, - &phandle); + &phandle, false); if (err < 0 && err != -FDT_ERR_EXISTS) { log_err("failed to add reserved memory: %d\n", err); return err; diff --git a/include/fdtdec.h b/include/fdtdec.h index 152eb07b9e0..62d16609732 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -1029,7 +1029,7 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * }; * uint32_t phandle; * - * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle); + * fdtdec_add_reserved_memory(fdt, "framebuffer", &fb, &phandle, false); * * This results in the following subnode being added to the top-level * /reserved-memory node: @@ -1056,11 +1056,12 @@ static inline int fdtdec_set_phandle(void *blob, int node, uint32_t phandle) * @param carveout information about the carveout region * @param phandlep return location for the phandle of the carveout region * can be NULL if no phandle should be added + * @param no_map add "no-map" property if true * @return 0 on success or a negative error code on failure */ int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, - uint32_t *phandlep); + uint32_t *phandlep, bool no_map); /** * fdtdec_get_carveout() - reads a carveout from an FDT diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 56bf9fcc793..b8fc5e2bff0 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -1316,7 +1316,7 @@ static int fdtdec_init_reserved_memory(void *blob) int fdtdec_add_reserved_memory(void *blob, const char *basename, const struct fdt_memory *carveout, - uint32_t *phandlep) + uint32_t *phandlep, bool no_map) { fdt32_t cells[4] = {}, *ptr = cells; uint32_t upper, lower, phandle; @@ -1416,6 +1416,12 @@ int fdtdec_add_reserved_memory(void *blob, const char *basename, if (err < 0) return err; + if (no_map) { + err = fdt_setprop(blob, node, "no-map", NULL, 0); + if (err < 0) + return err; + } + /* return the phandle for the new node for the caller to use */ if (phandlep) *phandlep = phandle; @@ -1481,7 +1487,7 @@ int fdtdec_set_carveout(void *blob, const char *node, const char *prop_name, fdt32_t value; void *prop; - err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle); + err = fdtdec_add_reserved_memory(blob, name, carveout, &phandle, false); if (err < 0) { debug("failed to add reserved memory: %d\n", err); return err; diff --git a/lib/optee/optee.c b/lib/optee/optee.c index 457d4cca8a0..963c2ff4304 100644 --- a/lib/optee/optee.c +++ b/lib/optee/optee.c @@ -192,7 +192,7 @@ int optee_copy_fdt_nodes(const void *old_blob, void *new_blob) ret = fdtdec_add_reserved_memory(new_blob, nodename, &carveout, - NULL); + NULL, false); free(oldname); if (ret < 0) diff --git a/test/dm/fdtdec.c b/test/dm/fdtdec.c index 716993f706f..4119003041e 100644 --- a/test/dm/fdtdec.c +++ b/test/dm/fdtdec.c @@ -80,7 +80,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region", - &resv, &phandle)); + &resv, &phandle, false)); /* Test /reserve-memory and its subnode should exist */ parent = fdt_path_offset(blob, "/reserved-memory"); @@ -101,7 +101,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x2000; resv.end = 0x2fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region1", - &resv, &phandle1)); + &resv, &phandle1, false)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region1"); ut_assert(subnode > 0); @@ -115,7 +115,7 @@ static int dm_test_fdtdec_add_reserved_memory(struct unit_test_state *uts) resv.start = 0x1000; resv.end = 0x1fff; ut_assertok(fdtdec_add_reserved_memory(blob, "rsvd_region2", - &resv, &phandle1)); + &resv, &phandle1, false)); subnode = fdt_path_offset(blob, "/reserved-memory/rsvd_region2"); ut_assert(subnode < 0); -- cgit v1.3.1 From 01d89e3d12e07a1a1ee0f8528706441a84eee328 Mon Sep 17 00:00:00 2001 From: Patrick Delaunay Date: Thu, 10 Sep 2020 18:26:17 +0200 Subject: dm: add cells_count parameter in live DT APIs of_parse_phandle_with_args In the live tree API ofnode_parse_phandle_with_args, the cell_count argument must be used when cells_name is NULL. But this argument is not provided to the live DT function of_parse_phandle_with_args even it is provided to fdtdec_parse_phandle_with_args. This patch adds support of the cells_count parameter in dev_ and of_node API to allow migration and support of live DT: - of_parse_phandle_with_args Signed-off-by: Patrick Delaunay Reviewed-by: Simon Glass --- drivers/core/of_access.c | 7 ++++--- drivers/core/ofnode.c | 3 ++- include/dm/of_access.h | 4 +++- 3 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/core/of_access.c b/drivers/core/of_access.c index 922e78f99b8..bcf1644d050 100644 --- a/drivers/core/of_access.c +++ b/drivers/core/of_access.c @@ -745,13 +745,14 @@ struct device_node *of_parse_phandle(const struct device_node *np, int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, - int index, struct of_phandle_args *out_args) + int cell_count, int index, + struct of_phandle_args *out_args) { if (index < 0) return -EINVAL; - return __of_parse_phandle_with_args(np, list_name, cells_name, 0, - index, out_args); + return __of_parse_phandle_with_args(np, list_name, cells_name, + cell_count, index, out_args); } int of_count_phandle_with_args(const struct device_node *np, diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c index d02d8d33fef..79fcdf5ce21 100644 --- a/drivers/core/ofnode.c +++ b/drivers/core/ofnode.c @@ -409,7 +409,8 @@ int ofnode_parse_phandle_with_args(ofnode node, const char *list_name, int ret; ret = of_parse_phandle_with_args(ofnode_to_np(node), - list_name, cells_name, index, + list_name, cells_name, + cell_count, index, &args); if (ret) return ret; diff --git a/include/dm/of_access.h b/include/dm/of_access.h index f95a00d0655..2fa65c9332e 100644 --- a/include/dm/of_access.h +++ b/include/dm/of_access.h @@ -407,6 +407,7 @@ struct device_node *of_parse_phandle(const struct device_node *np, * @np: pointer to a device tree node containing a list * @list_name: property name that contains a list * @cells_name: property name that specifies phandles' arguments count + * @cells_count: Cell count to use if @cells_name is NULL * @index: index of a phandle to parse out * @out_args: optional pointer to output arguments structure (will be filled) * @return 0 on success (with @out_args filled out if not NULL), -ENOENT if @@ -440,7 +441,8 @@ struct device_node *of_parse_phandle(const struct device_node *np, */ int of_parse_phandle_with_args(const struct device_node *np, const char *list_name, const char *cells_name, - int index, struct of_phandle_args *out_args); + int cells_count, int index, + struct of_phandle_args *out_args); /** * of_count_phandle_with_args() - Count the number of phandle in a list -- cgit v1.3.1 From abe450322e9eb8b42ab7f8fa4f86cea0c6b476cc Mon Sep 17 00:00:00 2001 From: Harini Katakam Date: Tue, 8 Sep 2020 15:22:36 +0530 Subject: include: dt-bindings: Add MSCC header Add MSCC header with delay definitions for VSC8531 and associated family devices. Signed-off-by: Harini Katakam Signed-off-by: Michal Simek --- include/dt-bindings/net/mscc-phy-vsc8531.h | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 include/dt-bindings/net/mscc-phy-vsc8531.h (limited to 'include') diff --git a/include/dt-bindings/net/mscc-phy-vsc8531.h b/include/dt-bindings/net/mscc-phy-vsc8531.h new file mode 100644 index 00000000000..61f5287d752 --- /dev/null +++ b/include/dt-bindings/net/mscc-phy-vsc8531.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Device Tree constants for Microsemi VSC8531 PHY + * + * Author: Nagaraju Lakkaraju + * + * Copyright (c) 2017 Microsemi Corporation + */ + +#ifndef _DT_BINDINGS_MSCC_VSC8531_H +#define _DT_BINDINGS_MSCC_VSC8531_H + +/* PHY LED Modes */ +#define VSC8531_LINK_ACTIVITY 0 +#define VSC8531_LINK_1000_ACTIVITY 1 +#define VSC8531_LINK_100_ACTIVITY 2 +#define VSC8531_LINK_10_ACTIVITY 3 +#define VSC8531_LINK_100_1000_ACTIVITY 4 +#define VSC8531_LINK_10_1000_ACTIVITY 5 +#define VSC8531_LINK_10_100_ACTIVITY 6 +#define VSC8584_LINK_100FX_1000X_ACTIVITY 7 +#define VSC8531_DUPLEX_COLLISION 8 +#define VSC8531_COLLISION 9 +#define VSC8531_ACTIVITY 10 +#define VSC8584_100FX_1000X_ACTIVITY 11 +#define VSC8531_AUTONEG_FAULT 12 +#define VSC8531_SERIAL_MODE 13 +#define VSC8531_FORCE_LED_OFF 14 +#define VSC8531_FORCE_LED_ON 15 + +#define VSC8531_RGMII_CLK_DELAY_0_2_NS 0 +#define VSC8531_RGMII_CLK_DELAY_0_8_NS 1 +#define VSC8531_RGMII_CLK_DELAY_1_1_NS 2 +#define VSC8531_RGMII_CLK_DELAY_1_7_NS 3 +#define VSC8531_RGMII_CLK_DELAY_2_0_NS 4 +#define VSC8531_RGMII_CLK_DELAY_2_3_NS 5 +#define VSC8531_RGMII_CLK_DELAY_2_6_NS 6 +#define VSC8531_RGMII_CLK_DELAY_3_4_NS 7 + +#endif -- cgit v1.3.1 From b7d4518eed716a483b4efa1e282033f37244ab2d Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Sep 2020 13:25:40 +0200 Subject: fpga: zynqmp: Get rid of ZYNQMP_SIP_SVC* macros There is no need to use these macros because enum pm_api_id can be used instead. Signed-off-by: Michal Simek --- drivers/fpga/zynqmppl.c | 8 ++++---- include/zynqmppl.h | 3 --- 2 files changed, 4 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/fpga/zynqmppl.c b/drivers/fpga/zynqmppl.c index 5b103cfeaf1..03878d32ec1 100644 --- a/drivers/fpga/zynqmppl.c +++ b/drivers/fpga/zynqmppl.c @@ -231,11 +231,11 @@ static int zynqmp_load(xilinx_desc *desc, const void *buf, size_t bsize, buf_hi = upper_32_bits(bin_buf); if (xilfpga_old) - ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, (u32)(uintptr_t)bsizeptr, bstype, ret_payload); else - ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, (u32)bsize, 0, ret_payload); if (ret) @@ -277,7 +277,7 @@ static int zynqmp_loads(xilinx_desc *desc, const void *buf, size_t bsize, buf_lo = lower_32_bits((ulong)buf); buf_hi = upper_32_bits((ulong)buf); - ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_LOAD, buf_lo, + ret = xilinx_pm_request(PM_FPGA_LOAD, buf_lo, buf_hi, (u32)(uintptr_t)fpga_sec_info->userkey_addr, flag, ret_payload); @@ -295,7 +295,7 @@ static int zynqmp_pcap_info(xilinx_desc *desc) int ret; u32 ret_payload[PAYLOAD_ARG_CNT]; - ret = xilinx_pm_request(ZYNQMP_SIP_SVC_PM_FPGA_STATUS, 0, 0, 0, + ret = xilinx_pm_request(PM_FPGA_GET_STATUS, 0, 0, 0, 0, ret_payload); if (!ret) printf("PCAP status\t0x%x\n", ret_payload[1]); diff --git a/include/zynqmppl.h b/include/zynqmppl.h index a0a52ec4c1d..35cfe17d444 100644 --- a/include/zynqmppl.h +++ b/include/zynqmppl.h @@ -10,9 +10,6 @@ #include #include -#define ZYNQMP_SIP_SVC_CSU_DMA_CHIPID 0xC2000018 -#define ZYNQMP_SIP_SVC_PM_FPGA_LOAD 0xC2000016 -#define ZYNQMP_SIP_SVC_PM_FPGA_STATUS 0xC2000017 #define ZYNQMP_FPGA_OP_INIT (1 << 0) #define ZYNQMP_FPGA_OP_LOAD (1 << 1) #define ZYNQMP_FPGA_OP_DONE (1 << 2) -- cgit v1.3.1 From 29bd8ada52e186ea6b7f8b633d7aa6296fb097d1 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 9 Sep 2020 14:41:56 +0200 Subject: fpga: kconfig: Rename SPL_FPGA_SUPPORT to SPL_FPGA The patch does sed 's/SPL_FPGA_SUPPORT/SPL_FPGA/g' but also fixing Makefile and zynqmp.c to simplify if/endif logic in zynqmp.c. This change is mostly done to be able to use CONFIG_IS_ENABLED macro and obj-$(CONFIG_$(SPL_)FPGA) in Makefile. For them symbols need to be in sync. And removing one line from Topic Miami boards which is not needed because symbol is not enabled via Kconfig. Signed-off-by: Michal Simek Reviewed-by: Simon Glass --- arch/arm/mach-zynq/cpu.c | 6 ++---- arch/arm/mach-zynq/spl.c | 2 +- board/xilinx/zynqmp/zynqmp.c | 9 ++------- common/spl/Kconfig | 2 +- common/spl/spl_fit.c | 4 ++-- configs/socfpga_arria10_defconfig | 2 +- configs/xilinx_zynq_virt_defconfig | 2 +- drivers/Makefile | 3 +-- include/configs/topic_miami.h | 1 - 9 files changed, 11 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index 77b7cb13071..3befc120289 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -17,8 +17,7 @@ #define ZYNQ_SILICON_VER_MASK 0xF0000000 #define ZYNQ_SILICON_VER_SHIFT 28 -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(FPGA) xilinx_desc fpga = { .family = xilinx_zynq, .iface = devcfg, @@ -111,8 +110,7 @@ static int __maybe_unused cpu_desc_id(void) #if defined(CONFIG_ARCH_EARLY_INIT_R) int arch_early_init_r(void) { -#if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \ - (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(FPGA) int cpu_id = cpu_desc_id(); if (cpu_id < 0) diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index 239ce3436a6..cb8cfd2f353 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -34,7 +34,7 @@ void board_init_f(ulong dummy) void spl_board_init(void) { preloader_console_init(); -#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA_SUPPORT) +#if defined(CONFIG_ARCH_EARLY_INIT_R) && defined(CONFIG_SPL_FPGA) arch_early_init_r(); #endif board_init(); diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index e95d13a14cd..30f757627f4 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -49,10 +49,7 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ - !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ - defined(CONFIG_SPL_BUILD)) - +#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC; enum { @@ -331,9 +328,7 @@ int board_init(void) /* Bug in ROM sets wrong value in this register */ writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG); -#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) && \ - !defined(CONFIG_SPL_BUILD) || (defined(CONFIG_SPL_FPGA_SUPPORT) && \ - defined(CONFIG_SPL_BUILD)) +#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL) zynqmppl.name = zynqmp_get_silicon_idcode_name(); printf("Chip ID:\t%s\n", zynqmppl.name); fpga_init(); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index af8255a8d6a..6e31d756296 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -602,7 +602,7 @@ config SPL_FAT_WRITE Support for the underlying block device (e.g. MMC or USB) must be enabled separately. -config SPL_FPGA_SUPPORT +config SPL_FPGA bool "Support FPGAs" help Enable support for FPGAs in SPL. Field-programmable Gate Arrays diff --git a/common/spl/spl_fit.c b/common/spl/spl_fit.c index a8bfd388b10..0e27ad1d6a5 100644 --- a/common/spl/spl_fit.c +++ b/common/spl/spl_fit.c @@ -253,7 +253,7 @@ static int spl_load_fit_image(struct spl_load_info *info, ulong sector, const void *data; bool external_data = false; - if (IS_ENABLED(CONFIG_SPL_FPGA_SUPPORT) || + if (IS_ENABLED(CONFIG_SPL_FPGA) || (IS_ENABLED(CONFIG_SPL_OS_BOOT) && IS_ENABLED(CONFIG_SPL_GZIP))) { if (fit_image_get_type(fit, node, &type)) puts("Cannot get image type.\n"); @@ -546,7 +546,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image, return -1; } -#ifdef CONFIG_SPL_FPGA_SUPPORT +#ifdef CONFIG_SPL_FPGA node = spl_fit_get_image_node(fit, images, "fpga", 0); if (node >= 0) { /* Load the image and set up the spl_image structure */ diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 8fdd21c0d37..5d6fe4f35ab 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -23,7 +23,7 @@ CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_FPGA=y CONFIG_CMD_ASKENV=y CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig index 8acdab25b70..b1279452970 100644 --- a/configs/xilinx_zynq_virt_defconfig +++ b/configs/xilinx_zynq_virt_defconfig @@ -20,7 +20,7 @@ CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000 CONFIG_LEGACY_IMAGE_FORMAT=y CONFIG_USE_PREBOOT=y CONFIG_SPL_STACK_R=y -CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_SPI_LOAD=y # CONFIG_BOOTM_NETBSD is not set diff --git a/drivers/Makefile b/drivers/Makefile index 33126b2da7b..9eb51453e57 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ obj-$(CONFIG_$(SPL_TPL_)ACPI_PMC) += power/acpi_pmc/ obj-$(CONFIG_$(SPL_)BOARD) += board/ obj-$(CONFIG_XEN) += xen/ +obj-$(CONFIG_$(SPL_)FPGA) += fpga/ ifndef CONFIG_TPL_BUILD ifdef CONFIG_SPL_BUILD @@ -60,7 +61,6 @@ obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += usb/host/ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/ obj-$(CONFIG_SPL_SATA_SUPPORT) += ata/ scsi/ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += block/ -obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/ obj-$(CONFIG_SPL_THERMAL) += thermal/ endif @@ -85,7 +85,6 @@ obj-y += cache/ obj-$(CONFIG_CPU) += cpu/ obj-y += crypto/ obj-$(CONFIG_FASTBOOT) += fastboot/ -obj-$(CONFIG_FPGA) += fpga/ obj-y += misc/ obj-$(CONFIG_MMC) += mmc/ obj-$(CONFIG_NVME) += nvme/ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h index 6e3953835d1..010d28ac86f 100644 --- a/include/configs/topic_miami.h +++ b/include/configs/topic_miami.h @@ -24,7 +24,6 @@ /* No falcon support */ #undef CONFIG_SPL_OS_BOOT -#undef CONFIG_SPL_FPGA_SUPPORT /* FPGA commands that we don't use */ -- cgit v1.3.1 From a2c87cb82ac7b09bc48650d84330aa76941839dd Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Wed, 16 Sep 2020 10:14:01 +0200 Subject: xilinx: versal: Fix compilation error when !CONFIG_NET PXE and DHCP shouldn't be listed when commands are not enabled that's why handle it in the same way as is done for Zynq and ZynqMP. Fixes: ec48b6c991f4 ("arm64: versal: Add support for new Xilinx Versal ACAPs") Signed-off-by: Michal Simek --- include/configs/xilinx_versal.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h index d7255a05dff..8b416327b57 100644 --- a/include/configs/xilinx_versal.h +++ b/include/configs/xilinx_versal.h @@ -94,6 +94,18 @@ # define BOOT_TARGET_DEVICES_MMC(func) #endif +#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) +#else +# define BOOT_TARGET_DEVICES_PXE(func) +#endif + +#if defined(CONFIG_CMD_DHCP) +# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) +#else +# define BOOT_TARGET_DEVICES_DHCP(func) +#endif + #if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) # define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) #else @@ -135,8 +147,8 @@ BOOT_TARGET_DEVICES_MMC(func) \ BOOT_TARGET_DEVICES_XSPI(func) \ BOOT_TARGET_DEVICES_DFU_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) + BOOT_TARGET_DEVICES_PXE(func) \ + BOOT_TARGET_DEVICES_DHCP(func) #include -- cgit v1.3.1 From 16c53ce7129b9362a801ffaf1abd496ffb7a5ef5 Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 16 Jul 2020 18:09:11 +0800 Subject: net: fsl_mdio: Correct the MII management register block address The MII management register block offset is different between gianfar and etsec2 compatible devices, this patch is to fix this issue by adding driver data for different compatible string. Fixes: 2932c5a802a9 ("net: tsec: fsl_mdio: add DM MDIO support") Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- drivers/net/fsl_mdio.c | 28 ++++++++++++++++++++++------ include/fsl_mdio.h | 4 ++++ 2 files changed, 26 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/net/fsl_mdio.c b/drivers/net/fsl_mdio.c index ae96ce4c7bf..77f1a96a2eb 100644 --- a/drivers/net/fsl_mdio.c +++ b/drivers/net/fsl_mdio.c @@ -11,6 +11,7 @@ #include #include #include +#include #ifdef CONFIG_DM_MDIO struct tsec_mdio_priv { @@ -190,17 +191,30 @@ static const struct mdio_ops tsec_mdio_ops = { .reset = tsec_mdio_reset, }; +static struct fsl_pq_mdio_data etsec2_data = { + .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, +}; + +static struct fsl_pq_mdio_data gianfar_data = { + .mdio_regs_off = 0x0, +}; + +static struct fsl_pq_mdio_data fman_data = { + .mdio_regs_off = 0x0, +}; + static const struct udevice_id tsec_mdio_ids[] = { - { .compatible = "fsl,gianfar-tbi" }, - { .compatible = "fsl,gianfar-mdio" }, - { .compatible = "fsl,etsec2-tbi" }, - { .compatible = "fsl,etsec2-mdio" }, - { .compatible = "fsl,fman-mdio" }, + { .compatible = "fsl,gianfar-tbi", .data = (ulong)&gianfar_data }, + { .compatible = "fsl,gianfar-mdio", .data = (ulong)&gianfar_data }, + { .compatible = "fsl,etsec2-tbi", .data = (ulong)&etsec2_data }, + { .compatible = "fsl,etsec2-mdio", .data = (ulong)&etsec2_data }, + { .compatible = "fsl,fman-mdio", .data = (ulong)&fman_data }, {} }; static int tsec_mdio_probe(struct udevice *dev) { + struct fsl_pq_mdio_data *data; struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL; struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) : NULL; @@ -213,7 +227,9 @@ static int tsec_mdio_probe(struct udevice *dev) printf("dev_get_priv(dev %p) = NULL\n", dev); return -1; } - priv->regs = dev_remap_addr(dev); + + data = (struct fsl_pq_mdio_data *)dev_get_driver_data(dev); + priv->regs = dev_remap_addr(dev) + data->mdio_regs_off; debug("%s priv %p @ regs %p, pdata %p\n", __func__, priv, priv->regs, pdata); diff --git a/include/fsl_mdio.h b/include/fsl_mdio.h index 41cb73717bc..b6c02cf342d 100644 --- a/include/fsl_mdio.h +++ b/include/fsl_mdio.h @@ -55,6 +55,10 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr, int regnum); int memac_mdio_reset(struct mii_dev *bus); +struct fsl_pq_mdio_data { + u32 mdio_regs_off; +}; + struct fsl_pq_mdio_info { struct tsec_mii_mng __iomem *regs; char *name; -- cgit v1.3.1 From 7fb568de53cd0276c3e616a9cbf942b71007ed4b Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 16 Jul 2020 18:09:14 +0800 Subject: net: tsec: Add the compatible string "gianfar" support Add compatible string "gianfar" support and update the device-tree-bindings doc. Signed-off-by: Hou Zhiqiang Reviewed-by: Vladimir Oltean Reviewed-by: Priyanka Jain --- doc/device-tree-bindings/net/fsl-tsec-phy.txt | 2 +- drivers/net/tsec.c | 16 ++++++++++++++-- include/tsec.h | 4 ++++ 3 files changed, 19 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/doc/device-tree-bindings/net/fsl-tsec-phy.txt b/doc/device-tree-bindings/net/fsl-tsec-phy.txt index 8e8574bc97f..a44c5fd9d9c 100644 --- a/doc/device-tree-bindings/net/fsl-tsec-phy.txt +++ b/doc/device-tree-bindings/net/fsl-tsec-phy.txt @@ -2,7 +2,7 @@ Properties: - - compatible : Should be "fsl,etsec2" + - compatible : Should be "fsl,etsec2" or "gianfar" - reg : Offset and length of the register set for the device - phy-handle : See ethernet.txt file in the same directory. - phy-connection-type : See ethernet.txt file in the same directory. This diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index af0d27a8e33..c436b8317d9 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -803,11 +803,14 @@ int tsec_probe(struct udevice *dev) struct tsec_private *priv = dev_get_priv(dev); struct ofnode_phandle_args phandle_args; u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; + struct tsec_data *data; const char *phy_mode; fdt_addr_t reg; ofnode parent; int ret; + data = (struct tsec_data *)dev_get_driver_data(dev); + pdata->iobase = (phys_addr_t)dev_read_addr(dev); priv->regs = dev_remap_addr(dev); @@ -828,7 +831,7 @@ int tsec_probe(struct udevice *dev) return -ENOENT; } - priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, + priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off, 0, MAP_NOCACHE); } @@ -880,8 +883,17 @@ static const struct eth_ops tsec_ops = { .mcast = tsec_mcast_addr, }; +static struct tsec_data etsec2_data = { + .mdio_regs_off = TSEC_MDIO_REGS_OFFSET, +}; + +static struct tsec_data gianfar_data = { + .mdio_regs_off = 0x0, +}; + static const struct udevice_id tsec_ids[] = { - { .compatible = "fsl,etsec2" }, + { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data }, + { .compatible = "gianfar", .data = (ulong)&gianfar_data }, { } }; diff --git a/include/tsec.h b/include/tsec.h index 43255e538f7..5433cfd9661 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -394,6 +394,10 @@ struct tsec { #define TX_BUF_CNT 2 +struct tsec_data { + u32 mdio_regs_off; +}; + struct tsec_private { struct txbd8 __iomem txbd[TX_BUF_CNT]; struct rxbd8 __iomem rxbd[PKTBUFSRX]; -- cgit v1.3.1 From 993c104dbea27e4ea7227bbef10e95e79df5909e Mon Sep 17 00:00:00 2001 From: Hou Zhiqiang Date: Thu, 16 Jul 2020 18:09:17 +0800 Subject: configs: p1_p2_rdb: Add the default address of vsc7385 firmware Add the environment 'vscfw_addr' to assign a default address for vsc7385 firmware uploading. Signed-off-by: Hou Zhiqiang Reviewed-by: Priyanka Jain --- include/configs/p1_p2_rdb_pc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 1b74177b2f2..a159285c981 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -451,6 +451,7 @@ /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET +#define __VSCFW_ADDR "vscfw_addr=ef000000" #define CONFIG_SYS_VSC7385_BASE 0xffb00000 #ifdef CONFIG_PHYS_64BIT @@ -809,6 +810,7 @@ i2c mw 18 3 __SW_BOOT_MASK 1; reset "ramdisk_size=120000\0" \ "map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \ "map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \ +__stringify(__VSCFW_ADDR)"\0" \ __stringify(__NOR_RST_CMD)"\0" \ __stringify(__SPI_RST_CMD)"\0" \ __stringify(__SD_RST_CMD)"\0" \ -- cgit v1.3.1 From 20b1ae018fc9e7587507a840f0c4a1cef109e9e7 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 11:56:35 +0530 Subject: board/freescale: Remove p1023rdb board support Remove NXP powerpc p1023rdb board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 8 - board/freescale/p1023rdb/Kconfig | 12 -- board/freescale/p1023rdb/MAINTAINERS | 6 - board/freescale/p1023rdb/Makefile | 8 - board/freescale/p1023rdb/ddr.c | 85 --------- board/freescale/p1023rdb/law.c | 17 -- board/freescale/p1023rdb/p1023rdb.c | 160 ----------------- board/freescale/p1023rdb/tlb.c | 98 ---------- configs/P1023RDB_defconfig | 50 ------ include/configs/P1023RDB.h | 338 ----------------------------------- 10 files changed, 782 deletions(-) delete mode 100644 board/freescale/p1023rdb/Kconfig delete mode 100644 board/freescale/p1023rdb/MAINTAINERS delete mode 100644 board/freescale/p1023rdb/Makefile delete mode 100644 board/freescale/p1023rdb/ddr.c delete mode 100644 board/freescale/p1023rdb/law.c delete mode 100644 board/freescale/p1023rdb/p1023rdb.c delete mode 100644 board/freescale/p1023rdb/tlb.c delete mode 100644 configs/P1023RDB_defconfig delete mode 100644 include/configs/P1023RDB.h (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 753d0750b2b..0707beebf8f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,13 +109,6 @@ config TARGET_P1010RDB_PB imply CMD_SATA imply PANIC_HANG -config TARGET_P1023RDB - bool "Support P1023RDB" - select ARCH_P1023 - select FSL_DDR_INTERACTIVE - imply CMD_EEPROM - imply PANIC_HANG - config TARGET_P1020MBG bool "Support P1020MBG-PC" select SUPPORT_SPL @@ -1506,7 +1499,6 @@ source "board/freescale/mpc8568mds/Kconfig" source "board/freescale/mpc8569mds/Kconfig" source "board/freescale/mpc8572ds/Kconfig" source "board/freescale/p1010rdb/Kconfig" -source "board/freescale/p1023rdb/Kconfig" source "board/freescale/p1_p2_rdb_pc/Kconfig" source "board/freescale/p2041rdb/Kconfig" source "board/freescale/qemu-ppce500/Kconfig" diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig deleted file mode 100644 index 1e4cd10c6c7..00000000000 --- a/board/freescale/p1023rdb/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_P1023RDB - -config SYS_BOARD - default "p1023rdb" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P1023RDB" - -endif diff --git a/board/freescale/p1023rdb/MAINTAINERS b/board/freescale/p1023rdb/MAINTAINERS deleted file mode 100644 index c06bac6d0d8..00000000000 --- a/board/freescale/p1023rdb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -P1023RDB BOARD -#M: - -S: Maintained -F: board/freescale/p1023rdb/ -F: include/configs/P1023RDB.h -F: configs/P1023RDB_defconfig diff --git a/board/freescale/p1023rdb/Makefile b/board/freescale/p1023rdb/Makefile deleted file mode 100644 index 78dc5d595a2..00000000000 --- a/board/freescale/p1023rdb/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2013 Freescale Semiconductor, Inc. - -obj-y += p1023rdb.o -obj-y += ddr.o -obj-y += law.o -obj-y += tlb.o diff --git a/board/freescale/p1023rdb/ddr.c b/board/freescale/p1023rdb/ddr.c deleted file mode 100644 index dc7a909e03b..00000000000 --- a/board/freescale/p1023rdb/ddr.c +++ /dev/null @@ -1,85 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* CONFIG_SYS_DDR_RAW_TIMING */ -/* - * Hynix H5TQ1G83TFR-H9C - */ -dimm_params_t ddr_raw_timing = { - .n_ranks = 1, - .rank_density = 536870912u, - .capacity = 536870912u, - .primary_sdram_width = 32, - .ec_sdram_width = 0, - .registered_dimm = 0, - .mirrored_dimm = 0, - .n_row_addr = 14, - .n_col_addr = 10, - .n_banks_per_sdram_device = 8, - .edc_config = 0, - .burst_lengths_bitmask = 0x0c, - - .tckmin_x_ps = 1875, - .caslat_x = 0x1e << 4, /* 5,6,7,8 */ - .taa_ps = 13125, - .twr_ps = 18000, - .trcd_ps = 13125, - .trrd_ps = 7500, - .trp_ps = 13125, - .tras_ps = 37500, - .trc_ps = 50625, - .trfc_ps = 160000, - .twtr_ps = 7500, - .trtp_ps = 7500, - .refresh_rate_ps = 7800000, - .tfaw_ps = 37500, -}; - -int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, - unsigned int controller_number, - unsigned int dimm_number) -{ - const char dimm_model[] = "Fixed DDR on board"; - - if ((controller_number == 0) && (dimm_number == 0)) { - memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); - memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); - memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); - } - - return 0; -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - int i; - popts->clk_adjust = 6; - popts->cpo_override = 0x1f; - popts->write_data_delay = 2; - popts->half_strength_driver_enable = 1; - /* Write leveling override */ - popts->wrlvl_en = 1; - popts->wrlvl_override = 1; - popts->wrlvl_sample = 0xf; - popts->wrlvl_start = 0x8; - popts->trwt_override = 1; - popts->trwt = 0; - - for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { - popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; - popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; - } -} diff --git a/board/freescale/p1023rdb/law.c b/board/freescale/p1023rdb/law.c deleted file mode 100644 index 405fcd7b490..00000000000 --- a/board/freescale/p1023rdb/law.c +++ /dev/null @@ -1,17 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include -#include - -struct law_entry law_table[] = { - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_4M, - LAW_TRGT_IF_DPAA_SWP_SRAM), - SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p1023rdb/p1023rdb.c b/board/freescale/p1023rdb/p1023rdb.c deleted file mode 100644 index b70ff6899a2..00000000000 --- a/board/freescale/p1023rdb/p1023rdb.c +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - /* Set ABSWP to implement conversion of addresses in the LBC */ - setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - - return 0; -} - -int checkboard(void) -{ - printf("Board: P1023 RDB\n"); - - return 0; -} - -#ifdef CONFIG_PCI -void pci_init_board(void) -{ - fsl_pcie_init_board(0); -} -#endif - -int board_early_init_r(void) -{ - const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; - int flash_esel = find_tlb_idx((void *)flashbase, 1); - - /* - * Remap Boot flash + PROMJET region to caching-inhibited - * so that flash can be erased properly. - */ - - /* Flush d-cache and invalidate i-cache of any FLASH data */ - flush_dcache(); - invalidate_icache(); - - if (flash_esel == -1) { - /* very unlikely unless something is messed up */ - puts("Error: Could not find TLB for FLASH BASE\n"); - flash_esel = 2; /* give our best effort to continue */ - } else { - /* invalidate existing TLB entry for flash + promjet */ - disable_tlb(flash_esel); - } - - set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, flash_esel, BOOKE_PAGESZ_256M, 1); - - setup_qbman_portals(); - - return 0; -} - -unsigned long get_board_sys_clk(ulong dummy) -{ - return gd->bus_clk; -} - -unsigned long get_board_ddr_clk(ulong dummy) -{ - return gd->mem_clk; -} - -int board_eth_init(struct bd_info *bis) -{ - ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; - struct fsl_pq_mdio_info dtsec_mdio_info; - - /* - * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting - * is not correct. - */ - setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); - - dtsec_mdio_info.regs = - (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; - dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; - - /* Register the 1G MDIO bus */ - fsl_pq_mdio_init(bis, &dtsec_mdio_info); - - fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); - fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); - - fm_info_set_mdio(FM1_DTSEC1, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - fm_info_set_mdio(FM1_DTSEC2, - miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); - -#ifdef CONFIG_FMAN_ENET - cpu_eth_init(bis); -#endif - - return pci_eth_init(bis); -} - -#if defined(CONFIG_OF_BOARD_SETUP) -int ft_board_setup(void *blob, struct bd_info *bd) -{ - phys_addr_t base; - phys_size_t size; - - ft_cpu_setup(blob, bd); - - base = env_get_bootm_low(); - size = env_get_bootm_size(); - - fdt_fixup_memory(blob, (u64)base, (u64)size); - -#ifdef CONFIG_HAS_FSL_DR_USB - fsl_fdt_fixup_dr_usb(blob, bd); -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#ifndef CONFIG_DM_ETH - fdt_fixup_fman_ethernet(blob); -#endif -#endif - return 0; -} -#endif diff --git a/board/freescale/p1023rdb/tlb.c b/board/freescale/p1023rdb/tlb.c deleted file mode 100644 index 9f0314d190f..00000000000 --- a/board/freescale/p1023rdb/tlb.c +++ /dev/null @@ -1,98 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#include -#include - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* TLB 1 */ - /* *I*** - Covers boot page */ - SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, - 0, 0, BOOKE_PAGESZ_4K, 1), - - /* *I*G* - CCSRBAR */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_4M, 1), - - /* W**G* - Flash, localbus */ - /* This will be changed to *I*G* after relocation to RAM. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_1G, 1), - - /* *I*G* - PCI */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, - CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), - - /* *I*G* - PCI I/O */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_256K, 1), - - /* Bman/Qman */ - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, - MAS3_SW|MAS3_SR, MAS2_M, - 0, 9, BOOKE_PAGESZ_1M, 1), - SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, - CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 10, BOOKE_PAGESZ_1M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, - MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 11, BOOKE_PAGESZ_16K, 1), - -#ifdef CONFIG_SYS_RAMBOOT - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, - CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 12, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, - 0, 13, BOOKE_PAGESZ_256M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/configs/P1023RDB_defconfig b/configs/P1023RDB_defconfig deleted file mode 100644 index a8bb5767b78..00000000000 --- a/configs/P1023RDB_defconfig +++ /dev/null @@ -1,50 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1023RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=-1 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_REGINFO=y -CONFIG_CMD_IMLS=y -# CONFIG_CMD_EEPROM is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -# CONFIG_MMC is not set -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_PHYLIB=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h deleted file mode 100644 index 5c29a4f274e..00000000000 --- a/include/configs/P1023RDB.h +++ /dev/null @@ -1,338 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Authors: Roy Zang - * Chunhe Lan - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* High Level Configuration Options */ - -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_HWCONFIG - -#define CONFIG_ENABLE_36BIT_PHYS - -/* Implement conversion of addresses in the LBC */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SYS_DDR_RAW_TIMING - -/* - * Memory map - * - * 0x0000_0000 0x1fff_ffff DDR 512M cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable - * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 - * - * Localbus non-cacheable - * - * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ - -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 - -/* For FM */ -#define CONFIG_SYS_DPAA_FMAN - -/* Default address of microcode for the Linux Fman driver */ -/* QE microcode/firmware address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off $ubootaddr +$filesize; " \ - "erase $ubootaddr +$filesize; " \ - "cp.b $loadaddr $ubootaddr $filesize; " \ - "protect on $ubootaddr +$filesize; " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p1023rdb.dtb\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From d521cece5adb198fdc3f3f0d4ae9c4ca657f8952 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 15:35:16 +0530 Subject: board/freescale: Remove P1025RDB board support Remove NXP powerpc P1025RDB board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 ---- board/freescale/p1_p2_rdb_pc/Kconfig | 1 - board/freescale/p1_p2_rdb_pc/MAINTAINERS | 5 -- board/freescale/p1_p2_rdb_pc/README | 1 - board/freescale/p1_p2_rdb_pc/ddr.c | 3 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 43 ++------------- configs/P1025RDB_36BIT_defconfig | 65 ----------------------- configs/P1025RDB_NAND_defconfig | 81 ----------------------------- configs/P1025RDB_SDCARD_defconfig | 74 -------------------------- configs/P1025RDB_SPIFLASH_defconfig | 77 --------------------------- configs/P1025RDB_defconfig | 63 ---------------------- include/configs/p1_p2_rdb_pc.h | 51 ------------------ 12 files changed, 4 insertions(+), 469 deletions(-) delete mode 100644 configs/P1025RDB_36BIT_defconfig delete mode 100644 configs/P1025RDB_NAND_defconfig delete mode 100644 configs/P1025RDB_SDCARD_defconfig delete mode 100644 configs/P1025RDB_SPIFLASH_defconfig delete mode 100644 configs/P1025RDB_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 0707beebf8f..eade333ef4c 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -163,15 +163,6 @@ config TARGET_P1024RDB imply CMD_SATA imply PANIC_HANG -config TARGET_P1025RDB - bool "Support P1025RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1025 - imply CMD_EEPROM - imply CMD_SATA - imply SATA_SIL - config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index 2f9640b67c5..8797b41e2ab 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -4,7 +4,6 @@ if TARGET_P1020MBG || \ TARGET_P1020UTM || \ TARGET_P1021RDB || \ TARGET_P1024RDB || \ - TARGET_P1025RDB || \ TARGET_P2020RDB config SYS_BOARD diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index c2e924798e3..b57af344c78 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -36,11 +36,6 @@ F: configs/P1024RDB_36BIT_defconfig F: configs/P1024RDB_NAND_defconfig F: configs/P1024RDB_SDCARD_defconfig F: configs/P1024RDB_SPIFLASH_defconfig -F: configs/P1025RDB_defconfig -F: configs/P1025RDB_36BIT_defconfig -F: configs/P1025RDB_NAND_defconfig -F: configs/P1025RDB_SDCARD_defconfig -F: configs/P1025RDB_SPIFLASH_defconfig F: configs/P2020RDB-PC_defconfig F: configs/P2020RDB-PC_36BIT_defconfig F: configs/P2020RDB-PC_36BIT_NAND_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index b85cf0209eb..adc273eb325 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -7,7 +7,6 @@ P1_P2_RDB_PC represents a set of boards including P1020UTM-PC P1021RDB-PC P1024RDB - P1025RDB P2020RDB-PC They have similar design of P1020RDB but have DDR3 instead of DDR2. P2020RDB-PC diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 2346f6a0c27..850e1c7103f 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -146,8 +146,7 @@ dimm_params_t ddr_raw_timing = { .refresh_rate_ps = 7800000, .tfaw_ps = 37500, }; -#elif defined(CONFIG_TARGET_P1024RDB) || \ - defined(CONFIG_TARGET_P1025RDB) +#elif defined(CONFIG_TARGET_P1024RDB) /* * Samsung K4B2G0846C-HCH9 * The following timing are for "downshift" diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index ba12bea92f5..2005944725c 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -53,7 +53,7 @@ #define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) #endif -#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) #define PCA_IOPORT_I2C_ADDR 0x23 #define PCA_IOPORT_OUTPUT_CMD 0x2 #define PCA_IOPORT_CFG_CMD 0x6 @@ -70,43 +70,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ - -#ifdef CONFIG_TARGET_P1025RDB - /* QE_MUX_MDC */ - {1, 19, 1, 0, 1}, /* QE_MUX_MDC */ - - /* QE_MUX_MDIO */ - {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */ - - /* UCC_1_MII */ - {0, 23, 2, 0, 2}, /* CLK12 */ - {0, 24, 2, 0, 1}, /* CLK9 */ - {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */ - {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */ - {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */ - {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */ - {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */ - {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */ - {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */ - {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */ - {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */ - {0, 13, 1, 0, 2}, /* ENET1_TX_ER */ - {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */ - {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */ - {0, 17, 2, 0, 2}, /* ENET1_CRS */ - {0, 16, 2, 0, 2}, /* ENET1_COL */ - - /* UCC_5_RMII */ - {1, 11, 2, 0, 1}, /* CLK13 */ - {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */ - {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */ - {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */ - {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */ - {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */ - {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */ - {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */ -#endif - {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */ }; #endif @@ -410,7 +373,7 @@ int board_eth_init(struct bd_info *bis) #endif #if defined(CONFIG_QE) && \ - (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)) + (defined(CONFIG_TARGET_P1021RDB)) static void fdt_board_fixup_qe_pins(void *blob) { unsigned int oldbus; @@ -481,7 +444,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", sizeof("okay"), 0); -#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB) +#if defined(CONFIG_TARGET_P1021RDB) fdt_board_fixup_qe_pins(blob); #endif #endif diff --git a/configs/P1025RDB_36BIT_defconfig b/configs/P1025RDB_36BIT_defconfig deleted file mode 100644 index d0fc144d8f8..00000000000 --- a/configs/P1025RDB_36BIT_defconfig +++ /dev/null @@ -1,65 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1025RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1025RDB_NAND_defconfig b/configs/P1025RDB_NAND_defconfig deleted file mode 100644 index 58efd11e942..00000000000 --- a/configs/P1025RDB_NAND_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1025RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1025RDB_SDCARD_defconfig b/configs/P1025RDB_SDCARD_defconfig deleted file mode 100644 index dad06be5474..00000000000 --- a/configs/P1025RDB_SDCARD_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1025RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1025RDB_SPIFLASH_defconfig b/configs/P1025RDB_SPIFLASH_defconfig deleted file mode 100644 index 48e35409869..00000000000 --- a/configs/P1025RDB_SPIFLASH_defconfig +++ /dev/null @@ -1,77 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1025RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1025RDB_defconfig b/configs/P1025RDB_defconfig deleted file mode 100644 index 7164526b715..00000000000 --- a/configs/P1025RDB_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1025RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index a159285c981..c7a2c807f5c 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -104,21 +104,6 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_TARGET_P1025RDB) -#define CONFIG_BOARDNAME "P1025RDB" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SLIC - -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of - addresses in the LBC */ -#define __SW_BOOT_MASK 0xf3 -#define __SW_BOOT_NOR 0x00 -#define __SW_BOOT_SPI 0x08 -#define __SW_BOOT_SD 0x04 -#define __SW_BOOT_NAND 0x0c -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - #if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC @@ -655,42 +640,6 @@ #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #endif /* CONFIG_QE */ -#ifdef CONFIG_TARGET_P1025RDB -/* - * QE UEC ethernet configuration - */ -#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) - -#undef CONFIG_UEC_ETH -#define CONFIG_PHY_MODE_NEED_CHANGE - -#define CONFIG_UEC_ETH1 /* ETH1 */ -#define CONFIG_HAS_ETH0 - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */ -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH1 */ - -#define CONFIG_UEC_ETH5 /* ETH5 */ -#define CONFIG_HAS_ETH1 - -#ifdef CONFIG_UEC_ETH5 -#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */ -#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */ -#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */ -#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100 -#endif /* CONFIG_UEC_ETH5 */ -#endif /* CONFIG_TARGET_P1025RDB */ - /* * Environment */ -- cgit v1.3.1 From da3dd417d73ffadfaf8837aaa5c170ead3334df2 Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 11:56:38 +0530 Subject: board/freescale: Remove P1020UTM board support Remove NXP powerpc P1020UTM board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 ---- board/freescale/p1_p2_rdb_pc/Kconfig | 1 - board/freescale/p1_p2_rdb_pc/MAINTAINERS | 4 -- board/freescale/p1_p2_rdb_pc/README | 1 - board/freescale/p1_p2_rdb_pc/ddr.c | 3 +- configs/P1020UTM-PC_36BIT_SDCARD_defconfig | 69 ------------------------------ configs/P1020UTM-PC_36BIT_defconfig | 57 ------------------------ configs/P1020UTM-PC_SDCARD_defconfig | 67 ----------------------------- configs/P1020UTM-PC_defconfig | 55 ------------------------ include/configs/p1_p2_rdb_pc.h | 11 ----- 10 files changed, 1 insertion(+), 276 deletions(-) delete mode 100644 configs/P1020UTM-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1020UTM-PC_36BIT_defconfig delete mode 100644 configs/P1020UTM-PC_SDCARD_defconfig delete mode 100644 configs/P1020UTM-PC_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index eade333ef4c..668aaf5b9fb 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -136,15 +136,6 @@ config TARGET_P1020RDB_PD imply CMD_SATA imply PANIC_HANG -config TARGET_P1020UTM - bool "Support P1020UTM" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P1021RDB bool "Support P1021RDB" select SUPPORT_SPL diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index 8797b41e2ab..39982b42a52 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,7 +1,6 @@ if TARGET_P1020MBG || \ TARGET_P1020RDB_PC || \ TARGET_P1020RDB_PD || \ - TARGET_P1020UTM || \ TARGET_P1021RDB || \ TARGET_P1024RDB || \ TARGET_P2020RDB diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index b57af344c78..710deedf99d 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -19,10 +19,6 @@ F: configs/P1020RDB-PD_defconfig F: configs/P1020RDB-PD_NAND_defconfig F: configs/P1020RDB-PD_SDCARD_defconfig F: configs/P1020RDB-PD_SPIFLASH_defconfig -F: configs/P1020UTM-PC_defconfig -F: configs/P1020UTM-PC_36BIT_defconfig -F: configs/P1020UTM-PC_36BIT_SDCARD_defconfig -F: configs/P1020UTM-PC_SDCARD_defconfig F: configs/P1021RDB-PC_defconfig F: configs/P1021RDB-PC_36BIT_defconfig F: configs/P1021RDB-PC_36BIT_NAND_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/README b/board/freescale/p1_p2_rdb_pc/README index adc273eb325..86ff04e69d9 100644 --- a/board/freescale/p1_p2_rdb_pc/README +++ b/board/freescale/p1_p2_rdb_pc/README @@ -4,7 +4,6 @@ P1_P2_RDB_PC represents a set of boards including P1020MSBG-PC P1020RDB-PC P1020RDB-PD - P1020UTM-PC P1021RDB-PC P1024RDB P2020RDB-PC diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 850e1c7103f..cbcdf9201b3 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -15,8 +15,7 @@ #ifdef CONFIG_SYS_DDR_RAW_TIMING #if defined(CONFIG_P1020RDB_PROTO) || \ - defined(CONFIG_TARGET_P1021RDB) || \ - defined(CONFIG_TARGET_P1020UTM) + defined(CONFIG_TARGET_P1021RDB) /* Micron MT41J256M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, diff --git a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig b/configs/P1020UTM-PC_36BIT_SDCARD_defconfig deleted file mode 100644 index d0b5065d6c3..00000000000 --- a/configs/P1020UTM-PC_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020UTM=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020UTM-PC_36BIT_defconfig b/configs/P1020UTM-PC_36BIT_defconfig deleted file mode 100644 index 5e3a92dec7a..00000000000 --- a/configs/P1020UTM-PC_36BIT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020UTM=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020UTM-PC_SDCARD_defconfig b/configs/P1020UTM-PC_SDCARD_defconfig deleted file mode 100644 index 6c06815a170..00000000000 --- a/configs/P1020UTM-PC_SDCARD_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020UTM=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020UTM-PC_defconfig b/configs/P1020UTM-PC_defconfig deleted file mode 100644 index 69744a30f5c..00000000000 --- a/configs/P1020UTM-PC_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020UTM=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index c7a2c807f5c..69365a6a191 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -22,14 +22,6 @@ #define CONFIG_SYS_L2_SIZE (256 << 10) #endif -#if defined(CONFIG_TARGET_P1020UTM) -#define CONFIG_BOARDNAME "P1020UTM-PC" -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0xe0 -#define __SW_BOOT_SD 0x50 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - #if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC @@ -301,9 +293,6 @@ #if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_TARGET_P1020UTM) -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ -#define CONFIG_SYS_FLASH_BASE 0xee000000 #else #define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ #define CONFIG_SYS_FLASH_BASE 0xef000000 -- cgit v1.3.1 From 53e3096cd0a76c59c69250dd46e8278dc1db553b Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 11:56:39 +0530 Subject: board/freescale: Remove P1020MBG board support Remove NXP powerpc P1020MBG board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 ---- board/freescale/p1_p2_rdb_pc/Kconfig | 3 +- board/freescale/p1_p2_rdb_pc/MAINTAINERS | 4 -- board/freescale/p1_p2_rdb_pc/tlb.c | 4 +- configs/P1020MBG-PC_36BIT_SDCARD_defconfig | 69 ------------------------------ configs/P1020MBG-PC_36BIT_defconfig | 57 ------------------------ configs/P1020MBG-PC_SDCARD_defconfig | 67 ----------------------------- configs/P1020MBG-PC_defconfig | 55 ------------------------ include/configs/p1_p2_rdb_pc.h | 14 +----- 9 files changed, 5 insertions(+), 277 deletions(-) delete mode 100644 configs/P1020MBG-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1020MBG-PC_36BIT_defconfig delete mode 100644 configs/P1020MBG-PC_SDCARD_defconfig delete mode 100644 configs/P1020MBG-PC_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 668aaf5b9fb..c2065026c8f 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -109,15 +109,6 @@ config TARGET_P1010RDB_PB imply CMD_SATA imply PANIC_HANG -config TARGET_P1020MBG - bool "Support P1020MBG-PC" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1020 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P1020RDB_PC bool "Support P1020RDB-PC" select SUPPORT_SPL diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index 39982b42a52..0f4f14df928 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,5 +1,4 @@ -if TARGET_P1020MBG || \ - TARGET_P1020RDB_PC || \ +if TARGET_P1020RDB_PC || \ TARGET_P1020RDB_PD || \ TARGET_P1021RDB || \ TARGET_P1024RDB || \ diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index 710deedf99d..2f35622294b 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -3,10 +3,6 @@ P1_P2_RDB_PC BOARD S: Maintained F: board/freescale/p1_p2_rdb_pc/ F: include/configs/p1_p2_rdb_pc.h -F: configs/P1020MBG-PC_defconfig -F: configs/P1020MBG-PC_36BIT_defconfig -F: configs/P1020MBG-PC_36BIT_SDCARD_defconfig -F: configs/P1020MBG-PC_SDCARD_defconfig F: configs/P1020RDB-PC_defconfig F: configs/P1020RDB-PC_36BIT_defconfig F: configs/P1020RDB-PC_36BIT_NAND_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 14971f0476e..fcd7a55199f 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -84,13 +84,13 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, 0, 8, BOOKE_PAGESZ_1G, 1), -#if defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD) +#if defined(CONFIG_TARGET_P1020RDB_PD) /* 2G DDR on P1020MBG, map the second 1G */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif /* TARGET_P1020MBG */ +#endif #endif /* RAMBOOT/SPL */ #ifdef CONFIG_SYS_INIT_L2_ADDR diff --git a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig b/configs/P1020MBG-PC_36BIT_SDCARD_defconfig deleted file mode 100644 index b5ef3954d33..00000000000 --- a/configs/P1020MBG-PC_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020MBG=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020MBG-PC_36BIT_defconfig b/configs/P1020MBG-PC_36BIT_defconfig deleted file mode 100644 index 39abe1f85a8..00000000000 --- a/configs/P1020MBG-PC_36BIT_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020MBG=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020MBG-PC_SDCARD_defconfig b/configs/P1020MBG-PC_SDCARD_defconfig deleted file mode 100644 index 12b01750e7d..00000000000 --- a/configs/P1020MBG-PC_SDCARD_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020MBG=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1020MBG-PC_defconfig b/configs/P1020MBG-PC_defconfig deleted file mode 100644 index 71ad06ca8f8..00000000000 --- a/configs/P1020MBG-PC_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1020MBG=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 69365a6a191..eed6ebc9870 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -12,16 +12,6 @@ #include -#if defined(CONFIG_TARGET_P1020MBG) -#define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_VSC7385_ENET -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0xe4 -#define __SW_BOOT_SD 0x54 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - #if defined(CONFIG_TARGET_P1020RDB_PC) #define CONFIG_BOARDNAME "P1020RDB-PC" #define CONFIG_NAND_FSL_ELBC @@ -223,7 +213,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS 0x52 -#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G #define CONFIG_CHIP_SELECTS_PER_CTRL 2 #else @@ -290,7 +280,7 @@ /* * Local Bus Definitions */ -#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) +#if defined(CONFIG_TARGET_P1020RDB_PD) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ #define CONFIG_SYS_FLASH_BASE 0xec000000 #else -- cgit v1.3.1 From 6d1dd76afe85947d605923dd7fc9f4ca7cf8c72d Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 15:36:25 +0530 Subject: board/freescale: Remove P1021RDB board support Remove NXP powerpc P1021RDB board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 --- board/freescale/p1_p2_rdb_pc/Kconfig | 1 - board/freescale/p1_p2_rdb_pc/MAINTAINERS | 8 --- board/freescale/p1_p2_rdb_pc/ddr.c | 3 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 77 ------------------------- configs/P1021RDB-PC_36BIT_NAND_defconfig | 86 ---------------------------- configs/P1021RDB-PC_36BIT_SDCARD_defconfig | 81 -------------------------- configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig | 83 --------------------------- configs/P1021RDB-PC_36BIT_defconfig | 69 ---------------------- configs/P1021RDB-PC_NAND_defconfig | 84 --------------------------- configs/P1021RDB-PC_SDCARD_defconfig | 79 ------------------------- configs/P1021RDB-PC_SPIFLASH_defconfig | 81 -------------------------- configs/P1021RDB-PC_defconfig | 67 ---------------------- include/configs/p1_p2_rdb_pc.h | 18 ------ 14 files changed, 1 insertion(+), 745 deletions(-) delete mode 100644 configs/P1021RDB-PC_36BIT_NAND_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_SDCARD_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig delete mode 100644 configs/P1021RDB-PC_36BIT_defconfig delete mode 100644 configs/P1021RDB-PC_NAND_defconfig delete mode 100644 configs/P1021RDB-PC_SDCARD_defconfig delete mode 100644 configs/P1021RDB-PC_SPIFLASH_defconfig delete mode 100644 configs/P1021RDB-PC_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index c2065026c8f..7d8f1349b24 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -127,15 +127,6 @@ config TARGET_P1020RDB_PD imply CMD_SATA imply PANIC_HANG -config TARGET_P1021RDB - bool "Support P1021RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1021 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P1024RDB bool "Support P1024RDB" select SUPPORT_SPL diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index 0f4f14df928..bd9b06ceef9 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,6 +1,5 @@ if TARGET_P1020RDB_PC || \ TARGET_P1020RDB_PD || \ - TARGET_P1021RDB || \ TARGET_P1024RDB || \ TARGET_P2020RDB diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index 2f35622294b..875c4410510 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -15,14 +15,6 @@ F: configs/P1020RDB-PD_defconfig F: configs/P1020RDB-PD_NAND_defconfig F: configs/P1020RDB-PD_SDCARD_defconfig F: configs/P1020RDB-PD_SPIFLASH_defconfig -F: configs/P1021RDB-PC_defconfig -F: configs/P1021RDB-PC_36BIT_defconfig -F: configs/P1021RDB-PC_36BIT_NAND_defconfig -F: configs/P1021RDB-PC_36BIT_SDCARD_defconfig -F: configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig -F: configs/P1021RDB-PC_NAND_defconfig -F: configs/P1021RDB-PC_SDCARD_defconfig -F: configs/P1021RDB-PC_SPIFLASH_defconfig F: configs/P1024RDB_defconfig F: configs/P1024RDB_36BIT_defconfig F: configs/P1024RDB_NAND_defconfig diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index cbcdf9201b3..be803ddf9c6 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -14,8 +14,7 @@ #include #ifdef CONFIG_SYS_DDR_RAW_TIMING -#if defined(CONFIG_P1020RDB_PROTO) || \ - defined(CONFIG_TARGET_P1021RDB) +#if defined(CONFIG_P1020RDB_PROTO) /* Micron MT41J256M8_187E */ dimm_params_t ddr_raw_timing = { .n_ranks = 1, diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index 2005944725c..4584f0147b5 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -45,28 +45,9 @@ #define GPIO_SLIC_PIN 30 #define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN)) -#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) -#define GPIO_DDR_RST_PORT 1 -#define GPIO_DDR_RST_PIN 8 -#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN)) - -#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2)) -#endif - -#if defined(CONFIG_TARGET_P1021RDB) -#define PCA_IOPORT_I2C_ADDR 0x23 -#define PCA_IOPORT_OUTPUT_CMD 0x2 -#define PCA_IOPORT_CFG_CMD 0x6 -#define PCA_IOPORT_QE_PIN_ENABLE 0xf8 -#define PCA_IOPORT_QE_TDM_ENABLE 0xf6 -#endif - const qe_iop_conf_t qe_iop_conf_tab[] = { /* GPIO */ {1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */ -#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) - {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */ -#endif {0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */ {GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */ {GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */ @@ -119,16 +100,6 @@ void board_gpio_init(void) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io); -#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT) - /* reset DDR3 */ - setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); - udelay(1000); - clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); - udelay(1000); - setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA); - /* disable CE_PB8 */ - clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK); -#endif /* Enable VSC7385 switch */ setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA); @@ -372,51 +343,6 @@ int board_eth_init(struct bd_info *bis) } #endif -#if defined(CONFIG_QE) && \ - (defined(CONFIG_TARGET_P1021RDB)) -static void fdt_board_fixup_qe_pins(void *blob) -{ - unsigned int oldbus; - u8 val8; - int node; - fsl_lbc_t *lbc = LBC_BASE_ADDR; - - if (hwconfig("qe")) { - /* For QE and eLBC pins multiplexing, - * there is a PCA9555 device on P1025RDB. - * It control the multiplex pins' functions, - * and setting the PCA9555 can switch the - * function between QE and eLBC. - */ - oldbus = i2c_get_bus_num(); - i2c_set_bus_num(0); - if (hwconfig("tdm")) - val8 = PCA_IOPORT_QE_TDM_ENABLE; - else - val8 = PCA_IOPORT_QE_PIN_ENABLE; - i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD, - 1, &val8, 1); - i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD, - 1, &val8, 1); - i2c_set_bus_num(oldbus); - /* if run QE TDM, Set ABSWP to implement - * conversion of addresses in the eLBC. - */ - if (hwconfig("tdm")) { - set_lbc_or(2, CONFIG_PMC_OR_PRELIM); - set_lbc_br(2, CONFIG_PMC_BR_PRELIM); - setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR); - } - } else { - node = fdt_path_offset(blob, "/qe"); - if (node >= 0) - fdt_del_node(blob, node); - } - - return; -} -#endif - #ifdef CONFIG_OF_BOARD_SETUP int ft_board_setup(void *blob, struct bd_info *bd) { @@ -444,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) #ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay", sizeof("okay"), 0); -#if defined(CONFIG_TARGET_P1021RDB) - fdt_board_fixup_qe_pins(blob); -#endif #endif #if defined(CONFIG_HAS_FSL_DR_USB) diff --git a/configs/P1021RDB-PC_36BIT_NAND_defconfig b/configs/P1021RDB-PC_36BIT_NAND_defconfig deleted file mode 100644 index ca5baae8f6b..00000000000 --- a/configs/P1021RDB-PC_36BIT_NAND_defconfig +++ /dev/null @@ -1,86 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig b/configs/P1021RDB-PC_36BIT_SDCARD_defconfig deleted file mode 100644 index 7a64eecc2fa..00000000000 --- a/configs/P1021RDB-PC_36BIT_SDCARD_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig deleted file mode 100644 index cc0fc1e35a9..00000000000 --- a/configs/P1021RDB-PC_36BIT_SPIFLASH_defconfig +++ /dev/null @@ -1,83 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_36BIT_defconfig b/configs/P1021RDB-PC_36BIT_defconfig deleted file mode 100644 index 58cdba9d7b1..00000000000 --- a/configs/P1021RDB-PC_36BIT_defconfig +++ /dev/null @@ -1,69 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=fef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=fef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_NAND_defconfig b/configs/P1021RDB-PC_NAND_defconfig deleted file mode 100644 index e8f99f0f40c..00000000000 --- a/configs/P1021RDB-PC_NAND_defconfig +++ /dev/null @@ -1,84 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_SDCARD_defconfig b/configs/P1021RDB-PC_SDCARD_defconfig deleted file mode 100644 index e285c014846..00000000000 --- a/configs/P1021RDB-PC_SDCARD_defconfig +++ /dev/null @@ -1,79 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_SPIFLASH_defconfig b/configs/P1021RDB-PC_SPIFLASH_defconfig deleted file mode 100644 index 3c1b4c8c2a6..00000000000 --- a/configs/P1021RDB-PC_SPIFLASH_defconfig +++ /dev/null @@ -1,81 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1021RDB-PC_defconfig b/configs/P1021RDB-PC_defconfig deleted file mode 100644 index 4b2083ce7c4..00000000000 --- a/configs/P1021RDB-PC_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1021RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=ef000000.nor" -CONFIG_MTDPARTS_DEFAULT="mtdparts=ef000000.nor:256k(vsc7385-firmware),256k(dtb),4608k(kernel),9728k(fs),256k(qe-ucode-firmware),1280k(u-boot)" -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_FLASH_CFI_MTD=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index eed6ebc9870..63500741f68 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -56,24 +56,6 @@ */ #endif -#if defined(CONFIG_TARGET_P1021RDB) -#define CONFIG_BOARDNAME "P1021RDB-PC" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_VSC7385_ENET -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of - addresses in the LBC */ -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0x5c -#define __SW_BOOT_SPI 0x1c -#define __SW_BOOT_SD 0x9c -#define __SW_BOOT_NAND 0xec -#define __SW_BOOT_PCIE 0x6c -#define CONFIG_SYS_L2_SIZE (256 << 10) -/* - * Dynamic MTD Partition support with mtdparts - */ -#endif - #if defined(CONFIG_TARGET_P1024RDB) #define CONFIG_BOARDNAME "P1024RDB" #define CONFIG_NAND_FSL_ELBC -- cgit v1.3.1 From 63310debc95bde86c82f340a4fc27b42d09c048d Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 11:56:41 +0530 Subject: board/freescale: Remove P1024RDB board support Remove NXP powerpc P1024RDB board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 9 ---- board/freescale/p1_p2_rdb_pc/Kconfig | 1 - board/freescale/p1_p2_rdb_pc/MAINTAINERS | 5 -- configs/P1024RDB_36BIT_defconfig | 63 -------------------------- configs/P1024RDB_NAND_defconfig | 78 -------------------------------- configs/P1024RDB_SDCARD_defconfig | 72 ----------------------------- configs/P1024RDB_SPIFLASH_defconfig | 74 ------------------------------ configs/P1024RDB_defconfig | 61 ------------------------- include/configs/p1_p2_rdb_pc.h | 12 ----- 9 files changed, 375 deletions(-) delete mode 100644 configs/P1024RDB_36BIT_defconfig delete mode 100644 configs/P1024RDB_NAND_defconfig delete mode 100644 configs/P1024RDB_SDCARD_defconfig delete mode 100644 configs/P1024RDB_SPIFLASH_defconfig delete mode 100644 configs/P1024RDB_defconfig (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7d8f1349b24..fcb1ce6574b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -127,15 +127,6 @@ config TARGET_P1020RDB_PD imply CMD_SATA imply PANIC_HANG -config TARGET_P1024RDB - bool "Support P1024RDB" - select SUPPORT_SPL - select SUPPORT_TPL - select ARCH_P1024 - imply CMD_EEPROM - imply CMD_SATA - imply PANIC_HANG - config TARGET_P2020RDB bool "Support P2020RDB-PC" select SUPPORT_SPL diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig index bd9b06ceef9..cd36150f637 100644 --- a/board/freescale/p1_p2_rdb_pc/Kconfig +++ b/board/freescale/p1_p2_rdb_pc/Kconfig @@ -1,6 +1,5 @@ if TARGET_P1020RDB_PC || \ TARGET_P1020RDB_PD || \ - TARGET_P1024RDB || \ TARGET_P2020RDB config SYS_BOARD diff --git a/board/freescale/p1_p2_rdb_pc/MAINTAINERS b/board/freescale/p1_p2_rdb_pc/MAINTAINERS index 875c4410510..b737b09b093 100644 --- a/board/freescale/p1_p2_rdb_pc/MAINTAINERS +++ b/board/freescale/p1_p2_rdb_pc/MAINTAINERS @@ -15,11 +15,6 @@ F: configs/P1020RDB-PD_defconfig F: configs/P1020RDB-PD_NAND_defconfig F: configs/P1020RDB-PD_SDCARD_defconfig F: configs/P1020RDB-PD_SPIFLASH_defconfig -F: configs/P1024RDB_defconfig -F: configs/P1024RDB_36BIT_defconfig -F: configs/P1024RDB_NAND_defconfig -F: configs/P1024RDB_SDCARD_defconfig -F: configs/P1024RDB_SPIFLASH_defconfig F: configs/P2020RDB-PC_defconfig F: configs/P2020RDB-PC_36BIT_defconfig F: configs/P2020RDB-PC_36BIT_NAND_defconfig diff --git a/configs/P1024RDB_36BIT_defconfig b/configs/P1024RDB_36BIT_defconfig deleted file mode 100644 index e74fc7f1b21..00000000000 --- a/configs/P1024RDB_36BIT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1024RDB=y -CONFIG_PHYS_64BIT=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1024RDB_NAND_defconfig b/configs/P1024RDB_NAND_defconfig deleted file mode 100644 index d1e91d37015..00000000000 --- a/configs/P1024RDB_NAND_defconfig +++ /dev/null @@ -1,78 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_ENV_SIZE=0x4000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_SPL_TEXT_BASE=0xFF800000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_TPL_LIBCOMMON_SUPPORT=y -CONFIG_TPL_LIBGENERIC_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1024RDB=y -CONFIG_SYS_CUSTOM_LDSCRIPT=y -CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_NAND_BOOT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_TPL=y -CONFIG_TPL_ENV_SUPPORT=y -CONFIG_TPL_I2C_SUPPORT=y -CONFIG_TPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_TPL_NAND_SUPPORT=y -CONFIG_TPL_SERIAL_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1024RDB_SDCARD_defconfig b/configs/P1024RDB_SDCARD_defconfig deleted file mode 100644 index e803ed80fa5..00000000000 --- a/configs/P1024RDB_SDCARD_defconfig +++ /dev/null @@ -1,72 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x0 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_MMC_SUPPORT=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1024RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SDCARD" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_MMC_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1024RDB_SPIFLASH_defconfig b/configs/P1024RDB_SPIFLASH_defconfig deleted file mode 100644 index ffabd5e7605..00000000000 --- a/configs/P1024RDB_SPIFLASH_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0x11001000 -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_SPL_TEXT_BASE=0xf8f81000 -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1024RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH" -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -# CONFIG_SPL_FRAMEWORK is not set -CONFIG_SPL_SPI_BOOT=y -CONFIG_SPL_ENV_SUPPORT=y -CONFIG_SPL_I2C_SUPPORT=y -CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P1024RDB_defconfig b/configs/P1024RDB_defconfig deleted file mode 100644 index e4adc0f5eb8..00000000000 --- a/configs/P1024RDB_defconfig +++ /dev/null @@ -1,61 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -# CONFIG_CMD_ERRATA is not set -CONFIG_TARGET_P1024RDB=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -# CONFIG_MISC_INIT_R is not set -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -# CONFIG_AUTO_COMPLETE is not set -CONFIG_CMD_IMLS=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_DATE=y -CONFIG_MP=y -# CONFIG_CMD_HASH is not set -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHY_ATHEROS=y -CONFIG_PHY_BROADCOM=y -CONFIG_PHY_DAVICOM=y -CONFIG_PHY_LXT=y -CONFIG_PHY_MARVELL=y -CONFIG_PHY_NATSEMI=y -CONFIG_PHY_REALTEK=y -CONFIG_PHY_SMSC=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_MII=y -CONFIG_TSEC_ENET=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 63500741f68..a9bf213d8b4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -56,18 +56,6 @@ */ #endif -#if defined(CONFIG_TARGET_P1024RDB) -#define CONFIG_BOARDNAME "P1024RDB" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0xf3 -#define __SW_BOOT_NOR 0x00 -#define __SW_BOOT_SPI 0x08 -#define __SW_BOOT_SD 0x04 -#define __SW_BOOT_NAND 0x0c -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - #if defined(CONFIG_TARGET_P2020RDB) #define CONFIG_BOARDNAME "P2020RDB-PC" #define CONFIG_NAND_FSL_ELBC -- cgit v1.3.1 From 8e01439dd30c4f74839d65962fecde6c1722b79d Mon Sep 17 00:00:00 2001 From: Priyanka Jain Date: Mon, 21 Sep 2020 11:56:44 +0530 Subject: board/freescale: Remove P5020DS board support Remove NXP powerpc P5020DS board support as it is no longer maintained. Signed-off-by: Priyanka Jain --- arch/powerpc/cpu/mpc85xx/Kconfig | 8 ---- board/freescale/common/Makefile | 1 - board/freescale/corenet_ds/Kconfig | 15 ------- board/freescale/corenet_ds/MAINTAINERS | 8 ---- board/freescale/corenet_ds/Makefile | 2 - board/freescale/corenet_ds/p5020ds_ddr.c | 15 ------- board/freescale/corenet_ds/rcw_p5020ds.cfg | 11 ------ configs/P5020DS_NAND_SECURE_BOOT_defconfig | 63 ------------------------------ configs/P5020DS_NAND_defconfig | 60 ---------------------------- configs/P5020DS_SDCARD_defconfig | 58 --------------------------- configs/P5020DS_SECURE_BOOT_defconfig | 60 ---------------------------- configs/P5020DS_SPIFLASH_defconfig | 59 ---------------------------- configs/P5020DS_SRIO_PCIE_BOOT_defconfig | 53 ------------------------- configs/P5020DS_defconfig | 57 --------------------------- include/configs/P5020DS.h | 25 ------------ 15 files changed, 495 deletions(-) delete mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c delete mode 100644 board/freescale/corenet_ds/rcw_p5020ds.cfg delete mode 100644 configs/P5020DS_NAND_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_NAND_defconfig delete mode 100644 configs/P5020DS_SDCARD_defconfig delete mode 100644 configs/P5020DS_SECURE_BOOT_defconfig delete mode 100644 configs/P5020DS_SPIFLASH_defconfig delete mode 100644 configs/P5020DS_SRIO_PCIE_BOOT_defconfig delete mode 100644 configs/P5020DS_defconfig delete mode 100644 include/configs/P5020DS.h (limited to 'include') diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index fcb1ce6574b..54c7fd9522a 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -40,14 +40,6 @@ config TARGET_P4080DS imply CMD_SATA imply PANIC_HANG -config TARGET_P5020DS - bool "Support P5020DS" - select PHYS_64BIT - select ARCH_P5020 - select BOARD_LATE_INIT if CHAIN_OF_TRUST - imply CMD_SATA - imply PANIC_HANG - config TARGET_P5040DS bool "Support P5040DS" select PHYS_64BIT diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index b0e109f0b82..04e04a63582 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,7 +53,6 @@ obj-$(CONFIG_TARGET_P1022DS) += ics307_clk.o obj-$(CONFIG_P2020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P3041DS) += ics307_clk.o obj-$(CONFIG_TARGET_P4080DS) += ics307_clk.o -obj-$(CONFIG_TARGET_P5020DS) += ics307_clk.o obj-$(CONFIG_TARGET_P5040DS) += ics307_clk.o obj-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig index 98b1adde620..e92b0d099da 100644 --- a/board/freescale/corenet_ds/Kconfig +++ b/board/freescale/corenet_ds/Kconfig @@ -28,21 +28,6 @@ source "board/freescale/common/Kconfig" endif -if TARGET_P5020DS - -config SYS_BOARD - default "corenet_ds" - -config SYS_VENDOR - default "freescale" - -config SYS_CONFIG_NAME - default "P5020DS" - -source "board/freescale/common/Kconfig" - -endif - if TARGET_P5040DS config SYS_BOARD diff --git a/board/freescale/corenet_ds/MAINTAINERS b/board/freescale/corenet_ds/MAINTAINERS index 88c852eb500..e22cf703b74 100644 --- a/board/freescale/corenet_ds/MAINTAINERS +++ b/board/freescale/corenet_ds/MAINTAINERS @@ -13,13 +13,6 @@ F: configs/P4080DS_defconfig F: configs/P4080DS_SDCARD_defconfig F: configs/P4080DS_SPIFLASH_defconfig F: configs/P4080DS_SRIO_PCIE_BOOT_defconfig -F: include/configs/P5020DS.h -F: configs/P5020DS_defconfig -F: configs/P5020DS_NAND_defconfig -F: configs/P5020DS_SDCARD_defconfig -F: configs/P5020DS_SECURE_BOOT_defconfig -F: configs/P5020DS_SPIFLASH_defconfig -F: configs/P5020DS_SRIO_PCIE_BOOT_defconfig F: include/configs/P5040DS.h F: configs/P5040DS_defconfig F: configs/P5040DS_NAND_defconfig @@ -31,5 +24,4 @@ CORENET_DS_SECURE_BOOT BOARD M: Ruchika Gupta S: Maintained F: configs/P3041DS_NAND_SECURE_BOOT_defconfig -F: configs/P5020DS_NAND_SECURE_BOOT_defconfig F: configs/P5040DS_NAND_SECURE_BOOT_defconfig diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 98322b27477..4d62fc9ce19 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -8,9 +8,7 @@ obj-y += corenet_ds.o obj-y += ddr.o obj-$(CONFIG_TARGET_P3041DS) += eth_hydra.o obj-$(CONFIG_TARGET_P4080DS) += eth_p4080.o -obj-$(CONFIG_TARGET_P5020DS) += eth_hydra.o obj-$(CONFIG_TARGET_P5040DS) += eth_superhydra.o obj-$(CONFIG_TARGET_P3041DS) += p3041ds_ddr.o obj-$(CONFIG_TARGET_P4080DS) += p4080ds_ddr.o -obj-$(CONFIG_TARGET_P5020DS) += p5020ds_ddr.o obj-$(CONFIG_TARGET_P5040DS) += p5040ds_ddr.o diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c deleted file mode 100644 index 112733be781..00000000000 --- a/board/freescale/corenet_ds/p5020ds_ddr.c +++ /dev/null @@ -1,15 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#include -#include - -fixed_ddr_parm_t fixed_ddr_parm_0[] = { - {0, 0, NULL} -}; - -fixed_ddr_parm_t fixed_ddr_parm_1[] = { - {0, 0, NULL} -}; diff --git a/board/freescale/corenet_ds/rcw_p5020ds.cfg b/board/freescale/corenet_ds/rcw_p5020ds.cfg deleted file mode 100644 index b09e409bbff..00000000000 --- a/board/freescale/corenet_ds/rcw_p5020ds.cfg +++ /dev/null @@ -1,11 +0,0 @@ -# -# Default RCW for P5020DS. -# - -#PBL preamble and RCW header -aa55aa55 010e0100 -#64 bytes RCW data -0C540000 00000000 1E120000 00000000 -D8984A01 03002000 58000000 41000000 -00000000 00000000 00000000 10070000 -00000000 00000000 00000000 00000000 diff --git a/configs/P5020DS_NAND_SECURE_BOOT_defconfig b/configs/P5020DS_NAND_SECURE_BOOT_defconfig deleted file mode 100644 index b781667430e..00000000000 --- a/configs/P5020DS_NAND_SECURE_BOOT_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_NAND_defconfig b/configs/P5020DS_NAND_defconfig deleted file mode 100644 index e5ea1665c43..00000000000 --- a/configs/P5020DS_NAND_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x20000 -CONFIG_ENV_OFFSET=0xE0000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SDCARD_defconfig b/configs/P5020DS_SDCARD_defconfig deleted file mode 100644 index 6bf1e9de3eb..00000000000 --- a/configs/P5020DS_SDCARD_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0xCF400 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SDCARD" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_MMC=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SECURE_BOOT_defconfig b/configs/P5020DS_SECURE_BOOT_defconfig deleted file mode 100644 index aae9a7d80dc..00000000000 --- a/configs/P5020DS_SECURE_BOOT_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_NXP_ESBC=y -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -# CONFIG_SYS_MALLOC_F is not set -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_DM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_SOFTWARE_EXP=y -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SPIFLASH_defconfig b/configs/P5020DS_SPIFLASH_defconfig deleted file mode 100644 index 683751a5312..00000000000 --- a/configs/P5020DS_SPIFLASH_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x100000 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPIFLASH" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig b/configs/P5020DS_SRIO_PCIE_BOOT_defconfig deleted file mode 100644 index 631f7ab2be9..00000000000 --- a/configs/P5020DS_SRIO_PCIE_BOOT_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xFFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE" -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_GREPENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_REMOTE=y -CONFIG_ENV_ADDR=0xFFE20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_REMOTE=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/configs/P5020DS_defconfig b/configs/P5020DS_defconfig deleted file mode 100644 index 73c3ed68fab..00000000000 --- a/configs/P5020DS_defconfig +++ /dev/null @@ -1,57 +0,0 @@ -CONFIG_PPC=y -CONFIG_SYS_TEXT_BASE=0xEFF40000 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_SECT_SIZE=0x20000 -CONFIG_MPC85xx=y -CONFIG_TARGET_P5020DS=y -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_OF_BOARD_SETUP=y -CONFIG_OF_STDOUT_VIA_ALIAS=y -CONFIG_BOOTDELAY=10 -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_BOARD_EARLY_INIT_R=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_IMLS=y -CONFIG_CMD_GREPENV=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_MP=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_FAT=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_ENV_ADDR=0xEFF20000 -CONFIG_FSL_CAAM=y -CONFIG_FSL_ESDHC=y -CONFIG_MTD=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=10000000 -CONFIG_SPI_FLASH_SPANSION=y -CONFIG_PHYLIB=y -CONFIG_PHYLIB_10G=y -CONFIG_PHY_TERANETICS=y -CONFIG_PHY_VITESSE=y -CONFIG_PHY_GIGE=y -CONFIG_E1000=y -CONFIG_FMAN_ENET=y -CONFIG_MII=y -CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550=y -CONFIG_SPI=y -CONFIG_FSL_ESPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_ADDR_MAP=y -CONFIG_SYS_NUM_ADDR_MAP=64 -CONFIG_OF_LIBFDT=y diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h deleted file mode 100644 index 873d39a10c5..00000000000 --- a/include/configs/P5020DS.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5020 DS board configuration file - * Also supports P5010 DS - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" -- cgit v1.3.1 From 99e555a79ab882eb8b38886fa5dab053d4d64bfa Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:44:55 -0600 Subject: x86: coral: Add ACPI tables for coral This device has a large set of ACPI tables. Bring these in from coreboot so that full functionality is available (apart from SMI). Signed-off-by: Simon Glass --- board/google/chromebook_coral/Makefile | 1 + board/google/chromebook_coral/baseboard_dptf.asl | 71 ++++++++++++ board/google/chromebook_coral/coral.c | 136 +++++++++++++++++++++++ board/google/chromebook_coral/dsdt.asl | 60 ++++++++++ board/google/chromebook_coral/variant_dptf.asl | 6 + board/google/chromebook_coral/variant_ec.h | 75 +++++++++++++ board/google/chromebook_coral/variant_gpio.h | 63 +++++++++++ include/bloblist.h | 5 + 8 files changed, 417 insertions(+) create mode 100644 board/google/chromebook_coral/baseboard_dptf.asl create mode 100644 board/google/chromebook_coral/dsdt.asl create mode 100644 board/google/chromebook_coral/variant_dptf.asl create mode 100644 board/google/chromebook_coral/variant_ec.h create mode 100644 board/google/chromebook_coral/variant_gpio.h (limited to 'include') diff --git a/board/google/chromebook_coral/Makefile b/board/google/chromebook_coral/Makefile index 6a27ce3da1b..f7a0ca6cc0a 100644 --- a/board/google/chromebook_coral/Makefile +++ b/board/google/chromebook_coral/Makefile @@ -3,3 +3,4 @@ # Copyright 2019 Google LLC obj-y += coral.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/google/chromebook_coral/baseboard_dptf.asl b/board/google/chromebook_coral/baseboard_dptf.asl new file mode 100644 index 00000000000..5da963a6705 --- /dev/null +++ b/board/google/chromebook_coral/baseboard_dptf.asl @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 105 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 120 +#define DPTF_TSR0_CRITICAL 125 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 46 +#define DPTF_TSR1_CRITICAL 75 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 58 +#define DPTF_TSR2_CRITICAL 90 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 1200, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 300, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index 12d4fe63cb0..f5ae48290f4 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -4,7 +4,24 @@ */ #include +#include #include +#include +#include +#include +#include +#include +#include +#include +#include +#include "variant_gpio.h" + +struct cros_gpio_info { + const char *linux_name; + enum cros_gpio_t type; + int gpio_num; + int flags; +}; int arch_misc_init(void) { @@ -18,3 +35,122 @@ int board_run_command(const char *cmdline) return 0; } + +int chromeos_get_gpio(const struct udevice *dev, const char *prop, + enum cros_gpio_t type, struct cros_gpio_info *info) +{ + struct udevice *pinctrl; + struct gpio_desc desc; + int ret; + + ret = gpio_request_by_name((struct udevice *)dev, prop, 0, &desc, 0); + if (ret == -ENOTBLK) + info->gpio_num = CROS_GPIO_VIRTUAL; + else if (ret) + return log_msg_ret("gpio", ret); + else + info->gpio_num = desc.offset; + info->linux_name = dev_read_string(desc.dev, "linux-name"); + if (!info->linux_name) + return log_msg_ret("linux-name", -ENOENT); + info->type = type; + /* Get ACPI pin from GPIO library if available */ + if (info->gpio_num != CROS_GPIO_VIRTUAL) { + pinctrl = dev_get_parent(desc.dev); + info->gpio_num = intel_pinctrl_get_acpi_pin(pinctrl, + info->gpio_num); + } + info->flags = desc.flags & GPIOD_ACTIVE_LOW ? CROS_GPIO_ACTIVE_LOW : + CROS_GPIO_ACTIVE_HIGH; + + return 0; +} + +static int chromeos_acpi_gpio_generate(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct cros_gpio_info info[3]; + int count, i; + int ret; + + count = 3; + ret = chromeos_get_gpio(dev, "recovery-gpios", CROS_GPIO_REC, &info[0]); + if (ret) + return log_msg_ret("rec", ret); + ret = chromeos_get_gpio(dev, "write-protect-gpios", CROS_GPIO_WP, + &info[1]); + if (ret) + return log_msg_ret("rec", ret); + ret = chromeos_get_gpio(dev, "phase-enforce-gpios", CROS_GPIO_PE, + &info[2]); + if (ret) + return log_msg_ret("rec", ret); + acpigen_write_scope(ctx, "\\"); + acpigen_write_name(ctx, "OIPG"); + acpigen_write_package(ctx, count); + for (i = 0; i < count; i++) { + acpigen_write_package(ctx, 4); + acpigen_write_integer(ctx, info[i].type); + acpigen_write_integer(ctx, info[i].flags); + acpigen_write_integer(ctx, info[i].gpio_num); + acpigen_write_string(ctx, info[i].linux_name); + acpigen_pop_len(ctx); + } + + acpigen_pop_len(ctx); + acpigen_pop_len(ctx); + + return 0; +} + +static int coral_write_acpi_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct acpi_global_nvs *gnvs; + struct nhlt *nhlt; + const char *oem_id = "coral"; + const char *oem_table_id = "coral"; + u32 oem_revision = 3; + int ret; + + gnvs = bloblist_find(BLOBLISTT_ACPI_GNVS, sizeof(*gnvs)); + if (!gnvs) + return log_msg_ret("bloblist", -ENOENT); + + nhlt = nhlt_init(); + if (!nhlt) + return -ENOMEM; + + log_debug("Setting up NHLT\n"); + ret = acpi_setup_nhlt(ctx, nhlt); + if (ret) + return log_msg_ret("setup", ret); + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)ctx->current; + gnvs->nhll = nhlt_current_size(nhlt); + + ret = nhlt_serialise_oem_overrides(ctx, nhlt, oem_id, oem_table_id, + oem_revision); + if (ret) + return log_msg_ret("serialise", ret); + + return 0; +} + +struct acpi_ops coral_acpi_ops = { + .write_tables = coral_write_acpi_tables, + .inject_dsdt = chromeos_acpi_gpio_generate, +}; + +static const struct udevice_id coral_ids[] = { + { .compatible = "google,coral" }, + { } +}; + +U_BOOT_DRIVER(coral_drv) = { + .name = "coral", + .id = UCLASS_BOARD, + .of_match = coral_ids, + ACPI_OPS_PTR(&coral_acpi_ops) +}; diff --git a/board/google/chromebook_coral/dsdt.asl b/board/google/chromebook_coral/dsdt.asl new file mode 100644 index 00000000000..b51e0b05005 --- /dev/null +++ b/board/google/chromebook_coral/dsdt.asl @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +#include "variant_ec.h" +#include "variant_gpio.h" +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + OEM_TABLE_ID, + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } + + /* Chrome OS specific */ + #include + + /* Chipset specific sleep states */ + #include + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + /* ACPI code for EC functions */ + #include + } + + /* Dynamic Platform Thermal Framework */ + Scope (\_SB) + { + /* Per board variant specific definitions. */ + #include "variant_dptf.asl" + /* Include soc specific DPTF changes */ + #include + /* Include common dptf ASL files */ + #include + } +} diff --git a/board/google/chromebook_coral/variant_dptf.asl b/board/google/chromebook_coral/variant_dptf.asl new file mode 100644 index 00000000000..943ebeaac26 --- /dev/null +++ b/board/google/chromebook_coral/variant_dptf.asl @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2016 Google Inc. + */ + +#include "baseboard_dptf.asl" diff --git a/board/google/chromebook_coral/variant_ec.h b/board/google/chromebook_coral/variant_ec.h new file mode 100644 index 00000000000..7d5e1a674cf --- /dev/null +++ b/board/google/chromebook_coral/variant_ec.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC +/* + * Taken from coreboot file of the same name + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include "variant_gpio.h" +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* EC can wake from S3 with lid or power button or key press */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) | \ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define EC_ENABLE_TBMC_DEVICE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + +#endif diff --git a/board/google/chromebook_coral/variant_gpio.h b/board/google/chromebook_coral/variant_gpio.h new file mode 100644 index 00000000000..f516d88be5c --- /dev/null +++ b/board/google/chromebook_coral/variant_gpio.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + * + * Taken from coreboot file of the same name + */ + +#ifndef BASEBOARD_GPIO_H +#define BASEBOARD_GPIO_H + +#include +#include + +/* + * GPIO_11 for SCI is routed to GPE0_DW1 and maps to group GPIO_GPE_N_31_0 + * which is North community + */ +#define EC_SCI_GPI GPE0_DW1_11 + +/* EC SMI */ +#define EC_SMI_GPI GPIO_49 + +/* + * On lidopen/lidclose GPIO_22 from North Community gets toggled and + * is used in _PRW to wake up device from sleep. GPIO_22 maps to + * group GPIO_GPE_N_31_0 and the pad is configured as SCI with + * EDGE_SINGLE and INVERT. + */ +#define GPE_EC_WAKE GPE0_DW1_22 + +/* Write Protect and indication if EC is in RW code. */ +#define GPIO_PCH_WP GPIO_75 +#define GPIO_EC_IN_RW GPIO_41 +/* Determine if board is in final shipping mode. */ +#define GPIO_SHIP_MODE GPIO_10 + +/* Memory SKU GPIOs. */ +#define MEM_CONFIG3 GPIO_45 +#define MEM_CONFIG2 GPIO_38 +#define MEM_CONFIG1 GPIO_102 +#define MEM_CONFIG0 GPIO_101 + +/* DMIC_CONFIG_PIN: High for 1-DMIC and low for 4-DMIC's */ +#define DMIC_CONFIG_PIN GPIO_17 + +#ifndef __ASSEMBLY__ + +enum cros_gpio_t { + CROS_GPIO_REC = 1, /* Recovery */ + + /* Developer; * deprecated (chromium:942901) */ + CROS_GPIO_DEPRECATED_DEV = 2, + CROS_GPIO_WP = 3, /* Write Protect */ + CROS_GPIO_PE = 4, /* Phase enforcement for final product */ + + CROS_GPIO_ACTIVE_LOW = 0, + CROS_GPIO_ACTIVE_HIGH = 1, + + CROS_GPIO_VIRTUAL = -1, +}; +#endif + +#endif /* BASEBOARD_GPIO_H */ diff --git a/include/bloblist.h b/include/bloblist.h index 609ac421d66..bbe0a35d5a2 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -27,6 +27,11 @@ enum bloblist_tag_t { BLOBLISTT_SPL_HANDOFF, /* Hand-off info from SPL */ BLOBLISTT_VBOOT_CTX, /* Chromium OS verified boot context */ BLOBLISTT_VBOOT_HANDOFF, /* Chromium OS internal handoff info */ + /* + * Advanced Configuration and Power Interface Global Non-Volatile + * Sleeping table. This forms part of the ACPI tables passed to Linux. + */ + BLOBLISTT_ACPI_GNVS, }; /** -- cgit v1.3.1 From e0a896b88f2e517b10c67a4f85f3846a0312041d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:44:56 -0600 Subject: acpi: Add support for writing a _PRW A 'Power Resource for Wake' list the resources a device depends on for wake. Add a function to generate this. Signed-off-by: Simon Glass --- include/acpi/acpigen.h | 10 ++++++++++ lib/acpi/acpigen.c | 10 ++++++++++ test/dm/acpigen.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 50 insertions(+) (limited to 'include') diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 228ac9c404b..a9b70123c0a 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -563,4 +563,14 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val, const char *dw0_read, const char *dw0_write, struct acpi_gpio *gpio, bool enable); +/** + * acpigen_write_prw() - Write a power resource for wake (_PRW) + * + * @ctx: ACPI context pointer + * @wake: GPE that wakes up the device + * @level: Deepest power system sleeping state that can be entered while still + * providing wake functionality + */ +void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level); + #endif diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index c609ef4daa4..527de89b1e1 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -426,6 +426,16 @@ void acpigen_write_register_resource(struct acpi_ctx *ctx, acpigen_write_resourcetemplate_footer(ctx); } +void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level) +{ + /* Name (_PRW, Package () { wake, level } */ + acpigen_write_name(ctx, "_PRW"); + acpigen_write_package(ctx, 2); + acpigen_write_integer(ctx, wake); + acpigen_write_integer(ctx, level); + acpigen_pop_len(ctx); +} + /* * ToUUID(uuid) * diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 1b2767e732d..1dc064ffbcf 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -1097,3 +1097,33 @@ static int dm_test_acpi_write_name(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_name, 0); + +/* Test emitting a _PRW component */ +static int dm_test_acpi_write_prw(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_prw(ctx, 5, 3); + ut_asserteq(NAME_OP, *ptr++); + + ut_asserteq_strn("_PRW", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ut_asserteq(8, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(2, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(5, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(3, *ptr++); + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_prw, 0); -- cgit v1.3.1 From da7cff338f08cf43706a96bcd8cf398b7fb6ae2d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:44:57 -0600 Subject: acpi: Add support for conditions and return values Add functions to support generating ACPI code for condition checks and return values. Signed-off-by: Simon Glass --- include/acpi/acpigen.h | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++ lib/acpi/acpigen.c | 68 ++++++++++++++++++++++++++++++++++++ test/dm/acpigen.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 252 insertions(+) (limited to 'include') diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index a9b70123c0a..fa9409e3528 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -52,12 +52,24 @@ enum { LOCAL5_OP = 0x65, LOCAL6_OP = 0x66, LOCAL7_OP = 0x67, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6a, + ARG3_OP = 0x6b, + ARG4_OP = 0x6c, + ARG5_OP = 0x6d, + ARG6_OP = 0x6e, STORE_OP = 0x70, AND_OP = 0x7b, OR_OP = 0x7d, NOT_OP = 0x80, DEVICE_OP = 0x82, POWER_RES_OP = 0x84, + LEQUAL_OP = 0x93, + TO_BUFFER_OP = 0x96, + TO_INTEGER_OP = 0x99, + IF_OP = 0xa0, + ELSE_OP = 0xa1, RETURN_OP = 0xa4, }; @@ -573,4 +585,85 @@ int acpigen_set_enable_tx_gpio(struct acpi_ctx *ctx, u32 tx_state_val, */ void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level); +/** + * acpigen_write_if() - Write an If block + * + * This requires a call to acpigen_pop_len() to complete the block + * + * @ctx: ACPI context pointer + */ +void acpigen_write_if(struct acpi_ctx *ctx); + +/** + * acpigen_write_if_lequal_op_int() - Write comparison between op and integer + * + * Generates ACPI code for checking if operand1 and operand2 are equal + * + * If (Lequal (op, val)) + * + * @ctx: ACPI context pointer + * @op: Operand to check + * @val: Value to check against + */ +void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val); + +/** + * acpigen_write_else() - Write an Ef block + * + * This requires a call to acpigen_pop_len() to complete the block + * + * @ctx: ACPI context pointer + */ +void acpigen_write_else(struct acpi_ctx *ctx); + +/** + * acpigen_write_to_buffer() - Write a ToBuffer operation + * + * E.g.: to generate: ToBuffer (Arg0, Local0) + * use acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP) + * + * @ctx: ACPI context pointer + * @src: Source argument + * @dst: Destination argument + */ +void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst); + +/** + * acpigen_write_to_integer() - Write a ToInteger operation + * + * E.g.: to generate: ToInteger (Arg0, Local0) + * use acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP) + * + * @ctx: ACPI context pointer + * @src: Source argument + * @dst: Destination argument + */ +void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst); + +/** + * acpigen_write_return_byte_buffer() - Write a return of a byte buffer + * + * @ctx: ACPI context pointer + * @arr: Array of bytes to return + * @size: Number of bytes + */ +void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr, + size_t size); + +/** + * acpigen_write_return_singleton_buffer() - Write a return of a 1-byte buffer + * + * @ctx: ACPI context pointer + * @arg: Byte to return + */ +void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg); + +/** + * acpigen_write_return_byte() - Write a return of a byte + * + * @ctx: ACPI context pointer + * @arg: Byte to return + */ +void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg); + #endif diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index 527de89b1e1..2518bf83dda 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -541,6 +541,74 @@ void acpigen_write_debug_string(struct acpi_ctx *ctx, const char *str) acpigen_emit_ext_op(ctx, DEBUG_OP); } +void acpigen_write_if(struct acpi_ctx *ctx) +{ + acpigen_emit_byte(ctx, IF_OP); + acpigen_write_len_f(ctx); +} + +void acpigen_write_if_lequal_op_int(struct acpi_ctx *ctx, uint op, u64 val) +{ + acpigen_write_if(ctx); + acpigen_emit_byte(ctx, LEQUAL_OP); + acpigen_emit_byte(ctx, op); + acpigen_write_integer(ctx, val); +} + +void acpigen_write_else(struct acpi_ctx *ctx) +{ + acpigen_emit_byte(ctx, ELSE_OP); + acpigen_write_len_f(ctx); +} + +void acpigen_write_to_buffer(struct acpi_ctx *ctx, uint src, uint dst) +{ + acpigen_emit_byte(ctx, TO_BUFFER_OP); + acpigen_emit_byte(ctx, src); + acpigen_emit_byte(ctx, dst); +} + +void acpigen_write_to_integer(struct acpi_ctx *ctx, uint src, uint dst) +{ + acpigen_emit_byte(ctx, TO_INTEGER_OP); + acpigen_emit_byte(ctx, src); + acpigen_emit_byte(ctx, dst); +} + +void acpigen_write_byte_buffer(struct acpi_ctx *ctx, u8 *arr, size_t size) +{ + size_t i; + + acpigen_emit_byte(ctx, BUFFER_OP); + acpigen_write_len_f(ctx); + acpigen_write_integer(ctx, size); + + for (i = 0; i < size; i++) + acpigen_emit_byte(ctx, arr[i]); + + acpigen_pop_len(ctx); +} + +void acpigen_write_return_byte_buffer(struct acpi_ctx *ctx, u8 *arr, + size_t size) +{ + acpigen_emit_byte(ctx, RETURN_OP); + acpigen_write_byte_buffer(ctx, arr, size); +} + +void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg) +{ + u8 buf = arg; + + acpigen_write_return_byte_buffer(ctx, &buf, 1); +} + +void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg) +{ + acpigen_emit_byte(ctx, RETURN_OP); + acpigen_write_byte(ctx, arg); +} + /** * acpigen_get_dw0_in_local5() - Generate code to put dw0 cfg0 in local5 * diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 1dc064ffbcf..cce19f11209 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -1127,3 +1127,94 @@ static int dm_test_acpi_write_prw(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_prw, 0); + +/* Test emitting writing conditionals */ +static int dm_test_acpi_write_cond(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_if(ctx); + acpigen_pop_len(ctx); + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(3, acpi_test_get_length(ptr)); + ptr += 3; + + acpigen_write_else(ctx); + acpigen_pop_len(ctx); + ut_asserteq(ELSE_OP, *ptr++); + ut_asserteq(3, acpi_test_get_length(ptr)); + ptr += 3; + + acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, 5); + acpigen_pop_len(ctx); + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(7, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL1_OP, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(5, *ptr++); + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_cond, 0); + +/* Test emitting writing return values and ToBuffer/ToInteger */ +static int dm_test_acpi_write_return(struct unit_test_state *uts) +{ + int len = sizeof(TEST_STRING); + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP); + ut_asserteq(TO_BUFFER_OP, *ptr++); + ut_asserteq(ARG0_OP, *ptr++); + ut_asserteq(LOCAL0_OP, *ptr++); + + acpigen_write_to_integer(ctx, ARG0_OP, LOCAL0_OP); + ut_asserteq(TO_INTEGER_OP, *ptr++); + ut_asserteq(ARG0_OP, *ptr++); + ut_asserteq(LOCAL0_OP, *ptr++); + + acpigen_write_return_byte_buffer(ctx, (u8 *)TEST_STRING, len); + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ut_asserteq(5 + len, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(len, *ptr++); + ut_asserteq_mem(TEST_STRING, ptr, len); + ptr += len; + + acpigen_write_return_singleton_buffer(ctx, 123); + len = 1; + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ut_asserteq(4 + len, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(ONE_OP, *ptr++); + ut_asserteq(123, *ptr++); + + acpigen_write_return_byte(ctx, 43); + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(43, *ptr++); + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_return, 0); -- cgit v1.3.1 From 88490e197903f6961cf2ee79d0ff8f0727155f27 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:44:58 -0600 Subject: acpi: Support generating a multi-function _DSM for devices Add a function to generate ACPI code for a _DSM method for a device. This includes functions for starting and ending each part of the _DSM. Signed-off-by: Simon Glass [bmeng: fix the "new blank line at EOF" git warning] Signed-off-by: Bin Meng --- include/acpi/acpi_device.h | 14 +++++ include/acpi/acpigen.h | 99 +++++++++++++++++++++++++++++++++++ lib/acpi/acpi_device.c | 43 ++++++++++++++++ lib/acpi/acpigen.c | 54 ++++++++++++++++++++ test/dm/acpigen.c | 125 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 335 insertions(+) (limited to 'include') diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h index 11461e168d3..a5b12217820 100644 --- a/include/acpi/acpi_device.h +++ b/include/acpi/acpi_device.h @@ -28,6 +28,9 @@ struct udevice; /* Length of a full path to an ACPI device */ #define ACPI_PATH_MAX 30 +/* UUID for an I2C _DSM method */ +#define ACPI_DSM_I2C_HID_UUID "3cdff6f7-4267-4555-ad05-b30a3d8938de" + /* Values that can be returned for ACPI device _STA method */ enum acpi_dev_status { ACPI_DSTATUS_PRESENT = BIT(0), @@ -319,6 +322,17 @@ int acpi_device_write_gpio_desc(struct acpi_ctx *ctx, int acpi_device_write_interrupt_or_gpio(struct acpi_ctx *ctx, struct udevice *dev, const char *prop); +/** + * acpi_device_write_dsm_i2c_hid() - Write a device-specific method for HID + * + * This writes a DSM for an I2C Human-Interface Device based on the config + * provided + * + * @hid_desc_reg_offset: HID register offset + */ +int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, + int hid_desc_reg_offset); + /** * acpi_device_write_i2c_dev() - Write an I2C device to ACPI * diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index fa9409e3528..34b3115bc9c 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -666,4 +666,103 @@ void acpigen_write_return_singleton_buffer(struct acpi_ctx *ctx, uint arg); */ void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg); +/** + * acpigen_write_dsm_start() - Start a _DSM method + * + * Generate ACPI AML code to start the _DSM method. + * + * The functions need to be called in the correct sequence as below. + * + * Within the region, Local0 and Local1 must be are left + * untouched, but Local2-Local7 can be used + * + * Arguments passed into _DSM method: + * Arg0 = UUID + * Arg1 = Revision + * Arg2 = Function index + * Arg3 = Function-specific arguments + * + * AML code generated looks like this: + * Method (_DSM, 4, Serialized) { -- acpigen_write_dsm_start) + * ToBuffer (Arg0, Local0) + * If (LEqual (Local0, ToUUID(uuid))) { -- acpigen_write_dsm_uuid_start + * ToInteger (Arg2, Local1) + * If (LEqual (Local1, 0)) { -- acpigen_write_dsm_uuid_start_cond + * + * } -- acpigen_write_dsm_uuid_end_cond + * ... + * If (LEqual (Local1, n)) { -- acpigen_write_dsm_uuid_start_cond + * + * } -- acpigen_write_dsm_uuid_end_cond + * Return (Buffer (One) { 0x0 }) + * } -- acpigen_write_dsm_uuid_end + * ... + * If (LEqual (Local0, ToUUID(uuidn))) { + * ... + * } + * Return (Buffer (One) { 0x0 }) -- acpigen_write_dsm_end + * } + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_start(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_uuid_start() - Start a new UUID block + * + * This starts generation of code to handle a particular UUID: + * + * If (LEqual (Local0, ToUUID(uuid))) { + * ToInteger (Arg2, Local1) + * + * @ctx: ACPI context pointer + */ +int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid); + +/** + * acpigen_write_dsm_uuid_start_cond() - Start a new condition block + * + * This starts generation of condition-checking code to handle a particular + * function: + * + * If (LEqual (Local1, i)) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq); + +/** + * acpigen_write_dsm_uuid_end_cond() - Start a new condition block + * + * This ends generation of condition-checking code to handle a particular + * function: + * + * } + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_uuid_end() - End a UUID block + * + * This ends generation of code to handle a particular UUID: + * + * Return (Buffer (One) { 0x0 }) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx); + +/** + * acpigen_write_dsm_end() - End a _DSM method + * + * This ends generates of the _DSM block: + * + * Return (Buffer (One) { 0x0 }) + * + * @ctx: ACPI context pointer + */ +void acpigen_write_dsm_end(struct acpi_ctx *ctx); + #endif diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c index 3c75b6d9629..8248664a10a 100644 --- a/lib/acpi/acpi_device.c +++ b/lib/acpi/acpi_device.c @@ -487,6 +487,49 @@ int acpi_device_add_power_res(struct acpi_ctx *ctx, u32 tx_state_val, return 0; } +int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, + int hid_desc_reg_offset) +{ + int ret; + + acpigen_write_dsm_start(ctx); + ret = acpigen_write_dsm_uuid_start(ctx, ACPI_DSM_I2C_HID_UUID); + if (ret) + return log_ret(ret); + + acpigen_write_dsm_uuid_start_cond(ctx, 0); + /* ToInteger (Arg1, Local2) */ + acpigen_write_to_integer(ctx, ARG1_OP, LOCAL2_OP); + /* If (LEqual (Local2, 0x0)) */ + acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x0); + /* Return (Buffer (One) { 0x1f }) */ + acpigen_write_return_singleton_buffer(ctx, 0x1f); + acpigen_pop_len(ctx); /* Pop : If */ + /* Else */ + acpigen_write_else(ctx); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal_op_int(ctx, LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3f }) */ + acpigen_write_return_singleton_buffer(ctx, 0x3f); + acpigen_pop_len(ctx); /* Pop : If */ + /* Else */ + acpigen_write_else(ctx); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(ctx, 0x0); + acpigen_pop_len(ctx); /* Pop : Else */ + acpigen_pop_len(ctx); /* Pop : Else */ + acpigen_write_dsm_uuid_end_cond(ctx); + + acpigen_write_dsm_uuid_start_cond(ctx, 1); + acpigen_write_return_byte(ctx, hid_desc_reg_offset); + acpigen_write_dsm_uuid_end_cond(ctx); + + acpigen_write_dsm_uuid_end(ctx); + acpigen_write_dsm_end(ctx); + + return 0; +} + /* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */ static void acpi_device_write_i2c(struct acpi_ctx *ctx, const struct acpi_i2c *i2c) diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index 2518bf83dda..d859f378413 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -609,6 +609,60 @@ void acpigen_write_return_byte(struct acpi_ctx *ctx, uint arg) acpigen_write_byte(ctx, arg); } +void acpigen_write_dsm_start(struct acpi_ctx *ctx) +{ + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized(ctx, "_DSM", 4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ctx, ARG0_OP, LOCAL0_OP); +} + +int acpigen_write_dsm_uuid_start(struct acpi_ctx *ctx, const char *uuid) +{ + int ret; + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(ctx); + acpigen_emit_byte(ctx, LEQUAL_OP); + acpigen_emit_byte(ctx, LOCAL0_OP); + ret = acpigen_write_uuid(ctx, uuid); + if (ret) + return log_msg_ret("uuid", ret); + + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ctx, ARG2_OP, LOCAL1_OP); + + return 0; +} + +void acpigen_write_dsm_uuid_start_cond(struct acpi_ctx *ctx, int seq) +{ + /* If (LEqual (Local1, i)) */ + acpigen_write_if_lequal_op_int(ctx, LOCAL1_OP, seq); +} + +void acpigen_write_dsm_uuid_end_cond(struct acpi_ctx *ctx) +{ + acpigen_pop_len(ctx); /* If */ +} + +void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx) +{ + /* Default case: Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(ctx, 0x0); + + acpigen_pop_len(ctx); /* If (LEqual (Local0, ToUUID(uuid))) */ +} + +void acpigen_write_dsm_end(struct acpi_ctx *ctx) +{ + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(ctx, 0x0); + + acpigen_pop_len(ctx); /* Method _DSM */ +} + /** * acpigen_get_dw0_in_local5() - Generate code to put dw0 cfg0 in local5 * diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index cce19f11209..62d48dc419c 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1218,3 +1219,127 @@ static int dm_test_acpi_write_return(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_return, 0); + +/* Test emitting a DSM for an I2C HID */ +static int dm_test_acpi_write_i2c_dsm(struct unit_test_state *uts) +{ + char uuid_str[UUID_STR_LEN + 1]; + const int reg_offset = 0x20; + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + ut_assertok(acpi_device_write_dsm_i2c_hid(ctx, reg_offset)); + + /* acpigen_write_dsm_start() */ + ut_asserteq(METHOD_OP, *ptr++); + ut_asserteq(0x78, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq_strn("_DSM", (char *)ptr); + ptr += 4; + ut_asserteq(ACPI_METHOD_SERIALIZED_MASK | 4, *ptr++); + + ut_asserteq(TO_BUFFER_OP, *ptr++); + ut_asserteq(ARG0_OP, *ptr++); + ut_asserteq(LOCAL0_OP, *ptr++); + + /* acpigen_write_dsm_uuid_start() */ + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(0x65, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL0_OP, *ptr++); + + ut_asserteq(BUFFER_OP, *ptr++); + ut_asserteq(UUID_BIN_LEN + 6, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(WORD_PREFIX, *ptr++); + ut_asserteq(UUID_BIN_LEN, get_unaligned((u16 *)ptr)); + ptr += 2; + uuid_bin_to_str(ptr, uuid_str, UUID_STR_FORMAT_GUID); + ut_asserteq_str(ACPI_DSM_I2C_HID_UUID, uuid_str); + ptr += UUID_BIN_LEN; + + ut_asserteq(TO_INTEGER_OP, *ptr++); + ut_asserteq(ARG2_OP, *ptr++); + ut_asserteq(LOCAL1_OP, *ptr++); + + /* acpigen_write_dsm_uuid_start_cond() */ + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(0x34, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL1_OP, *ptr++); + ut_asserteq(ZERO_OP, *ptr++); + + /* + * See code from acpi_device_write_dsm_i2c_hid(). We don't check every + * piece + */ + ut_asserteq(TO_INTEGER_OP, *ptr++); + ut_asserteq(ARG1_OP, *ptr++); + ut_asserteq(LOCAL2_OP, *ptr++); + + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(0xd, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL2_OP, *ptr++); + ut_asserteq(ZERO_OP, *ptr++); /* function 0 */ + + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 5; + + ut_asserteq(ELSE_OP, *ptr++); + ptr += 3; + + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(0xd, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL2_OP, *ptr++); + ut_asserteq(ONE_OP, *ptr++); + + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 5; + + ut_asserteq(ELSE_OP, *ptr++); + ptr += 3; + + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 5; + + /* acpigen_write_dsm_uuid_start_cond() */ + ut_asserteq(IF_OP, *ptr++); + ut_asserteq(9, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq(LEQUAL_OP, *ptr++); + ut_asserteq(LOCAL1_OP, *ptr++); + ut_asserteq(ONE_OP, *ptr++); /* function 1 */ + + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(reg_offset, *ptr++); + + /* acpigen_write_dsm_uuid_end() */ + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 5; + + /* acpigen_write_dsm_end */ + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 5; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_i2c_dsm, 0); -- cgit v1.3.1 From 23dd0ea4c7edbde5bc05a1567ba0bf41734ea524 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:44:59 -0600 Subject: dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio() This function currently accepts the IRQ-polarity type. Fix it to use the GPIO type instead. Signed-off-by: Simon Glass --- drivers/sound/max98357a.c | 2 +- include/acpi/acpi_dp.h | 2 +- lib/acpi/acpi_dp.c | 4 ++-- test/dm/acpi_dp.c | 4 ++-- 4 files changed, 6 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index 841bc6ef682..827262d235c 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -81,7 +81,7 @@ static int max98357a_acpi_fill_ssdt(const struct udevice *dev, dp = acpi_dp_new_table("_DSD"); acpi_dp_add_gpio(dp, "sdmode-gpio", path, 0, 0, priv->sdmode_gpio.flags & GPIOD_ACTIVE_LOW ? - ACPI_IRQ_ACTIVE_LOW : ACPI_IRQ_ACTIVE_HIGH); + ACPI_GPIO_ACTIVE_LOW : ACPI_GPIO_ACTIVE_HIGH); acpi_dp_add_integer(dp, "sdmode-delay", dev_read_u32_default(dev, "sdmode-delay", 0)); acpi_dp_write(ctx, dp); diff --git a/include/acpi/acpi_dp.h b/include/acpi/acpi_dp.h index 0b514bce59c..5e539b1d218 100644 --- a/include/acpi/acpi_dp.h +++ b/include/acpi/acpi_dp.h @@ -221,7 +221,7 @@ struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, */ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, - enum acpi_irq_polarity polarity); + enum acpi_gpio_polarity polarity); /** * acpi_dp_write() - Write Device Property hierarchy and clean up resources diff --git a/lib/acpi/acpi_dp.c b/lib/acpi/acpi_dp.c index 579cab47715..7e3e3259d8d 100644 --- a/lib/acpi/acpi_dp.c +++ b/lib/acpi/acpi_dp.c @@ -324,7 +324,7 @@ struct acpi_dp *acpi_dp_add_integer_array(struct acpi_dp *dp, const char *name, struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, int index, int pin, - enum acpi_irq_polarity polarity) + enum acpi_gpio_polarity polarity) { struct acpi_dp *gpio; @@ -336,7 +336,7 @@ struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, if (!acpi_dp_add_reference(gpio, NULL, ref) || !acpi_dp_add_integer(gpio, NULL, index) || !acpi_dp_add_integer(gpio, NULL, pin) || - !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_IRQ_ACTIVE_LOW)) + !acpi_dp_add_integer(gpio, NULL, polarity == ACPI_GPIO_ACTIVE_LOW)) return NULL; if (!acpi_dp_add_array(dp, gpio)) diff --git a/test/dm/acpi_dp.c b/test/dm/acpi_dp.c index e0fa61263c8..44bcabda6bc 100644 --- a/test/dm/acpi_dp.c +++ b/test/dm/acpi_dp.c @@ -398,9 +398,9 @@ static int dm_test_acpi_dp_gpio(struct unit_test_state *uts) /* Try a few different parameters */ ut_assertnonnull(acpi_dp_add_gpio(dp, "reset", TEST_REF, 0x23, 0x24, - ACPI_IRQ_ACTIVE_HIGH)); + ACPI_GPIO_ACTIVE_HIGH)); ut_assertnonnull(acpi_dp_add_gpio(dp, "allow", TEST_REF, 0, 0, - ACPI_IRQ_ACTIVE_LOW)); + ACPI_GPIO_ACTIVE_LOW)); ptr = acpigen_get_current(ctx); ut_assertok(acpi_dp_write(ctx, dp)); -- cgit v1.3.1 From fd42f263cef9fd6bba9ded76a82d4ac66450e156 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:01 -0600 Subject: i2c: Add a generic driver to generate ACPI info Many I2C devices produce roughly the same ACPI data with just things like the GPIO/interrupt information being different. This can be handled by a generic driver along with some information in the device tree. Add a generic i2c driver for this purpose. Signed-off-by: Simon Glass Reviewed-by: Heiko Schocher --- doc/device-tree-bindings/i2c/generic-acpi.txt | 42 +++++ drivers/i2c/Makefile | 3 + drivers/i2c/acpi_i2c.c | 226 ++++++++++++++++++++++++++ drivers/i2c/acpi_i2c.h | 15 ++ drivers/i2c/i2c-uclass.c | 17 ++ include/acpi/acpi_device.h | 55 +++++++ include/i2c.h | 23 +++ 7 files changed, 381 insertions(+) create mode 100644 doc/device-tree-bindings/i2c/generic-acpi.txt create mode 100644 drivers/i2c/acpi_i2c.c create mode 100644 drivers/i2c/acpi_i2c.h (limited to 'include') diff --git a/doc/device-tree-bindings/i2c/generic-acpi.txt b/doc/device-tree-bindings/i2c/generic-acpi.txt new file mode 100644 index 00000000000..3510a71b570 --- /dev/null +++ b/doc/device-tree-bindings/i2c/generic-acpi.txt @@ -0,0 +1,42 @@ +I2C generic device +================== + +This is used only to generate ACPI tables for an I2C device. + +Required properties : + + - compatible : "i2c-chip"; + - reg : I2C chip address + - acpi,hid : HID name for the device + +Optional properies in addition to device.txt: + + - reset-gpios : GPIO used to assert reset to the device + - irq-gpios : GPIO used for interrupt (if Interrupt is not used) + - stop-gpios : GPIO used to stop the device + - interrupts-extended : Interrupt to use for the device + - reset-delay-ms : Delay after de-asserting reset, in ms + - reset-off-delay-ms : Delay after asserting reset (during power off) + - enable-delay-ms : Delay after asserting enable + - enable-off-delay-ms : Delay after de-asserting enable (during power off) + - stop-delay-ms : Delay after de-aserting stop + - stop-off-delay-ms : Delay after asserting stop (during power off) + - hid-descr-addr : HID register offset (for Human Interface Devices) + +Example +------- + + elan-touchscreen@10 { + compatible = "i2c-chip"; + reg = <0x10>; + acpi,hid = "ELAN0001"; + acpi,ddn = "ELAN Touchscreen"; + interrupts-extended = <&acpi_gpe GPIO_21_IRQ + IRQ_TYPE_EDGE_FALLING>; + linux,probed; + reset-gpios = <&gpio_n GPIO_36 GPIO_ACTIVE_HIGH>; + reset-delay-ms = <20>; + enable-gpios = <&gpio_n GPIO_152 GPIO_ACTIVE_HIGH>; + enable-delay-ms = <1>; + acpi,has-power-resource; + }; diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index f7b27864488..bd248cbf52b 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -3,6 +3,9 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. obj-$(CONFIG_DM_I2C) += i2c-uclass.o +ifdef CONFIG_ACPIGEN +obj-$(CONFIG_DM_I2C) += acpi_i2c.o +endif obj-$(CONFIG_DM_I2C_GPIO) += i2c-gpio.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_TUNNEL) += cros_ec_tunnel.o obj-$(CONFIG_$(SPL_)I2C_CROS_EC_LDO) += cros_ec_ldo.o diff --git a/drivers/i2c/acpi_i2c.c b/drivers/i2c/acpi_i2c.c new file mode 100644 index 00000000000..57d29683cbf --- /dev/null +++ b/drivers/i2c/acpi_i2c.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 Google LLC + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_X86 +#include +#endif +#include +#include + +static bool acpi_i2c_add_gpios_to_crs(struct acpi_i2c_priv *priv) +{ + /* + * Return false if: + * 1. Request to explicitly disable export of GPIOs in CRS, or + * 2. Both reset and enable GPIOs are not provided. + */ + if (priv->disable_gpio_export_in_crs || + (!dm_gpio_is_valid(&priv->reset_gpio) && + !dm_gpio_is_valid(&priv->enable_gpio))) + return false; + + return true; +} + +static int acpi_i2c_write_gpio(struct acpi_ctx *ctx, struct gpio_desc *gpio, + int *curindex) +{ + int ret; + + if (!dm_gpio_is_valid(gpio)) + return -ENOENT; + + acpi_device_write_gpio_desc(ctx, gpio); + ret = *curindex; + (*curindex)++; + + return ret; +} + +int acpi_i2c_fill_ssdt(const struct udevice *dev, struct acpi_ctx *ctx) +{ + int reset_gpio_index = -1, enable_gpio_index = -1, irq_gpio_index = -1; + enum i2c_device_t type = dev_get_driver_data(dev); + struct acpi_i2c_priv *priv = dev_get_priv(dev); + struct acpi_dp *dsd = NULL; + char scope[ACPI_PATH_MAX]; + char name[ACPI_NAME_MAX]; + int tx_state_val; + int curindex = 0; + int ret; + +#ifdef CONFIG_X86 + tx_state_val = PAD_CFG0_TX_STATE; +#elif defined(CONFIG_SANDBOX) + tx_state_val = BIT(7); /* test value */ +#else +#error "Not supported on this architecture" +#endif + ret = acpi_get_name(dev, name); + if (ret) + return log_msg_ret("name", ret); + ret = acpi_device_scope(dev, scope, sizeof(scope)); + if (ret) + return log_msg_ret("scope", ret); + + /* Device */ + acpigen_write_scope(ctx, scope); + acpigen_write_device(ctx, name); + acpigen_write_name_string(ctx, "_HID", priv->hid); + if (type == I2C_DEVICE_HID_OVER_I2C) + acpigen_write_name_string(ctx, "_CID", "PNP0C50"); + acpigen_write_name_integer(ctx, "_UID", priv->uid); + acpigen_write_name_string(ctx, "_DDN", priv->desc); + acpigen_write_sta(ctx, acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name(ctx, "_CRS"); + acpigen_write_resourcetemplate_header(ctx); + acpi_device_write_i2c_dev(ctx, dev); + + /* Use either Interrupt() or GpioInt() */ + if (dm_gpio_is_valid(&priv->irq_gpio)) { + irq_gpio_index = acpi_i2c_write_gpio(ctx, &priv->irq_gpio, + &curindex); + } else { + ret = acpi_device_write_interrupt_irq(ctx, &priv->irq); + if (ret < 0) + return log_msg_ret("irq", ret); + } + + if (acpi_i2c_add_gpios_to_crs(priv)) { + reset_gpio_index = acpi_i2c_write_gpio(ctx, &priv->reset_gpio, + &curindex); + enable_gpio_index = acpi_i2c_write_gpio(ctx, &priv->enable_gpio, + &curindex); + } + acpigen_write_resourcetemplate_footer(ctx); + + /* Wake capabilities */ + if (priv->wake) { + acpigen_write_name_integer(ctx, "_S0W", 4); + acpigen_write_prw(ctx, priv->wake, 3); + } + + /* DSD */ + if (priv->probed || priv->property_count || priv->compat_string || + reset_gpio_index >= 0 || enable_gpio_index >= 0 || + irq_gpio_index >= 0) { + char path[ACPI_PATH_MAX]; + + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + + dsd = acpi_dp_new_table("_DSD"); + if (priv->compat_string) + acpi_dp_add_string(dsd, "compatible", + priv->compat_string); + if (priv->probed) + acpi_dp_add_integer(dsd, "linux,probed", 1); + if (irq_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "irq-gpios", path, + irq_gpio_index, 0, + priv->irq_gpio.flags & + GPIOD_ACTIVE_LOW ? + ACPI_GPIO_ACTIVE_LOW : 0); + if (reset_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "reset-gpios", path, + reset_gpio_index, 0, + priv->reset_gpio.flags & + GPIOD_ACTIVE_LOW ? + ACPI_GPIO_ACTIVE_LOW : 0); + if (enable_gpio_index >= 0) + acpi_dp_add_gpio(dsd, "enable-gpios", path, + enable_gpio_index, 0, + priv->enable_gpio.flags & + GPIOD_ACTIVE_LOW ? + ACPI_GPIO_ACTIVE_LOW : 0); + /* Generic property list is not supported */ + acpi_dp_write(ctx, dsd); + } + + /* Power Resource */ + if (priv->has_power_resource) { + ret = acpi_device_add_power_res(ctx, tx_state_val, + "\\_SB.GPC0", "\\_SB.SPC0", + &priv->reset_gpio, priv->reset_delay_ms, + priv->reset_off_delay_ms, &priv->enable_gpio, + priv->enable_delay_ms, priv->enable_off_delay_ms, + &priv->stop_gpio, priv->stop_delay_ms, + priv->stop_off_delay_ms); + if (ret) + return log_msg_ret("power", ret); + } + if (priv->hid_desc_reg_offset) { + ret = acpi_device_write_dsm_i2c_hid(ctx, + priv->hid_desc_reg_offset); + if (ret) + return log_msg_ret("dsm", ret); + } + + acpigen_pop_len(ctx); /* Device */ + acpigen_pop_len(ctx); /* Scope */ + + return 0; +} + +int acpi_i2c_ofdata_to_platdata(struct udevice *dev) +{ + struct acpi_i2c_priv *priv = dev_get_priv(dev); + + gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset_gpio, + GPIOD_IS_OUT); + gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable_gpio, + GPIOD_IS_OUT); + gpio_request_by_name(dev, "irq-gpios", 0, &priv->irq_gpio, GPIOD_IS_IN); + gpio_request_by_name(dev, "stop-gpios", 0, &priv->stop_gpio, + GPIOD_IS_OUT); + irq_get_by_index(dev, 0, &priv->irq); + priv->hid = dev_read_string(dev, "acpi,hid"); + if (!priv->hid) + return log_msg_ret("hid", -EINVAL); + dev_read_u32(dev, "acpi,uid", &priv->uid); + priv->desc = dev_read_string(dev, "acpi,ddn"); + dev_read_u32(dev, "acpi,wake", &priv->wake); + priv->probed = dev_read_bool(dev, "linux,probed"); + priv->compat_string = dev_read_string(dev, "acpi,compatible"); + priv->has_power_resource = dev_read_bool(dev, + "acpi,has-power-resource"); + dev_read_u32(dev, "hid-descr-addr", &priv->hid_desc_reg_offset); + dev_read_u32(dev, "reset-delay-ms", &priv->reset_delay_ms); + dev_read_u32(dev, "reset-off-delay-ms", &priv->reset_off_delay_ms); + dev_read_u32(dev, "enable-delay-ms", &priv->enable_delay_ms); + dev_read_u32(dev, "enable-off-delay-ms", &priv->enable_off_delay_ms); + dev_read_u32(dev, "stop-delay-ms", &priv->stop_delay_ms); + dev_read_u32(dev, "stop-off-delay-ms", &priv->stop_off_delay_ms); + + return 0; +} + +/* Use name specified in priv or build one from I2C address */ +static int acpi_i2c_get_name(const struct udevice *dev, char *out_name) +{ + struct dm_i2c_chip *chip = dev_get_parent_platdata(dev); + struct acpi_i2c_priv *priv = dev_get_priv(dev); + + snprintf(out_name, ACPI_NAME_MAX, + priv->hid_desc_reg_offset ? "H%03X" : "D%03X", + chip->chip_addr); + + return 0; +} + +struct acpi_ops acpi_i2c_ops = { + .fill_ssdt = acpi_i2c_fill_ssdt, + .get_name = acpi_i2c_get_name, +}; diff --git a/drivers/i2c/acpi_i2c.h b/drivers/i2c/acpi_i2c.h new file mode 100644 index 00000000000..1f4be296016 --- /dev/null +++ b/drivers/i2c/acpi_i2c.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef __ACPI_I2C_H +#define __ACPI_I2C_H + +#include + +extern struct acpi_ops acpi_i2c_ops; + +int acpi_i2c_ofdata_to_platdata(struct udevice *dev); + +#endif diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index 2373aa2ea4c..5c4626b0442 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -9,6 +9,8 @@ #include #include #include +#include +#include #include #include #include @@ -16,6 +18,7 @@ #include #endif #include +#include "acpi_i2c.h" #define I2C_MAX_OFFSET_LEN 4 @@ -749,7 +752,21 @@ UCLASS_DRIVER(i2c_generic) = { .name = "i2c_generic", }; +static const struct udevice_id generic_chip_i2c_ids[] = { + { .compatible = "i2c-chip", .data = I2C_DEVICE_GENERIC }, +#if CONFIG_IS_ENABLED(ACPIGEN) + { .compatible = "hid-over-i2c", .data = I2C_DEVICE_HID_OVER_I2C }, +#endif + { } +}; + U_BOOT_DRIVER(i2c_generic_chip_drv) = { .name = "i2c_generic_chip_drv", .id = UCLASS_I2C_GENERIC, + .of_match = generic_chip_i2c_ids, +#if CONFIG_IS_ENABLED(ACPIGEN) + .ofdata_to_platdata = acpi_i2c_ofdata_to_platdata, + .priv_auto_alloc_size = sizeof(struct acpi_i2c_priv), +#endif + ACPI_OPS_PTR(&acpi_i2c_ops) }; diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h index a5b12217820..1b838fcb857 100644 --- a/include/acpi/acpi_device.h +++ b/include/acpi/acpi_device.h @@ -10,7 +10,9 @@ #define __ACPI_DEVICE_H #include +#include #include +#include #include struct acpi_ctx; @@ -235,6 +237,59 @@ struct acpi_spi { const char *resource; }; +/** + * struct acpi_i2c_priv - Information read from device tree + * + * This is used by devices which want to specify various pieces of ACPI + * information, including power control. It allows a generic function to + * generate the information for ACPI, based on device-tree properties. + * + * @disable_gpio_export_in_crs: Don't export GPIOs in the CRS + * @reset_gpio: GPIO used to assert reset to the device + * @enable_gpio: GPIO used to enable the device + * @stop_gpio: GPIO used to stop the device + * @irq_gpio: GPIO used for interrupt (if @irq is not used) + * @irq: IRQ used for interrupt (if @irq_gpio is not used) + * @hid: _HID value for device (required) + * @uid: _UID value for device + * @desc: _DDN value for device + * @wake: Wake event, e.g. GPE0_DW1_15; 0 if none + * @property_count: Number of other DSD properties (currently always 0) + * @probed: true set set 'linux,probed' property + * @compat_string: Device tree compatible string to report through ACPI + * @has_power_resource: true if this device has a power resource + * @reset_delay_ms: Delay after de-asserting reset, in ms + * @reset_off_delay_ms: Delay after asserting reset (during power off) + * @enable_delay_ms: Delay after asserting enable + * @enable_off_delay_ms: Delay after de-asserting enable (during power off) + * @stop_delay_ms: Delay after de-aserting stop + * @stop_off_delay_ms: Delay after asserting stop (during power off) + * @hid_desc_reg_offset: HID register offset (for Human Interface Devices) + */ +struct acpi_i2c_priv { + bool disable_gpio_export_in_crs; + struct gpio_desc reset_gpio; + struct gpio_desc enable_gpio; + struct gpio_desc irq_gpio; + struct gpio_desc stop_gpio; + struct irq irq; + const char *hid; + u32 uid; + const char *desc; + u32 wake; + u32 property_count; + bool probed; + const char *compat_string; + bool has_power_resource; + u32 reset_delay_ms; + u32 reset_off_delay_ms; + u32 enable_delay_ms; + u32 enable_off_delay_ms; + u32 stop_delay_ms; + u32 stop_off_delay_ms; + u32 hid_desc_reg_offset; +}; + /** * acpi_device_path() - Get the full path to an ACPI device * diff --git a/include/i2c.h b/include/i2c.h index 1d792db454a..880aa8032b7 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -58,6 +58,12 @@ enum i2c_address_mode { I2C_MODE_10_BIT }; +/** enum i2c_device_t - Types of I2C devices, used for compatible strings */ +enum i2c_device_t { + I2C_DEVICE_GENERIC, + I2C_DEVICE_HID_OVER_I2C, +}; + struct udevice; /** * struct dm_i2c_chip - information about an i2c chip @@ -558,6 +564,23 @@ int i2c_emul_find(struct udevice *dev, struct udevice **emulp); */ struct udevice *i2c_emul_get_device(struct udevice *emul); +/* ACPI operations for generic I2C devices */ +extern struct acpi_ops i2c_acpi_ops; + +/** + * acpi_i2c_ofdata_to_platdata() - Read properties intended for ACPI + * + * This reads the generic I2C properties from the device tree, so that these + * can be used to create ACPI information for the device. + * + * See the i2c/generic-acpi.txt binding file for information about the + * properties. + * + * @dev: I2C device to process + * @return 0 if OK, -EINVAL if acpi,hid is not present + */ +int acpi_i2c_ofdata_to_platdata(struct udevice *dev); + #ifndef CONFIG_DM_I2C /* -- cgit v1.3.1 From c9cc37de2c71ebbf953c290144c3efc18145ded9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:03 -0600 Subject: x86: apl: Support writing the IntelGraphicsMem table This table is needed by the Linux graphics driver to handle graphics correctly. Write it to ACPI. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 8 + arch/x86/cpu/apollolake/Kconfig | 1 + arch/x86/cpu/intel_common/Makefile | 4 + arch/x86/cpu/intel_common/intel_opregion.c | 168 ++++++++++++++++++++ arch/x86/include/asm/intel_opregion.h | 247 +++++++++++++++++++++++++++++ arch/x86/lib/fsp/fsp_graphics.c | 32 ++++ include/bloblist.h | 1 + 7 files changed, 461 insertions(+) create mode 100644 arch/x86/cpu/intel_common/intel_opregion.c create mode 100644 arch/x86/include/asm/intel_opregion.h (limited to 'include') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 680f26f1b8e..675a43e3b60 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1001,4 +1001,12 @@ config PCIEX_LENGTH_128MB config PCIEX_LENGTH_64MB bool +config INTEL_GMA_ACPI + bool "Generate ACPI table for Intel GMA graphics" + help + The Intel GMA graphics driver in Linux expects an ACPI table + which describes the layout of the registers and the display + connected to the device. Enable this option to create this + table so that graphics works correctly. + endmenu diff --git a/arch/x86/cpu/apollolake/Kconfig b/arch/x86/cpu/apollolake/Kconfig index 16ac2b3f504..319f12684b7 100644 --- a/arch/x86/cpu/apollolake/Kconfig +++ b/arch/x86/cpu/apollolake/Kconfig @@ -48,6 +48,7 @@ config INTEL_APOLLOLAKE imply CMD_CLK imply CLK_INTEL imply ACPI_GPE + imply INTEL_GMA_ACPI if INTEL_APOLLOLAKE diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 374803b8760..207d5413965 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -9,6 +9,10 @@ obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += report_platform.o obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += mrc.o endif +ifndef CONFIG_SPL_BUILD +obj-$(CONFIG_INTEL_GMA_ACPI) += intel_opregion.o +endif + ifdef CONFIG_INTEL_CAR_CQOS obj-$(CONFIG_TPL_BUILD) += car2.o ifndef CONFIG_SPL_BUILD diff --git a/arch/x86/cpu/intel_common/intel_opregion.c b/arch/x86/cpu/intel_common/intel_opregion.c new file mode 100644 index 00000000000..4e6c64d9aaa --- /dev/null +++ b/arch/x86/cpu/intel_common/intel_opregion.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.c + */ + +#include +#include +#include +#include +#include +#include + +static char vbt_data[8 << 10]; + +static int locate_vbt(char **vbtp, int *sizep) +{ + struct binman_entry vbt; + struct udevice *dev; + u32 vbtsig = 0; + int size; + int ret; + + ret = binman_entry_find("intel-vbt", &vbt); + if (ret) + return log_msg_ret("find VBT", ret); + ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev); + if (ret) + return log_msg_ret("find flash", ret); + size = vbt.size; + if (size > sizeof(vbt_data)) + return log_msg_ret("vbt", -E2BIG); + ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data); + if (ret) + return log_msg_ret("read", ret); + + memcpy(&vbtsig, vbt_data, sizeof(vbtsig)); + if (vbtsig != VBT_SIGNATURE) { + log_err("Missing/invalid signature in VBT data file!\n"); + return -EINVAL; + } + + log_info("Found a VBT of %u bytes\n", size); + *sizep = size; + *vbtp = vbt_data; + + return 0; +} + +/* Write ASLS PCI register and prepare SWSCI register */ +static int intel_gma_opregion_register(struct udevice *dev, ulong opregion) +{ + int sci_reg; + + if (!device_active(dev)) + return -ENOENT; + + /* + * Intel BIOS Specification + * Chapter 5.3.7 "Initialise Hardware State" + */ + dm_pci_write_config32(dev, ASLS, opregion); + + /* + * Atom-based platforms use a combined SMI/SCI register, + * whereas non-Atom platforms use a separate SCI register + */ + if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI)) + sci_reg = SWSMISCI; + else + sci_reg = SWSCI; + + /* + * Intel's Windows driver relies on this: + * Intel BIOS Specification + * Chapter 5.4 "ASL Software SCI Handler" + */ + dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL); + + return 0; +} + +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion) +{ + struct optionrom_vbt *vbt = NULL; + char *vbt_buf; + int vbt_size; + int ret; + + ret = locate_vbt(&vbt_buf, &vbt_size); + if (ret) { + log_err("GMA: VBT couldn't be found\n"); + return log_msg_ret("find vbt", ret); + } + vbt = (struct optionrom_vbt *)vbt_buf; + + memset(opregion, '\0', sizeof(struct igd_opregion)); + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(opregion->header.signature)); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, + ARRAY_SIZE(vbt->coreblock_biosbuild)); + /* Extended VBT support */ + if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) { + struct optionrom_vbt *ext_vbt; + + ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT, + vbt->hdr_vbt_size, + (void **)&ext_vbt); + if (ret) { + log_err("GMA: Unable to add Ext VBT to bloblist\n"); + return log_msg_ret("blob", ret); + } + + memcpy(ext_vbt, vbt, vbt->hdr_vbt_size); + opregion->mailbox3.rvda = (uintptr_t)ext_vbt; + opregion->mailbox3.rvds = vbt->hdr_vbt_size; + } else { + /* Raw VBT size which can fit in gvd1 */ + printf("copy to %p\n", opregion->vbt.gvd1); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size); + } + + /* 8kb */ + opregion->header.size = sizeof(struct igd_opregion) / 1024; + + /* + * Left-shift version field to accommodate Intel Windows driver quirk + * when not using a VBIOS. + * Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver. + * + * No adverse effects when using VBIOS or booting Linux. + */ + opregion->header.version = IGD_OPREGION_VERSION << 24; + + /* We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* Initialise Mailbox 1 */ + opregion->mailbox1.clid = 1; + + /* Initialise Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + /* Write ASLS PCI register and prepare SWSCI register */ + ret = intel_gma_opregion_register(dev, (ulong)opregion); + if (ret) + return log_msg_ret("write asls", ret); + + return 0; +} diff --git a/arch/x86/include/asm/intel_opregion.h b/arch/x86/include/asm/intel_opregion.h new file mode 100644 index 00000000000..fb3e38617e4 --- /dev/null +++ b/arch/x86/include/asm/intel_opregion.h @@ -0,0 +1,247 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Writing IntelGraphicsMem table for ACPI + * + * Copyright 2019 Google LLC + * Modified from coreboot src/soc/intel/gma/opregion.h + */ + +#ifndef _ASM_INTEL_OPREGION_H_ +#define _ASM_INTEL_OPREGION_H_ + +#define VBT_SIGNATURE 0x54425624 + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define SWSMISCI 0xe0 /* SWSMISCI Register */ +#define GSSCIE BIT(0) /* SCI Event trigger */ +#define SMISCISEL BIT(15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +struct __packed opregion_header { + u8 signature[16]; /* Offset 0 OpRegion signature */ + u32 size; /* Offset 16 OpRegion size */ + u32 version; /* Offset 20 OpRegion structure version */ + u8 sbios_version[32]; /* Offset 24 System BIOS build version */ + u8 vbios_version[16]; /* Offset 56 Video BIOS build version */ + u8 driver_version[16]; /* Offset 72 Graphic drvr build version */ + u32 mailboxes; /* Offset 88 Mailboxes supported */ + u32 dmod; /* Offset 92 Driver Model */ + u32 pcon; /* Offset 96 Platform Capabilities */ + u16 dver[16]; /* Offset 100 GOP Version */ + u8 reserved[124]; /* Offset 132 Reserved */ +}; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 BIT(0) +#define IGD_MBOX2 BIT(1) +#define IGD_MBOX3 BIT(2) +#define IGD_MBOX4 BIT(3) +#define IGD_MBOX5 BIT(4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public ACPI methods */ +struct __packed opregion_mailbox1 { + u32 drdy; /* Offset 0 Driver readiness */ + u32 csts; /* Offset 4 Status */ + u32 cevt; /* Offset 8 Current event */ + u8 reserved[20]; /* Offset 12 Reserved */ + u32 didl; /* Offset 32 Supported display device 1 */ + u32 ddl2; /* Offset 36 Supported display device 2 */ + u32 ddl3; /* Offset 40 Supported display device 3 */ + u32 ddl4; /* Offset 44 Supported display device 4 */ + u32 ddl5; /* Offset 48 Supported display device 5 */ + u32 ddl6; /* Offset 52 Supported display device 6 */ + u32 ddl7; /* Offset 56 Supported display device 7 */ + u32 ddl8; /* Offset 60 Supported display device 8 */ + u32 cpdl; /* Offset 64 Currently present display device 1 */ + u32 cpl2; /* Offset 68 Currently present display device 2 */ + u32 cpl3; /* Offset 72 Currently present display device 3 */ + u32 cpl4; /* Offset 76 Currently present display device 4 */ + u32 cpl5; /* Offset 80 Currently present display device 5 */ + u32 cpl6; /* Offset 84 Currently present display device 6 */ + u32 cpl7; /* Offset 88 Currently present display device 7 */ + u32 cpl8; /* Offset 92 Currently present display device 8 */ + u32 cadl; /* Offset 96 Currently active display device 1 */ + u32 cal2; /* Offset 100 Currently active display device 2 */ + u32 cal3; /* Offset 104 Currently active display device 3 */ + u32 cal4; /* Offset 108 Currently active display device 4 */ + u32 cal5; /* Offset 112 Currently active display device 5 */ + u32 cal6; /* Offset 116 Currently active display device 6 */ + u32 cal7; /* Offset 120 Currently active display device 7 */ + u32 cal8; /* Offset 124 Currently active display device 8 */ + u32 nadl; /* Offset 128 Next active device 1 */ + u32 ndl2; /* Offset 132 Next active device 2 */ + u32 ndl3; /* Offset 136 Next active device 3 */ + u32 ndl4; /* Offset 140 Next active device 4 */ + u32 ndl5; /* Offset 144 Next active device 5 */ + u32 ndl6; /* Offset 148 Next active device 6 */ + u32 ndl7; /* Offset 152 Next active device 7 */ + u32 ndl8; /* Offset 156 Next active device 8 */ + u32 aslp; /* Offset 160 ASL sleep timeout */ + u32 tidx; /* Offset 164 Toggle table index */ + u32 chpd; /* Offset 168 Current hot plug enable indicator */ + u32 clid; /* Offset 172 Current lid state indicator */ + u32 cdck; /* Offset 176 Current docking state indicator */ + u32 sxsw; /* Offset 180 Display Switch notification on Sx State + * resume + */ + u32 evts; /* Offset 184 Events supported by ASL */ + u32 cnot; /* Offset 188 Current OS Notification */ + u32 nrdy; /* Offset 192 Reasons for DRDY = 0 */ + u32 ddl9; /* Offset 196 Extended Supported display device 1 */ + u32 dd10; /* Offset 200 Extended Supported display device 2 */ + u32 dd11; /* Offset 204 Extended Supported display device 3 */ + u32 dd12; /* Offset 208 Extended Supported display device 4 */ + u32 dd13; /* Offset 212 Extended Supported display device 5 */ + u32 dd14; /* Offset 216 Extended Supported display device 6 */ + u32 dd15; /* Offset 220 Extended Supported display device 7 */ + u32 cpl9; /* Offset 224 Extended Currently present device 1 */ + u32 cp10; /* Offset 228 Extended Currently present device 2 */ + u32 cp11; /* Offset 232 Extended Currently present device 3 */ + u32 cp12; /* Offset 236 Extended Currently present device 4 */ + u32 cp13; /* Offset 240 Extended Currently present device 5 */ + u32 cp14; /* Offset 244 Extended Currently present device 6 */ + u32 cp15; /* Offset 248 Extended Currently present device 7 */ + u8 reserved2[4]; /* Offset 252 Reserved 4 bytes */ +}; + +/* mailbox 2: software sci interface */ +struct __packed opregion_mailbox2 { + u32 scic; /* Offset 0 Software SCI function number parameters */ + u32 parm; /* Offset 4 Software SCI function number parameters */ + u32 dslp; /* Offset 8 Driver sleep timeout */ + u8 reserved[244]; /* Offset 12 Reserved */ +}; + +/* mailbox 3: power conservation */ +struct __packed opregion_mailbox3 { + u32 ardy; /* Offset 0 Driver readiness */ + u32 aslc; /* Offset 4 ASLE interrupt command / status */ + u32 tche; /* Offset 8 Technology enabled indicator */ + u32 alsi; /* Offset 12 Current ALS illuminance reading */ + u32 bclp; /* Offset 16 Backlight britness to set */ + u32 pfit; /* Offset 20 Panel fitting Request */ + u32 cblv; /* Offset 24 Brightness Current State */ + /* Offset 28 Backlight Brightness Level Duty Cycle Mapping Table */ + u16 bclm[20]; + u32 cpfm; /* Offset 68 Panel Fitting Current Mode */ + u32 epfm; /* Offset 72 Enabled Panel Fitting Modes */ + u8 plut[74]; /* Offset 76 Panel Look Up Table */ + /* Offset 150 PWM Frequency and Minimum Brightness */ + u32 pfmb; + u32 ccdv; /* Offset 154 Color Correction Default Values */ + u32 pcft; /* Offset 158 Power Conservation Features */ + u32 srot; /* Offset 162 Supported Rotation angle */ + u32 iuer; /* Offset 166 Intel Ultrabook Event Register */ + u64 fdsp; /* Offset 170 FFS Display Physical address */ + u32 fdss; /* Offset 178 FFS Display Size */ + u32 stat; /* Offset 182 State Indicator */ + /* + * Offset 186 (Igd opregion offset 0x3BAh) + * Physical address of Raw VBT data + */ + u64 rvda; + /* Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data */ + u32 rvds; + u8 reserved[58]; /* Offset 198 Reserved */ +}; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID BIT(31) +#define IGD_WORD_FIELD_VALID BIT(15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +struct __packed opregion_vbt { + u8 gvd1[6 << 10]; +}; + +/* Mailbox 5: BIOS to Driver Notification Extension */ +struct __packed opregion_mailbox5 { + u32 phed; /* Offset 7168 Panel Header */ + u8 bddc[256]; /* Offset 7172 Panel EDID */ + u8 reserved[764]; /* Offset 7428 764 bytes */ +}; + +/* IGD OpRegion */ +struct __packed igd_opregion { + struct opregion_header header; + struct opregion_mailbox1 mailbox1; + struct opregion_mailbox2 mailbox2; + struct opregion_mailbox3 mailbox3; + struct opregion_vbt vbt; + struct opregion_mailbox5 mailbox5; +}; + +/* Intel Video BIOS (Option ROM) */ +struct __packed optionrom_header { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +}; + +#define OPROM_SIGNATURE 0xaa55 + +struct __packed optionrom_pcir { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +}; + +struct __packed optionrom_vbt { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +}; + +/** + * intel_gma_init_igd_opregion() - Initialise IGD OpRegion + * + * This is called from ACPI code and OS drivers + * + * @return 0 if OK, -ve on error + */ +int intel_gma_init_igd_opregion(struct udevice *dev, + struct igd_opregion *opregion); + +#endif /* _ASM_INTEL_OPREGION_H_ */ diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index e8c1e07af1c..858d7942fed 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -3,14 +3,19 @@ * Copyright (C) 2017, Bin Meng */ +#define LOG_CATEGORY UCLASS_VIDEO + #include #include #include #include #include #include +#include #include +#include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -127,6 +132,32 @@ static int fsp_video_bind(struct udevice *dev) return 0; } +#ifdef CONFIG_INTEL_GMA_ACPI +static int fsp_video_acpi_write_tables(const struct udevice *dev, + struct acpi_ctx *ctx) +{ + struct igd_opregion *opregion; + int ret; + + printf("ACPI: * IGD OpRegion\n"); + opregion = (struct igd_opregion *)ctx->current; + + ret = intel_gma_init_igd_opregion((struct udevice *)dev, opregion); + if (ret) + return ret; + + acpi_inc_align(ctx, sizeof(struct igd_opregion)); + + return 0; +} +#endif + +struct acpi_ops fsp_video_acpi_ops = { +#ifdef CONFIG_INTEL_GMA_ACPI + .write_tables = fsp_video_acpi_write_tables, +#endif +}; + static const struct udevice_id fsp_video_ids[] = { { .compatible = "fsp-fb" }, { } @@ -139,6 +170,7 @@ U_BOOT_DRIVER(fsp_video) = { .bind = fsp_video_bind, .probe = fsp_video_probe, .flags = DM_FLAG_PRE_RELOC, + ACPI_OPS_PTR(&fsp_video_acpi_ops) }; static struct pci_device_id fsp_video_supported[] = { diff --git a/include/bloblist.h b/include/bloblist.h index bbe0a35d5a2..7d8480548e0 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -32,6 +32,7 @@ enum bloblist_tag_t { * Sleeping table. This forms part of the ACPI tables passed to Linux. */ BLOBLISTT_ACPI_GNVS, + BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ }; /** -- cgit v1.3.1 From 10552377d44045fbf1a30615b2c2d1d4ae5d03ec Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:06 -0600 Subject: x86: apl: Add power-management definitions Add SCI and power-state definitions required by ACPI tables. Fix the license to match the original source file. Als update the guard on acpi_pmc.h to avoid an error when buiding ASL. Signed-off-by: Simon Glass --- arch/x86/include/asm/arch-apollolake/pm.h | 40 ++++++++++++++++++++++++++++++- include/power/acpi_pmc.h | 4 ++-- 2 files changed, 41 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/arch/x86/include/asm/arch-apollolake/pm.h b/arch/x86/include/asm/arch-apollolake/pm.h index 6718290c4fe..9a8d971e910 100644 --- a/arch/x86/include/asm/arch-apollolake/pm.h +++ b/arch/x86/include/asm/arch-apollolake/pm.h @@ -1,12 +1,15 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao for Intel Corp.) + * Copyright 2019 Google LLC */ #ifndef _ASM_ARCH_PM_H #define _ASM_ARCH_PM_H +#include + #define PMC_GPE_SW_31_0 0 #define PMC_GPE_SW_63_32 1 #define PMC_GPE_NW_31_0 3 @@ -16,4 +19,39 @@ #define PMC_GPE_N_63_32 7 #define PMC_GPE_W_31_0 9 +#define IRQ_REG 0x106c +#define SCI_IRQ_SHIFT 24 +#define SCI_IRQ_MASK (0xff << SCI_IRQ_SHIFT) +#define SCIS_IRQ9 9 +#define SCIS_IRQ10 10 +#define SCIS_IRQ11 11 +#define SCIS_IRQ20 20 +#define SCIS_IRQ21 21 +#define SCIS_IRQ22 22 +#define SCIS_IRQ23 23 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +#ifndef __ASSEMBLY__ +/* Track power state from reset to log events */ +struct __packed chipset_power_state { + u16 pm1_sts; + u16 pm1_en; + u32 pm1_cnt; + u32 gpe0_sts[GPE0_REG_MAX]; + u32 gpe0_en[GPE0_REG_MAX]; + u16 tco1_sts; + u16 tco2_sts; + u32 prsts; + u32 gen_pmcon1; + u32 gen_pmcon2; + u32 gen_pmcon3; + u32 prev_sleep_state; +}; +#endif /* !__ASSEMBLY__ */ + #endif diff --git a/include/power/acpi_pmc.h b/include/power/acpi_pmc.h index 5fbf7451369..222288b71a4 100644 --- a/include/power/acpi_pmc.h +++ b/include/power/acpi_pmc.h @@ -6,7 +6,7 @@ #ifndef __ACPI_PMC_H #define __ACPI_PMC_H -#ifndef __ACPI__ +#ifndef __ASSEMBLY__ enum { GPE0_REG_MAX = 4, @@ -194,6 +194,6 @@ void pmc_dump_info(struct udevice *dev); */ int pmc_gpe_init(struct udevice *dev); -#endif /* !__ACPI__ */ +#endif /* !__ASSEMBLY__ */ #endif -- cgit v1.3.1 From 6c0da2da7ca9f4bf75e384dc679bcb4575a9940e Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:08 -0600 Subject: x86: Add a few common Intel CPU functions Add functions to query CPU information, needed for ACPI. Signed-off-by: Simon Glass --- arch/x86/cpu/intel_common/cpu.c | 64 +++++++++++++++++++++++++++++++++++++++ arch/x86/include/asm/cpu_common.h | 49 ++++++++++++++++++++++++++++++ include/acpi/acpigen.h | 12 ++++++++ 3 files changed, 125 insertions(+) (limited to 'include') diff --git a/arch/x86/cpu/intel_common/cpu.c b/arch/x86/cpu/intel_common/cpu.c index 509730aea96..cb4ef84013a 100644 --- a/arch/x86/cpu/intel_common/cpu.c +++ b/arch/x86/cpu/intel_common/cpu.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -227,3 +228,66 @@ void cpu_set_eist(bool eist_status) msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP; msr_write(MSR_IA32_MISC_ENABLE, msr); } + +int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +int cpu_get_min_ratio(void) +{ + msr_t msr; + + /* Get bus ratio limits and calculate clock speeds */ + msr = msr_read(MSR_PLATFORM_INFO); + + return (msr.hi >> 8) & 0xff; /* Max Efficiency Ratio */ +} + +int cpu_get_max_ratio(void) +{ + u32 ratio_max; + msr_t msr; + + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = msr_read(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = msr_read(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + + return ratio_max; +} + +int cpu_get_bus_clock_khz(void) +{ + /* + * CPU bus clock is set by default here to 100MHz. This function returns + * the bus clock in KHz. + */ + return INTEL_BCLK_MHZ * 1000; +} + +int cpu_get_power_max(void) +{ + int power_unit; + msr_t msr; + + msr = msr_read(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = msr_read(MSR_PKG_POWER_SKU); + + return (msr.lo & 0x7fff) * 1000 / power_unit; +} + +int cpu_get_max_turbo_ratio(void) +{ + msr_t msr; + + msr = msr_read(MSR_TURBO_RATIO_LIMIT); + + return msr.lo & 0xff; +} diff --git a/arch/x86/include/asm/cpu_common.h b/arch/x86/include/asm/cpu_common.h index cdd99a90b76..a7b7112d417 100644 --- a/arch/x86/include/asm/cpu_common.h +++ b/arch/x86/include/asm/cpu_common.h @@ -128,4 +128,53 @@ void cpu_set_eist(bool eist_status); */ void cpu_set_p_state_to_turbo_ratio(void); +/** + * cpu_get_coord_type() - Get the type of coordination for P-State transition + * + * See ACPI spec v6.3 section 8.4.6.5 _PSD (P-State Dependency) + * + * @return HW_ALL (always) + */ +int cpu_get_coord_type(void); + +/** + * cpu_get_min_ratio() - get minimum support frequency ratio for CPU + * + * @return minimum ratio + */ +int cpu_get_min_ratio(void); + +/** + * cpu_get_max_ratio() - get nominal TDP ration or max non-turbo ratio + * + * If a nominal TDP ratio is available, it is returned. Otherwise this returns + * the maximum non-turbo frequency ratio for this processor + * + * @return max ratio + */ +int cpu_get_max_ratio(void); + +/** + * cpu_get_bus_clock_khz() - Get the bus clock frequency in KHz + * + * This is the value the clock ratio is multiplied with + * + * @return bus-block frequency in KHz + */ +int cpu_get_bus_clock_khz(void); + +/** + * cpu_get_power_max() - Get maximum CPU TDP + * + * @return maximum CPU TDP (Thermal-design power) in mW + */ +int cpu_get_power_max(void); + +/** + * cpu_get_max_turbo_ratio() - Get maximum turbo ratio + * + * @return maximum ratio + */ +int cpu_get_max_turbo_ratio(void); + #endif diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 34b3115bc9c..c412898169e 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -73,6 +73,18 @@ enum { RETURN_OP = 0xa4, }; +/** + * enum psd_coord - Coordination types for P-states + * + * The type of coordination that exists (hardware) or is required (software) as + * a result of the underlying hardware dependency + */ +enum psd_coord { + SW_ALL = 0xfc, + SW_ANY = 0xfd, + HW_ALL = 0xfe +}; + /** * acpigen_get_current() - Get the current ACPI code output pointer * -- cgit v1.3.1 From d2628984b7831b26d8f9ac25c966d6151df7a929 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:09 -0600 Subject: x86: acpi: Support generation of the HPET table Add an implementation of the HPET (High Precision Event Timer) ACPI table. Since this is x86-specific, put it in an x86-specific file Signed-off-by: Simon Glass --- arch/x86/include/asm/acpi_table.h | 10 +++++++ arch/x86/lib/acpi_table.c | 59 +++++++++++++++++++++++++++++++++++++++ include/acpi/acpi_table.h | 31 ++++++++++++++------ 3 files changed, 91 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 733085c1785..7047ee6c772 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -36,6 +36,16 @@ int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u32 acpi_fill_mcfg(u32 current); u32 acpi_fill_csrt(u32 current); +/** + * acpi_write_hpet() - Write out a HPET table + * + * Write out the table for High-Precision Event Timers + * + * @ctx: Current ACPI context + * @return 0 if OK, -ve on error + */ +int acpi_write_hpet(struct acpi_ctx *ctx); + /** * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table * diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 36ef3e5f0b7..0080c96cfe7 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -529,3 +529,62 @@ ulong acpi_get_rsdp_addr(void) { return acpi_rsdp_addr; } + +/** + * acpi_write_hpet() - Write out a HPET table + * + * Write out the table for High-Precision Event Timers + * + * @hpet: Place to put HPET table + */ +static int acpi_create_hpet(struct acpi_hpet *hpet) +{ + struct acpi_table_header *header = &hpet->header; + struct acpi_gen_regaddr *addr = &hpet->addr; + + /* + * See IA-PC HPET (High Precision Event Timers) Specification v1.0a + * https://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/software-developers-hpet-spec-1-0a.pdf + */ + memset((void *)hpet, '\0', sizeof(struct acpi_hpet)); + + /* Fill out header fields. */ + acpi_fill_header(header, "HPET"); + + header->aslc_revision = ASL_REVISION; + header->length = sizeof(struct acpi_hpet); + header->revision = acpi_get_table_revision(ACPITAB_HPET); + + /* Fill out HPET address */ + addr->space_id = 0; /* Memory */ + addr->bit_width = 64; + addr->bit_offset = 0; + addr->addrl = CONFIG_HPET_ADDRESS & 0xffffffff; + addr->addrh = ((unsigned long long)CONFIG_HPET_ADDRESS) >> 32; + + hpet->id = *(u32 *)CONFIG_HPET_ADDRESS; + hpet->number = 0; + hpet->min_tick = 0; /* HPET_MIN_TICKS */ + + header->checksum = table_compute_checksum(hpet, + sizeof(struct acpi_hpet)); + + return 0; +} + +int acpi_write_hpet(struct acpi_ctx *ctx) +{ + struct acpi_hpet *hpet; + int ret; + + log_debug("ACPI: * HPET\n"); + + hpet = ctx->current; + acpi_inc_align(ctx, sizeof(struct acpi_hpet)); + acpi_create_hpet(hpet); + ret = acpi_add_table(ctx, hpet); + if (ret) + return log_msg_ret("add", ret); + + return 0; +} diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index fe9b29f3f82..f8140446a59 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -20,6 +20,9 @@ #define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ #define ASLC_ID "INTL" /* Intel ASL Compiler */ +/* TODO(sjg@chromium.org): Figure out how to get compiler revision */ +#define ASL_REVISION 0 + #define ACPI_RSDP_REV_ACPI_1_0 0 #define ACPI_RSDP_REV_ACPI_2_0 2 @@ -56,6 +59,15 @@ struct __packed acpi_table_header { u32 aslc_revision; /* ASL compiler revision number */ }; +struct acpi_gen_regaddr { + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 access_size; /* Access size */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ +}; + /* A maximum number of 32 ACPI tables ought to be enough for now */ #define MAX_ACPI_TABLES 32 @@ -71,6 +83,16 @@ struct acpi_xsdt { u64 entry[MAX_ACPI_TABLES]; }; +/* HPET timers */ +struct __packed acpi_hpet { + struct acpi_table_header header; + u32 id; + struct acpi_gen_regaddr addr; + u8 number; + u16 min_tick; + u8 attributes; +}; + /* FADT Preferred Power Management Profile */ enum acpi_pm_profile { ACPI_PM_UNSPECIFIED = 0, @@ -138,15 +160,6 @@ enum acpi_address_space_size { ACPI_ACCESS_SIZE_QWORD_ACCESS }; -struct acpi_gen_regaddr { - u8 space_id; /* Address space ID */ - u8 bit_width; /* Register size in bits */ - u8 bit_offset; /* Register bit offset */ - u8 access_size; /* Access size */ - u32 addrl; /* Register address, low 32 bits */ - u32 addrh; /* Register address, high 32 bits */ -}; - /* FADT (Fixed ACPI Description Table) */ struct __packed acpi_fadt { struct acpi_table_header header; -- cgit v1.3.1 From f37979e7b75e1290e9756c3e964a85ef8b10c3c7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:10 -0600 Subject: x86: acpi: Support generation of the DBG2 table Add an implementation of the DBG2 (Debug Port Table 2) ACPI table. Adjust one of the header includes to be in the correct order, before adding more. Note that the DBG2 table is generic but the PCI UART is x86-specific at present since it assumes an ns16550 UART. It can be generalised later if necessary. Signed-off-by: Simon Glass --- arch/x86/include/asm/acpi_table.h | 11 +++++++ arch/x86/lib/acpi_table.c | 41 +++++++++++++++++++++++++ include/acpi/acpi_table.h | 40 ++++++++++++++++++++++++ lib/acpi/acpi_table.c | 64 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 156 insertions(+) (limited to 'include') diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 7047ee6c772..1b7ff509516 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -46,6 +46,17 @@ u32 acpi_fill_csrt(u32 current); */ int acpi_write_hpet(struct acpi_ctx *ctx); +/** + * acpi_write_dbg2_pci_uart() - Write out a DBG2 table + * + * @ctx: Current ACPI context + * @dev: Debug UART device to describe + * @access_size: Access size for UART (e.g. ACPI_ACCESS_SIZE_DWORD_ACCESS) + * @return 0 if OK, -ve on error + */ +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size); + /** * acpi_create_gnvs() - Create a GNVS (Global Non Volatile Storage) table * diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0080c96cfe7..e257c789838 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -588,3 +589,43 @@ int acpi_write_hpet(struct acpi_ctx *ctx) return 0; } + +int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, + uint access_size) +{ + struct acpi_dbg2_header *dbg2 = ctx->current; + char path[ACPI_PATH_MAX]; + struct acpi_gen_regaddr address; + phys_addr_t addr; + int ret; + + if (!device_active(dev)) { + log_info("Device not enabled\n"); + return -EACCES; + } + /* + * PCI devices don't remember their resource allocation information in + * U-Boot at present. We assume that MMIO is used for the UART and that + * the address space is 32 bytes: ns16550 uses 8 registers of up to + * 32-bits each. This is only for debugging so it is not a big deal. + */ + addr = dm_pci_read_bar32(dev, 0); + printf("UART addr %lx\n", (ulong)addr); + + memset(&address, '\0', sizeof(address)); + address.space_id = ACPI_ADDRESS_SPACE_MEMORY; + address.addrl = (uint32_t)addr; + address.addrh = (uint32_t)((addr >> 32) & 0xffffffff); + address.access_size = access_size; + + ret = acpi_device_path(dev, path, sizeof(path)); + if (ret) + return log_msg_ret("path", ret); + acpi_create_dbg2(dbg2, ACPI_DBG2_SERIAL_PORT, + ACPI_DBG2_16550_COMPATIBLE, &address, 0x1000, path); + + acpi_inc_align(ctx, dbg2->header.length); + acpi_add_table(ctx, dbg2); + + return 0; +} diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index f8140446a59..c826a797f5b 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -448,6 +448,29 @@ struct __packed acpi_dmar { #define ACPI_DBG2_UNKNOWN 0x00FF +/* DBG2: Microsoft Debug Port Table 2 header */ +struct __packed acpi_dbg2_header { + struct acpi_table_header header; + u32 devices_offset; + u32 devices_count; +}; + +/* DBG2: Microsoft Debug Port Table 2 device entry */ +struct __packed acpi_dbg2_device { + u8 revision; + u16 length; + u8 address_count; + u16 namespace_string_length; + u16 namespace_string_offset; + u16 oem_data_length; + u16 oem_data_offset; + u16 port_type; + u16 port_subtype; + u8 reserved[2]; + u16 base_address_offset; + u16 address_size_offset; +}; + /* SPCR (Serial Port Console Redirection table) */ struct __packed acpi_spcr { struct acpi_table_header header; @@ -522,6 +545,23 @@ int acpi_get_table_revision(enum acpi_tables table); */ int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags); +/** + * acpi_create_dbg2() - Create a DBG2 table + * + * This table describes how to access the debug UART + * + * @dbg2: Place to put information + * @port_type: Serial port type (see ACPI_DBG2_...) + * @port_subtype: Serial port sub-type (see ACPI_DBG2_...) + * @address: ACPI address of port + * @address_size: Size of address space + * @device_path: Path of device (created using acpi_device_path()) + */ +void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, + int port_type, int port_subtype, + struct acpi_gen_regaddr *address, uint32_t address_size, + const char *device_path); + /** * acpi_fill_header() - Set up a new table header * diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index acc55e7fad6..908d8903893 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -264,3 +264,67 @@ void acpi_setup_base_tables(struct acpi_ctx *ctx, void *start) */ acpi_align64(ctx); } + +void acpi_create_dbg2(struct acpi_dbg2_header *dbg2, + int port_type, int port_subtype, + struct acpi_gen_regaddr *address, u32 address_size, + const char *device_path) +{ + uintptr_t current; + struct acpi_dbg2_device *device; + u32 *dbg2_addr_size; + struct acpi_table_header *header; + size_t path_len; + const char *path; + char *namespace; + + /* Fill out header fields. */ + current = (uintptr_t)dbg2; + memset(dbg2, '\0', sizeof(struct acpi_dbg2_header)); + header = &dbg2->header; + + header->revision = acpi_get_table_revision(ACPITAB_DBG2); + acpi_fill_header(header, "DBG2"); + header->aslc_revision = ASL_REVISION; + + /* One debug device defined */ + dbg2->devices_offset = sizeof(struct acpi_dbg2_header); + dbg2->devices_count = 1; + current += sizeof(struct acpi_dbg2_header); + + /* Device comes after the header */ + device = (struct acpi_dbg2_device *)current; + memset(device, 0, sizeof(struct acpi_dbg2_device)); + current += sizeof(struct acpi_dbg2_device); + + device->revision = 0; + device->address_count = 1; + device->port_type = port_type; + device->port_subtype = port_subtype; + + /* Base Address comes after device structure */ + memcpy((void *)current, address, sizeof(struct acpi_gen_regaddr)); + device->base_address_offset = current - (uintptr_t)device; + current += sizeof(struct acpi_gen_regaddr); + + /* Address Size comes after address structure */ + dbg2_addr_size = (uint32_t *)current; + device->address_size_offset = current - (uintptr_t)device; + *dbg2_addr_size = address_size; + current += sizeof(uint32_t); + + /* Namespace string comes last, use '.' if not provided */ + path = device_path ? : "."; + /* Namespace string length includes NULL terminator */ + path_len = strlen(path) + 1; + namespace = (char *)current; + device->namespace_string_length = path_len; + device->namespace_string_offset = current - (uintptr_t)device; + strncpy(namespace, path, path_len); + current += path_len; + + /* Update structure lengths and checksum */ + device->length = current - (uintptr_t)device; + header->length = current - (uintptr_t)dbg2; + header->checksum = table_compute_checksum(dbg2, header->length); +} -- cgit v1.3.1 From 15403289e5ddb0d777f95f5836add1316e2d9ae2 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:11 -0600 Subject: acpi: Add support for generating processor tables ACPI has a number of CPU-related tables. Add utility functions to write out the basic packages. Signed-off-by: Simon Glass --- include/acpi/acpigen.h | 39 ++++++++++++++++++ lib/acpi/acpigen.c | 55 +++++++++++++++++++++++++ test/dm/acpigen.c | 107 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 201 insertions(+) (limited to 'include') diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index c412898169e..3a2c6339d5e 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -64,7 +64,9 @@ enum { OR_OP = 0x7d, NOT_OP = 0x80, DEVICE_OP = 0x82, + PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, + NOTIFY_OP = 0x86, LEQUAL_OP = 0x93, TO_BUFFER_OP = 0x96, TO_INTEGER_OP = 0x99, @@ -777,4 +779,41 @@ void acpigen_write_dsm_uuid_end(struct acpi_ctx *ctx); */ void acpigen_write_dsm_end(struct acpi_ctx *ctx); +/** + * acpigen_write_processor() - Write a Processor package + * + * This emits a Processor package header with the required information. The + * caller must complete the information and call acpigen_pop_len() at the end + * + * @ctx: ACPI context pointer + * @cpuindex: CPU number + * @pblock_addr: PBlk system IO address + * @pblock_len: PBlk length + */ +void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex, + u32 pblock_addr, uint pblock_len); + +/** + * acpigen_write_processor_package() - Write a package containing the processors + * + * The package containins the name of each processor in the SoC + * + * @ctx: ACPI context pointer + * @name: Package name (.e.g "PPKG") + * @first_core: Number of the first core (e.g. 0) + * @core_count: Number of cores (e.g. 4) + */ +void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name, + uint first_core, uint core_count); + +/** + * acpigen_write_processor_cnot() - Write a processor notification method + * + * This writes a method that notifies all CPU cores + * + * @ctx: ACPI context pointer + * @num_cores: Number of CPU cores + */ +void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores); + #endif diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index d859f378413..b9985075cde 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -17,6 +17,9 @@ #include #include +/* CPU path format */ +#define ACPI_CPU_STRING "\\_PR.CP%02d" + u8 *acpigen_get_current(struct acpi_ctx *ctx) { return ctx->current; @@ -340,6 +343,58 @@ void acpigen_write_method_serialized(struct acpi_ctx *ctx, const char *name, ACPI_METHOD_SERIALIZED_MASK); } +void acpigen_write_processor(struct acpi_ctx *ctx, uint cpuindex, + u32 pblock_addr, uint pblock_len) +{ + /* + * Processor (\_PR.CPnn, cpuindex, pblock_addr, pblock_len) + * { + */ + char pscope[16]; + + acpigen_emit_ext_op(ctx, PROCESSOR_OP); + acpigen_write_len_f(ctx); + + snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, cpuindex); + acpigen_emit_namestring(ctx, pscope); + acpigen_emit_byte(ctx, cpuindex); + acpigen_emit_dword(ctx, pblock_addr); + acpigen_emit_byte(ctx, pblock_len); +} + +void acpigen_write_processor_package(struct acpi_ctx *ctx, + const char *const name, + const uint first_core, + const uint core_count) +{ + uint i; + char pscope[16]; + + acpigen_write_name(ctx, name); + acpigen_write_package(ctx, core_count); + for (i = first_core; i < first_core + core_count; ++i) { + snprintf(pscope, sizeof(pscope), ACPI_CPU_STRING, i); + acpigen_emit_namestring(ctx, pscope); + } + acpigen_pop_len(ctx); +} + +void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores) +{ + int core_id; + + acpigen_write_method(ctx, "\\_PR.CNOT", 1); + for (core_id = 0; core_id < num_cores; core_id++) { + char buffer[30]; + + snprintf(buffer, sizeof(buffer), ACPI_CPU_STRING, core_id); + acpigen_emit_byte(ctx, NOTIFY_OP); + acpigen_emit_namestring(ctx, buffer); + acpigen_emit_byte(ctx, ARG0_OP); + } + acpigen_pop_len(ctx); +} + void acpigen_write_device(struct acpi_ctx *ctx, const char *name) { acpigen_emit_ext_op(ctx, DEVICE_OP); diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 62d48dc419c..74b7e23aab3 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -1343,3 +1343,110 @@ static int dm_test_acpi_write_i2c_dsm(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_i2c_dsm, 0); + +/* Test emitting a processor */ +static int dm_test_acpi_write_processor(struct unit_test_state *uts) +{ + const int cpuindex = 6; + const u32 pblock_addr = 0x12345600; + const u32 pblock_len = 0x60; + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_processor(ctx, cpuindex, pblock_addr, pblock_len); + acpigen_pop_len(ctx); + + ut_asserteq(EXT_OP_PREFIX, *ptr++); + ut_asserteq(PROCESSOR_OP, *ptr++); + ut_asserteq(0x13, acpi_test_get_length(ptr)); + ptr += 3; + ut_asserteq_strn("\\._PR_CP06", (char *)ptr); + ptr += 10; + ut_asserteq(cpuindex, *ptr++); + ut_asserteq(pblock_addr, get_unaligned((u32 *)ptr)); + ptr += 4; + ut_asserteq(pblock_len, *ptr++); + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_processor, 0); + +/* Test emitting a processor package */ +static int dm_test_acpi_write_processor_package(struct unit_test_state *uts) +{ + const int core_count = 3; + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_processor_package(ctx, "XCPU", 0, core_count); + + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("XCPU", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(core_count, *ptr++); + + ut_asserteq_strn("\\._PR_CP00", (char *)ptr); + ptr += 10; + ut_asserteq_strn("\\._PR_CP01", (char *)ptr); + ptr += 10; + ut_asserteq_strn("\\._PR_CP02", (char *)ptr); + ptr += 10; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_processor_package, 0); + +/* Test emitting a processor notification package */ +static int dm_test_acpi_write_processor_cnot(struct unit_test_state *uts) +{ + const int core_count = 3; + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_processor_cnot(ctx, core_count); + + ut_asserteq(METHOD_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq_strn("\\._PR_CNOT", (char *)ptr); + ptr += 10; + ut_asserteq(1, *ptr++); + + ut_asserteq(NOTIFY_OP, *ptr++); + ut_asserteq_strn("\\._PR_CP00", (char *)ptr); + ptr += 10; + ut_asserteq(ARG0_OP, *ptr++); + ut_asserteq(NOTIFY_OP, *ptr++); + ut_asserteq_strn("\\._PR_CP01", (char *)ptr); + ptr += 10; + ut_asserteq(ARG0_OP, *ptr++); + ut_asserteq(NOTIFY_OP, *ptr++); + ut_asserteq_strn("\\._PR_CP02", (char *)ptr); + ptr += 10; + ut_asserteq(ARG0_OP, *ptr++); + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_processor_cnot, 0); -- cgit v1.3.1 From 350c7f52b93c5612dd3d53966bd54cb68b94d80b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:13 -0600 Subject: acpi: Add more support for generating processor tables This adds tables relating to P-States and C-States. Signed-off-by: Simon Glass --- include/acpi/acpigen.h | 162 +++++++++++++++++++++++++++ lib/acpi/acpigen.c | 167 ++++++++++++++++++++++++++++ test/dm/acpigen.c | 294 +++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 623 insertions(+) (limited to 'include') diff --git a/include/acpi/acpigen.h b/include/acpi/acpigen.h index 3a2c6339d5e..976f4dbb9af 100644 --- a/include/acpi/acpigen.h +++ b/include/acpi/acpigen.h @@ -10,8 +10,10 @@ #ifndef __ACPI_ACPIGEN_H #define __ACPI_ACPIGEN_H +#include #include +struct acpi_cstate; struct acpi_ctx; struct acpi_gen_regaddr; struct acpi_gpio; @@ -87,6 +89,53 @@ enum psd_coord { HW_ALL = 0xfe }; +/** + * enum csd_coord - Coordination types for C-states + * + * The type of coordination that exists (hardware) or is required (software) as + * a result of the underlying hardware dependency + */ +enum csd_coord { + CSD_HW_ALL = 0xfe, +}; + +/** + * struct acpi_cstate - Information about a C-State + * + * @ctype: C State type (1=C1, 2=C2, 3=C3) + * @latency: Worst-case latency to enter and exit the C State (in uS) + * @power: Average power consumption of the processor when in this C-State (mW) + * @resource: Register to read to place the processor in this state + */ +struct acpi_cstate { + uint ctype; + uint latency; + uint power; + struct acpi_gen_regaddr resource; +}; + +/** + * struct acpi_tstate - Information about a Throttling Supported State + * + * See ACPI v6.3 section 8.4.5.2: _TSS (Throttling Supported States) + * + * @percent: Percent of the core CPU operating frequency that will be + * available when this throttling state is invoked + * @power: Throttling state’s maximum power dissipation (mw) + * @latency: Worst-case latency (uS) that the CPU is unavailable during a + * transition from any throttling state to this throttling state + * @control: Value to be written to the Processor Control Register + * (THROTTLE_CTRL) to initiate a transition to this throttling state + * @status: Value in THROTTLE_STATUS when in this state + */ +struct acpi_tstate { + uint percent; + uint power; + uint latency; + uint control; + uint status; +}; + /** * acpigen_get_current() - Get the current ACPI code output pointer * @@ -816,4 +865,117 @@ void acpigen_write_processor_package(struct acpi_ctx *ctx, const char *name, */ void acpigen_write_processor_cnot(struct acpi_ctx *ctx, const uint num_cores); +/** + * acpigen_write_ppc() - generates a function returning max P-states + * + * @ctx: ACPI context pointer + * @num_pstates: Number of pstates to return + */ +void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates); + +/** + * acpigen_write_ppc() - generates a function returning PPCM + * + * This returns the maximum number of supported P-states, as saved in the + * variable PPCM + * + * @ctx: ACPI context pointer + */ +void acpigen_write_ppc_nvs(struct acpi_ctx *ctx); + +/** + * acpigen_write_tpc() - Write a _TPC method that returns the TPC limit + * + * @ctx: ACPI context pointer + * @gnvs_tpc_limit: Variable that holds the TPC limit + */ +void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit); + +/** + * acpigen_write_pss_package() - Write a PSS package + * + * See ACPI v6.3 section 8.4.6: Processor Performance Control + * + * @ctx: ACPI context pointer + * @corefreq: CPU core frequency in MHz + * @translat: worst-case latency in uS that the CPU is unavailable during a + * transition from any performance state to this performance state + * @busmlat: worst-case latency in microseconds that Bus Masters are prevented + * from accessing memory during a transition from any performance state to + * this performance state + * @control: Value to write to PERF_CTRL to move to this performance state + * @status: Expected PERF_STATUS value when in this state + */ +void acpigen_write_pss_package(struct acpi_ctx *ctx, uint corefreq, uint power, + uint translat, uint busmlat, uint control, + uint status); + +/** + * acpigen_write_psd_package() - Write a PSD package + * + * Writes a P-State dependency package + * + * See ACPI v6.3 section 8.4.6.5: _PSD (P-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: Dependency domain number to which this P state entry belongs + * @numprocs: Number of processors belonging to the domain for this logical + * processor’s P-states + * @coordtype: Coordination type + */ +void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum psd_coord coordtype); + +/** + * acpigen_write_cst_package() - Write a _CST package + * + * See ACPI v6.3 section 8.4.2.1: _CST (C States) + * + * @ctx: ACPI context pointer + * @entry: Array of entries + * @nentries; Number of entries + */ +void acpigen_write_cst_package(struct acpi_ctx *ctx, + const struct acpi_cstate *entry, int nentries); + +/** + * acpigen_write_csd_package() - Write a _CSD Package + * + * See ACPI v6.3 section 8.4.2.2: _CSD (C-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: dependency domain number to which this C state entry belongs + * @numprocs: number of processors belonging to the domain for the particular + * C-state + * @coordtype: Co-ordination type + * @index: Index of the C-State entry in the _CST object for which the + * dependency applies + */ +void acpigen_write_csd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum csd_coord coordtype, uint index); + +/** + * acpigen_write_tss_package() - Write a _TSS package + * + * @ctx: ACPI context pointer + * @entry: Entries to write + * @nentries: Number of entries to write + */ +void acpigen_write_tss_package(struct acpi_ctx *ctx, + struct acpi_tstate *entry, int nentries); + +/** + * acpigen_write_tsd_package() - Write a _TSD package + * + * See ACPI v6.3 section 8.4.5.4: _TSD (T-State Dependency) + * + * @ctx: ACPI context pointer + * @domain: dependency domain number to which this T state entry belongs + * @numprocs: Number of processors belonging to the domain for this logical + * processor’s T-states + * @coordtype: Coordination type + */ +void acpigen_write_tsd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum psd_coord coordtype); + #endif diff --git a/lib/acpi/acpigen.c b/lib/acpi/acpigen.c index b9985075cde..e395226e3de 100644 --- a/lib/acpi/acpigen.c +++ b/lib/acpi/acpigen.c @@ -481,6 +481,53 @@ void acpigen_write_register_resource(struct acpi_ctx *ctx, acpigen_write_resourcetemplate_footer(ctx); } +void acpigen_write_ppc(struct acpi_ctx *ctx, uint num_pstates) +{ + /* + * Method (_PPC, 0, NotSerialized) + * { + * Return (num_pstates) + * } + */ + acpigen_write_method(ctx, "_PPC", 0); + acpigen_emit_byte(ctx, RETURN_OP); + acpigen_write_byte(ctx, num_pstates); + acpigen_pop_len(ctx); +} + +/* + * Generates a func with max supported P-states saved + * in the variable PPCM. + */ +void acpigen_write_ppc_nvs(struct acpi_ctx *ctx) +{ + /* + * Method (_PPC, 0, NotSerialized) + * { + * Return (PPCM) + * } + */ + acpigen_write_method(ctx, "_PPC", 0); + acpigen_emit_byte(ctx, RETURN_OP); + acpigen_emit_namestring(ctx, "PPCM"); + acpigen_pop_len(ctx); +} + +void acpigen_write_tpc(struct acpi_ctx *ctx, const char *gnvs_tpc_limit) +{ + /* + * // Sample _TPC method + * Method (_TPC, 0, NotSerialized) + * { + * Return (\TLVL) + * } + */ + acpigen_write_method(ctx, "_TPC", 0); + acpigen_emit_byte(ctx, RETURN_OP); + acpigen_emit_namestring(ctx, gnvs_tpc_limit); + acpigen_pop_len(ctx); +} + void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level) { /* Name (_PRW, Package () { wake, level } */ @@ -491,6 +538,126 @@ void acpigen_write_prw(struct acpi_ctx *ctx, uint wake, uint level) acpigen_pop_len(ctx); } +void acpigen_write_pss_package(struct acpi_ctx *ctx, u32 core_freq, u32 power, + u32 trans_lat, u32 busm_lat, u32 control, + u32 status) +{ + acpigen_write_package(ctx, 6); + acpigen_write_dword(ctx, core_freq); + acpigen_write_dword(ctx, power); + acpigen_write_dword(ctx, trans_lat); + acpigen_write_dword(ctx, busm_lat); + acpigen_write_dword(ctx, control); + acpigen_write_dword(ctx, status); + acpigen_pop_len(ctx); + + log_debug("PSS: %uMHz power %u control 0x%x status 0x%x\n", + core_freq, power, control, status); +} + +void acpigen_write_psd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum psd_coord coordtype) +{ + acpigen_write_name(ctx, "_PSD"); + acpigen_write_package(ctx, 1); + acpigen_write_package(ctx, 5); + acpigen_write_byte(ctx, 5); // 5 values + acpigen_write_byte(ctx, 0); // revision 0 + acpigen_write_dword(ctx, domain); + acpigen_write_dword(ctx, coordtype); + acpigen_write_dword(ctx, numprocs); + acpigen_pop_len(ctx); + acpigen_pop_len(ctx); +} + +static void acpigen_write_cst_package_entry(struct acpi_ctx *ctx, + const struct acpi_cstate *cstate) +{ + acpigen_write_package(ctx, 4); + acpigen_write_register_resource(ctx, &cstate->resource); + acpigen_write_dword(ctx, cstate->ctype); + acpigen_write_dword(ctx, cstate->latency); + acpigen_write_dword(ctx, cstate->power); + acpigen_pop_len(ctx); +} + +void acpigen_write_cst_package(struct acpi_ctx *ctx, + const struct acpi_cstate *cstate, int nentries) +{ + int i; + + acpigen_write_name(ctx, "_CST"); + acpigen_write_package(ctx, nentries + 1); + acpigen_write_dword(ctx, nentries); + + for (i = 0; i < nentries; i++) + acpigen_write_cst_package_entry(ctx, cstate + i); + + acpigen_pop_len(ctx); +} + +void acpigen_write_csd_package(struct acpi_ctx *ctx, uint domain, uint numprocs, + enum csd_coord coordtype, uint index) +{ + acpigen_write_name(ctx, "_CSD"); + acpigen_write_package(ctx, 1); + acpigen_write_package(ctx, 6); + acpigen_write_byte(ctx, 6); // 6 values + acpigen_write_byte(ctx, 0); // revision 0 + acpigen_write_dword(ctx, domain); + acpigen_write_dword(ctx, coordtype); + acpigen_write_dword(ctx, numprocs); + acpigen_write_dword(ctx, index); + acpigen_pop_len(ctx); + acpigen_pop_len(ctx); +} + +void acpigen_write_tss_package(struct acpi_ctx *ctx, + struct acpi_tstate *entry, int nentries) +{ + /* + * Sample _TSS package with 100% and 50% duty cycles + * Name (_TSS, Package (0x02) + * { + * Package(){100, 1000, 0, 0x00, 0) + * Package(){50, 520, 0, 0x18, 0) + * }) + */ + struct acpi_tstate *tstate = entry; + int i; + + acpigen_write_name(ctx, "_TSS"); + acpigen_write_package(ctx, nentries); + + for (i = 0; i < nentries; i++) { + acpigen_write_package(ctx, 5); + acpigen_write_dword(ctx, tstate->percent); + acpigen_write_dword(ctx, tstate->power); + acpigen_write_dword(ctx, tstate->latency); + acpigen_write_dword(ctx, tstate->control); + acpigen_write_dword(ctx, tstate->status); + acpigen_pop_len(ctx); + tstate++; + } + + acpigen_pop_len(ctx); +} + +void acpigen_write_tsd_package(struct acpi_ctx *ctx, u32 domain, u32 numprocs, + enum psd_coord coordtype) +{ + acpigen_write_name(ctx, "_TSD"); + acpigen_write_package(ctx, 1); + acpigen_write_package(ctx, 5); + acpigen_write_byte(ctx, 5); // 5 values + acpigen_write_byte(ctx, 0); // revision 0 + acpigen_write_dword(ctx, domain); + acpigen_write_dword(ctx, coordtype); + acpigen_write_dword(ctx, numprocs); + acpigen_pop_len(ctx); + acpigen_pop_len(ctx); +} + /* * ToUUID(uuid) * diff --git a/test/dm/acpigen.c b/test/dm/acpigen.c index 74b7e23aab3..3ec2743af9f 100644 --- a/test/dm/acpigen.c +++ b/test/dm/acpigen.c @@ -1450,3 +1450,297 @@ static int dm_test_acpi_write_processor_cnot(struct unit_test_state *uts) return 0; } DM_TEST(dm_test_acpi_write_processor_cnot, 0); + +/* Test acpigen_write_tpc */ +static int dm_test_acpi_write_tpc(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_tpc(ctx, "\\TLVL"); + + ut_asserteq(METHOD_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq_strn("_TPC", (char *)ptr); + ptr += 4; + ut_asserteq(0, *ptr++); + ut_asserteq(RETURN_OP, *ptr++); + ut_asserteq_strn("\\TLVL", (char *)ptr); + ptr += 5; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_tpc, 0); + +/* Test acpigen_write_pss_package(), etc. */ +static int dm_test_acpi_write_pss_psd(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_pss_package(ctx, 1, 2, 3, 4, 5, 6); + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(6, *ptr++); + + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(1, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(2, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(3, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(4, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(5, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(6, get_unaligned((u32 *)ptr)); + ptr += 4; + + acpigen_write_psd_package(ctx, 6, 7, HW_ALL); + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("_PSD", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(1, *ptr++); + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(5, *ptr++); + + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(5, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(0, *ptr++); + + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(6, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(HW_ALL, get_unaligned((u32 *)ptr)); + ptr += 5; + + ut_asserteq(7, get_unaligned((u32 *)ptr)); + ptr += 4; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_pss_psd, 0); + +/* Test acpi_write_cst_package() */ +static int dm_test_acpi_write_cst(struct unit_test_state *uts) +{ + static struct acpi_cstate cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_FIXED, + }, + }, { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = { + .space_id = ACPI_ADDRESS_SPACE_IO, + .bit_width = 8, + .addrl = 0x415, + }, + }, + }; + int nentries = ARRAY_SIZE(cstate_map); + struct acpi_ctx *ctx; + u8 *ptr; + int i; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_cst_package(ctx, cstate_map, nentries); + + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("_CST", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(nentries + 1, *ptr++); + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(nentries, get_unaligned((u32 *)ptr)); + ptr += 4; + + for (i = 0; i < nentries; i++) { + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(4, *ptr++); + ut_asserteq(BUFFER_OP, *ptr++); + ptr += 0x17; + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(cstate_map[i].ctype, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(cstate_map[i].latency, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(cstate_map[i].power, get_unaligned((u32 *)ptr)); + ptr += 4; + } + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_cst, 0); + +/* Test acpi_write_cst_package() */ +static int dm_test_acpi_write_csd(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_csd_package(ctx, 12, 34, CSD_HW_ALL, 56); + + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("_CSD", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(1, *ptr++); + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(6, *ptr++); + + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(6, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(0, *ptr++); + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(12, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(CSD_HW_ALL, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(34, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(56, get_unaligned((u32 *)ptr)); + ptr += 4; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_csd, 0); + +/* Test acpigen_write_tss_package() */ +static int dm_test_acpi_write_tss(struct unit_test_state *uts) +{ + static struct acpi_tstate tstate_list[] = { + { 1, 2, 3, 4, 5, }, + { 6, 7, 8, 9, 10, }, + }; + int nentries = ARRAY_SIZE(tstate_list); + struct acpi_ctx *ctx; + u8 *ptr; + int i; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_tss_package(ctx, tstate_list, nentries); + + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("_TSS", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(nentries, *ptr++); + + for (i = 0; i < nentries; i++) { + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(5, *ptr++); + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(tstate_list[i].percent, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(tstate_list[i].power, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(tstate_list[i].latency, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(tstate_list[i].control, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(tstate_list[i].status, get_unaligned((u32 *)ptr)); + ptr += 4; + } + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_tss, 0); + +/* Test acpigen_write_tsd_package() */ +static int dm_test_acpi_write_tsd_package(struct unit_test_state *uts) +{ + struct acpi_ctx *ctx; + u8 *ptr; + + ut_assertok(alloc_context(&ctx)); + + ptr = acpigen_get_current(ctx); + acpigen_write_tsd_package(ctx, 12, 34, HW_ALL); + + ut_asserteq(NAME_OP, *ptr++); + ut_asserteq_strn("_TSD", (char *)ptr); + ptr += 4; + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(1, *ptr++); + ut_asserteq(PACKAGE_OP, *ptr++); + ptr += 3; /* skip length */ + ut_asserteq(5, *ptr++); + + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(5, *ptr++); + ut_asserteq(BYTE_PREFIX, *ptr++); + ut_asserteq(0, *ptr++); + ut_asserteq(DWORD_PREFIX, *ptr++); + ut_asserteq(12, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(CSD_HW_ALL, get_unaligned((u32 *)ptr)); + ptr += 5; + ut_asserteq(34, get_unaligned((u32 *)ptr)); + ptr += 4; + + ut_asserteq_ptr(ptr, ctx->current); + + free_context(&ctx); + + return 0; +} +DM_TEST(dm_test_acpi_write_tsd_package, 0); -- cgit v1.3.1 From 540f0bae9bd0e19d00d11796a62a08f94d895189 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:16 -0600 Subject: x86: acpi: Add support for additional Intel tables Apollo Lake needs to generate a few more table types used on Intel SoCs. Add support for these into the x86 ACPI code. Signed-off-by: Simon Glass --- arch/x86/include/asm/acpi_table.h | 115 ++++++++++++++++++++++++++++++++++++++ arch/x86/lib/acpi_table.c | 111 ++++++++++++++++++++++++++++++++++++ include/acpi/acpi_table.h | 43 ++++++++++++++ 3 files changed, 269 insertions(+) (limited to 'include') diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 3245e447813..faf31730730 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -98,4 +98,119 @@ int arch_write_sci_irq_select(uint scis); */ int arch_madt_sci_irq_polarity(int sci); +/** + * acpi_create_dmar_drhd() - Create a table for DMA remapping with the IOMMU + * + * See here for the specification + * https://software.intel.com/sites/default/files/managed/c5/15/vt-directed-io-spec.pdf + * + * @ctx: ACPI context pointer + * @flags: (DRHD_INCLUDE_...) + * @segment: PCI segment asscociated with this unit + * @bar: Base address of remapping hardware register-set for this unit + */ +void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment, + u64 bar); + +/** + * acpi_create_dmar_rmrr() - Set up an RMRR + * + * This sets up a Reserved-Memory Region Reporting structure, used to allow + * DMA to regions used by devices that the BIOS controls. + * + * @ctx: ACPI context pointer + * @segment: PCI segment asscociated with this unit + * @bar: Base address of mapping + * @limit: End address of mapping + */ +void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar, + u64 limit); + +/** + * acpi_dmar_drhd_fixup() - Set the length of an DRHD + * + * This sets the DRHD length field based on the current ctx->current + * + * @ctx: ACPI context pointer + * @base: Address of the start of the DRHD + */ +void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base); + +/** + * acpi_dmar_rmrr_fixup() - Set the length of an RMRR + * + * This sets the RMRR length field based on the current ctx->current + * + * @ctx: ACPI context pointer + * @base: Address of the start of the RMRR + */ +void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base); + +/** + * acpi_create_dmar_ds_pci() - Set up a DMAR scope for a PCI device + * + * @ctx: ACPI context pointer + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_pci_br() - Set up a DMAR scope for a PCI bridge + * + * This is used to provide a mapping for a PCI bridge + * + * @ctx: ACPI context pointer + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_ioapic() - Set up a DMAR scope for an IOAPIC device + * + * @ctx: ACPI context pointer + * @enumeration_id: Enumeration ID (typically 2) + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf); + +/** + * acpi_create_dmar_ds_msi_hpet() - Set up a DMAR scope for an HPET + * + * Sets up a scope for a High-Precision Event Timer that supports + * Message-Signalled Interrupts + * + * @ctx: ACPI context pointer + * @enumeration_id: Enumeration ID (typically 0) + * @bdf: PCI device to add + * @return length of mapping in bytes + */ +int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf); + +/** + * acpi_fadt_common() - Handle common parts of filling out an FADT + * + * This sets up the Fixed ACPI Description Table + * + * @fadt: Pointer to place to put FADT + * @facs: Pointer to the FACS + * @dsdt: Pointer to the DSDT + */ +void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt); + +/** + * intel_acpi_fill_fadt() - Set up the contents of the FADT + * + * This sets up parts of the Fixed ACPI Description Table that are common to + * Intel chips + * + * @fadt: Pointer to place to put FADT + */ +void intel_acpi_fill_fadt(struct acpi_fadt *fadt); + #endif /* __ASM_ACPI_TABLE_H__ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index e257c789838..86a9a35cb25 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -629,3 +629,114 @@ int acpi_write_dbg2_pci_uart(struct acpi_ctx *ctx, struct udevice *dev, return 0; } + +void acpi_fadt_common(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &fadt->header; + + memset((void *)fadt, '\0', sizeof(struct acpi_fadt)); + + acpi_fill_header(header, "FACP"); + header->length = sizeof(struct acpi_fadt); + header->revision = 4; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->aslc_id, ASLC_ID, 4); + header->aslc_revision = 1; + + fadt->firmware_ctrl = (unsigned long)facs; + fadt->dsdt = (unsigned long)dsdt; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->preferred_pm_profile = ACPI_PM_MOBILE; + + /* Use ACPI 3.0 revision */ + fadt->header.revision = 4; +} + +void acpi_create_dmar_drhd(struct acpi_ctx *ctx, uint flags, uint segment, + u64 bar) +{ + struct dmar_entry *drhd = ctx->current; + + memset(drhd, '\0', sizeof(*drhd)); + drhd->type = DMAR_DRHD; + drhd->length = sizeof(*drhd); /* will be fixed up later */ + drhd->flags = flags; + drhd->segment = segment; + drhd->bar = bar; + acpi_inc(ctx, drhd->length); +} + +void acpi_create_dmar_rmrr(struct acpi_ctx *ctx, uint segment, u64 bar, + u64 limit) +{ + struct dmar_rmrr_entry *rmrr = ctx->current; + + memset(rmrr, '\0', sizeof(*rmrr)); + rmrr->type = DMAR_RMRR; + rmrr->length = sizeof(*rmrr); /* will be fixed up later */ + rmrr->segment = segment; + rmrr->bar = bar; + rmrr->limit = limit; + acpi_inc(ctx, rmrr->length); +} + +void acpi_dmar_drhd_fixup(struct acpi_ctx *ctx, void *base) +{ + struct dmar_entry *drhd = base; + + drhd->length = ctx->current - base; +} + +void acpi_dmar_rmrr_fixup(struct acpi_ctx *ctx, void *base) +{ + struct dmar_rmrr_entry *rmrr = base; + + rmrr->length = ctx->current - base; +} + +static int acpi_create_dmar_ds(struct acpi_ctx *ctx, enum dev_scope_type type, + uint enumeration_id, pci_dev_t bdf) +{ + /* we don't support longer paths yet */ + const size_t dev_scope_length = sizeof(struct dev_scope) + 2; + struct dev_scope *ds = ctx->current; + + memset(ds, '\0', dev_scope_length); + ds->type = type; + ds->length = dev_scope_length; + ds->enumeration = enumeration_id; + ds->start_bus = PCI_BUS(bdf); + ds->path[0].dev = PCI_DEV(bdf); + ds->path[0].fn = PCI_FUNC(bdf); + + return ds->length; +} + +int acpi_create_dmar_ds_pci_br(struct acpi_ctx *ctx, pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_PCI_SUB, 0, bdf); +} + +int acpi_create_dmar_ds_pci(struct acpi_ctx *ctx, pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_PCI_ENDPOINT, 0, bdf); +} + +int acpi_create_dmar_ds_ioapic(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_IOAPIC, enumeration_id, bdf); +} + +int acpi_create_dmar_ds_msi_hpet(struct acpi_ctx *ctx, uint enumeration_id, + pci_dev_t bdf) +{ + return acpi_create_dmar_ds(ctx, SCOPE_MSI_HPET, enumeration_id, bdf); +} diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index c826a797f5b..a2e510cf56e 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -377,6 +377,49 @@ struct acpi_csrt_shared_info { u32 max_block_size; }; +/* Port types for ACPI _UPC object */ +enum acpi_upc_type { + UPC_TYPE_A, + UPC_TYPE_MINI_AB, + UPC_TYPE_EXPRESSCARD, + UPC_TYPE_USB3_A, + UPC_TYPE_USB3_B, + UPC_TYPE_USB3_MICRO_B, + UPC_TYPE_USB3_MICRO_AB, + UPC_TYPE_USB3_POWER_B, + UPC_TYPE_C_USB2_ONLY, + UPC_TYPE_C_USB2_SS_SWITCH, + UPC_TYPE_C_USB2_SS, + UPC_TYPE_PROPRIETARY = 0xff, + /* + * The following types are not directly defined in the ACPI + * spec but are used by coreboot to identify a USB device type. + */ + UPC_TYPE_INTERNAL = 0xff, + UPC_TYPE_UNUSED, + UPC_TYPE_HUB +}; + +enum dev_scope_type { + SCOPE_PCI_ENDPOINT = 1, + SCOPE_PCI_SUB = 2, + SCOPE_IOAPIC = 3, + SCOPE_MSI_HPET = 4, + SCOPE_ACPI_NAMESPACE_DEVICE = 5 +}; + +struct __packed dev_scope { + u8 type; + u8 length; + u8 reserved[2]; + u8 enumeration; + u8 start_bus; + struct { + u8 dev; + u8 fn; + } __packed path[0]; +}; + enum dmar_type { DMAR_DRHD = 0, DMAR_RMRR = 1, -- cgit v1.3.1 From 022256b95b134dc62317d4aba11510add00a0c28 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:18 -0600 Subject: p2sb: Add some definitions used for ACPI Allow this header to be included in ASL files by adding a header guard and a few definitions that are needed. Signed-off-by: Simon Glass --- include/p2sb.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/p2sb.h b/include/p2sb.h index 93e1155dca6..a25170e3d11 100644 --- a/include/p2sb.h +++ b/include/p2sb.h @@ -10,6 +10,12 @@ /* Port Id lives in bits 23:16 and register offset lives in 15:0 of address */ #define PCR_PORTID_SHIFT 16 +#if !defined(__ACPI__) + +/* These registers contain IOAPIC and HPET devfn */ +#define PCH_P2SB_IBDF 0x6c +#define PCH_P2SB_HBDF 0x70 + /** * struct p2sb_child_platdata - Information about each child of a p2sb device * @@ -164,4 +170,6 @@ int p2sb_get_port_id(struct udevice *dev); */ void *pcr_reg_address(struct udevice *dev, uint offset); +#endif /* !__ACPI__ */ + #endif -- cgit v1.3.1 From da2c1b8fd9db6ffa6a8de6d11380a90feea725b4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:19 -0600 Subject: x86: apl: Generate required ACPI tables Add support for generating various ACPI tables for Apollo Lake. Add a few S3 definitions that are needed. Signed-off-by: Simon Glass --- arch/x86/cpu/apollolake/Makefile | 1 + arch/x86/cpu/apollolake/acpi.c | 211 ++++++++++++++++++++++++++++ arch/x86/include/asm/arch-apollolake/acpi.h | 18 +++ include/acpi/acpi_s3.h | 4 + 4 files changed, 234 insertions(+) create mode 100644 arch/x86/cpu/apollolake/acpi.c create mode 100644 arch/x86/include/asm/arch-apollolake/acpi.h (limited to 'include') diff --git a/arch/x86/cpu/apollolake/Makefile b/arch/x86/cpu/apollolake/Makefile index 3aa2a556765..2ddf4af62c5 100644 --- a/arch/x86/cpu/apollolake/Makefile +++ b/arch/x86/cpu/apollolake/Makefile @@ -16,6 +16,7 @@ obj-y += fsp_m.o endif endif ifndef CONFIG_SPL_BUILD +obj-y += acpi.o obj-y += fsp_s.o endif diff --git a/arch/x86/cpu/apollolake/acpi.c b/arch/x86/cpu/apollolake/acpi.c new file mode 100644 index 00000000000..69b544f0d98 --- /dev/null +++ b/arch/x86/cpu/apollolake/acpi.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2017-2019 Siemens AG + * (Written by Lance Zhao for Intel Corp.) + * Copyright 2019 Google LLC + * + * Modified from coreboot apollolake/acpi.c + */ + +#define LOG_CATEGORY LOGC_ACPI + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int arch_read_sci_irq_select(void) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + + return readl(upriv->pmc_bar0 + IRQ_REG); +} + +int arch_write_sci_irq_select(uint scis) +{ + struct acpi_pmc_upriv *upriv; + struct udevice *dev; + int ret; + + ret = uclass_first_device_err(UCLASS_ACPI_PMC, &dev); + if (ret) + return log_msg_ret("pmc", ret); + upriv = dev_get_uclass_priv(dev); + writel(scis, upriv->pmc_bar0 + IRQ_REG); + + return 0; +} + +int acpi_create_gnvs(struct acpi_global_nvs *gnvs) +{ + struct udevice *cpu; + int ret; + + /* Clear out GNV */ + memset(gnvs, '\0', sizeof(*gnvs)); + + /* TODO(sjg@chromium.org): Add the console log to gnvs->cbmc */ + +#ifdef CONFIG_CHROMEOS + /* Initialise Verified Boot data */ + chromeos_init_acpi(&gnvs->chromeos); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; +#endif + /* Set unknown wake source */ + gnvs->pm1i = ~0ULL; + + /* CPU core count */ + gnvs->pcnt = 1; + ret = uclass_find_first_device(UCLASS_CPU, &cpu); + if (cpu) { + ret = cpu_get_count(cpu); + if (ret > 0) + gnvs->pcnt = ret; + } + + return 0; +} + +uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en) +{ + /* + * WAK_STS bit is set when the system is in one of the sleep states + * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting + * this bit, the PMC will transition the system to the ON state and + * can only be set by hardware and can only be cleared by writing a one + * to this bit position. + */ + generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN; + + return generic_pm1_en; +} + +int arch_madt_sci_irq_polarity(int sci) +{ + return MP_IRQ_POLARITY_LOW; +} + +void fill_fadt(struct acpi_fadt *fadt) +{ + fadt->pm_tmr_blk = IOMAP_ACPI_BASE + PM1_TMR; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + + fadt->pm_tmr_len = 4; + fadt->duty_width = 3; + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = IOMAP_ACPI_BASE + PM1_TMR; +} + +void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs, + void *dsdt) +{ + struct acpi_table_header *header = &fadt->header; + + acpi_fadt_common(fadt, facs, dsdt); + intel_acpi_fill_fadt(fadt); + fill_fadt(fadt); + header->checksum = table_compute_checksum(fadt, header->length); +} + +int apl_acpi_fill_dmar(struct acpi_ctx *ctx) +{ + struct udevice *dev, *sa_dev; + u64 gfxvtbar = readq(MCHBAR_REG(GFXVTBAR)) & VTBAR_MASK; + u64 defvtbar = readq(MCHBAR_REG(DEFVTBAR)) & VTBAR_MASK; + bool gfxvten = readl(MCHBAR_REG(GFXVTBAR)) & VTBAR_ENABLED; + bool defvten = readl(MCHBAR_REG(DEFVTBAR)) & VTBAR_ENABLED; + void *tmp; + int ret; + + uclass_find_first_device(UCLASS_VIDEO, &dev); + ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &sa_dev); + if (ret) + return log_msg_ret("no sa", ret); + + /* IGD has to be enabled, GFXVTBAR set and enabled */ + if (dev && device_active(dev) && gfxvtbar && gfxvten) { + tmp = ctx->current; + + acpi_create_dmar_drhd(ctx, 0, 0, gfxvtbar); + ret = acpi_create_dmar_ds_pci(ctx, PCI_BDF(0, 2, 0)); + if (ret) + return log_msg_ret("ds_pci", ret); + acpi_dmar_drhd_fixup(ctx, tmp); + + /* Add RMRR entry */ + tmp = ctx->current; + acpi_create_dmar_rmrr(ctx->current, 0, sa_get_gsm_base(sa_dev), + sa_get_tolud_base(sa_dev) - 1); + acpi_create_dmar_ds_pci(ctx->current, PCI_BDF(0, 2, 0)); + acpi_dmar_rmrr_fixup(ctx, tmp); + } + + /* DEFVTBAR has to be set and enabled */ + if (defvtbar && defvten) { + struct udevice *p2sb_dev; + u16 ibdf, hbdf; + uint ioapic, hpet; + int ret; + + tmp = ctx->current; + /* + * P2SB may already be hidden. There's no clear rule, when. + * It is needed to get bus, device and function for IOAPIC and + * HPET device which is stored in P2SB device. So unhide it to + * get the info and hide it again when done. + * + * TODO(sjg@chromium.org): p2sb_unhide() ? + */ + ret = uclass_first_device_err(UCLASS_P2SB, &p2sb_dev); + if (ret) + return log_msg_ret("p2sb", ret); + + dm_pci_read_config16(p2sb_dev, PCH_P2SB_IBDF, &ibdf); + ioapic = PCI_TO_BDF(ibdf); + dm_pci_read_config16(p2sb_dev, PCH_P2SB_HBDF, &hbdf); + hpet = PCI_TO_BDF(hbdf); + /* TODO(sjg@chromium.org): p2sb_hide() ? */ + + acpi_create_dmar_drhd(ctx, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); + acpi_create_dmar_ds_ioapic(ctx, 2, ioapic); + acpi_create_dmar_ds_msi_hpet(ctx, 0, hpet); + acpi_dmar_drhd_fixup(tmp, ctx->current); + } + + return 0; +} diff --git a/arch/x86/include/asm/arch-apollolake/acpi.h b/arch/x86/include/asm/arch-apollolake/acpi.h new file mode 100644 index 00000000000..ed852feee03 --- /dev/null +++ b/arch/x86/include/asm/arch-apollolake/acpi.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +#ifndef _ASM_ARCH_ACPI_H +#define _ASM_ARCH_ACPI_H + +struct acpi_ctx; + +/** + * apl_acpi_fill_dmar() - Set up the DMAR for APL + * + * @ctx: ACPI context pointer + */ +int apl_acpi_fill_dmar(struct acpi_ctx *ctx); + +#endif /* _ASM_ARCH_CPU_H */ diff --git a/include/acpi/acpi_s3.h b/include/acpi/acpi_s3.h index baa848dcd15..847139baa0c 100644 --- a/include/acpi/acpi_s3.h +++ b/include/acpi/acpi_s3.h @@ -28,6 +28,10 @@ #define SLP_TYP_S4 6 #define SLP_TYP_S5 7 +/* PM1_STS register */ +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) + /* Memory size reserved for S3 resume */ #define S3_RESERVE_SIZE 0x1000 -- cgit v1.3.1 From 9179c3571ce587e96b957d0da8f0e4dcabc8d293 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:32 -0600 Subject: acpi: tpm: Add a TPM2 table This provides information about a v2 TPM in the system. Generate this table if the TPM is present. Signed-off-by: Simon Glass --- arch/x86/lib/acpi_table.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++ include/acpi/acpi_table.h | 11 +++++++ include/bloblist.h | 1 + 3 files changed, 86 insertions(+) (limited to 'include') diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 5876355afe2..c31cc923c9c 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -7,6 +7,7 @@ */ #include +#include #include #include #include @@ -214,6 +215,64 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); } +static int get_tpm2_log(void **ptrp, int *sizep) +{ + const int tpm2_default_log_len = 0x10000; + int size; + int ret; + + *sizep = 0; + size = tpm2_default_log_len; + ret = bloblist_ensure_size_ret(BLOBLISTT_TPM2_TCG_LOG, &size, ptrp); + if (ret) + return log_msg_ret("blob", ret); + *sizep = size; + + return 0; +} + +static int acpi_create_tpm2(struct acpi_tpm2 *tpm2) +{ + struct acpi_table_header *header = &tpm2->header; + int tpm2_log_len; + void *lasa; + int ret; + + memset((void *)tpm2, 0, sizeof(struct acpi_tpm2)); + + /* + * Some payloads like SeaBIOS depend on log area to use TPM2. + * Get the memory size and address of TPM2 log area or initialize it. + */ + ret = get_tpm2_log(&lasa, &tpm2_log_len); + if (ret) + return ret; + + /* Fill out header fields. */ + acpi_fill_header(header, "TPM2"); + memcpy(header->aslc_id, ASLC_ID, 4); + + header->length = sizeof(struct acpi_tpm2); + header->revision = acpi_get_table_revision(ACPITAB_TPM2); + + /* Hard to detect for coreboot. Just set it to 0 */ + tpm2->platform_class = 0; + + /* Must be set to 0 for FIFO-interface support */ + tpm2->control_area = 0; + tpm2->start_method = 6; + memset(tpm2->msp, 0, sizeof(tpm2->msp)); + + /* Fill the log area size and start address fields. */ + tpm2->laml = tpm2_log_len; + tpm2->lasa = (uintptr_t)lasa; + + /* Calculate checksum. */ + header->checksum = table_compute_checksum((void *)tpm2, header->length); + + return 0; +} + __weak u32 acpi_fill_csrt(u32 current) { return 0; @@ -499,6 +558,21 @@ ulong write_acpi_tables(ulong start_addr) acpi_inc_align(ctx, mcfg->header.length); acpi_add_table(ctx, mcfg); + if (IS_ENABLED(CONFIG_TPM_V2)) { + struct acpi_tpm2 *tpm2; + int ret; + + debug("ACPI: * TPM2\n"); + tpm2 = (struct acpi_tpm2 *)ctx->current; + ret = acpi_create_tpm2(tpm2); + if (!ret) { + acpi_inc_align(ctx, tpm2->header.length); + acpi_add_table(ctx, tpm2); + } else { + log_warning("TPM2 table creation failed\n"); + } + } + debug("ACPI: * MADT\n"); madt = ctx->current; acpi_create_madt(madt); diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index a2e510cf56e..c7ee8b55da4 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -93,6 +93,17 @@ struct __packed acpi_hpet { u8 attributes; }; +struct __packed acpi_tpm2 { + struct acpi_table_header header; + u16 platform_class; + u8 reserved[2]; + u64 control_area; + u32 start_method; + u8 msp[12]; + u32 laml; + u64 lasa; +}; + /* FADT Preferred Power Management Profile */ enum acpi_pm_profile { ACPI_PM_UNSPECIFIED = 0, diff --git a/include/bloblist.h b/include/bloblist.h index 7d8480548e0..dc7d80bd851 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -33,6 +33,7 @@ enum bloblist_tag_t { */ BLOBLISTT_ACPI_GNVS, BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ + BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */ }; /** -- cgit v1.3.1 From 77bb1c69dfca24e4c14fd6876a68a38118142cae Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:33 -0600 Subject: acpi: tpm: Add a TPM1 table This provides information about a v1 TPM in the system. Generate this table if the TPM is present. Add a required new bloblist type and correct the header order of one header file. Signed-off-by: Simon Glass --- arch/x86/lib/acpi_table.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++- include/acpi/acpi_table.h | 7 ++++++ include/bloblist.h | 1 + 3 files changed, 61 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index c31cc923c9c..10cf3b70945 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -215,6 +215,47 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) header->checksum = table_compute_checksum((void *)mcfg, header->length); } +/** + * acpi_create_tcpa() - Create a TCPA table + * + * @tcpa: Pointer to place to put table + * + * Trusted Computing Platform Alliance Capabilities Table + * TCPA PC Specific Implementation SpecificationTCPA is defined in the PCI + * Firmware Specification 3.0 + */ +static int acpi_create_tcpa(struct acpi_tcpa *tcpa) +{ + struct acpi_table_header *header = &tcpa->header; + u32 current = (u32)tcpa + sizeof(struct acpi_tcpa); + int size = 0x10000; /* Use this as the default size */ + void *log; + int ret; + + if (!CONFIG_IS_ENABLED(BLOBLIST)) + return -ENXIO; + memset(tcpa, '\0', sizeof(struct acpi_tcpa)); + + /* Fill out header fields */ + acpi_fill_header(header, "TCPA"); + header->length = sizeof(struct acpi_tcpa); + header->revision = 1; + + ret = bloblist_ensure_size_ret(BLOBLISTT_TCPA_LOG, &size, &log); + if (ret) + return log_msg_ret("blob", ret); + + tcpa->platform_class = 0; + tcpa->laml = size; + tcpa->lasa = (ulong)log; + + /* (Re)calculate length and checksum */ + header->length = current - (u32)tcpa; + header->checksum = table_compute_checksum((void *)tcpa, header->length); + + return 0; +} + static int get_tpm2_log(void **ptrp, int *sizep) { const int tpm2_default_log_len = 0x10000; @@ -457,11 +498,13 @@ ulong write_acpi_tables(ulong start_addr) struct acpi_fadt *fadt; struct acpi_table_header *ssdt; struct acpi_mcfg *mcfg; + struct acpi_tcpa *tcpa; struct acpi_madt *madt; struct acpi_csrt *csrt; struct acpi_spcr *spcr; void *start; ulong addr; + int ret; int i; start = map_sysmem(start_addr, 0); @@ -560,7 +603,6 @@ ulong write_acpi_tables(ulong start_addr) if (IS_ENABLED(CONFIG_TPM_V2)) { struct acpi_tpm2 *tpm2; - int ret; debug("ACPI: * TPM2\n"); tpm2 = (struct acpi_tpm2 *)ctx->current; @@ -579,6 +621,16 @@ ulong write_acpi_tables(ulong start_addr) acpi_inc_align(ctx, madt->header.length); acpi_add_table(ctx, madt); + debug("ACPI: * TCPA\n"); + tcpa = (struct acpi_tcpa *)ctx->current; + ret = acpi_create_tcpa(tcpa); + if (ret) { + log_warning("Failed to create TCPA table (err=%d)\n", ret); + } else { + acpi_inc_align(ctx, tcpa->header.length); + acpi_add_table(ctx, tcpa); + } + debug("ACPI: * CSRT\n"); csrt = ctx->current; if (!acpi_create_csrt(csrt)) { diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index c7ee8b55da4..9fba6536f50 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -104,6 +104,13 @@ struct __packed acpi_tpm2 { u64 lasa; }; +struct __packed acpi_tcpa { + struct acpi_table_header header; + u16 platform_class; + u32 laml; + u64 lasa; +}; + /* FADT Preferred Power Management Profile */ enum acpi_pm_profile { ACPI_PM_UNSPECIFIED = 0, diff --git a/include/bloblist.h b/include/bloblist.h index dc7d80bd851..5784c2226e7 100644 --- a/include/bloblist.h +++ b/include/bloblist.h @@ -34,6 +34,7 @@ enum bloblist_tag_t { BLOBLISTT_ACPI_GNVS, BLOBLISTT_INTEL_VBT, /* Intel Video-BIOS table */ BLOBLISTT_TPM2_TCG_LOG, /* TPM v2 log space */ + BLOBLISTT_TCPA_LOG, /* TPM log space */ }; /** -- cgit v1.3.1 From 2a2ebf880cae6d961b8259b7b767d0aa0d34f070 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:39 -0600 Subject: acpi: Use defines for field lengths A few fields have an open-coded length. Use the defines for this purpose instead. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/acpi/acpi_table.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 9fba6536f50..3a243bf19ce 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -13,6 +13,7 @@ #ifndef __ACPI_TABLE_H__ #define __ACPI_TABLE_H__ +#include #include #define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ @@ -48,7 +49,7 @@ struct acpi_rsdp { /* Generic ACPI header, provided by (almost) all tables */ struct __packed acpi_table_header { - char signature[4]; /* ACPI signature (4 ASCII characters) */ + char signature[ACPI_NAME_LEN]; /* ACPI signature (4 ASCII chars) */ u32 length; /* Table length in bytes (incl. header) */ u8 revision; /* Table version (not ACPI version!) */ volatile u8 checksum; /* To make sum of entire table == 0 */ @@ -263,7 +264,7 @@ struct __packed acpi_fadt { /* FACS (Firmware ACPI Control Structure) */ struct acpi_facs { - char signature[4]; /* "FACS" */ + char signature[ACPI_NAME_LEN]; /* "FACS" */ u32 length; /* Length in bytes (>= 64) */ u32 hardware_signature; /* Hardware signature */ u32 firmware_waking_vector; /* Firmware waking vector */ -- cgit v1.3.1 From ee3cb7c648988aa5f7ae0872ecfb6bdcfa9c6c76 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:41 -0600 Subject: x86: Move include of bitops out of ACPI region At present linux/bitops.h is included in ACPI code. This is not needed and can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move the #include into the part not used by ACPI. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- include/acpi/acpi_table.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/acpi/acpi_table.h b/include/acpi/acpi_table.h index 3a243bf19ce..abbca6530db 100644 --- a/include/acpi/acpi_table.h +++ b/include/acpi/acpi_table.h @@ -14,7 +14,6 @@ #define __ACPI_TABLE_H__ #include -#include #define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ #define OEM_ID "U-BOOT" /* U-Boot */ @@ -29,6 +28,8 @@ #if !defined(__ACPI__) +#include + struct acpi_ctx; /* -- cgit v1.3.1 From 1e4073b8559615509af45f2f826d157c39841fd0 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:43 -0600 Subject: acpi: Add more documentation for struct acpi_gpio Add some documentation provided by Andy Shevchenko to describe how to use struct acpi_gpio. Signed-off-by: Simon Glass --- include/acpi/acpi_device.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'include') diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h index 1b838fcb857..007b7e7caf1 100644 --- a/include/acpi/acpi_device.h +++ b/include/acpi/acpi_device.h @@ -170,6 +170,28 @@ enum acpi_gpio_polarity { * @io_shared; true if GPIO is shared * @io_restrict: I/O restriction setting * @polarity: GPIO polarity + * + * Note that GpioIo doesn't have any means of Active Low / High setting, so a + * _DSD must be provided to mitigate this. + * + * GpioIo doesn't properly communicate the initial state of the output pin, + * thus Linux assumes the simple rule: + * + * Pull Bias Polarity Requested... + * + * Implicit x AS IS (assumed firmware configured for us) + * Explicit x (no _DSD) as Pull Bias (Up == High, Down == Low), + * assuming non-active (Polarity = !Pull Bias) + * + * Down Low as low, assuming active + * Down High as high, assuming non-active + * Up Low as high, assuming non-active + * Up High as high, assuming active + * + * GpioIo() can be used as interrupt and in this case the IoRestriction mustn't + * be OutputOnly. It also requires active_low flag from _DSD in cases where it's + * needed (better to always provide than rely on above assumption made on OS + * level). */ struct acpi_gpio { int pin_count; -- cgit v1.3.1 From 9c6aaf13473b611508e9bc3a5ab851255403c3bf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 12:45:44 -0600 Subject: acpi: Use I2cSerialBusV2() instead of I2cSerialBus() Use the correct name of the ACPI structure being created. Signed-off-by: Simon Glass --- include/acpi/acpi_device.h | 2 +- lib/acpi/acpi_device.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/acpi/acpi_device.h b/include/acpi/acpi_device.h index 007b7e7caf1..ed4acd912a1 100644 --- a/include/acpi/acpi_device.h +++ b/include/acpi/acpi_device.h @@ -413,7 +413,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, /** * acpi_device_write_i2c_dev() - Write an I2C device to ACPI * - * This creates a I2cSerialBus descriptor for an I2C device, including + * This creates a I2cSerialBusV2 descriptor for an I2C device, including * information ACPI needs to use it. * * @ctx: ACPI context pointer diff --git a/lib/acpi/acpi_device.c b/lib/acpi/acpi_device.c index 8248664a10a..95dfac583fc 100644 --- a/lib/acpi/acpi_device.c +++ b/lib/acpi/acpi_device.c @@ -530,7 +530,7 @@ int acpi_device_write_dsm_i2c_hid(struct acpi_ctx *ctx, return 0; } -/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBus() */ +/* ACPI 6.3 section 6.4.3.8.2.1 - I2cSerialBusV2() */ static void acpi_device_write_i2c(struct acpi_ctx *ctx, const struct acpi_i2c *i2c) { -- cgit v1.3.1 From 308b1a960e3173148a313dfab29a00349168eced Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 22 Sep 2020 21:16:40 -0600 Subject: x86: video: Show information about each video device At present the 'bdinfo' command shows the framebuffer address, but not the address of the copy framebuffer, if present. Add support for this. Signed-off-by: Simon Glass Reviewed-by: Bin Meng --- cmd/bdinfo.c | 32 +++++++++++++++++++++++++++++++- include/video.h | 6 ++---- 2 files changed, 33 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index 0229846d3ea..8d8daa6336a 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -8,9 +8,11 @@ #include #include +#include #include #include #include +#include #include #include @@ -34,6 +36,12 @@ static void print_eth(int idx) printf("%-12s= %s\n", name, val); } +static void print_phys_addr(const char *name, phys_addr_t value) +{ + printf("%-12s= 0x%.*llx\n", name, 2 * (int)sizeof(ulong), + (unsigned long long)value); +} + void bdinfo_print_mhz(const char *name, unsigned long hz) { char buf[32]; @@ -58,6 +66,26 @@ __weak void arch_print_bdinfo(void) { } +static void show_video_info(void) +{ + const struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) { + printf("%-12s= %s %sactive\n", "Video", dev->name, + device_active(dev) ? "" : "in"); + if (device_active(dev)) { + struct video_priv *upriv = dev_get_uclass_priv(dev); + + print_phys_addr("FB base", (ulong)upriv->fb); + if (upriv->copy_fb) + print_phys_addr("FB copy", (ulong)upriv->copy_fb); + printf("%-12s= %dx%dx%d\n", "FB size", upriv->xsize, + upriv->ysize, 1 << upriv->bpix); + } + } +} + int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct bd_info *bd = gd->bd; @@ -86,7 +114,9 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) bdinfo_print_num("fdt_blob", (ulong)gd->fdt_blob); bdinfo_print_num("new_fdt", (ulong)gd->new_fdt); bdinfo_print_num("fdt_size", (ulong)gd->fdt_size); -#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) + if (IS_ENABLED(CONFIG_DM_VIDEO)) + show_video_info(); +#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) bdinfo_print_num("FB base ", gd->fb_base); #endif #if CONFIG_IS_ENABLED(MULTI_DTB_FIT) diff --git a/include/video.h b/include/video.h index 1a0ffd80379..9d09d2409af 100644 --- a/include/video.h +++ b/include/video.h @@ -13,8 +13,6 @@ #ifndef _VIDEO_H_ #define _VIDEO_H_ -#ifdef CONFIG_DM_VIDEO - #include struct udevice; @@ -140,6 +138,7 @@ struct video_ops { */ int video_reserve(ulong *addrp); +#ifdef CONFIG_DM_VIDEO /** * video_clear() - Clear a device's frame buffer to background color. * @@ -147,6 +146,7 @@ int video_reserve(ulong *addrp); * @return 0 */ int video_clear(struct udevice *dev); +#endif /* CONFIG_DM_VIDEO */ /** * video_sync() - Sync a device's frame buffer with its hardware @@ -243,8 +243,6 @@ static inline int video_sync_copy(struct udevice *dev, void *from, void *to) } #endif -#endif /* CONFIG_DM_VIDEO */ - #ifndef CONFIG_DM_VIDEO /* Video functions */ -- cgit v1.3.1 From 16dcfbcd2b9885279892e468ef89915532c31bdd Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Jul 2017 21:28:50 +0200 Subject: ARM: rmobile: Enable RPC on Salvator-X, ULCB, Ebisu Enable the RPC Hyperflash driver on R8A7795,R8A7796,R8A77965 Salvator-X,ULCB and R8A77990 Ebisu. Note that to make the HF accessible, mainline ATF is mandatory and must be built with RCAR_RPC_HYPERFLASH_LOCKED=0 . Note that this is intended for development and testing convenience only and must be disabled in deployment for platform security reasons. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- arch/arm/dts/r8a77950-salvator-x-u-boot.dts | 5 +++++ arch/arm/dts/r8a77950-ulcb-u-boot.dts | 5 +++++ arch/arm/dts/r8a77960-salvator-x-u-boot.dts | 5 +++++ arch/arm/dts/r8a77960-ulcb-u-boot.dts | 5 +++++ arch/arm/dts/r8a77965-salvator-x-u-boot.dts | 5 +++++ arch/arm/dts/r8a77965-ulcb-u-boot.dts | 5 +++++ arch/arm/dts/r8a77990-ebisu-u-boot.dts | 5 +++++ arch/arm/dts/r8a77995-draak-u-boot.dts | 5 +++++ configs/r8a77990_ebisu_defconfig | 5 +++++ configs/rcar3_salvator-x_defconfig | 5 +++++ configs/rcar3_ulcb_defconfig | 5 +++++ include/configs/ebisu.h | 12 ++++++++++++ include/configs/salvator-x.h | 12 ++++++++++++ include/configs/ulcb.h | 12 ++++++++++++ 14 files changed, 91 insertions(+) (limited to 'include') diff --git a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts index e039e33d594..36c8a44a902 100644 --- a/arch/arm/dts/r8a77950-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77950-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77950-salvator-x.dts" #include "r8a77950-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77950-ulcb-u-boot.dts b/arch/arm/dts/r8a77950-ulcb-u-boot.dts index b7f26c11b15..d3191c55d57 100644 --- a/arch/arm/dts/r8a77950-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77950-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts index d3b09246f59..439fd6c3ada 100644 --- a/arch/arm/dts/r8a77960-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77960-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77960-salvator-x.dts" #include "r8a77960-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77960-ulcb-u-boot.dts b/arch/arm/dts/r8a77960-ulcb-u-boot.dts index bd1d6345748..aab9c95931f 100644 --- a/arch/arm/dts/r8a77960-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77960-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts index d6f07085554..8cbef83b9c4 100644 --- a/arch/arm/dts/r8a77965-salvator-x-u-boot.dts +++ b/arch/arm/dts/r8a77965-salvator-x-u-boot.dts @@ -8,6 +8,11 @@ #include "r8a77965-salvator-x.dts" #include "r8a77965-u-boot.dtsi" +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77965-ulcb-u-boot.dts b/arch/arm/dts/r8a77965-ulcb-u-boot.dts index 954d8b685c3..38966bf644e 100644 --- a/arch/arm/dts/r8a77965-ulcb-u-boot.dts +++ b/arch/arm/dts/r8a77965-ulcb-u-boot.dts @@ -19,6 +19,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77990-ebisu-u-boot.dts b/arch/arm/dts/r8a77990-ebisu-u-boot.dts index 0ea0cc9cb1c..6afc0be66e9 100644 --- a/arch/arm/dts/r8a77990-ebisu-u-boot.dts +++ b/arch/arm/dts/r8a77990-ebisu-u-boot.dts @@ -18,6 +18,11 @@ }; }; +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; + &sdhi0 { sd-uhs-sdr12; sd-uhs-sdr25; diff --git a/arch/arm/dts/r8a77995-draak-u-boot.dts b/arch/arm/dts/r8a77995-draak-u-boot.dts index 2f53970809e..10fb9cb3b67 100644 --- a/arch/arm/dts/r8a77995-draak-u-boot.dts +++ b/arch/arm/dts/r8a77995-draak-u-boot.dts @@ -7,3 +7,8 @@ #include "r8a77995-draak.dts" #include "r8a77995-u-boot.dtsi" + +&rpc { + reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0x04000000>; + status = "okay"; +}; diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index efdb8e6eb7e..f94d4256f44 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -49,6 +49,11 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_RENESAS_RPC_HF=y CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 0fbd1e0c826..4537b52c207 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -52,6 +52,11 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_RENESAS_RPC_HF=y CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index 710b2f4a4aa..b90b9e12b38 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -52,6 +52,11 @@ CONFIG_MMC_IO_VOLTAGE=y CONFIG_MMC_UHS_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_NOR_FLASH=y +CONFIG_CFI_FLASH=y +CONFIG_RENESAS_RPC_HF=y CONFIG_BITBANGMII=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h index 06cbb03dc6a..ee9ddb13362 100644 --- a/include/configs/ebisu.h +++ b/include/configs/ebisu.h @@ -22,4 +22,16 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + #endif /* __EBISU_H */ diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h index 240df9c63b9..db06fa5ffd6 100644 --- a/include/configs/salvator-x.h +++ b/include/configs/salvator-x.h @@ -19,4 +19,16 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + #endif /* __SALVATOR_X_H */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h index 15fb6272287..165c82d508e 100644 --- a/include/configs/ulcb.h +++ b/include/configs/ulcb.h @@ -19,4 +19,16 @@ /* Environment in eMMC, at the end of 2nd "boot sector" */ +#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_MTD +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT +#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_WRITE_SWAPPED_DATA + #endif /* __ULCB_H */ -- cgit v1.3.1 From 00407251c377e57f1192f79f90e5f7e1f2bfe975 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Sep 2020 15:36:28 +0100 Subject: arm: dts: r8a774a1: Import DTS from Linux 5.9-rc4 Synchronize RZ/G2M SoC DTs with mainline Linux 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/dts/r8a774a1.dtsi | 10 +-- include/dt-bindings/clock/r8a774a1-cpg-mssr.h | 96 +++++++++++++-------------- include/dt-bindings/power/r8a774a1-sysc.h | 2 - 3 files changed, 51 insertions(+), 57 deletions(-) (limited to 'include') diff --git a/arch/arm/dts/r8a774a1.dtsi b/arch/arm/dts/r8a774a1.dtsi index a603d947970..8e80f50132a 100644 --- a/arch/arm/dts/r8a774a1.dtsi +++ b/arch/arm/dts/r8a774a1.dtsi @@ -10,6 +10,8 @@ #include #include +#define CPG_AUDIO_CLK_I R8A774A1_CLK_S0D4 + / { compatible = "renesas,r8a774a1"; #address-cells = <2>; @@ -2250,7 +2252,7 @@ status = "disabled"; }; - sdhi0: sd@ee100000 { + sdhi0: mmc@ee100000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee100000 0 0x2000>; @@ -2262,7 +2264,7 @@ status = "disabled"; }; - sdhi1: sd@ee120000 { + sdhi1: mmc@ee120000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee120000 0 0x2000>; @@ -2274,7 +2276,7 @@ status = "disabled"; }; - sdhi2: sd@ee140000 { + sdhi2: mmc@ee140000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee140000 0 0x2000>; @@ -2286,7 +2288,7 @@ status = "disabled"; }; - sdhi3: sd@ee160000 { + sdhi3: mmc@ee160000 { compatible = "renesas,sdhi-r8a774a1", "renesas,rcar-gen3-sdhi"; reg = <0 0xee160000 0 0x2000>; diff --git a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h index ac3fde148c6..67bf8cdf496 100644 --- a/include/dt-bindings/clock/r8a774a1-cpg-mssr.h +++ b/include/dt-bindings/clock/r8a774a1-cpg-mssr.h @@ -10,56 +10,50 @@ /* r8a774a1 CPG Core Clocks */ #define R8A774A1_CLK_Z 0 #define R8A774A1_CLK_Z2 1 -#define R8A774A1_CLK_ZR 2 -#define R8A774A1_CLK_ZG 3 -#define R8A774A1_CLK_ZTR 4 -#define R8A774A1_CLK_ZTRD2 5 -#define R8A774A1_CLK_ZT 6 -#define R8A774A1_CLK_ZX 7 -#define R8A774A1_CLK_S0D1 8 -#define R8A774A1_CLK_S0D2 9 -#define R8A774A1_CLK_S0D3 10 -#define R8A774A1_CLK_S0D4 11 -#define R8A774A1_CLK_S0D6 12 -#define R8A774A1_CLK_S0D8 13 -#define R8A774A1_CLK_S0D12 14 -#define R8A774A1_CLK_S1D1 15 -#define R8A774A1_CLK_S1D2 16 -#define R8A774A1_CLK_S1D4 17 -#define R8A774A1_CLK_S2D1 18 -#define R8A774A1_CLK_S2D2 19 -#define R8A774A1_CLK_S2D4 20 -#define R8A774A1_CLK_S3D1 21 -#define R8A774A1_CLK_S3D2 22 -#define R8A774A1_CLK_S3D4 23 -#define R8A774A1_CLK_LB 24 -#define R8A774A1_CLK_CL 25 -#define R8A774A1_CLK_ZB3 26 -#define R8A774A1_CLK_ZB3D2 27 -#define R8A774A1_CLK_ZB3D4 28 -#define R8A774A1_CLK_CR 29 -#define R8A774A1_CLK_CRD2 30 -#define R8A774A1_CLK_SD0H 31 -#define R8A774A1_CLK_SD0 32 -#define R8A774A1_CLK_SD1H 33 -#define R8A774A1_CLK_SD1 34 -#define R8A774A1_CLK_SD2H 35 -#define R8A774A1_CLK_SD2 36 -#define R8A774A1_CLK_SD3H 37 -#define R8A774A1_CLK_SD3 38 -#define R8A774A1_CLK_SSP2 39 -#define R8A774A1_CLK_SSP1 40 -#define R8A774A1_CLK_SSPRS 41 -#define R8A774A1_CLK_RPC 42 -#define R8A774A1_CLK_RPCD2 43 -#define R8A774A1_CLK_MSO 44 -#define R8A774A1_CLK_CANFD 45 -#define R8A774A1_CLK_HDMI 46 -#define R8A774A1_CLK_CSI0 47 -#define R8A774A1_CLK_CSIREF 48 -#define R8A774A1_CLK_CP 49 -#define R8A774A1_CLK_CPEX 50 -#define R8A774A1_CLK_R 51 -#define R8A774A1_CLK_OSC 52 +#define R8A774A1_CLK_ZG 2 +#define R8A774A1_CLK_ZTR 3 +#define R8A774A1_CLK_ZTRD2 4 +#define R8A774A1_CLK_ZT 5 +#define R8A774A1_CLK_ZX 6 +#define R8A774A1_CLK_S0D1 7 +#define R8A774A1_CLK_S0D2 8 +#define R8A774A1_CLK_S0D3 9 +#define R8A774A1_CLK_S0D4 10 +#define R8A774A1_CLK_S0D6 11 +#define R8A774A1_CLK_S0D8 12 +#define R8A774A1_CLK_S0D12 13 +#define R8A774A1_CLK_S1D2 14 +#define R8A774A1_CLK_S1D4 15 +#define R8A774A1_CLK_S2D1 16 +#define R8A774A1_CLK_S2D2 17 +#define R8A774A1_CLK_S2D4 18 +#define R8A774A1_CLK_S3D1 19 +#define R8A774A1_CLK_S3D2 20 +#define R8A774A1_CLK_S3D4 21 +#define R8A774A1_CLK_LB 22 +#define R8A774A1_CLK_CL 23 +#define R8A774A1_CLK_ZB3 24 +#define R8A774A1_CLK_ZB3D2 25 +#define R8A774A1_CLK_ZB3D4 26 +#define R8A774A1_CLK_CR 27 +#define R8A774A1_CLK_CRD2 28 +#define R8A774A1_CLK_SD0H 29 +#define R8A774A1_CLK_SD0 30 +#define R8A774A1_CLK_SD1H 31 +#define R8A774A1_CLK_SD1 32 +#define R8A774A1_CLK_SD2H 33 +#define R8A774A1_CLK_SD2 34 +#define R8A774A1_CLK_SD3H 35 +#define R8A774A1_CLK_SD3 36 +#define R8A774A1_CLK_RPC 37 +#define R8A774A1_CLK_RPCD2 38 +#define R8A774A1_CLK_MSO 39 +#define R8A774A1_CLK_HDMI 40 +#define R8A774A1_CLK_CSI0 41 +#define R8A774A1_CLK_CP 42 +#define R8A774A1_CLK_CPEX 43 +#define R8A774A1_CLK_R 44 +#define R8A774A1_CLK_OSC 45 +#define R8A774A1_CLK_CANFD 46 #endif /* __DT_BINDINGS_CLOCK_R8A774A1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a774a1-sysc.h b/include/dt-bindings/power/r8a774a1-sysc.h index d84ea0eb12f..d35183557c4 100644 --- a/include/dt-bindings/power/r8a774a1-sysc.h +++ b/include/dt-bindings/power/r8a774a1-sysc.h @@ -18,12 +18,10 @@ #define R8A774A1_PD_CA53_CPU2 7 #define R8A774A1_PD_CA53_CPU3 8 #define R8A774A1_PD_CA57_SCU 12 -#define R8A774A1_PD_CR7 13 #define R8A774A1_PD_A3VC 14 #define R8A774A1_PD_3DG_A 17 #define R8A774A1_PD_3DG_B 18 #define R8A774A1_PD_CA53_SCU 21 -#define R8A774A1_PD_A3IR 24 #define R8A774A1_PD_A2VC0 25 #define R8A774A1_PD_A2VC1 26 -- cgit v1.3.1 From 1abdab94f1294989bdffab5adefc2f59e29d1b70 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Sep 2020 09:05:07 +0100 Subject: arm: dts: r8a774b1: Import DTS from Linux 5.9-rc4 Import R8A774B1 (RZ/G2N) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/dts/r8a774b1.dtsi | 2630 +++++++++++++++++++++++++ include/dt-bindings/clock/r8a774b1-cpg-mssr.h | 57 + include/dt-bindings/power/r8a774b1-sysc.h | 26 + 3 files changed, 2713 insertions(+) create mode 100644 arch/arm/dts/r8a774b1.dtsi create mode 100644 include/dt-bindings/clock/r8a774b1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774b1-sysc.h (limited to 'include') diff --git a/arch/arm/dts/r8a774b1.dtsi b/arch/arm/dts/r8a774b1.dtsi new file mode 100644 index 00000000000..23119c0ae7b --- /dev/null +++ b/arch/arm/dts/r8a774b1.dtsi @@ -0,0 +1,2630 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774b1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#define CPG_AUDIO_CLK_I R8A774B1_CLK_S0D4 + +/ { + compatible = "renesas,r8a774b1"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <830000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774B1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774b1-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a774b1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774b1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774b1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774b1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774b1-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774b1-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774b1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a774b1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774b1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774b1", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774b1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a774b1", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x200>; + interrupts = ; + clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0 3>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 704>, <&cpg 703>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a774b1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a774b1-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = , + ; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb3_phy0: usb-phy@e65ee000 { + compatible = "renesas,r8a774b1-usb3-phy", + "renesas,rcar-gen3-usb3-phy"; + reg = <0 0xe65ee000 0 0x90>; + clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, + <&usb_extal_clk>; + clock-names = "usb3-if", "usb3s_clk", "usb_extal"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + #phy-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@e7740000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@e6570000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@e67b0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp: iommu@ec670000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: iommu@fd800000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A774B1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@febd0000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: iommu@fe990000 { + compatible = "renesas,ipmmu-r8a774b1"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774b1", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774b1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a774b1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774B1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + #pwm-cells = <2>; + clocks = <&cpg CPG_MOD 523>; + resets = <&cpg 523>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774b1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774B1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774b1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + vin0: video@e6ef0000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef0000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 811>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 811>; + renesas,id = <0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin0csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin0>; + }; + vin0csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin0>; + }; + }; + }; + }; + + vin1: video@e6ef1000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef1000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 810>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 810>; + renesas,id = <1>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin1csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin1>; + }; + vin1csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin1>; + }; + }; + }; + }; + + vin2: video@e6ef2000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef2000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 809>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 809>; + renesas,id = <2>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin2csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin2>; + }; + vin2csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin2>; + }; + }; + }; + }; + + vin3: video@e6ef3000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef3000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 808>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 808>; + renesas,id = <3>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin3csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin3>; + }; + vin3csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin3>; + }; + }; + }; + }; + + vin4: video@e6ef4000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef4000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 807>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 807>; + renesas,id = <4>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin4csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin4>; + }; + vin4csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin4>; + }; + }; + }; + }; + + vin5: video@e6ef5000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef5000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 806>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 806>; + renesas,id = <5>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin5csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin5>; + }; + vin5csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin5>; + }; + }; + }; + }; + + vin6: video@e6ef6000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef6000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 805>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 805>; + renesas,id = <6>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin6csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin6>; + }; + vin6csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin6>; + }; + }; + }; + }; + + vin7: video@e6ef7000 { + compatible = "renesas,vin-r8a774b1"; + reg = <0 0xe6ef7000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 804>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 804>; + renesas,id = <7>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + vin7csi20: endpoint@0 { + reg = <0>; + remote-endpoint = <&csi20vin7>; + }; + vin7csi40: endpoint@2 { + reg = <2>; + remote-endpoint = <&csi40vin7>; + }; + }; + }; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A774B1_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, + <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, + <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0"; + status = "disabled"; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = ; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = ; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = ; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = ; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = ; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = ; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = ; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = ; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = ; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = ; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = ; + dmas = <&audma0 0x01>, <&audma1 0x02>; + dma-names = "rx", "tx"; + }; + ssi1: ssi-1 { + interrupts = ; + dmas = <&audma0 0x03>, <&audma1 0x04>; + dma-names = "rx", "tx"; + }; + ssi2: ssi-2 { + interrupts = ; + dmas = <&audma0 0x05>, <&audma1 0x06>; + dma-names = "rx", "tx"; + }; + ssi3: ssi-3 { + interrupts = ; + dmas = <&audma0 0x07>, <&audma1 0x08>; + dma-names = "rx", "tx"; + }; + ssi4: ssi-4 { + interrupts = ; + dmas = <&audma0 0x09>, <&audma1 0x0a>; + dma-names = "rx", "tx"; + }; + ssi5: ssi-5 { + interrupts = ; + dmas = <&audma0 0x0b>, <&audma1 0x0c>; + dma-names = "rx", "tx"; + }; + ssi6: ssi-6 { + interrupts = ; + dmas = <&audma0 0x0d>, <&audma1 0x0e>; + dma-names = "rx", "tx"; + }; + ssi7: ssi-7 { + interrupts = ; + dmas = <&audma0 0x0f>, <&audma1 0x10>; + dma-names = "rx", "tx"; + }; + ssi8: ssi-8 { + interrupts = ; + dmas = <&audma0 0x11>, <&audma1 0x12>; + dma-names = "rx", "tx"; + }; + ssi9: ssi-9 { + interrupts = ; + dmas = <&audma0 0x13>, <&audma1 0x14>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssiu { + ssiu00: ssiu-0 { + dmas = <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx"; + }; + ssiu01: ssiu-1 { + dmas = <&audma0 0x35>, <&audma1 0x36>; + dma-names = "rx", "tx"; + }; + ssiu02: ssiu-2 { + dmas = <&audma0 0x37>, <&audma1 0x38>; + dma-names = "rx", "tx"; + }; + ssiu03: ssiu-3 { + dmas = <&audma0 0x47>, <&audma1 0x48>; + dma-names = "rx", "tx"; + }; + ssiu04: ssiu-4 { + dmas = <&audma0 0x3F>, <&audma1 0x40>; + dma-names = "rx", "tx"; + }; + ssiu05: ssiu-5 { + dmas = <&audma0 0x43>, <&audma1 0x44>; + dma-names = "rx", "tx"; + }; + ssiu06: ssiu-6 { + dmas = <&audma0 0x4F>, <&audma1 0x50>; + dma-names = "rx", "tx"; + }; + ssiu07: ssiu-7 { + dmas = <&audma0 0x53>, <&audma1 0x54>; + dma-names = "rx", "tx"; + }; + ssiu10: ssiu-8 { + dmas = <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx"; + }; + ssiu11: ssiu-9 { + dmas = <&audma0 0x4B>, <&audma1 0x4C>; + dma-names = "rx", "tx"; + }; + ssiu12: ssiu-10 { + dmas = <&audma0 0x57>, <&audma1 0x58>; + dma-names = "rx", "tx"; + }; + ssiu13: ssiu-11 { + dmas = <&audma0 0x59>, <&audma1 0x5A>; + dma-names = "rx", "tx"; + }; + ssiu14: ssiu-12 { + dmas = <&audma0 0x5F>, <&audma1 0x60>; + dma-names = "rx", "tx"; + }; + ssiu15: ssiu-13 { + dmas = <&audma0 0xC3>, <&audma1 0xC4>; + dma-names = "rx", "tx"; + }; + ssiu16: ssiu-14 { + dmas = <&audma0 0xC7>, <&audma1 0xC8>; + dma-names = "rx", "tx"; + }; + ssiu17: ssiu-15 { + dmas = <&audma0 0xCB>, <&audma1 0xCC>; + dma-names = "rx", "tx"; + }; + ssiu20: ssiu-16 { + dmas = <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx"; + }; + ssiu21: ssiu-17 { + dmas = <&audma0 0x67>, <&audma1 0x68>; + dma-names = "rx", "tx"; + }; + ssiu22: ssiu-18 { + dmas = <&audma0 0x6B>, <&audma1 0x6C>; + dma-names = "rx", "tx"; + }; + ssiu23: ssiu-19 { + dmas = <&audma0 0x6D>, <&audma1 0x6E>; + dma-names = "rx", "tx"; + }; + ssiu24: ssiu-20 { + dmas = <&audma0 0xCF>, <&audma1 0xCE>; + dma-names = "rx", "tx"; + }; + ssiu25: ssiu-21 { + dmas = <&audma0 0xEB>, <&audma1 0xEC>; + dma-names = "rx", "tx"; + }; + ssiu26: ssiu-22 { + dmas = <&audma0 0xED>, <&audma1 0xEE>; + dma-names = "rx", "tx"; + }; + ssiu27: ssiu-23 { + dmas = <&audma0 0xEF>, <&audma1 0xF0>; + dma-names = "rx", "tx"; + }; + ssiu30: ssiu-24 { + dmas = <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx"; + }; + ssiu31: ssiu-25 { + dmas = <&audma0 0x21>, <&audma1 0x22>; + dma-names = "rx", "tx"; + }; + ssiu32: ssiu-26 { + dmas = <&audma0 0x23>, <&audma1 0x24>; + dma-names = "rx", "tx"; + }; + ssiu33: ssiu-27 { + dmas = <&audma0 0x25>, <&audma1 0x26>; + dma-names = "rx", "tx"; + }; + ssiu34: ssiu-28 { + dmas = <&audma0 0x27>, <&audma1 0x28>; + dma-names = "rx", "tx"; + }; + ssiu35: ssiu-29 { + dmas = <&audma0 0x29>, <&audma1 0x2A>; + dma-names = "rx", "tx"; + }; + ssiu36: ssiu-30 { + dmas = <&audma0 0x2B>, <&audma1 0x2C>; + dma-names = "rx", "tx"; + }; + ssiu37: ssiu-31 { + dmas = <&audma0 0x2D>, <&audma1 0x2E>; + dma-names = "rx", "tx"; + }; + ssiu40: ssiu-32 { + dmas = <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx"; + }; + ssiu41: ssiu-33 { + dmas = <&audma0 0x17>, <&audma1 0x18>; + dma-names = "rx", "tx"; + }; + ssiu42: ssiu-34 { + dmas = <&audma0 0x19>, <&audma1 0x1A>; + dma-names = "rx", "tx"; + }; + ssiu43: ssiu-35 { + dmas = <&audma0 0x1B>, <&audma1 0x1C>; + dma-names = "rx", "tx"; + }; + ssiu44: ssiu-36 { + dmas = <&audma0 0x1D>, <&audma1 0x1E>; + dma-names = "rx", "tx"; + }; + ssiu45: ssiu-37 { + dmas = <&audma0 0x1F>, <&audma1 0x20>; + dma-names = "rx", "tx"; + }; + ssiu46: ssiu-38 { + dmas = <&audma0 0x31>, <&audma1 0x32>; + dma-names = "rx", "tx"; + }; + ssiu47: ssiu-39 { + dmas = <&audma0 0x33>, <&audma1 0x34>; + dma-names = "rx", "tx"; + }; + ssiu50: ssiu-40 { + dmas = <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx"; + }; + ssiu60: ssiu-41 { + dmas = <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx"; + }; + ssiu70: ssiu-42 { + dmas = <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx"; + }; + ssiu80: ssiu-43 { + dmas = <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx"; + }; + ssiu90: ssiu-44 { + dmas = <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx"; + }; + ssiu91: ssiu-45 { + dmas = <&audma0 0x7F>, <&audma1 0x80>; + dma-names = "rx", "tx"; + }; + ssiu92: ssiu-46 { + dmas = <&audma0 0x81>, <&audma1 0x82>; + dma-names = "rx", "tx"; + }; + ssiu93: ssiu-47 { + dmas = <&audma0 0x83>, <&audma1 0x84>; + dma-names = "rx", "tx"; + }; + ssiu94: ssiu-48 { + dmas = <&audma0 0xA3>, <&audma1 0xA4>; + dma-names = "rx", "tx"; + }; + ssiu95: ssiu-49 { + dmas = <&audma0 0xA5>, <&audma1 0xA6>; + dma-names = "rx", "tx"; + }; + ssiu96: ssiu-50 { + dmas = <&audma0 0xA7>, <&audma1 0xA8>; + dma-names = "rx", "tx"; + }; + ssiu97: ssiu-51 { + dmas = <&audma0 0xA9>, <&audma1 0xAA>; + dma-names = "rx", "tx"; + }; + }; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a774b1", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a774b1", + "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + usb3_peri0: usb@ee020000 { + compatible = "renesas,r8a774b1-usb3-peri", + "renesas,rcar-gen3-usb3-peri"; + reg = <0 0xee020000 0 0x400>; + interrupts = ; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 1>; + phy-names = "usb"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + phys = <&usb2_phy0 2>; + phy-names = "usb"; + companion = <&ohci0>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1 2>; + phy-names = "usb"; + companion = <&ohci1>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a774b1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 703>, <&cpg 704>; + #phy-cells = <1>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a774b1", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <1>; + status = "disabled"; + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a774b1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a774b1", + "renesas,rcar-gen3-sata"; + reg = <0 0xee300000 0 0x200000>; + interrupts = ; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774b1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + ; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = ; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 615>; + }; + + vspb: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = ; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x5000>; + interrupts = ; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 607>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A774B1_PD_A3VP>; + resets = <&cpg 611>; + }; + + csi20: csi2@fea80000 { + compatible = "renesas,r8a774b1-csi2"; + reg = <0 0xfea80000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 714>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi20vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi20>; + }; + csi20vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi20>; + }; + csi20vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi20>; + }; + csi20vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi20>; + }; + csi20vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi20>; + }; + csi20vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi20>; + }; + csi20vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi20>; + }; + csi20vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi20>; + }; + }; + }; + }; + + csi40: csi2@feaa0000 { + compatible = "renesas,r8a774b1-csi2"; + reg = <0 0xfeaa0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 716>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + + reg = <1>; + + csi40vin0: endpoint@0 { + reg = <0>; + remote-endpoint = <&vin0csi40>; + }; + csi40vin1: endpoint@1 { + reg = <1>; + remote-endpoint = <&vin1csi40>; + }; + csi40vin2: endpoint@2 { + reg = <2>; + remote-endpoint = <&vin2csi40>; + }; + csi40vin3: endpoint@3 { + reg = <3>; + remote-endpoint = <&vin3csi40>; + }; + csi40vin4: endpoint@4 { + reg = <4>; + remote-endpoint = <&vin4csi40>; + }; + csi40vin5: endpoint@5 { + reg = <5>; + remote-endpoint = <&vin5csi40>; + }; + csi40vin6: endpoint@6 { + reg = <6>; + remote-endpoint = <&vin6csi40>; + }; + csi40vin7: endpoint@7 { + reg = <7>; + remote-endpoint = <&vin7csi40>; + }; + }; + }; + }; + + hdmi0: hdmi@fead0000 { + compatible = "renesas,r8a774b1-hdmi", + "renesas,rcar-gen3-hdmi"; + reg = <0 0xfead0000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD 729>, + <&cpg CPG_CORE R8A774B1_CLK_HDMI>; + clock-names = "iahb", "isfr"; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 729>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dw_hdmi0_in: endpoint { + remote-endpoint = <&du_out_hdmi0>; + }; + }; + port@1 { + reg = <1>; + }; + port@2 { + /* HDMI sound */ + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a774b1"; + reg = <0 0xfeb00000 0 0x80000>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 721>; + clock-names = "du.0", "du.1", "du.3"; + resets = <&cpg 724>, <&cpg 722>; + reset-names = "du.0", "du.3"; + status = "disabled"; + + renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + remote-endpoint = <&dw_hdmi0_in>; + }; + }; + port@2 { + reg = <2>; + du_out_lvds0: endpoint { + remote-endpoint = <&lvds0_in>; + }; + }; + }; + }; + + lvds0: lvds@feb90000 { + compatible = "renesas,r8a774b1-lvds"; + reg = <0 0xfeb90000 0 0x14>; + clocks = <&cpg CPG_MOD 727>; + power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; + resets = <&cpg 727>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&du_out_lvds0>; + }; + }; + port@1 { + reg = <1>; + lvds0_out: endpoint { + }; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <2439>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <2439>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <2439>; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + }; + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; diff --git a/include/dt-bindings/clock/r8a774b1-cpg-mssr.h b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h new file mode 100644 index 00000000000..28e0f8f76ca --- /dev/null +++ b/include/dt-bindings/clock/r8a774b1-cpg-mssr.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ + +#include + +/* r8a774b1 CPG Core Clocks */ +#define R8A774B1_CLK_Z 0 +#define R8A774B1_CLK_ZG 1 +#define R8A774B1_CLK_ZTR 2 +#define R8A774B1_CLK_ZTRD2 3 +#define R8A774B1_CLK_ZT 4 +#define R8A774B1_CLK_ZX 5 +#define R8A774B1_CLK_S0D1 6 +#define R8A774B1_CLK_S0D2 7 +#define R8A774B1_CLK_S0D3 8 +#define R8A774B1_CLK_S0D4 9 +#define R8A774B1_CLK_S0D6 10 +#define R8A774B1_CLK_S0D8 11 +#define R8A774B1_CLK_S0D12 12 +#define R8A774B1_CLK_S1D2 13 +#define R8A774B1_CLK_S1D4 14 +#define R8A774B1_CLK_S2D1 15 +#define R8A774B1_CLK_S2D2 16 +#define R8A774B1_CLK_S2D4 17 +#define R8A774B1_CLK_S3D1 18 +#define R8A774B1_CLK_S3D2 19 +#define R8A774B1_CLK_S3D4 20 +#define R8A774B1_CLK_LB 21 +#define R8A774B1_CLK_CL 22 +#define R8A774B1_CLK_ZB3 23 +#define R8A774B1_CLK_ZB3D2 24 +#define R8A774B1_CLK_CR 25 +#define R8A774B1_CLK_DDR 26 +#define R8A774B1_CLK_SD0H 27 +#define R8A774B1_CLK_SD0 28 +#define R8A774B1_CLK_SD1H 29 +#define R8A774B1_CLK_SD1 30 +#define R8A774B1_CLK_SD2H 31 +#define R8A774B1_CLK_SD2 32 +#define R8A774B1_CLK_SD3H 33 +#define R8A774B1_CLK_SD3 34 +#define R8A774B1_CLK_RPC 35 +#define R8A774B1_CLK_RPCD2 36 +#define R8A774B1_CLK_MSO 37 +#define R8A774B1_CLK_HDMI 38 +#define R8A774B1_CLK_CSI0 39 +#define R8A774B1_CLK_CP 40 +#define R8A774B1_CLK_CPEX 41 +#define R8A774B1_CLK_R 42 +#define R8A774B1_CLK_OSC 43 +#define R8A774B1_CLK_CANFD 44 + +#endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a774b1-sysc.h b/include/dt-bindings/power/r8a774b1-sysc.h new file mode 100644 index 00000000000..96afda0446b --- /dev/null +++ b/include/dt-bindings/power/r8a774b1-sysc.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774B1_PD_CA57_CPU0 0 +#define R8A774B1_PD_CA57_CPU1 1 +#define R8A774B1_PD_A3VP 9 +#define R8A774B1_PD_CA57_SCU 12 +#define R8A774B1_PD_A3VC 14 +#define R8A774B1_PD_3DG_A 17 +#define R8A774B1_PD_3DG_B 18 +#define R8A774B1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774B1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774B1_SYSC_H__ */ -- cgit v1.3.1 From 3afde5aab671870a0ea1a02bddae3788e07765d0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 16 Sep 2020 11:38:04 +0100 Subject: arm: dts: r8a774e1: Import DTS from Linux 5.9-rc4 Import R8A774E1 (RZ/G2H) SoC DTSI and headers from upstream Linux kernel 5.9-rc4 commit f4d51dffc6c0 ("Linux 5.9-rc4") Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar --- arch/arm/dts/r8a774e1.dtsi | 1664 +++++++++++++++++++++++++ include/dt-bindings/clock/r8a774e1-cpg-mssr.h | 59 + include/dt-bindings/power/r8a774e1-sysc.h | 36 + 3 files changed, 1759 insertions(+) create mode 100644 arch/arm/dts/r8a774e1.dtsi create mode 100644 include/dt-bindings/clock/r8a774e1-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a774e1-sysc.h (limited to 'include') diff --git a/arch/arm/dts/r8a774e1.dtsi b/arch/arm/dts/r8a774e1.dtsi new file mode 100644 index 00000000000..0f86cfd5242 --- /dev/null +++ b/arch/arm/dts/r8a774e1.dtsi @@ -0,0 +1,1664 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the r8a774e1 SoC + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ + +#include +#include +#include +#include + +#define CPG_AUDIO_CLK_I R8A774E1_CLK_S0D4 + +/ { + compatible = "renesas,r8a774e1"; + #address-cells = <2>; + #size-cells = <2>; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + cluster0_opp: opp_table0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + opp-suspend; + }; + }; + + cluster1_opp: opp_table1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <820000>; + clock-latency-ns = <300000>; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&a57_0>; + }; + core1 { + cpu = <&a57_1>; + }; + core2 { + cpu = <&a57_2>; + }; + core3 { + cpu = <&a57_3>; + }; + }; + + cluster1 { + core0 { + cpu = <&a53_0>; + }; + core1 { + cpu = <&a53_1>; + }; + core2 { + cpu = <&a53_2>; + }; + core3 { + cpu = <&a53_3>; + }; + }; + }; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + dynamic-power-coefficient = <854>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z>; + operating-points-v2 = <&cluster0_opp>; + capacity-dmips-mhz = <1024>; + #cooling-cells = <2>; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + #cooling-cells = <2>; + dynamic-power-coefficient = <277>; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A774E1_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + clocks = <&cpg CPG_CORE R8A774E1_CLK_Z2>; + operating-points-v2 = <&cluster1_opp>; + capacity-dmips-mhz = <535>; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A774E1_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, <&a57_1>, <&a57_2>, <&a57_3>; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + rwdt: watchdog@e6020000 { + compatible = "renesas,r8a774e1-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + interrupts = ; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a774e1", + "renesas,rcar-gen3-gpio"; + reg = <0 0xe6055800 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a774e1"; + reg = <0 0xe6060000 0 0x50c>; + }; + + cmt0: timer@e60f0000 { + compatible = "renesas,r8a774e1-cmt0", + "renesas,rcar-gen3-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 303>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 303>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 302>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 302>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 301>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 301>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a774e1-cmt1", + "renesas,rcar-gen3-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 300>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 300>; + status = "disabled"; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a774e1-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a774e1-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a774e1-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a774e1-thermal"; + reg = <0 0xe6198000 0 0x100>, + <0 0xe61a0000 0 0x100>, + <0 0xe61a8000 0 0x100>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a774e1", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 125>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 125>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 124>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 124>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 123>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 123>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 122>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 122>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a774e1", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 121>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 121>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a774e1", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a774e1", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 926>; + dmas = <&dmac0 0x11>, <&dmac0 0x10>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a774e1", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + reg = <0 0xe6590000 0 0x200>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_phy0: usb-phy@e65ee000 { + reg = <0 0xe65ee000 0 0x90>; + #phy-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, + <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, + <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, + <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, + <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, + <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, + <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, + <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, + <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, + <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, + <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, + <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, + <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, + <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, + <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a774e1", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, + <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, + <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, + <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, + <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, + <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, + <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, + <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; + }; + + ipmmu_ds0: iommu@e6740000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe6740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 0>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_ds1: iommu@e7740000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe7740000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 1>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_hc: iommu@e6570000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe6570000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 2>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mm: iommu@e67b0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xe67b0000 0 0x1000>; + interrupts = , + ; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_mp0: iommu@ec670000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xec670000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 4>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv0: iommu@fd800000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd800000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 6>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv1: iommu@fd950000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd950000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 7>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv2: iommu@fd960000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd960000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 8>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_pv3: iommu@fd970000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfd970000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 9>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vc0: iommu@fe6b0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe6b0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 12>; + power-domains = <&sysc R8A774E1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vc1: iommu@fe6f0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe6f0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 13>; + power-domains = <&sysc R8A774E1_PD_A3VC>; + #iommu-cells = <1>; + }; + + ipmmu_vi0: iommu@febd0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfebd0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 14>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vi1: iommu@febe0000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfebe0000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 15>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + #iommu-cells = <1>; + }; + + ipmmu_vp0: iommu@fe990000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe990000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 16>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + #iommu-cells = <1>; + }; + + ipmmu_vp1: iommu@fe980000 { + compatible = "renesas,ipmmu-r8a774e1"; + reg = <0 0xfe980000 0 0x1000>; + renesas,ipmmu-main = <&ipmmu_mm 17>; + power-domains = <&sysc R8A774E1_PD_A3VP>; + #iommu-cells = <1>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a774e1", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii"; + iommus = <&ipmmu_ds0 16>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a774e1", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a774e1-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A774E1_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A774E1_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + pwm0: pwm@e6e30000 { + reg = <0 0xe6e30000 0 0x8>; + #pwm-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>, + <&dmac2 0x13>, <&dmac2 0x12>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a774e1", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A774E1_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a774e1", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + status = "disabled"; + + /* placeholder */ + + rcar_sound,ssi { + ssi2: ssi-2 { + /* placeholder */ + }; + }; + }; + + xhci0: usb@ee000000 { + reg = <0 0xee000000 0 0xc00>; + status = "disabled"; + + /* placeholder */ + }; + + usb3_peri0: usb@ee020000 { + reg = <0 0xee020000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ohci0: usb@ee080000 { + reg = <0 0xee080000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ohci1: usb@ee0a0000 { + reg = <0 0xee0a0000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci0: usb@ee080100 { + reg = <0 0xee080100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci1: usb@ee0a0100 { + reg = <0 0xee0a0100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy0: usb-phy@ee080200 { + reg = <0 0xee080200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy1: usb-phy@ee0a0200 { + reg = <0 0xee0a0200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee100000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 314>; + iommus = <&ipmmu_ds1 32>; + status = "disabled"; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee120000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 313>; + iommus = <&ipmmu_ds1 33>; + status = "disabled"; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 312>; + iommus = <&ipmmu_ds1 34>; + status = "disabled"; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a774e1", + "renesas,rcar-gen3-sdhi"; + reg = <0 0xee160000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 311>; + iommus = <&ipmmu_ds1 35>; + status = "disabled"; + }; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = ; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + pciec0: pcie@fe000000 { + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + status = "disabled"; + + /* placeholder */ + }; + + hdmi0: hdmi@fead0000 { + reg = <0 0xfead0000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + du: display@feb00000 { + reg = <0 0xfeb00000 0 0x80000>; + status = "disabled"; + + /* placeholder */ + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + port@1 { + reg = <1>; + }; + port@2 { + reg = <2>; + }; + }; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + sustainable-power = <6313>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + sustainable-power = <6313>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + sustainable-power = <6313>; + + trips { + target: trip-point1 { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = <&a57_0 0 2>; + contribution = <1024>; + }; + + map1 { + trip = <&target>; + cooling-device = <&a53_0 0 2>; + contribution = <1024>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + /* External USB clocks - can be overridden by the board */ + usb3s0_clk: usb3s0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; +}; diff --git a/include/dt-bindings/clock/r8a774e1-cpg-mssr.h b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h new file mode 100644 index 00000000000..b2fc1d1c3c4 --- /dev/null +++ b/include/dt-bindings/clock/r8a774e1-cpg-mssr.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ + +#include + +/* R8A774E1 CPG Core Clocks */ +#define R8A774E1_CLK_Z 0 +#define R8A774E1_CLK_Z2 1 +#define R8A774E1_CLK_ZG 2 +#define R8A774E1_CLK_ZTR 3 +#define R8A774E1_CLK_ZTRD2 4 +#define R8A774E1_CLK_ZT 5 +#define R8A774E1_CLK_ZX 6 +#define R8A774E1_CLK_S0D1 7 +#define R8A774E1_CLK_S0D2 8 +#define R8A774E1_CLK_S0D3 9 +#define R8A774E1_CLK_S0D4 10 +#define R8A774E1_CLK_S0D6 11 +#define R8A774E1_CLK_S0D8 12 +#define R8A774E1_CLK_S0D12 13 +#define R8A774E1_CLK_S1D2 14 +#define R8A774E1_CLK_S1D4 15 +#define R8A774E1_CLK_S2D1 16 +#define R8A774E1_CLK_S2D2 17 +#define R8A774E1_CLK_S2D4 18 +#define R8A774E1_CLK_S3D1 19 +#define R8A774E1_CLK_S3D2 20 +#define R8A774E1_CLK_S3D4 21 +#define R8A774E1_CLK_LB 22 +#define R8A774E1_CLK_CL 23 +#define R8A774E1_CLK_ZB3 24 +#define R8A774E1_CLK_ZB3D2 25 +#define R8A774E1_CLK_ZB3D4 26 +#define R8A774E1_CLK_CR 27 +#define R8A774E1_CLK_CRD2 28 +#define R8A774E1_CLK_SD0H 29 +#define R8A774E1_CLK_SD0 30 +#define R8A774E1_CLK_SD1H 31 +#define R8A774E1_CLK_SD1 32 +#define R8A774E1_CLK_SD2H 33 +#define R8A774E1_CLK_SD2 34 +#define R8A774E1_CLK_SD3H 35 +#define R8A774E1_CLK_SD3 36 +#define R8A774E1_CLK_RPC 37 +#define R8A774E1_CLK_RPCD2 38 +#define R8A774E1_CLK_MSO 39 +#define R8A774E1_CLK_HDMI 40 +#define R8A774E1_CLK_CSI0 41 +#define R8A774E1_CLK_CP 42 +#define R8A774E1_CLK_CPEX 43 +#define R8A774E1_CLK_R 44 +#define R8A774E1_CLK_OSC 45 +#define R8A774E1_CLK_CANFD 46 + +#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a774e1-sysc.h b/include/dt-bindings/power/r8a774e1-sysc.h new file mode 100644 index 00000000000..7edb8161db3 --- /dev/null +++ b/include/dt-bindings/power/r8a774e1-sysc.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2020 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A774E1_PD_CA57_CPU0 0 +#define R8A774E1_PD_CA57_CPU1 1 +#define R8A774E1_PD_CA57_CPU2 2 +#define R8A774E1_PD_CA57_CPU3 3 +#define R8A774E1_PD_CA53_CPU0 5 +#define R8A774E1_PD_CA53_CPU1 6 +#define R8A774E1_PD_CA53_CPU2 7 +#define R8A774E1_PD_CA53_CPU3 8 +#define R8A774E1_PD_A3VP 9 +#define R8A774E1_PD_CA57_SCU 12 +#define R8A774E1_PD_A3VC 14 +#define R8A774E1_PD_3DG_A 17 +#define R8A774E1_PD_3DG_B 18 +#define R8A774E1_PD_3DG_C 19 +#define R8A774E1_PD_3DG_D 20 +#define R8A774E1_PD_CA53_SCU 21 +#define R8A774E1_PD_3DG_E 22 +#define R8A774E1_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A774E1_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A774E1_SYSC_H__ */ -- cgit v1.3.1 From 3576121687965ffe580fc44f5dd1d8e9ab434c5b Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 28 Sep 2020 10:52:22 -0400 Subject: timer: Add helper for drivers using timebase fallback This function is designed to be used when a timer used to be initialized by the cpu (e.g. RISC-V timers), but now is initialized by dm_timer_init. In such a case, the timer may prefer to use the clocks and clock-frequency properties, but should be able to fall back on using the cpu's timebase-frequency. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- drivers/timer/timer-uclass.c | 31 +++++++++++++++++++++++++++++++ include/timer.h | 15 +++++++++++++++ 2 files changed, 46 insertions(+) (limited to 'include') diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c index 14dde950a18..e9802c8b43e 100644 --- a/drivers/timer/timer-uclass.c +++ b/drivers/timer/timer-uclass.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -79,6 +80,36 @@ static int timer_post_probe(struct udevice *dev) return 0; } +/* + * TODO: should be CONFIG_IS_ENABLED(CPU), but the SPL config has _SUPPORT on + * the end... + */ +#if defined(CONFIG_CPU) || defined(CONFIG_SPL_CPU_SUPPORT) +int timer_timebase_fallback(struct udevice *dev) +{ + struct udevice *cpu; + struct cpu_platdata *cpu_plat; + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + + /* Did we get our clock rate from the device tree? */ + if (uc_priv->clock_rate) + return 0; + + /* Fall back to timebase-frequency */ + dev_dbg(dev, "missing clocks or clock-frequency property; falling back on timebase-frequency\n"); + cpu = cpu_get_current_dev(); + if (!cpu) + return -ENODEV; + + cpu_plat = dev_get_parent_platdata(cpu); + if (!cpu_plat) + return -ENODEV; + + uc_priv->clock_rate = cpu_plat->timebase_freq; + return 0; +} +#endif + u64 timer_conv_64(u32 count) { /* increment tbh if tbl has rolled over */ diff --git a/include/timer.h b/include/timer.h index a49b500ce35..8b9fa51c53d 100644 --- a/include/timer.h +++ b/include/timer.h @@ -15,6 +15,21 @@ */ int dm_timer_init(void); +/** + * timer_timebase_fallback() - Helper for timers using timebase fallback + * @dev: A timer partially-probed timer device + * + * This is a helper function designed for timers which need to fall back on the + * cpu's timebase. This function is designed to be called during the driver's + * probe(). If there is a clocks or clock-frequency property in the timer's + * binding, then it will be used. Otherwise, the timebase of the current cpu + * will be used. This is initialized by the cpu driver, and usually gotten from + * ``/cpus/timebase-frequency`` or ``/cpus/cpu@X/timebase-frequency``. + * + * Return: 0 if OK, or negative error code on failure + */ +int timer_timebase_fallback(struct udevice *dev); + /* * timer_conv_64 - convert 32-bit counter value to 64-bit * -- cgit v1.3.1 From a952c3a4546ba1d6c5a487cae2e73760ecfd0c60 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Mon, 28 Sep 2020 10:52:27 -0400 Subject: riscv: clk: Add CLINT clock to kendryte clock driver Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson --- drivers/clk/kendryte/clk.c | 4 ++++ include/dt-bindings/clock/k210-sysctl.h | 1 + 2 files changed, 5 insertions(+) (limited to 'include') diff --git a/drivers/clk/kendryte/clk.c b/drivers/clk/kendryte/clk.c index 981b3b7699b..bb196961afd 100644 --- a/drivers/clk/kendryte/clk.c +++ b/drivers/clk/kendryte/clk.c @@ -646,6 +646,10 @@ static int k210_clk_probe(struct udevice *dev) REGISTER_GATE(K210_CLK_RTC, "rtc", in0); #undef REGISTER_GATE + /* The MTIME register in CLINT runs at one 50th the CPU clock speed */ + clk_dm(K210_CLK_CLINT, + clk_register_fixed_factor(NULL, "clint", "cpu", 0, 1, 50)); + return 0; } diff --git a/include/dt-bindings/clock/k210-sysctl.h b/include/dt-bindings/clock/k210-sysctl.h index 0e3ed3fb9fa..fe852bbd92a 100644 --- a/include/dt-bindings/clock/k210-sysctl.h +++ b/include/dt-bindings/clock/k210-sysctl.h @@ -55,5 +55,6 @@ #define K210_CLK_OTP 43 #define K210_CLK_RTC 44 #define K210_CLK_ACLK 45 +#define K210_CLK_CLINT 46 #endif /* CLOCK_K210_SYSCTL_H */ -- cgit v1.3.1 From 68fd6026623a60a718c69a86efc644c396c5d834 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 15 Sep 2020 10:44:45 -0400 Subject: mmc: Add mmc_dev() This macro is necessary for arasan_zynqmp_dll_reset to compile. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Tested-by: Patrick Delaunay --- include/mmc.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/mmc.h b/include/mmc.h index 82562193cc4..75bcaaf6b35 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -888,6 +888,8 @@ void mmc_set_preinit(struct mmc *mmc, int preinit); #define mmc_host_is_spi(mmc) 0 #endif +#define mmc_dev(x) ((x)->dev) + void board_mmc_power_init(void); int board_mmc_init(struct bd_info *bis); int cpu_mmc_init(struct bd_info *bis); -- cgit v1.3.1 From 69876c54de27f8cd7ac3ed73a4a1f1dc5b7ebb1a Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 15 Sep 2020 10:44:58 -0400 Subject: linux/compat.h: Remove netdev_xxx functions No drivers in U-Boot use these functions. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Tested-by: Patrick Delaunay --- include/linux/compat.h | 19 ------------------- 1 file changed, 19 deletions(-) (limited to 'include') diff --git a/include/linux/compat.h b/include/linux/compat.h index 363b2b94255..d1297803122 100644 --- a/include/linux/compat.h +++ b/include/linux/compat.h @@ -52,25 +52,6 @@ extern struct p_current *current; #define dev_warn(dev, fmt, args...) \ printf(fmt, ##args) -#define netdev_emerg(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_alert(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_crit(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_err(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_warn(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_notice(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_info(dev, fmt, args...) \ - printf(fmt, ##args) -#define netdev_dbg(dev, fmt, args...) \ - debug(fmt, ##args) -#define netdev_vdbg(dev, fmt, args...) \ - debug(fmt, ##args) - #define GFP_ATOMIC ((gfp_t) 0) #define GFP_KERNEL ((gfp_t) 0) #define GFP_NOFS ((gfp_t) 0) -- cgit v1.3.1 From b608c54b522c04098ba34471beed214127672931 Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 15 Sep 2020 10:45:07 -0400 Subject: remoteproc: Remove unused function rproc_elf_sanity_check This function is never used anywhere, and it also tries to log with a nonexistant device. Signed-off-by: Sean Anderson Tested-by: Patrick Delaunay --- drivers/remoteproc/rproc-elf-loader.c | 16 ---------------- include/remoteproc.h | 13 ------------- 2 files changed, 29 deletions(-) (limited to 'include') diff --git a/drivers/remoteproc/rproc-elf-loader.c b/drivers/remoteproc/rproc-elf-loader.c index c464ecebb77..b185a6cafb8 100644 --- a/drivers/remoteproc/rproc-elf-loader.c +++ b/drivers/remoteproc/rproc-elf-loader.c @@ -158,22 +158,6 @@ int rproc_elf64_sanity_check(ulong addr, ulong size) return 0; } -/* Basic function to verify ELF image format */ -int rproc_elf_sanity_check(ulong addr, ulong size) -{ - Elf32_Ehdr *ehdr = (Elf32_Ehdr *)addr; - - if (!addr) { - dev_err(dev, "Invalid firmware address\n"); - return -EFAULT; - } - - if (ehdr->e_ident[EI_CLASS] == ELFCLASS64) - return rproc_elf64_sanity_check(addr, size); - else - return rproc_elf32_sanity_check(addr, size); -} - int rproc_elf32_load_image(struct udevice *dev, unsigned long addr, ulong size) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ diff --git a/include/remoteproc.h b/include/remoteproc.h index a903acb9b24..74d01723f6a 100644 --- a/include/remoteproc.h +++ b/include/remoteproc.h @@ -226,19 +226,6 @@ int rproc_elf32_sanity_check(ulong addr, ulong size); */ int rproc_elf64_sanity_check(ulong addr, ulong size); -/** - * rproc_elf_sanity_check() - Verify if an image is a valid ELF one - * - * Check if a valid ELF image exists at the given memory location. Auto - * detects ELF32/ELF64 and verifies basic ELF64/ELF32 format requirements - * like magic number and sections size. - * - * @addr: address of the image to verify - * @size: size of the image - * @return 0 if the image looks good, else appropriate error value. - */ -int rproc_elf_sanity_check(ulong addr, ulong size); - /** * rproc_elf32_load_image() - load an ELF32 image * @dev: device loading the ELF32 image -- cgit v1.3.1 From 4d14600bf6b80676278594890e50222d5ad3e7ba Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 15 Sep 2020 10:45:21 -0400 Subject: dm: Use symbolic constants for log levels in dev_xxx This substitutes literal log levels with their symbolic constants. Signed-off-by: Sean Anderson Reviewed-by: Simon Glass Tested-by: Patrick Delaunay --- include/dm/device_compat.h | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/dm/device_compat.h b/include/dm/device_compat.h index 3d8cd09f4c0..7c14aa464d9 100644 --- a/include/dm/device_compat.h +++ b/include/dm/device_compat.h @@ -10,6 +10,7 @@ #ifndef _DM_DEVICE_COMPAT_H #define _DM_DEVICE_COMPAT_H +#include #include /* @@ -48,28 +49,28 @@ }) #define dev_emerg(dev, fmt, ...) \ - __dev_printk(0, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_EMERG, dev, fmt, ##__VA_ARGS__) #define dev_alert(dev, fmt, ...) \ - __dev_printk(1, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_ALERT, dev, fmt, ##__VA_ARGS__) #define dev_crit(dev, fmt, ...) \ - __dev_printk(2, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_CRIT, dev, fmt, ##__VA_ARGS__) #define dev_err(dev, fmt, ...) \ - __dev_printk(3, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_ERR, dev, fmt, ##__VA_ARGS__) #define dev_warn(dev, fmt, ...) \ - __dev_printk(4, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_WARNING, dev, fmt, ##__VA_ARGS__) #define dev_notice(dev, fmt, ...) \ - __dev_printk(5, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_NOTICE, dev, fmt, ##__VA_ARGS__) #define dev_info(dev, fmt, ...) \ - __dev_printk(6, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_INFO, dev, fmt, ##__VA_ARGS__) #ifdef DEBUG #define dev_dbg(dev, fmt, ...) \ - __dev_printk(7, dev, fmt, ##__VA_ARGS__) + __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__) #else #define dev_dbg(dev, fmt, ...) \ ({ \ if (0) \ - __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ + __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__); \ }) #endif @@ -79,7 +80,7 @@ #define dev_vdbg(dev, fmt, ...) \ ({ \ if (0) \ - __dev_printk(7, dev, fmt, ##__VA_ARGS__); \ + __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__); \ }) #endif -- cgit v1.3.1 From ceb70bb870ac0761992d3e38e9287a338e3b846a Mon Sep 17 00:00:00 2001 From: Sean Anderson Date: Tue, 15 Sep 2020 10:45:22 -0400 Subject: dm: Print device name in dev_xxx like Linux This adorns messages generated by dev_xxx with the device and driver names. It also redirects dev_xxx to log when it is available. The names of these functions very roughly take inspiration from Linux, but there is no deeper correlation. Both struct udevice and struct device are supported when logging, though logging with struct device is no better than using log_xxx. The latter is supported because of the large amount of existing code which logs with struct device. Signed-off-by: Sean Anderson Tested-by: Patrick Delaunay --- include/dm/device_compat.h | 110 +++++++++++++++++++++++++++++++++------------ 1 file changed, 82 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/include/dm/device_compat.h b/include/dm/device_compat.h index 7c14aa464d9..8f26053b450 100644 --- a/include/dm/device_compat.h +++ b/include/dm/device_compat.h @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* + * Copyright (C) 2020 Sean Anderson * Copyright (c) 2013 Google, Inc * * (C) Copyright 2012 @@ -11,6 +12,7 @@ #define _DM_DEVICE_COMPAT_H #include +#include #include /* @@ -34,18 +36,87 @@ #endif /* - * REVISIT: - * print device name like Linux + * Define a new identifier which can be tested on by C code. A similar + * definition is made for DEBUG in . */ -#define dev_printk(dev, fmt, ...) \ -({ \ - printk(fmt, ##__VA_ARGS__); \ +#ifdef VERBOSE_DEBUG +#define _VERBOSE_DEBUG 1 +#else +#define _VERBOSE_DEBUG 0 +#endif + +/** + * dev_printk_emit() - Emit a formatted log message + * @cat: Category of the message + * @level: Log level of the message + * @fmt: Format string + * @...: Arguments for @fmt + * + * This macro logs a message through the appropriate channel. It is a macro so + * the if statements can be optimized out (as @level should be a constant known + * at compile-time). + * + * If DEBUG or VERBOSE_DEBUG is defined, then some messages are always printed + * (through printf()). This is to match the historical behavior of the dev_xxx + * functions. + * + * If LOG is enabled, use log() to emit the message, otherwise print it based on + * the console loglevel. + */ +#define dev_printk_emit(cat, level, fmt, ...) \ +({ \ + if ((_DEBUG && level == LOGL_DEBUG) || \ + (_VERBOSE_DEBUG && level == LOGL_DEBUG_CONTENT)) \ + printf(fmt, ##__VA_ARGS__); \ + else if (CONFIG_IS_ENABLED(LOG)) \ + log(cat, level, fmt, ##__VA_ARGS__); \ + else if (level < CONFIG_VAL(LOGLEVEL)) \ + printf(fmt, ##__VA_ARGS__); \ }) -#define __dev_printk(level, dev, fmt, ...) \ -({ \ - if (level < CONFIG_VAL(LOGLEVEL)) \ - dev_printk(dev, fmt, ##__VA_ARGS__); \ +/** + * __dev_printk() - Log a message for a device + * @level: Log level of the message + * @dev: A &struct udevice or &struct device + * @fmt: Format string + * @...: Arguments for @fmt + * + * This macro formats and prints dev_xxx log messages. It is done as a macro + * because working with variadic argument is much easier this way, we can + * interrogate the type of device we are passed (and whether it *is* a &struct + * udevice or &struct device), and dev_printk_emit() can optimize out unused if + * branches. + * + * Because this is a macro, we must enforce type checks ourselves. Ideally, we + * would only accept udevices, but there is a significant amount of code (mostly + * USB) which calls dev_xxx with &struct device. When assigning ``__dev``, we + * must first cast ``dev`` to ``void *`` so we don't get warned when ``dev`` is + * a &struct device. Even though the latter branch is not taken, it will still + * get compiled and type-checked. + * + * The format strings in case of a ``NULL`` ``dev`` MUST be kept the same. + * Otherwise, @fmt will be duplicated in the data section (with slightly + * different prefixes). This is why ``(NULL udevice *)`` is printed as two + * string arguments, and not by string pasting. + */ +#define __dev_printk(level, dev, fmt, ...) \ +({ \ + if (__same_type(dev, struct device *)) { \ + dev_printk_emit(LOG_CATEGORY, level, fmt, ##__VA_ARGS__); \ + } else { \ + BUILD_BUG_ON(!__same_type(dev, struct udevice *)); \ + struct udevice *__dev = (void *)dev; \ + if (__dev) \ + dev_printk_emit(__dev->driver->id, level, \ + "%s %s: " fmt, \ + __dev->driver->name, __dev->name, \ + ##__VA_ARGS__); \ + else \ + dev_printk_emit(LOG_CATEGORY, level, \ + "%s %s: " fmt, \ + "(NULL", "udevice *)", \ + ##__VA_ARGS__); \ + } \ }) #define dev_emerg(dev, fmt, ...) \ @@ -62,26 +133,9 @@ __dev_printk(LOGL_NOTICE, dev, fmt, ##__VA_ARGS__) #define dev_info(dev, fmt, ...) \ __dev_printk(LOGL_INFO, dev, fmt, ##__VA_ARGS__) - -#ifdef DEBUG #define dev_dbg(dev, fmt, ...) \ __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__) -#else -#define dev_dbg(dev, fmt, ...) \ -({ \ - if (0) \ - __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__); \ -}) -#endif - -#ifdef VERBOSE_DEBUG -#define dev_vdbg dev_dbg -#else -#define dev_vdbg(dev, fmt, ...) \ -({ \ - if (0) \ - __dev_printk(LOGL_DEBUG, dev, fmt, ##__VA_ARGS__); \ -}) -#endif +#define dev_vdbg(dev, fmt, ...) \ + __dev_printk(LOGL_DEBUG_CONTENT, dev, fmt, ##__VA_ARGS__) #endif -- cgit v1.3.1 From 139e4a1cbe60de96d4febbc6db5882929801ca46 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Wed, 9 Sep 2020 15:37:03 +0530 Subject: drivers: reset: Add a managed API to get reset controllers from the DT Add managed functions to get a reset_ctl from the device-tree, based on a name or an index. Also add a managed functions to get a reset_ctl_bulk (array of reset_ctl) from the device-tree. When the device is unbound, the reset controllers are automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- drivers/reset/reset-uclass.c | 118 +++++++++++++++++++++++++++++++++++-- include/reset.h | 135 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 248 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/drivers/reset/reset-uclass.c b/drivers/reset/reset-uclass.c index 5e38ce5c066..e7e407ca350 100644 --- a/drivers/reset/reset-uclass.c +++ b/drivers/reset/reset-uclass.c @@ -11,6 +11,7 @@ #include #include #include +#include static inline struct reset_ops *reset_dev_ops(struct udevice *dev) { @@ -100,13 +101,14 @@ int reset_get_by_index_nodev(ofnode node, int index, index > 0, reset_ctl); } -int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) +static int __reset_get_bulk(struct udevice *dev, ofnode node, + struct reset_ctl_bulk *bulk) { int i, ret, err, count; - + bulk->count = 0; - count = dev_count_phandle_with_args(dev, "resets", "#reset-cells"); + count = ofnode_count_phandle_with_args(node, "resets", "#reset-cells"); if (count < 1) return count; @@ -116,7 +118,7 @@ int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) return -ENOMEM; for (i = 0; i < count; i++) { - ret = reset_get_by_index(dev, i, &bulk->resets[i]); + ret = reset_get_by_index_nodev(node, i, &bulk->resets[i]); if (ret < 0) goto bulk_get_err; @@ -134,6 +136,11 @@ bulk_get_err: return ret; } +int reset_get_bulk(struct udevice *dev, struct reset_ctl_bulk *bulk) +{ + return __reset_get_bulk(dev, dev_ofnode(dev), bulk); +} + int reset_get_by_name(struct udevice *dev, const char *name, struct reset_ctl *reset_ctl) { @@ -246,6 +253,109 @@ int reset_release_all(struct reset_ctl *reset_ctl, int count) return 0; } +static void devm_reset_release(struct udevice *dev, void *res) +{ + reset_free(res); +} + +struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev, + int index) +{ + int rc; + struct reset_ctl *reset_ctl; + + reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl), + __GFP_ZERO); + if (unlikely(!reset_ctl)) + return ERR_PTR(-ENOMEM); + + rc = reset_get_by_index(dev, index, reset_ctl); + if (rc) + return ERR_PTR(rc); + + devres_add(dev, reset_ctl); + return reset_ctl; +} + +struct reset_ctl *devm_reset_control_get(struct udevice *dev, const char *id) +{ + int rc; + struct reset_ctl *reset_ctl; + + reset_ctl = devres_alloc(devm_reset_release, sizeof(struct reset_ctl), + __GFP_ZERO); + if (unlikely(!reset_ctl)) + return ERR_PTR(-ENOMEM); + + rc = reset_get_by_name(dev, id, reset_ctl); + if (rc) + return ERR_PTR(rc); + + devres_add(dev, reset_ctl); + return reset_ctl; +} + +struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev, + const char *id) +{ + struct reset_ctl *r = devm_reset_control_get(dev, id); + + if (IS_ERR(r)) + return NULL; + + return r; +} + +static void devm_reset_bulk_release(struct udevice *dev, void *res) +{ + struct reset_ctl_bulk *bulk = res; + + reset_release_all(bulk->resets, bulk->count); +} + +struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev, + ofnode node) +{ + int rc; + struct reset_ctl_bulk *bulk; + + bulk = devres_alloc(devm_reset_bulk_release, + sizeof(struct reset_ctl_bulk), + __GFP_ZERO); + if (unlikely(!bulk)) + return ERR_PTR(-ENOMEM); + + rc = __reset_get_bulk(dev, node, bulk); + if (rc) + return ERR_PTR(rc); + + devres_add(dev, bulk); + return bulk; +} + +struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev, + ofnode node) +{ + struct reset_ctl_bulk *bulk; + + bulk = devm_reset_bulk_get_by_node(dev, node); + + if (IS_ERR(bulk)) + return NULL; + + return bulk; +} + +struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev) +{ + return devm_reset_bulk_get_by_node(dev, dev_ofnode(dev)); +} + +struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev) +{ + return devm_reset_bulk_get_optional_by_node(dev, dev_ofnode(dev)); +} + UCLASS_DRIVER(reset) = { .id = UCLASS_RESET, .name = "reset", diff --git a/include/reset.h b/include/reset.h index 4fac4e6a202..cde2c4b4a8c 100644 --- a/include/reset.h +++ b/include/reset.h @@ -7,7 +7,7 @@ #define _RESET_H #include -#include +#include /** * A reset is a hardware signal indicating that a HW module (or IP block, or @@ -84,6 +84,98 @@ struct reset_ctl_bulk { }; #if CONFIG_IS_ENABLED(DM_RESET) + +/** + * devm_reset_control_get - resource managed reset_get_by_name() + * @dev: device to be reset by the controller + * @id: reset line name + * + * Managed reset_get_by_name(). For reset controllers returned + * from this function, reset_free() is called automatically on driver + * detach. + * + * Returns a struct reset_ctl or IS_ERR() condition containing errno. + */ +struct reset_ctl *devm_reset_control_get(struct udevice *dev, const char *id); + +/** + * devm_reset_control_get_optional - resource managed reset_get_by_name() that + * can fail + * @dev: The client device. + * @id: reset line name + * + * Managed reset_get_by_name(). For reset controllers returned + * from this function, reset_free() is called automatically on driver + * detach. + * + * Returns a struct reset_ctl or a dummy reset controller if it failed. + */ +struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev, + const char *id); + +/** + * devm_reset_control_get - resource managed reset_get_by_index() + * @dev: The client device. + * @index: The index of the reset signal to request, within the client's + * list of reset signals. + * + * Managed reset_get_by_index(). For reset controllers returned + * from this function, reset_free() is called automatically on driver + * detach. + * + * Returns a struct reset_ctl or IS_ERR() condition containing errno. + */ +struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev, + int index); + +/** + * devm_reset_bulk_get - resource managed reset_get_bulk() + * @dev: device to be reset by the controller + * + * Managed reset_get_bulk(). For reset controllers returned + * from this function, reset_free() is called automatically on driver + * detach. + * + * Returns a struct reset_ctl or IS_ERR() condition containing errno. + */ +struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev); + +/** + * devm_reset_bulk_get_optional - resource managed reset_get_bulk() that + * can fail + * @dev: The client device. + * + * Managed reset_get_bulk(). For reset controllers returned + * from this function, reset_free() is called automatically on driver + * detach. + * + * Returns a struct reset_ctl or NULL if it failed. + */ +struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev); + +/** + * devm_reset_bulk_get_by_node - resource managed reset_get_bulk() + * @dev: device to be reset by the controller + * @node: ofnode where the "resets" property is. Usually a sub-node of + * the dev's node. + * + * see devm_reset_bulk_get() + */ +struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev, + ofnode node); + +/** + * devm_reset_bulk_get_optional_by_node - resource managed reset_get_bulk() + * that can fail + * @dev: device to be reset by the controller + * @node: ofnode where the "resets" property is. Usually a sub-node of + * the dev's node. + * + * see devm_reset_bulk_get_optional() + */ +struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev, + ofnode node); + /** * reset_get_by_index - Get/request a reset signal by integer index. * @@ -265,7 +357,48 @@ static inline int reset_release_bulk(struct reset_ctl_bulk *bulk) { return reset_release_all(bulk->resets, bulk->count); } + #else +static inline struct reset_ctl *devm_reset_control_get(struct udevice *dev, + const char *id) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct reset_ctl *devm_reset_control_get_optional(struct udevice *dev, + const char *id) +{ + return NULL; +} + +static inline struct reset_ctl *devm_reset_control_get_by_index(struct udevice *dev, + int index) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct reset_ctl_bulk *devm_reset_bulk_get(struct udevice *dev) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct reset_ctl_bulk *devm_reset_bulk_get_optional(struct udevice *dev) +{ + return NULL; +} + +static inline struct reset_ctl_bulk *devm_reset_bulk_get_by_node(struct udevice *dev, + ofnode node) +{ + return ERR_PTR(-ENOTSUPP); +} + +static inline struct reset_ctl_bulk *devm_reset_bulk_get_optional_by_node(struct udevice *dev, + ofnode node) +{ + return NULL; +} + static inline int reset_get_by_index(struct udevice *dev, int index, struct reset_ctl *reset_ctl) { -- cgit v1.3.1 From d4b722e3a85f3a5704501f3a71faa43db1979209 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Fri, 11 Sep 2020 13:43:34 +0530 Subject: drivers: gpio: Add a managed API to get a GPIO from the device-tree Add managed functions to get a gpio from the devce-tree, based on a property name (minus the '-gpios' suffix) and optionally an index. When the device is unbound, the GPIO is automatically released and the data structure is freed. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- drivers/gpio/gpio-uclass.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++ include/asm-generic/gpio.h | 47 ++++++++++++++++++++++++++++++ 2 files changed, 118 insertions(+) (limited to 'include') diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-uclass.c index 9c53299b6a3..0c01413b587 100644 --- a/drivers/gpio/gpio-uclass.c +++ b/drivers/gpio/gpio-uclass.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include #include #include #include @@ -1209,6 +1211,75 @@ int gpio_dev_request_index(struct udevice *dev, const char *nodename, flags, 0, dev); } +static void devm_gpiod_release(struct udevice *dev, void *res) +{ + dm_gpio_free(dev, res); +} + +static int devm_gpiod_match(struct udevice *dev, void *res, void *data) +{ + return res == data; +} + +struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id, + unsigned int index, int flags) +{ + int rc; + struct gpio_desc *desc; + char *propname; + static const char suffix[] = "-gpios"; + + propname = malloc(strlen(id) + sizeof(suffix)); + if (!propname) { + rc = -ENOMEM; + goto end; + } + + strcpy(propname, id); + strcat(propname, suffix); + + desc = devres_alloc(devm_gpiod_release, sizeof(struct gpio_desc), + __GFP_ZERO); + if (unlikely(!desc)) { + rc = -ENOMEM; + goto end; + } + + rc = gpio_request_by_name(dev, propname, index, desc, flags); + +end: + if (propname) + free(propname); + + if (rc) + return ERR_PTR(rc); + + devres_add(dev, desc); + + return desc; +} + +struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev, + const char *id, + unsigned int index, + int flags) +{ + struct gpio_desc *desc = devm_gpiod_get_index(dev, id, index, flags); + + if (IS_ERR(desc)) + return NULL; + + return desc; +} + +void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc) +{ + int rc; + + rc = devres_release(dev, devm_gpiod_release, devm_gpiod_match, desc); + WARN_ON(rc); +} + static int gpio_post_bind(struct udevice *dev) { struct udevice *child; diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h index a57dd2665ce..3ae1894a981 100644 --- a/include/asm-generic/gpio.h +++ b/include/asm-generic/gpio.h @@ -701,4 +701,51 @@ int gpio_get_number(const struct gpio_desc *desc); */ int gpio_get_acpi(const struct gpio_desc *desc, struct acpi_gpio *gpio); +/** + * devm_gpiod_get_index - Resource-managed gpiod_get() + * @dev: GPIO consumer + * @con_id: function within the GPIO consumer + * @index: index of the GPIO to obtain in the consumer + * @flags: optional GPIO initialization flags + * + * Managed gpiod_get(). GPIO descriptors returned from this function are + * automatically disposed on device unbind. + * Return the GPIO descriptor corresponding to the function con_id of device + * dev, -ENOENT if no GPIO has been assigned to the requested function, or + * another IS_ERR() code if an error occurred while trying to acquire the GPIO. + */ +struct gpio_desc *devm_gpiod_get_index(struct udevice *dev, const char *id, + unsigned int index, int flags); + +#define devm_gpiod_get(dev, id, flags) devm_gpiod_get_index(dev, id, 0, flags) +/** + * gpiod_get_optional - obtain an optional GPIO for a given GPIO function + * @dev: GPIO consumer, can be NULL for system-global GPIOs + * @con_id: function within the GPIO consumer + * @index: index of the GPIO to obtain in the consumer + * @flags: optional GPIO initialization flags + * + * This is equivalent to devm_gpiod_get(), except that when no GPIO was + * assigned to the requested function it will return NULL. This is convenient + * for drivers that need to handle optional GPIOs. + */ +struct gpio_desc *devm_gpiod_get_index_optional(struct udevice *dev, + const char *id, + unsigned int index, + int flags); + +#define devm_gpiod_get_optional(dev, id, flags) \ + devm_gpiod_get_index_optional(dev, id, 0, flags) + +/** + * devm_gpiod_put - Resource-managed gpiod_put() + * @dev: GPIO consumer + * @desc: GPIO descriptor to dispose of + * + * Dispose of a GPIO descriptor obtained with devm_gpiod_get() or + * devm_gpiod_get_index(). Normally this function will not be called as the GPIO + * will be disposed of by the resource management code. + */ +void devm_gpiod_put(struct udevice *dev, struct gpio_desc *desc); + #endif /* _ASM_GENERIC_GPIO_H_ */ -- cgit v1.3.1 From ffb22f6b847d21b30831c91294ec21d6a5e80ed4 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Thu, 24 Sep 2020 10:04:10 +0530 Subject: regmap: Add devm_regmap_init() Most of new linux drivers are using managed-API to allocate resources. To ease porting drivers from linux to U-Boot, introduce devm_regmap_init() as a managed API to get a regmap from the device tree. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- drivers/core/regmap.c | 29 +++++++++++++++++++++++++++++ include/regmap.h | 18 ++++++++++++++++++ 2 files changed, 47 insertions(+) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index a67a237b88f..74225361fd6 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -14,7 +14,10 @@ #include #include #include +#include #include +#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -228,6 +231,32 @@ err: return ret; } + +static void devm_regmap_release(struct udevice *dev, void *res) +{ + regmap_uninit(*(struct regmap **)res); +} + +struct regmap *devm_regmap_init(struct udevice *dev, + const struct regmap_bus *bus, + void *bus_context, + const struct regmap_config *config) +{ + int rc; + struct regmap **mapp; + + mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *), + __GFP_ZERO); + if (unlikely(!mapp)) + return ERR_PTR(-ENOMEM); + + rc = regmap_init_mem(dev_ofnode(dev), mapp); + if (rc) + return ERR_PTR(rc); + + devres_add(dev, mapp); + return *mapp; +} #endif void *regmap_get_range(struct regmap *map, unsigned int range_num) diff --git a/include/regmap.h b/include/regmap.h index 30183c5e711..c7dd240a74f 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -75,6 +75,9 @@ struct regmap_range { ulong size; }; +struct regmap_bus; +struct regmap_config; + /** * struct regmap - a way of accessing hardware/bus registers * @@ -335,6 +338,21 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); +/** + * devm_regmap_init() - Initialise register map (device managed) + * + * @dev: Device that will be interacted with + * @bus: Bus-specific callbacks to use with device (IGNORED) + * @bus_context: Data passed to bus-specific callbacks (IGNORED) + * @config: Configuration for register map (IGNORED) + * + * @Return a valid pointer to a struct regmap or a ERR_PTR() on error. + * The structure is automatically freed when the device is unbound + */ +struct regmap *devm_regmap_init(struct udevice *dev, + const struct regmap_bus *bus, + void *bus_context, + const struct regmap_config *config); /** * regmap_get_range() - Obtain the base memory address of a regmap range * -- cgit v1.3.1 From 78aaedba9f1b92335a4f0ce8344f6abf7a63dccb Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 24 Sep 2020 10:04:12 +0530 Subject: regmap: Allow specifying read/write width Right now, regmap_read() and regmap_write() read/write a 32-bit value only. To write other lengths, regmap_raw_read() and regmap_raw_write() need to be used. This means that any driver ported from Linux that relies on regmap_{read,write}() to know the size already has to be updated at each callsite. This makes the port harder to maintain. So, allow specifying the read/write width to make it easier to port the drivers, since now the only change needed is when initializing the regmap. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- drivers/core/regmap.c | 15 ++++++++++++--- include/regmap.h | 38 ++++++++++++++++++++++---------------- 2 files changed, 34 insertions(+), 19 deletions(-) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 809f58489f0..c71b961234a 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -25,6 +25,10 @@ DECLARE_GLOBAL_DATA_PTR; * regmap_alloc() - Allocate a regmap with a given number of ranges. * * @count: Number of ranges to be allocated for the regmap. + * + * The default regmap width is set to REGMAP_SIZE_32. Callers can override it + * if they need. + * * Return: A pointer to the newly allocated regmap, or NULL on error. */ static struct regmap *regmap_alloc(int count) @@ -36,6 +40,7 @@ static struct regmap *regmap_alloc(int count) if (!map) return NULL; map->range_count = count; + map->width = REGMAP_SIZE_32; return map; } @@ -244,7 +249,7 @@ struct regmap *devm_regmap_init(struct udevice *dev, const struct regmap_config *config) { int rc; - struct regmap **mapp; + struct regmap **mapp, *map; mapp = devres_alloc(devm_regmap_release, sizeof(struct regmap *), __GFP_ZERO); @@ -255,6 +260,10 @@ struct regmap *devm_regmap_init(struct udevice *dev, if (rc) return ERR_PTR(rc); + map = *mapp; + if (config) + map->width = config->width; + devres_add(dev, mapp); return *mapp; } @@ -377,7 +386,7 @@ int regmap_raw_read(struct regmap *map, uint offset, void *valp, size_t val_len) int regmap_read(struct regmap *map, uint offset, uint *valp) { - return regmap_raw_read(map, offset, valp, REGMAP_SIZE_32); + return regmap_raw_read(map, offset, valp, map->width); } static inline void __write_8(u8 *addr, const u8 *val, @@ -487,7 +496,7 @@ int regmap_raw_write(struct regmap *map, uint offset, const void *val, int regmap_write(struct regmap *map, uint offset, uint val) { - return regmap_raw_write(map, offset, &val, REGMAP_SIZE_32); + return regmap_raw_write(map, offset, &val, map->width); } int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val) diff --git a/include/regmap.h b/include/regmap.h index c7dd240a74f..19474e6de12 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -76,16 +76,28 @@ struct regmap_range { }; struct regmap_bus; -struct regmap_config; + +/** + * struct regmap_config - Configure the behaviour of a regmap + * + * @width: Width of the read/write operations. Defaults to + * REGMAP_SIZE_32 if set to 0. + */ +struct regmap_config { + enum regmap_size_t width; +}; /** * struct regmap - a way of accessing hardware/bus registers * + * @width: Width of the read/write operations. Defaults to + * REGMAP_SIZE_32 if set to 0. * @range_count: Number of ranges available within the map * @ranges: Array of ranges */ struct regmap { enum regmap_endianness_t endianness; + enum regmap_size_t width; int range_count; struct regmap_range ranges[0]; }; @@ -96,32 +108,24 @@ struct regmap { */ /** - * regmap_write() - Write a 32-bit value to a regmap + * regmap_write() - Write a value to a regmap * * @map: Regmap to write to * @offset: Offset in the regmap to write to * @val: Data to write to the regmap at the specified offset * - * Note that this function will only write values of 32 bit width to the - * regmap; if the size of data to be read is different, the regmap_raw_write - * function can be used. - * * Return: 0 if OK, -ve on error */ int regmap_write(struct regmap *map, uint offset, uint val); /** - * regmap_read() - Read a 32-bit value from a regmap + * regmap_read() - Read a value from a regmap * * @map: Regmap to read from * @offset: Offset in the regmap to read from * @valp: Pointer to the buffer to receive the data read from the regmap * at the specified offset * - * Note that this function will only read values of 32 bit width from the - * regmap; if the size of data to be read is different, the regmap_raw_read - * function can be used. - * * Return: 0 if OK, -ve on error */ int regmap_read(struct regmap *map, uint offset, uint *valp); @@ -135,8 +139,9 @@ int regmap_read(struct regmap *map, uint offset, uint *valp); * @val_len: Length of the data to be written to the regmap * * Note that this function will, as opposed to regmap_write, write data of - * arbitrary length to the regmap, and not just 32-bit values, and is thus a - * generalized version of regmap_write. + * arbitrary length to the regmap, and not just the size configured in the + * regmap (defaults to 32-bit) and is thus a generalized version of + * regmap_write. * * Return: 0 if OK, -ve on error */ @@ -153,8 +158,9 @@ int regmap_raw_write(struct regmap *map, uint offset, const void *val, * @val_len: Length of the data to be read from the regmap * * Note that this function will, as opposed to regmap_read, read data of - * arbitrary length from the regmap, and not just 32-bit values, and is thus a - * generalized version of regmap_read. + * arbitrary length from the regmap, and not just the size configured in the + * regmap (defaults to 32-bit) and is thus a generalized version of + * regmap_read. * * Return: 0 if OK, -ve on error */ @@ -344,7 +350,7 @@ int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); * @dev: Device that will be interacted with * @bus: Bus-specific callbacks to use with device (IGNORED) * @bus_context: Data passed to bus-specific callbacks (IGNORED) - * @config: Configuration for register map (IGNORED) + * @config: Configuration for register map * * @Return a valid pointer to a struct regmap or a ERR_PTR() on error. * The structure is automatically freed when the device is unbound -- cgit v1.3.1 From 7aa5ddffe7fbafe7ef828088ba1dbc76270300c5 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 24 Sep 2020 10:04:13 +0530 Subject: regmap: Allow left shifting register offset before access Drivers can configure it to adjust the final read/write location. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- drivers/core/regmap.c | 6 +++++- include/regmap.h | 6 ++++++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index c71b961234a..173ae808909 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -261,8 +261,10 @@ struct regmap *devm_regmap_init(struct udevice *dev, return ERR_PTR(rc); map = *mapp; - if (config) + if (config) { map->width = config->width; + map->reg_offset_shift = config->reg_offset_shift; + } devres_add(dev, mapp); return *mapp; @@ -349,6 +351,7 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, } range = &map->ranges[range_num]; + offset <<= map->reg_offset_shift; if (offset + val_len > range->size) { debug("%s: offset/size combination invalid\n", __func__); return -ERANGE; @@ -458,6 +461,7 @@ int regmap_raw_write_range(struct regmap *map, uint range_num, uint offset, } range = &map->ranges[range_num]; + offset <<= map->reg_offset_shift; if (offset + val_len > range->size) { debug("%s: offset/size combination invalid\n", __func__); return -ERANGE; diff --git a/include/regmap.h b/include/regmap.h index 19474e6de12..e6c59dfbced 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -82,9 +82,12 @@ struct regmap_bus; * * @width: Width of the read/write operations. Defaults to * REGMAP_SIZE_32 if set to 0. + * @reg_offset_shift Left shift the register offset by this value before + * performing read or write. */ struct regmap_config { enum regmap_size_t width; + u32 reg_offset_shift; }; /** @@ -92,12 +95,15 @@ struct regmap_config { * * @width: Width of the read/write operations. Defaults to * REGMAP_SIZE_32 if set to 0. + * @reg_offset_shift Left shift the register offset by this value before + * performing read or write. * @range_count: Number of ranges available within the map * @ranges: Array of ranges */ struct regmap { enum regmap_endianness_t endianness; enum regmap_size_t width; + u32 reg_offset_shift; int range_count; struct regmap_range ranges[0]; }; -- cgit v1.3.1 From 0e01a7c3f4b6a42f768a19f7fc1df92d3e3b5d37 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 24 Sep 2020 10:04:14 +0530 Subject: regmap: Add regmap_init_mem_range() Right now, the base of a regmap can only be obtained from the device tree. This makes it impossible for devices which calculate the base at runtime to use a regmap. An example of such a device is the Cadence Sierra PHY. Allow creating a regmap with one range whose start and size can be specified by the driver based on calculations at runtime. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- drivers/core/regmap.c | 27 +++++++++++++++++++++++++++ include/regmap.h | 19 +++++++++++++++++++ 2 files changed, 46 insertions(+) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index 173ae808909..a9087df32b9 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -164,6 +164,33 @@ err: return ret; } +int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size, + struct regmap **mapp) +{ + struct regmap *map; + struct regmap_range *range; + + map = regmap_alloc(1); + if (!map) + return -ENOMEM; + + range = &map->ranges[0]; + range->start = r_start; + range->size = r_size; + + if (ofnode_read_bool(node, "little-endian")) + map->endianness = REGMAP_LITTLE_ENDIAN; + else if (ofnode_read_bool(node, "big-endian")) + map->endianness = REGMAP_BIG_ENDIAN; + else if (ofnode_read_bool(node, "native-endian")) + map->endianness = REGMAP_NATIVE_ENDIAN; + else /* Default: native endianness */ + map->endianness = REGMAP_NATIVE_ENDIAN; + + *mapp = map; + return 0; +} + int regmap_init_mem(ofnode node, struct regmap **mapp) { struct regmap_range *range; diff --git a/include/regmap.h b/include/regmap.h index e6c59dfbced..7c8ad047599 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -350,6 +350,25 @@ int regmap_init_mem_platdata(struct udevice *dev, fdt_val_t *reg, int count, int regmap_init_mem_index(ofnode node, struct regmap **mapp, int index); +/** + * regmap_init_mem_range() - Set up a new memory region for ofnode with the + * specified range. + * + * @node: The ofnode for the map. + * @r_start: Start of the range. + * @r_size: Size of the range. + * @mapp: Returns allocated map. + * + * Return: 0 in success, -errno otherwise + * + * This creates a regmap with one range where instead of extracting the range + * from 'node', it is created based on the parameters specified. This is + * useful when a driver needs to calculate the base of the regmap at runtime, + * and can't specify it in device tree. + */ +int regmap_init_mem_range(ofnode node, ulong r_start, ulong r_size, + struct regmap **mapp); + /** * devm_regmap_init() - Initialise register map (device managed) * -- cgit v1.3.1 From d8babb9598ce237ffb1feccb576c66a21c52e5f7 Mon Sep 17 00:00:00 2001 From: Pratyush Yadav Date: Thu, 24 Sep 2020 10:04:15 +0530 Subject: regmap: Allow devices to specify regmap range start and size in config Some devices need to calculate the regmap base address at runtime. This makes it impossible to use device tree to get the regmap base. Instead, allow devices to specify it in the regmap config. This will create a regmap with a single range that corresponds to the start and size given by the driver. Signed-off-by: Pratyush Yadav Reviewed-by: Simon Glass --- drivers/core/regmap.c | 6 +++++- include/regmap.h | 6 ++++++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index a9087df32b9..a3da0cf7c3f 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -283,7 +283,11 @@ struct regmap *devm_regmap_init(struct udevice *dev, if (unlikely(!mapp)) return ERR_PTR(-ENOMEM); - rc = regmap_init_mem(dev_ofnode(dev), mapp); + if (config && config->r_size != 0) + rc = regmap_init_mem_range(dev_ofnode(dev), config->r_start, + config->r_size, mapp); + else + rc = regmap_init_mem(dev_ofnode(dev), mapp); if (rc) return ERR_PTR(rc); diff --git a/include/regmap.h b/include/regmap.h index 7c8ad047599..7a6fcc7f53b 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -84,10 +84,16 @@ struct regmap_bus; * REGMAP_SIZE_32 if set to 0. * @reg_offset_shift Left shift the register offset by this value before * performing read or write. + * @r_start: If specified, the regmap is created with one range + * which starts at this address, instead of finding the + * start from device tree. + * @r_size: Same as above for the range size */ struct regmap_config { enum regmap_size_t width; u32 reg_offset_shift; + ulong r_start; + ulong r_size; }; /** -- cgit v1.3.1 From 1c4db59d9bf711e7f8902eaa145959429d659679 Mon Sep 17 00:00:00 2001 From: Jean-Jacques Hiblot Date: Thu, 24 Sep 2020 10:04:16 +0530 Subject: regmap: Add support for regmap fields A regmap field is an abstraction available in Linux. It provides to access bitfields in a regmap without having to worry about shifts and masks. Signed-off-by: Jean-Jacques Hiblot Reviewed-by: Simon Glass Signed-off-by: Pratyush Yadav --- drivers/core/regmap.c | 83 ++++++++++++++++++++++++++++++++++ include/regmap.h | 122 ++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 205 insertions(+) (limited to 'include') diff --git a/drivers/core/regmap.c b/drivers/core/regmap.c index a3da0cf7c3f..c2bed88eac4 100644 --- a/drivers/core/regmap.c +++ b/drivers/core/regmap.c @@ -18,6 +18,20 @@ #include #include #include +#include + +/* + * Internal representation of a regmap field. Instead of storing the MSB and + * LSB, store the shift and mask. This makes the code a bit cleaner and faster + * because the shift and mask don't have to be calculated every time. + */ +struct regmap_field { + struct regmap *regmap; + unsigned int mask; + /* lsb */ + unsigned int shift; + unsigned int reg; +}; DECLARE_GLOBAL_DATA_PTR; @@ -547,3 +561,72 @@ int regmap_update_bits(struct regmap *map, uint offset, uint mask, uint val) return regmap_write(map, offset, reg | (val & mask)); } + +int regmap_field_read(struct regmap_field *field, unsigned int *val) +{ + int ret; + unsigned int reg_val; + + ret = regmap_read(field->regmap, field->reg, ®_val); + if (ret != 0) + return ret; + + reg_val &= field->mask; + reg_val >>= field->shift; + *val = reg_val; + + return ret; +} + +int regmap_field_write(struct regmap_field *field, unsigned int val) +{ + return regmap_update_bits(field->regmap, field->reg, field->mask, + val << field->shift); +} + +static void regmap_field_init(struct regmap_field *rm_field, + struct regmap *regmap, + struct reg_field reg_field) +{ + rm_field->regmap = regmap; + rm_field->reg = reg_field.reg; + rm_field->shift = reg_field.lsb; + rm_field->mask = GENMASK(reg_field.msb, reg_field.lsb); +} + +struct regmap_field *devm_regmap_field_alloc(struct udevice *dev, + struct regmap *regmap, + struct reg_field reg_field) +{ + struct regmap_field *rm_field = devm_kzalloc(dev, sizeof(*rm_field), + GFP_KERNEL); + if (!rm_field) + return ERR_PTR(-ENOMEM); + + regmap_field_init(rm_field, regmap, reg_field); + + return rm_field; +} + +void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field) +{ + devm_kfree(dev, field); +} + +struct regmap_field *regmap_field_alloc(struct regmap *regmap, + struct reg_field reg_field) +{ + struct regmap_field *rm_field = kzalloc(sizeof(*rm_field), GFP_KERNEL); + + if (!rm_field) + return ERR_PTR(-ENOMEM); + + regmap_field_init(rm_field, regmap, reg_field); + + return rm_field; +} + +void regmap_field_free(struct regmap_field *field) +{ + kfree(field); +} diff --git a/include/regmap.h b/include/regmap.h index 7a6fcc7f53b..c6258face30 100644 --- a/include/regmap.h +++ b/include/regmap.h @@ -312,6 +312,43 @@ int regmap_raw_read_range(struct regmap *map, uint range_num, uint offset, regmap_read_poll_timeout_test(map, addr, val, cond, sleep_us, \ timeout_ms, 0) \ +/** + * regmap_field_read_poll_timeout - Poll until a condition is met or a timeout + * occurs + * + * @field: Regmap field to read from + * @val: Unsigned integer variable to read the value into + * @cond: Break condition (usually involving @val) + * @sleep_us: Maximum time to sleep between reads in us (0 tight-loops). + * @timeout_ms: Timeout in ms, 0 means never timeout + * + * Returns 0 on success and -ETIMEDOUT upon a timeout or the regmap_field_read + * error return value in case of a error read. In the two former cases, + * the last read value at @addr is stored in @val. + * + * This is modelled after the regmap_read_poll_timeout macros in linux but + * with millisecond timeout. + */ +#define regmap_field_read_poll_timeout(field, val, cond, sleep_us, timeout_ms) \ +({ \ + unsigned long __start = get_timer(0); \ + int __ret; \ + for (;;) { \ + __ret = regmap_field_read((field), &(val)); \ + if (__ret) \ + break; \ + if (cond) \ + break; \ + if ((timeout_ms) && get_timer(__start) > (timeout_ms)) { \ + __ret = regmap_field_read((field), &(val)); \ + break; \ + } \ + if ((sleep_us)) \ + udelay((sleep_us)); \ + } \ + __ret ?: ((cond) ? 0 : -ETIMEDOUT); \ +}) + /** * regmap_update_bits() - Perform a read/modify/write using a mask * @@ -407,4 +444,89 @@ void *regmap_get_range(struct regmap *map, unsigned int range_num); */ int regmap_uninit(struct regmap *map); +/** + * struct reg_field - Description of an register field + * + * @reg: Offset of the register within the regmap bank + * @lsb: lsb of the register field. + * @msb: msb of the register field. + */ +struct reg_field { + unsigned int reg; + unsigned int lsb; + unsigned int msb; +}; + +struct regmap_field; + +/** + * REG_FIELD() - A convenient way to initialize a 'struct reg_feild'. + * + * @_reg: Offset of the register within the regmap bank + * @_lsb: lsb of the register field. + * @_msb: msb of the register field. + * + * Register fields are often described in terms of 3 things: the register it + * belongs to, its LSB, and its MSB. This macro can be used by drivers to + * clearly and easily initialize a 'struct regmap_field'. + * + * For example, say a device has a register at offset DEV_REG1 (0x100) and a + * field of DEV_REG1 is on bits [7:3]. So a driver can initialize a regmap + * field for this by doing: + * struct reg_field field = REG_FIELD(DEV_REG1, 3, 7); + */ +#define REG_FIELD(_reg, _lsb, _msb) { \ + .reg = _reg, \ + .lsb = _lsb, \ + .msb = _msb, \ + } + +/** + * devm_regmap_field_alloc() - Allocate and initialise a register field. + * + * @dev: Device that will be interacted with + * @regmap: regmap bank in which this register field is located. + * @reg_field: Register field with in the bank. + * + * The return value will be an ERR_PTR() on error or a valid pointer + * to a struct regmap_field. The regmap_field will be automatically freed + * by the device management code. + */ +struct regmap_field *devm_regmap_field_alloc(struct udevice *dev, + struct regmap *regmap, + struct reg_field reg_field); +/** + * devm_regmap_field_free() - Free a register field allocated using + * devm_regmap_field_alloc. + * + * @dev: Device that will be interacted with + * @field: regmap field which should be freed. + * + * Free register field allocated using devm_regmap_field_alloc(). Usually + * drivers need not call this function, as the memory allocated via devm + * will be freed as per device-driver life-cyle. + */ +void devm_regmap_field_free(struct udevice *dev, struct regmap_field *field); + +/** + * regmap_field_write() - Write a value to a regmap field + * + * @field: Regmap field to write to + * @val: Data to write to the regmap at the specified offset + * + * Return: 0 if OK, -ve on error + */ +int regmap_field_write(struct regmap_field *field, unsigned int val); + +/** + * regmap_read() - Read a 32-bit value from a regmap + * + * @field: Regmap field to write to + * @valp: Pointer to the buffer to receive the data read from the regmap + * field + * + * Return: 0 if OK, -ve on error + */ +int regmap_field_read(struct regmap_field *field, unsigned int *val); + #endif -- cgit v1.3.1 From 358599efd827b0ee48af864537cc86facc9167c0 Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 9 Sep 2020 18:44:00 +0200 Subject: firmware: add SCMI agent uclass This change introduces SCMI agent uclass to interact with a firmware using the SCMI protocols [1]. SCMI agent uclass currently supports a single method to request processing of the SCMI message by an identified server. A SCMI message is made of a byte payload associated to a protocol ID and a message ID, all defined by the SCMI specification [1]. On return from process_msg() method, the caller gets the service response. SCMI agent uclass defines a post bind generic sequence for all devices. The sequence binds all the SCMI protocols listed in the FDT for that SCMI agent device. Currently none, but later change will introduce protocols. This change implements a simple sandbox device for the SCMI agent uclass. The sandbox nicely answers SCMI_NOT_SUPPORTED to SCMI messages. To prepare for further test support, the sandbox exposes a architecture function for test application to read the sandbox emulated devices state. Currently supports 2 SCMI agents, identified by an ID in the FDT device name. The simplistic DM test does nothing yet. SCMI agent uclass is designed for platforms that embed a SCMI server in a firmware hosted somewhere, for example in a companion co-processor or in the secure world of the executing processor. SCMI protocols allow an SCMI agent to discover and access external resources as clock, reset controllers and more. SCMI agent and server communicate following the SCMI specification [1]. This SCMI agent implementation complies with the DT bindings defined in the Linux kernel source tree regarding SCMI agent description since v5.8. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere Cc: Simon Glass Cc: Peng Fan Cc: Sudeep Holla Reviewed-by: Simon Glass --- arch/sandbox/dts/test.dts | 16 ++++ arch/sandbox/include/asm/scmi_test.h | 43 +++++++++ configs/sandbox_defconfig | 2 + drivers/firmware/Kconfig | 2 + drivers/firmware/Makefile | 1 + drivers/firmware/scmi/Kconfig | 17 ++++ drivers/firmware/scmi/Makefile | 2 + drivers/firmware/scmi/sandbox-scmi_agent.c | 142 +++++++++++++++++++++++++++++ drivers/firmware/scmi/scmi_agent-uclass.c | 107 ++++++++++++++++++++++ include/dm/uclass-id.h | 1 + include/scmi_agent-uclass.h | 24 +++++ include/scmi_agent.h | 68 ++++++++++++++ include/scmi_protocols.h | 41 +++++++++ test/dm/Makefile | 1 + test/dm/scmi.c | 38 ++++++++ 15 files changed, 505 insertions(+) create mode 100644 arch/sandbox/include/asm/scmi_test.h create mode 100644 drivers/firmware/scmi/Kconfig create mode 100644 drivers/firmware/scmi/Makefile create mode 100644 drivers/firmware/scmi/sandbox-scmi_agent.c create mode 100644 drivers/firmware/scmi/scmi_agent-uclass.c create mode 100644 include/scmi_agent-uclass.h create mode 100644 include/scmi_agent.h create mode 100644 include/scmi_protocols.h create mode 100644 test/dm/scmi.c (limited to 'include') diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 2523e597237..4769ec08669 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -366,6 +366,22 @@ sandbox_firmware: sandbox-firmware { compatible = "sandbox,firmware"; }; + + sandbox-scmi-agent@0 { + compatible = "sandbox,scmi-agent"; + #address-cells = <1>; + #size-cells = <0>; + }; + + sandbox-scmi-agent@1 { + compatible = "sandbox,scmi-agent"; + #address-cells = <1>; + #size-cells = <0>; + + protocol@10 { + reg = <0x10>; + }; + }; }; pinctrl-gpio { diff --git a/arch/sandbox/include/asm/scmi_test.h b/arch/sandbox/include/asm/scmi_test.h new file mode 100644 index 00000000000..a811fe19c35 --- /dev/null +++ b/arch/sandbox/include/asm/scmi_test.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020, Linaro Limited + */ + +#ifndef __SANDBOX_SCMI_TEST_H +#define __SANDBOX_SCMI_TEST_H + +struct udevice; +struct sandbox_scmi_agent; +struct sandbox_scmi_service; + +/** + * struct sandbox_scmi_agent - Simulated SCMI service seen by SCMI agent + * @idx: Identifier for the SCMI agent, its index + */ +struct sandbox_scmi_agent { + uint idx; +}; + +/** + * struct sandbox_scmi_service - Reference to simutaed SCMI agents/services + * @agent: Pointer to SCMI sandbox agent pointers array + * @agent_count: Number of emulated agents exposed in array @agent. + */ +struct sandbox_scmi_service { + struct sandbox_scmi_agent **agent; + size_t agent_count; +}; + +#ifdef CONFIG_SCMI_FIRMWARE +/** + * sandbox_scmi_service_context - Get the simulated SCMI services context + * @return: Reference to backend simulated resources state + */ +struct sandbox_scmi_service *sandbox_scmi_service_ctx(void); +#else +static inline struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) +{ + return NULL; +} +#endif /* CONFIG_SCMI_FIRMWARE */ +#endif /* __SANDBOX_SCMI_TEST_H */ diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 6e9f029cc96..2c130c01f07 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -132,6 +132,8 @@ CONFIG_BOARD_SANDBOX=y CONFIG_DMA=y CONFIG_DMA_CHANNELS=y CONFIG_SANDBOX_DMA=y +CONFIG_FIRMWARE=y +CONFIG_SCMI_FIRMWARE=y CONFIG_GPIO_HOG=y CONFIG_DM_GPIO_LOOKUP_LABEL=y CONFIG_PM8916_GPIO=y diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index b70a2063551..ef958b3a7a4 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -36,3 +36,5 @@ config ZYNQMP_FIRMWARE various platform management services. Say yes to enable ZynqMP firmware interface driver. If in doubt, say N. + +source "drivers/firmware/scmi/Kconfig" diff --git a/drivers/firmware/Makefile b/drivers/firmware/Makefile index a0c250a473e..7ce83d72bd3 100644 --- a/drivers/firmware/Makefile +++ b/drivers/firmware/Makefile @@ -3,3 +3,4 @@ obj-$(CONFIG_$(SPL_)ARM_PSCI_FW) += psci.o obj-$(CONFIG_TI_SCI_PROTOCOL) += ti_sci.o obj-$(CONFIG_SANDBOX) += firmware-sandbox.o obj-$(CONFIG_ZYNQMP_FIRMWARE) += firmware-zynqmp.o +obj-$(CONFIG_SCMI_FIRMWARE) += scmi/ diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig new file mode 100644 index 00000000000..57e2ebbe428 --- /dev/null +++ b/drivers/firmware/scmi/Kconfig @@ -0,0 +1,17 @@ +config SCMI_FIRMWARE + bool "Enable SCMI support" + select FIRMWARE + select OF_TRANSLATE + depends on SANDBOX + help + System Control and Management Interface (SCMI) is a communication + protocol that defines standard interfaces for power, performance + and system management. The SCMI specification is available at + https://developer.arm.com/architectures/system-architectures/software-standards/scmi + + An SCMI agent communicates with a related SCMI server firmware + located in another sub-system, as a companion micro controller + or a companion host in the CPU system. + + Communications between agent (client) and the SCMI server are + based on message exchange. diff --git a/drivers/firmware/scmi/Makefile b/drivers/firmware/scmi/Makefile new file mode 100644 index 00000000000..336ea1f2a32 --- /dev/null +++ b/drivers/firmware/scmi/Makefile @@ -0,0 +1,2 @@ +obj-y += scmi_agent-uclass.o +obj-$(CONFIG_SANDBOX) += sandbox-scmi_agent.o diff --git a/drivers/firmware/scmi/sandbox-scmi_agent.c b/drivers/firmware/scmi/sandbox-scmi_agent.c new file mode 100644 index 00000000000..3179438aabf --- /dev/null +++ b/drivers/firmware/scmi/sandbox-scmi_agent.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * The sandbox SCMI agent driver simulates to some extend a SCMI message + * processing. It simulates few of the SCMI services for some of the + * SCMI protocols embedded in U-Boot. Currently none. + * + * This driver simulates 2 SCMI agents for test purpose. + * + * This Driver exports sandbox_scmi_service_ct() for the test sequence to + * get the state of the simulated services (clock state, rate, ...) and + * check back-end device state reflects the request send through the + * various uclass devices, currently nothing. + */ + +#define SANDBOX_SCMI_AGENT_COUNT 2 + +/* The list saves to simulted end devices references for test purpose */ +struct sandbox_scmi_agent *sandbox_scmi_agent_list[SANDBOX_SCMI_AGENT_COUNT]; + +static struct sandbox_scmi_service sandbox_scmi_service_state = { + .agent = sandbox_scmi_agent_list, + .agent_count = SANDBOX_SCMI_AGENT_COUNT, +}; + +struct sandbox_scmi_service *sandbox_scmi_service_ctx(void) +{ + return &sandbox_scmi_service_state; +} + +static void debug_print_agent_state(struct udevice *dev, char *str) +{ + struct sandbox_scmi_agent *agent = dev_get_priv(dev); + + dev_dbg(dev, "Dump sandbox_scmi_agent %u: %s\n", agent->idx, str); +}; + +static int sandbox_scmi_test_process_msg(struct udevice *dev, + struct scmi_msg *msg) +{ + switch (msg->protocol_id) { + case SCMI_PROTOCOL_ID_BASE: + case SCMI_PROTOCOL_ID_POWER_DOMAIN: + case SCMI_PROTOCOL_ID_SYSTEM: + case SCMI_PROTOCOL_ID_PERF: + case SCMI_PROTOCOL_ID_CLOCK: + case SCMI_PROTOCOL_ID_SENSOR: + case SCMI_PROTOCOL_ID_RESET_DOMAIN: + *(u32 *)msg->out_msg = SCMI_NOT_SUPPORTED; + return 0; + default: + break; + } + + dev_err(dev, "%s(%s): Unhandled protocol_id %#x/message_id %#x\n", + __func__, dev->name, msg->protocol_id, msg->message_id); + + if (msg->out_msg_sz < sizeof(u32)) + return -EINVAL; + + /* Intentionnaly report unhandled IDs through the SCMI return code */ + *(u32 *)msg->out_msg = SCMI_PROTOCOL_ERROR; + return 0; +} + +static int sandbox_scmi_test_remove(struct udevice *dev) +{ + struct sandbox_scmi_agent *agent = dev_get_priv(dev); + + debug_print_agent_state(dev, "removed"); + + /* We only need to dereference the agent in the context */ + sandbox_scmi_service_ctx()->agent[agent->idx] = NULL; + + return 0; +} + +static int sandbox_scmi_test_probe(struct udevice *dev) +{ + static const char basename[] = "sandbox-scmi-agent@"; + struct sandbox_scmi_agent *agent = dev_get_priv(dev); + const size_t basename_size = sizeof(basename) - 1; + + if (strncmp(basename, dev->name, basename_size)) + return -ENOENT; + + switch (dev->name[basename_size]) { + case '0': + *agent = (struct sandbox_scmi_agent){ + .idx = 0, + }; + break; + case '1': + *agent = (struct sandbox_scmi_agent){ + .idx = 1, + }; + break; + default: + dev_err(dev, "%s(): Unexpected agent ID %s\n", + __func__, dev->name + basename_size); + return -ENOENT; + } + + debug_print_agent_state(dev, "probed"); + + /* Save reference for tests purpose */ + sandbox_scmi_service_ctx()->agent[agent->idx] = agent; + + return 0; +}; + +static const struct udevice_id sandbox_scmi_test_ids[] = { + { .compatible = "sandbox,scmi-agent" }, + { } +}; + +struct scmi_agent_ops sandbox_scmi_test_ops = { + .process_msg = sandbox_scmi_test_process_msg, +}; + +U_BOOT_DRIVER(sandbox_scmi_agent) = { + .name = "sandbox-scmi_agent", + .id = UCLASS_SCMI_AGENT, + .of_match = sandbox_scmi_test_ids, + .priv_auto_alloc_size = sizeof(struct sandbox_scmi_agent), + .probe = sandbox_scmi_test_probe, + .remove = sandbox_scmi_test_remove, + .ops = &sandbox_scmi_test_ops, +}; diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c new file mode 100644 index 00000000000..67a6f907c99 --- /dev/null +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -0,0 +1,107 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Linaro Limited. + */ + +#include +#include +#include +#include +#include + +#include +#include + +/** + * struct error_code - Helper structure for SCMI error code conversion + * @scmi: SCMI error code + * @errno: Related standard error number + */ +struct error_code { + int scmi; + int errno; +}; + +static const struct error_code scmi_linux_errmap[] = { + { .scmi = SCMI_NOT_SUPPORTED, .errno = -EOPNOTSUPP, }, + { .scmi = SCMI_INVALID_PARAMETERS, .errno = -EINVAL, }, + { .scmi = SCMI_DENIED, .errno = -EACCES, }, + { .scmi = SCMI_NOT_FOUND, .errno = -ENOENT, }, + { .scmi = SCMI_OUT_OF_RANGE, .errno = -ERANGE, }, + { .scmi = SCMI_BUSY, .errno = -EBUSY, }, + { .scmi = SCMI_COMMS_ERROR, .errno = -ECOMM, }, + { .scmi = SCMI_GENERIC_ERROR, .errno = -EIO, }, + { .scmi = SCMI_HARDWARE_ERROR, .errno = -EREMOTEIO, }, + { .scmi = SCMI_PROTOCOL_ERROR, .errno = -EPROTO, }, +}; + +int scmi_to_linux_errno(s32 scmi_code) +{ + int n; + + if (!scmi_code) + return 0; + + for (n = 0; n < ARRAY_SIZE(scmi_linux_errmap); n++) + if (scmi_code == scmi_linux_errmap[n].scmi) + return scmi_linux_errmap[1].errno; + + return -EPROTO; +} + +/* + * SCMI agent devices binds devices of various uclasses depeding on + * the FDT description. scmi_bind_protocol() is a generic bind sequence + * called by the uclass at bind stage, that is uclass post_bind. + */ +static int scmi_bind_protocols(struct udevice *dev) +{ + int ret = 0; + ofnode node; + struct driver *drv; + + dev_for_each_subnode(node, dev) { + u32 protocol_id; + + if (!ofnode_is_available(node)) + continue; + + if (ofnode_read_u32(node, "reg", &protocol_id)) + continue; + + switch (protocol_id) { + default: + dev_info(dev, "Ignore unsupported SCMI protocol %#x\n", + protocol_id); + continue; + } + + ret = device_bind_ofnode(dev, drv, ofnode_get_name(node), + NULL, node, NULL); + if (ret) + break; + } + + return ret; +} + +static const struct scmi_agent_ops *transport_dev_ops(struct udevice *dev) +{ + return (const struct scmi_agent_ops *)dev->driver->ops; +} + +int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg) +{ + const struct scmi_agent_ops *ops = transport_dev_ops(dev); + + if (ops->process_msg) + return ops->process_msg(dev, msg); + + return -EPROTONOSUPPORT; +} + +UCLASS_DRIVER(scmi_agent) = { + .id = UCLASS_SCMI_AGENT, + .name = "scmi_agent", + .post_bind = scmi_bind_protocols, +}; diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h index 4ec5fa6670a..88f10c46221 100644 --- a/include/dm/uclass-id.h +++ b/include/dm/uclass-id.h @@ -94,6 +94,7 @@ enum uclass_id { UCLASS_RESET, /* Reset controller device */ UCLASS_RNG, /* Random Number Generator */ UCLASS_RTC, /* Real time clock device */ + UCLASS_SCMI_AGENT, /* Interface with an SCMI server */ UCLASS_SCSI, /* SCSI device */ UCLASS_SERIAL, /* Serial UART */ UCLASS_SIMPLE_BUS, /* Bus with child devices */ diff --git a/include/scmi_agent-uclass.h b/include/scmi_agent-uclass.h new file mode 100644 index 00000000000..a501d1b4825 --- /dev/null +++ b/include/scmi_agent-uclass.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019-2020 Linaro Limited. + */ +#ifndef _SCMI_AGENT_UCLASS_H +#define _SCMI_AGENT_UCLASS_H + +struct udevice; +struct scmi_msg; + +/** + * struct scmi_transport_ops - The functions that a SCMI transport layer must implement. + */ +struct scmi_agent_ops { + /* + * process_msg - Request transport to get the SCMI message processed + * + * @agent: Agent using the transport + * @msg: SCMI message to be transmitted + */ + int (*process_msg)(struct udevice *dev, struct scmi_msg *msg); +}; + +#endif /* _SCMI_TRANSPORT_UCLASS_H */ diff --git a/include/scmi_agent.h b/include/scmi_agent.h new file mode 100644 index 00000000000..f1be9ff2091 --- /dev/null +++ b/include/scmi_agent.h @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (C) 2019-2020, Linaro Limited + * + * An SCMI agent device represent on communication path from a + * device driver to the remote SCMI server which driver sends + * messages to and receives response messages from. + */ +#ifndef SCMI_AGENT_H +#define SCMI_AGENT_H + +#include + +struct udevice; + +/* + * struct scmi_msg - Context of a SCMI message sent and the response received + * + * @protocol_id: SCMI protocol ID + * @message_id: SCMI message ID for a defined protocol ID + * @in_msg: Pointer to the message payload sent by the driver + * @in_msg_sz: Byte size of the message payload sent + * @out_msg: Pointer to buffer to store response message payload + * @out_msg_sz: Byte size of the response buffer and response payload + */ +struct scmi_msg { + unsigned int protocol_id; + unsigned int message_id; + u8 *in_msg; + size_t in_msg_sz; + u8 *out_msg; + size_t out_msg_sz; +}; + +/* Helper macro to match a message on input/output array references */ +#define SCMI_MSG_IN(_protocol, _message, _in_array, _out_array) \ + (struct scmi_msg){ \ + .protocol_id = (_protocol), \ + .message_id = (_message), \ + .in_msg = (uint8_t *)&(_in_array), \ + .in_msg_sz = sizeof(_in_array), \ + .out_msg = (uint8_t *)&(_out_array), \ + .out_msg_sz = sizeof(_out_array), \ + } + +/** + * scmi_send_and_process_msg() - send and process a SCMI message + * + * Send a message to a SCMI server through a target SCMI agent device. + * Caller sets scmi_msg::out_msg_sz to the output message buffer size. + * On return, scmi_msg::out_msg_sz stores the response payload size. + * + * @dev: SCMI agent device + * @msg: Message structure reference + * @return 0 on success and a negative errno on failure + */ +int devm_scmi_process_msg(struct udevice *dev, struct scmi_msg *msg); + +/** + * scmi_to_linux_errno() - Convert an SCMI error code into a Linux errno code + * + * @scmi_errno: SCMI error code value + * @return 0 for successful status and a negative errno otherwise + */ +int scmi_to_linux_errno(s32 scmi_errno); + +#endif /* SCMI_H */ diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h new file mode 100644 index 00000000000..86a2d109c8c --- /dev/null +++ b/include/scmi_protocols.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (c) 2015-2019, Arm Limited and Contributors. All rights reserved. + * Copyright (C) 2019-2020, Linaro Limited + */ +#ifndef _SCMI_PROTOCOLS_H +#define _SCMI_PROTOCOLS_H + +#include + +/* + * Subset the SCMI protocols definition + * based on SCMI specification v2.0 (DEN0056B) + * https://developer.arm.com/docs/den0056/b + */ + +enum scmi_std_protocol { + SCMI_PROTOCOL_ID_BASE = 0x10, + SCMI_PROTOCOL_ID_POWER_DOMAIN = 0x11, + SCMI_PROTOCOL_ID_SYSTEM = 0x12, + SCMI_PROTOCOL_ID_PERF = 0x13, + SCMI_PROTOCOL_ID_CLOCK = 0x14, + SCMI_PROTOCOL_ID_SENSOR = 0x15, + SCMI_PROTOCOL_ID_RESET_DOMAIN = 0x16, +}; + +enum scmi_status_code { + SCMI_SUCCESS = 0, + SCMI_NOT_SUPPORTED = -1, + SCMI_INVALID_PARAMETERS = -2, + SCMI_DENIED = -3, + SCMI_NOT_FOUND = -4, + SCMI_OUT_OF_RANGE = -5, + SCMI_BUSY = -6, + SCMI_COMMS_ERROR = -7, + SCMI_GENERIC_ERROR = -8, + SCMI_HARDWARE_ERROR = -9, + SCMI_PROTOCOL_ERROR = -10, +}; + +#endif /* _SCMI_PROTOCOLS_H */ diff --git a/test/dm/Makefile b/test/dm/Makefile index 864c8d0b4ce..70ba1b66953 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -80,4 +80,5 @@ obj-$(CONFIG_DM_RNG) += rng.o obj-$(CONFIG_CLK_K210_SET_RATE) += k210_pll.o obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o obj-$(CONFIG_RESET_SYSCON) += syscon-reset.o +obj-$(CONFIG_SCMI_FIRMWARE) += scmi.o endif diff --git a/test/dm/scmi.c b/test/dm/scmi.c new file mode 100644 index 00000000000..d8c1e71f127 --- /dev/null +++ b/test/dm/scmi.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020, Linaro Limited + * + * Tests scmi_agent uclass and the SCMI drivers implemented in other + * uclass devices probe when a SCMI server exposes resources. + * + * Note in test.dts the protocol@10 node in agent 1. Protocol 0x10 is not + * implemented in U-Boot SCMI components but the implementation is exepected + * to not complain on unknown protocol IDs, as long as it is not used. Note + * in test.dts tests that SCMI drivers probing does not fail for such an + * unknown SCMI protocol ID. + */ + +#include +#include +#include +#include +#include +#include + +/* + * Test SCMI states when loading and releasing resources + * related to SCMI drivers. + */ +static int dm_test_scmi_sandbox_agent(struct unit_test_state *uts) +{ + struct sandbox_scmi_service *scmi_ctx = sandbox_scmi_service_ctx(); + + ut_assertnonnull(scmi_ctx); + ut_asserteq(2, scmi_ctx->agent_count); + ut_assertnull(scmi_ctx->agent[0]); + ut_assertnull(scmi_ctx->agent[1]); + + return 0; +} + +DM_TEST(dm_test_scmi_sandbox_agent, UT_TESTF_SCAN_FDT); -- cgit v1.3.1 From 60388844836f5639e6c9a4331335ff22298128da Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 9 Sep 2020 18:44:04 +0200 Subject: clk: add clock driver for SCMI agents This change introduces a clock driver for SCMI agent devices. When SCMI agent and SCMI clock drivers are enabled, SCMI agent binds a clock device for each SCMI clock protocol devices enabled in the FDT. SCMI clock driver is embedded upon CONFIG_CLK_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Clock protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere Cc: Lukasz Majewski Cc: Simon Glass Cc: Peng Fan Cc: Sudeep Holla Reviewed-by: Simon Glass --- drivers/clk/Kconfig | 8 +++ drivers/clk/Makefile | 1 + drivers/clk/clk_scmi.c | 99 +++++++++++++++++++++++++++++++ drivers/firmware/scmi/scmi_agent-uclass.c | 14 ++++- include/scmi_protocols.h | 78 ++++++++++++++++++++++++ 5 files changed, 197 insertions(+), 3 deletions(-) create mode 100644 drivers/clk/clk_scmi.c (limited to 'include') diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 6003e140b58..4dfbad7986b 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -159,6 +159,14 @@ config CLK_CDCE9XX Enable the clock synthesizer driver for CDCE913/925/937/949 series of chips. +config CLK_SCMI + bool "Enable SCMI clock driver" + depends on SCMI_FIRMWARE + help + Enable this option if you want to support clock devices exposed + by a SCMI agent based on SCMI clock protocol communication + with a SCMI server. + source "drivers/clk/analogbits/Kconfig" source "drivers/clk/at91/Kconfig" source "drivers/clk/exynos/Kconfig" diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index cda4b4b605f..d1e295ac7c1 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o obj-$(CONFIG_CLK_OWL) += owl/ obj-$(CONFIG_CLK_RENESAS) += renesas/ +obj-$(CONFIG_CLK_SCMI) += clk_scmi.o obj-$(CONFIG_CLK_SIFIVE) += sifive/ obj-$(CONFIG_ARCH_SUNXI) += sunxi/ obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o diff --git a/drivers/clk/clk_scmi.c b/drivers/clk/clk_scmi.c new file mode 100644 index 00000000000..93a4819501c --- /dev/null +++ b/drivers/clk/clk_scmi.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2020 Linaro Limited + */ +#include +#include +#include +#include +#include +#include + +static int scmi_clk_gate(struct clk *clk, int enable) +{ + struct scmi_clk_state_in in = { + .clock_id = clk->id, + .attributes = enable, + }; + struct scmi_clk_state_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_CONFIG_SET, + in, out); + int ret; + + ret = devm_scmi_process_msg(clk->dev->parent, &msg); + if (ret) + return ret; + + return scmi_to_linux_errno(out.status); +} + +static int scmi_clk_enable(struct clk *clk) +{ + return scmi_clk_gate(clk, 1); +} + +static int scmi_clk_disable(struct clk *clk) +{ + return scmi_clk_gate(clk, 0); +} + +static ulong scmi_clk_get_rate(struct clk *clk) +{ + struct scmi_clk_rate_get_in in = { + .clock_id = clk->id, + }; + struct scmi_clk_rate_get_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_RATE_GET, + in, out); + int ret; + + ret = devm_scmi_process_msg(clk->dev->parent, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + return (ulong)(((u64)out.rate_msb << 32) | out.rate_lsb); +} + +static ulong scmi_clk_set_rate(struct clk *clk, ulong rate) +{ + struct scmi_clk_rate_set_in in = { + .clock_id = clk->id, + .flags = SCMI_CLK_RATE_ROUND_CLOSEST, + .rate_lsb = (u32)rate, + .rate_msb = (u32)((u64)rate >> 32), + }; + struct scmi_clk_rate_set_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_CLOCK, + SCMI_CLOCK_RATE_SET, + in, out); + int ret; + + ret = devm_scmi_process_msg(clk->dev->parent, &msg); + if (ret < 0) + return ret; + + ret = scmi_to_linux_errno(out.status); + if (ret < 0) + return ret; + + return scmi_clk_get_rate(clk); +} + +static const struct clk_ops scmi_clk_ops = { + .enable = scmi_clk_enable, + .disable = scmi_clk_disable, + .get_rate = scmi_clk_get_rate, + .set_rate = scmi_clk_set_rate, +}; + +U_BOOT_DRIVER(scmi_clock) = { + .name = "scmi_clk", + .id = UCLASS_CLK, + .ops = &scmi_clk_ops, +}; diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 67a6f907c99..1f36f23b6d8 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -58,9 +58,9 @@ static int scmi_bind_protocols(struct udevice *dev) { int ret = 0; ofnode node; - struct driver *drv; dev_for_each_subnode(node, dev) { + struct driver *drv = NULL; u32 protocol_id; if (!ofnode_is_available(node)) @@ -70,9 +70,17 @@ static int scmi_bind_protocols(struct udevice *dev) continue; switch (protocol_id) { + case SCMI_PROTOCOL_ID_CLOCK: + if (IS_ENABLED(CONFIG_CLK_SCMI)) + drv = DM_GET_DRIVER(scmi_clock); + break; default: - dev_info(dev, "Ignore unsupported SCMI protocol %#x\n", - protocol_id); + break; + } + + if (!drv) { + dev_dbg(dev, "Ignore unsupported SCMI protocol %#x\n", + protocol_id); continue; } diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 86a2d109c8c..4778bcfc474 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -7,6 +7,7 @@ #define _SCMI_PROTOCOLS_H #include +#include /* * Subset the SCMI protocols definition @@ -38,4 +39,81 @@ enum scmi_status_code { SCMI_PROTOCOL_ERROR = -10, }; +/* + * SCMI Clock Protocol + */ + +enum scmi_clock_message_id { + SCMI_CLOCK_RATE_SET = 0x5, + SCMI_CLOCK_RATE_GET = 0x6, + SCMI_CLOCK_CONFIG_SET = 0x7, +}; + +#define SCMI_CLK_RATE_ASYNC_NOTIFY BIT(0) +#define SCMI_CLK_RATE_ASYNC_NORESP (BIT(0) | BIT(1)) +#define SCMI_CLK_RATE_ROUND_DOWN 0 +#define SCMI_CLK_RATE_ROUND_UP BIT(2) +#define SCMI_CLK_RATE_ROUND_CLOSEST BIT(3) + +/** + * struct scmi_clk_state_in - Message payload for CLOCK_CONFIG_SET command + * @clock_id: SCMI clock ID + * @attributes: Attributes of the targets clock state + */ +struct scmi_clk_state_in { + u32 clock_id; + u32 attributes; +}; + +/** + * struct scmi_clk_state_out - Response payload for CLOCK_CONFIG_SET command + * @status: SCMI command status + */ +struct scmi_clk_state_out { + s32 status; +}; + +/** + * struct scmi_clk_state_in - Message payload for CLOCK_RATE_GET command + * @clock_id: SCMI clock ID + * @attributes: Attributes of the targets clock state + */ +struct scmi_clk_rate_get_in { + u32 clock_id; +}; + +/** + * struct scmi_clk_rate_get_out - Response payload for CLOCK_RATE_GET command + * @status: SCMI command status + * @rate_lsb: 32bit LSB of the clock rate in Hertz + * @rate_msb: 32bit MSB of the clock rate in Hertz + */ +struct scmi_clk_rate_get_out { + s32 status; + u32 rate_lsb; + u32 rate_msb; +}; + +/** + * struct scmi_clk_state_in - Message payload for CLOCK_RATE_SET command + * @clock_id: SCMI clock ID + * @flags: Flags for the clock rate set request + * @rate_lsb: 32bit LSB of the clock rate in Hertz + * @rate_msb: 32bit MSB of the clock rate in Hertz + */ +struct scmi_clk_rate_set_in { + u32 clock_id; + u32 flags; + u32 rate_lsb; + u32 rate_msb; +}; + +/** + * struct scmi_clk_rate_set_out - Response payload for CLOCK_RATE_SET command + * @status: SCMI command status + */ +struct scmi_clk_rate_set_out { + s32 status; +}; + #endif /* _SCMI_PROTOCOLS_H */ -- cgit v1.3.1 From 34d76fefb2667d0ca138ff4fcf8bc8443032449f Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Wed, 9 Sep 2020 18:44:06 +0200 Subject: reset: add reset controller driver for SCMI agents This change introduces a reset controller driver for SCMI agent devices. When SCMI agent and SCMI reset domain drivers are enabled, SCMI agent binds a reset controller device for each SCMI reset domain protocol devices enabled in the FDT. SCMI reset driver is embedded upon CONFIG_RESET_SCMI=y. If enabled, CONFIG_SCMI_AGENT is also enabled. SCMI Reset Domain protocol is defined in the SCMI specification [1]. Links: [1] https://developer.arm.com/architectures/system-architectures/software-standards/scmi Signed-off-by: Etienne Carriere Cc: Simon Glass Cc: Peng Fan Cc: Sudeep Holla Reviewed-by: Simon Glass --- drivers/firmware/scmi/scmi_agent-uclass.c | 4 ++ drivers/reset/Kconfig | 8 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-scmi.c | 81 +++++++++++++++++++++++++++++++ include/scmi_protocols.h | 60 +++++++++++++++++++++++ 5 files changed, 154 insertions(+) create mode 100644 drivers/reset/reset-scmi.c (limited to 'include') diff --git a/drivers/firmware/scmi/scmi_agent-uclass.c b/drivers/firmware/scmi/scmi_agent-uclass.c index 1f36f23b6d8..77160b19995 100644 --- a/drivers/firmware/scmi/scmi_agent-uclass.c +++ b/drivers/firmware/scmi/scmi_agent-uclass.c @@ -74,6 +74,10 @@ static int scmi_bind_protocols(struct udevice *dev) if (IS_ENABLED(CONFIG_CLK_SCMI)) drv = DM_GET_DRIVER(scmi_clock); break; + case SCMI_PROTOCOL_ID_RESET_DOMAIN: + if (IS_ENABLED(CONFIG_RESET_SCMI)) + drv = DM_GET_DRIVER(scmi_reset_domain); + break; default: break; } diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 3fdfe4a6cb0..b60e11f98b2 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -181,4 +181,12 @@ config RESET_RASPBERRYPI relevant. This driver provides a reset controller capable of interfacing with RPi4's co-processor and model these firmware initialization routines as reset lines. + +config RESET_SCMI + bool "Enable SCMI reset domain driver" + select SCMI_FIRMWARE + help + Enable this option if you want to support reset controller + devices exposed by a SCMI agent based on SCMI reset domain + protocol communication with a SCMI server. endmenu diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 5176da58853..10a7973f823 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -27,3 +27,4 @@ obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o +obj-$(CONFIG_RESET_SCMI) += reset-scmi.o diff --git a/drivers/reset/reset-scmi.c b/drivers/reset/reset-scmi.c new file mode 100644 index 00000000000..1bff8075ee3 --- /dev/null +++ b/drivers/reset/reset-scmi.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019-2020 Linaro Limited + */ +#include +#include +#include +#include +#include +#include +#include + +static int scmi_reset_set_level(struct reset_ctl *rst, bool assert_not_deassert) +{ + struct scmi_rd_reset_in in = { + .domain_id = rst->id, + .flags = assert_not_deassert ? SCMI_RD_RESET_FLAG_ASSERT : 0, + .reset_state = 0, + }; + struct scmi_rd_reset_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN, + SCMI_RESET_DOMAIN_RESET, + in, out); + int ret; + + ret = devm_scmi_process_msg(rst->dev->parent, &msg); + if (ret) + return ret; + + return scmi_to_linux_errno(out.status); +} + +static int scmi_reset_assert(struct reset_ctl *rst) +{ + return scmi_reset_set_level(rst, true); +} + +static int scmi_reset_deassert(struct reset_ctl *rst) +{ + return scmi_reset_set_level(rst, false); +} + +static int scmi_reset_request(struct reset_ctl *rst) +{ + struct scmi_rd_attr_in in = { + .domain_id = rst->id, + }; + struct scmi_rd_attr_out out; + struct scmi_msg msg = SCMI_MSG_IN(SCMI_PROTOCOL_ID_RESET_DOMAIN, + SCMI_RESET_DOMAIN_ATTRIBUTES, + in, out); + int ret; + + /* + * We don't really care about the attribute, just check + * the reset domain exists. + */ + ret = devm_scmi_process_msg(rst->dev->parent, &msg); + if (ret) + return ret; + + return scmi_to_linux_errno(out.status); +} + +static int scmi_reset_rfree(struct reset_ctl *rst) +{ + return 0; +} + +static const struct reset_ops scmi_reset_domain_ops = { + .request = scmi_reset_request, + .rfree = scmi_reset_rfree, + .rst_assert = scmi_reset_assert, + .rst_deassert = scmi_reset_deassert, +}; + +U_BOOT_DRIVER(scmi_reset_domain) = { + .name = "scmi_reset_domain", + .id = UCLASS_RESET, + .ops = &scmi_reset_domain_ops, +}; diff --git a/include/scmi_protocols.h b/include/scmi_protocols.h index 4778bcfc474..ccab97c96c9 100644 --- a/include/scmi_protocols.h +++ b/include/scmi_protocols.h @@ -116,4 +116,64 @@ struct scmi_clk_rate_set_out { s32 status; }; +/* + * SCMI Reset Domain Protocol + */ + +enum scmi_reset_domain_message_id { + SCMI_RESET_DOMAIN_ATTRIBUTES = 0x3, + SCMI_RESET_DOMAIN_RESET = 0x4, +}; + +#define SCMI_RD_NAME_LEN 16 + +#define SCMI_RD_ATTRIBUTES_FLAG_ASYNC BIT(31) +#define SCMI_RD_ATTRIBUTES_FLAG_NOTIF BIT(30) + +#define SCMI_RD_RESET_FLAG_ASYNC BIT(2) +#define SCMI_RD_RESET_FLAG_ASSERT BIT(1) +#define SCMI_RD_RESET_FLAG_CYCLE BIT(0) + +/** + * struct scmi_rd_attr_in - Payload for RESET_DOMAIN_ATTRIBUTES message + * @domain_id: SCMI reset domain ID + */ +struct scmi_rd_attr_in { + u32 domain_id; +}; + +/** + * struct scmi_rd_attr_out - Payload for RESET_DOMAIN_ATTRIBUTES response + * @status: SCMI command status + * @attributes: Retrieved attributes of the reset domain + * @latency: Reset cycle max lantency + * @name: Reset domain name + */ +struct scmi_rd_attr_out { + s32 status; + u32 attributes; + u32 latency; + char name[SCMI_RD_NAME_LEN]; +}; + +/** + * struct scmi_rd_reset_in - Message payload for RESET command + * @domain_id: SCMI reset domain ID + * @flags: Flags for the reset request + * @reset_state: Reset target state + */ +struct scmi_rd_reset_in { + u32 domain_id; + u32 flags; + u32 reset_state; +}; + +/** + * struct scmi_rd_reset_out - Response payload for RESET command + * @status: SCMI command status + */ +struct scmi_rd_reset_out { + s32 status; +}; + #endif /* _SCMI_PROTOCOLS_H */ -- cgit v1.3.1 From b43ea1bf18bf4ba5eeec7131c1a19d864399e422 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 18 Sep 2020 14:13:00 +0200 Subject: net: add a generic udp protocol This commit adds a generic udp protocol framework in the network loop. So protocol based on udp may be implemented without modifying the network loop (for example custom wait magic packet). Signed-off-by: Philippe Reynes Reviewed-by: Simon Glass --- doc/README.udp | 35 +++++++++++++++++++++++++++++++++++ include/net.h | 2 +- include/net/udp.h | 41 +++++++++++++++++++++++++++++++++++++++++ net/Kconfig | 6 ++++++ net/Makefile | 1 + net/net.c | 13 ++++++++++++- net/udp.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 142 insertions(+), 2 deletions(-) create mode 100644 doc/README.udp create mode 100644 include/net/udp.h create mode 100644 net/udp.c (limited to 'include') diff --git a/doc/README.udp b/doc/README.udp new file mode 100644 index 00000000000..da0725719dc --- /dev/null +++ b/doc/README.udp @@ -0,0 +1,35 @@ +Udp framework + +The udp framework is build on top of network framework and is designed +to define new protocol or new command based on udp without modifying +the network framework. + +The udp framework define a function udp_loop that take as argument +a structure udp_ops (defined in include/net/udp.h) : + +struct udp_ops { + int (*prereq)(void *data); + int (*start)(void *data); + void *data; +}; + +The callback prereq define if all the requirements are +valid before running the network/udp loop. + +The callback start define the first step in the network/udp loop, +and it may also be used to configure a timemout and udp handler. + +The pointer data is used to store private data that +could be used by both callback. + +A simple example to use this framework: + +static struct udp_ops udp_ops = { + .prereq = wmp_prereq, + .start = wmp_start, + .data = NULL, +}; + +... + +err = udp_loop(&udp_ops); diff --git a/include/net.h b/include/net.h index 1bf9867f8cf..219107194f7 100644 --- a/include/net.h +++ b/include/net.h @@ -551,7 +551,7 @@ extern int net_restart_wrap; /* Tried all network devices */ enum proto_t { BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP, - TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL + TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, UDP }; extern char net_boot_file_name[1024];/* Boot File name */ diff --git a/include/net/udp.h b/include/net/udp.h new file mode 100644 index 00000000000..2ae56e84477 --- /dev/null +++ b/include/net/udp.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#ifndef __UDP +#define __UDP + +/** + * struct udp_ops - function to handle udp packet + * + * This structure provides the function to handle udp packet in + * the network loop. + * + * @prereq: callback called to check the requirement + * @start: callback called to start the protocol/feature + * @data: pointer to store private data (used by prereq and start) + */ +struct udp_ops { + int (*prereq)(void *data); + int (*start)(void *data); + void *data; +}; + +int udp_prereq(void); + +int udp_start(void); + +/** + * udp_loop() - network loop for udp protocol + * + * Launch a network loop for udp protocol and use callbacks + * provided in parameter @ops to initialize the loop, and then + * to handle udp packet. + * + * @ops: udp callback + * @return: 0 if success, otherwise < 0 on error + */ +int udp_loop(struct udp_ops *ops); + +#endif diff --git a/net/Kconfig b/net/Kconfig index 6874b55aacb..1b3e420d0d1 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -8,6 +8,12 @@ menuconfig NET if NET +config PROT_UDP + bool "Enable generic udp framework" + help + Enable a generic udp framework that allows defining a custom + handler for udp protocol. + config BOOTP_SEND_HOSTNAME bool "Send hostname to DNS server" help diff --git a/net/Makefile b/net/Makefile index fef71b940a0..76527f704c4 100644 --- a/net/Makefile +++ b/net/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_CMD_SNTP) += sntp.o obj-$(CONFIG_CMD_TFTPBOOT) += tftp.o obj-$(CONFIG_UDP_FUNCTION_FASTBOOT) += fastboot.o obj-$(CONFIG_CMD_WOL) += wol.o +obj-$(CONFIG_PROT_UDP) += udp.o # Disable this warning as it is triggered by: # sprintf(buf, index ? "foo%d" : "foo", index) diff --git a/net/net.c b/net/net.c index 28d9eebf9dd..1ce0eb57a75 100644 --- a/net/net.c +++ b/net/net.c @@ -102,6 +102,7 @@ #if defined(CONFIG_CMD_PCAP) #include #endif +#include #if defined(CONFIG_LED_STATUS) #include #include @@ -544,6 +545,9 @@ restart: break; } + if (IS_ENABLED(CONFIG_PROT_UDP) && protocol == UDP) + udp_start(); + break; } @@ -1364,6 +1368,13 @@ static int net_check_prereq(enum proto_t protocol) } goto common; #endif +#if defined(CONFIG_PROT_UDP) + case UDP: + if (udp_prereq()) + return 1; + goto common; +#endif + #if defined(CONFIG_CMD_NFS) case NFS: #endif @@ -1375,7 +1386,7 @@ static int net_check_prereq(enum proto_t protocol) return 1; } #if defined(CONFIG_CMD_PING) || defined(CONFIG_CMD_SNTP) || \ - defined(CONFIG_CMD_DNS) + defined(CONFIG_CMD_DNS) || defined(CONFIG_PROT_UDP) common: #endif /* Fall through */ diff --git a/net/udp.c b/net/udp.c new file mode 100644 index 00000000000..a93822f511c --- /dev/null +++ b/net/udp.c @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2020 Philippe Reynes + */ + +#include +#include +#include + +static struct udp_ops *udp_ops; + +int udp_prereq(void) +{ + int ret = 0; + + if (udp_ops->prereq) + ret = udp_ops->prereq(udp_ops->data); + + return ret; +} + +int udp_start(void) +{ + return udp_ops->start(udp_ops->data); +} + +int udp_loop(struct udp_ops *ops) +{ + int ret = -1; + + if (!ops) { + printf("%s: ops should not be null\n", __func__); + goto out; + } + + if (!ops->start) { + printf("%s: no start function defined\n", __func__); + goto out; + } + + udp_ops = ops; + ret = net_loop(UDP); + + out: + return ret; +} -- cgit v1.3.1 From 912ece4c3dd486bcd62f0d0dfee760b9f01caac6 Mon Sep 17 00:00:00 2001 From: Philippe Reynes Date: Fri, 18 Sep 2020 14:13:02 +0200 Subject: sntp: use udp framework This commits update the support of sntp to use the framework udp. This change allows to remove all the reference to sntp in the main network file net/net.c. Signed-off-by: Philippe Reynes Reviewed-by: Simon Glass --- cmd/Kconfig | 1 + cmd/net.c | 10 +++++++++- include/net/sntp.h | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ net/net.c | 31 +---------------------------- net/sntp.c | 29 +++++++++++++++++++++++++-- net/sntp.h | 57 ----------------------------------------------------- 6 files changed, 96 insertions(+), 90 deletions(-) create mode 100644 include/net/sntp.h delete mode 100644 net/sntp.h (limited to 'include') diff --git a/cmd/Kconfig b/cmd/Kconfig index 30c358d7e74..999b6cf239a 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1645,6 +1645,7 @@ config CMD_CDP config CMD_SNTP bool "sntp" + select PROT_UDP help Synchronize RTC via network diff --git a/cmd/net.c b/cmd/net.c index 9bbcdbcfe07..beb2877dfd5 100644 --- a/cmd/net.c +++ b/cmd/net.c @@ -13,6 +13,8 @@ #include #include #include +#include +#include static int netboot_common(enum proto_t, struct cmd_tbl *, int, char * const []); @@ -356,6 +358,12 @@ U_BOOT_CMD( #endif #if defined(CONFIG_CMD_SNTP) +static struct udp_ops sntp_ops = { + .prereq = sntp_prereq, + .start = sntp_start, + .data = NULL, +}; + int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char *toff; @@ -380,7 +388,7 @@ int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) else net_ntp_time_offset = simple_strtol(toff, NULL, 10); - if (net_loop(SNTP) < 0) { + if (udp_loop(&sntp_ops) < 0) { printf("SNTP failed: host %pI4 not responding\n", &net_ntp_server); return CMD_RET_FAILURE; diff --git a/include/net/sntp.h b/include/net/sntp.h new file mode 100644 index 00000000000..30b44d1c066 --- /dev/null +++ b/include/net/sntp.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Masami Komiya 2005 + */ + +#ifndef __SNTP_H__ +#define __SNTP_H__ + +#define NTP_SERVICE_PORT 123 +#define SNTP_PACKET_LEN 48 + + +/* Leap Indicator */ +#define NTP_LI_NOLEAP 0x0 +#define NTP_LI_61SECS 0x1 +#define NTP_LI_59SECS 0x2 +#define NTP_LI_ALARM 0x3 + +/* Version */ + +#define NTP_VERSION 4 + +/* Mode */ +#define NTP_MODE_RESERVED 0 +#define NTP_MODE_SYMACTIVE 1 /* Symmetric Active */ +#define NTP_MODE_SYMPASSIVE 2 /* Symmetric Passive */ +#define NTP_MODE_CLIENT 3 +#define NTP_MODE_SERVER 4 +#define NTP_MODE_BROADCAST 5 +#define NTP_MODE_NTPCTRL 6 /* Reserved for NTP control message */ +#define NTP_MODE_PRIVATE 7 /* Reserved for private use */ + +struct sntp_pkt_t { +#if __LITTLE_ENDIAN + uchar mode:3; + uchar vn:3; + uchar li:2; +#else + uchar li:2; + uchar vn:3; + uchar mode:3; +#endif + uchar stratum; + uchar poll; + uchar precision; + uint root_delay; + uint root_dispersion; + uint reference_id; + unsigned long long reference_timestamp; + unsigned long long originate_timestamp; + unsigned long long receive_timestamp; + unsigned long long transmit_timestamp; +} __attribute__((packed)); + +int sntp_prereq(void *data); +int sntp_start(void *data); /* Begin SNTP */ + +#endif /* __SNTP_H__ */ diff --git a/net/net.c b/net/net.c index 1ce0eb57a75..197fde3568d 100644 --- a/net/net.c +++ b/net/net.c @@ -72,12 +72,6 @@ * We want: - load the boot file * Next step: none * - * SNTP: - * - * Prerequisites: - own ethernet address - * - own IP address - * We want: - network time - * Next step: none * * WOL: * @@ -119,9 +113,6 @@ #include "nfs.h" #include "ping.h" #include "rarp.h" -#if defined(CONFIG_CMD_SNTP) -#include "sntp.h" -#endif #if defined(CONFIG_CMD_WOL) #include "wol.h" #endif @@ -185,13 +176,6 @@ u32 net_boot_file_size; /* Boot file size in blocks as reported by the DHCP server */ u32 net_boot_file_expected_size_in_blocks; -#if defined(CONFIG_CMD_SNTP) -/* NTP server IP address */ -struct in_addr net_ntp_server; -/* offset time from UTC */ -int net_ntp_time_offset; -#endif - static uchar net_pkt_buf[(PKTBUFSRX+1) * PKTSIZE_ALIGN + PKTALIGN]; /* Receive packets */ uchar *net_rx_packets[PKTBUFSRX]; @@ -521,11 +505,6 @@ restart: nc_start(); break; #endif -#if defined(CONFIG_CMD_SNTP) - case SNTP: - sntp_start(); - break; -#endif #if defined(CONFIG_CMD_DNS) case DNS: dns_start(); @@ -1352,14 +1331,6 @@ static int net_check_prereq(enum proto_t protocol) } goto common; #endif -#if defined(CONFIG_CMD_SNTP) - case SNTP: - if (net_ntp_server.s_addr == 0) { - puts("*** ERROR: NTP server address not given\n"); - return 1; - } - goto common; -#endif #if defined(CONFIG_CMD_DNS) case DNS: if (net_dns_server.s_addr == 0) { @@ -1385,7 +1356,7 @@ static int net_check_prereq(enum proto_t protocol) puts("*** ERROR: `serverip' not set\n"); return 1; } -#if defined(CONFIG_CMD_PING) || defined(CONFIG_CMD_SNTP) || \ +#if defined(CONFIG_CMD_PING) || \ defined(CONFIG_CMD_DNS) || defined(CONFIG_PROT_UDP) common: #endif diff --git a/net/sntp.c b/net/sntp.c index 39d7664a224..d5d56719331 100644 --- a/net/sntp.c +++ b/net/sntp.c @@ -12,12 +12,17 @@ #include #include -#include "sntp.h" +#include #define SNTP_TIMEOUT 10000UL static int sntp_our_port; +/* NTP server IP address */ +struct in_addr net_ntp_server; +/* offset time from UTC */ +int net_ntp_time_offset; + static void sntp_send(void) { struct sntp_pkt_t pkt; @@ -93,7 +98,25 @@ static void sntp_handler(uchar *pkt, unsigned dest, struct in_addr sip, net_set_state(NETLOOP_SUCCESS); } -void sntp_start(void) +/* + * SNTP: + * + * Prerequisites: - own ethernet address + * - own IP address + * We want: - network time + * Next step: none + */ +int sntp_prereq(void *data) +{ + if (net_ntp_server.s_addr == 0) { + puts("*** ERROR: NTP server address not given\n"); + return 1; + } + + return 0; +} + +int sntp_start(void *data) { debug("%s\n", __func__); @@ -102,4 +125,6 @@ void sntp_start(void) memset(net_server_ethaddr, 0, sizeof(net_server_ethaddr)); sntp_send(); + + return 0; } diff --git a/net/sntp.h b/net/sntp.h deleted file mode 100644 index d3cbfbc69a6..00000000000 --- a/net/sntp.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Masami Komiya 2005 - */ - -#ifndef __SNTP_H__ -#define __SNTP_H__ - -#define NTP_SERVICE_PORT 123 -#define SNTP_PACKET_LEN 48 - - -/* Leap Indicator */ -#define NTP_LI_NOLEAP 0x0 -#define NTP_LI_61SECS 0x1 -#define NTP_LI_59SECS 0x2 -#define NTP_LI_ALARM 0x3 - -/* Version */ - -#define NTP_VERSION 4 - -/* Mode */ -#define NTP_MODE_RESERVED 0 -#define NTP_MODE_SYMACTIVE 1 /* Symmetric Active */ -#define NTP_MODE_SYMPASSIVE 2 /* Symmetric Passive */ -#define NTP_MODE_CLIENT 3 -#define NTP_MODE_SERVER 4 -#define NTP_MODE_BROADCAST 5 -#define NTP_MODE_NTPCTRL 6 /* Reserved for NTP control message */ -#define NTP_MODE_PRIVATE 7 /* Reserved for private use */ - -struct sntp_pkt_t { -#if __LITTLE_ENDIAN - uchar mode:3; - uchar vn:3; - uchar li:2; -#else - uchar li:2; - uchar vn:3; - uchar mode:3; -#endif - uchar stratum; - uchar poll; - uchar precision; - uint root_delay; - uint root_dispersion; - uint reference_id; - unsigned long long reference_timestamp; - unsigned long long originate_timestamp; - unsigned long long receive_timestamp; - unsigned long long transmit_timestamp; -} __attribute__((packed)); - -void sntp_start(void); /* Begin SNTP */ - -#endif /* __SNTP_H__ */ -- cgit v1.3.1 From 719d7d8df41d2f20be599c38c3ab3e7a904c92c6 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 18:59:55 +0200 Subject: usb: xhci: add a member hci_version in xhci_ctrl struct Add a member to save xHCI version, it's used some times. Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-ring.c | 4 ++-- drivers/usb/host/xhci.c | 1 + include/usb/xhci.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 092ed6eaf10..79bfc349f44 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -682,7 +682,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, field |= TRB_ISP; /* Set the TRB length, TD size, and interrupter fields. */ - if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) < 0x100) + if (ctrl->hci_version < 0x100) remainder = xhci_td_remainder(length - running_total); else remainder = xhci_v1_0_td_remainder(running_total, @@ -830,7 +830,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, field |= 0x1; /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ - if (HC_VERSION(xhci_readl(&ctrl->hccr->cr_capbase)) >= 0x100) { + if (ctrl->hci_version >= 0x100) { if (length > 0) { if (req->requesttype & USB_DIR_IN) field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 126dabc11ba..4be14112435 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -1283,6 +1283,7 @@ static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) reg = HC_VERSION(xhci_readl(&hccr->cr_capbase)); printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff); + ctrl->hci_version = reg; return 0; } diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 7d34103fd5c..a3e5914b10f 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1227,6 +1227,7 @@ struct xhci_ctrl { struct xhci_scratchpad *scratchpad; struct xhci_virt_device *devs[MAX_HC_SLOTS]; int rootdev; + u16 hci_version; }; unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); -- cgit v1.3.1 From e3ea481bee1fbc8f090f46c38354838a64958af4 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 18:59:56 +0200 Subject: usb: xhci: create one unified function to calculate TRB TD remainder xhci versions 1.0 and later report the untransferred data remaining in a TD a bit differently than older hosts. We used to have separate functions for these, and needed to check host version before calling the right function. Now Mediatek host has an additional quirk on how it uses the TD Size field for remaining data. To prevent yet another function for calculating remainder we instead want to make one quirk friendly unified function. Porting from the Linux: c840d6ce772d("xhci: create one unified function to calculate TRB TD remainder.") 124c39371114("xhci: use boolean to indicate last trb in td remainder calculation") Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-ring.c | 105 +++++++++++++++++++++---------------------- include/usb/xhci.h | 2 + 2 files changed, 52 insertions(+), 55 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 79bfc349f44..603e0e5b765 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -298,55 +298,52 @@ void xhci_queue_command(struct xhci_ctrl *ctrl, u8 *ptr, u32 slot_id, xhci_writel(&ctrl->dba->doorbell[0], DB_VALUE_HOST); } -/** - * The TD size is the number of bytes remaining in the TD (including this TRB), - * right shifted by 10. - * It must fit in bits 21:17, so it can't be bigger than 31. +/* + * For xHCI 1.0 host controllers, TD size is the number of max packet sized + * packets remaining in the TD (*not* including this TRB). * - * @param remainder remaining packets to be sent - * @return remainder if remainder is less than max else max - */ -static u32 xhci_td_remainder(unsigned int remainder) -{ - u32 max = (1 << (21 - 17 + 1)) - 1; - - if ((remainder >> 10) >= max) - return max << 17; - else - return (remainder >> 10) << 17; -} - -/** - * Finds out the remanining packets to be sent + * Total TD packet count = total_packet_count = + * DIV_ROUND_UP(TD size in bytes / wMaxPacketSize) + * + * Packets transferred up to and including this TRB = packets_transferred = + * rounddown(total bytes transferred including this TRB / wMaxPacketSize) + * + * TD size = total_packet_count - packets_transferred * - * @param running_total total size sent so far + * For xHCI 0.96 and older, TD size field should be the remaining bytes + * including this TRB, right shifted by 10 + * + * For all hosts it must fit in bits 21:17, so it can't be bigger than 31. + * This is taken care of in the TRB_TD_SIZE() macro + * + * The last TRB in a TD must have the TD size set to zero. + * + * @param ctrl host controller data structure + * @param transferred total size sent so far * @param trb_buff_len length of the TRB Buffer - * @param total_packet_count total packet count - * @param maxpacketsize max packet size of current pipe - * @param num_trbs_left number of TRBs left to be processed - * @return 0 if running_total or trb_buff_len is 0, else remainder + * @param td_total_len total packet count + * @param maxp max packet size of current pipe + * @param more_trbs_coming indicate last trb in TD + * @return remainder */ -static u32 xhci_v1_0_td_remainder(int running_total, - int trb_buff_len, - unsigned int total_packet_count, - int maxpacketsize, - unsigned int num_trbs_left) +static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred, + int trb_buff_len, unsigned int td_total_len, + int maxp, bool more_trbs_coming) { - int packets_transferred; + u32 total_packet_count; + + if (ctrl->hci_version < 0x100) + return ((td_total_len - transferred) >> 10); /* One TRB with a zero-length data packet. */ - if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0)) + if (!more_trbs_coming || (transferred == 0 && trb_buff_len == 0) || + trb_buff_len == td_total_len) return 0; - /* - * All the TRB queueing functions don't count the current TRB in - * running_total. - */ - packets_transferred = (running_total + trb_buff_len) / maxpacketsize; + total_packet_count = DIV_ROUND_UP(td_total_len, maxp); - if ((total_packet_count - packets_transferred) > 31) - return 31 << 17; - return (total_packet_count - packets_transferred) << 17; + /* Queueing functions don't count the current TRB into transferred */ + return (total_packet_count - ((transferred + trb_buff_len) / maxp)); } /** @@ -572,7 +569,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, union xhci_trb *event; int running_total, trb_buff_len; - unsigned int total_packet_count; + bool more_trbs_coming = true; int maxpacketsize; u64 addr; int ret; @@ -636,8 +633,6 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, running_total = 0; maxpacketsize = usb_maxpacket(udev, pipe); - total_packet_count = DIV_ROUND_UP(length, maxpacketsize); - /* How much data is in the first TRB? */ /* * How much data is (potentially) left before the 64KB boundary? @@ -672,27 +667,24 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, * Chain all the TRBs together; clear the chain bit in the last * TRB to indicate it's the last TRB in the chain. */ - if (num_trbs > 1) + if (num_trbs > 1) { field |= TRB_CHAIN; - else + } else { field |= TRB_IOC; + more_trbs_coming = false; + } /* Only set interrupt on short packet for IN endpoints */ if (usb_pipein(pipe)) field |= TRB_ISP; /* Set the TRB length, TD size, and interrupter fields. */ - if (ctrl->hci_version < 0x100) - remainder = xhci_td_remainder(length - running_total); - else - remainder = xhci_v1_0_td_remainder(running_total, - trb_buff_len, - total_packet_count, - maxpacketsize, - num_trbs - 1); + remainder = xhci_td_remainder(ctrl, running_total, trb_buff_len, + length, maxpacketsize, + more_trbs_coming); length_field = ((trb_buff_len & TRB_LEN_MASK) | - remainder | + TRB_TD_SIZE(remainder) | ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT)); @@ -764,6 +756,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, struct xhci_virt_device *virt_dev = ctrl->devs[slot_id]; struct xhci_ring *ep_ring; union xhci_trb *event; + u32 remainder; debug("req=%u (%#x), type=%u (%#x), value=%u (%#x), index=%u\n", req->request, req->request, @@ -866,12 +859,14 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, else field = (TRB_DATA << TRB_TYPE_SHIFT); - length_field = (length & TRB_LEN_MASK) | xhci_td_remainder(length) | + remainder = xhci_td_remainder(ctrl, 0, length, length, + usb_maxpacket(udev, pipe), true); + length_field = (length & TRB_LEN_MASK) | TRB_TD_SIZE(remainder) | ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); debug("length_field = %d, length = %d," "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n", length_field, (length & TRB_LEN_MASK), - xhci_td_remainder(length), 0); + TRB_TD_SIZE(remainder), 0); if (length > 0) { if (req->requesttype & USB_DIR_IN) diff --git a/include/usb/xhci.h b/include/usb/xhci.h index a3e5914b10f..15926eb9f4d 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -850,6 +850,8 @@ struct xhci_event_cmd { /* transfer_len bitmasks - bits 0:16 */ #define TRB_LEN(p) ((p) & 0x1ffff) #define TRB_LEN_MASK (0x1ffff) +/* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ +#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) /* Interrupter Target - which MSI-X vector to target the completion event at */ #define TRB_INTR_TARGET_SHIFT (22) #define TRB_INTR_TARGET_MASK (0x3ff) -- cgit v1.3.1 From 740820519c69d84b320199a8a4348e47c447ebfb Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 18:59:57 +0200 Subject: usb: xhci: add quirks flag to support MediaTek xHCI 0.96 There some vendor quirks for MTK xHCI 0.96 host controller: 1. It defines some extra SW scheduling parameters for HW to minimize the scheduling effort for synchronous and interrupt endpoints. The parameters are put into reserved DWs of slot context and endpoint context. 2. Its TDS in Normal TRB defines a number of packets that remains to be transferred for a TD after processing all Max packets in all previous TRBs. Signed-off-by: Chunfeng Yun Tested-by: Frank Wunderlich Reviewed-by: Bin Meng --- drivers/usb/host/xhci-mtk.c | 1 + drivers/usb/host/xhci-ring.c | 9 +++++++-- drivers/usb/host/xhci.c | 2 +- include/usb/xhci.h | 2 ++ 4 files changed, 11 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c index 8ff71854fcd..f3f181dae01 100644 --- a/drivers/usb/host/xhci-mtk.c +++ b/drivers/usb/host/xhci-mtk.c @@ -258,6 +258,7 @@ static int xhci_mtk_probe(struct udevice *dev) if (ret) goto ssusb_init_err; + mtk->ctrl.quirks = XHCI_MTK_HOST; hcor = (struct xhci_hcor *)((uintptr_t)mtk->hcd + HC_LENGTH(xhci_readl(&mtk->hcd->cr_capbase))); diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 603e0e5b765..3f915ae115e 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -332,7 +332,8 @@ static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred, { u32 total_packet_count; - if (ctrl->hci_version < 0x100) + /* MTK xHCI 0.96 contains some features from 1.0 */ + if (ctrl->hci_version < 0x100 && !(ctrl->quirks & XHCI_MTK_HOST)) return ((td_total_len - transferred) >> 10); /* One TRB with a zero-length data packet. */ @@ -340,6 +341,10 @@ static u32 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred, trb_buff_len == td_total_len) return 0; + /* for MTK xHCI 0.96, TD size include this TRB, but not in 1.x */ + if ((ctrl->quirks & XHCI_MTK_HOST) && (ctrl->hci_version < 0x100)) + trb_buff_len = 0; + total_packet_count = DIV_ROUND_UP(td_total_len, maxp); /* Queueing functions don't count the current TRB into transferred */ @@ -823,7 +828,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, field |= 0x1; /* xHCI 1.0 6.4.1.2.1: Transfer Type field */ - if (ctrl->hci_version >= 0x100) { + if (ctrl->hci_version >= 0x100 || ctrl->quirks & XHCI_MTK_HOST) { if (length > 0) { if (req->requesttype & USB_DIR_IN) field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 4be14112435..51edeb22c14 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -650,7 +650,7 @@ static int xhci_set_configuration(struct usb_device *udev) * are put into reserved DWs in Slot and Endpoint Contexts * for synchronous endpoints. */ - if (IS_ENABLED(CONFIG_USB_XHCI_MTK)) { + if (ctrl->quirks & XHCI_MTK_HOST) { ep_ctx[ep_index]->reserved[0] = cpu_to_le32(EP_BPKTS(1) | EP_BBM(1)); } diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 15926eb9f4d..3de46cd95e7 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -1230,6 +1230,8 @@ struct xhci_ctrl { struct xhci_virt_device *devs[MAX_HC_SLOTS]; int rootdev; u16 hci_version; + u32 quirks; +#define XHCI_MTK_HOST BIT(0) }; unsigned long trb_addr(struct xhci_segment *seg, union xhci_trb *trb); -- cgit v1.3.1 From 86d1fa17fb91d2579ed059db0125a198c7a388fd Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 18:59:58 +0200 Subject: usb: xhci: convert to HCS_MAX_PORTS() Use HCS_MAX_PORTS(p) instead of ((p & HCS_MAX_PORTS_MASK) >> HCS_MAX_PORTS_SHIFT) Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci.c | 3 +-- include/usb/xhci.h | 2 -- 2 files changed, 1 insertion(+), 4 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 51edeb22c14..5f3a0fba4b5 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -1257,8 +1257,7 @@ static int xhci_lowlevel_init(struct xhci_ctrl *ctrl) return -ENOMEM; reg = xhci_readl(&hccr->cr_hcsparams1); - descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >> - HCS_MAX_PORTS_SHIFT); + descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg); printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts); /* Port Indicators */ diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 3de46cd95e7..cf4c0208b2d 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -101,8 +101,6 @@ struct xhci_hccr { /* bits 8:18, Max Interrupters */ #define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff) /* bits 24:31, Max Ports - max value is 0x7F = 127 ports */ -#define HCS_MAX_PORTS_SHIFT 24 -#define HCS_MAX_PORTS_MASK (0xff << HCS_MAX_PORTS_SHIFT) #define HCS_MAX_PORTS(p) (((p) >> 24) & 0xff) /* HCSPARAMS2 - hcs_params2 - bitmasks */ -- cgit v1.3.1 From a826d76f2bab971b293b4ba6bf45b81871051383 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 18:59:59 +0200 Subject: usb: xhci: convert to TRB_TYPE() Use TRB_TYPE(p) instead of ((p) << TRB_TYPE_SHIFT) Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-mem.c | 3 +-- drivers/usb/host/xhci-ring.c | 11 +++++------ include/usb/xhci.h | 1 - 3 files changed, 6 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index 1da0524aa0e..d627aa55556 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -236,8 +236,7 @@ static void xhci_link_segments(struct xhci_segment *prev, */ val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control); val &= ~TRB_TYPE_BITMASK; - val |= (TRB_LINK << TRB_TYPE_SHIFT); - + val |= TRB_TYPE(TRB_LINK); prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val); } } diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 3f915ae115e..13c98fb09a7 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -696,7 +696,7 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, trb_fields[0] = lower_32_bits(addr); trb_fields[1] = upper_32_bits(addr); trb_fields[2] = length_field; - trb_fields[3] = field | (TRB_NORMAL << TRB_TYPE_SHIFT); + trb_fields[3] = field | TRB_TYPE(TRB_NORMAL); queue_trb(ctrl, ring, (num_trbs > 1), trb_fields); @@ -823,7 +823,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, /* Queue setup TRB - see section 6.4.1.2.1 */ /* FIXME better way to translate setup_packet into two u32 fields? */ field = 0; - field |= TRB_IDT | (TRB_SETUP << TRB_TYPE_SHIFT); + field |= TRB_IDT | TRB_TYPE(TRB_SETUP); if (start_cycle == 0) field |= 0x1; @@ -860,9 +860,9 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, /* If there's data, queue data TRBs */ /* Only set interrupt on short packet for IN endpoints */ if (usb_pipein(pipe)) - field = TRB_ISP | (TRB_DATA << TRB_TYPE_SHIFT); + field = TRB_ISP | TRB_TYPE(TRB_DATA); else - field = (TRB_DATA << TRB_TYPE_SHIFT); + field = TRB_TYPE(TRB_DATA); remainder = xhci_td_remainder(ctrl, 0, length, length, usb_maxpacket(udev, pipe), true); @@ -904,8 +904,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); /* Event on completion */ trb_fields[3] = field | TRB_IOC | - (TRB_STATUS << TRB_TYPE_SHIFT) | - ep_ring->cycle_state; + TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state; queue_trb(ctrl, ep_ring, false, trb_fields); diff --git a/include/usb/xhci.h b/include/usb/xhci.h index cf4c0208b2d..bdba51df599 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -903,7 +903,6 @@ union xhci_trb { /* TRB bit mask */ #define TRB_TYPE_BITMASK (0xfc00) #define TRB_TYPE(p) ((p) << 10) -#define TRB_TYPE_SHIFT (10) #define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10) /* TRB type IDs */ -- cgit v1.3.1 From 4312638eaf7f0bd29ffa8c7957bd51c5eb7d5a32 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 19:00:00 +0200 Subject: usb: xhci: convert to TRB_LEN() and TRB_INTR_TARGET() For normal TRB fields: use TRB_LEN(x) instead of ((x) & TRB_LEN_MASK); and use TRB_INTR_TARGET(x) instead of (((x) & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT) Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-ring.c | 16 +++++++--------- include/usb/xhci.h | 3 --- 2 files changed, 7 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 13c98fb09a7..9ef72efe959 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -688,10 +688,9 @@ int xhci_bulk_tx(struct usb_device *udev, unsigned long pipe, length, maxpacketsize, more_trbs_coming); - length_field = ((trb_buff_len & TRB_LEN_MASK) | + length_field = (TRB_LEN(trb_buff_len) | TRB_TD_SIZE(remainder) | - ((0 & TRB_INTR_TARGET_MASK) << - TRB_INTR_TARGET_SHIFT)); + TRB_INTR_TARGET(0)); trb_fields[0] = lower_32_bits(addr); trb_fields[1] = upper_32_bits(addr); @@ -849,8 +848,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, trb_fields[1] = le16_to_cpu(req->index) | le16_to_cpu(req->length) << 16; /* TRB_LEN | (TRB_INTR_TARGET) */ - trb_fields[2] = (8 | ((0 & TRB_INTR_TARGET_MASK) << - TRB_INTR_TARGET_SHIFT)); + trb_fields[2] = (TRB_LEN(8) | TRB_INTR_TARGET(0)); /* Immediate data in pointer */ trb_fields[3] = field; queue_trb(ctrl, ep_ring, true, trb_fields); @@ -866,11 +864,11 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, remainder = xhci_td_remainder(ctrl, 0, length, length, usb_maxpacket(udev, pipe), true); - length_field = (length & TRB_LEN_MASK) | TRB_TD_SIZE(remainder) | - ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + length_field = TRB_LEN(length) | TRB_TD_SIZE(remainder) | + TRB_INTR_TARGET(0); debug("length_field = %d, length = %d," "xhci_td_remainder(length) = %d , TRB_INTR_TARGET(0) = %d\n", - length_field, (length & TRB_LEN_MASK), + length_field, TRB_LEN(length), TRB_TD_SIZE(remainder), 0); if (length > 0) { @@ -901,7 +899,7 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, trb_fields[0] = 0; trb_fields[1] = 0; - trb_fields[2] = ((0 & TRB_INTR_TARGET_MASK) << TRB_INTR_TARGET_SHIFT); + trb_fields[2] = TRB_INTR_TARGET(0); /* Event on completion */ trb_fields[3] = field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state; diff --git a/include/usb/xhci.h b/include/usb/xhci.h index bdba51df599..35c66042baa 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -847,12 +847,9 @@ struct xhci_event_cmd { /* Normal TRB fields */ /* transfer_len bitmasks - bits 0:16 */ #define TRB_LEN(p) ((p) & 0x1ffff) -#define TRB_LEN_MASK (0x1ffff) /* TD Size, packets remaining in this TD, bits 21:17 (5 bits, so max 31) */ #define TRB_TD_SIZE(p) (min((p), (u32)31) << 17) /* Interrupter Target - which MSI-X vector to target the completion event at */ -#define TRB_INTR_TARGET_SHIFT (22) -#define TRB_INTR_TARGET_MASK (0x3ff) #define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22) #define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff) #define TRB_TBC(p) (((p) & 0x3) << 7) -- cgit v1.3.1 From bf58cf9ab1bf13654815d9db35d73c16d4651609 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 19:00:01 +0200 Subject: usb: xhci: convert to TRB_TX_TYPE() Use TRB_TX_TYPE() instead of (TRB_DATA_OUT/IN << TRB_TX_TYPE_SHIFT) Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-ring.c | 4 ++-- include/usb/xhci.h | 1 - 2 files changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c index 9ef72efe959..b118207d937 100644 --- a/drivers/usb/host/xhci-ring.c +++ b/drivers/usb/host/xhci-ring.c @@ -830,9 +830,9 @@ int xhci_ctrl_tx(struct usb_device *udev, unsigned long pipe, if (ctrl->hci_version >= 0x100 || ctrl->quirks & XHCI_MTK_HOST) { if (length > 0) { if (req->requesttype & USB_DIR_IN) - field |= (TRB_DATA_IN << TRB_TX_TYPE_SHIFT); + field |= TRB_TX_TYPE(TRB_DATA_IN); else - field |= (TRB_DATA_OUT << TRB_TX_TYPE_SHIFT); + field |= TRB_TX_TYPE(TRB_DATA_OUT); } } diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 35c66042baa..07b1aebc692 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -879,7 +879,6 @@ struct xhci_event_cmd { /* Control transfer TRB specific fields */ #define TRB_DIR_IN (1<<16) #define TRB_TX_TYPE(p) ((p) << 16) -#define TRB_TX_TYPE_SHIFT (16) #define TRB_DATA_OUT 2 #define TRB_DATA_IN 3 -- cgit v1.3.1 From 23a54ccfb6da1c011c42359b2d20928617928902 Mon Sep 17 00:00:00 2001 From: Chunfeng Yun Date: Tue, 8 Sep 2020 19:00:02 +0200 Subject: usb: xhci: use macros with parameter to fill ep_info2 Use macros with parameter to fill ep_info2, then some macros for MASK and SHIFT can be removed Signed-off-by: Chunfeng Yun Reviewed-by: Bin Meng --- drivers/usb/host/xhci-mem.c | 15 +++++---------- drivers/usb/host/xhci.c | 6 ++---- include/usb/xhci.h | 6 ------ 3 files changed, 7 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index d627aa55556..0b496149956 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -825,25 +825,22 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, /* Step 4 - ring already allocated */ /* Step 5 */ - ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT); + ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP)); debug("SPEED = %d\n", speed); switch (speed) { case USB_SPEED_SUPER: - ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) << - MAX_PACKET_SHIFT)); + ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512)); debug("Setting Packet size = 512bytes\n"); break; case USB_SPEED_HIGH: /* USB core guesses at a 64-byte max packet first for FS devices */ case USB_SPEED_FULL: - ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) << - MAX_PACKET_SHIFT)); + ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64)); debug("Setting Packet size = 64bytes\n"); break; case USB_SPEED_LOW: - ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) << - MAX_PACKET_SHIFT)); + ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8)); debug("Setting Packet size = 8bytes\n"); break; default: @@ -852,9 +849,7 @@ void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, } /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */ - ep0_ctx->ep_info2 |= - cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) | - ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT)); + ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3)); trb_64 = virt_to_phys(virt_dev->eps[0].ring->first_seg->trbs); ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state); diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c index 5f3a0fba4b5..fe30101d938 100644 --- a/drivers/usb/host/xhci.c +++ b/drivers/usb/host/xhci.c @@ -618,8 +618,7 @@ static int xhci_set_configuration(struct usb_device *udev) cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) | EP_INTERVAL(interval) | EP_MULT(mult)); - ep_ctx[ep_index]->ep_info2 = - cpu_to_le32(ep_type << EP_TYPE_SHIFT); + ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type)); ep_ctx[ep_index]->ep_info2 |= cpu_to_le32(MAX_PACKET (get_unaligned(&endpt_desc->wMaxPacketSize))); @@ -832,8 +831,7 @@ int xhci_check_maxpacket(struct usb_device *udev) ctrl->devs[slot_id]->out_ctx, ep_index); in_ctx = ctrl->devs[slot_id]->in_ctx; ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index); - ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK) - << MAX_PACKET_SHIFT)); + ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK)); ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size)); /* diff --git a/include/usb/xhci.h b/include/usb/xhci.h index 07b1aebc692..e1d382369a3 100644 --- a/include/usb/xhci.h +++ b/include/usb/xhci.h @@ -632,11 +632,8 @@ struct xhci_ep_ctx { */ #define FORCE_EVENT (0x1) #define ERROR_COUNT(p) (((p) & 0x3) << 1) -#define ERROR_COUNT_SHIFT (1) -#define ERROR_COUNT_MASK (0x3) #define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7) #define EP_TYPE(p) ((p) << 3) -#define EP_TYPE_SHIFT (3) #define ISOC_OUT_EP 1 #define BULK_OUT_EP 2 #define INT_OUT_EP 3 @@ -647,13 +644,10 @@ struct xhci_ep_ctx { /* bit 6 reserved */ /* bit 7 is Host Initiate Disable - for disabling stream selection */ #define MAX_BURST(p) (((p)&0xff) << 8) -#define MAX_BURST_MASK (0xff) -#define MAX_BURST_SHIFT (8) #define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff) #define MAX_PACKET(p) (((p)&0xffff) << 16) #define MAX_PACKET_MASK (0xffff) #define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff) -#define MAX_PACKET_SHIFT (16) /* Get max packet size from ep desc. Bit 10..0 specify the max packet size. * USB2.0 spec 9.6.6. -- cgit v1.3.1