From e443c944cf4050daffb46d4788446d6c2df8ac6c Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 20 Mar 2006 18:02:44 +0100 Subject: Support for redundant environment in NAND Flash. --- include/configs/delta.h | 1 + include/environment.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) (limited to 'include') diff --git a/include/configs/delta.h b/include/configs/delta.h index b42a7e2c1ae..f230b038551 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -282,6 +282,7 @@ /* #define CFG_ENV_IS_NOWHERE */ #define CFG_ENV_IS_IN_NAND 1 #define CFG_ENV_OFFSET 0x40000 +#define CFG_ENV_OFFSET_REDUND 0x44000 #define CFG_ENV_SIZE 0x4000 #endif /* __CONFIG_H */ diff --git a/include/environment.h b/include/environment.h index bb109649f6b..422f800897f 100644 --- a/include/environment.h +++ b/include/environment.h @@ -69,6 +69,18 @@ # endif #endif /* CFG_ENV_IS_IN_FLASH */ +#if defined(CFG_ENV_IS_IN_NAND) +# ifndef CFG_ENV_OFFSET +# error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND" +# endif +# ifndef CFG_ENV_SIZE +# error "Need to define CFG_ENV_SIZE when using CFG_ENV_IS_IN_NAND" +# endif +# ifdef CFG_ENV_OFFSET_REDUND +# define CFG_REDUNDAND_ENVIRONMENT +# endif +#endif /* CFG_ENV_IS_IN_NAND */ + #ifdef CFG_REDUNDAND_ENVIRONMENT # define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) -- cgit v1.3.1 From 552fc624f28d5db7b25f38c4e104fb7255d7df6b Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 20 Mar 2006 20:19:37 +0100 Subject: Cleanup of the monahans cpu and delta board port. --- board/delta/lowlevel_init.S | 245 +----------------------------------- board/delta/nand.c | 10 +- include/asm-arm/arch-pxa/pxa-regs.h | 117 ++++++++--------- include/configs/delta.h | 100 ++------------- 4 files changed, 77 insertions(+), 395 deletions(-) (limited to 'include') diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S index 498cf7f600d..f059db5059b 100644 --- a/board/delta/lowlevel_init.S +++ b/board/delta/lowlevel_init.S @@ -1,10 +1,5 @@ /* - * Most of this taken from Redboot hal_platform_setup.h with cleanup - * - * NOTE: I haven't clean this up considerably, just enough to get it - * running. See hal_platform_setup.h for the source. See - * board/cradle/lowlevel_init.S for another PXA250 setup that is - * much cleaner. + * (C) Copyright 2006 DENX Software Engineering * * See file CREDITS for list of people who contributed to this * project. @@ -31,14 +26,6 @@ DRAM_SIZE: .long CFG_DRAM_SIZE -/* wait for coprocessor write complete */ -.macro CPWAIT reg - mrc p15,0,\reg,c2,c0,0 - mov \reg,\reg - sub pc,pc,#4 -.endm - - .macro wait time ldr r2, =OSCR mov r3, #0 @@ -49,13 +36,9 @@ DRAM_SIZE: .long CFG_DRAM_SIZE bls 0b .endm -/* - * Memory setup - */ - .globl lowlevel_init lowlevel_init: - /* Set up GPIO pins first ----------------------------------------- */ + /* Set up GPIO pins first */ mov r10, lr /* Configure GPIO Pins 97, 98 UART1 / altern. Fkt. 1 */ @@ -73,22 +56,7 @@ lowlevel_init: bic r1, r1, #0x80000000 str r1, [r0] - /* ---------------------------------------------------------------- */ - /* Enable memory interface */ - /* ---------------------------------------------------------------- */ - - /* ---------------------------------------------------------------- */ - /* Step 1: Wait for at least 200 microsedonds to allow internal */ - /* clocks to settle. Only necessary after hard reset... */ - /* FIXME: can be optimized later */ - /* ---------------------------------------------------------------- */ -; wait #300 - mem_init: - -#define NEW_SDRAM_INIT 1 -#ifdef NEW_SDRAM_INIT - /* Configure ACCR Register - enable DMEMC Clock at 260 / 2 MHz */ ldr r0, =ACCR ldr r1, [r0] @@ -99,7 +67,7 @@ mem_init: /* 2. Programm MDCNFG, leaving DMCEN de-asserted */ ldr r0, =MDCNFG ldr r1, =(MDCNFG_DMAP | MDCNFG_DTYPE | MDCNFG_DTC_2 | MDCNFG_DCSE0 | MDCNFG_DRAC_13) - /* ldr r1, =0x80000403 */ + /* ldr r1, =0x80000403 */ str r1, [r0] ldr r1, [r0] /* delay until written */ @@ -140,121 +108,6 @@ mem_init: orr r1, r1, #MDCNFG_DMCEN str r1, [r0] - -#else /* NEW_SDRAM_INIT */ - - /* configure the MEMCLKCFG register */ - ldr r1, =MEMCLKCFG - ldr r2, =0x00010001 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set CSADRCFG[0] to data flash SRAM mode */ - ldr r1, =CSADRCFG0 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set CSADRCFG[1] to data flash SRAM mode */ - ldr r1, =CSADRCFG1 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set MSC 0 register for SRAM memory */ - ldr r1, =MSC0 - ldr r2, =0x11191119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set CSADRCFG[2] to data flash SRAM mode */ - ldr r1, =CSADRCFG2 - ldr r2, =0x00320809 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set CSADRCFG[3] to VLIO mode */ - ldr r1, =CSADRCFG3 - ldr r2, =0x0032080B - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - - /* set MSC 1 register for VLIO memory */ - ldr r1, =MSC1 - ldr r2, =0x123C1119 - str r2, [r1] @ WRITE - ldr r2, [r1] @ DELAY UNTIL WRITTEN - -#if 0 - /* This does not work in Zylonite. -SC */ - ldr r0, =0x15fffff0 - ldr r1, =0xb10b - str r1, [r0] - str r1, [r0, #4] -#endif - - /* Configure ACCR Register */ - ldr r0, =ACCR @ ACCR - ldr r1, =0x0180b108 - str r1, [r0] - ldr r1, [r0] - - /* Configure MDCNFG Register */ - ldr r0, =MDCNFG @ MDCNFG - ldr r1, =0x403 - str r1, [r0] - ldr r1, [r0] - - /* Perform Resistive Compensation by configuring RCOMP register */ - ldr r1, =RCOMP @ RCOMP - ldr r2, =0x000000ff - str r2, [r1] - ldr r2, [r1] - - /* Configure MDMRS Register for SDCS0 */ - ldr r1, =MDMRS @ MDMRS - ldr r2, =0x60000023 - ldr r3, [r1] - orr r2, r2, r3 - str r2, [r1] - ldr r2, [r1] - - /* Configure MDMRS Register for SDCS1 */ - ldr r1, =MDMRS @ MDMRS - ldr r2, =0xa0000023 - ldr r3, [r1] - orr r2, r2, r3 - str r2, [r1] - ldr r2, [r1] - - /* Configure MDREFR */ - ldr r1, =MDREFR @ MDREFR - ldr r2, =0x00000006 - str r2, [r1] - ldr r2, [r1] - - /* Configure EMPI */ - ldr r1, =EMPI @ EMPI - ldr r2, =0x80000000 - str r2, [r1] - ldr r2, [r1] - - /* Hardware DDR Read-Strobe Delay Calibration */ - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] - wait #5 - ldr r1, [r0] - - /* Here we assume the hardware calibration alwasy be successful. -SC */ - /* Set DMCEN bit in MDCNFG Register */ - ldr r0, =MDCNFG @ MDCNFG - ldr r1, [r0] - orr r1, r1, #0x40000000 @ enable SDRAM for Normal Access - str r1, [r0] - -#endif /* NEW_SDRAM_INIT */ - #ifndef CFG_SKIP_DRAM_SCRUB /* scrub/init SDRAM if enabled/present */ ldr r8, =CFG_DRAM_BASE /* base address of SDRAM (CFG_DRAM_BASE) */ @@ -290,96 +143,4 @@ mem_init: mcr p14,0,r0,c10,c0,0 /* dcsr */ endlowlevel_init: - mov pc, lr - - -/* -@******************************************************************************** -@ DDR calibration -@ -@ This function is used to calibrate DQS delay lines. -@ Monahans supports three ways to do it. One is software -@ calibration. Two is hardware calibration. Three is hybrid -@ calibration. -@ -@ TBD -@ -SC -ddr_calibration: - - @ Case 1: Write the correct delay value once - @ Configure DDR_SCAL Register - ldr r0, =DDR_SCAL @ DDR_SCAL -q ldr r1, =0xaf2f2f2f - str r1, [r0] - ldr r1, [r0] -*/ -/* @ Case 2: Software Calibration - @ Write test pattern to memory - ldr r5, =0x0faf0faf @ Data Pattern - ldr r4, =0xa0000000 @ DDR ram - str r5, [r4] - - mov r1, =0x0 @ delay count - mov r6, =0x0 - mov r7, =0x0 -ddr_loop1: - add r1, r1, =0x1 - cmp r1, =0xf - ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] - - ldr r2, [r4] - cmp r2, r5 - bne ddr_loop1 - mov r6, r1 -ddr_loop2: - add r1, r1, =0x1 - cmp r1, =0xf - ble end_loop - mov r3, r1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - str r3, [r2] - - ldr r2, [r4] - cmp r2, r5 - be ddr_loop2 - mov r7, r2 - - add r3, r6, r7 - lsr r3, r3, =0x1 - mov r0, r1, lsl #30 - orr r3, r3, r0 - mov r0, r1, lsl #22 - orr r3, r3, r0 - mov r0, r1, lsl #14 - orr r3, r3, r0 - orr r3, r3, =0x80000000 - ldr r2, =DDR_SCAL - -end_loop: - - @ Case 3: Hardware Calibratoin - ldr r0, =DDR_HCAL @ DDR_HCAL - ldr r1, =0x803ffc07 @ the offset is correct? -SC - str r1, [r0] - wait #5 - ldr r1, [r0] - mov pc, lr -*/ diff --git a/board/delta/nand.c b/board/delta/nand.c index 50def590906..c332f710d22 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -293,11 +293,6 @@ static int dfc_wait(struct mtd_info *mtd, struct nand_chip *this, int state) { unsigned long ndsr=0, event=0; - /* mk@tbd set appropriate timeouts */ - /* if (state == FL_ERASING) */ - /* timeo = CFG_HZ * 400; */ - /* else */ - /* timeo = CFG_HZ * 20; */ if(state == FL_WRITING) { event = NDSR_CS0_CMDD | NDSR_CS0_BBD; } else if(state == FL_ERASING) { @@ -563,13 +558,12 @@ void board_nand_init(struct nand_chip *nand) /* wait 10 us due to cmd buffer clear reset */ - /* wait(10); */ + /* wait(10); */ nand->hwcontrol = dfc_hwcontrol; -/* nand->dev_ready = dfc_device_ready; */ +/* nand->dev_ready = dfc_device_ready; */ nand->eccmode = NAND_ECC_SOFT; - nand->chip_delay = NAND_DELAY_US; nand->options = NAND_BUSWIDTH_16; nand->waitfunc = dfc_wait; nand->read_byte = dfc_read_byte; diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index 83ae5e3e13c..a92a4504dc8 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -821,21 +821,21 @@ typedef void (*ExcpHndlr) (void) ; #define RTAR __REG(0x40900004) /* RTC Alarm Register */ #define RTSR __REG(0x40900008) /* RTC Status Register */ #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */ -#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */ -#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */ -#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */ -#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */ -#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */ -#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */ -#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ -#define RDCR __REG(0x40900010) /* RTC Day Count Register. */ -#define RYCR __REG(0x40900014) /* RTC Year Count Register. */ -#define SWCR __REG(0x40900028) /* Stopwatch Count Register */ -#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */ - -#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ -#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ -#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ +#define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */ +#define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */ +#define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */ +#define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */ +#define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */ +#define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */ +#define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */ +#define RDCR __REG(0x40900010) /* RTC Day Count Register. */ +#define RYCR __REG(0x40900014) /* RTC Year Count Register. */ +#define SWCR __REG(0x40900028) /* Stopwatch Count Register */ +#define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */ + +#define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */ +#define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */ +#define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */ #define RTSR_HZE (1 << 3) /* HZ interrupt enable */ #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */ #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */ @@ -921,9 +921,10 @@ typedef void (*ExcpHndlr) (void) ; #ifdef CONFIG_CPU_MONAHANS #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ -/* Missing: 32 Interrupt priority registers */ -/* mk@tbd: These are the same as beneath for PXA27x: maybe can be - * merged if GPIO Stuff is same too. */ +/* Missing: 32 Interrupt priority registers + * These are the same as beneath for PXA27x: maybe can be merged if + * GPIO Stuff is same too. + */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */ @@ -983,24 +984,24 @@ typedef void (*ExcpHndlr) (void) ; #define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */ #define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */ -#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ +#define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */ #define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */ -#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ +#define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */ #define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */ -#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ +#define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */ #define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */ -#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ +#define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */ #define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */ -#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ +#define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */ #define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */ -#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ +#define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */ #define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */ -#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ +#define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */ #define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */ -#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ +#define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */ #define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3) #define GCDR(x) __REG2(0x40300420, ((x) & 0x60) >> 3) @@ -1488,8 +1489,8 @@ typedef void (*ExcpHndlr) (void) ; #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) -#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) -#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) +#define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT) +#define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT) /* * Power Manager @@ -1709,10 +1710,10 @@ typedef void (*ExcpHndlr) (void) ; #define ACCR_13MEND2 (1 << 21) #define ACCR_PCCE (1 << 11) -#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ -#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ -#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ -#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ +#define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */ +#define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */ +#define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */ +#define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */ #define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */ #define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */ #define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */ @@ -1720,27 +1721,27 @@ typedef void (*ExcpHndlr) (void) ; #define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */ #define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */ #define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */ -#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ -#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ -#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ -#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ -#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ -#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ -#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ -#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ -#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ -#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ -#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ -#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ +#define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */ +#define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */ +#define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */ +#define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */ +#define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */ +#define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */ +#define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */ +#define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */ +#define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */ +#define CKENA_9_SMC (1 << 9) /* Static Memory Controller */ +#define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */ +#define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */ #define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */ -#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ -#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ +#define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */ +#define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */ #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */ #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */ #define CKENB_8_1WIRE ((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */ -#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ -#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ +#define CKENB_7_GPIO ((1 << 7) + 32) /* GPIO Clock Enable */ +#define CKENB_6_IRQ ((1 << 6) + 32) /* Interrupt Controller Clock Enable */ #define CKENB_4_I2C ((1 << 4) + 32) /* I2C Unit Clock Enable */ #define CKENB_1_PWM1 ((1 << 1) + 32) /* PWM2 & PWM3 Clock Enable */ #define CKENB_0_PWM0 ((1 << 0) + 32) /* PWM0 & PWM1 Clock Enable */ @@ -2382,16 +2383,16 @@ typedef void (*ExcpHndlr) (void) ; #define KPAS_SO (0x1 << 31) #define KPASMKPx_SO (0x1 << 31) -#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ -#define PSLR __REG(0x40F00034) -#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ -#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ -#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ -#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ -#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ -#define OSMR4 __REG(0x40A00080) /* */ -#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ -#define OMCR4 __REG(0x40A000C0) /* */ +#define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */ +#define PSLR __REG(0x40F00034) +#define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */ +#define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */ +#define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */ +#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */ +#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */ +#define OSMR4 __REG(0x40A00080) /* */ +#define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */ +#define OMCR4 __REG(0x40A000C0) /* */ #endif /* CONFIG_PXA27X */ diff --git a/include/configs/delta.h b/include/configs/delta.h index f230b038551..cb002f72631 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -62,7 +62,7 @@ /* * select serial console configuration */ -#define CONFIG_FFUART 1 +#define CONFIG_FFUART 1 /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE @@ -168,8 +168,6 @@ #define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 -#define NAND_DELAY_US 25 /* mk@tbd: could be 0, I guess */ /* nand timeout values */ #define CFG_NAND_PROG_ERASE_TO 3000 @@ -178,16 +176,15 @@ #undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ /* NAND Timing Parameters (in ns) */ -#define NAND_TIMING_tCH 10 -#define NAND_TIMING_tCS 0 +#define NAND_TIMING_tCH 10 +#define NAND_TIMING_tCS 0 #define NAND_TIMING_tWH 20 -#define NAND_TIMING_tWP 40 +#define NAND_TIMING_tWP 40 -#define NAND_TIMING_tRH 20 -#define NAND_TIMING_tRP 40 +#define NAND_TIMING_tRH 20 +#define NAND_TIMING_tRP 40 -#define NAND_TIMING_tR 11123 -/* #define NAND_TIMING_tWHR 110 */ +#define NAND_TIMING_tR 11123 #define NAND_TIMING_tWHR 100 #define NAND_TIMING_tAR 10 @@ -199,87 +196,16 @@ #define CONFIG_MTD_DEBUG #define CONFIG_MTD_DEBUG_VERBOSE 1 -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 +#define ADDR_COLUMN 1 +#define ADDR_PAGE 2 +#define ADDR_COLUMN_PAGE 3 #define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - -#define CFG_NO_FLASH 1 -#ifndef CGF_NO_FLASH -/* these are required by the environment code */ -#define PHYS_FLASH_1 CFG_NAND0_BASE /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define PHYS_FLASH_BANK_SIZE 0x04000000 /* 64 MB Banks */ -#define PHYS_FLASH_SECT_SIZE (SECTORSIZE*1024) /* KB sectors (x2) */ -#endif +#define NAND_MAX_FLOORS 1 +#define NAND_MAX_CHIPS 1 -/* - * GPIO settings - */ -#define CFG_GPSR0_VAL 0x00008000 -#define CFG_GPSR1_VAL 0x00FC0382 -#define CFG_GPSR2_VAL 0x0001FFFF -#define CFG_GPCR0_VAL 0x00000000 -#define CFG_GPCR1_VAL 0x00000000 -#define CFG_GPCR2_VAL 0x00000000 -#define CFG_GPDR0_VAL 0x0060A800 -#define CFG_GPDR1_VAL 0x00FF0382 -#define CFG_GPDR2_VAL 0x0001C000 -#define CFG_GAFR0_L_VAL 0x98400000 -#define CFG_GAFR0_U_VAL 0x00002950 -#define CFG_GAFR1_L_VAL 0x000A9558 -#define CFG_GAFR1_U_VAL 0x0005AAAA -#define CFG_GAFR2_L_VAL 0xA0000000 -#define CFG_GAFR2_U_VAL 0x00000002 - -#define CFG_PSSR_VAL 0x20 - -/* - * Memory settings - */ -#define CFG_MSC0_VAL 0x23F223F2 -#define CFG_MSC1_VAL 0x3FF1A441 -#define CFG_MSC2_VAL 0x7FF97FF1 -#define CFG_MDCNFG_VAL 0x00001AC9 -#define CFG_MDREFR_VAL 0x00018018 -#define CFG_MDMRS_VAL 0x00000000 - -/* - * PCMCIA and CF Interfaces - */ -#define CFG_MECR_VAL 0x00000000 -#define CFG_MCMEM0_VAL 0x00010504 -#define CFG_MCMEM1_VAL 0x00010504 -#define CFG_MCATT0_VAL 0x00010504 -#define CFG_MCATT1_VAL 0x00010504 -#define CFG_MCIO0_VAL 0x00004715 -#define CFG_MCIO1_VAL 0x00004715 - -#define _LED 0x08000010 -#define LED_BLANK 0x08000040 - -/* - * FLASH and environment organization - */ -#ifndef CFG_NO_FLASH -#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ - - -/* NOTE: many default partitioning schemes assume the kernel starts at the - * second sector, not an environment. You have been warned! - */ -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#endif /* #ifndef CFG_NO_FLASH */ +#define CFG_NO_FLASH 1 -/* #define CFG_ENV_IS_NOWHERE */ #define CFG_ENV_IS_IN_NAND 1 #define CFG_ENV_OFFSET 0x40000 #define CFG_ENV_OFFSET_REDUND 0x44000 -- cgit v1.3.1 From 5725f94aace1ed75bbeb9f3c528f34d1ae4dbe69 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Tue, 21 Mar 2006 01:58:07 +0100 Subject: Cleanup MCC200 board configuration; omit non-existent stuff. --- CHANGELOG | 2 ++ include/configs/mcc200.h | 25 +++---------------------- 2 files changed, 5 insertions(+), 22 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 08595d52e03..f96f3f9f226 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Cleanup MCC200 board configuration; omit non-existent stuff. + * Add support for MPC859/866 Rev. A.0 * Add command for handling DDR ECC registers on MPC8349EE MDS board. diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index d4dee3b77a1..b9b54eb879f 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -67,13 +67,8 @@ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ ADD_USB_CMD | \ CFG_CMD_BEDBUG | \ - CFG_CMD_DATE | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ CFG_CMD_FAT | \ - CFG_CMD_I2C | \ - CFG_CMD_NFS | \ - CFG_CMD_SNTP ) + CFG_CMD_I2C) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include @@ -131,25 +126,11 @@ * I2C configuration */ #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */ +#define CFG_I2C_MODULE 1 /* Select I2C module #1 or #2 */ #define CFG_I2C_SPEED 100000 /* 100 kHz */ #define CFG_I2C_SLAVE 0x7F -/* - * EEPROM configuration - */ -#define CFG_I2C_EEPROM_ADDR 0x58 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * RTC configuration - */ -#define CONFIG_RTC_PCF8563 -#define CFG_I2C_RTC_ADDR 0x51 - /* * Flash configuration (8,16 or 32 MB) * TEXT base always at 0xFFF00000 @@ -231,7 +212,7 @@ */ /* 0x10000004 = 32MB SDRAM */ /* 0x90000004 = 64MB SDRAM */ -#define CFG_GPS_PORT_CONFIG 0x10000004 +#define CFG_GPS_PORT_CONFIG 0x00000004 /* * Miscellaneous configurable options -- cgit v1.3.1 From 05d8dce9d07cf4073ea15fbc448c1ce22b6baf0f Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 23 Mar 2006 17:10:30 +0100 Subject: Enable Quad UART om MCC200 board. --- CHANGELOG | 2 ++ include/configs/mcc200.h | 5 +++++ 2 files changed, 7 insertions(+) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index f96f3f9f226..34b8d20ebb6 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Enable Quad UART om MCC200 board. + * Cleanup MCC200 board configuration; omit non-existent stuff. * Add support for MPC859/866 Rev. A.0 diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index b9b54eb879f..67c248367af 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -247,6 +247,11 @@ #define CFG_CS0_START CFG_FLASH_BASE #define CFG_CS0_SIZE CFG_FLASH_SIZE +/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ +#define CFG_CS2_START 0x80000000 +#define CFG_CS2_SIZE 0x00001000 +#define CFG_CS2_CFG 0x1d800 + #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 -- cgit v1.3.1 From ba70d6a4170ebbec5513f01ceae66a200102ba9a Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Fri, 24 Mar 2006 12:23:27 +0100 Subject: delta board: DA9030 initialization and i2c support. Some minor changes to make the pxa i2c driver work with the monahans cpu. --- board/delta/delta.c | 67 +++++++++++++++++++++++ cpu/pxa/i2c.c | 19 +++++-- include/asm-arm/arch-pxa/pxa-regs.h | 6 +- include/configs/delta.h | 18 ++++-- include/da9030.h | 106 ++++++++++++++++++++++++++++++++++++ 5 files changed, 204 insertions(+), 12 deletions(-) create mode 100644 include/da9030.h (limited to 'include') diff --git a/board/delta/delta.c b/board/delta/delta.c index 3ffcc2af9b1..6ef7e2fc26f 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -26,9 +26,13 @@ */ #include +#include +#include +#include /* ------------------------------------------------------------------------- */ +static void init_DA9030(void); /* * Miscelaneous platform dependent initialisations @@ -54,6 +58,7 @@ int board_late_init(void) { setenv("stdout", "serial"); setenv("stderr", "serial"); + init_DA9030(); return 0; } @@ -73,3 +78,65 @@ int dram_init (void) return 0; } + +/* initialize the DA9030 Power Controller */ +static void init_DA9030() +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + + /* setup I2C GPIO's */ + GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ + GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ + + /* rising Edge on EXTON */ + GPIO17 = 0x8800; + udelay(5); + GPIO17 = 0xc800; + udelay(100000); /* wait for DA9030 */ + + /* reset the watchdog and go active (0xec) */ + val = (SYS_CONTROL_A_HWRES_ENABLE | + (0x6<<4) | + SYS_CONTROL_A_WDOG_ACTION | + SYS_CONTROL_A_WATCHDOG); + + i2c_reg_write(addr, SYS_CONTROL_A, val); + + i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ + i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */ + i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */ + i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */ + i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */ + i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */ + i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */ + i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */ + i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */ + i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */ + i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */ + i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */ + i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */ + i2c_reg_write(addr, REG_CONTROL_2_18, 0x43); /* Ball on */ + i2c_reg_write(addr, MISC_CONTROLB, 0x08); /* session valid enable */ + i2c_reg_write(addr, USBPUMP, 0xc1); /* start pump, ignore HW signals */ + + val = i2c_reg_read(addr, STATUS); + if(val & STATUS_CHDET) + printf("Charger detected, turning on LED.\n"); + else { + printf("No charger detetected.\n"); + /* undervoltage? print error and power down */ + } +} + + +#if 0 +/* reset the DA9030 watchdog */ +void hw_watchdog_reset(void) +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + val = i2c_reg_read(addr, SYS_CONTROL_A); + val |= SYS_CONTROL_A_WATCHDOG; + i2c_reg_write(addr, SYS_CONTROL_A, val); +} +#endif diff --git a/cpu/pxa/i2c.c b/cpu/pxa/i2c.c index b6155b137ed..722d949473f 100644 --- a/cpu/pxa/i2c.c +++ b/cpu/pxa/i2c.c @@ -47,7 +47,13 @@ /*#define DEBUG_I2C 1 /###* activate local debugging output */ #define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ -#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) + +#if (CFG_I2C_SPEED == 400000) +#define I2C_ICR_INIT (ICR_FM | ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#else +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) +#endif + #define I2C_ISR_INIT 0x7FF #ifdef DEBUG_I2C @@ -91,7 +97,11 @@ static void i2c_reset( void ) ICR |= ICR_UR; /* reset the unit */ udelay(100); ICR &= ~ICR_IUE; /* disable unit */ +#ifdef CONFIG_CPU_MONAHANS + CKENB |= (CKENB_4_I2C); /* | CKENB_1_PWM1 | CKENB_0_PWM0); */ +#else /* CONFIG_CPU_MONAHANS */ CKEN |= CKEN14_I2C; /* set the global I2C clock on */ +#endif ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ ICR = I2C_ICR_INIT; /* set control register values */ ISR = I2C_ISR_INIT; /* set clear interrupt bits */ @@ -104,9 +114,8 @@ static void i2c_reset( void ) * i2c_isr_set_cleared: - wait until certain bits of the I2C status register * are set and cleared * - * @return: 0 in case of success, 1 means timeout (no match within 10 ms). + * @return: 1 in case of success, 0 means timeout (no match within 10 ms). */ - static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) { int timeout = 10000; @@ -360,9 +369,9 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) msg.data = 0x00; if ((ret=i2c_transfer(&msg))) return -1; - *(buffer++) = msg.data; - + *buffer = msg.data; PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); + buffer++; } diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index a92a4504dc8..ebda7192ed0 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -475,11 +475,11 @@ typedef void (*ExcpHndlr) (void) ; #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ #define ICR_TB 0x8 /* transfer byte bit */ #define ICR_MA 0x10 /* master abort */ -#define ICR_SCLE 0x20 /* master clock enable */ +#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */ #define ICR_IUE 0x40 /* unit enable */ #define ICR_GCD 0x80 /* general call disable */ #define ICR_ITEIE 0x100 /* enable tx interrupts */ -#define ICR_IRFIE 0x200 /* enable rx interrupts */ +#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */ #define ICR_BEIE 0x400 /* enable bus error ints */ #define ICR_SSDIE 0x800 /* slave STOP detected int enable */ #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ @@ -923,7 +923,7 @@ typedef void (*ExcpHndlr) (void) ; #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */ /* Missing: 32 Interrupt priority registers * These are the same as beneath for PXA27x: maybe can be merged if - * GPIO Stuff is same too. + * GPIO Stuff is same too. */ #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */ #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */ diff --git a/include/configs/delta.h b/include/configs/delta.h index cb002f72631..eaa4c432b8a 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -49,7 +49,6 @@ /* * Hardware drivers */ - #undef TURN_ON_ETHERNET #ifdef TURN_ON_ETHERNET # define CONFIG_DRIVER_SMC91111 1 @@ -59,6 +58,12 @@ # undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ #endif +#define CONFIG_HARD_I2C 1 /* required for DA9030 access */ +#define CFG_I2C_SPEED 400000 /* I2C speed */ +#define CFG_I2C_SLAVE 1 /* I2C controllers address */ +#define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ +/* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ + /* * select serial console configuration */ @@ -73,8 +78,13 @@ #ifdef TURN_ON_ETHERNET # define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_PING) #else -# define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_ENV | CFG_CMD_NAND) \ - & ~(CFG_CMD_NET | CFG_CMD_FLASH | CFG_CMD_IMLS)) +# define CONFIG_COMMANDS ((CONFIG_CMD_DFL \ + | CFG_CMD_ENV \ + | CFG_CMD_NAND \ + | CFG_CMD_I2C) \ + & ~(CFG_CMD_NET \ + | CFG_CMD_FLASH \ + | CFG_CMD_IMLS)) #endif @@ -121,7 +131,7 @@ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ +#define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ #define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ /* valid baudrates */ diff --git a/include/da9030.h b/include/da9030.h new file mode 100644 index 00000000000..41108b9b36f --- /dev/null +++ b/include/da9030.h @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* DA9030 register definitions */ +#define CID 0x00 +#define EVENT_A 0x01 +#define EVENT_B 0x02 +#define EVENT_C 0x03 +#define STATUS 0x04 +#define IRQ_MASK_A 0x05 +#define IRQ_MASK_B 0x06 +#define IRQ_MASK_C 0x07 +#define SYS_CONTROL_A 0x08 +#define SYS_CONTROL_B 0x09 +#define FAULT_LOG 0x0A +#define LDO_10_11 0x10 +#define LDO_15 0x11 +#define LDO_14_16 0x12 +#define LDO_18_19 0x13 +#define LDO_17_SIMCP0 0x14 +#define BUCK2_DVC1 0x15 +#define BUCK2_DVC2 0x16 +#define REG_CONTROL_1_17 0x17 +#define REG_CONTROL_2_18 0x18 +#define USBPUMP 0x19 +#define SLEEP_CONTROL 0x1A +#define STARTUP_CONTROL 0x1B +#define LED1_CONTROL 0x20 +#define LED2_CONTROL 0x21 +#define LED3_CONTROL 0x22 +#define LED4_CONTROL 0x23 +#define LEDPC_CONTROL 0x24 +#define WLED_CONTROL 0x25 +#define MISC_CONTROLA 0x26 +#define MISC_CONTROLB 0x27 +#define CHARGE_CONTROL 0x28 +#define CCTR_CONTROL 0x29 +#define TCTR_CONTROL 0x2A +#define CHARGE_PULSE 0x2B + +/* ... some missing ...*/ + +#define LDO1 0x90 +#define LDO2_3 0x91 +#define LDO4_5 0x92 +#define LDO6_SIMCP 0x93 +#define LDO7_8 0x94 +#define LDO9_12 0x95 +#define BUCK 0x96 +#define REG_CONTROL_1_97 0x97 +#define REG_CONTROL_2_98 0x98 +#define REG_SLEEP_CONTROL1 0x99 +#define REG_SLEEP_CONTROL2 0x9A +#define REG_SLEEP_CONTROL3 0x9B +#define ADC_MAN_CONTROL 0xA0 +#define ADC_AUTO_CONTROL 0xA1 +#define VBATMON 0xA2 +#define VBATMONTXMON 0xA3 +#define TBATHIGHP 0xA4 +#define TBATHIGHN 0xA5 +#define TBATLOW 0xA6 +#define MAN_RES 0xB0 +#define VBAT_RES 0xB1 +#define VBATMIN_RES 0xB2 +#define VBATMINTXON_RES 0xB3 +#define ICHMAX_RES 0xB4 +#define ICHMIN_RES 0xB5 +#define ICHAVERAGE_RES 0xB6 +#define VCHMAX_RES 0xB7 +#define VCHMIN_RES 0xB8 +#define TBAT_RES 0xB9 +#define ADC_IN4_RES 0xBA + +#define STATUS_ONKEY_N 0x1 /* current ONKEY_N value */ +#define STATUS_PWREN1 (1<<1) /* PWREN1 value */ +#define STATUS_EXTON (1<<2) /* EXTON value */ +#define STATUS_CHDET (1<<3) /* Charger detection status */ +#define STATUS_TBAT (1<<4) /* Battery over/under temperature status */ +#define STATUS_VBATMON (1<<5) /* VBATMON comparison status */ +#define STATUS_VBATMONTXON (1<<6) /* VBATMONTXON comparison status */ +#define STATUS_CHIOVER (1<<7) /* Charge overcurrent */ + +#define SYS_CONTROL_A_SLEEP_N_PIN_ENABLE 0x1 +#define SYS_CONTROL_A_SHUT_DOWN (1<<1) +#define SYS_CONTROL_A_HWRES_ENABLE (1<<2) +#define SYS_CONTROL_A_WDOG_ACTION (1<<3) +#define SYS_CONTROL_A_WATCHDOG (1<<7) -- cgit v1.3.1 From 40b0bafbb282a8fd2d705be0623948ff551bf26a Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Fri, 24 Mar 2006 14:35:25 +0100 Subject: Added config options CFG_MONAHANS_RUN_MODE_OSC_RATIO and CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core frequency. --- cpu/pxa/start.S | 17 +++++++++++++++-- include/configs/delta.h | 8 +++++++- 2 files changed, 22 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/cpu/pxa/start.S b/cpu/pxa/start.S index 9541c9b2b9f..ffaa30fdc58 100644 --- a/cpu/pxa/start.S +++ b/cpu/pxa/start.S @@ -190,6 +190,14 @@ OSTIMER_BASE: .word 0x40a00000 #define OIER 0x1C /* Clock Manager Registers */ +#ifdef CONFIG_CPU_MONAHANS +# ifndef CFG_MONAHANS_RUN_MODE_OSC_RATIO +# error "You have to define CFG_MONAHANS_RUN_MODE_OSC_RATIO!!" +# endif +# ifndef CFG_MONAHANS_TURBO_RUN_MODE_RATIO +# define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 0x1 +# endif +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED CC_BASE: .word 0x41300000 #define CCCR 0x00 @@ -197,6 +205,7 @@ cpuspeed: .word CFG_CPUSPEED #else #error "You have to define CFG_CPUSPEED!!" #endif +#endif /* CONFIG_CPU_MONAHANS */ /* takes care the CP15 update has taken place */ .macro CPWAIT reg @@ -233,9 +242,13 @@ cpu_init_crit: str r2, [r1] #endif -#ifndef CONFIG_CPU_MONAHANS + /* set clock speed */ +#ifdef CONFIG_CPU_MONAHANS + ldr r0, =ACCR + ldr r1, =(((CFG_MONAHANS_TURBO_RUN_MODE_RATIO<<8) & ACCR_XN_MASK) | (CFG_MONAHANS_RUN_MODE_OSC_RATIO & ACCR_XL_MASK)) + str r1, [r0] +#else /* ! CONFIG_CPU_MONAHANS */ #ifdef CFG_CPUSPEED - /* set clock speed tbd@mk: required for monahans? */ ldr r0, CC_BASE ldr r1, cpuspeed str r1, [r0, #CCCR] diff --git a/include/configs/delta.h b/include/configs/delta.h index eaa4c432b8a..776ee15d1a7 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -132,7 +132,13 @@ #define CFG_LOAD_ADDR (CFG_DRAM_BASE + 0x8000) /* default load address */ #define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ + +/* Monahans Core Frequency = + * + */ +#define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ +#define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ + /* valid baudrates */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -- cgit v1.3.1 From c855ef6768cf9cb0bc12f4965592dcd5f353686a Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Mon, 27 Mar 2006 16:01:03 +0200 Subject: delta board: fix DA9030 reset procedure. --- board/delta/delta.c | 13 ++++++++++--- include/configs/delta.h | 5 ++--- 2 files changed, 12 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/board/delta/delta.c b/board/delta/delta.c index 6ef7e2fc26f..96928a53c3b 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -89,10 +89,17 @@ static void init_DA9030() GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ /* rising Edge on EXTON */ - GPIO17 = 0x8800; + GPIO17 = 0xc800; /* enable pullup */ + GPDR0 |= (1<<17); /* GPIO17 is output */ + GSDR0 = (1<<17); + GPCR0 = (1<<17); /* drive GPIO17 low */ udelay(5); - GPIO17 = 0xc800; - udelay(100000); /* wait for DA9030 */ + GPSR0 = (1<<17); /* drive GPIO17 high */ +#if CFG_DA9030_EXTON_DELAY + udelay((unsigned long) CFG_DA9030_EXTON_DELAY); /* wait for DA9030 */ +#endif + GPCR0 = (1<<17); /* drive GPIO17 low */ + GPIO17 = 0x8800; /* disable pullup */ /* reset the watchdog and go active (0xec) */ val = (SYS_CONTROL_A_HWRES_ENABLE | diff --git a/include/configs/delta.h b/include/configs/delta.h index 776ee15d1a7..6329c256b18 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -62,6 +62,7 @@ #define CFG_I2C_SPEED 400000 /* I2C speed */ #define CFG_I2C_SLAVE 1 /* I2C controllers address */ #define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ +#define CFG_DA9030_EXTON_DELAY 0 /* wait x us after DA9030 reset via EXTON */ /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ /* @@ -133,9 +134,7 @@ #define CFG_HZ 3250000 /* incrementer freq: 3.25 MHz */ -/* Monahans Core Frequency = - * - */ +/* Monahans Core Frequency */ #define CFG_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ #define CFG_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ -- cgit v1.3.1 From b66a9383421805c705654ce9456ec28c202819fb Mon Sep 17 00:00:00 2001 From: Rafal Jaworowski Date: Wed, 29 Mar 2006 13:17:09 +0200 Subject: Set SDelay register in the DDR controller for the MPC5200B chip. --- board/icecube/icecube.c | 21 +++++++++++++++++++++ cpu/mpc5xxx/cpu.c | 10 +++++----- include/configs/IceCube.h | 8 +++++--- include/mpc5xxx.h | 1 + 4 files changed, 32 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 44831c625a9..4197a7c5212 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -27,6 +27,7 @@ #include #include #include +#include #if defined(CONFIG_LITE5200B) #include "mt46v32m16.h" @@ -89,6 +90,8 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; + #ifndef CFG_RAMBOOT ulong test1, test2; @@ -183,6 +186,24 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && + (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 2d695d12eb1..8d1e7c63779 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -38,7 +38,7 @@ int checkcpu (void) ulong clock = gd->cpu_clk; char buf[32]; #ifndef CONFIG_MGT5100 - uint svr; + uint svr, pvr; #endif puts ("CPU: "); @@ -47,7 +47,8 @@ int checkcpu (void) puts (CPU_ID_STR); printf (" (JTAG ID %08lx)", *(vu_long *)MPC5XXX_CDM_JTAGID); #else - svr = get_svr (); + svr = get_svr(); + pvr = get_pvr(); switch (SVR_VER (svr)) { case SVR_MPC5200: printf ("MPC5200"); @@ -57,11 +58,10 @@ int checkcpu (void) break; } - printf (" v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr)); + printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), + PVR_MAJ(pvr), PVR_MIN(pvr)); #endif - printf (" at %s MHz\n", strmhz (buf, clock)); - return 0; } diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 596e52ce3c7..1152f838d98 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -56,7 +56,9 @@ * 0x40000000 - 0x4fffffff - PCI Memory * 0x50000000 - 0x50ffffff - PCI IO Space */ -#define CONFIG_PCI 1 +#define CONFIG_PCI + +#if defined(CONFIG_PCI) #define CONFIG_PCI_PNP 1 #define CONFIG_PCI_SCAN_SHOW 1 @@ -67,6 +69,8 @@ #define CONFIG_PCI_IO_BUS 0x50000000 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x01000000 +#define ADD_PCI_CMD CFG_CMD_PCI +#endif #define CFG_XLB_PIPELINING 1 @@ -76,8 +80,6 @@ #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define CONFIG_NS8382X 1 -#define ADD_PCI_CMD CFG_CMD_PCI - #else /* MPC5100 */ #define CONFIG_MII 1 diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index f33d8585522..50a6ac1e98d 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -131,6 +131,7 @@ #if defined(CONFIG_MGT5100) #define MPC5XXX_SDRAM_XLBSEL (MPC5XXX_SDRAM + 0x0010) #endif +#define MPC5XXX_SDRAM_SDELAY (MPC5XXX_SDRAM + 0x0090) /* Clock Distribution Module */ #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) -- cgit v1.3.1 From 89f2dfa4c349ae3b040779ac0ab1c9baa1ef025d Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Wed, 29 Mar 2006 17:49:27 +0200 Subject: delta board: minor update to DA9030 code. --- board/delta/delta.c | 6 ++++-- include/configs/delta.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/delta/delta.c b/board/delta/delta.c index 96928a53c3b..78d1f7f5390 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -106,8 +106,10 @@ static void init_DA9030() (0x6<<4) | SYS_CONTROL_A_WDOG_ACTION | SYS_CONTROL_A_WATCHDOG); - - i2c_reg_write(addr, SYS_CONTROL_A, val); + if(i2c_write(addr, SYS_CONTROL_A, 1, &val, 1)) { + printf("Error accessing DA9030 via i2c.\n"); + return; + } i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ diff --git a/include/configs/delta.h b/include/configs/delta.h index 6329c256b18..f2e0a8ce151 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -62,7 +62,7 @@ #define CFG_I2C_SPEED 400000 /* I2C speed */ #define CFG_I2C_SLAVE 1 /* I2C controllers address */ #define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ -#define CFG_DA9030_EXTON_DELAY 0 /* wait x us after DA9030 reset via EXTON */ +#define CFG_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */ /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ /* -- cgit v1.3.1 From eeaab720f66f0281b9a1ea3c1f8765bf34e4411e Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Wed, 29 Mar 2006 17:59:20 +0200 Subject: Change delta board memory map to start at 0x80000000. --- board/delta/config.mk | 2 +- include/configs/delta.h | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/delta/config.mk b/board/delta/config.mk index 9564625478e..c72e956524e 100644 --- a/board/delta/config.mk +++ b/board/delta/config.mk @@ -2,7 +2,7 @@ #TEXT_BASE = 0xa1700000 #TEXT_BASE = 0xa3080000 #TEXT_BASE = 0x9ffe0000 -TEXT_BASE = 0xa3008000 +TEXT_BASE = 0x83008000 # Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) BOARDLIBS = drivers/nand/libnand.a diff --git a/include/configs/delta.h b/include/configs/delta.h index f2e0a8ce151..053a8f726ce 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -125,8 +125,8 @@ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_DEVICE_NULLDEV 1 -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CFG_MEMTEST_START 0x80400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x80800000 /* 4 ... 8 MB in DRAM */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ @@ -159,16 +159,16 @@ * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1 0x80000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_2 0xa1000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2 0x81000000 /* SDRAM Bank #2 */ #define PHYS_SDRAM_2_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_3 0xa2000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3 0x82000000 /* SDRAM Bank #3 */ #define PHYS_SDRAM_3_SIZE 0x1000000 /* 64 MB */ -#define PHYS_SDRAM_4 0xa3000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4 0x83000000 /* SDRAM Bank #4 */ #define PHYS_SDRAM_4_SIZE 0x1000000 /* 64 MB */ -#define CFG_DRAM_BASE 0xa0000000 /* at CS0 */ +#define CFG_DRAM_BASE 0x80000000 /* at CS0 */ #define CFG_DRAM_SIZE 0x04000000 /* 64 MB Ram */ #undef CFG_SKIP_DRAM_SCRUB -- cgit v1.3.1 From f2841d377060cb2c3bedfcdfda6aab3066d6c4f1 Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Thu, 30 Mar 2006 13:40:55 +0200 Subject: Add support for ymodem protocol (loady command). Patch by Stefano Babic, 29 Mar 2006 --- common/Makefile | 2 +- common/cmd_load.c | 105 +++++++- common/crc16.c | 106 ++++++++ common/xyzModem.c | 739 +++++++++++++++++++++++++++++++++++++++++++++++++++++ include/crc.h | 101 ++++++++ include/xyzModem.h | 112 ++++++++ 6 files changed, 1151 insertions(+), 14 deletions(-) create mode 100644 common/crc16.c create mode 100644 common/xyzModem.c create mode 100644 include/crc.h create mode 100644 include/xyzModem.h (limited to 'include') diff --git a/common/Makefile b/common/Makefile index 7dbf84a555e..eb0b5dadfec 100644 --- a/common/Makefile +++ b/common/Makefile @@ -51,7 +51,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o \ memsize.o miiphybb.o miiphyutil.o \ s_record.o serial.o soft_i2c.o soft_spi.o spartan2.o spartan3.o \ usb.o usb_kbd.o usb_storage.o \ - virtex2.o xilinx.o + virtex2.o xilinx.o crc16.o xyzModem.o OBJS = $(AOBJS) $(COBJS) diff --git a/common/cmd_load.c b/common/cmd_load.c index 749849711a0..54460cdcc33 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -29,10 +29,11 @@ #include #include #include - +#include #if (CONFIG_COMMANDS & CFG_CMD_LOADS) static ulong load_serial (ulong offset); +static ulong load_serial_ymodem (ulong offset); static int read_record (char *buf, ulong len); # if (CONFIG_COMMANDS & CFG_CMD_SAVES) static int save_serial (ulong offset, ulong size); @@ -475,21 +476,31 @@ int do_load_serial_bin (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } } - printf ("## Ready for binary (kermit) download " - "to 0x%08lX at %d bps...\n", - offset, - load_baudrate); - addr = load_serial_bin (offset); + if (strcmp(argv[0],"loady")==0) { + printf ("## Ready for binary (ymodem) download " + "to 0x%08lX at %d bps...\n", + offset, + load_baudrate); + + addr = load_serial_ymodem (offset); - if (addr == ~0) { - load_addr = 0; - printf ("## Binary (kermit) download aborted\n"); - rcode = 1; } else { - printf ("## Start Addr = 0x%08lX\n", addr); - load_addr = addr; - } + printf ("## Ready for binary (kermit) download " + "to 0x%08lX at %d bps...\n", + offset, + load_baudrate); + addr = load_serial_bin (offset); + + if (addr == ~0) { + load_addr = 0; + printf ("## Binary (kermit) download aborted\n"); + rcode = 1; + } else { + printf ("## Start Addr = 0x%08lX\n", addr); + load_addr = addr; + } + } if (load_baudrate != current_baudrate) { printf ("## Switch baudrate to %d bps and press ESC ...\n", current_baudrate); @@ -963,6 +974,66 @@ START: } return ((ulong) os_data_addr - (ulong) bin_start_address); } + +static int getcxmodem(void) { + if (tstc()) + return (getc()); + return -1; +} +static ulong load_serial_ymodem (ulong offset) +{ + int size; + char buf[32]; + int err; + int res; + connection_info_t info; + char ymodemBuf[1024]; + ulong store_addr = ~0; + ulong addr = 0; + + size=0; + info.mode=xyzModem_ymodem; + res=xyzModem_stream_open(&info, &err); + if (!res) { + + while ((res=xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0 ){ + store_addr = addr + offset; + size+=res; + addr+=res; +#ifndef CFG_NO_FLASH + if (addr2info(store_addr)) { + int rc; + + rc = flash_write((char *)ymodemBuf,store_addr,res); + if (rc != 0) { + flash_perror (rc); + return (~0); + } + } else +#endif + { + memcpy ((char *)(store_addr), ymodemBuf, res); + } + + } + } + else { + printf ("%s\n",xyzModem_error(err)); + } + + xyzModem_stream_close(&err); + xyzModem_stream_terminate(false,&getcxmodem); + + + flush_cache (offset, size); + + printf("## Total Size = 0x%08x = %d Bytes\n", size, size); + sprintf(buf, "%X", size); + setenv("filesize", buf); + + return offset; +} + #endif /* CFG_CMD_LOADB */ /* -------------------------------------------------------------------- */ @@ -1022,6 +1093,14 @@ U_BOOT_CMD( " with offset 'off' and baudrate 'baud'\n" ); +U_BOOT_CMD( + loady, 3, 0, do_load_serial_bin, + "loady - load binary file over serial line (ymodem mode)\n", + "[ off ] [ baud ]\n" + " - load binary file over serial line" + " with offset 'off' and baudrate 'baud'\n" +); + #endif /* CFG_CMD_LOADB */ /* -------------------------------------------------------------------- */ diff --git a/common/crc16.c b/common/crc16.c new file mode 100644 index 00000000000..d5714051793 --- /dev/null +++ b/common/crc16.c @@ -0,0 +1,106 @@ +//========================================================================== +// +// crc16.c +// +// 16 bit CRC with polynomial x^16+x^12+x^5+1 +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas,asl +// Date: 2001-01-31 +// Purpose: +// Description: +// +// This code is part of eCos (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#include "crc.h" + +// Table of CRC constants - implements x^16+x^12+x^5+1 +static const uint16_t crc16_tab[] = { + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, +}; + +uint16_t +cyg_crc16(unsigned char *buf, int len) +{ + int i; + uint16_t cksum; + + cksum = 0; + for (i = 0; i < len; i++) { + cksum = crc16_tab[((cksum>>8) ^ *buf++) & 0xFF] ^ (cksum << 8); + } + return cksum; +} + diff --git a/common/xyzModem.c b/common/xyzModem.c new file mode 100644 index 00000000000..3c86b138b36 --- /dev/null +++ b/common/xyzModem.c @@ -0,0 +1,739 @@ +//========================================================================== +// +// xyzModem.c +// +// RedBoot stream handler for xyzModem protocol +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas, tsmith, Yoshinori Sato +// Date: 2000-07-14 +// Purpose: +// Description: +// +// This code is part of RedBoot (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== +#include +#include +#include +#include + +// Assumption - run xyzModem protocol over the console port + +// Values magic to the protocol +#define SOH 0x01 +#define STX 0x02 +#define EOT 0x04 +#define ACK 0x06 +#define BSP 0x08 +#define NAK 0x15 +#define CAN 0x18 +#define EOF 0x1A // ^Z for DOS officionados + +#define USE_YMODEM_LENGTH + +// Data & state local to the protocol +static struct { +#ifdef REDBOOT + hal_virtual_comm_table_t* __chan; +#else + int *__chan; +#endif + unsigned char pkt[1024], *bufp; + unsigned char blk,cblk,crc1,crc2; + unsigned char next_blk; // Expected block + int len, mode, total_retries; + int total_SOH, total_STX, total_CAN; + bool crc_mode, at_eof, tx_ack; +#ifdef USE_YMODEM_LENGTH + unsigned long file_length, read_length; +#endif +} xyz; + +#define xyzModem_CHAR_TIMEOUT 2000 // 2 seconds +#define xyzModem_MAX_RETRIES 20 +#define xyzModem_MAX_RETRIES_WITH_CRC 10 +#define xyzModem_CAN_COUNT 3 // Wait for 3 CAN before quitting + + +#ifndef REDBOOT //SB +typedef int cyg_int32; +int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) { +#define DELAY 20 + unsigned long counter=0; + while (!tstc() && (counter < xyzModem_CHAR_TIMEOUT*1000/DELAY)) { + udelay(DELAY); + counter++; + } + if (tstc()) { + *c=getc(); + return 1; + } + return 0; +} + +void CYGACC_COMM_IF_PUTC(char x,char y) { + putc(y); +} + +// Validate a hex character +__inline__ static bool +_is_hex(char c) +{ + return (((c >= '0') && (c <= '9')) || + ((c >= 'A') && (c <= 'F')) || + ((c >= 'a') && (c <= 'f'))); +} + +// Convert a single hex nibble +__inline__ static int +_from_hex(char c) +{ + int ret = 0; + + if ((c >= '0') && (c <= '9')) { + ret = (c - '0'); + } else if ((c >= 'a') && (c <= 'f')) { + ret = (c - 'a' + 0x0a); + } else if ((c >= 'A') && (c <= 'F')) { + ret = (c - 'A' + 0x0A); + } + return ret; +} + +// Convert a character to lower case +__inline__ static char +_tolower(char c) +{ + if ((c >= 'A') && (c <= 'Z')) { + c = (c - 'A') + 'a'; + } + return c; +} + + + +// +// Parse (scan) a number +// +bool +parse_num(char *s, unsigned long *val, char **es, char *delim) +{ + bool first = true; + int radix = 10; + char c; + unsigned long result = 0; + int digit; + + while (*s == ' ') s++; + while (*s) { + if (first && (s[0] == '0') && (_tolower(s[1]) == 'x')) { + radix = 16; + s += 2; + } + first = false; + c = *s++; + if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) { + // Valid digit +#ifdef CYGPKG_HAL_MIPS + // FIXME: tx49 compiler generates 0x2539018 for MUL which + // isn't any good. + if (16 == radix) + result = result << 4; + else + result = 10 * result; + result += digit; +#else + result = (result * radix) + digit; +#endif + } else { + if (delim != (char *)0) { + // See if this character is one of the delimiters + char *dp = delim; + while (*dp && (c != *dp)) dp++; + if (*dp) break; // Found a good delimiter + } + return false; // Malformatted number + } + } + *val = result; + if (es != (char **)0) { + *es = s; + } + return true; +} + +#endif + +#define USE_SPRINTF +#ifdef DEBUG +#ifndef USE_SPRINTF +// +// Note: this debug setup only works if the target platform has two serial ports +// available so that the other one (currently only port 1) can be used for debug +// messages. +// +static int +zm_dprintf(char *fmt, ...) +{ + int cur_console; + va_list args; + + va_start(args, fmt); +#ifdef REDBOOT + cur_console = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + CYGACC_CALL_IF_SET_CONSOLE_COMM(1); +#endif + diag_vprintf(fmt, args); +#ifdef REDBOOT + CYGACC_CALL_IF_SET_CONSOLE_COMM(cur_console); +#endif +} + +static void +zm_flush(void) +{ +} + +#else +// +// Note: this debug setup works by storing the strings in a fixed buffer +// +#define FINAL +#ifdef FINAL +static char *zm_out = (char *)0x00380000; +static char *zm_out_start = (char *)0x00380000; +#else +static char zm_buf[8192]; +static char *zm_out=zm_buf; +static char *zm_out_start = zm_buf; + +#endif +static int +zm_dprintf(char *fmt, ...) +{ + int len; + va_list args; + + va_start(args, fmt); + len = diag_vsprintf(zm_out, fmt, args); + zm_out += len; + return len; +} + +static void +zm_flush(void) +{ + char *p = zm_out_start; +#ifdef REDBOOT + while (*p) mon_write_char(*p++); +#endif + zm_out = zm_out_start; +} +#endif + +static void +zm_dump_buf(void *buf, int len) +{ +#ifdef REDBOOT + diag_vdump_buf_with_offset(zm_dprintf, buf, len, 0); +#else + +#endif +} + +static unsigned char zm_buf[2048]; +static unsigned char *zm_bp; + +static void +zm_new(void) +{ + zm_bp = zm_buf; +} + +static void +zm_save(unsigned char c) +{ + *zm_bp++ = c; +} + +static void +zm_dump(int line) +{ + zm_dprintf("Packet at line: %d\n", line); + zm_dump_buf(zm_buf, zm_bp-zm_buf); +} + +#define ZM_DEBUG(x) x +#else +#define ZM_DEBUG(x) +#endif + +// Wait for the line to go idle +static void +xyzModem_flush(void) +{ + int res; + char c; + while (true) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + if (!res) return; + } +} + +static int +xyzModem_get_hdr(void) +{ + char c; + int res; + bool hdr_found = false; + int i, can_total, hdr_chars; + unsigned short cksum; + + ZM_DEBUG(zm_new()); + // Find the start of a header + can_total = 0; + hdr_chars = 0; + + if (xyz.tx_ack) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + xyz.tx_ack = false; + } + while (!hdr_found) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + hdr_chars++; + switch (c) { + case SOH: + xyz.total_SOH++; + case STX: + if (c == STX) xyz.total_STX++; + hdr_found = true; + break; + case CAN: + xyz.total_CAN++; + ZM_DEBUG(zm_dump(__LINE__)); + if (++can_total == xyzModem_CAN_COUNT) { + return xyzModem_cancel; + } else { + // Wait for multiple CAN to avoid early quits + break; + } + case EOT: + // EOT only supported if no noise + if (hdr_chars == 1) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__)); + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_eof; + } + default: + // Ignore, waiting for start of header + ; + } + } else { + // Data stream timed out + xyzModem_flush(); // Toss any current input + ZM_DEBUG(zm_dump(__LINE__)); + CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); + return xyzModem_timeout; + } + } + + // Header found, now read the data + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.blk); + ZM_DEBUG(zm_save(xyz.blk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.cblk); + ZM_DEBUG(zm_save(xyz.cblk)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + xyz.len = (c == SOH) ? 128 : 1024; + xyz.bufp = xyz.pkt; + for (i = 0; i < xyz.len; i++) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &c); + ZM_DEBUG(zm_save(c)); + if (res) { + xyz.pkt[i] = c; + } else { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + } + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.crc1); + ZM_DEBUG(zm_save(xyz.crc1)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + if (xyz.crc_mode) { + res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.crc2); + ZM_DEBUG(zm_save(xyz.crc2)); + if (!res) { + ZM_DEBUG(zm_dump(__LINE__)); + return xyzModem_timeout; + } + } + ZM_DEBUG(zm_dump(__LINE__)); + // Validate the message + if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) { + ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk))); + ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len)); + xyzModem_flush(); + return xyzModem_frame; + } + // Verify checksum/CRC + if (xyz.crc_mode) { + cksum = cyg_crc16(xyz.pkt, xyz.len); + if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) { + ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n", + xyz.crc1, xyz.crc2, cksum & 0xFFFF)); + return xyzModem_cksum; + } + } else { + cksum = 0; + for (i = 0; i < xyz.len; i++) { + cksum += xyz.pkt[i]; + } + if (xyz.crc1 != (cksum & 0xFF)) { + ZM_DEBUG(zm_dprintf("Checksum error - recvd: %x, computed: %x\n", xyz.crc1, cksum & 0xFF)); + return xyzModem_cksum; + } + } + // If we get here, the message passes [structural] muster + return 0; +} + +int +xyzModem_stream_open(connection_info_t *info, int *err) +{ + int console_chan, stat=0; + int retries = xyzModem_MAX_RETRIES; + int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; + +// ZM_DEBUG(zm_out = zm_out_start); +#ifdef xyzModem_zmodem + if (info->mode == xyzModem_zmodem) { + *err = xyzModem_noZmodem; + return -1; + } +#endif + +#ifdef REDBOOT + // Set up the I/O channel. Note: this allows for using a different port in the future + console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); + if (info->chan >= 0) { + CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan); + } else { + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); + } + xyz.__chan = CYGACC_CALL_IF_CONSOLE_PROCS(); + + CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); + CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT); +#else +// TODO: CHECK ! + int dummy; + xyz.__chan=&dummy; +#endif + xyz.len = 0; + xyz.crc_mode = true; + xyz.at_eof = false; + xyz.tx_ack = false; + xyz.mode = info->mode; + xyz.total_retries = 0; + xyz.total_SOH = 0; + xyz.total_STX = 0; + xyz.total_CAN = 0; +#ifdef USE_YMODEM_LENGTH + xyz.read_length = 0; + xyz.file_length = 0; +#endif + + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + + if (xyz.mode == xyzModem_xmodem) { + // X-modem doesn't have an information header - exit here + xyz.next_blk = 1; + return 0; + } + + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + // Y-modem file information header + if (xyz.blk == 0) { +#ifdef USE_YMODEM_LENGTH + // skip filename + while (*xyz.bufp++); + // get the length + parse_num(xyz.bufp, &xyz.file_length, NULL, " "); +#endif + // The rest of the file name data block quietly discarded + xyz.tx_ack = true; + } + xyz.next_blk = 1; + xyz.len = 0; + return 0; + } else + if (stat == xyzModem_timeout) { + if (--crc_retries <= 0) xyz.crc_mode = false; + CYGACC_CALL_IF_DELAY_US(5*100000); // Extra delay for startup + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat == xyzModem_cancel) { + break; + } + } + *err = stat; + ZM_DEBUG(zm_flush()); + return -1; +} + +int +xyzModem_stream_read(char *buf, int size, int *err) +{ + int stat, total, len; + int retries; + + total = 0; + stat = xyzModem_cancel; + // Try and get 'size' bytes into the buffer + while (!xyz.at_eof && (size > 0)) { + if (xyz.len == 0) { + retries = xyzModem_MAX_RETRIES; + while (retries-- > 0) { + stat = xyzModem_get_hdr(); + if (stat == 0) { + if (xyz.blk == xyz.next_blk) { + xyz.tx_ack = true; + ZM_DEBUG(zm_dprintf("ACK block %d (%d)\n", xyz.blk, __LINE__)); + xyz.next_blk = (xyz.next_blk + 1) & 0xFF; + +#if defined(xyzModem_zmodem) || defined(USE_YMODEM_LENGTH) + if (xyz.mode == xyzModem_xmodem || xyz.file_length == 0) { +#else + if (1) { +#endif + // Data blocks can be padded with ^Z (EOF) characters + // This code tries to detect and remove them + if ((xyz.bufp[xyz.len-1] == EOF) && + (xyz.bufp[xyz.len-2] == EOF) && + (xyz.bufp[xyz.len-3] == EOF)) { + while (xyz.len && (xyz.bufp[xyz.len-1] == EOF)) { + xyz.len--; + } + } + } + +#ifdef USE_YMODEM_LENGTH + // See if accumulated length exceeds that of the file. + // If so, reduce size (i.e., cut out pad bytes) + // Only do this for Y-modem (and Z-modem should it ever + // be supported since it can fall back to Y-modem mode). + if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) { + xyz.read_length += xyz.len; + if (xyz.read_length > xyz.file_length) { + xyz.len -= (xyz.read_length - xyz.file_length); + } + } +#endif + break; + } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) { + // Just re-ACK this so sender will get on with it + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + continue; // Need new header + } else { + stat = xyzModem_sequence; + } + } + if (stat == xyzModem_cancel) { + break; + } + if (stat == xyzModem_eof) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("ACK (%d)\n", __LINE__)); + if (xyz.mode == xyzModem_ymodem) { + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("Reading Final Header\n")); + stat = xyzModem_get_hdr(); + CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); + ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__)); + } + xyz.at_eof = true; + break; + } + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); + xyz.total_retries++; + ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); + } + if (stat < 0) { + *err = stat; + xyz.len = -1; + return total; + } + } + // Don't "read" data from the EOF protocol package + if (!xyz.at_eof) { + len = xyz.len; + if (size < len) len = size; + memcpy(buf, xyz.bufp, len); + size -= len; + buf += len; + total += len; + xyz.len -= len; + xyz.bufp += len; + } + } + return total; +} + +void +xyzModem_stream_close(int *err) +{ + diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", + xyz.crc_mode ? "CRC" : "Cksum", + xyz.total_SOH, xyz.total_STX, xyz.total_CAN, + xyz.total_retries); + ZM_DEBUG(zm_flush()); +} + +// Need to be able to clean out the input buffer, so have to take the +// getc +void xyzModem_stream_terminate(bool abort, int (*getc)(void)) +{ + int c; + + if (abort) { + ZM_DEBUG(zm_dprintf("!!!! TRANSFER ABORT !!!!\n")); + switch (xyz.mode) { + case xyzModem_xmodem: + case xyzModem_ymodem: + // The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal + // number of Backspaces is a friendly way to get the other end to abort. + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); + // Now consume the rest of what's waiting on the line. + ZM_DEBUG(zm_dprintf("Flushing serial line.\n")); + xyzModem_flush(); + xyz.at_eof = true; + break; +#ifdef xyzModem_zmodem + case xyzModem_zmodem: + // Might support it some day I suppose. +#endif + break; + } + } else { + ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n")); + // Consume any trailing crap left in the inbuffer from + // previous recieved blocks. Since very few files are an exact multiple + // of the transfer block size, there will almost always be some gunk here. + // If we don't eat it now, RedBoot will think the user typed it. + ZM_DEBUG(zm_dprintf("Trailing gunk:\n")); + while ((c = (*getc)()) > -1) ; + ZM_DEBUG(zm_dprintf("\n")); + // Make a small delay to give terminal programs like minicom + // time to get control again after their file transfer program + // exits. + CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); + } +} + +char * +xyzModem_error(int err) +{ + switch (err) { + case xyzModem_access: + return "Can't access file"; + break; + case xyzModem_noZmodem: + return "Sorry, zModem not available yet"; + break; + case xyzModem_timeout: + return "Timed out"; + break; + case xyzModem_eof: + return "End of file"; + break; + case xyzModem_cancel: + return "Cancelled"; + break; + case xyzModem_frame: + return "Invalid framing"; + break; + case xyzModem_cksum: + return "CRC/checksum error"; + break; + case xyzModem_sequence: + return "Block sequence error"; + break; + default: + return "Unknown error"; + break; + } +} + +// +// RedBoot interface +// +#if 0 // SB +GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close, + xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error); +RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem); +RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem); +#endif diff --git a/include/crc.h b/include/crc.h new file mode 100644 index 00000000000..63399bf8f6e --- /dev/null +++ b/include/crc.h @@ -0,0 +1,101 @@ +//========================================================================== +// +// crc.h +// +// Interface for the CRC algorithms. +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 2002 Andrew Lunn +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): Andrew Lunn +// Contributors: Andrew Lunn +// Date: 2002-08-06 +// Purpose: +// Description: +// +// This code is part of eCos (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef _SERVICES_CRC_CRC_H_ +#define _SERVICES_CRC_CRC_H_ + +#include + +#ifndef __externC +# ifdef __cplusplus +# define __externC extern "C" +# else +# define __externC extern +# endif +#endif + +// Compute a CRC, using the POSIX 1003 definition +extern uint32_t +cyg_posix_crc32(unsigned char *s, int len); + +// Gary S. Brown's 32 bit CRC + +extern uint32_t +cyg_crc32(unsigned char *s, int len); + +// Gary S. Brown's 32 bit CRC, but accumulate the result from a +// previous CRC calculation + +extern uint32_t +cyg_crc32_accumulate(uint32_t crc, unsigned char *s, int len); + +// Ethernet FCS Algorithm + +extern uint32_t +cyg_ether_crc32(unsigned char *s, int len); + +// Ethernet FCS algorithm, but accumulate the result from a previous +// CRC calculation. + +extern uint32_t +cyg_ether_crc32_accumulate(uint32_t crc, unsigned char *s, int len); + +// 16 bit CRC with polynomial x^16+x^12+x^5+1 + +extern uint16_t cyg_crc16(unsigned char *s, int len); + +#endif // _SERVICES_CRC_CRC_H_ + + + diff --git a/include/xyzModem.h b/include/xyzModem.h new file mode 100644 index 00000000000..a62a174b378 --- /dev/null +++ b/include/xyzModem.h @@ -0,0 +1,112 @@ +//========================================================================== +// +// xyzModem.h +// +// RedBoot stream handler for xyzModem protocol +// +//========================================================================== +//####ECOSGPLCOPYRIGHTBEGIN#### +// ------------------------------------------- +// This file is part of eCos, the Embedded Configurable Operating System. +// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. +// Copyright (C) 2002 Gary Thomas +// +// eCos is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free +// Software Foundation; either version 2 or (at your option) any later version. +// +// eCos is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or +// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +// for more details. +// +// You should have received a copy of the GNU General Public License along +// with eCos; if not, write to the Free Software Foundation, Inc., +// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. +// +// As a special exception, if other files instantiate templates or use macros +// or inline functions from this file, or you compile this file and link it +// with other works to produce a work based on this file, this file does not +// by itself cause the resulting work to be covered by the GNU General Public +// License. However the source code for this file must still be made available +// in accordance with section (3) of the GNU General Public License. +// +// This exception does not invalidate any other reasons why a work based on +// this file might be covered by the GNU General Public License. +// +// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. +// at http://sources.redhat.com/ecos/ecos-license/ +// ------------------------------------------- +//####ECOSGPLCOPYRIGHTEND#### +//========================================================================== +//#####DESCRIPTIONBEGIN#### +// +// Author(s): gthomas +// Contributors: gthomas +// Date: 2000-07-14 +// Purpose: +// Description: +// +// This code is part of RedBoot (tm). +// +//####DESCRIPTIONEND#### +// +//========================================================================== + +#ifndef _XYZMODEM_H_ +#define _XYZMODEM_H_ + +#define xyzModem_xmodem 1 +#define xyzModem_ymodem 2 +// Don't define this until the protocol support is in place +//#define xyzModem_zmodem 3 + +#define xyzModem_access -1 +#define xyzModem_noZmodem -2 +#define xyzModem_timeout -3 +#define xyzModem_eof -4 +#define xyzModem_cancel -5 +#define xyzModem_frame -6 +#define xyzModem_cksum -7 +#define xyzModem_sequence -8 + +#define xyzModem_close 1 +#define xyzModem_abort 2 + + +#ifdef REDBOOT +extern getc_io_funcs_t xyzModem_io; +#else +#define CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT +#define CYGACC_CALL_IF_SET_CONSOLE_COMM(x) + +#define diag_vprintf vprintf +#define diag_printf printf +#define diag_vsprintf vsprintf + +#define CYGACC_CALL_IF_DELAY_US(x) udelay(x) + +typedef struct { + char *filename; + int mode; + int chan; +#ifdef CYGPKG_REDBOOT_NETWORKING + struct sockaddr_in *server; +#endif +} connection_info_t; + +typedef unsigned int bool; + +#define false 0 +#define true 1 + +#endif + + +int xyzModem_stream_open(connection_info_t *info, int *err); +void xyzModem_stream_close(int *err); +void xyzModem_stream_terminate(bool method, int (*getc)(void)); +int xyzModem_stream_read(char *buf, int size, int *err); +char *xyzModem_error(int err); + +#endif // _XYZMODEM_H_ -- cgit v1.3.1 From 9e7b5ce61b2641e726a38505ffc077642bff44fa Mon Sep 17 00:00:00 2001 From: Markus Klotzbuecher Date: Thu, 30 Mar 2006 17:00:39 +0200 Subject: delta board: one more DA9030 fix. --- board/delta/delta.c | 29 ++++++++++++++++++----------- include/configs/delta.h | 1 + 2 files changed, 19 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/board/delta/delta.c b/board/delta/delta.c index 78d1f7f5390..d00d72d8db4 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -79,27 +79,34 @@ int dram_init (void) return 0; } -/* initialize the DA9030 Power Controller */ -static void init_DA9030() +void i2c_init_board() { - uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + CKENB |= (CKENB_4_I2C); /* setup I2C GPIO's */ GPIO32 = 0x801; /* SCL = Alt. Fkt. 1 */ GPIO33 = 0x801; /* SDA = Alt. Fkt. 1 */ +} - /* rising Edge on EXTON */ - GPIO17 = 0xc800; /* enable pullup */ +/* initialize the DA9030 Power Controller */ +static void init_DA9030() +{ + uchar addr = (uchar) DA9030_I2C_ADDR, val = 0; + + CKENB |= CKENB_7_GPIO; + udelay(100); + + /* Rising Edge on EXTON to reset DA9030 */ + GPIO17 = 0x8800; /* configure GPIO17, no pullup, -down */ GPDR0 |= (1<<17); /* GPIO17 is output */ GSDR0 = (1<<17); GPCR0 = (1<<17); /* drive GPIO17 low */ - udelay(5); GPSR0 = (1<<17); /* drive GPIO17 high */ + #if CFG_DA9030_EXTON_DELAY udelay((unsigned long) CFG_DA9030_EXTON_DELAY); /* wait for DA9030 */ #endif GPCR0 = (1<<17); /* drive GPIO17 low */ - GPIO17 = 0x8800; /* disable pullup */ /* reset the watchdog and go active (0xec) */ val = (SYS_CONTROL_A_HWRES_ENABLE | @@ -114,14 +121,14 @@ static void init_DA9030() i2c_reg_write(addr, REG_CONTROL_1_97, 0xfd); /* disable LDO1, enable LDO6 */ i2c_reg_write(addr, LDO2_3, 0xd1); /* LDO2 =1,9V, LDO3=3,1V */ i2c_reg_write(addr, LDO4_5, 0xcc); /* LDO2 =1,9V, LDO3=3,1V */ - i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */ + i2c_reg_write(addr, LDO6_SIMCP, 0x3e); /* LDO6=3,2V, SIMCP = 5V support */ i2c_reg_write(addr, LDO7_8, 0xc9); /* LDO7=2,7V, LDO8=3,0V */ i2c_reg_write(addr, LDO9_12, 0xec); /* LDO9=3,0V, LDO12=3,2V */ - i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */ + i2c_reg_write(addr, BUCK, 0x0c); /* Buck=1.2V */ i2c_reg_write(addr, REG_CONTROL_2_98, 0x7f); /* All LDO'S on 8,9,10,11,12,14 */ - i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */ + i2c_reg_write(addr, LDO_10_11, 0xcc); /* LDO10=3.0V LDO11=3.0V */ i2c_reg_write(addr, LDO_15, 0xae); /* LDO15=1.8V, dislock first 3bit */ - i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */ + i2c_reg_write(addr, LDO_14_16, 0x05); /* LDO14=2.8V, LDO16=NB */ i2c_reg_write(addr, LDO_18_19, 0x9c); /* LDO18=3.0V, LDO19=2.7V */ i2c_reg_write(addr, LDO_17_SIMCP0, 0x2c); /* LDO17=3.0V, SIMCP=3V support */ i2c_reg_write(addr, BUCK2_DVC1, 0x9a); /* Buck2=1.5V plus Update support of 520 MHz */ diff --git a/include/configs/delta.h b/include/configs/delta.h index 053a8f726ce..5edea95a4f3 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -63,6 +63,7 @@ #define CFG_I2C_SLAVE 1 /* I2C controllers address */ #define DA9030_I2C_ADDR 0x49 /* I2C address of DA9030 */ #define CFG_DA9030_EXTON_DELAY 100000 /* wait x us after DA9030 reset via EXTON */ +#define CFG_I2C_INIT_BOARD 1 /* #define CONFIG_HW_WATCHDOG 1 /\* Required for hitting the DA9030 WD *\/ */ /* -- cgit v1.3.1 From 62534beb2fdd67490c3723f22b8982e7d64fc104 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Fri, 17 Mar 2006 10:28:24 +0100 Subject: Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006 --- CHANGELOG | 18 +++ cpu/ppc4xx/sdram.c | 298 ++++++++++++++++++++++++++++++++++----- cpu/ppc4xx/sdram.h | 78 ++++++++++ include/configs/PPChameleonEVB.h | 10 ++ include/configs/p3p440.h | 12 +- 5 files changed, 378 insertions(+), 38 deletions(-) create mode 100644 cpu/ppc4xx/sdram.h (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 34b8d20ebb6..16b50e96f92 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -33,6 +33,24 @@ Changes since U-Boot 1.1.4: * Add support for Lite5200B board. Patch by Patch by Jose Maria (Txema) Lopez, 16 Jan 2006 +* Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) + + 405 SDRAM: - The SDRAM parameters can now be defined in the board + config file and the 405 SDRAM controller values will + be calculated upon bootup (see PPChameleonEVB). + When those settings are not defined in the board + config file, the register setup will be as it is now, + so this implementation should not break any current + design using this code. + + Thanks to Andrea Marson from DAVE for this patch. + + 440 DDR: - Added function sdram_tr1_set to auto calculate the + TR1 value for the DDR. + - Added ECC support (see p3p440). + + Patch by Stefan Roese, 17 Mar 2006 + * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer and cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index e9548cdcf3d..c5ab01738c5 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -1,7 +1,10 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * + * (C) Copyright 2006 + * DAVE Srl + * * (C) Copyright 2002-2004 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com * @@ -27,28 +30,19 @@ #include #include #include +#include "sdram.h" #ifdef CONFIG_SDRAM_BANK0 -#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - - -struct sdram_conf_s { - unsigned long size; - unsigned long reg; -}; - -typedef struct sdram_conf_s sdram_conf_t; - #ifndef CFG_SDRAM_TABLE sdram_conf_t mb0cf[] = { - {(128 << 20), 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ - {(64 << 20), 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ - {(32 << 20), 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ - {(16 << 20), 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ - {(4 << 20), 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ + {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ + {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ + {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ + {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ + {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ }; #else sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; @@ -59,31 +53,138 @@ sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; #ifndef CONFIG_440 +#ifdef CFG_SDRAM_CASL +static ulong ns2clks(ulong ns) +{ + ulong bus_period_x_10 = ONE_BILLION / (get_bus_freq(0) / 10); + + return ((ns * 10) + bus_period_x_10) / bus_period_x_10; +} +#endif /* CFG_SDRAM_CASL */ + +static ulong compute_sdtr1(ulong speed) +{ +#ifdef CFG_SDRAM_CASL + ulong tmp; + ulong sdtr1 = 0; + + /* CASL */ + if (CFG_SDRAM_CASL < 2) + sdtr1 |= (1 << SDRAM0_TR_CASL); + else + if (CFG_SDRAM_CASL > 4) + sdtr1 |= (3 << SDRAM0_TR_CASL); + else + sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); + + /* PTA */ + tmp = ns2clks(CFG_SDRAM_PTA); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); + else + sdtr1 |= ((4-1) << SDRAM0_TR_PTA); + + /* CTP */ + tmp = ns2clks(CFG_SDRAM_CTP); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); + else + sdtr1 |= ((4-1) << SDRAM0_TR_CTP); + + /* LDF */ + tmp = ns2clks(CFG_SDRAM_LDF); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); + else + sdtr1 |= ((2-1) << SDRAM0_TR_LDF); + + /* RFTA */ + tmp = ns2clks(CFG_SDRAM_RFTA); + if ((tmp >= 4) && (tmp <= 10)) + sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); + else + sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); + + /* RCD */ + tmp = ns2clks(CFG_SDRAM_RCD); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); + else + sdtr1 |= ((4-1) << SDRAM0_TR_RCD); + + return sdtr1; +#else /* CFG_SDRAM_CASL */ + /* + * If no values are configured in the board config file + * use the default values, which seem to be ok for most + * boards. + * + * REMARK: + * For new board ports we strongly recommend to define the + * correct values for the used SDRAM chips in your board + * config file (see PPChameleonEVB.h) + */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ + return 0x01074015; + } else { + /* + * default: 100 MHz SDRAM + */ + return 0x0086400d; + } +#endif /* CFG_SDRAM_CASL */ +} + +/* refresh is expressed in ms */ +static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) +{ +#ifdef CFG_SDRAM_CASL + ulong tmp; + + tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); + tmp /= 1000000; + + return ((tmp & 0x00003FF8) << 16); +#else /* CFG_SDRAM_CASL */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ + return 0x07f00000; + } else { + /* + * default: 100 MHz SDRAM + */ + return 0x05f00000; + } +#endif /* CFG_SDRAM_CASL */ +} + /* * Autodetect onboard SDRAM on 405 platforms */ void sdram_init(void) { + ulong speed; ulong sdtr1; - ulong rtr; int i; - /* - * Support for 100MHz and 133MHz SDRAM - */ - if (get_bus_freq(0) > 100000000) { - /* - * 133 MHz SDRAM - */ - sdtr1 = 0x01074015; - rtr = 0x07f00000; - } else { - /* - * default: 100 MHz SDRAM - */ - sdtr1 = 0x0086400d; - rtr = 0x05f00000; - } + /* + * Determine SDRAM speed + */ + speed = get_bus_freq(0); /* parameter not used on ppc4xx */ + + /* + * sdtr1 (register SDRAM0_TR) must take into account timings listed + * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into + * account actual SDRAM size. So we can set up sdtr1 according to what + * is specified in board configuration file while rtr dependds on SDRAM + * size we are assuming before detection. + */ + sdtr1 = compute_sdtr1(speed); for (i=0; i all done */ diff --git a/cpu/ppc4xx/sdram.h b/cpu/ppc4xx/sdram.h new file mode 100644 index 00000000000..62b5442f3ba --- /dev/null +++ b/cpu/ppc4xx/sdram.h @@ -0,0 +1,78 @@ +/* + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * (C) Copyright 2006 + * DAVE Srl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SDRAM_H_ +#define _SDRAM_H_ + +#include + +#define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) + +#define ONE_BILLION 1000000000 + +struct sdram_conf_s { + unsigned long size; + int rows; + unsigned long reg; +}; + +typedef struct sdram_conf_s sdram_conf_t; + +/* Bitfields offsets */ +#define SDRAM0_TR_CASL (31 - 8) +#define SDRAM0_TR_PTA (31 - 13) +#define SDRAM0_TR_CTP (31 - 15) +#define SDRAM0_TR_LDF (31 - 17) +#define SDRAM0_TR_RFTA (31 - 29) +#define SDRAM0_TR_RCD (31 - 31) + +#ifdef CFG_SDRAM_CL +/* SDRAM timings [ns] according to AMCC/IBM names (see SDRAM_faq.doc) */ +#define CFG_SDRAM_CASL CFG_SDRAM_CL +#define CFG_SDRAM_PTA CFG_SDRAM_tRP +#define CFG_SDRAM_CTP (CFG_SDRAM_tRC - CFG_SDRAM_tRCD - CFG_SDRAM_tRP) +#define CFG_SDRAM_LDF 0 +#ifdef CFG_SDRAM_tRFC +#define CFG_SDRAM_RFTA CFG_SDRAM_tRFC +#else +#define CFG_SDRAM_RFTA CFG_SDRAM_tRC +#endif +#define CFG_SDRAM_RCD CFG_SDRAM_tRCD +#endif /* #ifdef CFG_SDRAM_CL */ + +/* + * Some defines for the 440 DDR controller + */ +#define SDRAM_CFG0_DC_EN 0x80000000 /* SDRAM Controller Enable */ +#define SDRAM_CFG0_MEMCHK 0x30000000 /* Memory data error checking mask*/ +#define SDRAM_CFG0_MEMCHK_NON 0x00000000 /* No ECC generation */ +#define SDRAM_CFG0_MEMCHK_GEN 0x20000000 /* ECC generation */ +#define SDRAM_CFG0_MEMCHK_CHK 0x30000000 /* ECC generation and checking */ +#define SDRAM_CFG0_DRAMWDTH 0x02000000 /* DRAM width mask */ +#define SDRAM_CFG0_DRAMWDTH_32 0x00000000 /* 32 bits */ +#define SDRAM_CFG0_DRAMWDTH_64 0x02000000 /* 64 bits */ + +#endif diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index e1155e2e438..16e2cc6d648 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -139,8 +139,18 @@ #define CFG_I2C_RTC_ADDR 0x68 #define CFG_M41T11_BASE_YEAR 1900 +/* + * SDRAM configuration (please see cpu/ppc/sdram.[ch]) + */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ +/* SDRAM timings used in datasheet */ +#define CFG_SDRAM_CL 2 +#define CFG_SDRAM_tRP 20 +#define CFG_SDRAM_tRC 65 +#define CFG_SDRAM_tRCD 20 +#undef CFG_SDRAM_tRFC + /* * Miscellaneous configurable options */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 831d018e2d4..0662544aed2 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005 + * (C) Copyright 2005-2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2002 Scott McNutt @@ -71,9 +71,10 @@ * DDR SDRAM *----------------------------------------------------------------------*/ #define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0*/ -#define CFG_SDRAM_TABLE { \ - {(256 << 20), 0x000C4001}, /* 256MB mode 3, 13x10(4) */ \ - {(64 << 20), 0x00082001}} /* 64MB mode 2, 12x9(4) */ +#define CONFIG_SDRAM_ECC /* enable ECC support */ +#define CFG_SDRAM_TABLE { \ + {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \ + {(64 << 20), 12, 0x00082001}} /* 64MB mode 2, 12x9(4) */ /*----------------------------------------------------------------------- * Serial Port @@ -275,6 +276,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +#define CFG_FLASH_PROTECTION 1 /* hardware flash protection */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ -- cgit v1.3.1 From 2662b40cace272da5759040622561d821c878d56 Mon Sep 17 00:00:00 2001 From: Stefan Roese Date: Sat, 1 Apr 2006 13:41:03 +0200 Subject: * Changes/fixes for drivers/cfi_flash.c: - Add Intel legacy lock/unlock support to common CFI driver On some Intel flash's (e.g. Intel J3) legacy unlocking is supported, meaning that unlocking of one sector will unlock all sectors of this bank. Using this feature, unlocking of all sectors upon startup (via env var "unlock=yes") will get much faster. - Fixed problem with multiple reads of envronment variable "unlock" as pointed out by Reinhard Arlt & Anders Larsen. - Removed unwanted linefeeds from "protect" command when CFG_FLASH_PROTECTION is enabled. - Changed p3p400 board to use CFG_FLASH_PROTECTION Patch by Stefan Roese, 01 Apr 2006 * Changes/fixes for drivers/cfi_flash.c: - Correctly handle the cases where CFG_HZ != 1000 (several XScale-based boards) - Fix the timeout calculation of buffered writes (off by a factor of 1000) Patch by Anders Larsen, 31 Mar 2006 --- CHANGELOG | 27 ++++++++++++++++++ common/cmd_flash.c | 5 ++-- drivers/cfi_flash.c | 71 ++++++++++++++++++++++++++++++++++++++++-------- include/configs/p3p440.h | 4 +++ include/flash.h | 1 + 5 files changed, 95 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 34b8d20ebb6..4c5b62c0689 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,33 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Changes/fixes for drivers/cfi_flash.c: + + - Add Intel legacy lock/unlock support to common CFI driver + + On some Intel flash's (e.g. Intel J3) legacy unlocking is + supported, meaning that unlocking of one sector will unlock + all sectors of this bank. Using this feature, unlocking + of all sectors upon startup (via env var "unlock=yes") will + get much faster. + + - Fixed problem with multiple reads of envronment variable + "unlock" as pointed out by Reinhard Arlt & Anders Larsen. + + - Removed unwanted linefeeds from "protect" command when + CFG_FLASH_PROTECTION is enabled. + + - Changed p3p400 board to use CFG_FLASH_PROTECTION + + Patch by Stefan Roese, 01 Apr 2006 + +* Changes/fixes for drivers/cfi_flash.c: + - Correctly handle the cases where CFG_HZ != 1000 (several + XScale-based boards) + - Fix the timeout calculation of buffered writes (off by a + factor of 1000) + Patch by Anders Larsen, 31 Mar 2006 + * Enable Quad UART om MCC200 board. * Cleanup MCC200 board configuration; omit non-existent stuff. diff --git a/common/cmd_flash.c b/common/cmd_flash.c index 0aa478306b8..201f4e33d44 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -455,6 +455,7 @@ int do_protect (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CONFIG_HAS_DATAFLASH int status; #endif + if (argc < 3) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; @@ -655,10 +656,10 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) #endif /* CFG_FLASH_PROTECTION */ } } + } #if defined(CFG_FLASH_PROTECTION) - if (!rcode) putc ('\n'); + puts (" done\n"); #endif /* CFG_FLASH_PROTECTION */ - } printf ("%sProtected %d sectors\n", p ? "" : "Un-", protected); diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index a989d346629..2e3748081e3 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -117,6 +117,7 @@ #define FLASH_OFFSET_CFI 0x55 #define FLASH_OFFSET_CFI_RESP 0x10 #define FLASH_OFFSET_PRIMARY_VENDOR 0x13 +#define FLASH_OFFSET_EXT_QUERY_T_P_ADDR 0x15 /* extended query table primary addr */ #define FLASH_OFFSET_WTOUT 0x1F #define FLASH_OFFSET_WBTOUT 0x20 #define FLASH_OFFSET_ETOUT 0x21 @@ -346,6 +347,10 @@ unsigned long flash_init (void) unsigned long size = 0; int i; +#ifdef CFG_FLASH_PROTECTION + char *s = getenv("unlock"); +#endif + /* Init: no FLASHes known */ for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; @@ -357,15 +362,39 @@ unsigned long flash_init (void) #endif /* CFG_FLASH_QUIET_TEST */ } #ifdef CFG_FLASH_PROTECTION - else { - char *s = getenv("unlock"); + else if ((s != NULL) && (strcmp(s, "yes") == 0)) { + /* + * Only the U-Boot image and it's environment is protected, + * all other sectors are unprotected (unlocked) if flash + * hardware protection is used (CFG_FLASH_PROTECTION) and + * the environment variable "unlock" is set to "yes". + */ + if (flash_info[i].legacy_unlock) { + int k; + + /* + * Disable legacy_unlock temporarily, since + * flash_real_protect would relock all other sectors + * again otherwise. + */ + flash_info[i].legacy_unlock = 0; - if (((s = getenv("unlock")) != NULL) && (strcmp(s, "yes") == 0)) { /* - * Only the U-Boot image and it's environment is protected, - * all other sectors are unprotected (unlocked) if flash - * hardware protection is used (CFG_FLASH_PROTECTION) and - * the environment variable "unlock" is set to "yes". + * Legacy unlocking (e.g. Intel J3) -> unlock only one + * sector. This will unlock all sectors. + */ + flash_real_protect (&flash_info[i], 0, 0); + + flash_info[i].legacy_unlock = 1; + + /* + * Manually mark other sectors as unlocked (unprotected) + */ + for (k = 1; k < flash_info[i].sector_count; k++) + flash_info[i].protect[k] = 0; + } else { + /* + * No legancy unlocking -> unlock all sectors */ flash_protect (FLAG_PROTECT_CLEAR, flash_info[i].start[0], @@ -668,8 +697,12 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) prot ? "protect" : "unprotect")) == 0) { info->protect[sector] = prot; - /* Intel's unprotect unprotects all locking */ - if (prot == 0) { + + /* + * On some of Intel's flash chips (marked via legacy_unlock) + * unprotect unprotects all locking. + */ + if ((prot == 0) && (info->legacy_unlock)) { flash_sect_t i; for (i = 0; i < info->sector_count; i++) { @@ -746,6 +779,10 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, { ulong start; +#if CFG_HZ != 1000 + tout *= CFG_HZ/1000; +#endif + /* Wait for command completion */ start = get_timer (0); while (flash_is_busy (info, sector)) { @@ -1082,6 +1119,10 @@ ulong flash_get_size (ulong base, int banknum) uchar num_erase_regions; int erase_region_size; int erase_region_count; +#ifdef CFG_FLASH_PROTECTION + int ext_addr; + info->legacy_unlock = 0; +#endif info->start[0] = base; @@ -1095,6 +1136,13 @@ ulong flash_get_size (ulong base, int banknum) case CFI_CMDSET_INTEL_EXTENDED: default: info->cmd_reset = FLASH_CMD_RESET; +#ifdef CFG_FLASH_PROTECTION + /* read legacy lock/unlock bit from intel flash */ + ext_addr = flash_read_ushort (info, 0, + FLASH_OFFSET_EXT_QUERY_T_P_ADDR); + info->legacy_unlock = + flash_read_uchar (info, ext_addr + 5) & 0x08; +#endif break; case CFI_CMDSET_AMD_STANDARD: case CFI_CMDSET_AMD_EXTENDED: @@ -1160,8 +1208,9 @@ ulong flash_get_size (ulong base, int banknum) info->buffer_size = (1 << flash_read_ushort (info, 0, FLASH_OFFSET_BUFFER_SIZE)); tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT); info->erase_blk_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT))); - tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT); - info->buffer_write_tout = (tmp * (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT))); + tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT)) * + (1 << flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)); + info->buffer_write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ tmp = (1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT)) * (1 << flash_read_uchar (info, FLASH_OFFSET_WMAX_TOUT)); info->write_tout = tmp / 1000 + (tmp % 1000 ? 1 : 0); /* round up when converting to ms */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 831d018e2d4..19656fc22af 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -146,6 +146,7 @@ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load;run update\0" \ + "unlock=yes\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" @@ -275,6 +276,9 @@ #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CFG_FLASH_PROTECTION 1 /* use hardware protection */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ diff --git a/include/flash.h b/include/flash.h index 4c68c6832f7..a84dc6872e1 100644 --- a/include/flash.h +++ b/include/flash.h @@ -45,6 +45,7 @@ typedef struct { ushort vendor; /* the primary vendor id */ ushort cmd_reset; /* Vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ + ushort legacy_unlock; /* support Intel legacy (un)locking */ #endif } flash_info_t; -- cgit v1.3.1 From 2fc000d756920b340945a74ec1214a34d9e84858 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Wed, 5 Apr 2006 20:46:41 +0200 Subject: Remove dependencies between DoC code and old legacy NAND driver. Necessary defines and data structures were copied to DoC specific files so that legacy NAND code could be entirely removed from u-boot tree in the near future. --- common/cmd_doc.c | 30 ++++++++++++++++++--- include/linux/mtd/doc2000.h | 65 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/common/cmd_doc.c b/common/cmd_doc.c index 37b7325be6a..ab375169531 100644 --- a/common/cmd_doc.c +++ b/common/cmd_doc.c @@ -22,11 +22,7 @@ #if (CONFIG_COMMANDS & CFG_CMD_DOC) #include -#include -#include - #include -#include #ifdef CFG_DOC_SUPPORT_2000 #define DoC_is_2000(doc) (doc->ChipID == DOC_ChipID_Doc2k) @@ -69,6 +65,32 @@ static struct DiskOnChip doc_dev_desc[CFG_MAX_DOC_DEVICE]; /* Current DOC Device */ static int curr_device = -1; +/* Supported NAND flash devices */ +static struct nand_flash_dev nand_flash_ids[] = { + {"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000, 0}, + {"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000, 0}, + {"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000, 0}, + {"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000, 0}, + {"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000, 0}, + {"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000, 0}, + {"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000, 0}, + {"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000, 0}, + {"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000, 0}, + {"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000, 0}, + {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000, 0}, + {"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000, 0}, + {"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000, 0}, + {"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000, 0}, + {"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000, 0}, + {"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000, 0}, + {"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000, 0}, + {"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000, 0}, + {"Samsung K9F5616Q0C", NAND_MFR_SAMSUNG, 0x45, 25, 0, 2, 0x4000, 1}, + {"Samsung K9K1216Q0C", NAND_MFR_SAMSUNG, 0x46, 26, 0, 3, 0x4000, 1}, + {"Samsung K9F1G08U0M", NAND_MFR_SAMSUNG, 0xf1, 27, 0, 2, 0, 0}, + {NULL,} +}; + /* ------------------------------------------------------------------------- */ int do_doc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h index ebf9a769241..eeb1d7e98e6 100644 --- a/include/linux/mtd/doc2000.h +++ b/include/linux/mtd/doc2000.h @@ -91,6 +91,13 @@ struct DiskOnChip; #define ADDR_PAGE 2 #define ADDR_COLUMN_PAGE 3 +struct Nand { + char floor, chip; + unsigned long curadr; + unsigned char curmode; + /* Also some erase/write/pipeline info when we get that far */ +}; + struct DiskOnChip { unsigned long physadr; unsigned long virtadr; @@ -148,4 +155,62 @@ void doc_probe(unsigned long physadr); void doc_print(struct DiskOnChip*); +/* + * Standard NAND flash commands + */ +#define NAND_CMD_READ0 0 +#define NAND_CMD_READ1 1 +#define NAND_CMD_PAGEPROG 0x10 +#define NAND_CMD_READOOB 0x50 +#define NAND_CMD_ERASE1 0x60 +#define NAND_CMD_STATUS 0x70 +#define NAND_CMD_SEQIN 0x80 +#define NAND_CMD_READID 0x90 +#define NAND_CMD_ERASE2 0xd0 +#define NAND_CMD_RESET 0xff + +/* + * NAND Flash Manufacturer ID Codes + */ +#define NAND_MFR_TOSHIBA 0x98 +#define NAND_MFR_SAMSUNG 0xec + +/* + * NAND Flash Device ID Structure + * + * Structure overview: + * + * name - Complete name of device + * + * manufacture_id - manufacturer ID code of device. + * + * model_id - model ID code of device. + * + * chipshift - total number of address bits for the device which + * is used to calculate address offsets and the total + * number of bytes the device is capable of. + * + * page256 - denotes if flash device has 256 byte pages or not. + * + * pageadrlen - number of bytes minus one needed to hold the + * complete address into the flash array. Keep in + * mind that when a read or write is done to a + * specific address, the address is input serially + * 8 bits at a time. This structure member is used + * by the read/write routines as a loop index for + * shifting the address out 8 bits at a time. + * + * erasesize - size of an erase block in the flash device. + */ +struct nand_flash_dev { + char * name; + int manufacture_id; + int model_id; + int chipshift; + char page256; + char pageadrlen; + unsigned long erasesize; + int bus16; +}; + #endif /* __MTD_DOC2000_H__ */ -- cgit v1.3.1 From 6db39708117d6391a72f3fc3ea7860231b630270 Mon Sep 17 00:00:00 2001 From: Marian Balakowicz Date: Sat, 8 Apr 2006 19:08:06 +0200 Subject: Fix JFFS2 support for legacy NAND driver. Some more NAND cleanup and small fixes. --- Makefile | 2 ++ board/amcc/bamboo/config.mk | 3 --- board/dave/PPChameleonEVB/config.mk | 6 ------ board/delta/config.mk | 3 --- board/delta/nand.c | 2 +- board/esd/ash405/config.mk | 3 --- board/esd/cms700/config.mk | 3 --- board/esd/common/auto_update.c | 16 ++++++++-------- board/esd/cpci405/config.mk | 3 --- board/esd/hh405/config.mk | 3 --- board/esd/hub405/config.mk | 3 --- board/esd/plu405/config.mk | 3 --- board/esd/voh405/config.mk | 3 --- board/esd/wuh405/config.mk | 3 --- board/netphone/config.mk | 3 --- board/netstar/config.mk | 3 --- board/netta/netta.c | 4 ++-- board/netta2/config.mk | 3 --- board/netvia/config.mk | 3 --- board/sixnet/config.mk | 3 --- drivers/nand/diskonchip.c | 5 ++--- drivers/nand/nand.c | 6 +----- drivers/nand/nand_base.c | 6 +----- drivers/nand/nand_bbt.c | 6 +----- drivers/nand/nand_ecc.c | 6 +----- drivers/nand/nand_ids.c | 6 +----- drivers/nand_legacy/nand_legacy.c | 18 +++++++++++------- fs/jffs2/jffs2_1pass.c | 34 ++++++++++++++++++++++++++++------ include/configs/CATcenter.h | 19 ++++++++++--------- include/configs/CPU86.h | 2 -- include/configs/IDS8247.h | 1 + include/configs/NC650.h | 2 ++ include/configs/NETTA.h | 1 + include/configs/RBC823.h | 2 -- include/configs/VCMA9.h | 1 + include/configs/delta.h | 3 ++- include/configs/omap2420h4.h | 1 + include/configs/stxxtc.h | 1 + 38 files changed, 78 insertions(+), 117 deletions(-) (limited to 'include') diff --git a/Makefile b/Makefile index af0c25af4c5..9b93463000f 100644 --- a/Makefile +++ b/Makefile @@ -133,6 +133,8 @@ LIBS += disk/libdisk.a LIBS += rtc/librtc.a LIBS += dtt/libdtt.a LIBS += drivers/libdrivers.a +LIBS += drivers/nand/libnand.a +LIBS += drivers/nand_legacy/libnand_legacy.a LIBS += drivers/sk98lin/libsk98lin.a LIBS += post/libpost.a post/cpu/libcpu.a LIBS += common/libcommon.a diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk index 433429bea71..35cb65584a1 100644 --- a/board/amcc/bamboo/config.mk +++ b/board/amcc/bamboo/config.mk @@ -32,6 +32,3 @@ endif ifeq ($(dbcr),1) PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000 endif - -# legacy nand support -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/dave/PPChameleonEVB/config.mk b/board/dave/PPChameleonEVB/config.mk index 1dc635fbf08..9083aacfabf 100644 --- a/board/dave/PPChameleonEVB/config.mk +++ b/board/dave/PPChameleonEVB/config.mk @@ -26,9 +26,3 @@ # Reserve 320 kB for Monitor TEXT_BASE = 0xFFFB0000 - -# Compile the new NAND code (CFG_NAND_LEGACY mustn't be defined) -BOARDLIBS = drivers/nand/libnand.a - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -#BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/delta/config.mk b/board/delta/config.mk index 9564625478e..61828bba996 100644 --- a/board/delta/config.mk +++ b/board/delta/config.mk @@ -3,6 +3,3 @@ #TEXT_BASE = 0xa3080000 #TEXT_BASE = 0x9ffe0000 TEXT_BASE = 0xa3008000 - -# Compile the new NAND code (needed iff #ifdef CONFIG_NEW_NAND_CODE) -BOARDLIBS = drivers/nand/libnand.a diff --git a/board/delta/nand.c b/board/delta/nand.c index c4df6e57eb7..7982548861e 100644 --- a/board/delta/nand.c +++ b/board/delta/nand.c @@ -23,7 +23,7 @@ #include #if (CONFIG_COMMANDS & CFG_CMD_NAND) -#ifdef CONFIG_NEW_NAND_CODE +#if !defined(CFG_NAND_LEGACY) #include #include diff --git a/board/esd/ash405/config.mk b/board/esd/ash405/config.mk index 3cf5dd85bf2..1d743a9f873 100644 --- a/board/esd/ash405/config.mk +++ b/board/esd/ash405/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xFFFC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/cms700/config.mk b/board/esd/cms700/config.mk index 0c56c40b9f1..5c3c01cf874 100644 --- a/board/esd/cms700/config.mk +++ b/board/esd/cms700/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xFFFC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c index cad82115cc6..5cd342332f5 100644 --- a/board/esd/common/auto_update.c +++ b/board/esd/common/auto_update.c @@ -24,8 +24,8 @@ #include -#ifndef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) +#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support! #endif #include @@ -74,7 +74,7 @@ extern int flash_write (char *, ulong, ulong); /* change char* to void* to shutup the compiler */ extern block_dev_desc_t *get_dev (char*, int); -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) /* references to names in cmd_nand.c */ #define NANDRW_READ 0x01 #define NANDRW_WRITE 0x00 @@ -84,7 +84,7 @@ extern struct nand_chip nand_dev_desc[]; extern int nand_legacy_rw(struct nand_chip* nand, int cmd, size_t start, size_t len, size_t * retlen, u_char * buf); extern int nand_legacy_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean); -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE]; @@ -188,7 +188,7 @@ int au_do_update(int i, long sz) int off, rc; uint nbytes; int k; -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) int total; #endif @@ -262,7 +262,7 @@ int au_do_update(int i, long sz) debug ("flash_sect_erase(%lx, %lx);\n", start, end); flash_sect_erase(start, end); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) printf("Updating NAND FLASH with image %s\n", au_image[i].name); debug ("nand_legacy_erase(%lx, %lx);\n", start, end); rc = nand_legacy_erase (nand_dev_desc, start, end - start + 1, 0); @@ -290,7 +290,7 @@ int au_do_update(int i, long sz) debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes); rc = flash_write((char *)addr, start, nbytes); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) debug ("nand_legacy_rw(%p, %lx %x)\n", addr, start, nbytes); rc = nand_legacy_rw(nand_dev_desc, NANDRW_WRITE | NANDRW_JFFS2, start, nbytes, (size_t *)&total, (uchar *)addr); @@ -308,7 +308,7 @@ int au_do_update(int i, long sz) if (au_image[i].type != AU_NAND) { rc = crc32 (0, (uchar *)(start + off), ntohl(hdr->ih_size)); } else { -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) rc = nand_legacy_rw(nand_dev_desc, NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP, start, nbytes, (size_t *)&total, (uchar *)addr); rc = crc32 (0, (uchar *)(addr + off), ntohl(hdr->ih_size)); diff --git a/board/esd/cpci405/config.mk b/board/esd/cpci405/config.mk index ceff4c4d1e7..0be45c70d7a 100644 --- a/board/esd/cpci405/config.mk +++ b/board/esd/cpci405/config.mk @@ -38,6 +38,3 @@ TEXT_BASE = 0xFFFD0000 endif endif endif - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hh405/config.mk b/board/esd/hh405/config.mk index 798a3fa4139..7129ad568bc 100644 --- a/board/esd/hh405/config.mk +++ b/board/esd/hh405/config.mk @@ -29,6 +29,3 @@ TEXT_BASE = 0xFFF80000 #TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/hub405/config.mk b/board/esd/hub405/config.mk index 4c60c3566d5..a6d31aad2ba 100644 --- a/board/esd/hub405/config.mk +++ b/board/esd/hub405/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xFFFC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/plu405/config.mk b/board/esd/plu405/config.mk index 916b285261e..25b21057998 100644 --- a/board/esd/plu405/config.mk +++ b/board/esd/plu405/config.mk @@ -27,6 +27,3 @@ TEXT_BASE = 0xFFFC0000 #TEXT_BASE = 0x00FC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/voh405/config.mk b/board/esd/voh405/config.mk index 72e81030abd..219a4eba15c 100644 --- a/board/esd/voh405/config.mk +++ b/board/esd/voh405/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xFFF80000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/esd/wuh405/config.mk b/board/esd/wuh405/config.mk index 3cf5dd85bf2..1d743a9f873 100644 --- a/board/esd/wuh405/config.mk +++ b/board/esd/wuh405/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xFFFC0000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netphone/config.mk b/board/netphone/config.mk index de179c2d657..8497ebc812b 100644 --- a/board/netphone/config.mk +++ b/board/netphone/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0x40000000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netstar/config.mk b/board/netstar/config.mk index 50d647add0e..8b73e975981 100644 --- a/board/netstar/config.mk +++ b/board/netstar/config.mk @@ -9,6 +9,3 @@ # XXX TEXT_BASE = 0x20012000 TEXT_BASE = 0x13FC0000 - -# Compile the new NAND code -BOARDLIBS = drivers/nand/libnand.a diff --git a/board/netta/netta.c b/board/netta/netta.c index 9194bfb9de3..4923e3addaf 100644 --- a/board/netta/netta.c +++ b/board/netta/netta.c @@ -555,9 +555,9 @@ int board_early_init_f(void) return 0; } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) -#include +#include extern ulong nand_probe(ulong physadr); extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; diff --git a/board/netta2/config.mk b/board/netta2/config.mk index de179c2d657..8497ebc812b 100644 --- a/board/netta2/config.mk +++ b/board/netta2/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0x40000000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/netvia/config.mk b/board/netvia/config.mk index 583174a4895..9dddaad54b4 100644 --- a/board/netvia/config.mk +++ b/board/netvia/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0x40000000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/board/sixnet/config.mk b/board/sixnet/config.mk index 8e73d2f3693..0cd8f441480 100644 --- a/board/sixnet/config.mk +++ b/board/sixnet/config.mk @@ -26,6 +26,3 @@ # TEXT_BASE = 0xF8000000 - -# Compile the legacy NAND code (CFG_NAND_LEGACY must be defined) -BOARDLIBS = drivers/nand_legacy/libnand_legacy.a diff --git a/drivers/nand/diskonchip.c b/drivers/nand/diskonchip.c index afaae834f1c..e17af70d07f 100644 --- a/drivers/nand/diskonchip.c +++ b/drivers/nand/diskonchip.c @@ -21,9 +21,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif +#if !defined(CFG_NAND_LEGACY) #include #include @@ -1786,3 +1784,4 @@ module_exit(cleanup_nanddoc); MODULE_LICENSE("GPL"); MODULE_AUTHOR("David Woodhouse "); MODULE_DESCRIPTION("M-Systems DiskOnChip 2000, Millennium and Millennium Plus device driver\n"); +#endif diff --git a/drivers/nand/nand.c b/drivers/nand/nand.c index dd80026fe02..e1781fcbbf8 100644 --- a/drivers/nand/nand.c +++ b/drivers/nand/nand.c @@ -23,11 +23,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand/nand_base.c b/drivers/nand/nand_base.c index e0b406041fb..b7a5d32fb3f 100644 --- a/drivers/nand/nand_base.c +++ b/drivers/nand/nand_base.c @@ -72,11 +72,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_bbt.c b/drivers/nand/nand_bbt.c index ac168723e22..aaa9400e54d 100644 --- a/drivers/nand/nand_bbt.c +++ b/drivers/nand/nand_bbt.c @@ -54,11 +54,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include #include diff --git a/drivers/nand/nand_ecc.c b/drivers/nand/nand_ecc.c index e0d0e8bcc40..f33be9655d3 100644 --- a/drivers/nand/nand_ecc.c +++ b/drivers/nand/nand_ecc.c @@ -37,11 +37,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include /* diff --git a/drivers/nand/nand_ids.c b/drivers/nand/nand_ids.c index 3d4d372f17f..8b58736bc10 100644 --- a/drivers/nand/nand_ids.c +++ b/drivers/nand/nand_ids.c @@ -13,11 +13,7 @@ #include -#ifdef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY defined in a file not using the legacy NAND support! -#endif - -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && !defined(CFG_NAND_LEGACY) #include diff --git a/drivers/nand_legacy/nand_legacy.c b/drivers/nand_legacy/nand_legacy.c index 3989ca2a2d7..458046d41c3 100644 --- a/drivers/nand_legacy/nand_legacy.c +++ b/drivers/nand_legacy/nand_legacy.c @@ -10,11 +10,6 @@ */ #include - -#ifndef CFG_NAND_LEGACY -#error CFG_NAND_LEGACY not defined in a file using the legacy NAND support! -#endif - #include #include #include @@ -27,7 +22,7 @@ # define SHOW_BOOT_PROGRESS(arg) #endif -#if (CONFIG_COMMANDS & CFG_CMD_NAND) +#if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) #include #include @@ -1612,4 +1607,13 @@ static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc) #endif -#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */ +#ifdef CONFIG_JFFS2_NAND +int read_jffs2_nand(size_t start, size_t len, + size_t * retlen, u_char * buf, int nanddev) +{ + return nand_legacy_rw(nand_dev_desc + nanddev, NANDRW_READ | NANDRW_JFFS2, + start, len, retlen, buf); +} +#endif /* CONFIG_JFFS2_NAND */ + +#endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) */ diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 49c86524c76..41ff4c1fbbd 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -144,7 +144,11 @@ static struct part_info *current_part; #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) +#if defined(CFG_NAND_LEGACY) +#include +#else #include +#endif /* * Support for jffs2 on top of NAND-flash * @@ -155,8 +159,14 @@ static struct part_info *current_part; * */ +#if defined(CFG_NAND_LEGACY) +/* this one defined in nand_legacy.c */ +int read_jffs2_nand(size_t start, size_t len, + size_t * retlen, u_char * buf, int nanddev); +#else /* info for NAND chips, defined in drivers/nand/nand.c */ extern nand_info_t nand_info[]; +#endif #define NAND_PAGE_SIZE 512 #define NAND_PAGE_SHIFT 9 @@ -167,7 +177,6 @@ extern nand_info_t nand_info[]; #endif #define NAND_CACHE_SIZE (NAND_CACHE_PAGES*NAND_PAGE_SIZE) -#ifdef CFG_NAND_LEGACY static u8* nand_cache = NULL; static u32 nand_cache_off = (u32)-1; @@ -175,7 +184,11 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) { struct mtdids *id = current_part->dev->id; u32 bytes_read = 0; +#if defined(CFG_NAND_LEGACY) + size_t retlen; +#else ulong retlen; +#endif int cpy_bytes; while (bytes_read < size) { @@ -193,14 +206,24 @@ static int read_nand_cached(u32 off, u32 size, u_char *buf) } } +#if defined(CFG_NAND_LEGACY) + if (read_jffs2_nand(nand_cache_off, NAND_CACHE_SIZE, + &retlen, nand_cache, id->num) < 0 || + retlen != NAND_CACHE_SIZE) { + printf("read_nand_cached: error reading nand off %#x size %d bytes\n", + nand_cache_off, NAND_CACHE_SIZE); + return -1; + } +#else retlen = NAND_CACHE_SIZE; if (nand_read(&nand_info[id->num], nand_cache_off, - &retlen, nand_cache) != 0 || + &retlen, nand_cache) != 0 || retlen != NAND_CACHE_SIZE) { printf("read_nand_cached: error reading nand off %#x size %d bytes\n", nand_cache_off, NAND_CACHE_SIZE); return -1; } +#endif } cpy_bytes = nand_cache_off + NAND_CACHE_SIZE - (off + bytes_read); if (cpy_bytes > size - bytes_read) @@ -251,7 +274,6 @@ static void put_fl_mem_nand(void *buf) { free(buf); } -#endif /* CFG_NAND_LEGACY */ #endif /* #if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) */ @@ -294,7 +316,7 @@ static inline void *get_fl_mem(u32 off, u32 size, void *ext_buf) return get_fl_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_fl_mem_nand(off, size, ext_buf); #endif @@ -312,7 +334,7 @@ static inline void *get_node_mem(u32 off) return get_node_mem_nor(off); #endif -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) if (id->type == MTD_DEV_TYPE_NAND) return get_node_mem_nand(off); #endif @@ -323,7 +345,7 @@ static inline void *get_node_mem(u32 off) static inline void put_fl_mem(void *buf) { -#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY) +#if defined(CONFIG_JFFS2_NAND) && (CONFIG_COMMANDS & CFG_CMD_NAND) struct mtdids *id = current_part->dev->id; if (id->type == MTD_DEV_TYPE_NAND) diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index ffe89cb78fc..7ec4599ebb5 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -193,6 +193,8 @@ */ #define CFG_NAND0_BASE 0xFF400000 #define CFG_NAND1_BASE 0xFF000000 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#define NAND_BIG_DELAY_US 25 /* For CATcenter there is only NAND on the module */ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ @@ -218,9 +220,9 @@ #define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */ -#define NAND_DISABLE_CE(nand) do \ +#define MACRO_NAND_DISABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \ @@ -231,9 +233,9 @@ } \ } while(0) -#define NAND_ENABLE_CE(nand) do \ +#define MACRO_NAND_ENABLE_CE(nandptr) do \ { \ - switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \ + switch((unsigned long)nandptr) \ { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \ @@ -244,8 +246,7 @@ } \ } while(0) - -#define NAND_CTL_CLRALE(nandptr) do \ +#define MACRO_NAND_CTL_CLRALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -258,7 +259,7 @@ } \ } while(0) -#define NAND_CTL_SETALE(nandptr) do \ +#define MACRO_NAND_CTL_SETALE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -271,7 +272,7 @@ } \ } while(0) -#define NAND_CTL_CLRCLE(nandptr) do \ +#define MACRO_NAND_CTL_CLRCLE(nandptr) do \ { \ switch((unsigned long)nandptr) \ { \ @@ -284,7 +285,7 @@ } \ } while(0) -#define NAND_CTL_SETCLE(nandptr) do { \ +#define MACRO_NAND_CTL_SETCLE(nandptr) do { \ switch((unsigned long)nandptr) { \ case CFG_NAND0_BASE: \ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \ diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 1e9a99eed33..16a9ea5dd71 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -178,8 +178,6 @@ /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include -#define CFG_NAND_LEGACY - /* * Miscellaneous configurable options */ diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index aaa44c53989..29eb874dbf0 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -236,6 +236,7 @@ */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CFG_NAND_LEGACY #define CFG_NAND0_BASE 0xE1000000 #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 371ea17edd2..3c59df4f45f 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -217,6 +217,8 @@ /* * NAND flash support */ +#define CFG_NAND_LEGACY + #define CFG_MAX_NAND_DEVICE 1 #define NAND_ChipID_UNKNOWN 0x00 #define SECTORSIZE 512 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 1bcd88d208a..25b63457c74 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -609,6 +609,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_UNSAFE diff --git a/include/configs/RBC823.h b/include/configs/RBC823.h index 21945a343cd..242c837a3b8 100644 --- a/include/configs/RBC823.h +++ b/include/configs/RBC823.h @@ -326,8 +326,6 @@ /************************************************************ * Disk-On-Chip configuration ************************************************************/ -#define CFG_NAND_LEGACY - #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ #define CFG_DOC_SHORT_TIMEOUT #define CFG_DOC_SUPPORT_2000 diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 3f29190e432..5f48a709381 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -248,6 +248,7 @@ */ #if (CONFIG_COMMANDS & CFG_CMD_NAND) +#define CFG_NAND_LEGACY #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define SECTORSIZE 512 diff --git a/include/configs/delta.h b/include/configs/delta.h index b42a7e2c1ae..31feaa35bfa 100644 --- a/include/configs/delta.h +++ b/include/configs/delta.h @@ -162,7 +162,8 @@ * NAND Flash */ /* Use the new NAND code. (BOARDLIBS = drivers/nand/libnand.a required) */ -#define CONFIG_NEW_NAND_CODE +#undef CFG_NAND_LEGACY + #define CFG_NAND0_BASE 0x0 /* 0x43100040 */ /* 0x10000000 */ #undef CFG_NAND1_BASE diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 12252ac129e..58374616a14 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -132,6 +132,7 @@ /* * Board NAND Info. */ +#define CFG_NAND_LEGACY #define CFG_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ #define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index be6c36cac9d..614a046105c 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -436,6 +436,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_ECC_JFFS2 #define CONFIG_MTD_NAND_VERIFY_WRITE -- cgit v1.3.1 From ad88297e2f14220f34417d1304d256285887aed4 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Tue, 11 Apr 2006 14:53:29 +0200 Subject: * Fix dbau1x00 Board - Fix dbau1x00 boards broken by dbau1550 patch PLL:s were not set for boards other than 1550. Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. Default boot is now bootp for cards other than 1550. Patch by Thomas Lange Aug 10 2005 --- CHANGELOG | 6 ++++++ board/dbau1x00/lowlevel_init.S | 5 ++++- include/configs/dbau1x00.h | 7 +++---- 3 files changed, 13 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 216cb633f75..e006f0e9d0c 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,6 +1,12 @@ ====================================================================== Changes since U-Boot 1.1.4: ====================================================================== +* Fix dbau1x00 Board + - Fix dbau1x00 boards broken by dbau1550 patch + PLL:s were not set for boards other than 1550. + Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. + Default boot is now bootp for cards other than 1550. + Patch by Thomas Lange Aug 10 2005 * Fixes common/cmd_flash.c: diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S index 7afd5840c86..14a78465f36 100644 --- a/board/dbau1x00/lowlevel_init.S +++ b/board/dbau1x00/lowlevel_init.S @@ -185,6 +185,8 @@ tlbloop: bne t0, t2, tlbloop nop +#endif /* CONFIG_DBAU1550 */ + /* First setup pll:s to make serial work ok */ /* We have a 12 MHz crystal */ li t0, SYS_CPUPLL @@ -205,6 +207,7 @@ tlbloop: sw t1, 0(t0) /* aux pll */ sync +#ifdef CONFIG_DBAU1550 /* Static memory controller */ /* RCE0 - can not change while fetching, do so from icache */ move t2, ra /* Store return address */ @@ -237,7 +240,7 @@ noCacheJump: sw t1, 0(t0) #else /* CONFIG_DBAU1550 */ li t0, MEM_STTIME0 - li t1, 0x00014C0F + li t1, 0x040181D7 sw t1, 0(t0) /* RCE0 AMD 29LV640M MirrorBit Flash */ diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index 0a10e3c75b4..4cc5085293b 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -81,8 +81,7 @@ CFG_CMD_MII | CFG_CMD_RUN | CFG_CMD_BDI | CFG_CMD_BEDBUG | \ CFG_CMD_NFS | CFG_CMD_ELF | CFG_CMD_PCMCIA | CFG_CMD_I2C)) #else /* CONFIG_DBAU1550 */ -/* Boot from Compact flash partition 2 as default */ -#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;bootm" +#define CONFIG_BOOTCOMMAND "bootp;bootm" #define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_IDE | CFG_CMD_DHCP | CFG_CMD_ELF) & \ ~(CFG_CMD_ENV | CFG_CMD_FAT | CFG_CMD_FLASH | CFG_CMD_FPGA | \ @@ -133,8 +132,6 @@ #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ -#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} - #else /* CONFIG_DBAU1550 */ #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ @@ -145,6 +142,8 @@ #endif /* CONFIG_DBAU1550 */ +#define CFG_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} + #define CFG_FLASH_CFI 1 #define CFG_FLASH_CFI_DRIVER 1 -- cgit v1.3.1 From b81a4630a3914d611ca3e72b451c4509c60ae9b1 Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Thu, 13 Apr 2006 16:35:22 +0200 Subject: Fix Quad UART mapping on MCC200 board due to new HW revision --- CHANGELOG | 2 ++ include/configs/mcc200.h | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 1ddbcc299c0..97f729c9787 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,8 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Fix Quad UART mapping on MCC200 board due to new HW revision + * Fix JFFS2 support for legacy NAND driver. * Remove dependencies between DoC code and old legacy NAND driver. diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index 67c248367af..2b1c0d00cb9 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -250,7 +250,7 @@ /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ #define CFG_CS2_START 0x80000000 #define CFG_CS2_SIZE 0x00001000 -#define CFG_CS2_CFG 0x1d800 +#define CFG_CS2_CFG 0x1d300 #define CFG_CS_BURST 0x00000000 #define CFG_CS_DEADCYCLE 0x33333333 -- cgit v1.3.1 From cf48eb9abd76e5a056937a4e49be094826026abc Mon Sep 17 00:00:00 2001 From: Wolfgang Denk Date: Sun, 16 Apr 2006 10:51:58 +0200 Subject: Some code cleanup --- CHANGELOG | 77 +++++------ README | 8 +- board/icecube/icecube.c | 12 +- board/mpc8349emds/mpc8349emds.c | 22 ++-- board/mx1ads/mx1ads.c | 2 +- common/cmd_load.c | 72 +++++----- common/crc16.c | 177 ++++++++++++------------- common/xyzModem.c | 284 ++++++++++++++++++++-------------------- cpu/mpc5xxx/cpu.c | 2 +- cpu/mpc83xx/cpu.c | 2 +- cpu/mpc83xx/spd_sdram.c | 4 +- cpu/ppc4xx/sdram.c | 214 +++++++++++++++--------------- doc/README.mpc8349emds.ddrecc | 2 - include/configs/MPC8349EMDS.h | 4 +- include/crc.h | 139 ++++++++++---------- include/xyzModem.h | 124 +++++++++--------- rtc/ds1374.c | 2 +- 17 files changed, 577 insertions(+), 570 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index 20f72e89b5a..becc55cd05a 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -1,19 +1,20 @@ ====================================================================== Changes since U-Boot 1.1.4: ====================================================================== -* Fix dbau1x00 Board - - Fix dbau1x00 boards broken by dbau1550 patch - PLL:s were not set for boards other than 1550. - Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. - Default boot is now bootp for cards other than 1550. - Patch by Thomas Lange Aug 10 2005 -* Fixes common/cmd_flash.c: +* Some code cleanup - - fix some compiler/parser error, if using m68k tool chain - - optical fix for protect on/off all messages, if using more - then one bank - Patch by Jens Scharsig, 28 July 2005 +* Fix dbau1x00 boards broken by dbau1550 patch + PLL:s were not set for boards other than 1550. + Flash CFI caused card to hang due to undefined CFG_FLASH_BANKS_LIST. + Default boot is now bootp for cards other than 1550. + Patch by Thomas Lange, 10 Aug 2005 + +* Fixes common/cmd_flash.c: + - fix some compiler/parser error, if using m68k tool chain + - optical fix for protect on/off all messages, if using more + then one bank + Patch by Jens Scharsig, 28 Jul 2005 * Fix Quad UART mapping on MCC200 board due to new HW revision @@ -57,18 +58,18 @@ Changes since U-Boot 1.1.4: * Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) 405 SDRAM: - The SDRAM parameters can now be defined in the board - config file and the 405 SDRAM controller values will - be calculated upon bootup (see PPChameleonEVB). - When those settings are not defined in the board - config file, the register setup will be as it is now, - so this implementation should not break any current - design using this code. + config file and the 405 SDRAM controller values will + be calculated upon bootup (see PPChameleonEVB). + When those settings are not defined in the board + config file, the register setup will be as it is now, + so this implementation should not break any current + design using this code. - Thanks to Andrea Marson from DAVE for this patch. + Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the - TR1 value for the DDR. - - Added ECC support (see p3p440). + TR1 value for the DDR. + - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006 @@ -442,7 +443,7 @@ Changes since U-Boot 1.1.4: are removed from the default U-Boot build. Enable DEBUG for lib_arm/board.c to enable debug messages. New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options. - Patch by Stefan Roese, 24 Jan 2006 + Patch by Stefan Roese, 24 Jan 2006 * Fix various compiler warnings on ppc4xx builds (ELDK 4.0) Patch by Stefan Roese, 18 Jan 2006 @@ -588,11 +589,11 @@ Changes for U-Boot 1.1.4: * Add support for multiple PHYs. Tested on the following boards: - cmcpu2 (at91rm9200/ether.c) + cmcpu2 (at91rm9200/ether.c) PPChameleon (ppc4xx/4xx_enet.c) - yukon (mpc8220/fec.c) - uc100 (mpc8xx/fec.c) - tqm834x (mpc834x/tsec.c) with EEPRO100 + yukon (mpc8220/fec.c) + uc100 (mpc8xx/fec.c) + tqm834x (mpc834x/tsec.c) with EEPRO100 lite5200 (mpc5xxx/fec.c) with EEPRO100 card (drivers/eepro100.c) Main changes include: common/miiphyutil.c @@ -1132,18 +1133,18 @@ Changes for U-Boot 1.1.3: The first one is to define a single, static partition: #undef CONFIG_JFFS2_CMDLINE - #define CONFIG_JFFS2_DEV "nor0" - #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ - #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ - #define CONFIG_JFFS2_PART_OFFSET 0x00000000 + #define CONFIG_JFFS2_DEV "nor0" + #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF /* use whole device */ + #define CONFIG_JFFS2_PART_SIZE 0x00100000 /* use 1MB */ + #define CONFIG_JFFS2_PART_OFFSET 0x00000000 The second method uses the mtdparts command line option and dynamic partitioning: /* mtdparts command line support */ #define CONFIG_JFFS2_CMDLINE - #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" - #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" + #define MTDIDS_DEFAULT "nor1=zuma-1,nor2=zuma-2" + #define MTDPARTS_DEFAULT "mtdparts=zuma-1:-(jffs2),zuma-2:-(user)" Command line of course produces bigger images, and may be inappropriate for some targets, so by default it's off. @@ -3456,7 +3457,7 @@ Changes for U-Boot 1.0.1: Bring ARM memory layout in sync with the documentation: stack and malloc-heap are now located _below_ the U-Boot code -* Accelerate booting on TRAB board: read and check autoupdate image +* Accelerate booting on TRAB board: read and check autoupdate image headers first instead of always reading the whole images. * Fix type in MPC5XXX code (pointed out by Victor Wren) @@ -3576,7 +3577,7 @@ Changes for U-Boot 1.0.0: * Make 5200 reset command _really_ reset the board, without running any other code after it -* Fix errors with flash erase when range spans across banks +* Fix errors with flash erase when range spans across banks that are mapped in reverse order * Fix flash mapping and display on P3G4 board @@ -3820,7 +3821,7 @@ Changes for U-Boot 0.4.8: or 1 x AM29LV652 (two LV065 in one chip = 16 MB); Run IPB at 133 Mhz; adjust the MII clock frequency accordingly -* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) +* Set BRG_CLK on PM825/826 to 64MHz (VCO_OUT / 4, instead of 16 MHz) to allow for more accurate baudrate settings (error now 0.7% at 115 kbps, instead of 3.5% before) @@ -4307,7 +4308,7 @@ Changes for U-Boot 0.4.0: Update for MPC8266ADS board * Get (mostly) rid of CFG_MONITOR_LEN definition; compute real length - instead CFG_MONITOR_LEN is now only used to determine _at_compile_ + instead CFG_MONITOR_LEN is now only used to determine _at_compile_ _time_ (!) if the environment is embedded within the U-Boot image, or in a separate flash sector. @@ -4357,7 +4358,7 @@ Changes for U-Boot 0.4.0: * Patch by Thomas Schäfer, 28 Apr 2003: Fix SPD handling for 256 ECC DIMM on Walnut -* Add support for arbitrary bitmaps for TRAB's VFD command; +* Add support for arbitrary bitmaps for TRAB's VFD command; allow to pass boot bitmap addresses in environment variables; allow for zero boot delay @@ -4700,7 +4701,7 @@ Changes for U-Boot 0.3.0: * Add VFD type detection to trab board -* extend drivers/cs8900.c driver to synchronize ethaddr environment +* extend drivers/cs8900.c driver to synchronize ethaddr environment variable with value in the EEPROM * Patch by Stefan Roese, 10 Feb 2003: @@ -4860,7 +4861,7 @@ Changes for U-Boot 0.2.0: * Patch by Pierre Aubert, 05 Nov 2002 Add support for slave serial Spartan 2 FPGAs -* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet +* Fix uninitialized memory (MAC address) in 8xx SCC/FEC ethernet drivers * Add support for log buffer which can be passed to Linux kernel's diff --git a/README b/README index ae9e10f533f..3ae9cfcc174 100644 --- a/README +++ b/README @@ -307,7 +307,7 @@ The following options need to be configured: CONFIG_ARMADILLO, CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_CSB637, CONFIG_DELTA, CONFIG_DNP1110, CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, - CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, + CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, CONFIG_KB9202, CONFIG_LART, CONFIG_LPD7A400, CONFIG_LUBBOCK, CONFIG_OSK_OMAP5912, CONFIG_OMAP2420H4, CONFIG_SHANNON, CONFIG_P2_OMAP730, CONFIG_SMDK2400, @@ -388,12 +388,12 @@ The following options need to be configured: frequency is this value multiplied by 13 MHz. CFG_MONAHANS_TURBO_RUN_MODE_RATIO - + Defines the Monahans turbo mode to oscillator ratio. Valid values are 1 (default if undefined) and - 2. The core frequency as calculated above is multiplied + 2. The core frequency as calculated above is multiplied by this value. - + - Linux Kernel Interface: CONFIG_CLOCKS_IN_MHZ diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c index 4197a7c5212..4f056b2fa44 100644 --- a/board/icecube/icecube.c +++ b/board/icecube/icecube.c @@ -187,17 +187,17 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ /* - * On MPC5200B we need to set the special configuration delay in the - * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: * - * "The SDelay should be written to a value of 0x00000004. It is - * required to account for changes caused by normal wafer processing + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing * parameters." - */ + */ svr = get_svr(); pvr = get_pvr(); - if ((SVR_MJREV(svr) >= 2) && + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c index 73a33f68cec..7ece7db7d06 100644 --- a/board/mpc8349emds/mpc8349emds.c +++ b/board/mpc8349emds/mpc8349emds.c @@ -116,14 +116,14 @@ int fixed_sdram(void) im->ddr.csbnds[2].csbnds = 0x0000000f; im->ddr.cs_config[2] = CFG_DDR_CONFIG; - /* currently we use only one CS, so disable the other banks */ + /* currently we use only one CS, so disable the other banks */ im->ddr.cs_config[0] = 0; im->ddr.cs_config[1] = 0; im->ddr.cs_config[3] = 0; im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - + im->ddr.sdram_cfg = SDRAM_CFG_SREN #if defined(CONFIG_DDR_2T_TIMING) @@ -136,7 +136,7 @@ int fixed_sdram(void) #endif im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; udelay(200); /* enable DDR controller */ @@ -361,12 +361,12 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) volatile u32 val; u64 *addr, count, val64; register u64 *i; - + if (argc > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } - + if (argc == 2) { if (strcmp(argv[1], "status") == 0) { ecc_print_status(); @@ -379,8 +379,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ddr->capture_attributes = 0; return 0; } - } - + } + if (argc == 3) { if (strcmp(argv[1], "sbecnt") == 0) { val = simple_strtoul(argv[2], NULL, 10); @@ -416,8 +416,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strcmp(argv[2], "+mse") == 0) { val |= ECC_ERROR_DISABLE_MSED; } else if (strcmp(argv[2], "+all") == 0) { - val |= (ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | + val |= (ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | ECC_ERROR_DISABLE_MSED); } else if (strcmp(argv[2], "-sbe") == 0) { val &= ~ECC_ERROR_DISABLE_SBED; @@ -426,8 +426,8 @@ int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } else if (strcmp(argv[2], "-mse") == 0) { val &= ~ECC_ERROR_DISABLE_MSED; } else if (strcmp(argv[2], "-all") == 0) { - val &= ~(ECC_ERROR_DISABLE_SBED | - ECC_ERROR_DISABLE_MBED | + val &= ~(ECC_ERROR_DISABLE_SBED | + ECC_ERROR_DISABLE_MBED | ECC_ERROR_DISABLE_MSED); } else { printf("Incorrect err_disable field\n"); diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index 913f95c5e89..abf2fd51e9b 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -85,7 +85,7 @@ int board_init (void) GPCR = 0x000003AB; /* I/O pad driving strength */ - /* MX1_CS1U = 0x00000A00; *//* SRAM initialization */ + /* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */ /* MX1_CS1L = 0x11110601; */ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */ diff --git a/common/cmd_load.c b/common/cmd_load.c index 31fef8151b7..2432ee20567 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -973,7 +973,7 @@ START: } static int getcxmodem(void) { - if (tstc()) + if (tstc()) return (getc()); return -1; } @@ -984,49 +984,51 @@ static ulong load_serial_ymodem (ulong offset) int err; int res; connection_info_t info; - char ymodemBuf[1024]; - ulong store_addr = ~0; - ulong addr = 0; + char ymodemBuf[1024]; + ulong store_addr = ~0; + ulong addr = 0; - size=0; - info.mode=xyzModem_ymodem; - res=xyzModem_stream_open(&info, &err); + size = 0; + info.mode = xyzModem_ymodem; + res = xyzModem_stream_open (&info, &err); if (!res) { - - while ((res=xyzModem_stream_read(ymodemBuf, 1024, &err)) > 0 ){ - store_addr = addr + offset; - size+=res; - addr+=res; -#ifndef CFG_NO_FLASH - if (addr2info(store_addr)) { - int rc; - rc = flash_write((char *)ymodemBuf,store_addr,res); - if (rc != 0) { - flash_perror (rc); - return (~0); - } - } else + while ((res = + xyzModem_stream_read (ymodemBuf, 1024, &err)) > 0) { + store_addr = addr + offset; + size += res; + addr += res; +#ifndef CFG_NO_FLASH + if (addr2info (store_addr)) { + int rc; + + rc = flash_write ((char *) ymodemBuf, + store_addr, res); + if (rc != 0) { + flash_perror (rc); + return (~0); + } + } else #endif - { - memcpy ((char *)(store_addr), ymodemBuf, res); - } - - } - } - else { - printf ("%s\n",xyzModem_error(err)); + { + memcpy ((char *) (store_addr), ymodemBuf, + res); + } + + } + } else { + printf ("%s\n", xyzModem_error (err)); } - - xyzModem_stream_close(&err); - xyzModem_stream_terminate(false,&getcxmodem); + + xyzModem_stream_close (&err); + xyzModem_stream_terminate (false, &getcxmodem); flush_cache (offset, size); - printf("## Total Size = 0x%08x = %d Bytes\n", size, size); - sprintf(buf, "%X", size); - setenv("filesize", buf); + printf ("## Total Size = 0x%08x = %d Bytes\n", size, size); + sprintf (buf, "%X", size); + setenv ("filesize", buf); return offset; } diff --git a/common/crc16.c b/common/crc16.c index d5714051793..3cef1060072 100644 --- a/common/crc16.c +++ b/common/crc16.c @@ -1,94 +1,96 @@ -//========================================================================== -// -// crc16.c -// -// 16 bit CRC with polynomial x^16+x^12+x^5+1 -// -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// Copyright (C) 2002 Gary Thomas -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): gthomas -// Contributors: gthomas,asl -// Date: 2001-01-31 -// Purpose: -// Description: -// -// This code is part of eCos (tm). -// -//####DESCRIPTIONEND#### -// -//========================================================================== +/* + *========================================================================== + * + * crc16.c + * + * 16 bit CRC with polynomial x^16+x^12+x^5+1 + * + *========================================================================== + *####ECOSGPLCOPYRIGHTBEGIN#### + * ------------------------------------------- + * This file is part of eCos, the Embedded Configurable Operating System. + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * Copyright (C) 2002 Gary Thomas + * + * eCos is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 or (at your option) any later version. + * + * eCos is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with eCos; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use macros + * or inline functions from this file, or you compile this file and link it + * with other works to produce a work based on this file, this file does not + * by itself cause the resulting work to be covered by the GNU General Public + * License. However the source code for this file must still be made available + * in accordance with section (3) of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + * + * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + * at http: *sources.redhat.com/ecos/ecos-license/ + * ------------------------------------------- + *####ECOSGPLCOPYRIGHTEND#### + *========================================================================== + *#####DESCRIPTIONBEGIN#### + * + * Author(s): gthomas + * Contributors: gthomas,asl + * Date: 2001-01-31 + * Purpose: + * Description: + * + * This code is part of eCos (tm). + * + *####DESCRIPTIONEND#### + * + *========================================================================== + */ #include "crc.h" -// Table of CRC constants - implements x^16+x^12+x^5+1 +/* Table of CRC constants - implements x^16+x^12+x^5+1 */ static const uint16_t crc16_tab[] = { - 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, - 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, - 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, - 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, - 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, - 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, - 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, - 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, - 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, - 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, - 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, - 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, - 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, - 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, - 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, - 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, - 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, - 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, - 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, - 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, - 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, - 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, - 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, - 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, - 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, - 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, - 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, - 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, - 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, - 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, - 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, - 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, + 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7, + 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef, + 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6, + 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de, + 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485, + 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d, + 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4, + 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc, + 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823, + 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b, + 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12, + 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a, + 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41, + 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49, + 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70, + 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78, + 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f, + 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067, + 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e, + 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256, + 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d, + 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405, + 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c, + 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634, + 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab, + 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3, + 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a, + 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92, + 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9, + 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1, + 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8, + 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0, }; uint16_t @@ -103,4 +105,3 @@ cyg_crc16(unsigned char *buf, int len) } return cksum; } - diff --git a/common/xyzModem.c b/common/xyzModem.c index 3c86b138b36..4a137bffdec 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -1,65 +1,67 @@ -//========================================================================== -// -// xyzModem.c -// -// RedBoot stream handler for xyzModem protocol -// -//========================================================================== -//####ECOSGPLCOPYRIGHTBEGIN#### -// ------------------------------------------- -// This file is part of eCos, the Embedded Configurable Operating System. -// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. -// Copyright (C) 2002 Gary Thomas -// -// eCos is free software; you can redistribute it and/or modify it under -// the terms of the GNU General Public License as published by the Free -// Software Foundation; either version 2 or (at your option) any later version. -// -// eCos is distributed in the hope that it will be useful, but WITHOUT ANY -// WARRANTY; without even the implied warranty of MERCHANTABILITY or -// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -// for more details. -// -// You should have received a copy of the GNU General Public License along -// with eCos; if not, write to the Free Software Foundation, Inc., -// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. -// -// As a special exception, if other files instantiate templates or use macros -// or inline functions from this file, or you compile this file and link it -// with other works to produce a work based on this file, this file does not -// by itself cause the resulting work to be covered by the GNU General Public -// License. However the source code for this file must still be made available -// in accordance with section (3) of the GNU General Public License. -// -// This exception does not invalidate any other reasons why a work based on -// this file might be covered by the GNU General Public License. -// -// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. -// at http://sources.redhat.com/ecos/ecos-license/ -// ------------------------------------------- -//####ECOSGPLCOPYRIGHTEND#### -//========================================================================== -//#####DESCRIPTIONBEGIN#### -// -// Author(s): gthomas -// Contributors: gthomas, tsmith, Yoshinori Sato -// Date: 2000-07-14 -// Purpose: -// Description: -// -// This code is part of RedBoot (tm). -// -//####DESCRIPTIONEND#### -// -//========================================================================== +/* + *========================================================================== + * + * xyzModem.c + * + * RedBoot stream handler for xyzModem protocol + * + *========================================================================== + *####ECOSGPLCOPYRIGHTBEGIN#### + * ------------------------------------------- + * This file is part of eCos, the Embedded Configurable Operating System. + * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. + * Copyright (C) 2002 Gary Thomas + * + * eCos is free software; you can redistribute it and/or modify it under + * the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 or (at your option) any later version. + * + * eCos is distributed in the hope that it will be useful, but WITHOUT ANY + * WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with eCos; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + * + * As a special exception, if other files instantiate templates or use macros + * or inline functions from this file, or you compile this file and link it + * with other works to produce a work based on this file, this file does not + * by itself cause the resulting work to be covered by the GNU General Public + * License. However the source code for this file must still be made available + * in accordance with section (3) of the GNU General Public License. + * + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + * + * Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. + * at http: *sources.redhat.com/ecos/ecos-license/ + * ------------------------------------------- + *####ECOSGPLCOPYRIGHTEND#### + *========================================================================== + *#####DESCRIPTIONBEGIN#### + * + * Author(s): gthomas + * Contributors: gthomas, tsmith, Yoshinori Sato + * Date: 2000-07-14 + * Purpose: + * Description: + * + * This code is part of RedBoot (tm). + * + *####DESCRIPTIONEND#### + * + *========================================================================== + */ #include #include #include #include -// Assumption - run xyzModem protocol over the console port +/* Assumption - run xyzModem protocol over the console port */ -// Values magic to the protocol +/* Values magic to the protocol */ #define SOH 0x01 #define STX 0x02 #define EOT 0x04 @@ -67,11 +69,11 @@ #define BSP 0x08 #define NAK 0x15 #define CAN 0x18 -#define EOF 0x1A // ^Z for DOS officionados +#define EOF 0x1A /* ^Z for DOS officionados */ #define USE_YMODEM_LENGTH -// Data & state local to the protocol +/* Data & state local to the protocol */ static struct { #ifdef REDBOOT hal_virtual_comm_table_t* __chan; @@ -80,7 +82,7 @@ static struct { #endif unsigned char pkt[1024], *bufp; unsigned char blk,cblk,crc1,crc2; - unsigned char next_blk; // Expected block + unsigned char next_blk; /* Expected block */ int len, mode, total_retries; int total_SOH, total_STX, total_CAN; bool crc_mode, at_eof, tx_ack; @@ -89,13 +91,13 @@ static struct { #endif } xyz; -#define xyzModem_CHAR_TIMEOUT 2000 // 2 seconds +#define xyzModem_CHAR_TIMEOUT 2000 /* 2 seconds */ #define xyzModem_MAX_RETRIES 20 #define xyzModem_MAX_RETRIES_WITH_CRC 10 -#define xyzModem_CAN_COUNT 3 // Wait for 3 CAN before quitting +#define xyzModem_CAN_COUNT 3 /* Wait for 3 CAN before quitting */ -#ifndef REDBOOT //SB +#ifndef REDBOOT /*SB */ typedef int cyg_int32; int CYGACC_COMM_IF_GETC_TIMEOUT (char chan,char *c) { #define DELAY 20 @@ -115,7 +117,7 @@ void CYGACC_COMM_IF_PUTC(char x,char y) { putc(y); } -// Validate a hex character +/* Validate a hex character */ __inline__ static bool _is_hex(char c) { @@ -124,7 +126,7 @@ _is_hex(char c) ((c >= 'a') && (c <= 'f'))); } -// Convert a single hex nibble +/* Convert a single hex nibble */ __inline__ static int _from_hex(char c) { @@ -140,7 +142,7 @@ _from_hex(char c) return ret; } -// Convert a character to lower case +/* Convert a character to lower case */ __inline__ static char _tolower(char c) { @@ -150,11 +152,7 @@ _tolower(char c) return c; } - - -// -// Parse (scan) a number -// +/* Parse (scan) a number */ bool parse_num(char *s, unsigned long *val, char **es, char *delim) { @@ -173,10 +171,10 @@ parse_num(char *s, unsigned long *val, char **es, char *delim) first = false; c = *s++; if (_is_hex(c) && ((digit = _from_hex(c)) < radix)) { - // Valid digit + /* Valid digit */ #ifdef CYGPKG_HAL_MIPS - // FIXME: tx49 compiler generates 0x2539018 for MUL which - // isn't any good. + /* FIXME: tx49 compiler generates 0x2539018 for MUL which */ + /* isn't any good. */ if (16 == radix) result = result << 4; else @@ -187,12 +185,12 @@ parse_num(char *s, unsigned long *val, char **es, char *delim) #endif } else { if (delim != (char *)0) { - // See if this character is one of the delimiters + /* See if this character is one of the delimiters */ char *dp = delim; while (*dp && (c != *dp)) dp++; - if (*dp) break; // Found a good delimiter + if (*dp) break; /* Found a good delimiter */ } - return false; // Malformatted number + return false; /* Malformatted number */ } } *val = result; @@ -207,11 +205,11 @@ parse_num(char *s, unsigned long *val, char **es, char *delim) #define USE_SPRINTF #ifdef DEBUG #ifndef USE_SPRINTF -// -// Note: this debug setup only works if the target platform has two serial ports -// available so that the other one (currently only port 1) can be used for debug -// messages. -// +/* + * Note: this debug setup only works if the target platform has two serial ports + * available so that the other one (currently only port 1) can be used for debug + * messages. + */ static int zm_dprintf(char *fmt, ...) { @@ -235,9 +233,9 @@ zm_flush(void) } #else -// -// Note: this debug setup works by storing the strings in a fixed buffer -// +/* + * Note: this debug setup works by storing the strings in a fixed buffer + */ #define FINAL #ifdef FINAL static char *zm_out = (char *)0x00380000; @@ -308,7 +306,7 @@ zm_dump(int line) #define ZM_DEBUG(x) #endif -// Wait for the line to go idle +/* Wait for the line to go idle */ static void xyzModem_flush(void) { @@ -330,7 +328,7 @@ xyzModem_get_hdr(void) unsigned short cksum; ZM_DEBUG(zm_new()); - // Find the start of a header + /* Find the start of a header */ can_total = 0; hdr_chars = 0; @@ -356,11 +354,11 @@ xyzModem_get_hdr(void) if (++can_total == xyzModem_CAN_COUNT) { return xyzModem_cancel; } else { - // Wait for multiple CAN to avoid early quits + /* Wait for multiple CAN to avoid early quits */ break; } case EOT: - // EOT only supported if no noise + /* EOT only supported if no noise */ if (hdr_chars == 1) { CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); ZM_DEBUG(zm_dprintf("ACK on EOT #%d\n", __LINE__)); @@ -368,19 +366,19 @@ xyzModem_get_hdr(void) return xyzModem_eof; } default: - // Ignore, waiting for start of header + /* Ignore, waiting for start of header */ ; } } else { - // Data stream timed out - xyzModem_flush(); // Toss any current input + /* Data stream timed out */ + xyzModem_flush(); /* Toss any current input */ ZM_DEBUG(zm_dump(__LINE__)); CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); return xyzModem_timeout; } } - // Header found, now read the data + /* Header found, now read the data */ res = CYGACC_COMM_IF_GETC_TIMEOUT(*xyz.__chan, &xyz.blk); ZM_DEBUG(zm_save(xyz.blk)); if (!res) { @@ -420,18 +418,18 @@ xyzModem_get_hdr(void) } } ZM_DEBUG(zm_dump(__LINE__)); - // Validate the message + /* Validate the message */ if ((xyz.blk ^ xyz.cblk) != (unsigned char)0xFF) { ZM_DEBUG(zm_dprintf("Framing error - blk: %x/%x/%x\n", xyz.blk, xyz.cblk, (xyz.blk ^ xyz.cblk))); ZM_DEBUG(zm_dump_buf(xyz.pkt, xyz.len)); xyzModem_flush(); return xyzModem_frame; } - // Verify checksum/CRC + /* Verify checksum/CRC */ if (xyz.crc_mode) { cksum = cyg_crc16(xyz.pkt, xyz.len); if (cksum != ((xyz.crc1 << 8) | xyz.crc2)) { - ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n", + ZM_DEBUG(zm_dprintf("CRC error - recvd: %02x%02x, computed: %x\n", xyz.crc1, xyz.crc2, cksum & 0xFFFF)); return xyzModem_cksum; } @@ -445,18 +443,18 @@ xyzModem_get_hdr(void) return xyzModem_cksum; } } - // If we get here, the message passes [structural] muster + /* If we get here, the message passes [structural] muster */ return 0; } -int +int xyzModem_stream_open(connection_info_t *info, int *err) { int console_chan, stat=0; int retries = xyzModem_MAX_RETRIES; int crc_retries = xyzModem_MAX_RETRIES_WITH_CRC; -// ZM_DEBUG(zm_out = zm_out_start); +/* ZM_DEBUG(zm_out = zm_out_start); */ #ifdef xyzModem_zmodem if (info->mode == xyzModem_zmodem) { *err = xyzModem_noZmodem; @@ -465,7 +463,7 @@ xyzModem_stream_open(connection_info_t *info, int *err) #endif #ifdef REDBOOT - // Set up the I/O channel. Note: this allows for using a different port in the future + /* Set up the I/O channel. Note: this allows for using a different port in the future */ console_chan = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT); if (info->chan >= 0) { CYGACC_CALL_IF_SET_CONSOLE_COMM(info->chan); @@ -477,9 +475,9 @@ xyzModem_stream_open(connection_info_t *info, int *err) CYGACC_CALL_IF_SET_CONSOLE_COMM(console_chan); CYGACC_COMM_IF_CONTROL(*xyz.__chan, __COMMCTL_SET_TIMEOUT, xyzModem_CHAR_TIMEOUT); #else -// TODO: CHECK ! +/* TODO: CHECK ! */ int dummy; - xyz.__chan=&dummy; + xyz.__chan=&dummy; #endif xyz.len = 0; xyz.crc_mode = true; @@ -494,11 +492,11 @@ xyzModem_stream_open(connection_info_t *info, int *err) xyz.read_length = 0; xyz.file_length = 0; #endif - + CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); if (xyz.mode == xyzModem_xmodem) { - // X-modem doesn't have an information header - exit here + /* X-modem doesn't have an information header - exit here */ xyz.next_blk = 1; return 0; } @@ -506,24 +504,24 @@ xyzModem_stream_open(connection_info_t *info, int *err) while (retries-- > 0) { stat = xyzModem_get_hdr(); if (stat == 0) { - // Y-modem file information header + /* Y-modem file information header */ if (xyz.blk == 0) { #ifdef USE_YMODEM_LENGTH - // skip filename + /* skip filename */ while (*xyz.bufp++); - // get the length + /* get the length */ parse_num(xyz.bufp, &xyz.file_length, NULL, " "); #endif - // The rest of the file name data block quietly discarded + /* The rest of the file name data block quietly discarded */ xyz.tx_ack = true; } xyz.next_blk = 1; xyz.len = 0; return 0; - } else + } else if (stat == xyzModem_timeout) { if (--crc_retries <= 0) xyz.crc_mode = false; - CYGACC_CALL_IF_DELAY_US(5*100000); // Extra delay for startup + CYGACC_CALL_IF_DELAY_US(5*100000); /* Extra delay for startup */ CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); xyz.total_retries++; ZM_DEBUG(zm_dprintf("NAK (%d)\n", __LINE__)); @@ -537,7 +535,7 @@ xyzModem_stream_open(connection_info_t *info, int *err) return -1; } -int +int xyzModem_stream_read(char *buf, int size, int *err) { int stat, total, len; @@ -545,7 +543,7 @@ xyzModem_stream_read(char *buf, int size, int *err) total = 0; stat = xyzModem_cancel; - // Try and get 'size' bytes into the buffer + /* Try and get 'size' bytes into the buffer */ while (!xyz.at_eof && (size > 0)) { if (xyz.len == 0) { retries = xyzModem_MAX_RETRIES; @@ -562,8 +560,8 @@ xyzModem_stream_read(char *buf, int size, int *err) #else if (1) { #endif - // Data blocks can be padded with ^Z (EOF) characters - // This code tries to detect and remove them + /* Data blocks can be padded with ^Z (EOF) characters */ + /* This code tries to detect and remove them */ if ((xyz.bufp[xyz.len-1] == EOF) && (xyz.bufp[xyz.len-2] == EOF) && (xyz.bufp[xyz.len-3] == EOF)) { @@ -574,10 +572,12 @@ xyzModem_stream_read(char *buf, int size, int *err) } #ifdef USE_YMODEM_LENGTH - // See if accumulated length exceeds that of the file. - // If so, reduce size (i.e., cut out pad bytes) - // Only do this for Y-modem (and Z-modem should it ever - // be supported since it can fall back to Y-modem mode). + /* + * See if accumulated length exceeds that of the file. + * If so, reduce size (i.e., cut out pad bytes) + * Only do this for Y-modem (and Z-modem should it ever + * be supported since it can fall back to Y-modem mode). + */ if (xyz.mode != xyzModem_xmodem && 0 != xyz.file_length) { xyz.read_length += xyz.len; if (xyz.read_length > xyz.file_length) { @@ -587,9 +587,9 @@ xyzModem_stream_read(char *buf, int size, int *err) #endif break; } else if (xyz.blk == ((xyz.next_blk - 1) & 0xFF)) { - // Just re-ACK this so sender will get on with it + /* Just re-ACK this so sender will get on with it */ CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); - continue; // Need new header + continue; /* Need new header */ } else { stat = xyzModem_sequence; } @@ -604,7 +604,7 @@ xyzModem_stream_read(char *buf, int size, int *err) CYGACC_COMM_IF_PUTC(*xyz.__chan, (xyz.crc_mode ? 'C' : NAK)); xyz.total_retries++; ZM_DEBUG(zm_dprintf("Reading Final Header\n")); - stat = xyzModem_get_hdr(); + stat = xyzModem_get_hdr(); CYGACC_COMM_IF_PUTC(*xyz.__chan, ACK); ZM_DEBUG(zm_dprintf("FINAL ACK (%d)\n", __LINE__)); } @@ -621,7 +621,7 @@ xyzModem_stream_read(char *buf, int size, int *err) return total; } } - // Don't "read" data from the EOF protocol package + /* Don't "read" data from the EOF protocol package */ if (!xyz.at_eof) { len = xyz.len; if (size < len) len = size; @@ -639,15 +639,15 @@ xyzModem_stream_read(char *buf, int size, int *err) void xyzModem_stream_close(int *err) { - diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", + diag_printf("xyzModem - %s mode, %d(SOH)/%d(STX)/%d(CAN) packets, %d retries\n", xyz.crc_mode ? "CRC" : "Cksum", xyz.total_SOH, xyz.total_STX, xyz.total_CAN, xyz.total_retries); ZM_DEBUG(zm_flush()); } -// Need to be able to clean out the input buffer, so have to take the -// getc +/* Need to be able to clean out the input buffer, so have to take the */ +/* getc */ void xyzModem_stream_terminate(bool abort, int (*getc)(void)) { int c; @@ -657,8 +657,8 @@ void xyzModem_stream_terminate(bool abort, int (*getc)(void)) switch (xyz.mode) { case xyzModem_xmodem: case xyzModem_ymodem: - // The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal - // number of Backspaces is a friendly way to get the other end to abort. + /* The X/YMODEM Spec seems to suggest that multiple CAN followed by an equal */ + /* number of Backspaces is a friendly way to get the other end to abort. */ CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); CYGACC_COMM_IF_PUTC(*xyz.__chan,CAN); @@ -667,29 +667,33 @@ void xyzModem_stream_terminate(bool abort, int (*getc)(void)) CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); CYGACC_COMM_IF_PUTC(*xyz.__chan,BSP); - // Now consume the rest of what's waiting on the line. + /* Now consume the rest of what's waiting on the line. */ ZM_DEBUG(zm_dprintf("Flushing serial line.\n")); xyzModem_flush(); xyz.at_eof = true; break; #ifdef xyzModem_zmodem case xyzModem_zmodem: - // Might support it some day I suppose. + /* Might support it some day I suppose. */ #endif break; } } else { ZM_DEBUG(zm_dprintf("Engaging cleanup mode...\n")); - // Consume any trailing crap left in the inbuffer from - // previous recieved blocks. Since very few files are an exact multiple - // of the transfer block size, there will almost always be some gunk here. - // If we don't eat it now, RedBoot will think the user typed it. + /* + * Consume any trailing crap left in the inbuffer from + * previous recieved blocks. Since very few files are an exact multiple + * of the transfer block size, there will almost always be some gunk here. + * If we don't eat it now, RedBoot will think the user typed it. + */ ZM_DEBUG(zm_dprintf("Trailing gunk:\n")); while ((c = (*getc)()) > -1) ; ZM_DEBUG(zm_dprintf("\n")); - // Make a small delay to give terminal programs like minicom - // time to get control again after their file transfer program - // exits. + /* + * Make a small delay to give terminal programs like minicom + * time to get control again after their file transfer program + * exits. + */ CYGACC_CALL_IF_DELAY_US((cyg_int32)250000); } } @@ -728,12 +732,12 @@ xyzModem_error(int err) } } -// -// RedBoot interface -// -#if 0 // SB +/* + * RedBoot interface + */ +#if 0 /* SB */ GETC_IO_FUNCS(xyzModem_io, xyzModem_stream_open, xyzModem_stream_close, xyzModem_stream_terminate, xyzModem_stream_read, xyzModem_error); RedBoot_load(xmodem, xyzModem_io, false, false, xyzModem_xmodem); RedBoot_load(ymodem, xyzModem_io, false, false, xyzModem_ymodem); -#endif +#endif diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index 5ad4baa94eb..6b6f8282cf3 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -58,7 +58,7 @@ int checkcpu (void) break; } - printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), + printf (" v%d.%d, Core v%d.%d", SVR_MJREV (svr), SVR_MNREV (svr), PVR_MAJ(pvr), PVR_MIN(pvr)); #endif printf (" at %s MHz\n", strmhz (buf, clock)); diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c index 7ca1cebc049..20bba6c66b6 100644 --- a/cpu/mpc83xx/cpu.c +++ b/cpu/mpc83xx/cpu.c @@ -260,7 +260,7 @@ int dma_xfer(void *dest, u32 count, void *src) dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT | DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B | DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN); - + dma->dmamr0 = swab32(dmamr0); __asm__ __volatile__ ("sync"); diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c index b4012a8ddfc..48624feca61 100644 --- a/cpu/mpc83xx/spd_sdram.c +++ b/cpu/mpc83xx/spd_sdram.c @@ -1,7 +1,7 @@ /* * (C) Copyright 2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * + * * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2003 Motorola Inc. * Xianghua Xiao (X.Xiao@motorola.com) @@ -426,7 +426,7 @@ static __inline__ unsigned long get_tbms (void) /* * Initialize all of memory for ECC, then enable errors. */ -//#define CONFIG_DDR_ECC_INIT_VIA_DMA +/* #define CONFIG_DDR_ECC_INIT_VIA_DMA */ void ddr_enable_ecc(unsigned int dram_size) { uint *p; diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index c5ab01738c5..e31d59d80ea 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -18,7 +18,7 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License @@ -38,17 +38,17 @@ #ifndef CFG_SDRAM_TABLE sdram_conf_t mb0cf[] = { - {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ - {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ - {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ - {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ - {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ + {(128 << 20), 13, 0x000A4001}, /* (0-128MB) Address Mode 3, 13x10(4) */ + {(64 << 20), 13, 0x00084001}, /* (0-64MB) Address Mode 3, 13x9(4) */ + {(32 << 20), 12, 0x00062001}, /* (0-32MB) Address Mode 2, 12x9(4) */ + {(16 << 20), 12, 0x00046001}, /* (0-16MB) Address Mode 4, 12x8(4) */ + {(4 << 20), 11, 0x00008001}, /* (0-4MB) Address Mode 5, 11x8(2) */ }; #else sdram_conf_t mb0cf[] = CFG_SDRAM_TABLE; #endif -#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) +#define N_MB0CF (sizeof(mb0cf) / sizeof(mb0cf[0])) #ifndef CONFIG_440 @@ -65,76 +65,76 @@ static ulong ns2clks(ulong ns) static ulong compute_sdtr1(ulong speed) { #ifdef CFG_SDRAM_CASL - ulong tmp; - ulong sdtr1 = 0; - - /* CASL */ - if (CFG_SDRAM_CASL < 2) - sdtr1 |= (1 << SDRAM0_TR_CASL); - else - if (CFG_SDRAM_CASL > 4) - sdtr1 |= (3 << SDRAM0_TR_CASL); - else - sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); - - /* PTA */ - tmp = ns2clks(CFG_SDRAM_PTA); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); - else - sdtr1 |= ((4-1) << SDRAM0_TR_PTA); - - /* CTP */ - tmp = ns2clks(CFG_SDRAM_CTP); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); - else - sdtr1 |= ((4-1) << SDRAM0_TR_CTP); - - /* LDF */ - tmp = ns2clks(CFG_SDRAM_LDF); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); - else - sdtr1 |= ((2-1) << SDRAM0_TR_LDF); - - /* RFTA */ - tmp = ns2clks(CFG_SDRAM_RFTA); - if ((tmp >= 4) && (tmp <= 10)) - sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); - else - sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); - - /* RCD */ - tmp = ns2clks(CFG_SDRAM_RCD); - if ((tmp >= 2) && (tmp <= 4)) - sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); - else - sdtr1 |= ((4-1) << SDRAM0_TR_RCD); - - return sdtr1; + ulong tmp; + ulong sdtr1 = 0; + + /* CASL */ + if (CFG_SDRAM_CASL < 2) + sdtr1 |= (1 << SDRAM0_TR_CASL); + else + if (CFG_SDRAM_CASL > 4) + sdtr1 |= (3 << SDRAM0_TR_CASL); + else + sdtr1 |= ((CFG_SDRAM_CASL-1) << SDRAM0_TR_CASL); + + /* PTA */ + tmp = ns2clks(CFG_SDRAM_PTA); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_PTA); + else + sdtr1 |= ((4-1) << SDRAM0_TR_PTA); + + /* CTP */ + tmp = ns2clks(CFG_SDRAM_CTP); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_CTP); + else + sdtr1 |= ((4-1) << SDRAM0_TR_CTP); + + /* LDF */ + tmp = ns2clks(CFG_SDRAM_LDF); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_LDF); + else + sdtr1 |= ((2-1) << SDRAM0_TR_LDF); + + /* RFTA */ + tmp = ns2clks(CFG_SDRAM_RFTA); + if ((tmp >= 4) && (tmp <= 10)) + sdtr1 |= ((tmp-4) << SDRAM0_TR_RFTA); + else + sdtr1 |= ((10-4) << SDRAM0_TR_RFTA); + + /* RCD */ + tmp = ns2clks(CFG_SDRAM_RCD); + if ((tmp >= 2) && (tmp <= 4)) + sdtr1 |= ((tmp-1) << SDRAM0_TR_RCD); + else + sdtr1 |= ((4-1) << SDRAM0_TR_RCD); + + return sdtr1; #else /* CFG_SDRAM_CASL */ - /* - * If no values are configured in the board config file - * use the default values, which seem to be ok for most - * boards. - * - * REMARK: - * For new board ports we strongly recommend to define the - * correct values for the used SDRAM chips in your board - * config file (see PPChameleonEVB.h) - */ - if (speed > 100000000) { - /* - * 133 MHz SDRAM - */ - return 0x01074015; - } else { - /* - * default: 100 MHz SDRAM - */ - return 0x0086400d; - } + /* + * If no values are configured in the board config file + * use the default values, which seem to be ok for most + * boards. + * + * REMARK: + * For new board ports we strongly recommend to define the + * correct values for the used SDRAM chips in your board + * config file (see PPChameleonEVB.h) + */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ + return 0x01074015; + } else { + /* + * default: 100 MHz SDRAM + */ + return 0x0086400d; + } #endif /* CFG_SDRAM_CASL */ } @@ -142,24 +142,24 @@ static ulong compute_sdtr1(ulong speed) static ulong compute_rtr(ulong speed, ulong rows, ulong refresh) { #ifdef CFG_SDRAM_CASL - ulong tmp; + ulong tmp; - tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); - tmp /= 1000000; + tmp = ((refresh*1000*1000) / (1 << rows)) * (speed / 1000); + tmp /= 1000000; - return ((tmp & 0x00003FF8) << 16); + return ((tmp & 0x00003FF8) << 16); #else /* CFG_SDRAM_CASL */ - if (speed > 100000000) { - /* - * 133 MHz SDRAM - */ + if (speed > 100000000) { + /* + * 133 MHz SDRAM + */ return 0x07f00000; - } else { - /* - * default: 100 MHz SDRAM - */ + } else { + /* + * default: 100 MHz SDRAM + */ return 0x05f00000; - } + } #endif /* CFG_SDRAM_CASL */ } @@ -172,19 +172,19 @@ void sdram_init(void) ulong sdtr1; int i; - /* - * Determine SDRAM speed - */ - speed = get_bus_freq(0); /* parameter not used on ppc4xx */ + /* + * Determine SDRAM speed + */ + speed = get_bus_freq(0); /* parameter not used on ppc4xx */ - /* - * sdtr1 (register SDRAM0_TR) must take into account timings listed - * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into - * account actual SDRAM size. So we can set up sdtr1 according to what - * is specified in board configuration file while rtr dependds on SDRAM - * size we are assuming before detection. - */ - sdtr1 = compute_sdtr1(speed); + /* + * sdtr1 (register SDRAM0_TR) must take into account timings listed + * in SDRAM chip datasheet. rtr (register SDRAM0_RTR) must take into + * account actual SDRAM size. So we can set up sdtr1 according to what + * is specified in board configuration file while rtr dependds on SDRAM + * size we are assuming before detection. + */ + sdtr1 = compute_sdtr1(speed); for (i=0; i Date: Wed, 19 Apr 2006 11:52:46 +0200 Subject: Update for NC650 board. Add NC650 based CP850 configuration. Signed-off-by: dzu@denx.de --- CHANGELOG | 5 ++++ Makefile | 17 ++++++++++-- board/nc650/Makefile | 3 ++- board/nc650/config.mk | 2 ++ board/nc650/nc650.c | 72 ++++++++++++++++++++++++++++++++++++++++++++----- include/configs/NC650.h | 66 ++++++++++++++++++++++++++++++++------------- 6 files changed, 137 insertions(+), 28 deletions(-) (limited to 'include') diff --git a/CHANGELOG b/CHANGELOG index cbc18d93695..6edcd25a9d2 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,6 +2,11 @@ Changes since U-Boot 1.1.4: ====================================================================== +* Update for NC650 board: + - Support rev1 and rev2 hardware + - adapt to new NAND layer + - add CP850 configuration based on NC650 + * MPC5200: enable snooping of DMA transactions on XLB even if no PCI is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail. diff --git a/Makefile b/Makefile index 9b93463000f..249c9f03f65 100644 --- a/Makefile +++ b/Makefile @@ -633,8 +633,21 @@ NETTA2_config: unconfig } @./mkconfig -a $(call xtract_NETTA2,$@) ppc mpc8xx netta2 -NC650_config: unconfig - @./mkconfig $(@:_config=) ppc mpc8xx nc650 +NC650_Rev1_config \ +NC650_Rev2_config \ +CP850_config: unconfig + @ >include/config.h + @[ -z "$(findstring CP850,$@)" ] || \ + { echo "#define CONFIG_CP850 1" >>include/config.h ; \ + echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \ + } + @[ -z "$(findstring Rev1,$@)" ] || \ + { echo "#define CONFIG_IDS852_REV1 1" >>include/config.h ; \ + } + @[ -z "$(findstring Rev2,$@)" ] || \ + { echo "#define CONFIG_IDS852_REV2 1" >>include/config.h ; \ + } + @./mkconfig -a NC650 ppc mpc8xx nc650 NX823_config: unconfig @./mkconfig $(@:_config=) ppc mpc8xx nx823 diff --git a/board/nc650/Makefile b/board/nc650/Makefile index a4dd85f508d..8dc4934f794 100644 --- a/board/nc650/Makefile +++ b/board/nc650/Makefile @@ -1,4 +1,5 @@ # +# (C) Copyright 2006 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -25,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = lib$(BOARD).a -OBJS = $(BOARD).o flash.o +OBJS = $(BOARD).o nand.o flash.o $(LIB): .depend $(OBJS) $(AR) crv $@ $(OBJS) diff --git a/board/nc650/config.mk b/board/nc650/config.mk index fa8ba3186ca..5b2284aec4d 100644 --- a/board/nc650/config.mk +++ b/board/nc650/config.mk @@ -1,4 +1,5 @@ # +# (C) Copyright 2006 Detlev Zundel, dzu@denx.de # (C) Copyright 2004 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # @@ -26,3 +27,4 @@ # TEXT_BASE = 0x40700000 +BOARDLIBS = drivers/nand/libnand.a diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c index fe96b93816f..c90ac9c955b 100644 --- a/board/nc650/nc650.c +++ b/board/nc650/nc650.c @@ -1,4 +1,5 @@ /* + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -108,7 +109,16 @@ const uint nand_flash_table[] = { int checkboard (void) { - puts ("Board: NC650\n"); +#if !defined(CONFIG_CP850) + puts ("Board: NC650"); +#else + puts ("Board: CP850"); +#endif +#if defined(CONFIG_IDS852_REV1) + puts (" with IDS852 rev 1 module\n"); +#elif defined(CONFIG_IDS852_REV2) + puts (" with IDS852 rev 2 module\n"); +#endif return 0; } @@ -241,13 +251,61 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize return (get_ram_size(base, maxsize)); } -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -void nand_init(void) -{ - extern unsigned long nand_probe(unsigned long physadr); - unsigned long totlen = nand_probe(CFG_NAND_BASE); +#if defined(CONFIG_CP850) + +#define DPRAM_VARNAME "KP850DIP" +#define PARAM_ADDR 0x7C0 +#define NAME_ADDR 0x7F8 +#define BOARD_NAME "KP01" +#define DEFAULT_LB "241111" - printf ("%4lu MB\n", totlen >> 20); +int misc_init_r(void) +{ + int iCompatMode = 0; + char *pParam = NULL; + char *envlb; + + /* + First byte in CPLD read address space signals compatibility mode + 0 - cp850 + 1 - kp852 + */ + pParam = (char*)(CFG_CPLD_BASE); + if( *pParam != 0) + iCompatMode = 1; + + if ( iCompatMode != 0) { + /* + In KP852 compatibility mode we have to write to + DPRAM as early as possible the binary coded + line config and board name. + The line config is derived from the environment + variable DPRAM_VARNAME by converting from ASCII + to binary per character. + */ + if ( (envlb = getenv ( DPRAM_VARNAME )) == 0) { + setenv( DPRAM_VARNAME, DEFAULT_LB); + envlb = DEFAULT_LB; + } + + /* Status string */ + printf("Mode: KP852(LB=%s)\n", envlb); + + /* copy appl init */ + pParam = (char*)(DPRAM_BASE_ADDR + PARAM_ADDR); + while (*envlb) { + *(pParam++) = *(envlb++) - '0'; + } + *pParam = '\0'; + + /* copy board id */ + pParam = (char*)(DPRAM_BASE_ADDR + NAME_ADDR); + strcpy( pParam, BOARD_NAME); + } else { + puts("Mode: CP850\n"); + } + + return 0; } #endif diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 3c59df4f45f..8da29c4afc0 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,4 +1,5 @@ /* + * (C) Copyright 2006 Detlev Zundel, dzu@denx.de * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * @@ -65,6 +66,11 @@ #define CFG_8XX_XIN CONFIG_8xx_OSCLK #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d seconds...\n" +#define CONFIG_AUTOBOOT_DELAY_STR "ids" +#define CONFIG_BOOT_RETRY_TIME 900 +#define CONFIG_BOOT_RETRY_MIN 30 #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" @@ -75,7 +81,7 @@ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ #undef CONFIG_STATUS_LED /* Status LED disabled */ @@ -96,12 +102,26 @@ /* * Software (bit-bang) I2C driver configuration */ +#if defined(CONFIG_IDS852_REV1) + #define SCL 0x1000 /* PA 3 */ #define SDA 0x2000 /* PA 2 */ #define __I2C_DIR immr->im_ioport.iop_padir #define __I2C_DAT immr->im_ioport.iop_padat #define __I2C_PAR immr->im_ioport.iop_papar + +#elif defined(CONFIG_IDS852_REV2) + +#define SCL 0x0002 /* PB 30 */ +#define SDA 0x0001 /* PB 31 */ + +#define __I2C_PAR immr->im_cpm.cp_pbpar +#define __I2C_DIR immr->im_cpm.cp_pbdir +#define __I2C_DAT immr->im_cpm.cp_pbdat + +#endif + #define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ __I2C_DIR |= (SDA|SCL); } #define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) @@ -229,17 +249,6 @@ #define ADDR_COLUMN 1 #define NAND_NO_RB -#define NAND_WAIT_READY(nand) udelay(12) -#define WRITE_NAND_COMMAND(d, adr) WRITE_NAND(d, adr + 2) -#define WRITE_NAND_ADDRESS(d, adr) WRITE_NAND(d, adr + 1) -#define WRITE_NAND(d, adr) (*(volatile uint8_t *)(adr) = (uint8_t)(d)) -#define READ_NAND(adr) (*(volatile uint8_t *)(adr)) -#define NAND_DISABLE_CE(nand) /* nop */ -#define NAND_ENABLE_CE(nand) /* nop */ -#define NAND_CTL_CLRALE(nandptr) /* nop */ -#define NAND_CTL_SETALE(nandptr) /* nop */ -#define NAND_CTL_CLRCLE(nandptr) /* nop */ -#define NAND_CTL_SETCLE(nandptr) /* nop */ /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 @@ -312,7 +321,8 @@ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) /* - * BR2 and OR2 (NAND Flash) - now addressed through UPMB + * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1 + * rev2 only uses the chipselect */ #define CFG_NAND_BASE 0x50000000 #define CFG_NAND_SIZE 0x04000000 @@ -337,6 +347,18 @@ #define CFG_OR3_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM) #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) +/* + * BR4 and OR4 (CPLD) + */ +#define CFG_CPLD_BASE 0x80000000 /* CPLD */ +#define CFG_CPLD_SIZE 0x10000 /* only 16 used */ + +#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_1_CLK) + +#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD) + /* * BR5 and OR5 (SRAM) */ @@ -349,6 +371,16 @@ #define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) #define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) +#if defined(CONFIG_CP850) +/* + * BR6 and OR6 (DPRAM) - only on CP850 + */ +#define CFG_OR6_PRELIM 0xffff8170 +#define CFG_BR6_PRELIM 0xa0000401 +#define DPRAM_BASE_ADDR 0xa0000000 + +#define CONFIG_MISC_INIT_R 1 +#endif /* * 4096 Rows from SDRAM example configuration @@ -413,14 +445,12 @@ #define CONFIG_JFFS2_PART_OFFSET 0x00000000 /* mtdparts command line support */ -/* #define CONFIG_JFFS2_CMDLINE #define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" #define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ - "2560k(cramfs1),2560k(cramfs2)," \ - "256k(u-boot),256k(env);" \ - "nc650-nand:4m(nand1),28m(nand2)" -*/ + "4m(cramfs1),1m(cramfs2)," \ + "256k(u-boot),128k(env);" \ + "nc650-nand:4m(jffs1),28m(jffs2)" #endif /* __CONFIG_H */ -- cgit v1.3.1