From bc2ad9f04dd9d15e7134f7e1b6386d1995772d69 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Feb 2015 20:06:05 +0100 Subject: lsxl: use default load addresses for legacy boot The load addresses for the bootcmd_legacy script were taken from the original bootloader from Buffalo. But newer kernels are too big and the uncompressing will overwrite parts of the initial ramdisk. Therefore, we switch to the load addresses which are also used by the other boot script. Signed-off-by: Michael Walle --- include/configs/lsxl.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index a14bfe3a85a..6c8e369861a 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -127,9 +127,9 @@ "ramdisk_addr=0x01000000\0" \ "fdt_addr=0x01ff0000\0" \ "bootcmd_legacy=ide reset " \ - "&& load ide ${hdpart} 0x00100000 /uImage.buffalo " \ - "&& load ide ${hdpart} 0x00800000 /initrd.buffalo " \ - "&& bootm 0x00100000 0x00800000\0" \ + "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \ + "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ + "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ "bootcmd_net=bootp ${kernel_addr} uImage " \ "&& tftpboot ${ramdisk_addr} uInitrd " \ "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ -- cgit v1.3.1 From 145df6fe2a5897cfda0ca2992d0e08cdb9cc0cde Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Feb 2015 20:06:06 +0100 Subject: lsxl: place the dtb below the inital ramdisk The dtb was loaded at a memory address after the initial ramdisk. Thus a large ramdisk would overwrite the dtb. Move it to "ramdisk_start - 64k". 64k should be enough for the device tree blob. Also the kernel documentation arm/Booting suggests to put the dtb before the initial ramdisk. Signed-off-by: Michael Walle --- include/configs/lsxl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index 6c8e369861a..dff90250a01 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -125,7 +125,7 @@ "hdpart=0:1\0" \ "kernel_addr=0x00800000\0" \ "ramdisk_addr=0x01000000\0" \ - "fdt_addr=0x01ff0000\0" \ + "fdt_addr=0x00ff0000\0" \ "bootcmd_legacy=ide reset " \ "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \ "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ -- cgit v1.3.1 From 4fe49d7becc2dfb7288f8b265e0976428b64323c Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Sun, 8 Feb 2015 20:06:07 +0100 Subject: lsxl: switch from bootm to bootz for boot commands Use the bootz command to load zImages in case of any new boot scripts. Only the legacy one will still use bootm. Apart form the fact, that this will simplify the image generation process, it saves one copy of the kernel image: Common practice is to generate an uImage with a loading address of 0x8000. This uImage contains a compressed zImage, which will unpack the kernel image to the beginning of the RAM. But because there is already the compressed image the uncompressor first relocates the compressed image to a higher location. The load address is encoded into the uImage which is generated by the distributions and thus cannot be easily changed. By using the bootz command we can load the compressed image to a higher memory address and the decompressor doesn't have to reloacte the image. Signed-off-by: Michael Walle --- include/configs/lsxl.h | 34 +++++++++++++++++++++------------- 1 file changed, 21 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h index dff90250a01..c354c292960 100644 --- a/include/configs/lsxl.h +++ b/include/configs/lsxl.h @@ -56,6 +56,7 @@ * Commands configuration */ #include +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_DHCP #define CONFIG_CMD_ELF #define CONFIG_CMD_ENV @@ -78,6 +79,9 @@ */ #include "mv-common.h" +/* loading initramfs images without uimage header */ +#define CONFIG_SUPPORT_RAW_INITRD + /* ST M25P40 */ #undef CONFIG_SPI_FLASH_MACRONIX #define CONFIG_SPI_FLASH_STMICRO @@ -130,22 +134,26 @@ "&& load ide ${hdpart} ${kernel_addr} /uImage.buffalo " \ "&& load ide ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "bootcmd_net=bootp ${kernel_addr} uImage " \ - "&& tftpboot ${ramdisk_addr} uInitrd " \ + "bootcmd_net=bootp ${kernel_addr} vmlinuz " \ + "&& tftpboot ${ramdisk_addr} initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ - "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ "bootcmd_hdd=ide reset " \ - "&& load ide ${hdpart} ${kernel_addr} /uImage " \ - "&& load ide ${hdpart} ${ramdisk_addr} /uInitrd " \ - "&& load ide ${hdpart} ${fdt_addr} " \ - "/" CONFIG_FDTFILE " " \ - "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "&& load ide ${hdpart} ${kernel_addr} /vmlinuz " \ + "&& load ide ${hdpart} ${ramdisk_addr} /initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ + "&& load ide ${hdpart} ${fdt_addr} /dtb " \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ "bootcmd_usb=usb start " \ - "&& load usb 0:1 ${kernel_addr} /uImage " \ - "&& load usb 0:1 ${ramdisk_addr} /uInitrd " \ - "&& load usb 0:1 ${fdt_addr} " \ - "/" CONFIG_FDTFILE " " \ - "&& bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "&& load usb 0:1 ${kernel_addr} /vmlinuz " \ + "&& load usb 0:1 ${ramdisk_addr} /initrd.img " \ + "&& setenv ramdisk_len ${filesize} " \ + "&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \ + "&& bootz ${kernel_addr} " \ + "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ "eraseenv=sf probe 0 " \ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ -- cgit v1.3.1 From 0bca284b1795942ac8fdd1646f04f49e478f0bcc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 11:51:36 -0700 Subject: powerpc: ppc4xx: canyonlands: config: Tidy up CONFIGs and config.mk Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk Signed-off-by: Simon Glass --- arch/powerpc/cpu/ppc4xx/config.mk | 5 +---- board/amcc/canyonlands/config.mk | 2 -- include/configs/canyonlands.h | 34 +++++++++++++++++----------------- 3 files changed, 18 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/arch/powerpc/cpu/ppc4xx/config.mk b/arch/powerpc/cpu/ppc4xx/config.mk index f87c9dc49be..9cb41bb3b53 100644 --- a/arch/powerpc/cpu/ppc4xx/config.mk +++ b/arch/powerpc/cpu/ppc4xx/config.mk @@ -7,10 +7,7 @@ PLATFORM_CPPFLAGS += -mstring -msoft-float -cfg=$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME:"%"=%).h -is440:=$(shell grep CONFIG_440 $(cfg)) - -ifneq (,$(findstring CONFIG_440,$(is440))) +ifneq (,$(CONFIG_440)) PLATFORM_CPPFLAGS += -Wa,-m440 -mcpu=440 else PLATFORM_CPPFLAGS += -Wa,-m405 -mcpu=405 diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk index 63b89737004..5cc90d20509 100644 --- a/board/amcc/canyonlands/config.mk +++ b/board/amcc/canyonlands/config.mk @@ -8,8 +8,6 @@ # AMCC 460EX/460GT Evaluation Board (Canyonlands) board # -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 8eeb15c0e10..7b1f368375a 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -19,10 +19,10 @@ * and Arches dual (460GT) */ #ifdef CONFIG_CANYONLANDS -#define CONFIG_460EX 1 /* Specific PPC460EX */ +#define CONFIG_460EX /* Specific PPC460EX */ #define CONFIG_HOSTNAME canyonlands #else -#define CONFIG_460GT 1 /* Specific PPC460GT */ +#define CONFIG_460GT /* Specific PPC460GT */ #ifdef CONFIG_GLACIER #define CONFIG_HOSTNAME glacier #else @@ -32,7 +32,7 @@ #endif #endif -#define CONFIG_440 1 +#define CONFIG_440 #ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0xFFF80000 @@ -45,10 +45,10 @@ #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */ -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */ -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ -#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */ +#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */ +#define CONFIG_MISC_INIT_R /* Call misc_init_r */ +#define CONFIG_BOARD_TYPES /* support board types */ /*----------------------------------------------------------------------- * Base addresses -- Note these are effective addresses where the @@ -134,7 +134,7 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ +#define CONFIG_SYS_FLASH_CFI_AMD_RESET /* Use AMD (Spansion) reset cmd */ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ @@ -172,9 +172,9 @@ * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot * code. */ -#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/ -#define CONFIG_DDR_ECC 1 /* with ECC support */ +#define CONFIG_DDR_ECC /* with ECC support */ #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */ #else /* defined(CONFIG_ARCHES) */ @@ -262,8 +262,8 @@ #define CONFIG_4xx_CONFIG_BLOCKSIZE 16 /* I2C SYSMON (LM75, AD7414 is almost compatible) */ -#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ -#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_LM75 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 /* use AD7414 */ #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ #define CONFIG_SYS_DTT_MAX_TEMP 70 #define CONFIG_SYS_DTT_LOW_TEMP -30 @@ -275,14 +275,14 @@ #if !defined(CONFIG_ARCHES) /* RTC configuration */ -#define CONFIG_RTC_M41T62 1 +#define CONFIG_RTC_M41T62 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 #endif /*----------------------------------------------------------------------- * Ethernet *----------------------------------------------------------------------*/ -#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_IBM_EMAC4_V4 #define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 @@ -322,9 +322,9 @@ #define CONFIG_GPCS_PHY2_ADDR 0xC #endif /* !defined(CONFIG_ARCHES) */ -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_PHY_DYNAMIC_ANEG 1 +#define CONFIG_PHY_RESET /* reset phy upon startup */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#define CONFIG_PHY_DYNAMIC_ANEG /*----------------------------------------------------------------------- * USB-OHCI -- cgit v1.3.1 From 6566041c0bf9523becf5292e45a0f5c3686ebdd4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 11:51:37 -0700 Subject: powerpc: ppc4xx: Move CANYONLANDS/GLACIER/ARCHES to Kconfig Move these options to Kconfig and remove them from the CONFIG files. Signed-off-by: Simon Glass --- board/amcc/canyonlands/Kconfig | 20 ++++++++++++++++++++ configs/arches_defconfig | 2 +- configs/canyonlands_defconfig | 2 +- configs/glacier_defconfig | 2 +- include/configs/canyonlands.h | 2 ++ 5 files changed, 25 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 530a6efd60b..0fc687739ca 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -9,4 +9,24 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "canyonlands" +choice BOARD_TYPE + prompt "Select which board to build for" + +config CANYONLANDS + bool "Glacier" + help + Select this to build for the Canyonlands 460EX board. + +config GLACIER + bool "Glacier" + help + Select this to build for the Glacier 460GT board. + +config ARCHES + bool "Arches" + help + Select this to build for the Arches dual 460GT board. + +endchoice + endif diff --git a/configs/arches_defconfig b/configs/arches_defconfig index 18d0a140da6..60e6ef9098d 100644 --- a/configs/arches_defconfig +++ b/configs/arches_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="ARCHES" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_ARCHES=y diff --git a/configs/canyonlands_defconfig b/configs/canyonlands_defconfig index 09b9ab93307..37a2b4d7968 100644 --- a/configs/canyonlands_defconfig +++ b/configs/canyonlands_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="CANYONLANDS" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_CANYONLANDS=y diff --git a/configs/glacier_defconfig b/configs/glacier_defconfig index 2a66bfb08c7..436b9f8d031 100644 --- a/configs/glacier_defconfig +++ b/configs/glacier_defconfig @@ -1,4 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="GLACIER" CONFIG_PPC=y CONFIG_4xx=y CONFIG_TARGET_CANYONLANDS=y +CONFIG_GLACIER=y diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 7b1f368375a..ed790ccaf3a 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -11,6 +11,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -- cgit v1.3.1 From 1d60f2b9860d3ba3563718d479a455495197f00d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 11:51:39 -0700 Subject: powerpc: ppc4xx: canyonlands: Move to generic board Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass --- arch/powerpc/cpu/ppc4xx/cpu_init.c | 2 ++ include/configs/canyonlands.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index e5a0e21e369..5f5c72002e4 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -450,10 +450,12 @@ cpu_init_f (void) PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ +#ifndef CONFIG_SYS_GENERIC_BOARD gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); /* Clear initial global data */ memset((void *)gd, 0, sizeof(gd_t)); +#endif } /* diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index ed790ccaf3a..7a1499d2e3a 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -13,6 +13,8 @@ #include +#define CONFIG_SYS_GENERIC_BOARD + /*----------------------------------------------------------------------- * High Level Configuration Options *----------------------------------------------------------------------*/ -- cgit v1.3.1 From 0e7806d24a77179053c64ba481b3857805e061c8 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 11:51:46 -0700 Subject: ppc: amcc: Omit unneeded ns16550 CONFIG if using driver model This comes from the device tree or a call to get_uart_clock(). Signed-off-by: Simon Glass --- arch/powerpc/include/asm/ppc460ex_gt.h | 2 ++ include/configs/amcc-common.h | 2 ++ 2 files changed, 4 insertions(+) (limited to 'include') diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h index f41df0da6a2..ea019aafdb0 100644 --- a/arch/powerpc/include/asm/ppc460ex_gt.h +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -19,10 +19,12 @@ /* Memory mapped registers */ #define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) +#endif #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 2aea89937a2..73e1b0afa80 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -20,8 +20,10 @@ */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} -- cgit v1.3.1 From 0da0fcd51f6566d84eb24cbbd4c8ad784c702849 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 19 Jan 2015 22:16:08 -0700 Subject: net: Use new checksum functions Drop the old checksum functions in favour of the new ones. Signed-off-by: Simon Glass Acked-by: Joe Hershberger --- include/net.h | 4 ---- net/net.c | 25 ++----------------------- net/ping.c | 10 ++++------ 3 files changed, 6 insertions(+), 33 deletions(-) (limited to 'include') diff --git a/include/net.h b/include/net.h index 73ea88b42d7..43e3d28729e 100644 --- a/include/net.h +++ b/include/net.h @@ -512,10 +512,6 @@ unsigned add_ip_checksums(unsigned offset, unsigned sum, unsigned new_sum); */ int ip_checksum_ok(const void *addr, unsigned nbytes); -/* Checksum */ -extern int NetCksumOk(uchar *, int); /* Return true if cksum OK */ -extern uint NetCksum(uchar *, int); /* Calculate the checksum */ - /* Callbacks */ extern rxhand_f *net_get_udp_handler(void); /* Get UDP RX packet handler */ extern void net_set_udp_handler(rxhand_f *); /* Set UDP RX packet handler */ diff --git a/net/net.c b/net/net.c index 2bea07b3cdf..b60ce6242ce 100644 --- a/net/net.c +++ b/net/net.c @@ -1086,7 +1086,7 @@ NetReceive(uchar *inpkt, int len) if ((ip->ip_hl_v & 0x0f) > 0x05) return; /* Check the Checksum of the header */ - if (!NetCksumOk((uchar *)ip, IP_HDR_SIZE / 2)) { + if (!ip_checksum_ok((uchar *)ip, IP_HDR_SIZE)) { debug("checksum bad\n"); return; } @@ -1290,27 +1290,6 @@ common: } /**********************************************************************/ -int -NetCksumOk(uchar *ptr, int len) -{ - return !((NetCksum(ptr, len) + 1) & 0xfffe); -} - - -unsigned -NetCksum(uchar *ptr, int len) -{ - ulong xsum; - ushort *p = (ushort *)ptr; - - xsum = 0; - while (len-- > 0) - xsum += *p++; - xsum = (xsum & 0xffff) + (xsum >> 16); - xsum = (xsum & 0xffff) + (xsum >> 16); - return xsum & 0xffff; -} - int NetEthHdrSize(void) { @@ -1410,7 +1389,7 @@ void net_set_udp_header(uchar *pkt, IPaddr_t dest, int dport, int sport, net_set_ip_header(pkt, dest, NetOurIP); ip->ip_len = htons(IP_UDP_HDR_SIZE + len); ip->ip_p = IPPROTO_UDP; - ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1); + ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); ip->udp_src = htons(sport); ip->udp_dst = htons(dport); diff --git a/net/ping.c b/net/ping.c index 2be56ed9295..366f51825f9 100644 --- a/net/ping.c +++ b/net/ping.c @@ -29,14 +29,14 @@ static void set_icmp_header(uchar *pkt, IPaddr_t dest) ip->ip_len = htons(IP_ICMP_HDR_SIZE); ip->ip_p = IPPROTO_ICMP; - ip->ip_sum = ~NetCksum((uchar *)ip, IP_HDR_SIZE >> 1); + ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); icmp->type = ICMP_ECHO_REQUEST; icmp->code = 0; icmp->checksum = 0; icmp->un.echo.id = 0; icmp->un.echo.sequence = htons(PingSeqNo++); - icmp->checksum = ~NetCksum((uchar *)icmp, ICMP_HDR_SIZE >> 1); + icmp->checksum = compute_ip_checksum(icmp, ICMP_HDR_SIZE); } static int ping_send(void) @@ -101,13 +101,11 @@ void ping_receive(struct ethernet_hdr *et, struct ip_udp_hdr *ip, int len) ip->ip_off = 0; NetCopyIP((void *)&ip->ip_dst, &ip->ip_src); NetCopyIP((void *)&ip->ip_src, &NetOurIP); - ip->ip_sum = ~NetCksum((uchar *)ip, - IP_HDR_SIZE >> 1); + ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); icmph->type = ICMP_ECHO_REPLY; icmph->checksum = 0; - icmph->checksum = ~NetCksum((uchar *)icmph, - (len - IP_HDR_SIZE) >> 1); + icmph->checksum = compute_ip_checksum(icmph, len - IP_HDR_SIZE); NetSendPacket((uchar *)et, eth_hdr_size + len); return; /* default: -- cgit v1.3.1 From ca88b9b93916f66c6737527aa955d2c1b4758080 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:32 -0700 Subject: dm: i2c: Add a dm_ prefix to driver model bus speed functions As with i2c_read() and i2c_write(), add a dm_ prefix to the driver model versions of these functions to avoid conflicts. Signed-off-by: Simon Glass Acked-by: Heiko Schocher --- common/cmd_i2c.c | 4 ++-- drivers/i2c/i2c-uclass.c | 11 +++-------- include/i2c.h | 8 ++++---- test/dm/i2c.c | 6 +++--- 4 files changed, 12 insertions(+), 17 deletions(-) (limited to 'include') diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 7c3ad00fdf0..fe8f77aaec0 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1730,7 +1730,7 @@ static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const #endif if (argc == 1) { #ifdef CONFIG_DM_I2C - speed = i2c_get_bus_speed(bus); + speed = dm_i2c_get_bus_speed(bus); #else speed = i2c_get_bus_speed(); #endif @@ -1740,7 +1740,7 @@ static int do_i2c_bus_speed(cmd_tbl_t * cmdtp, int flag, int argc, char * const speed = simple_strtoul(argv[1], NULL, 10); printf("Setting bus speed to %d Hz\n", speed); #ifdef CONFIG_DM_I2C - ret = i2c_set_bus_speed(bus, speed); + ret = dm_i2c_set_bus_speed(bus, speed); #else ret = i2c_set_bus_speed(speed); #endif diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c index eafa457845d..a6991bf875d 100644 --- a/drivers/i2c/i2c-uclass.c +++ b/drivers/i2c/i2c-uclass.c @@ -325,7 +325,7 @@ int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, return ret; } -int i2c_set_bus_speed(struct udevice *bus, unsigned int speed) +int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) { struct dm_i2c_ops *ops = i2c_get_ops(bus); struct dm_i2c_bus *i2c = bus->uclass_priv; @@ -346,12 +346,7 @@ int i2c_set_bus_speed(struct udevice *bus, unsigned int speed) return 0; } -/* - * i2c_get_bus_speed: - * - * Returns speed of selected I2C bus in Hz - */ -int i2c_get_bus_speed(struct udevice *bus) +int dm_i2c_get_bus_speed(struct udevice *bus) { struct dm_i2c_ops *ops = i2c_get_ops(bus); struct dm_i2c_bus *i2c = bus->uclass_priv; @@ -440,7 +435,7 @@ static int i2c_post_probe(struct udevice *dev) i2c->speed_hz = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "clock-frequency", 100000); - return i2c_set_bus_speed(dev, i2c->speed_hz); + return dm_i2c_set_bus_speed(dev, i2c->speed_hz); } static int i2c_post_bind(struct udevice *dev) diff --git a/include/i2c.h b/include/i2c.h index 27fe00f1736..1635e9ac06c 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -125,21 +125,21 @@ int dm_i2c_probe(struct udevice *bus, uint chip_addr, uint chip_flags, struct udevice **devp); /** - * i2c_set_bus_speed() - set the speed of a bus + * dm_i2c_set_bus_speed() - set the speed of a bus * * @bus: Bus to adjust * @speed: Requested speed in Hz * @return 0 if OK, -EINVAL for invalid values */ -int i2c_set_bus_speed(struct udevice *bus, unsigned int speed); +int dm_i2c_set_bus_speed(struct udevice *bus, unsigned int speed); /** - * i2c_get_bus_speed() - get the speed of a bus + * dm_i2c_get_bus_speed() - get the speed of a bus * * @bus: Bus to check * @return speed of selected I2C bus in Hz, -ve on error */ -int i2c_get_bus_speed(struct udevice *bus); +int dm_i2c_get_bus_speed(struct udevice *bus); /** * i2c_set_chip_flags() - set flags for a chip diff --git a/test/dm/i2c.c b/test/dm/i2c.c index ef88372d563..541b73b8037 100644 --- a/test/dm/i2c.c +++ b/test/dm/i2c.c @@ -67,10 +67,10 @@ static int dm_test_i2c_speed(struct dm_test_state *dms) ut_assertok(uclass_get_device_by_seq(UCLASS_I2C, busnum, &bus)); ut_assertok(i2c_get_chip(bus, chip, 1, &dev)); - ut_assertok(i2c_set_bus_speed(bus, 100000)); + ut_assertok(dm_i2c_set_bus_speed(bus, 100000)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); - ut_assertok(i2c_set_bus_speed(bus, 400000)); - ut_asserteq(400000, i2c_get_bus_speed(bus)); + ut_assertok(dm_i2c_set_bus_speed(bus, 400000)); + ut_asserteq(400000, dm_i2c_get_bus_speed(bus)); ut_assertok(dm_i2c_read(dev, 0, buf, 5)); ut_asserteq(-EINVAL, dm_i2c_write(dev, 0, buf, 5)); -- cgit v1.3.1 From fffff7268b6c30dc7058d3615021628d4f60fac5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:33 -0700 Subject: dm: i2c: Make API accessible even without CONFIG_DM Make the driver model I2C API available always, even if driver model is not enabled. This allows for a 'soft' switch-over, where drivers can use the new structures in code which is compiled but not yet used. This makes migration easier in some cases. Fix up the existing drivers which define their own 'struct i2c_msg'. Signed-off-by: Simon Glass Acked-by: Heiko Schocher --- drivers/i2c/adi_i2c.c | 6 +++--- drivers/i2c/kona_i2c.c | 16 ++++++++-------- drivers/i2c/mv_i2c.c | 10 +++++----- include/i2c.h | 5 +---- 4 files changed, 17 insertions(+), 20 deletions(-) (limited to 'include') diff --git a/drivers/i2c/adi_i2c.c b/drivers/i2c/adi_i2c.c index 20495b1d7f8..c58f14a36e5 100644 --- a/drivers/i2c/adi_i2c.c +++ b/drivers/i2c/adi_i2c.c @@ -63,7 +63,7 @@ struct twi_regs { #endif /* All transfers are described by this data structure */ -struct i2c_msg { +struct adi_i2c_msg { u8 flags; #define I2C_M_COMBO 0x4 #define I2C_M_STOP 0x2 @@ -81,7 +81,7 @@ struct i2c_msg { * wait_for_completion - manage the actual i2c transfer * @msg: the i2c msg */ -static int wait_for_completion(struct twi_regs *twi, struct i2c_msg *msg) +static int wait_for_completion(struct twi_regs *twi, struct adi_i2c_msg *msg) { u16 int_stat, ctl; ulong timebase = get_timer(0); @@ -151,7 +151,7 @@ static int i2c_transfer(struct i2c_adapter *adap, uint8_t chip, uint addr, (addr >> 8), (addr >> 16), }; - struct i2c_msg msg = { + struct adi_i2c_msg msg = { .flags = flags | (len >= 0xff ? I2C_M_STOP : 0), .buf = buffer, .len = len, diff --git a/drivers/i2c/kona_i2c.c b/drivers/i2c/kona_i2c.c index 5eab338cfc4..9af496bbb1c 100644 --- a/drivers/i2c/kona_i2c.c +++ b/drivers/i2c/kona_i2c.c @@ -156,7 +156,7 @@ static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = { #define I2C_M_RD 0x0001 /* read data */ #define I2C_M_NOSTART 0x4000 /* no restart between msgs */ -struct i2c_msg { +struct kona_i2c_msg { uint16_t addr; uint16_t flags; uint16_t len; @@ -297,7 +297,7 @@ static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, /* Read any amount of data using the RX FIFO from the i2c bus */ static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, - struct i2c_msg *msg) + struct kona_i2c_msg *msg) { unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; unsigned int last_byte_nak = 0; @@ -392,7 +392,7 @@ static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, /* Write any amount of data using TX FIFO to the i2c bus */ static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, - struct i2c_msg *msg) + struct kona_i2c_msg *msg) { unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; unsigned int bytes_written = 0; @@ -418,7 +418,7 @@ static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, /* Send i2c address */ static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, - struct i2c_msg *msg) + struct kona_i2c_msg *msg) { unsigned char addr; @@ -480,9 +480,9 @@ static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) /* Master transfer function */ static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev, - struct i2c_msg msgs[], int num) + struct kona_i2c_msg msgs[], int num) { - struct i2c_msg *pmsg; + struct kona_i2c_msg *pmsg; int rc = 0; int i; @@ -635,7 +635,7 @@ static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { /* msg[0] writes the addr, msg[1] reads the data */ - struct i2c_msg msg[2]; + struct kona_i2c_msg msg[2]; unsigned char msgbuf0[64]; struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); @@ -663,7 +663,7 @@ static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c_msg msg[1]; + struct kona_i2c_msg msg[1]; unsigned char msgbuf0[64]; unsigned int i; struct bcm_kona_i2c_dev *dev = kona_get_dev(adap); diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index dac346334d8..e65cce0d8e7 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -31,7 +31,7 @@ #endif /* All transfers are described by this data structure */ -struct i2c_msg { +struct mv_i2c_msg { u8 condition; u8 acknack; u8 direction; @@ -157,7 +157,7 @@ static int i2c_isr_set_cleared(unsigned long set_mask, * -5: illegal parameters * -6: bus is busy and couldn't be aquired */ -int i2c_transfer(struct i2c_msg *msg) +int i2c_transfer(struct mv_i2c_msg *msg) { int ret; @@ -286,7 +286,7 @@ void i2c_init(int speed, int slaveaddr) */ int i2c_probe(uchar chip) { - struct i2c_msg msg; + struct mv_i2c_msg msg; i2c_reset(); @@ -322,7 +322,7 @@ int i2c_probe(uchar chip) */ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c_msg msg; + struct mv_i2c_msg msg; u8 addr_bytes[3]; /* lowest...highest byte of data address */ PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, " @@ -410,7 +410,7 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) */ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) { - struct i2c_msg msg; + struct mv_i2c_msg msg; u8 addr_bytes[3]; /* lowest...highest byte of data address */ PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, " diff --git a/include/i2c.h b/include/i2c.h index 1635e9ac06c..31b038991e5 100644 --- a/include/i2c.h +++ b/include/i2c.h @@ -25,14 +25,13 @@ * enough as to be incompatible for compilation purposes. */ -#ifdef CONFIG_DM_I2C - enum dm_i2c_chip_flags { DM_I2C_CHIP_10BIT = 1 << 0, /* Use 10-bit addressing */ DM_I2C_CHIP_RD_ADDRESS = 1 << 1, /* Send address for each read byte */ DM_I2C_CHIP_WR_ADDRESS = 1 << 2, /* Send address for each write byte */ }; +struct udevice; /** * struct dm_i2c_chip - information about an i2c chip * @@ -439,8 +438,6 @@ int i2c_get_chip_for_busnum(int busnum, int chip_addr, uint offset_len, int i2c_chip_ofdata_to_platdata(const void *blob, int node, struct dm_i2c_chip *chip); -#endif - #ifndef CONFIG_DM_I2C /* -- cgit v1.3.1 From 91a91ff804d50d7a4b7560d10fa6863fc4c04307 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:36 -0700 Subject: dm: Add Kconfig options for driver model SPL support The SPL support cannot be enabled yet, but we can add the Kconfig options in preparation for this. Signed-off-by: Simon Glass --- drivers/core/Kconfig | 44 ++++++++++++++++++++++++++++++++++++++++++++ include/config_defaults.h | 6 ++++++ 2 files changed, 50 insertions(+) (limited to 'include') diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index dc32385e854..f0d611007af 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -6,3 +6,47 @@ config DM support, including scanning of platform data on start-up. If CONFIG_OF_CONTROL is enabled, the device tree will be scanned also when available. + +config SPL_DM + bool "Enable Driver Model for SPL" + depends on DM && SPL + help + Enable driver model in SPL. You will need to provide a + suitable malloc() implementation. If you are not using the + full malloc() enabled by CONFIG_SYS_SPL_MALLOC_START, + consider using CONFIG_SYS_MALLOC_SIMPLE. In that case you + must provide CONFIG_SYS_MALLOC_F_LEN to set the size. + In most cases driver model will only allocate a few uclasses + and devices in SPL, so 1KB should be enable. See + CONFIG_SYS_MALLOC_F_LEN for more details on how to enable it. + +config DM_WARN + bool "Enable warnings in driver model" + help + The dm_warn() function can use up quite a bit of space for its + strings. By default this is disabled for SPL builds to save space. + This will cause dm_warn() to be compiled out - it will do nothing + when called. + depends on DM + default y if !SPL_BUILD + default n if SPL_BUILD + +config DM_DEVICE_REMOVE + bool "Support device removal" + help + We can save some code space by dropping support for removing a + device. This is not normally required in SPL, so by default this + option is disabled for SPL. + depends on DM + default y if !SPL_BUILD + default n if SPL_BUILD + +config DM_STDIO + bool "Support stdio registration" + help + Normally serial drivers register with stdio so that they can be used + as normal output devices. In SPL we don't normally use stdio, so + we can omit this feature. + depends on DM + default y if !SPL_BUILD + default n if SPL_BUILD diff --git a/include/config_defaults.h b/include/config_defaults.h index 4d493150444..fa998389573 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -21,9 +21,15 @@ #define CONFIG_PARTITIONS 1 #ifndef CONFIG_SPL_BUILD +#ifndef CONFIG_DM_WARN #define CONFIG_DM_WARN +#endif +#ifndef CONFIG_DM_DEVICE_REMOVE #define CONFIG_DM_DEVICE_REMOVE +#endif +#ifndef CONFIG_DM_STDIO #define CONFIG_DM_STDIO #endif +#endif #endif -- cgit v1.3.1 From f058f154a9cad41b8cc97ce85b9308051ff297b9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:38 -0700 Subject: dm: Add CMD_DM and CMD_DEMO to Kconfig Add Kconfig settings for these two options. Signed-off-by: Simon Glass Reviewed-by: Masahiro Yamada --- common/Kconfig | 23 +++++++++++++++++++++++ include/configs/sandbox.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/ti_am335x_common.h | 1 - include/configs/uniphier.h | 2 -- 5 files changed, 23 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/common/Kconfig b/common/Kconfig index fd84fa08bd3..2ca002de270 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -153,6 +153,29 @@ endmenu menu "Device access commands" +config CMD_DM + bool "dm - Access to driver model information" + depends on DM + default y + help + Provides access to driver model data structures and information, + such as a list of devices, list of uclasses and the state of each + device (e.g. activated). This is not required for operation, but + can be useful to see the state of driver model for debugging or + interest. + +config CMD_DEMO + bool "demo - Demonstration commands for driver model" + depends on DM + help + Provides a 'demo' command which can be used to play around with + driver model. To use this properly you will need to enable one or + both of the demo devices (DM_DEMO_SHAPE and DM_DEMO_SIMPLE). + Otherwise you will always get an empty list of devices. The demo + devices are defined in the sandbox device tree, so the easiest + option is to use sandbox and pass the -d point to sandbox's + u-boot.dtb file. + config CMD_LOADB bool "loadb" help diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index e9d3f3226b3..deff4d648c6 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -24,7 +24,6 @@ #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT #define CONFIG_CMD_DEMO -#define CONFIG_CMD_DM #define CONFIG_DM_DEMO #define CONFIG_DM_DEMO_SIMPLE #define CONFIG_DM_DEMO_SHAPE diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cea52dbf7b7..325120da2e6 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -28,7 +28,6 @@ #define CONFIG_SYS_TEXT_BASE 0x4a000000 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) -# define CONFIG_CMD_DM # define CONFIG_DM_GPIO # define CONFIG_DM_SERIAL # define CONFIG_DW_SERIAL diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 598526bf95f..35332b5ed82 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -23,7 +23,6 @@ #ifndef CONFIG_DM # define CONFIG_DM #endif -# define CONFIG_CMD_DM # define CONFIG_DM_GPIO # define CONFIG_DM_SERIAL # define CONFIG_OMAP_SERIAL diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 9420e6b48b8..6f4ecc9b04c 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -192,8 +192,6 @@ #define CONFIG_FAT_WRITE #define CONFIG_DOS_PARTITION -#define CONFIG_CMD_DM - /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01000000) -- cgit v1.3.1 From 34e609ca82d8846dc1fcee485e9a2ad71060f77f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:39 -0700 Subject: dm: Move Raspberry Pi driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config header and use Kconfig instead. Signed-off-by: Simon Glass --- arch/arm/Kconfig | 2 ++ arch/arm/cpu/arm1176/bcm2835/Kconfig | 12 ++++++++++++ include/configs/rpi.h | 6 ------ 3 files changed, 14 insertions(+), 6 deletions(-) create mode 100644 arch/arm/cpu/arm1176/bcm2835/Kconfig (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1f1ccad10ac..41f32205803 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -839,6 +839,8 @@ endchoice source "arch/arm/cpu/arm926ejs/davinci/Kconfig" +source "arch/arm/cpu/arm1176/bcm2835/Kconfig" + source "arch/arm/cpu/armv7/exynos/Kconfig" source "arch/arm/cpu/armv7/highbank/Kconfig" diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig new file mode 100644 index 00000000000..94f57d732fe --- /dev/null +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -0,0 +1,12 @@ +if TARGET_RPI + +config DM + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index c94f4112026..ea19ad8d072 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -30,12 +30,6 @@ */ #define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 -/* Enable driver model */ -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL - /* Memory layout */ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x00000000 -- cgit v1.3.1 From aab7e80d5fbc3aeb5feddae88c9cbb649d23345a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:40 -0700 Subject: dm: exynos: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/exynos/Kconfig | 15 +++++++++++++++ board/samsung/goni/Kconfig | 9 +++++++++ board/samsung/smdk5420/Kconfig | 6 ++++++ board/samsung/smdkc100/Kconfig | 9 +++++++++ include/configs/exynos-common.h | 6 ------ include/configs/peach-pi.h | 1 - include/configs/peach-pit.h | 1 - include/configs/s5p_goni.h | 4 ---- include/configs/smdkc100.h | 4 ---- 9 files changed, 39 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 7fcb5d2094e..17ad567c190 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -65,6 +65,21 @@ endchoice config SYS_SOC default "exynos" +config DM + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + +config DM_SPI + default y if !SPL_BUILD + +config DM_SPI_FLASH + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig index cbbf5a93156..2c5d3fc3be5 100644 --- a/board/samsung/goni/Kconfig +++ b/board/samsung/goni/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "s5p_goni" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index a9d62fffa55..576abaea698 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -22,6 +22,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pi" +config DM_CROS_EC + default y + endif if TARGET_PEACH_PIT @@ -35,6 +38,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pit" +config DM_CROS_EC + default y + endif if TARGET_SMDK5420 diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig index d2157b4d05f..996fe3cc450 100644 --- a/board/samsung/smdkc100/Kconfig +++ b/board/samsung/smdkc100/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "smdkc100" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 1f3ee55098f..2c4f35af9fe 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -17,12 +17,6 @@ #include #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL -#define CONFIG_DM_SPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index a1c980d3202..f724164d898 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -44,7 +44,6 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_DM_CROS_EC #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 6516a727642..de12a9e1b18 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -44,7 +44,6 @@ #define CONFIG_POWER_TPS65090_EC #define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_DM_CROS_EC #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index dfa2e079480..26167a4ece7 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -290,9 +290,5 @@ #define CONFIG_OF_LIBFDT #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL #endif /* __CONFIG_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 982d0dcea39..a7eb33ed43f 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -224,9 +224,5 @@ #define CONFIG_OF_LIBFDT #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL #endif /* __CONFIG_H */ -- cgit v1.3.1 From 9a89d50d8eca3db64ecd71db2d3273a5c57bbdb1 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:41 -0700 Subject: dm: x86: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- arch/x86/Kconfig | 9 +++++++++ include/configs/x86-common.h | 5 ----- 2 files changed, 9 insertions(+), 5 deletions(-) (limited to 'include') diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fef11f35528..bb3ff4393ea 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -67,6 +67,15 @@ config TARGET_GALILEO endchoice +config DM + default y + +config DM_GPIO + default y + +config DM_SERIAL + default y + config RAMBASE hex default 0x100000 diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 062e6c22198..277a95c199a 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -22,11 +22,6 @@ #define CONFIG_DISPLAY_BOARDINFO_LATE #define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL - #define CONFIG_LMB #define CONFIG_OF_LIBFDT -- cgit v1.3.1 From d7a4b2e42e6f782c304e2ba0d6d48c2c77ccd8bf Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:42 -0700 Subject: dm: tegra: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/tegra-common/Kconfig | 18 ++++++++++++++++++ include/configs/tegra-common.h | 10 ---------- 2 files changed, 18 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 1446452c236..93dc7320c99 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -20,6 +20,24 @@ endchoice config USE_PRIVATE_LIBGCC default y if SPL_BUILD +config DM + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + +config DM_SPI + default y if !SPL_BUILD + +config DM_SPI_FLASH + default y if !SPL_BUILD + +config DM_I2C + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + source "arch/arm/cpu/armv7/tegra20/Kconfig" source "arch/arm/cpu/armv7/tegra30/Kconfig" source "arch/arm/cpu/armv7/tegra114/Kconfig" diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 8f1e3709155..ef259802525 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -18,16 +18,6 @@ #include /* get chip and board defs */ -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_SERIAL -#endif -#define CONFIG_DM_SPI -#define CONFIG_DM_SPI_FLASH -#define CONFIG_DM_I2C - #define CONFIG_SYS_TIMER_RATE 1000000 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE -- cgit v1.3.1 From 001646c478429f7ee1e9a4aff667ad9ed3bc4ee4 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:44 -0700 Subject: dm: omap3: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- arch/arm/cpu/armv7/omap3/Kconfig | 9 +++++++++ board/compulab/cm_t335/Kconfig | 9 +++++++++ board/gumstix/pepper/Kconfig | 9 +++++++++ board/isee/igep0033/Kconfig | 9 +++++++++ board/phytec/pcm051/Kconfig | 9 +++++++++ board/silica/pengwyn/Kconfig | 9 +++++++++ board/ti/am335x/Kconfig | 10 ++++++++++ configs/am3517_crane_defconfig | 3 +++ configs/am3517_evm_defconfig | 3 +++ configs/cm_t3517_defconfig | 3 +++ configs/cm_t35_defconfig | 3 +++ configs/devkit8000_defconfig | 3 +++ configs/dig297_defconfig | 3 +++ configs/eco5pk_defconfig | 3 +++ configs/mcx_defconfig | 3 +++ configs/mt_ventoux_defconfig | 3 +++ configs/nokia_rx51_defconfig | 3 +++ configs/omap3_beagle_defconfig | 3 +++ configs/omap3_evm_defconfig | 3 +++ configs/omap3_evm_quick_mmc_defconfig | 3 +++ configs/omap3_evm_quick_nand_defconfig | 3 +++ configs/omap3_ha_defconfig | 3 +++ configs/omap3_logic_defconfig | 3 +++ configs/omap3_mvblx_defconfig | 3 +++ configs/omap3_pandora_defconfig | 3 +++ configs/omap3_sdp3430_defconfig | 3 +++ configs/tao3530_defconfig | 3 +++ configs/tricorder_defconfig | 3 +++ configs/tricorder_flash_defconfig | 3 +++ configs/twister_defconfig | 3 +++ include/configs/nokia_rx51.h | 1 + include/configs/ti_am335x_common.h | 5 ----- include/configs/ti_omap3_common.h | 4 ---- 33 files changed, 134 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index a029379a4f2..2fe323230fe 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -93,6 +93,15 @@ config TARGET_TWISTER endchoice +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if DM && !SPL_BUILD + +config DM_SERIAL + default y if DM && !SPL_BUILD + config SYS_SOC default "omap3" diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig index 683efde7644..aadbfbc84dc 100644 --- a/board/compulab/cm_t335/Kconfig +++ b/board/compulab/cm_t335/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "cm_t335" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig index 6f94612fe21..3099a9eae15 100644 --- a/board/gumstix/pepper/Kconfig +++ b/board/gumstix/pepper/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pepper" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig index e989e4b15cf..2fe2ef17062 100644 --- a/board/isee/igep0033/Kconfig +++ b/board/isee/igep0033/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "am335x_igep0033" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig index 2cc0d8872d7..65094cf9fde 100644 --- a/board/phytec/pcm051/Kconfig +++ b/board/phytec/pcm051/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pcm051" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig index f2e1098f62a..6ecda8041c9 100644 --- a/board/silica/pengwyn/Kconfig +++ b/board/silica/pengwyn/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pengwyn" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index 1ddbb2c67c1..d6581ac4687 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -37,4 +37,14 @@ config NOR_BOOT booted via NOR. In this case we will enable certain pinmux early as the ROM only partially sets up pinmux. We also default to using NOR for environment. + +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if DM && !SPL_BUILD + +config DM_SERIAL + default y if DM && !SPL_BUILD + endif diff --git a/configs/am3517_crane_defconfig b/configs/am3517_crane_defconfig index cf9d8c7120e..33b63c7e0e7 100644 --- a/configs/am3517_crane_defconfig +++ b/configs/am3517_crane_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_AM3517_CRANE=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index 2336f1ed829..7558b89e495 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_AM3517_EVM=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/cm_t3517_defconfig b/configs/cm_t3517_defconfig index 4000d2c75d4..6eb37c0695e 100644 --- a/configs/cm_t3517_defconfig +++ b/configs/cm_t3517_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=n +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_CM_T3517=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/cm_t35_defconfig b/configs/cm_t35_defconfig index 2bb616fb903..84a6fb0efab 100644 --- a/configs/cm_t35_defconfig +++ b/configs/cm_t35_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_CM_T35=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 578ae74bbad..05a87007594 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_DEVKIT8000=y +CONFIG_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_GPIO=y diff --git a/configs/dig297_defconfig b/configs/dig297_defconfig index 95bc3539267..0d182900f94 100644 --- a/configs/dig297_defconfig +++ b/configs/dig297_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_DIG297=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/eco5pk_defconfig b/configs/eco5pk_defconfig index e45bdadf3fd..e07df8bbd4b 100644 --- a/configs/eco5pk_defconfig +++ b/configs/eco5pk_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_ECO5PK=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/mcx_defconfig b/configs/mcx_defconfig index c2031f85b78..6566d40c194 100644 --- a/configs/mcx_defconfig +++ b/configs/mcx_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_MCX=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/mt_ventoux_defconfig b/configs/mt_ventoux_defconfig index a0678bb8230..a4747c62566 100644 --- a/configs/mt_ventoux_defconfig +++ b/configs/mt_ventoux_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_MT_VENTOUX=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index e03f5868808..20a51e1d2fd 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_NOKIA_RX51=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index a3e4c2c6d62..5a2d20b0df7 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -3,3 +3,6 @@ CONFIG_SYS_EXTRA_OPTIONS="NAND" +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_OMAP3_BEAGLE=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index c749aa74b73..3bb191135e0 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_OMAP3_EVM=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_evm_quick_mmc_defconfig b/configs/omap3_evm_quick_mmc_defconfig index e89bb82ac91..4e1471bac8e 100644 --- a/configs/omap3_evm_quick_mmc_defconfig +++ b/configs/omap3_evm_quick_mmc_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_OMAP3_EVM_QUICK_MMC=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_evm_quick_nand_defconfig b/configs/omap3_evm_quick_nand_defconfig index e70fddd7944..f98672f8625 100644 --- a/configs/omap3_evm_quick_nand_defconfig +++ b/configs/omap3_evm_quick_nand_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_OMAP3_EVM_QUICK_NAND=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_ha_defconfig b/configs/omap3_ha_defconfig index 50bffa90a2e..1a8b1b4e9ee 100644 --- a/configs/omap3_ha_defconfig +++ b/configs/omap3_ha_defconfig @@ -3,3 +3,6 @@ CONFIG_SYS_EXTRA_OPTIONS="SYS_BOARD_OMAP3_HA" +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_TAO3530=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index 5f2c063b6ec..790ccbaa344 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_LOGIC=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_mvblx_defconfig b/configs/omap3_mvblx_defconfig index fb6edc252af..b75f51323e8 100644 --- a/configs/omap3_mvblx_defconfig +++ b/configs/omap3_mvblx_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_MVBLX=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_pandora_defconfig b/configs/omap3_pandora_defconfig index bf285378a3f..dd0f17c20c5 100644 --- a/configs/omap3_pandora_defconfig +++ b/configs/omap3_pandora_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_PANDORA=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/omap3_sdp3430_defconfig b/configs/omap3_sdp3430_defconfig index 1172c2adc59..b3a8745a02f 100644 --- a/configs/omap3_sdp3430_defconfig +++ b/configs/omap3_sdp3430_defconfig @@ -1,3 +1,6 @@ CONFIG_ARM=y CONFIG_OMAP34XX=y CONFIG_TARGET_OMAP3_SDP3430=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/tao3530_defconfig b/configs/tao3530_defconfig index a5113890ef3..39ed8723492 100644 --- a/configs/tao3530_defconfig +++ b/configs/tao3530_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_TAO3530=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/tricorder_defconfig b/configs/tricorder_defconfig index 7ea5e02f5ed..3efe8290d90 100644 --- a/configs/tricorder_defconfig +++ b/configs/tricorder_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_TRICORDER=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/tricorder_flash_defconfig b/configs/tricorder_flash_defconfig index f6e1c464aad..8f999ff6214 100644 --- a/configs/tricorder_flash_defconfig +++ b/configs/tricorder_flash_defconfig @@ -3,3 +3,6 @@ CONFIG_SYS_EXTRA_OPTIONS="FLASHCARD" +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_TRICORDER=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/configs/twister_defconfig b/configs/twister_defconfig index 902373601ad..d21a551f952 100644 --- a/configs/twister_defconfig +++ b/configs/twister_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_OMAP34XX=y +S:CONFIG_TARGET_TWISTER=y +CONFIG_DM=n +CONFIG_DM_SERIAL=n +CONFIG_DM_GPIO=n diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 46fc91e5e19..6e1f501b64d 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -72,6 +72,7 @@ #define CONFIG_UBI_SIZE (512 << 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ (128 << 10)) +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* * Hardware drivers diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 35332b5ed82..4ce9d49c189 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -20,11 +20,6 @@ #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC #ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_DM -# define CONFIG_DM -#endif -# define CONFIG_DM_GPIO -# define CONFIG_DM_SERIAL # define CONFIG_OMAP_SERIAL # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 3c634ee680d..77211de9a50 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -19,10 +19,6 @@ #include #ifndef CONFIG_SPL_BUILD -# define CONFIG_DM -# define CONFIG_CMD_DM -# define CONFIG_DM_GPIO -# define CONFIG_DM_SERIAL # define CONFIG_OMAP_SERIAL # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif -- cgit v1.3.1 From f4aae59fdfc161cbcd3bc628af100d305d739033 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:45 -0700 Subject: dm: sandbox: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- arch/sandbox/Kconfig | 24 ++++++++++++++++++++++++ include/configs/sandbox.h | 11 ----------- 2 files changed, 24 insertions(+), 11 deletions(-) (limited to 'include') diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig index 3057325b476..2098b9c323b 100644 --- a/arch/sandbox/Kconfig +++ b/arch/sandbox/Kconfig @@ -10,4 +10,28 @@ config SYS_BOARD config SYS_CONFIG_NAME default "sandbox" +config DM + default y + +config DM_GPIO + default y + +config DM_SERIAL + default y + +config DM_CROS_EC + default y + +config DM_SPI + default y + +config DM_SPI_FLASH + default y + +config DM_I2C + default y + +config DM_TEST + default y + endmenu diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index deff4d648c6..bff01708f68 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -23,14 +23,6 @@ #define CONFIG_BOOTSTAGE #define CONFIG_BOOTSTAGE_REPORT -#define CONFIG_CMD_DEMO -#define CONFIG_DM_DEMO -#define CONFIG_DM_DEMO_SIMPLE -#define CONFIG_DM_DEMO_SHAPE -#define CONFIG_DM_GPIO -#define CONFIG_DM_TEST -#define CONFIG_DM_SERIAL -#define CONFIG_DM_CROS_EC #define CONFIG_SYS_STDIO_DEREGISTER @@ -95,8 +87,6 @@ #define CONFIG_CMD_SF_TEST #define CONFIG_CMD_SPI #define CONFIG_SPI_FLASH -#define CONFIG_DM_SPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_SPI_FLASH_ATMEL #define CONFIG_SPI_FLASH_EON #define CONFIG_SPI_FLASH_GIGADEVICE @@ -107,7 +97,6 @@ #define CONFIG_SPI_FLASH_STMICRO #define CONFIG_SPI_FLASH_WINBOND -#define CONFIG_DM_I2C #define CONFIG_CMD_I2C #define CONFIG_SYS_I2C_SANDBOX #define CONFIG_I2C_EDID -- cgit v1.3.1 From 7b051c5235d6c82cbb396e4419e8d90c7d7635e7 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:46 -0700 Subject: dm: sunxi: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass Acked-by: Ian Campbell --- configs/Linksprite_pcDuino3_fdt_defconfig | 2 ++ include/configs/sunxi-common.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig index 3b6dfa6fa69..cfed375fc2c 100644 --- a/configs/Linksprite_pcDuino3_fdt_defconfig +++ b/configs/Linksprite_pcDuino3_fdt_defconfig @@ -2,6 +2,8 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="AXP209_POWER,SUNXI_GMAC,AHCI,SATAPWR=SUNXI_GPH(2),USB_EHCI" CONFIG_FDTFILE="sun7i-a20-pcduino3.dtb" CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y CONFIG_DEFAULT_DEVICE_TREE="sun7i-a20-pcduino3" CONFIG_OF_CONTROL=y CONFIG_OF_SEPARATE=y diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 325120da2e6..0c5c18cb304 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -28,8 +28,6 @@ #define CONFIG_SYS_TEXT_BASE 0x4a000000 #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) -# define CONFIG_DM_GPIO -# define CONFIG_DM_SERIAL # define CONFIG_DW_SERIAL # define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif -- cgit v1.3.1 From 70c45aeb433d1c4c8f970927aba0cd45d701a7ae Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:47 -0700 Subject: dm: mx6: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- configs/cm_fx6_defconfig | 3 +++ include/configs/cm_fx6.h | 4 ---- 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index 3c0d64fecbc..d2ebf692f36 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -2,3 +2,6 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" +S:CONFIG_ARM=y +S:CONFIG_TARGET_CM_FX6=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 1f644950551..40083069441 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,13 +21,9 @@ #define CONFIG_MACH_TYPE 4273 #ifndef CONFIG_SPL_BUILD -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO #define CONFIG_CMD_GPIO -#define CONFIG_DM_SERIAL #define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif -- cgit v1.3.1 From 0f36f957f4108d2d1d935e3076b7ae91f4e65a7d Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Thu, 5 Feb 2015 21:41:49 -0700 Subject: dm: socfpga: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- configs/socfpga_socrates_defconfig | 3 +++ include/configs/socfpga_common.h | 7 ------- 2 files changed, 3 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index 0f3896d5f03..888bbb6c6f6 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -3,3 +3,6 @@ CONFIG_SPL=y +S:CONFIG_TARGET_SOCFPGA_CYCLONE5=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates" +CONFIG_DM=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index 6b1f967c44e..ee227fef0f4 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -190,10 +190,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); * QSPI support */ #ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CMD_DM -#define CONFIG_DM -#define CONFIG_DM_SPI -#define CONFIG_DM_SPI_FLASH #define CONFIG_CADENCE_QSPI /* Enable multiple SPI NOR flash manufacturers */ #define CONFIG_SPI_FLASH /* SPI flash subsystem */ @@ -210,9 +206,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); #endif #ifdef CONFIG_OF_CONTROL /* DW SPI is controlled via DT */ -#define CONFIG_CMD_DM -#define CONFIG_DM -#define CONFIG_DM_SPI #define CONFIG_DESIGNWARE_SPI #define CONFIG_CMD_SPI #endif -- cgit v1.3.1 From 59088e4a762d5ea2791b6ecd39c81765ba4c4546 Mon Sep 17 00:00:00 2001 From: Nobuhiro Iwamatsu Date: Thu, 12 Feb 2015 13:48:04 +0900 Subject: dm: sh: serial: Add support driver model This adds driver model support with this driver. This was tested by Koelsch board and Gose board. Signed-off-by: Nobuhiro Iwamatsu Acked-by: Simon Glass --- drivers/serial/serial_sh.c | 321 ++++++++++++++++++++++++----------- drivers/serial/serial_sh.h | 30 ++-- include/dm/platform_data/serial_sh.h | 37 ++++ 3 files changed, 275 insertions(+), 113 deletions(-) create mode 100644 include/dm/platform_data/serial_sh.h (limited to 'include') diff --git a/drivers/serial/serial_sh.c b/drivers/serial/serial_sh.c index 7c1f2713761..3641c9f8340 100644 --- a/drivers/serial/serial_sh.c +++ b/drivers/serial/serial_sh.c @@ -1,78 +1,21 @@ /* * SuperH SCIF device driver. * Copyright (C) 2013 Renesas Electronics Corporation - * Copyright (C) 2007,2008,2010 Nobuhiro Iwamatsu + * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu * Copyright (C) 2002 - 2008 Paul Mundt * * SPDX-License-Identifier: GPL-2.0+ */ #include +#include +#include #include #include -#include "serial_sh.h" #include #include - -#if defined(CONFIG_CONS_SCIF0) -# define SCIF_BASE SCIF0_BASE -#elif defined(CONFIG_CONS_SCIF1) -# define SCIF_BASE SCIF1_BASE -#elif defined(CONFIG_CONS_SCIF2) -# define SCIF_BASE SCIF2_BASE -#elif defined(CONFIG_CONS_SCIF3) -# define SCIF_BASE SCIF3_BASE -#elif defined(CONFIG_CONS_SCIF4) -# define SCIF_BASE SCIF4_BASE -#elif defined(CONFIG_CONS_SCIF5) -# define SCIF_BASE SCIF5_BASE -#elif defined(CONFIG_CONS_SCIF6) -# define SCIF_BASE SCIF6_BASE -#elif defined(CONFIG_CONS_SCIF7) -# define SCIF_BASE SCIF7_BASE -#else -# error "Default SCIF doesn't set....." -#endif - -#if defined(CONFIG_SCIF_A) - #define SCIF_BASE_PORT PORT_SCIFA -#else - #define SCIF_BASE_PORT PORT_SCIF -#endif - -static struct uart_port sh_sci = { - .membase = (unsigned char*)SCIF_BASE, - .mapbase = SCIF_BASE, - .type = SCIF_BASE_PORT, -}; - -static void sh_serial_setbrg(void) -{ - DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_SCIF_USE_EXT_CLK - unsigned short dl = DL_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ); - sci_out(&sh_sci, DL, dl); - /* Need wait: Clock * 1/dl $B!_(B 1/16 */ - udelay((1000000 * dl * 16 / CONFIG_SYS_CLK_FREQ) * 1000 + 1); -#else - sci_out(&sh_sci, SCBRR, - SCBRR_VALUE(gd->baudrate, CONFIG_SH_SCIF_CLK_FREQ)); -#endif -} - -static int sh_serial_init(void) -{ - sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci)); - sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci)); - sci_out(&sh_sci, SCSMR, 0); - sci_out(&sh_sci, SCSMR, 0); - sci_out(&sh_sci, SCFCR, SCFCR_RFRST|SCFCR_TFRST); - sci_in(&sh_sci, SCFCR); - sci_out(&sh_sci, SCFCR, 0); - - serial_setbrg(); - return 0; -} +#include +#include "serial_sh.h" #if defined(CONFIG_CPU_SH7760) || \ defined(CONFIG_CPU_SH7780) || \ @@ -86,7 +29,7 @@ static int scif_rxfill(struct uart_port *port) static int scif_rxfill(struct uart_port *port) { if ((port->mapbase == 0xffe00000) || - (port->mapbase == 0xffe08000)) { + (port->mapbase == 0xffe08000)) { /* SCIF0/1*/ return sci_in(port, SCRFDR) & 0xff; } else { @@ -109,80 +52,253 @@ static int scif_rxfill(struct uart_port *port) } #endif -static int serial_rx_fifo_level(void) +static void sh_serial_init_generic(struct uart_port *port) { - return scif_rxfill(&sh_sci); + sci_out(port, SCSCR , SCSCR_INIT(port)); + sci_out(port, SCSCR , SCSCR_INIT(port)); + sci_out(port, SCSMR, 0); + sci_out(port, SCSMR, 0); + sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); + sci_in(port, SCFCR); + sci_out(port, SCFCR, 0); } -static void handle_error(void) +static void +sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) { - sci_in(&sh_sci, SCxSR); - sci_out(&sh_sci, SCxSR, SCxSR_ERROR_CLEAR(&sh_sci)); - sci_in(&sh_sci, SCLSR); - sci_out(&sh_sci, SCLSR, 0x00); + if (port->clk_mode == EXT_CLK) { + unsigned short dl = DL_VALUE(baudrate, clk); + sci_out(port, DL, dl); + /* Need wait: Clock * 1/dl $B!_(B 1/16 */ + udelay((1000000 * dl * 16 / clk) * 1000 + 1); + } else { + sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); + } } -static void serial_raw_putc(const char c) +static void handle_error(struct uart_port *port) { - while (1) { - /* Tx fifo is empty */ - if (sci_in(&sh_sci, SCxSR) & SCxSR_TEND(&sh_sci)) - break; - } + sci_in(port, SCxSR); + sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); + sci_in(port, SCLSR); + sci_out(port, SCLSR, 0x00); +} + +static int serial_raw_putc(struct uart_port *port, const char c) +{ + /* Tx fifo is empty */ + if (!(sci_in(port, SCxSR) & SCxSR_TEND(port))) + return -EAGAIN; - sci_out(&sh_sci, SCxTDR, c); - sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci)); + sci_out(port, SCxTDR, c); + sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port)); + + return 0; } -static void sh_serial_putc(const char c) +static int serial_rx_fifo_level(struct uart_port *port) { - if (c == '\n') - serial_raw_putc('\r'); - serial_raw_putc(c); + return scif_rxfill(port); } -static int sh_serial_tstc(void) +static int sh_serial_tstc_generic(struct uart_port *port) { - if (sci_in(&sh_sci, SCxSR) & SCIF_ERRORS) { - handle_error(); + if (sci_in(port, SCxSR) & SCIF_ERRORS) { + handle_error(port); return 0; } - return serial_rx_fifo_level() ? 1 : 0; + return serial_rx_fifo_level(port) ? 1 : 0; } - -static int serial_getc_check(void) +static int serial_getc_check(struct uart_port *port) { unsigned short status; - status = sci_in(&sh_sci, SCxSR); + status = sci_in(port, SCxSR); if (status & SCIF_ERRORS) - handle_error(); - if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci)) - handle_error(); - return status & (SCIF_DR | SCxSR_RDxF(&sh_sci)); + handle_error(port); + if (sci_in(port, SCLSR) & SCxSR_ORER(port)) + handle_error(port); + return status & (SCIF_DR | SCxSR_RDxF(port)); } -static int sh_serial_getc(void) +static int sh_serial_getc_generic(struct uart_port *port) { unsigned short status; char ch; - while (!serial_getc_check()) - ; + if (!serial_getc_check(port)) + return -EAGAIN; - ch = sci_in(&sh_sci, SCxRDR); - status = sci_in(&sh_sci, SCxSR); + ch = sci_in(port, SCxRDR); + status = sci_in(port, SCxSR); - sci_out(&sh_sci, SCxSR, SCxSR_RDxF_CLEAR(&sh_sci)); + sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); if (status & SCIF_ERRORS) - handle_error(); + handle_error(port); + + if (sci_in(port, SCLSR) & SCxSR_ORER(port)) + handle_error(port); + + return ch; +} + +#ifdef CONFIG_DM_SERIAL + +static int sh_serial_pending(struct udevice *dev, bool input) +{ + struct uart_port *priv = dev_get_priv(dev); + + return sh_serial_tstc_generic(priv); +} + +static int sh_serial_putc(struct udevice *dev, const char ch) +{ + struct uart_port *priv = dev_get_priv(dev); + + return serial_raw_putc(priv, ch); +} + +static int sh_serial_getc(struct udevice *dev) +{ + struct uart_port *priv = dev_get_priv(dev); + + return sh_serial_getc_generic(priv); +} + +static int sh_serial_setbrg(struct udevice *dev, int baudrate) +{ + struct sh_serial_platdata *plat = dev_get_platdata(dev); + struct uart_port *priv = dev_get_priv(dev); + + sh_serial_setbrg_generic(priv, plat->clk, baudrate); + + return 0; +} + +static int sh_serial_probe(struct udevice *dev) +{ + struct sh_serial_platdata *plat = dev_get_platdata(dev); + struct uart_port *priv = dev_get_priv(dev); + + priv->membase = (unsigned char *)plat->base; + priv->mapbase = plat->base; + priv->type = plat->type; + priv->clk_mode = plat->clk_mode; + + sh_serial_init_generic(priv); + + return 0; +} + +static const struct dm_serial_ops sh_serial_ops = { + .putc = sh_serial_putc, + .pending = sh_serial_pending, + .getc = sh_serial_getc, + .setbrg = sh_serial_setbrg, +}; + +U_BOOT_DRIVER(serial_sh) = { + .name = "serial_sh", + .id = UCLASS_SERIAL, + .probe = sh_serial_probe, + .ops = &sh_serial_ops, + .flags = DM_FLAG_PRE_RELOC, + .priv_auto_alloc_size = sizeof(struct uart_port), +}; + +#else /* CONFIG_DM_SERIAL */ + +#if defined(CONFIG_CONS_SCIF0) +# define SCIF_BASE SCIF0_BASE +#elif defined(CONFIG_CONS_SCIF1) +# define SCIF_BASE SCIF1_BASE +#elif defined(CONFIG_CONS_SCIF2) +# define SCIF_BASE SCIF2_BASE +#elif defined(CONFIG_CONS_SCIF3) +# define SCIF_BASE SCIF3_BASE +#elif defined(CONFIG_CONS_SCIF4) +# define SCIF_BASE SCIF4_BASE +#elif defined(CONFIG_CONS_SCIF5) +# define SCIF_BASE SCIF5_BASE +#elif defined(CONFIG_CONS_SCIF6) +# define SCIF_BASE SCIF6_BASE +#elif defined(CONFIG_CONS_SCIF7) +# define SCIF_BASE SCIF7_BASE +#else +# error "Default SCIF doesn't set....." +#endif + +#if defined(CONFIG_SCIF_A) + #define SCIF_BASE_PORT PORT_SCIFA +#else + #define SCIF_BASE_PORT PORT_SCIF +#endif + +static struct uart_port sh_sci = { + .membase = (unsigned char *)SCIF_BASE, + .mapbase = SCIF_BASE, + .type = SCIF_BASE_PORT, +#ifdef CONFIG_SCIF_USE_EXT_CLK + .clk_mode = EXT_CLK, +#endif +}; + +static void sh_serial_setbrg(void) +{ + DECLARE_GLOBAL_DATA_PTR; + struct uart_port *port = &sh_sci; + + sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate); +} + +static int sh_serial_init(void) +{ + struct uart_port *port = &sh_sci; + + sh_serial_init_generic(port); + serial_setbrg(); + + return 0; +} + +static void sh_serial_putc(const char c) +{ + struct uart_port *port = &sh_sci; + + if (c == '\n') { + while (1) { + if (serial_raw_putc(port, '\r') != -EAGAIN) + break; + } + } + while (1) { + if (serial_raw_putc(port, c) != -EAGAIN) + break; + } +} + +static int sh_serial_tstc(void) +{ + struct uart_port *port = &sh_sci; + + return sh_serial_tstc_generic(port); +} + +static int sh_serial_getc(void) +{ + struct uart_port *port = &sh_sci; + int ch; + + while (1) { + ch = sh_serial_getc_generic(port); + if (ch != -EAGAIN) + break; + } - if (sci_in(&sh_sci, SCLSR) & SCxSR_ORER(&sh_sci)) - handle_error(); return ch; } @@ -206,3 +322,4 @@ __weak struct serial_device *default_serial_console(void) { return &sh_serial_drv; } +#endif /* CONFIG_DM_SERIAL */ diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index ef88c8f2733..528aa7351d2 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -2,18 +2,16 @@ * Copy and modify from linux/drivers/serial/sh-sci.h */ +#include + struct uart_port { unsigned long iobase; /* in/out[bwl] */ unsigned char *membase; /* read/write[bwl] */ unsigned long mapbase; /* for ioremap */ - unsigned int type; /* port type */ + enum sh_serial_type type; /* port type */ + enum sh_clk_mode clk_mode; /* clock mode */ }; -#define PORT_SCI 52 -#define PORT_SCIF 53 -#define PORT_SCIFA 83 -#define PORT_SCIFB 93 - #if defined(CONFIG_H83007) || defined(CONFIG_H83068) #include #endif @@ -526,6 +524,7 @@ SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCxTDR, 0x20, 8) SCIF_FNS(SCxRDR, 0x24, 8) SCIF_FNS(SCLSR, 0x00, 0) +SCIF_FNS(DL, 0x00, 0) /* dummy */ #elif defined(CONFIG_ARCH_SH7372) || \ defined(CONFIG_R8A7740) SCIF_FNS(SCSMR, 0x00, 16) @@ -541,6 +540,7 @@ SCIF_FNS(SCRFDR, 0x3c, 16) SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8) SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8) SCIF_FNS(SCLSR, 0x00, 0) +SCIF_FNS(DL, 0x00, 0) /* dummy */ #elif defined(CONFIG_CPU_SH7723) ||\ defined(CONFIG_CPU_SH7724) SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16) @@ -555,6 +555,7 @@ SCIF_FNS(SCFER, 0x10, 16) SCIF_FNS(SCFCR, 0x18, 16) SCIF_FNS(SCFDR, 0x1c, 16) SCIF_FNS(SCLSR, 0x24, 16) +SCIF_FNS(DL, 0x00, 0) /* dummy */ #else /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/ /* name off sz off sz off sz off sz off sz*/ @@ -583,18 +584,21 @@ SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) SCIF_FNS(SCLSR, 0, 0, 0x28, 16) #else + SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16) #if defined(CONFIG_CPU_SH7722) SCIF_FNS(SCSPTR, 0, 0, 0, 0) #else SCIF_FNS(SCSPTR, 0, 0, 0x20, 16) #endif +SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +#endif #if defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) SCIF_FNS(DL, 0, 0, 0x30, 16) SCIF_FNS(CKS, 0, 0, 0x34, 16) -#endif -SCIF_FNS(SCLSR, 0, 0, 0x24, 16) +#else +SCIF_FNS(DL, 0, 0, 0x0, 0) /* dummy */ #endif #endif #define sci_in(port, reg) sci_##reg##_in(port) @@ -725,14 +729,14 @@ static inline int sci_rxd_in(struct uart_port *port) #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) #elif defined(CONFIG_CPU_SH7723) ||\ defined(CONFIG_CPU_SH7724) -static inline int scbrr_calc(struct uart_port port, int bps, int clk) +static inline int scbrr_calc(struct uart_port *port, int bps, int clk) { - if (port.type == PORT_SCIF) + if (port->type == PORT_SCIF) return (clk+16*bps)/(32*bps)-1; else return ((clk*2)+16*bps)/(16*bps)-1; } -#define SCBRR_VALUE(bps, clk) scbrr_calc(sh_sci, bps, clk) +#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) #elif defined(__H8300H__) || defined(__H8300S__) #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ @@ -742,3 +746,7 @@ static inline int scbrr_calc(struct uart_port port, int bps, int clk) #else /* Generic SH */ #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) #endif + +#ifndef DL_VALUE +#define DL_VALUE(bps, clk) 0 +#endif diff --git a/include/dm/platform_data/serial_sh.h b/include/dm/platform_data/serial_sh.h new file mode 100644 index 00000000000..0271ad67b36 --- /dev/null +++ b/include/dm/platform_data/serial_sh.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2014 Nobuhiro Iwamatsu + * Copyright (c) 2014 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __serial_sh_h +#define __serial_sh_h + +enum sh_clk_mode { + INT_CLK, + EXT_CLK, +}; + +enum sh_serial_type { + PORT_SCI, + PORT_SCIF, + PORT_SCIFA, + PORT_SCIFB, +}; + +/* + * Information about SCIF port + * + * @base: Register base address + * @clk: Input clock rate, used for calculating the baud rate divisor + * @clk_mode: Clock mode, set internal (INT) or external (EXT) + * @type: Type of SCIF + */ +struct sh_serial_platdata { + unsigned long base; + unsigned int clk; + enum sh_clk_mode clk_mode; + enum sh_serial_type type; +}; +#endif /* __serial_sh_h */ -- cgit v1.3.1 From ad885e45702029362575cec27e4808585c279832 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Feb 2015 16:32:58 -0700 Subject: dm: at91: snapper: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- configs/snapper9260_defconfig | 3 +++ configs/snapper9g20_defconfig | 3 +++ include/configs/snapper9260.h | 4 ---- 3 files changed, 6 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 7055e2a13bc..035146c6575 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -1,3 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9260" CONFIG_ARM=y CONFIG_TARGET_SNAPPER9260=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 2faae15930d..66c44ccf78a 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -1,3 +1,6 @@ CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9G20" CONFIG_ARM=y CONFIG_TARGET_SNAPPER9260=y +CONFIG_DM=y +CONFIG_DM_GPIO=y +CONFIG_DM_SERIAL=y diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 9fa644f7c28..712f9b74ce4 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -21,10 +21,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_DM -#define CONFIG_CMD_DM -#define CONFIG_DM_GPIO -#define CONFIG_DM_SERIAL #define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* CPU */ -- cgit v1.3.1 From b724bd7d63498449d3960bbd3075ba94d7152890 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Feb 2015 16:32:59 -0700 Subject: dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass --- Kconfig | 19 +++++++++++++++++++ arch/arm/cpu/armv7/exynos/Kconfig | 6 ++++++ arch/arm/cpu/armv7/omap3/Kconfig | 6 ++++++ arch/arm/cpu/armv7/tegra-common/Kconfig | 6 ++++++ arch/arm/cpu/armv7/uniphier/Kconfig | 6 ++++++ arch/x86/Kconfig | 6 ++++++ board/ti/am335x/Kconfig | 6 ++++++ configs/Linksprite_pcDuino3_fdt_defconfig | 2 ++ configs/am335x_igep0033_defconfig | 2 ++ configs/cm_fx6_defconfig | 2 ++ configs/cm_t335_defconfig | 2 ++ configs/gwventana_defconfig | 2 ++ configs/mx6dlsabreauto_defconfig | 2 ++ configs/mx6qsabreauto_defconfig | 2 ++ configs/mx6qsabresd_defconfig | 2 ++ configs/mx6sxsabresd_defconfig | 2 ++ configs/nokia_rx51_defconfig | 2 ++ configs/pcm051_rev1_defconfig | 2 ++ configs/pcm051_rev3_defconfig | 2 ++ configs/pengwyn_defconfig | 2 ++ configs/pepper_defconfig | 2 ++ configs/rpi_defconfig | 2 ++ configs/s5p_goni_defconfig | 2 ++ configs/sandbox_defconfig | 2 ++ configs/smdkc100_defconfig | 2 ++ configs/snapper9260_defconfig | 2 ++ configs/snapper9g20_defconfig | 2 ++ configs/stv0991_defconfig | 2 ++ include/configs/cm_fx6.h | 3 --- include/configs/exynos-common.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/mx6sabre_common.h | 1 - include/configs/mx6sxsabresd.h | 1 - include/configs/nokia_rx51.h | 1 - include/configs/novena.h | 1 - include/configs/rpi.h | 1 - include/configs/s5p_goni.h | 1 - include/configs/sandbox.h | 1 - include/configs/smdkc100.h | 3 --- include/configs/snapper9260.h | 1 - include/configs/stv0991.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/tegra-common.h | 1 - include/configs/ti_am335x_common.h | 1 - include/configs/ti_omap3_common.h | 1 - include/configs/uniphier.h | 2 -- include/configs/x86-common.h | 1 - 47 files changed, 97 insertions(+), 24 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index 6112a7778e1..75bab7f6cc0 100644 --- a/Kconfig +++ b/Kconfig @@ -56,6 +56,25 @@ config CC_OPTIMIZE_FOR_SIZE This option is enabled by default for U-Boot. +config SYS_MALLOC_F + bool "Enable malloc() pool before relocation" + default 0x400 + help + Before relocation memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + +config SYS_MALLOC_F_LEN + hex "Size of malloc() pool before relocation" + depends on SYS_MALLOC_F + default 0x400 + help + Before relocation memory is very limited on many platforms. Still, + we can provide a small malloc() pool if needed. Driver model in + particular needs this to operate, so that it can allocate the + initial serial device and any others that are needed. + menuconfig EXPERT bool "Configure standard U-Boot features (expert users)" help diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 17ad567c190..2064efa7619 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -80,6 +80,12 @@ config DM_SPI_FLASH config DM_GPIO default y if !SPL_BUILD +config SYS_MALLOC_F + default y if !SPL_BUILD + +config SYS_MALLOC_F_LEN + default 0x400 if !SPL_BUILD + source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" source "board/samsung/universal_c210/Kconfig" diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 2fe323230fe..46440981b37 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -102,6 +102,12 @@ config DM_GPIO config DM_SERIAL default y if DM && !SPL_BUILD +config SYS_MALLOC_F + default y if DM && !SPL_BUILD + +config SYS_MALLOC_F_LEN + default 0x400 if DM && !SPL_BUILD + config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/tegra-common/Kconfig b/arch/arm/cpu/armv7/tegra-common/Kconfig index 93dc7320c99..ee3246929a3 100644 --- a/arch/arm/cpu/armv7/tegra-common/Kconfig +++ b/arch/arm/cpu/armv7/tegra-common/Kconfig @@ -17,6 +17,12 @@ config TEGRA124 endchoice +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x1800 + config USE_PRIVATE_LIBGCC default y if SPL_BUILD diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 5c5a84fe56c..1a47ac90290 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -48,6 +48,12 @@ config DCC_MICRO_SUPPORT_CARD endchoice +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x2000 + config CMD_PINMON bool "Enable boot mode pins monitor command" default y diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index bb3ff4393ea..35d24e4acae 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -76,6 +76,12 @@ config DM_GPIO config DM_SERIAL default y +config SYS_MALLOC_F + default y + +config SYS_MALLOC_F_LEN + default 0x800 + config RAMBASE hex default 0x100000 diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index d6581ac4687..a20e0c1ab95 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -47,4 +47,10 @@ config DM_GPIO config DM_SERIAL default y if DM && !SPL_BUILD +config SYS_MALLOC_F + default y if DM && !SPL_BUILD + +config SYS_MALLOC_F_LEN + default 0x400 if DM && !SPL_BUILD + endif diff --git a/configs/Linksprite_pcDuino3_fdt_defconfig b/configs/Linksprite_pcDuino3_fdt_defconfig index cfed375fc2c..1e749cded15 100644 --- a/configs/Linksprite_pcDuino3_fdt_defconfig +++ b/configs/Linksprite_pcDuino3_fdt_defconfig @@ -13,3 +13,5 @@ CONFIG_OF_SEPARATE=y +S:CONFIG_DRAM_CLK=480 +S:CONFIG_DRAM_ZQ=122 +S:CONFIG_DRAM_EMR1=4 +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/am335x_igep0033_defconfig b/configs/am335x_igep0033_defconfig index 23f0a32d635..f3544b5238f 100644 --- a/configs/am335x_igep0033_defconfig +++ b/configs/am335x_igep0033_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_AM335X_IGEP0033=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index d2ebf692f36..631698c95dd 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -5,3 +5,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL,SPL" CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/cm_t335_defconfig b/configs/cm_t335_defconfig index 5ff4f9c4a59..5c1d3cf3a5d 100644 --- a/configs/cm_t335_defconfig +++ b/configs/cm_t335_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_CM_T335=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/gwventana_defconfig b/configs/gwventana_defconfig index 4cddbdd6553..5b1a4c4e587 100644 --- a/configs/gwventana_defconfig +++ b/configs/gwventana_defconfig @@ -2,3 +2,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6QDL" +S:CONFIG_ARM=y +S:CONFIG_TARGET_GW_VENTANA=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index b649935912f..ccdfe31992f 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index 7d86700b30a..fe3d7978519 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 67c1b77e05d..09b01905e6f 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index f23d48f361f..72e0f103ec0 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sxsabresd/imximage.cfg,MX6SX" CONFIG_ARM=y CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig index 20a51e1d2fd..1bb7664ed7a 100644 --- a/configs/nokia_rx51_defconfig +++ b/configs/nokia_rx51_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_NOKIA_RX51=y CONFIG_DM=n CONFIG_DM_SERIAL=n CONFIG_DM_GPIO=n +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pcm051_rev1_defconfig b/configs/pcm051_rev1_defconfig index 8b27682997e..baa2b231b05 100644 --- a/configs/pcm051_rev1_defconfig +++ b/configs/pcm051_rev1_defconfig @@ -2,3 +2,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="REV1" +S:CONFIG_ARM=y +S:CONFIG_TARGET_PCM051=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pcm051_rev3_defconfig b/configs/pcm051_rev3_defconfig index 27ad6ff26b1..b5c62a6a3b0 100644 --- a/configs/pcm051_rev3_defconfig +++ b/configs/pcm051_rev3_defconfig @@ -2,3 +2,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="REV3" +S:CONFIG_ARM=y +S:CONFIG_TARGET_PCM051=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pengwyn_defconfig b/configs/pengwyn_defconfig index 1b9aa68260c..cbdd404c70d 100644 --- a/configs/pengwyn_defconfig +++ b/configs/pengwyn_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_PENGWYN=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/pepper_defconfig b/configs/pepper_defconfig index 22c7bb4a606..14266ef8750 100644 --- a/configs/pepper_defconfig +++ b/configs/pepper_defconfig @@ -1,3 +1,5 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_TARGET_PEPPER=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/rpi_defconfig b/configs/rpi_defconfig index 9379cf00d44..98d3199ccdf 100644 --- a/configs/rpi_defconfig +++ b/configs/rpi_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y CONFIG_TARGET_RPI=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index 618e5908025..33e6fb8848c 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_S5P_GONI=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 660063ebf33..0bf5ea34d0c 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -5,3 +5,5 @@ CONFIG_FIT_VERBOSE=y CONFIG_FIT_SIGNATURE=y CONFIG_DM=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 041030f942f..e933a329b62 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -2,3 +2,5 @@ CONFIG_ARM=y CONFIG_TARGET_SMDKC100=y CONFIG_ARCH_S5PC1XX=y CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/snapper9260_defconfig b/configs/snapper9260_defconfig index 035146c6575..97c49f3363a 100644 --- a/configs/snapper9260_defconfig +++ b/configs/snapper9260_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/snapper9g20_defconfig b/configs/snapper9g20_defconfig index 66c44ccf78a..d5f1d9fa196 100644 --- a/configs/snapper9g20_defconfig +++ b/configs/snapper9g20_defconfig @@ -4,3 +4,5 @@ CONFIG_TARGET_SNAPPER9260=y CONFIG_DM=y CONFIG_DM_GPIO=y CONFIG_DM_SERIAL=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index a05e9917b65..37b10ba8939 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="stv0991" CONFIG_ARM=y CONFIG_TARGET_STV0991=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index 40083069441..4207504464d 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -21,10 +21,7 @@ #define CONFIG_MACH_TYPE 4273 #ifndef CONFIG_SPL_BUILD - #define CONFIG_CMD_GPIO - -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif /* Display information on boot */ diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h index 2c4f35af9fe..59676ae61b8 100644 --- a/include/configs/exynos-common.h +++ b/include/configs/exynos-common.h @@ -36,7 +36,6 @@ #define CONFIG_ENV_OVERWRITE /* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* select serial console configuration */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 4f137fc96bf..620f9501d25 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -39,7 +39,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* Init Functions */ #define CONFIG_BOARD_EARLY_INIT_F diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index f0f721e9b7e..80e48d141e8 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -27,7 +27,6 @@ #define CONFIG_DM #define CONFIG_DM_THERMAL -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_IMX6_THERMAL #define CONFIG_SYS_GENERIC_BOARD diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 404b922d39c..1005b9e6bc6 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -229,7 +229,6 @@ #define CONFIG_DM #define CONFIG_DM_THERMAL -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_IMX6_THERMAL #define CONFIG_CMD_FUSE diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h index 6e1f501b64d..46fc91e5e19 100644 --- a/include/configs/nokia_rx51.h +++ b/include/configs/nokia_rx51.h @@ -72,7 +72,6 @@ #define CONFIG_UBI_SIZE (512 << 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ (128 << 10)) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* * Hardware drivers diff --git a/include/configs/novena.h b/include/configs/novena.h index ea75d2c2b97..074110c9395 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -116,7 +116,6 @@ #define CONFIG_SYS_MEMTEST_END 0x20000000 #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* SPL */ #define CONFIG_SPL_FAT_SUPPORT diff --git a/include/configs/rpi.h b/include/configs/rpi.h index ea19ad8d072..7ad8d080215 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -46,7 +46,6 @@ CONFIG_SYS_SDRAM_SIZE - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x00200000 #define CONFIG_LOADADDR 0x00200000 diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 26167a4ece7..8fadc682395 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -40,7 +40,6 @@ #define CONFIG_CMDLINE_EDITING /* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index bff01708f68..5c116508d0d 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -60,7 +60,6 @@ /* * Size of malloc() pool, before and after relocation */ -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_MALLOC_F_ADDR 0x0010000 #define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index a7eb33ed43f..080fc3a8459 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -48,9 +48,6 @@ */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) -/* Small malloc pool before relocation */ -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) - /* * select serial console configuration */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 712f9b74ce4..6c685965a2c 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -21,7 +21,6 @@ #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 #define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) /* CPU */ #define CONFIG_ARCH_CPU_INIT diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index fd9bd638c65..071b1c2ca79 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -28,7 +28,6 @@ (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) -#define CONFIG_SYS_MALLOC_F_LEN 0x2000 #define CONFIG_DM /* serial port (PL011) configuration */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0c5c18cb304..09889eeb443 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -29,7 +29,6 @@ #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_DM) # define CONFIG_DW_SERIAL -# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif /* diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index ef259802525..005fc6aeb37 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -37,7 +37,6 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index 4ce9d49c189..20a55f4aa82 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -21,7 +21,6 @@ #ifndef CONFIG_SPL_BUILD # define CONFIG_OMAP_SERIAL -# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif #include diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 77211de9a50..840e108e053 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -20,7 +20,6 @@ #ifndef CONFIG_SPL_BUILD # define CONFIG_OMAP_SERIAL -# define CONFIG_SYS_MALLOC_F_LEN (1 << 10) #endif /* The chip has SDRC controller */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index 6f4ecc9b04c..3f738fb6420 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -80,8 +80,6 @@ #define CONFIG_SMC911X_BASE CONFIG_SUPPORT_CARD_ETHER_BASE #define CONFIG_SMC911X_32_BIT -#define CONFIG_SYS_MALLOC_F_LEN 0x2000 - /*----------------------------------------------------------------------- * MMU and Cache Setting *----------------------------------------------------------------------*/ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 277a95c199a..994874ca600 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -187,7 +187,6 @@ #define CONFIG_SYS_STACK_SIZE (32 * 1024) #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_MALLOC_LEN 0x200000 -#define CONFIG_SYS_MALLOC_F_LEN (2 << 10) /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -- cgit v1.3.1 From be9891c52d5472156949a3137be5f48355fd3f29 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Feb 2015 16:33:00 -0700 Subject: dm: Drop unused driver model config_defaults These are now in Kconfig so we can drop them from the header file. Signed-off-by: Simon Glass --- include/config_defaults.h | 12 ------------ 1 file changed, 12 deletions(-) (limited to 'include') diff --git a/include/config_defaults.h b/include/config_defaults.h index fa998389573..ad08c1d335d 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -20,16 +20,4 @@ #define CONFIG_ZLIB 1 #define CONFIG_PARTITIONS 1 -#ifndef CONFIG_SPL_BUILD -#ifndef CONFIG_DM_WARN -#define CONFIG_DM_WARN -#endif -#ifndef CONFIG_DM_DEVICE_REMOVE -#define CONFIG_DM_DEVICE_REMOVE -#endif -#ifndef CONFIG_DM_STDIO -#define CONFIG_DM_STDIO -#endif -#endif - #endif -- cgit v1.3.1 From c9cac3f8413c1f67d1e1b7a1770e584584107cd2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 10 Feb 2015 14:46:32 +0800 Subject: dm: introduce dev_get_addr interface Abstracting dev_get_addr can improve drivers that want to get device's address. Signed-off-by: Peng Fan Acked-by: Igor Grinberg Acked-by: Simon Glass --- drivers/core/device.c | 12 ++++++++++++ include/dm/device.h | 10 ++++++++++ 2 files changed, 22 insertions(+) (limited to 'include') diff --git a/drivers/core/device.c b/drivers/core/device.c index b73d3b8961d..73c3e07c28b 100644 --- a/drivers/core/device.c +++ b/drivers/core/device.c @@ -449,3 +449,15 @@ enum uclass_id device_get_uclass_id(struct udevice *dev) { return dev->uclass->uc_drv->id; } + +#ifdef CONFIG_OF_CONTROL +fdt_addr_t dev_get_addr(struct udevice *dev) +{ + return fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); +} +#else +fdt_addr_t dev_get_addr(struct udevice *dev) +{ + return FDT_ADDR_T_NONE; +} +#endif diff --git a/include/dm/device.h b/include/dm/device.h index 81afa8c6281..7a48eb88b8c 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -12,6 +12,7 @@ #define _DM_DEVICE_H #include +#include #include #include @@ -351,4 +352,13 @@ int device_find_first_child(struct udevice *parent, struct udevice **devp); */ int device_find_next_child(struct udevice **devp); +/** + * dev_get_addr() - Get the reg property of a device + * + * @dev: Pointer to a device + * + * @return addr + */ +fdt_addr_t dev_get_addr(struct udevice *dev); + #endif -- cgit v1.3.1 From 3b7f0e109cd3f3fba387784f3f6debd4127cdefd Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 12 Jan 2015 19:17:07 +0300 Subject: arm: rmobile: Add SILK board support SILK is an entry level development board based on R-Car E2 SoC (R8A7794) This commit supports the following peripherals: - SCIF, I2C, Ethernet, QSPI, MMC, USB Host Signed-off-by: Vladimir Barinov Reviewed-by: Tom Rini Signed-off-by: Nobuhiro Iwamatsu --- arch/arm/cpu/armv7/rmobile/Kconfig | 6 +- board/renesas/silk/Kconfig | 12 + board/renesas/silk/MAINTAINERS | 6 + board/renesas/silk/Makefile | 10 + board/renesas/silk/qos.c | 951 +++++++++++++++++++++++++++++++++++++ board/renesas/silk/silk.c | 175 +++++++ configs/silk_defconfig | 3 + include/configs/silk.h | 117 +++++ 8 files changed, 1279 insertions(+), 1 deletion(-) create mode 100644 board/renesas/silk/Kconfig create mode 100644 board/renesas/silk/MAINTAINERS create mode 100644 board/renesas/silk/Makefile create mode 100644 board/renesas/silk/qos.c create mode 100644 board/renesas/silk/silk.c create mode 100644 configs/silk_defconfig create mode 100644 include/configs/silk.h (limited to 'include') diff --git a/arch/arm/cpu/armv7/rmobile/Kconfig b/arch/arm/cpu/armv7/rmobile/Kconfig index 6d94199de85..35866508a38 100644 --- a/arch/arm/cpu/armv7/rmobile/Kconfig +++ b/arch/arm/cpu/armv7/rmobile/Kconfig @@ -21,6 +21,9 @@ config TARGET_KZM9G config TARGET_ALT bool "Alt board" +config TARGET_SILK + bool "Silk board" + endchoice config SYS_SOC @@ -28,7 +31,7 @@ config SYS_SOC config RMOBILE_EXTRAM_BOOT bool "Enable boot from RAM" - depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER + depends on TARGET_ALT || TARGET_KOELSCH || TARGET_LAGER || TARGET_SILK default n source "board/atmark-techno/armadillo-800eva/Kconfig" @@ -37,5 +40,6 @@ source "board/renesas/koelsch/Kconfig" source "board/renesas/lager/Kconfig" source "board/kmc/kzm9g/Kconfig" source "board/renesas/alt/Kconfig" +source "board/renesas/silk/Kconfig" endif diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig new file mode 100644 index 00000000000..07aee0e50f8 --- /dev/null +++ b/board/renesas/silk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SILK + +config SYS_BOARD + default "silk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "silk" + +endif diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS new file mode 100644 index 00000000000..b566ccfbd9e --- /dev/null +++ b/board/renesas/silk/MAINTAINERS @@ -0,0 +1,6 @@ +SILK BOARD +M: Cogent Embedded, Inc. +S: Maintained +F: board/renesas/silk/ +F: include/configs/silk.h +F: configs/silk_defconfig diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile new file mode 100644 index 00000000000..e6eea6142ec --- /dev/null +++ b/board/renesas/silk/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/silk/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# Copyright (C) 2015 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := silk.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c new file mode 100644 index 00000000000..4f6e46ce527 --- /dev/null +++ b/board/renesas/silk/qos.c @@ -0,0 +1,951 @@ +/* + * board/renesas/silk/qos.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include +#include +#include +#include +#include + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.11 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c new file mode 100644 index 00000000000..8818211d32f --- /dev/null +++ b/board/renesas/silk/silk.c @@ -0,0 +1,175 @@ +/* + * board/renesas/silk/silk.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); + +#ifndef CONFIG_DCACHE_OFF + /* + * The caches are disabled when ACTLR.SMP is set to 0 + * regardless of the value of the SCTLR.C (cache enable bit) + * on Cortex-A7 MPCore + */ + asm volatile( + "mrc 15, 0, r0, c1, c0, 1\n" /* read ACTLR */ + "orr r0, r0, #(1 << 6)\n" /* set ACTLR.SMP bit */ + "mcr p15, 0, r0, c1, c0, 1\n"); /* write ACTLR */ +#endif +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF2_MSTP719 (1 << 19) +#define ETHER_MSTP813 (1 << 13) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + /* MMC0 */ + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/configs/silk_defconfig b/configs/silk_defconfig new file mode 100644 index 00000000000..515ee3372bd --- /dev/null +++ b/configs/silk_defconfig @@ -0,0 +1,3 @@ +CONFIG_ARM=y +CONFIG_RMOBILE=y +CONFIG_TARGET_SILK=y diff --git a/include/configs/silk.h b/include/configs/silk.h new file mode 100644 index 00000000000..a4235e94d0e --- /dev/null +++ b/include/configs/silk.h @@ -0,0 +1,117 @@ +/* + * include/configs/silk.h + * This file is silk board configuration. + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __SILK_H +#define __SILK_H + +#undef DEBUG +#define CONFIG_R8A7794 +#define CONFIG_RMOBILE_BOARD_STRING "Silk" + +#include "rcar-gen2-common.h" + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x70000000 +#else +#define CONFIG_SYS_TEXT_BASE 0xE6304000 +#endif + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC +#else +#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC +#endif +#define STACK_AREA_SIZE 0xC000 +#define LOW_LEVEL_MERAM_STACK \ + (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) + +/* MEMORY */ +#define RCAR_GEN2_SDRAM_BASE 0x40000000 +#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) +#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF2 +#define CONFIG_SCIF_USE_EXT_CLK + +/* FLASH */ +#define CONFIG_SPI +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SH_QSPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_QUAD +#define CONFIG_SYS_NO_FLASH + +/* SH Ether */ +#define CONFIG_NET_MULTI +#define CONFIG_SH_ETHER +#define CONFIG_SH_ETHER_USE_PORT 0 +#define CONFIG_SH_ETHER_PHY_ADDR 0x1 +#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII +#define CONFIG_SH_ETHER_CACHE_WRITEBACK +#define CONFIG_SH_ETHER_CACHE_INVALIDATE +#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* Board Clock */ +#define RMOBILE_XTAL_CLK 20000000u +#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK +#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) +#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) +#define CONFIG_SH_SCIF_CLK_FREQ 14745600 /* External Clock */ + +#define CONFIG_SYS_TMU_CLK_DIV 4 + +/* i2c */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SH +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 +#define CONFIG_SYS_I2C_SH_SPEED0 400000 +#define CONFIG_SYS_I2C_SH_SPEED1 400000 +#define CONFIG_SYS_I2C_SH_SPEED2 400000 +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 10000000 + +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ + +/* USB */ +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_RMOBILE +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 + +/* MMCIF */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee200000 +#define CONFIG_SH_MMCIF_CLK 48000000 + +/* Module stop status bits */ +/* INTC-RT */ +#define CONFIG_SMSTP0_ENA 0x00400000 +/* MSIF */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* INTC-SYS, IRQC */ +#define CONFIG_SMSTP4_ENA 0x00000180 +/* SCIF2 */ +#define CONFIG_SMSTP7_ENA 0x00080000 + +#endif /* __SILK_H */ -- cgit v1.3.1 From 1ae067952d509893bee7c267be954d45ab49f9dc Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Feb 2015 13:41:30 -0700 Subject: dm: stv0991: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- configs/stv0991_defconfig | 2 ++ include/configs/stv0991.h | 10 ---------- 2 files changed, 2 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/configs/stv0991_defconfig b/configs/stv0991_defconfig index 37b10ba8939..1c9ba881a4a 100644 --- a/configs/stv0991_defconfig +++ b/configs/stv0991_defconfig @@ -3,3 +3,5 @@ CONFIG_ARM=y CONFIG_TARGET_STV0991=y CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DM=y +CONFIG_DM_SERIAL=y diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h index 071b1c2ca79..156e0fa8e16 100644 --- a/include/configs/stv0991.h +++ b/include/configs/stv0991.h @@ -29,19 +29,9 @@ #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) -#define CONFIG_DM /* serial port (PL011) configuration */ #define CONFIG_BAUDRATE 115200 -#ifdef CONFIG_DM -#define CONFIG_DM_SERIAL #define CONFIG_PL01X_SERIAL -#else -#define CONFIG_SYS_SERIAL0 0x80406000 -#define CONFIG_CONS_INDEX 0 -#define CONFIG_PL011_SERIAL -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} -#define CONFIG_PL011_CLOCK (2700 * 1000) -#endif /* user interface */ #define CONFIG_SYS_PROMPT "STV0991> " -- cgit v1.3.1 From b1f6659c420dae9cd06514fbd8342f39b3f326b9 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 9 Feb 2015 13:41:31 -0700 Subject: dm: mx6: sabre: Move driver model CONFIGs to Kconfig Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass --- configs/mx6dlsabreauto_defconfig | 2 ++ configs/mx6dlsabresd_defconfig | 2 ++ configs/mx6qsabreauto_defconfig | 2 ++ configs/mx6qsabrelite_defconfig | 2 ++ configs/mx6qsabresd_defconfig | 2 ++ configs/mx6sabresd_spl_defconfig | 3 ++- include/configs/mx6sabre_common.h | 2 -- 7 files changed, 12 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/configs/mx6dlsabreauto_defconfig b/configs/mx6dlsabreauto_defconfig index ccdfe31992f..47f3f871ec3 100644 --- a/configs/mx6dlsabreauto_defconfig +++ b/configs/mx6dlsabreauto_defconfig @@ -3,3 +3,5 @@ CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig index 7f6cdff3841..6adfd55708d 100644 --- a/configs/mx6dlsabresd_defconfig +++ b/configs/mx6dlsabresd_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL" CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabreauto_defconfig b/configs/mx6qsabreauto_defconfig index fe3d7978519..ab72942ad59 100644 --- a/configs/mx6qsabreauto_defconfig +++ b/configs/mx6qsabreauto_defconfig @@ -3,3 +3,5 @@ CONFIG_ARM=y CONFIG_TARGET_MX6QSABREAUTO=y CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabrelite_defconfig b/configs/mx6qsabrelite_defconfig index dfa9c2e4db1..50b75aee20b 100644 --- a/configs/mx6qsabrelite_defconfig +++ b/configs/mx6qsabrelite_defconfig @@ -1,3 +1,5 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,SABRELITE" CONFIG_ARM=y CONFIG_TARGET_NITROGEN6X=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig index 09b01905e6f..112918b1bbf 100644 --- a/configs/mx6qsabresd_defconfig +++ b/configs/mx6qsabresd_defconfig @@ -3,3 +3,5 @@ CONFIG_ARM=y CONFIG_TARGET_MX6SABRESD=y CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig index 12e784435cd..67079ba0cfe 100644 --- a/configs/mx6sabresd_spl_defconfig +++ b/configs/mx6sabresd_spl_defconfig @@ -2,4 +2,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6Q" +S:CONFIG_ARM=y +S:CONFIG_TARGET_MX6SABRESD=y - +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index 80e48d141e8..4aa81015240 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -25,8 +25,6 @@ #define CONFIG_INITRD_TAG #define CONFIG_REVISION_TAG -#define CONFIG_DM -#define CONFIG_DM_THERMAL #define CONFIG_IMX6_THERMAL #define CONFIG_SYS_GENERIC_BOARD -- cgit v1.3.1 From af21f2fb6f7a1178a98f1172bf5df7b7fd8545ee Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sat, 7 Feb 2015 13:38:19 +0100 Subject: config_distro_bootcmd.h: Enable CONFIG_CMD_PART The recent changes to config_distro_bootcmd.h require CONFIG_CMD_PART to be defined, as the default bootcmd now uses the "part" command. This fixes sunxi boards not booting with v2015.04-rc1. Signed-off-by: Hans de Goede Acked-by: Stephen Warren --- include/config_distro_bootcmd.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 49674f45375..07a0b3b2347 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -10,6 +10,10 @@ #ifndef _CONFIG_CMD_DISTRO_BOOTCMD_H #define _CONFIG_CMD_DISTRO_BOOTCMD_H +/* We need the part command */ +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + #define BOOTENV_SHARED_BLKDEV_BODY(devtypel) \ "if " #devtypel " dev ${devnum}; then " \ "setenv devtype " #devtypel "; " \ -- cgit v1.3.1 From 5633a296ebb970d0a6be839fb37eaf8a11aa35f8 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 2 Feb 2015 17:13:29 +0100 Subject: sunxi: video: Do not use CONFIG_SYS_MEM_TOP_HIDE for the framebuffer Do not use CONFIG_SYS_MEM_TOP_HIDE for the framebuffer, instead override board_get_usable_ram_top to make sure that u-boot is not relocated into the area where we want to use the framebuffer, and patch the devicetree from sunxi_simplefb_setup() to tell the kernel to not touch the framebuffer. This makes u-boot properly see the framebuffer as dram, and initalize the level 2 cache for it, fixing the very slow cfb scrolling problem. As an added bonus this stops us from reserving the framebuffer when simplefb is not used because an older kernel is booted, or hdp is used and no hdmi cable was plugged in, freeing up the memory for kernel use in these cases. Reported-by: Siarhei Siamashka Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- drivers/video/sunxi_display.c | 22 +++++++++++++++++++++- include/configs/sunxi-common.h | 8 +++----- 2 files changed, 24 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/drivers/video/sunxi_display.c b/drivers/video/sunxi_display.c index f5f24fc020b..cd5963a7514 100644 --- a/drivers/video/sunxi_display.c +++ b/drivers/video/sunxi_display.c @@ -1060,6 +1060,11 @@ static const char *sunxi_get_mon_desc(enum sunxi_monitor monitor) return NULL; /* never reached */ } +ulong board_get_usable_ram_top(ulong total_size) +{ + return gd->ram_top - CONFIG_SUNXI_MAX_FB_SIZE; +} + void *video_hw_init(void) { static GraphicDevice *graphic_device = &sunxi_display.graphic_device; @@ -1076,7 +1081,7 @@ void *video_hw_init(void) memset(&sunxi_display, 0, sizeof(struct sunxi_display)); printf("Reserved %dkB of RAM for Framebuffer.\n", - CONFIG_SUNXI_FB_SIZE >> 10); + CONFIG_SUNXI_MAX_FB_SIZE >> 10); gd->fb_base = gd->ram_top; video_get_ctfb_res_modes(RES_MODE_1024x768, 24, &mode, @@ -1194,6 +1199,7 @@ int sunxi_simplefb_setup(void *blob) { static GraphicDevice *graphic_device = &sunxi_display.graphic_device; int offset, ret; + u64 start, size; const char *pipeline = NULL; #ifdef CONFIG_MACH_SUN4I @@ -1237,6 +1243,20 @@ int sunxi_simplefb_setup(void *blob) return 0; /* Keep older kernels working */ } + /* + * Do not report the framebuffer as free RAM to the OS, note we cannot + * use fdt_add_mem_rsv() here, because then it is still seen as RAM, + * and e.g. Linux refuses to iomap RAM on ARM, see: + * linux/arch/arm/mm/ioremap.c around line 301. + */ + start = gd->bd->bi_dram[0].start; + size = gd->bd->bi_dram[0].size - CONFIG_SUNXI_MAX_FB_SIZE; + ret = fdt_fixup_memory_banks(blob, &start, &size, 1); + if (ret) { + eprintf("Cannot setup simplefb: Error reserving memory\n"); + return ret; + } + ret = fdt_setup_simplefb_node(blob, offset, gd->fb_base, graphic_device->winSizeX, graphic_device->winSizeY, graphic_device->winSizeX * graphic_device->gdfBytesPP, diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index cea52dbf7b7..33c06146c6d 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -210,10 +210,10 @@ #ifdef CONFIG_VIDEO /* - * The amount of RAM that is reserved for the FB. This will not show up as - * RAM to the kernel, but will be reclaimed by a KMS driver in future. + * The amount of RAM to keep free at the top of RAM when relocating u-boot, + * to use as framebuffer. This must be a multiple of 4096. */ -#define CONFIG_SUNXI_FB_SIZE (9 << 20) +#define CONFIG_SUNXI_MAX_FB_SIZE (9 << 20) /* Do we want to initialize a simple FB? */ #define CONFIG_VIDEO_DT_SIMPLEFB @@ -231,8 +231,6 @@ /* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ #define CONFIG_VGA_AS_SINGLE_DEVICE -#define CONFIG_SYS_MEM_TOP_HIDE ((CONFIG_SUNXI_FB_SIZE + 0xFFF) & ~0xFFF) - /* To be able to hook simplefb into dt */ #ifdef CONFIG_VIDEO_DT_SIMPLEFB #define CONFIG_OF_BOARD_SETUP -- cgit v1.3.1 From 942cb0b6a29f74507adeb0bce7ff7f23f69faf84 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Sat, 7 Feb 2015 10:47:30 -0700 Subject: sunxi: Normalise FEL support Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove these. This series is available at u-boot-dm, branch sunxi-working. Signed-off-by: Simon Glass Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- arch/arm/cpu/armv7/start.S | 5 +- arch/arm/cpu/armv7/sunxi/Makefile | 4 +- arch/arm/cpu/armv7/sunxi/board.c | 21 ++++++++ arch/arm/cpu/armv7/sunxi/config.mk | 2 - arch/arm/cpu/armv7/sunxi/fel_utils.S | 25 +++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds | 82 ----------------------------- arch/arm/include/asm/arch-sunxi/sys_proto.h | 10 ++++ board/sunxi/Kconfig | 10 ++++ include/configs/sunxi-common.h | 6 +-- scripts/Makefile.spl | 2 - 10 files changed, 73 insertions(+), 94 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/fel_utils.S delete mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds (limited to 'include') diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 9b49ece2d65..098a83ab714 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -54,7 +54,8 @@ save_boot_params_ret: * (OMAP4 spl TEXT_BASE is not 32 byte aligned. * Continue to use ROM code vector only in OMAP4 spl) */ -#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) && \ + !defined(CONFIG_SPL_FEL) /* Set V=0 in CP15 SCTLR register - for VBAR to point to vector */ mrc p15, 0, r0, c1, c0, 0 @ Read CP15 SCTLR Register bic r0, #CR_V @ V = 0 @@ -67,7 +68,9 @@ save_boot_params_ret: /* the mask ROM code should have PLL and others stable */ #ifndef CONFIG_SKIP_LOWLEVEL_INIT +#ifndef CONFIG_SPL_FEL bl cpu_init_cp15 +#endif bl cpu_init_crit #endif diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index a790a2392f9..4bb12ad8bdb 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -39,7 +39,5 @@ obj-$(CONFIG_MACH_SUN5I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN6I) += dram_sun6i.o obj-$(CONFIG_MACH_SUN7I) += dram_sun4i.o obj-$(CONFIG_MACH_SUN8I) += dram_sun8i.o -ifdef CONFIG_SPL_FEL -obj-y += start.o -endif +obj-y += fel_utils.o endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 6e28bcd0406..b7492ac1fe5 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -27,6 +27,13 @@ #include +struct fel_stash { + uint32_t sp; + uint32_t lr; +}; + +struct fel_stash fel_stash __attribute__((section(".data"))); + static int gpio_init(void) { #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) @@ -65,6 +72,12 @@ static int gpio_init(void) return 0; } +void spl_board_load_image(void) +{ + debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr); + return_to_fel(fel_stash.sp, fel_stash.lr); +} + void s_init(void) { #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I @@ -95,6 +108,14 @@ void s_init(void) */ u32 spl_boot_device(void) { + /* + * Have we been asked to return to the FEL portion of the boot ROM? + * TODO: We need a more robust test here, or bracket this with + * #ifdef CONFIG_SPL_FEL. + */ + if (fel_stash.lr >= 0xffff0000 && fel_stash.lr < 0xffff4000) + return BOOT_DEVICE_BOARD; + return BOOT_DEVICE_MMC1; } diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk index 00f5ffc6830..76ffec9df6a 100644 --- a/arch/arm/cpu/armv7/sunxi/config.mk +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -1,8 +1,6 @@ # Build a combined spl + u-boot image ifdef CONFIG_SPL ifndef CONFIG_SPL_BUILD -ifndef CONFIG_SPL_FEL ALL-y += u-boot-sunxi-with-spl.bin endif endif -endif diff --git a/arch/arm/cpu/armv7/sunxi/fel_utils.S b/arch/arm/cpu/armv7/sunxi/fel_utils.S new file mode 100644 index 00000000000..0c1de52df88 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/fel_utils.S @@ -0,0 +1,25 @@ +/* + * Utility functions for FEL mode. + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +ENTRY(save_boot_params) + ldr r0, =fel_stash + str sp, [r0, #0] + str lr, [r0, #4] + b save_boot_params_ret +ENDPROC(save_boot_params) + +ENTRY(return_to_fel) + mov sp, r0 + mov lr, r1 + bx lr +ENDPROC(return_to_fel) diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds deleted file mode 100644 index 928b7c19e03..00000000000 --- a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2013 - * Henrik Nordstrom - * - * SPDX-License-Identifier: GPL-2.0+ - */ -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(s_init) -SECTIONS -{ - . = 0x00002000; - - . = ALIGN(4); - .text : - { - *(.text.s_init) - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } - - . = ALIGN(4); - .data : { - *(.data*) - } - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - . = ALIGN(4); - . = .; - - . = ALIGN(4); - .rel.dyn : { - __rel_dyn_start = .; - *(.rel*) - __rel_dyn_end = .; - } - - .dynsym : { - __dynsym_start = .; - *(.dynsym) - } - - . = ALIGN(4); - .note.gnu.build-id : - { - *(.note.gnu.build-id) - } - _end = .; - - . = ALIGN(4096); - .mmutable : { - *(.mmutable) - } - - .bss_start __rel_dyn_start (OVERLAY) : { - KEEP(*(.__bss_start)); - __bss_base = .; - } - - .bss __bss_base (OVERLAY) : { - *(.bss*) - . = ALIGN(4); - __bss_limit = .; - } - - .bss_end __bss_limit (OVERLAY) : { - KEEP(*(.__bss_end)); - } - - /DISCARD/ : { *(.dynstr*) } - /DISCARD/ : { *(.dynamic*) } - /DISCARD/ : { *(.plt*) } - /DISCARD/ : { *(.interp*) } - /DISCARD/ : { *(.gnu*) } - /DISCARD/ : { *(.note*) } -} diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index c3e636e1d9b..60a5bd8c850 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -13,4 +13,14 @@ void sdelay(unsigned long); +/* return_to_fel() - Return to BROM from SPL + * + * This returns back into the BROM after U-Boot SPL has performed its initial + * init. It uses the provided lr and sp to do so. + * + * @lr: BROM link register value (return address) + * @sp: BROM stack pointer + */ +void return_to_fel(uint32_t lr, uint32_t sp); + #endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 4a2158988fc..3eab81fd12b 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -149,6 +149,16 @@ config SPL_FEL bool "SPL/FEL mode support" depends on SPL default n + help + This enables support for Fast Early Loader (FEL) mode. This + allows U-Boot to be loaded to the board over USB by the on-chip + boot rom. U-Boot should be sent in two parts: SPL first, with + 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with + 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option + shrinks the amount of SRAM available to SPL, so only enable it if + you need FEL. Note that enabling this option only allows FEL to be + used; it is still possible to boot U-Boot from boot media. U-Boot + SPL detects when it is being loaded using FEL. config UART0_PORT_F bool "UART0 on MicroSD breakout board" diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 33c06146c6d..5ece0202a6c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -18,10 +18,8 @@ */ #define CONFIG_SUNXI /* sunxi family */ #ifdef CONFIG_SPL_BUILD -#ifndef CONFIG_SPL_FEL #define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ #endif -#endif #include /* get chip and board defs */ @@ -149,10 +147,10 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_BOARD_LOAD_IMAGE + #ifdef CONFIG_SPL_FEL -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" #define CONFIG_SPL_TEXT_BASE 0x2000 #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index e4b98811867..cc189adc0c6 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -154,10 +154,8 @@ ALL-y += $(obj)/$(BOARD)-spl.bin endif ifdef CONFIG_SUNXI -ifndef CONFIG_SPL_FEL ALL-y += $(obj)/sunxi-spl.bin endif -endif ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += boot.bin -- cgit v1.3.1 From 2973b098baf6fcb49d9fb7a2ed187e6a65532175 Mon Sep 17 00:00:00 2001 From: Valentin Longchamp Date: Tue, 10 Feb 2015 17:10:17 +0100 Subject: 82xx/km82xx: read the IVM eeprom earlier This allows to define the ethaddr env variable according to the the IVM content by reading the IVM in misc_init_r. Later, when HUSH is available the content read earlier is analyzed to populate some non env variables. Signed-off-by: Valentin Longchamp --- board/keymile/km82xx/km82xx.c | 10 +++++++++- include/configs/km82xx.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index bf84676b9bd..c3a113172c0 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -18,6 +18,8 @@ #include #include "../common/common.h" +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + /* * I/O Port configuration table * @@ -393,9 +395,15 @@ int board_early_init_r(void) return 0; } +int misc_init_r(void) +{ + ivm_simple_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} + int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } diff --git a/include/configs/km82xx.h b/include/configs/km82xx.h index 14fd290be1f..12f9d424cb1 100644 --- a/include/configs/km82xx.h +++ b/include/configs/km82xx.h @@ -34,6 +34,8 @@ #define CONFIG_SYS_TEXT_BASE 0xFE000000 +#define CONFIG_MISC_INIT_R + /* include common defines/options for all Keymile boards */ #include "km/keymile-common.h" #include "km/km-powerpc.h" -- cgit v1.3.1 From 5290ab876e18d87bd51e29520494abc6473806ec Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Mon, 16 Feb 2015 15:48:49 -0500 Subject: Revert "sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART" This reverts commit bd2a4888b123713adec271d6c8040ca9f609aa2f which was an older version of af21f2f which is what we actually want in. Signed-off-by: Tom Rini --- include/configs/sunxi-common.h | 3 --- 1 file changed, 3 deletions(-) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5e8885277f0..1238d821b36 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -79,9 +79,6 @@ #define CONFIG_CMD_MEMORY #define CONFIG_CMD_SETEXPR -#define CONFIG_PARTITION_UUIDS -#define CONFIG_CMD_PART - #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -- cgit v1.3.1 From dbdb5abd070163f59901884c672b49c25b1aeea9 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 6 Feb 2015 23:06:39 +0100 Subject: avr32: use dlmalloc for DMA buffers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- arch/avr32/include/asm/dma-mapping.h | 7 ++++- arch/avr32/lib/board.c | 51 ------------------------------------ include/configs/atngw100.h | 1 - include/configs/atngw100mkii.h | 1 - include/configs/atstk1002.h | 1 - include/configs/atstk1006.h | 1 - include/configs/favr-32-ezkit.h | 1 - include/configs/grasshopper.h | 1 - include/configs/hammerhead.h | 1 - include/configs/mimc200.h | 1 - 10 files changed, 6 insertions(+), 60 deletions(-) (limited to 'include') diff --git a/arch/avr32/include/asm/dma-mapping.h b/arch/avr32/include/asm/dma-mapping.h index dbdd2fee380..1cde8275f4f 100644 --- a/arch/avr32/include/asm/dma-mapping.h +++ b/arch/avr32/include/asm/dma-mapping.h @@ -14,7 +14,12 @@ enum dma_data_direction { DMA_TO_DEVICE = 1, DMA_FROM_DEVICE = 2, }; -extern void *dma_alloc_coherent(size_t len, unsigned long *handle); + +static inline void *dma_alloc_coherent(size_t len, unsigned long *handle) +{ + *handle = (unsigned long)memalign(ARCH_DMA_MINALIGN, len); + return (void *)*handle; +} static inline unsigned long dma_map_single(volatile void *vaddr, size_t len, enum dma_data_direction dir) diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index bf0997f98dc..7d13ac534b8 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -45,50 +45,6 @@ int cpu_mmc_init(bd_t *bd) return atmel_mci_init((void *)ATMEL_BASE_MMCI); } -#ifdef CONFIG_SYS_DMA_ALLOC_LEN -#include -#include - -static unsigned long dma_alloc_start; -static unsigned long dma_alloc_end; -static unsigned long dma_alloc_brk; - -static void dma_alloc_init(void) -{ - unsigned long monitor_addr; - - monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off; - dma_alloc_end = monitor_addr - CONFIG_SYS_MALLOC_LEN; - dma_alloc_start = dma_alloc_end - CONFIG_SYS_DMA_ALLOC_LEN; - dma_alloc_brk = dma_alloc_start; - - printf("DMA: Using memory from 0x%08lx to 0x%08lx\n", - dma_alloc_start, dma_alloc_end); - - invalidate_dcache_range((unsigned long)cached(dma_alloc_start), - dma_alloc_end); -} - -void *dma_alloc_coherent(size_t len, unsigned long *handle) -{ - unsigned long paddr = dma_alloc_brk; - - if (dma_alloc_brk + len > dma_alloc_end) - return NULL; - - dma_alloc_brk = ((paddr + len + CONFIG_SYS_DCACHE_LINESZ - 1) - & ~(CONFIG_SYS_DCACHE_LINESZ - 1)); - - *handle = paddr; - return uncached(paddr); -} -#else -static inline void dma_alloc_init(void) -{ - -} -#endif - static int init_baudrate(void) { gd->baudrate = getenv_ulong("baudrate", 10, CONFIG_BAUDRATE); @@ -180,12 +136,6 @@ void board_init_f(ulong board_type) /* Reserve memory for malloc() */ addr -= CONFIG_SYS_MALLOC_LEN; -#ifdef CONFIG_SYS_DMA_ALLOC_LEN - /* Reserve DMA memory (must be cache aligned) */ - addr &= ~(CONFIG_SYS_DCACHE_LINESZ - 1); - addr -= CONFIG_SYS_DMA_ALLOC_LEN; -#endif - #ifdef CONFIG_LCD #ifdef CONFIG_FB_ADDR printf("LCD: Frame buffer allocated at preset 0x%08x\n", @@ -264,7 +214,6 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) /* The malloc area is right below the monitor image in RAM */ mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off - CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN); - dma_alloc_init(); enable_interrupts(); diff --git a/include/configs/atngw100.h b/include/configs/atngw100.h index 9c81e3199f9..540e86ae478 100644 --- a/include/configs/atngw100.h +++ b/include/configs/atngw100.h @@ -143,7 +143,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/atngw100mkii.h b/include/configs/atngw100mkii.h index 7b4f9cf2063..35eae769301 100644 --- a/include/configs/atngw100mkii.h +++ b/include/configs/atngw100mkii.h @@ -164,7 +164,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 8f3fd0bb000..9e58238f1d1 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -158,7 +158,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/atstk1006.h b/include/configs/atstk1006.h index bbe0aea8616..25090a68fa7 100644 --- a/include/configs/atstk1006.h +++ b/include/configs/atstk1006.h @@ -159,7 +159,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/favr-32-ezkit.h b/include/configs/favr-32-ezkit.h index 338d3dc7823..75bff4ce288 100644 --- a/include/configs/favr-32-ezkit.h +++ b/include/configs/favr-32-ezkit.h @@ -162,7 +162,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 73534addfc1..83f0ed2a622 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -151,7 +151,6 @@ CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) diff --git a/include/configs/hammerhead.h b/include/configs/hammerhead.h index 4f0603abc13..0bc42f12e0a 100644 --- a/include/configs/hammerhead.h +++ b/include/configs/hammerhead.h @@ -137,7 +137,6 @@ #define CONFIG_SYS_MALLOC_LEN (256*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000) diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index fc7ecfaee47..2fd3addc1ad 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -157,7 +157,6 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE) #define CONFIG_SYS_MALLOC_LEN (1024*1024) -#define CONFIG_SYS_DMA_ALLOC_LEN (16384) /* Allow 4MB for the kernel run-time image */ #define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) -- cgit v1.3.1 From 68145d4c7b3aa83d74c2dc904a39fab17cee1691 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 6 Feb 2015 23:06:45 +0100 Subject: common/board_f: factor out reserve_stacks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Introduce arch_reserve_stacks() to tailor gd->start_addr_sp and gd->irq_sp to the architecture needs. Signed-off-by: Andreas Bießmann Reviewed-by: Simon Glass --- arch/arm/lib/Makefile | 1 + arch/arm/lib/stack.c | 42 ++++++++++++++++++++++++++++++++++++++++++ arch/powerpc/lib/Makefile | 1 + arch/powerpc/lib/stack.c | 31 +++++++++++++++++++++++++++++++ common/board_f.c | 44 +++++++++----------------------------------- include/common.h | 18 ++++++++++++++++++ 6 files changed, 102 insertions(+), 35 deletions(-) create mode 100644 arch/arm/lib/stack.c create mode 100644 arch/powerpc/lib/stack.c (limited to 'include') diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index d74e4b8415f..da8ed72a11e 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -35,6 +35,7 @@ endif obj-$(CONFIG_SEMIHOSTING) += semihosting.o obj-y += sections.o +obj-y += stack.o ifdef CONFIG_ARM64 obj-y += gic_64.o obj-y += interrupts_64.o diff --git a/arch/arm/lib/stack.c b/arch/arm/lib/stack.c new file mode 100644 index 00000000000..cf10a53ec6f --- /dev/null +++ b/arch/arm/lib/stack.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 Andreas Bießmann + * + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_reserve_stacks(void) +{ +#ifdef CONFIG_SPL_BUILD + gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ + gd->irq_sp = gd->start_addr_sp; +#else + /* setup stack pointer for exceptions */ + gd->irq_sp = gd->start_addr_sp; + +# if !defined(CONFIG_ARM64) +# ifdef CONFIG_USE_IRQ + gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); + debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", + CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); + + /* 8-byte alignment for ARM ABI compliance */ + gd->start_addr_sp &= ~0x07; +# endif + /* leave 3 words for abort-stack, plus 1 for alignment */ + gd->start_addr_sp -= 16; +# endif +#endif + + return 0; +} diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 0f6298269a7..05b22bb5f70 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -40,6 +40,7 @@ obj-y += extable.o obj-y += interrupts.o obj-$(CONFIG_CMD_KGDB) += kgdb.o obj-$(CONFIG_CMD_IDE) += ide.o +obj-y += stack.o obj-y += time.o # Don't include the MPC5xxx special memcpy into the diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c new file mode 100644 index 00000000000..1985f0348de --- /dev/null +++ b/arch/powerpc/lib/stack.c @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2015 Andreas Bießmann + * + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2002-2006 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include + +DECLARE_GLOBAL_DATA_PTR; + +int arch_reserve_stacks(void) +{ + ulong *s; + + /* setup stack pointer for exceptions */ + gd->irq_sp = gd->start_addr_sp; + + /* Clear initial stack frame */ + s = (ulong *)gd->start_addr_sp; + *s = 0; /* Terminate back chain */ + *++s = 0; /* NULL return address */ + + return 0; +} diff --git a/common/board_f.c b/common/board_f.c index 2c10215a177..ef3f036dadc 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -573,48 +573,22 @@ static int reserve_fdt(void) return 0; } -static int reserve_stacks(void) +int arch_reserve_stacks(void) { -#ifdef CONFIG_SPL_BUILD -# ifdef CONFIG_ARM - gd->start_addr_sp -= 128; /* leave 32 words for abort-stack */ - gd->irq_sp = gd->start_addr_sp; -# endif -#else -# ifdef CONFIG_PPC - ulong *s; -# endif + return 0; +} - /* setup stack pointer for exceptions */ +static int reserve_stacks(void) +{ + /* make stack pointer 16-byte aligned */ gd->start_addr_sp -= 16; gd->start_addr_sp &= ~0xf; - gd->irq_sp = gd->start_addr_sp; /* - * Handle architecture-specific things here - * TODO(sjg@chromium.org): Perhaps create arch_reserve_stack() - * to handle this and put in arch/xxx/lib/stack.c + * let the architecture specific code tailor gd->start_addr_sp and + * gd->irq_sp */ -# if defined(CONFIG_ARM) && !defined(CONFIG_ARM64) -# ifdef CONFIG_USE_IRQ - gd->start_addr_sp -= (CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ); - debug("Reserving %zu Bytes for IRQ stack at: %08lx\n", - CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ, gd->start_addr_sp); - - /* 8-byte alignment for ARM ABI compliance */ - gd->start_addr_sp &= ~0x07; -# endif - /* leave 3 words for abort-stack, plus 1 for alignment */ - gd->start_addr_sp -= 16; -# elif defined(CONFIG_PPC) - /* Clear initial stack frame */ - s = (ulong *) gd->start_addr_sp; - *s = 0; /* Terminate back chain */ - *++s = 0; /* NULL return address */ -# endif /* Architecture specific code */ - - return 0; -#endif + return arch_reserve_stacks(); } static int display_new_sp(void) diff --git a/include/common.h b/include/common.h index 91294547f5c..77c55c6f26d 100644 --- a/include/common.h +++ b/include/common.h @@ -252,6 +252,24 @@ static inline int print_cpuinfo(void) int update_flash_size(int flash_size); int arch_early_init_r(void); +/** + * Reserve all necessary stacks + * + * This is used in generic board init sequence in common/board_f.c. Each + * architecture could provide this function to tailor the required stacks. + * + * On entry gd->start_addr_sp is pointing to the suggested top of the stack. + * The callee ensures gd->start_add_sp is 16-byte aligned, so architectures + * require only this can leave it untouched. + * + * On exit gd->start_addr_sp and gd->irq_sp should be set to the respective + * positions of the stack. The stack pointer(s) will be set to this later. + * gd->irq_sp is only required, if the architecture needs it. + * + * @return 0 if no error + */ +__weak int arch_reserve_stacks(void); + /** * Show the DRAM size in a board-specific way * -- cgit v1.3.1 From a752a8b4c49d67daa4ea9f9ebac3972bb1c2328b Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 6 Feb 2015 23:06:48 +0100 Subject: avr32: add generic board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- arch/avr32/config.mk | 3 +++ arch/avr32/cpu/u-boot.lds | 2 ++ arch/avr32/include/asm/config.h | 1 + arch/avr32/include/asm/u-boot.h | 7 +++++++ arch/avr32/lib/Makefile | 2 ++ arch/avr32/lib/interrupts.c | 5 +++++ common/board_f.c | 2 +- common/board_r.c | 13 ++++++++++--- common/cmd_bdinfo.c | 4 ++-- include/asm-generic/u-boot.h | 4 ++++ 10 files changed, 37 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/arch/avr32/config.mk b/arch/avr32/config.mk index 469185e8b44..8252f598c3b 100644 --- a/arch/avr32/config.mk +++ b/arch/avr32/config.mk @@ -9,6 +9,9 @@ ifeq ($(CROSS_COMPILE),) CROSS_COMPILE := avr32-linux- endif +# avr32 has generic board support +__HAVE_ARCH_GENERIC_BOARD := y + CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 PLATFORM_RELFLAGS += -ffixed-r5 -fPIC -mno-init-got -mrelax diff --git a/arch/avr32/cpu/u-boot.lds b/arch/avr32/cpu/u-boot.lds index cb29a22b1ea..b0180e35345 100644 --- a/arch/avr32/cpu/u-boot.lds +++ b/arch/avr32/cpu/u-boot.lds @@ -48,9 +48,11 @@ SECTIONS _edata = .; .bss (NOLOAD) : { + __bss_start = .; *(.bss) *(.bss.*) } . = ALIGN(8); __bss_end = .; + __init_end = .; } diff --git a/arch/avr32/include/asm/config.h b/arch/avr32/include/asm/config.h index 63056a4dfa1..529fe227a6b 100644 --- a/arch/avr32/include/asm/config.h +++ b/arch/avr32/include/asm/config.h @@ -8,5 +8,6 @@ #define _ASM_CONFIG_H_ #define CONFIG_NEEDS_MANUAL_RELOC +#define CONFIG_SYS_GENERIC_GLOBAL_DATA #endif diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index 232350ead8c..8b047ec7c8b 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -6,6 +6,11 @@ #ifndef __ASM_U_BOOT_H__ #define __ASM_U_BOOT_H__ 1 +#ifdef CONFIG_SYS_GENERIC_BOARD +/* Use the generic board which requires a unified bd_info */ +#include +#else + typedef struct bd_info { unsigned char bi_phy_id[4]; unsigned long bi_board_number; @@ -22,6 +27,8 @@ typedef struct bd_info { #define bi_memstart bi_dram[0].start #define bi_memsize bi_dram[0].size +#endif + /* For image.h:image_check_target_arch() */ #define IH_ARCH_DEFAULT IH_ARCH_AVR32 diff --git a/arch/avr32/lib/Makefile b/arch/avr32/lib/Makefile index 5f2d97bfc7d..67509136308 100644 --- a/arch/avr32/lib/Makefile +++ b/arch/avr32/lib/Makefile @@ -8,7 +8,9 @@ # obj-y += memset.o +ifndef CONFIG_SYS_GENERIC_BOARD obj-y += board.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += interrupts.o obj-y += dram_init.o diff --git a/arch/avr32/lib/interrupts.c b/arch/avr32/lib/interrupts.c index bacb2d186ad..5f3a49e1521 100644 --- a/arch/avr32/lib/interrupts.c +++ b/arch/avr32/lib/interrupts.c @@ -7,6 +7,11 @@ #include +int interrupt_init(void) +{ + return 0; +} + void enable_interrupts(void) { asm volatile("csrf %0" : : "n"(SYSREG_GM_OFFSET)); diff --git a/common/board_f.c b/common/board_f.c index ef3f036dadc..4d8b8a626be 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -883,7 +883,7 @@ static init_fnc_t init_sequence_f[] = { #endif announce_dram_init, /* TODO: unify all these dram functions? */ -#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) +#if defined(CONFIG_ARM) || defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) dram_init, /* configure available RAM banks */ #endif #if defined(CONFIG_MIPS) || defined(CONFIG_PPC) diff --git a/common/board_r.c b/common/board_r.c index f0b4f9d9351..4fcd4f6a705 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -55,6 +55,9 @@ #include #include #include +#ifdef CONFIG_AVR32 +#include +#endif DECLARE_GLOBAL_DATA_PTR; @@ -498,7 +501,7 @@ static int initr_api(void) #endif /* enable exceptions */ -#ifdef CONFIG_ARM +#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) static int initr_enable_interrupts(void) { enable_interrupts(); @@ -825,10 +828,10 @@ init_fnc_t init_sequence_r[] = { initr_kgdb, #endif interrupt_init, -#if defined(CONFIG_ARM) +#if defined(CONFIG_ARM) || defined(CONFIG_AVR32) initr_enable_interrupts, #endif -#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) +#if defined(CONFIG_X86) || defined(CONFIG_MICROBLAZE) || defined(CONFIG_AVR32) timer_init, /* initialize timer */ #endif #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) @@ -893,6 +896,10 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) int i; #endif +#ifdef CONFIG_AVR32 + mmu_init_r(dest_addr); +#endif + #if !defined(CONFIG_X86) && !defined(CONFIG_ARM) && !defined(CONFIG_ARM64) gd = new_gd; #endif diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index e9eab232f96..aa81da227b9 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -345,8 +345,8 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bd_t *bd = gd->bd; print_num("boot_params", (ulong)bd->bi_boot_params); - print_num("memstart", (ulong)bd->bi_memstart); - print_lnum("memsize", (u64)bd->bi_memsize); + print_num("memstart", (ulong)bd->bi_dram[0].start); + print_lnum("memsize", (u64)bd->bi_dram[0].size); print_num("flashstart", (ulong)bd->bi_flashstart); print_num("flashsize", (ulong)bd->bi_flashsize); print_num("flashoffset", (ulong)bd->bi_flashoffset); diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h index aef39d78846..a63a87a2871 100644 --- a/include/asm-generic/u-boot.h +++ b/include/asm-generic/u-boot.h @@ -32,6 +32,10 @@ typedef struct bd_info { unsigned long bi_flashoffset; /* reserved area for startup monitor */ unsigned long bi_sramstart; /* start of SRAM memory */ unsigned long bi_sramsize; /* size of SRAM memory */ +#ifdef CONFIG_AVR32 + unsigned char bi_phy_id[4]; /* PHY address for ATAG_ETHERNET */ + unsigned long bi_board_number;/* ATAG_BOARDINFO */ +#endif #ifdef CONFIG_ARM unsigned long bi_arm_freq; /* arm frequency */ unsigned long bi_dsp_freq; /* dsp core frequency */ -- cgit v1.3.1 From 573feec8a43bd1b44134a1a5ce10676b577d0358 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 6 Feb 2015 23:06:49 +0100 Subject: grasshopper: enable generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/grasshopper.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/grasshopper.h b/include/configs/grasshopper.h index 83f0ed2a622..54eb9777d77 100644 --- a/include/configs/grasshopper.h +++ b/include/configs/grasshopper.h @@ -62,6 +62,10 @@ #define CONFIG_USART_BASE ATMEL_BASE_USART1 #define CONFIG_USART_ID 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R + /* User serviceable stuff */ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS -- cgit v1.3.1 From 5c98d7ffb0b11c9e3909f56ec5ce9dff682f1e30 Mon Sep 17 00:00:00 2001 From: Andreas Bießmann Date: Fri, 6 Feb 2015 23:06:50 +0100 Subject: atstk1002: enable generic board MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Bießmann --- include/configs/atstk1002.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 9e58238f1d1..a9c064a45df 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -104,6 +104,10 @@ #define CONFIG_BOOTP_SUBNETMASK #define CONFIG_BOOTP_GATEWAY +/* generic board */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* * Command line configuration. -- cgit v1.3.1 From 90fbee3e4051badff770a0ee1b1ca21cb808d634 Mon Sep 17 00:00:00 2001 From: Joe Hershberger Date: Wed, 4 Feb 2015 21:56:53 -0600 Subject: cmd_fdt: Actually fix fdt command in sandbox Commit 90bac29a76bc8d649b41a55f2786c0abef9bb2c1 claims to fix this bug that was introduced in commit a92fd6577ea17751ead9b50243e3c562125cf581 but doesn't actually make the change that the commit message describes. Actually fix the bug this time. Signed-off-by: Joe Hershberger Acked-by: Simon Glass --- common/bootm.c | 2 +- common/cmd_fdt.c | 8 ++++---- common/image-fdt.c | 2 +- include/fdt_support.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/common/bootm.c b/common/bootm.c index e2dc16486b3..34f60bbb531 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -233,7 +233,7 @@ static int bootm_find_fdt(int flag, int argc, char * const argv[]) return 1; } - set_working_fdt_addr(images.ft_addr); + set_working_fdt_addr((ulong)images.ft_addr); return 0; } diff --git a/common/cmd_fdt.c b/common/cmd_fdt.c index dc59fab8280..58784965750 100644 --- a/common/cmd_fdt.c +++ b/common/cmd_fdt.c @@ -38,13 +38,13 @@ static int is_printable_string(const void *data, int len); */ struct fdt_header *working_fdt; -void set_working_fdt_addr(void *addr) +void set_working_fdt_addr(ulong addr) { void *buf; - buf = map_sysmem((ulong)addr, 0); + buf = map_sysmem(addr, 0); working_fdt = buf; - setenv_addr("fdtaddr", addr); + setenv_ulong("fdtaddr", addr); } /* @@ -123,7 +123,7 @@ static int do_fdt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (control) gd->fdt_blob = blob; else - set_working_fdt_addr((void *)blob); + set_working_fdt_addr(addr); if (argc >= 2) { int len; diff --git a/common/image-fdt.c b/common/image-fdt.c index e3f06cdd1a2..d9e47283c71 100644 --- a/common/image-fdt.c +++ b/common/image-fdt.c @@ -190,7 +190,7 @@ int boot_relocate_fdt(struct lmb *lmb, char **of_flat_tree, ulong *of_size) *of_flat_tree = of_start; *of_size = of_len; - set_working_fdt_addr(*of_flat_tree); + set_working_fdt_addr((ulong)*of_flat_tree); return 0; error: diff --git a/include/fdt_support.h b/include/fdt_support.h index 1f19fe4c962..ae5e8a3ef63 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -100,7 +100,7 @@ void ft_pci_setup(void *blob, bd_t *bd); */ int ft_system_setup(void *blob, bd_t *bd); -void set_working_fdt_addr(void *addr); +void set_working_fdt_addr(ulong addr); int fdt_shrink_to_minimum(void *blob); int fdt_increase_size(void *fdt, int add_len); -- cgit v1.3.1 From 6fb9ac15ebac4bcc4864be7958bf9b2b2b7420de Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 13 Feb 2015 12:20:47 -0700 Subject: dm: cros_ec: Convert to Kconfig Since both I2C and SPI are converted to Kconfig, we can convert cros_ec to Kconfig for these buses. LPC will need to wait until driver mode PCI is available. Signed-off-by: Simon Glass --- configs/peach-pi_defconfig | 4 ++++ configs/peach-pit_defconfig | 4 ++++ configs/sandbox_defconfig | 5 ++++ configs/snow_defconfig | 5 ++++ drivers/input/Kconfig | 6 +++++ drivers/misc/Kconfig | 48 ++++++++++++++++++++++++++++++++++++- include/configs/exynos5-dt-common.h | 3 --- include/configs/peach-pi.h | 1 - include/configs/peach-pit.h | 1 - include/configs/sandbox.h | 4 ---- include/configs/snow.h | 2 -- 11 files changed, 71 insertions(+), 12 deletions(-) (limited to 'include') diff --git a/configs/peach-pi_defconfig b/configs/peach-pi_defconfig index 8ada0dbe40c..333e335a26b 100644 --- a/configs/peach-pi_defconfig +++ b/configs/peach-pi_defconfig @@ -3,3 +3,7 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_PEACH_PI=y CONFIG_DEFAULT_DEVICE_TREE="exynos5800-peach-pi" +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/peach-pit_defconfig b/configs/peach-pit_defconfig index b944b3bb502..cf84444950a 100644 --- a/configs/peach-pit_defconfig +++ b/configs/peach-pit_defconfig @@ -3,3 +3,7 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_PEACH_PIT=y CONFIG_DEFAULT_DEVICE_TREE="exynos5420-peach-pit" +CONFIG_CROS_EC=y +CONFIG_CROS_EC_SPI=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig index 0bf5ea34d0c..70f5b86b858 100644 --- a/configs/sandbox_defconfig +++ b/configs/sandbox_defconfig @@ -7,3 +7,8 @@ CONFIG_DM=y CONFIG_DEFAULT_DEVICE_TREE="sandbox" CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_CROS_EC=y +CONFIG_DM_CROS_EC=y +CONFIG_CROS_EC_SANDBOX=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/configs/snow_defconfig b/configs/snow_defconfig index 14ed793f6d7..353ddb03a08 100644 --- a/configs/snow_defconfig +++ b/configs/snow_defconfig @@ -3,3 +3,8 @@ CONFIG_SPL=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_SNOW=y CONFIG_DEFAULT_DEVICE_TREE="exynos5250-snow" +CONFIG_CROS_EC=y +CONFIG_DM_CROS_EC=y +CONFIG_CROS_EC_I2C=y +CONFIG_CROS_EC_KEYB=y +CONFIG_CMD_CROS_EC=y diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index e69de29bb2d..bb00de7c576 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -0,0 +1,6 @@ +config CROS_EC_KEYB + bool "Enable Chrome OS EC keyboard support" + help + Most ARM Chromebooks use an EC to provide access to the keyboard. + Messages are used to request key scans from the EC and these are + then decoded into keys by this driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 813d1c24b97..0df25c331ff 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -1,3 +1,49 @@ +config CMD_CROS_EC + bool "Enable crosec command" + depends on CROS_EC + help + Enable command-line access to the Chrome OS EC (Embedded + Controller). This provides the 'crosec' command which has + a number of sub-commands for performing EC tasks such as + updating its flash, accessing a small saved context area + and talking to the I2C bus behind the EC (if there is one). + +config CROS_EC + bool "Enable Chrome OS EC" + help + Enable access to the Chrome OS EC. This is a separate + microcontroller typically available on a SPI bus on Chromebooks. It + provides access to the keyboard, some internal storage and may + control access to the battery and main PMIC depending on the + device. You can use the 'crosec' command to access it. + +config CROS_EC_I2C + bool "Enable Chrome OS EC I2C driver" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on older + ARM Chromebooks such as snow and spring before the standard bus + changed to SPI. The EC will accept commands across the I2C using + a special message protocol, and provide responses. + +config CROS_EC_LPC + bool "Enable Chrome OS EC LPC driver" + depends on CROS_EC + help + Enable I2C access to the Chrome OS EC. This is used on x86 + Chromebooks such as link and falco. The keyboard is provided + through a legacy port interface, so on x86 machines the main + function of the EC is power and thermal management. + +config CROS_EC_SPI + bool "Enable Chrome OS EC SPI driver" + depends on CROS_EC + help + Enable SPI access to the Chrome OS EC. This is used on newer + ARM Chromebooks such as pit, pi and nyan-big. The SPI interface + provides a faster and more robust interface than I2C but the bugs + are less interesting. + config DM_CROS_EC bool "Enable Driver Model for Chrome OS EC" depends on DM @@ -5,5 +51,5 @@ config DM_CROS_EC Enable driver model for the Chrome OS EC interface. This allows the cros_ec SPI driver to operate with CONFIG_DM_SPI but otherwise makes few changes. Since cros_ec also supports - I2C and LPC (which don't support driver model yet), a full + LPC (which doesn't support driver model yet), a full conversion is not yet possible. diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h index 9cef0b0a38f..b1b8e1ace70 100644 --- a/include/configs/exynos5-dt-common.h +++ b/include/configs/exynos5-dt-common.h @@ -24,9 +24,6 @@ #define CONFIG_POWER_TPS65090 /* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC #define CONFIG_KEYBOARD #endif diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h index f724164d898..f04f0613aac 100644 --- a/include/configs/peach-pi.h +++ b/include/configs/peach-pi.h @@ -43,7 +43,6 @@ #endif #define CONFIG_POWER_TPS65090_EC -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index de12a9e1b18..b5efbdcaa66 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -43,7 +43,6 @@ #endif #define CONFIG_POWER_TPS65090_EC -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ #define CONFIG_USB_XHCI #define CONFIG_USB_XHCI_EXYNOS diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h index 5c116508d0d..febbfb69f6b 100644 --- a/include/configs/sandbox.h +++ b/include/configs/sandbox.h @@ -141,9 +141,6 @@ #define CONFIG_BOOTARGS "" -#define CONFIG_CROS_EC -#define CONFIG_CMD_CROS_EC -#define CONFIG_CROS_EC_SANDBOX #define CONFIG_ARCH_EARLY_INIT_R #define CONFIG_BOARD_LATE_INIT @@ -166,7 +163,6 @@ #define LCD_BPP LCD_COLOR16 #define CONFIG_LCD_BMP_RLE8 -#define CONFIG_CROS_EC_KEYB #define CONFIG_KEYBOARD #define CONFIG_EXTRA_ENV_SETTINGS "stdin=serial,cros-ec-keyb\0" \ diff --git a/include/configs/snow.h b/include/configs/snow.h index ce6676eae7f..fe802f253c9 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -20,9 +20,7 @@ #include -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ #define CONFIG_POWER_TPS65090_I2C -#define CONFIG_DM_CROS_EC #define CONFIG_BOARD_COMMON #define CONFIG_ARCH_EARLY_INIT_R -- cgit v1.3.1 From 4bba9d3f77061ea742d8f697ce72251fb79c8016 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 13 Feb 2015 12:20:48 -0700 Subject: dm: Move CONFIG_I2C_COMPAT to Kconfig Make this option available in Kconfig and clean up the board that uses it. Note there is also an entry in exynos5-common.h but this affects multiple boards and should be dropped as part of the Samsung I2C migration to driver model. Signed-off-by: Simon Glass --- configs/odroid_defconfig | 2 ++ drivers/i2c/Kconfig | 9 +++++++++ include/configs/exynos5-common.h | 2 ++ include/configs/odroid.h | 2 -- 4 files changed, 13 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index a8428373acf..816a3fad3c9 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -3,3 +3,5 @@ CONFIG_ARCH_EXYNOS=y CONFIG_TARGET_ODROID=y CONFIG_OF_CONTROL=y CONFIG_DEFAULT_DEVICE_TREE="exynos4412-odroid" +CONFIG_DM_I2C=y +CONFIG_DM_I2C_COMPAT=y diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 2cc776c73f4..692810d057e 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -13,6 +13,15 @@ config DM_I2C enabled together (it is not possible to use driver model for one and not the other). +config DM_I2C_COMPAT + bool "Enable I2C compatibility layer" + depends on DM + help + Enable old-style I2C functions for compatibility with existing code. + This option can be enabled as a temporary measure to avoid needing + to convert all code for a board in a single commit. It should not + be enabled for any board in an official release. + config SYS_I2C_UNIPHIER bool "UniPhier I2C driver" depends on ARCH_UNIPHIER && DM_I2C diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h index 0ba39a23dd0..3ab8d559bfd 100644 --- a/include/configs/exynos5-common.h +++ b/include/configs/exynos5-common.h @@ -126,6 +126,8 @@ #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) /* I2C */ + +/* TODO(sjg@chromium.org): Move these two options to Kconfig */ #define CONFIG_DM_I2C #define CONFIG_DM_I2C_COMPAT #define CONFIG_CMD_I2C diff --git a/include/configs/odroid.h b/include/configs/odroid.h index 9d5dbdce369..8b47537614e 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -177,8 +177,6 @@ /* I2C */ #define CONFIG_CMD_I2C -#define CONFIG_DM_I2C -#define CONFIG_DM_I2C_COMPAT #define CONFIG_SYS_I2C_S3C24X0 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 -- cgit v1.3.1 From f11199f0d0495177fe17e651e99955dc7494ab52 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 13 Feb 2015 12:20:49 -0700 Subject: dm: mx6: Adjust mx6sxsabresd to use Kconfig for DM_THERMAL Use Kconfig instead of board config for DM and DM_THERMAL. Signed-off-by: Simon Glass --- configs/mx6sxsabresd_defconfig | 2 ++ configs/mx6sxsabresd_spl_defconfig | 2 ++ include/configs/mx6sxsabresd.h | 2 -- 3 files changed, 4 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/configs/mx6sxsabresd_defconfig b/configs/mx6sxsabresd_defconfig index 72e0f103ec0..cc823226c1d 100644 --- a/configs/mx6sxsabresd_defconfig +++ b/configs/mx6sxsabresd_defconfig @@ -3,3 +3,5 @@ CONFIG_ARM=y CONFIG_TARGET_MX6SXSABRESD=y CONFIG_SYS_MALLOC_F=y CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/configs/mx6sxsabresd_spl_defconfig b/configs/mx6sxsabresd_spl_defconfig index 6b36e06a85e..901b01bf98e 100644 --- a/configs/mx6sxsabresd_spl_defconfig +++ b/configs/mx6sxsabresd_spl_defconfig @@ -2,3 +2,5 @@ CONFIG_SPL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,MX6SX" +S:CONFIG_ARM=y +S:CONFIG_TARGET_MX6SXSABRESD=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 1005b9e6bc6..a2901294a63 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -227,8 +227,6 @@ #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) #endif -#define CONFIG_DM -#define CONFIG_DM_THERMAL #define CONFIG_IMX6_THERMAL #define CONFIG_CMD_FUSE -- cgit v1.3.1 From 2f964aa7b1bf7de50587a1864cf60d187ebefb2c Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 26 Jan 2015 18:27:07 -0700 Subject: serial: Support an early UART for debugging This came up in a discussion on the mailing list here: https://patchwork.ozlabs.org/patch/384613/ My concerns at the time were: - it doesn't need to be written in assembler - it doesn't need to be ARM-specific This patch provides a possible alternative. It works by allowing any serial driver to export one init function and provide a putc() function. These can be used to output debug data before the real serial driver is available. This implementation does not depend on driver model, and it is possible for it to operate without a stack on some architectures (e.g. PowerPC, ARM). It provides the same features as the ARM-specific debug.S but with more UART and architecture support. Signed-off-by: Simon Glass --- configs/minnowmax_defconfig | 2 - drivers/serial/Kconfig | 46 +++++++++++++++ include/debug_uart.h | 139 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 185 insertions(+), 2 deletions(-) create mode 100644 include/debug_uart.h (limited to 'include') diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index 7bc9085b325..d12428996d2 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -7,7 +7,5 @@ CONFIG_DEFAULT_DEVICE_TREE="minnowmax" CONFIG_VIDEO_X86=y CONFIG_FRAMEBUFFER_SET_VESA_MODE=y CONFIG_FRAMEBUFFER_VESA_MODE_11A=y -CONFIG_DEBUG_UART_NS16550=y -CONFIG_DEBUG_UART=y CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_HAVE_INTEL_ME=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c94353ba6ac..6313258eac6 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -7,6 +7,52 @@ config DM_SERIAL implements serial_putc() etc. The uclass interface is defined in include/serial.h. +config DEBUG_UART + bool "Enable an early debug UART for debugging" + help + The debug UART is intended for use very early in U-Boot to debug + problems when an ICE or other debug mechanism is not available. + + To use it you should: + - Make sure your UART supports this interface + - Enable CONFIG_DEBUG_UART + - Enable the CONFIG for your UART to tell it to provide this interface + (e.g. CONFIG_DEBUG_UART_NS16550) + - Define the required settings as needed (see below) + - Call debug_uart_init() before use + - Call debug_uart_putc() to output a character + + Depending on your platform it may be possible to use this UART before + a stack is available. + + If your UART does not support this interface you can probably add + support quite easily. Remember that you cannot use driver model and + it is preferred to use no stack. + + You must not use this UART once driver model is working and the + serial drivers are up and running (done in serial_init()). Otherwise + the drivers may conflict and you will get strange output. + +config DEBUG_UART_BASE + hex "Base address of UART" + depends on DEBUG_UART + help + This is the base address of your UART for memory-mapped UARTs. + + A default should be provided by your board, but if not you will need + to use the correct value here. + +config DEBUG_UART_CLOCK + int "UART input clock" + depends on DEBUG_UART + help + The UART input clock determines the speed of the internal UART + circuitry. The baud rate is derived from this by dividing the input + clock down. + + A default should be provided by your board, but if not you will need + to use the correct value here. + config UNIPHIER_SERIAL bool "UniPhier on-chip UART support" depends on ARCH_UNIPHIER && DM_SERIAL diff --git a/include/debug_uart.h b/include/debug_uart.h new file mode 100644 index 00000000000..f56797b72f4 --- /dev/null +++ b/include/debug_uart.h @@ -0,0 +1,139 @@ +/* + * Early debug UART support + * + * (C) Copyright 2014 Google, Inc + * Writte by Simon Glass + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DEBUG_UART_H +#define _DEBUG_UART_H + +#include + +/* + * The debug UART is intended for use very early in U-Boot to debug problems + * when an ICE or other debug mechanism is not available. + * + * To use it you should: + * - Make sure your UART supports this interface + * - Enable CONFIG_DEBUG_UART + * - Enable the CONFIG for your UART to tell it to provide this interface + * (e.g. CONFIG_DEBUG_UART_NS16550) + * - Define the required settings as needed (see below) + * - Call debug_uart_init() before use + * - Call printch() to output a character + * + * Depending on your platform it may be possible to use this UART before a + * stack is available. + * + * If your UART does not support this interface you can probably add support + * quite easily. Remember that you cannot use driver model and it is preferred + * to use no stack. + * + * You must not use this UART once driver model is working and the serial + * drivers are up and running (done in serial_init()). Otherwise the drivers + * may conflict and you will get strange output. + * + * + * To enable the debug UART in your serial driver: + * + * - #include + * - Define debug_uart_init(), trying to avoid using the stack + * - Define _debug_uart_putc() as static inline (avoiding stack usage) + * - Immediately afterwards, add DEBUG_UART_FUNCS to define the rest of the + * functionality (printch(), etc.) + */ + +/** + * debug_uart_init() - Set up the debug UART ready for use + * + * This sets up the UART with the correct baud rate, etc. + * + * Available CONFIG is: + * + * - CONFIG_DEBUG_UART_BASE: Base address of UART + * - CONFIG_BAUDRATE: Requested baud rate + * - CONFIG_DEBUG_UART_CLOCK: Input clock for UART + */ +void debug_uart_init(void); + +/** + * printch() - Output a character to the debug UART + * + * @ch: Character to output + */ +asmlinkage void printch(int ch); + +/** + * printascii() - Output an ASCII string to the debug UART + * + * @str: String to output + */ +asmlinkage void printascii(const char *str); + +/** + * printhex2() - Output a 2-digit hex value + * + * @value: Value to output + */ +asmlinkage void printhex2(uint value); + +/** + * printhex4() - Output a 4-digit hex value + * + * @value: Value to output + */ +asmlinkage void printhex4(uint value); + +/** + * printhex8() - Output a 8-digit hex value + * + * @value: Value to output + */ +asmlinkage void printhex8(uint value); + +/* + * Now define some functions - this should be inserted into the serial driver + */ +#define DEBUG_UART_FUNCS \ + asmlinkage void printch(int ch) \ + { \ + _debug_uart_putc(ch); \ + } \ +\ + asmlinkage void printascii(const char *str) \ + { \ + while (*str) \ + _debug_uart_putc(*str++); \ + } \ +\ + static inline void printhex1(uint digit) \ + { \ + digit &= 0xf; \ + _debug_uart_putc(digit > 9 ? digit - 10 + 'a' : digit + '0'); \ + } \ +\ + static inline void printhex(uint value, int digits) \ + { \ + while (digits-- > 0) \ + printhex1(value >> (4 * digits)); \ + } \ +\ + asmlinkage void printhex2(uint value) \ + { \ + printhex(value, 2); \ + } \ +\ + asmlinkage void printhex4(uint value) \ + { \ + printhex(value, 4); \ + } \ +\ + asmlinkage void printhex8(uint value) \ + { \ + printhex(value, 8); \ + } + +#endif -- cgit v1.3.1 From 66c03151fc8752c29b7d17003b9c87218640b10b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 18 Feb 2015 22:36:18 +0100 Subject: dm: Protect device_unbind() with CONFIG_DM_DEVICE_REMOVE Since device_unbind() is also defined in device-remove.c, which is compiled in only in case CONFIG_DM_DEVICE_REMOVE is defined, protect the device_unbind() prototype with the same CONFIG_DM_DEVICE_REMOVE check. Signed-off-by: Marek Vasut Cc: Simon Glass Cc: Stefan Roese Cc: Tom Rini Acked-by: Simon Glass --- include/dm/device-internal.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/dm/device-internal.h b/include/dm/device-internal.h index f0cc7947505..e2418fedb97 100644 --- a/include/dm/device-internal.h +++ b/include/dm/device-internal.h @@ -101,7 +101,11 @@ static inline int device_remove(struct udevice *dev) { return 0; } * @dev: Pointer to device to unbind * @return 0 if OK, -ve on error */ +#ifdef CONFIG_DM_DEVICE_REMOVE int device_unbind(struct udevice *dev); +#else +static inline int device_unbind(struct udevice *dev) { return 0; } +#endif #ifdef CONFIG_DM_DEVICE_REMOVE void device_free(struct udevice *dev); -- cgit v1.3.1 From 55410089cb979d7a86ee817c0309c4c2348a90df Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 16 Feb 2015 17:23:25 +0100 Subject: sunxi: video: Add support for LCD panels which need to be configured via i2c This commits adds support for configuring a a bitbang i2c controller, which is used on some boards to configure the LCD panel (via i2c). Signed-off-by: Hans de Goede Acked-by: Ian Campbell --- board/sunxi/Kconfig | 24 ++++++++++++++++++++++++ board/sunxi/board.c | 10 ++++++++++ include/configs/sunxi-common.h | 16 ++++++++++++++++ 3 files changed, 50 insertions(+) (limited to 'include') diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index a170c561aab..bbb4d1b1e5f 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -344,6 +344,30 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW ---help--- Set this if the backlight pwm output is active low. +config VIDEO_LCD_PANEL_I2C + bool "LCD panel needs to be configured via i2c" + depends on VIDEO + default m + ---help--- + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. + +config VIDEO_LCD_PANEL_I2C_SDA + string "LCD panel i2c interface SDA pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG12" + ---help--- + Set the SDA pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_PANEL_I2C_SCL + string "LCD panel i2c interface SCL pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG10" + ---help--- + Set the SCL pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b70e00ce6bc..e1891d198e4 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -33,6 +33,12 @@ #include #include +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ +int soft_i2c_gpio_sda; +int soft_i2c_gpio_scl; +#endif + DECLARE_GLOBAL_DATA_PTR; /* add board specific code here */ @@ -152,6 +158,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); clock_twi_onoff(0, 1); +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) + soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); + soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); +#endif } #ifdef CONFIG_SPL_BUILD diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1238d821b36..f5efebbf282 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -183,6 +183,22 @@ #define CONFIG_SYS_I2C_MVTWSI #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x7f + +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +#define CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C_SOFT_SPEED 50000 +#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 +#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ +#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ +/* We use pin names in Kconfig and sunxi_name_to_gpio() */ +#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda +#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl +#ifndef __ASSEMBLY__ +extern int soft_i2c_gpio_sda; +extern int soft_i2c_gpio_scl; +#endif +#endif + #define CONFIG_CMD_I2C /* PMU */ -- cgit v1.3.1 From 620118403e1521b4c883848a84d2fb68e3fa1aa0 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Feb 2015 17:04:03 +0900 Subject: ARM: at91: collect SoC sources into mach-at91 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit moves source files as follows: arch/arm/cpu/arm920t/at91/* -> arch/arm/mach-at91/arm920t/* arch/arm/cpu/arm926ejs/at91/* -> arch/arm/mach-at91/arm926ejs/* arch/arm/cpu/armv7/at91/* -> arch/arm/mach-at91/armv7/* arch/arm/cpu/at91-common/* -> arch/arm/mach-at91/* Signed-off-by: Masahiro Yamada Acked-by: Andreas Bießmann --- MAINTAINERS | 3 +- arch/arm/Makefile | 1 + arch/arm/cpu/Makefile | 1 - arch/arm/cpu/arm920t/Makefile | 1 - arch/arm/cpu/arm920t/at91/Makefile | 13 -- arch/arm/cpu/arm920t/at91/at91rm9200_devices.c | 67 ------ arch/arm/cpu/arm920t/at91/clock.c | 157 ------------- arch/arm/cpu/arm920t/at91/cpu.c | 26 --- arch/arm/cpu/arm920t/at91/lowlevel_init.S | 152 ------------ arch/arm/cpu/arm920t/at91/reset.c | 41 ---- arch/arm/cpu/arm920t/at91/timer.c | 127 ----------- arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/at91/Makefile | 28 --- arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c | 245 -------------------- arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c | 140 ------------ arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c | 218 ------------------ .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 184 --------------- arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c | 161 ------------- arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 103 --------- arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c | 244 -------------------- arch/arm/cpu/arm926ejs/at91/clock.c | 249 -------------------- arch/arm/cpu/arm926ejs/at91/config.mk | 2 - arch/arm/cpu/arm926ejs/at91/cpu.c | 57 ----- arch/arm/cpu/arm926ejs/at91/eflash.c | 254 --------------------- arch/arm/cpu/arm926ejs/at91/led.c | 48 ---- arch/arm/cpu/arm926ejs/at91/lowlevel_init.S | 246 -------------------- arch/arm/cpu/arm926ejs/at91/reset.c | 29 --- arch/arm/cpu/arm926ejs/at91/timer.c | 120 ---------- arch/arm/cpu/armv7/Makefile | 1 - arch/arm/cpu/armv7/at91/Makefile | 16 -- arch/arm/cpu/armv7/at91/clock.c | 175 -------------- arch/arm/cpu/armv7/at91/config.mk | 8 - arch/arm/cpu/armv7/at91/cpu.c | 76 ------ arch/arm/cpu/armv7/at91/reset.c | 31 --- arch/arm/cpu/armv7/at91/sama5d3_devices.c | 218 ------------------ arch/arm/cpu/armv7/at91/sama5d4_devices.c | 93 -------- arch/arm/cpu/armv7/at91/timer.c | 124 ---------- arch/arm/cpu/at91-common/Makefile | 18 -- arch/arm/cpu/at91-common/mpddrc.c | 133 ----------- arch/arm/cpu/at91-common/phy.c | 57 ----- arch/arm/cpu/at91-common/sdram.c | 77 ------- arch/arm/cpu/at91-common/spl.c | 50 ---- arch/arm/cpu/at91-common/spl_at91.c | 124 ---------- arch/arm/cpu/at91-common/spl_atmel.c | 96 -------- arch/arm/cpu/at91-common/u-boot-spl.lds | 55 ----- arch/arm/mach-at91/Makefile | 12 + arch/arm/mach-at91/arm920t/Makefile | 13 ++ arch/arm/mach-at91/arm920t/at91rm9200_devices.c | 67 ++++++ arch/arm/mach-at91/arm920t/clock.c | 157 +++++++++++++ arch/arm/mach-at91/arm920t/cpu.c | 26 +++ arch/arm/mach-at91/arm920t/lowlevel_init.S | 152 ++++++++++++ arch/arm/mach-at91/arm920t/reset.c | 41 ++++ arch/arm/mach-at91/arm920t/timer.c | 127 +++++++++++ arch/arm/mach-at91/arm926ejs/Makefile | 28 +++ arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c | 245 ++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c | 140 ++++++++++++ arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c | 218 ++++++++++++++++++ .../mach-at91/arm926ejs/at91sam9m10g45_devices.c | 184 +++++++++++++++ arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c | 161 +++++++++++++ arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c | 103 +++++++++ arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c | 244 ++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/clock.c | 249 ++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/cpu.c | 57 +++++ arch/arm/mach-at91/arm926ejs/eflash.c | 254 +++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/led.c | 48 ++++ arch/arm/mach-at91/arm926ejs/lowlevel_init.S | 246 ++++++++++++++++++++ arch/arm/mach-at91/arm926ejs/reset.c | 29 +++ arch/arm/mach-at91/arm926ejs/timer.c | 120 ++++++++++ arch/arm/mach-at91/armv7/Makefile | 16 ++ arch/arm/mach-at91/armv7/clock.c | 175 ++++++++++++++ arch/arm/mach-at91/armv7/cpu.c | 76 ++++++ arch/arm/mach-at91/armv7/reset.c | 31 +++ arch/arm/mach-at91/armv7/sama5d3_devices.c | 218 ++++++++++++++++++ arch/arm/mach-at91/armv7/sama5d4_devices.c | 93 ++++++++ arch/arm/mach-at91/armv7/timer.c | 124 ++++++++++ arch/arm/mach-at91/config.mk | 9 + arch/arm/mach-at91/mpddrc.c | 133 +++++++++++ arch/arm/mach-at91/phy.c | 57 +++++ arch/arm/mach-at91/sdram.c | 77 +++++++ arch/arm/mach-at91/spl.c | 50 ++++ arch/arm/mach-at91/spl_at91.c | 124 ++++++++++ arch/arm/mach-at91/spl_atmel.c | 96 ++++++++ arch/arm/mach-at91/u-boot-spl.lds | 55 +++++ include/configs/sama5d3_xplained.h | 2 +- include/configs/sama5d3xek.h | 2 +- 85 files changed, 4259 insertions(+), 4270 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/at91/Makefile delete mode 100644 arch/arm/cpu/arm920t/at91/at91rm9200_devices.c delete mode 100644 arch/arm/cpu/arm920t/at91/clock.c delete mode 100644 arch/arm/cpu/arm920t/at91/cpu.c delete mode 100644 arch/arm/cpu/arm920t/at91/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm920t/at91/reset.c delete mode 100644 arch/arm/cpu/arm920t/at91/timer.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/clock.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/config.mk delete mode 100644 arch/arm/cpu/arm926ejs/at91/cpu.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/eflash.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/led.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm926ejs/at91/reset.c delete mode 100644 arch/arm/cpu/arm926ejs/at91/timer.c delete mode 100644 arch/arm/cpu/armv7/at91/Makefile delete mode 100644 arch/arm/cpu/armv7/at91/clock.c delete mode 100644 arch/arm/cpu/armv7/at91/config.mk delete mode 100644 arch/arm/cpu/armv7/at91/cpu.c delete mode 100644 arch/arm/cpu/armv7/at91/reset.c delete mode 100644 arch/arm/cpu/armv7/at91/sama5d3_devices.c delete mode 100644 arch/arm/cpu/armv7/at91/sama5d4_devices.c delete mode 100644 arch/arm/cpu/armv7/at91/timer.c delete mode 100644 arch/arm/cpu/at91-common/Makefile delete mode 100644 arch/arm/cpu/at91-common/mpddrc.c delete mode 100644 arch/arm/cpu/at91-common/phy.c delete mode 100644 arch/arm/cpu/at91-common/sdram.c delete mode 100644 arch/arm/cpu/at91-common/spl.c delete mode 100644 arch/arm/cpu/at91-common/spl_at91.c delete mode 100644 arch/arm/cpu/at91-common/spl_atmel.c delete mode 100644 arch/arm/cpu/at91-common/u-boot-spl.lds create mode 100644 arch/arm/mach-at91/Makefile create mode 100644 arch/arm/mach-at91/arm920t/Makefile create mode 100644 arch/arm/mach-at91/arm920t/at91rm9200_devices.c create mode 100644 arch/arm/mach-at91/arm920t/clock.c create mode 100644 arch/arm/mach-at91/arm920t/cpu.c create mode 100644 arch/arm/mach-at91/arm920t/lowlevel_init.S create mode 100644 arch/arm/mach-at91/arm920t/reset.c create mode 100644 arch/arm/mach-at91/arm920t/timer.c create mode 100644 arch/arm/mach-at91/arm926ejs/Makefile create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c create mode 100644 arch/arm/mach-at91/arm926ejs/clock.c create mode 100644 arch/arm/mach-at91/arm926ejs/cpu.c create mode 100644 arch/arm/mach-at91/arm926ejs/eflash.c create mode 100644 arch/arm/mach-at91/arm926ejs/led.c create mode 100644 arch/arm/mach-at91/arm926ejs/lowlevel_init.S create mode 100644 arch/arm/mach-at91/arm926ejs/reset.c create mode 100644 arch/arm/mach-at91/arm926ejs/timer.c create mode 100644 arch/arm/mach-at91/armv7/Makefile create mode 100644 arch/arm/mach-at91/armv7/clock.c create mode 100644 arch/arm/mach-at91/armv7/cpu.c create mode 100644 arch/arm/mach-at91/armv7/reset.c create mode 100644 arch/arm/mach-at91/armv7/sama5d3_devices.c create mode 100644 arch/arm/mach-at91/armv7/sama5d4_devices.c create mode 100644 arch/arm/mach-at91/armv7/timer.c create mode 100644 arch/arm/mach-at91/config.mk create mode 100644 arch/arm/mach-at91/mpddrc.c create mode 100644 arch/arm/mach-at91/phy.c create mode 100644 arch/arm/mach-at91/sdram.c create mode 100644 arch/arm/mach-at91/spl.c create mode 100644 arch/arm/mach-at91/spl_at91.c create mode 100644 arch/arm/mach-at91/spl_atmel.c create mode 100644 arch/arm/mach-at91/u-boot-spl.lds (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 74a56ecf4ff..a558bd4fcb4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -76,8 +76,7 @@ ARM ATMEL AT91 M: Andreas Bießmann S: Maintained T: git git://git.denx.de/u-boot-atmel.git -F: arch/arm/cpu/armv7/at91/ -F: arch/arm/cpu/at91-common/ +F: arch/arm/mach-at91/ F: arch/arm/include/asm/arch-at91/ ARM FREESCALE IMX diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5da2c231e97..f4e9af65988 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -4,6 +4,7 @@ # Machine directory name. This list is sorted alphanumerically # by CONFIG_* macro name. +machine-$(CONFIG_ARCH_AT91) += at91 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y)) diff --git a/arch/arm/cpu/Makefile b/arch/arm/cpu/Makefile index 35d8d387bd0..ba4f3900f70 100644 --- a/arch/arm/cpu/Makefile +++ b/arch/arm/cpu/Makefile @@ -1,4 +1,3 @@ -obj-$(CONFIG_AT91FAMILY) += at91-common/ obj-$(CONFIG_TEGRA20) += tegra20-common/ obj-$(CONFIG_TEGRA30) += tegra30-common/ obj-$(CONFIG_TEGRA114) += tegra114-common/ diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a72e5de99eb..a16838b4797 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -11,7 +11,6 @@ obj-y += cpu.o obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(if $(filter a320,$(SOC)),y) += a320/ -obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ obj-$(CONFIG_KS8695) += ks8695/ diff --git a/arch/arm/cpu/arm920t/at91/Makefile b/arch/arm/cpu/arm920t/at91/Makefile deleted file mode 100644 index 561b4b4cbb7..00000000000 --- a/arch/arm/cpu/arm920t/at91/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += lowlevel_init.o -obj-y += reset.o -obj-y += timer.o -obj-y += clock.o -obj-y += cpu.o -obj-y += at91rm9200_devices.o diff --git a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c b/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c deleted file mode 100644 index fc54327c0d3..00000000000 --- a/arch/arm/cpu/arm920t/at91/at91rm9200_devices.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c] - * - * (C) Copyright 2011 - * Andreas Bießmann - * - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */ - /* writing SYS to PCER has no effect on AT91RM9200 */ -} diff --git a/arch/arm/cpu/arm920t/at91/clock.c b/arch/arm/cpu/arm920t/at91/clock.c deleted file mode 100644 index 2813bf78216..00000000000 --- a/arch/arm/cpu/arm920t/at91/clock.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] - * - * Copyright (C) 2011 Andreas Bießmann - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include -#include -#include - -#if !defined(CONFIG_AT91FAMILY) -# error You need to define CONFIG_AT91FAMILY in your board config! -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static unsigned long at91_css_to_rate(unsigned long css) -{ - switch (css) { - case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; - case AT91_PMC_MCKR_CSS_MAIN: - return gd->arch.main_clk_rate_hz; - case AT91_PMC_MCKR_CSS_PLLA: - return gd->arch.plla_rate_hz; - case AT91_PMC_MCKR_CSS_PLLB: - return gd->arch.pllb_rate_hz; - } - - return 0; -} - -#ifdef CONFIG_USB_ATMEL -static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) -{ - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; -fail: - return 0; -} -#endif - -static u32 at91_pll_rate(u32 freq, u32 reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; - - return freq; -} - -int at91_clock_init(unsigned long main_clock) -{ - unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK - unsigned tmp; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(&pmc->mcfr); - } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); - tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); - } -#endif - gd->arch.main_clk_rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); - -#ifdef CONFIG_USB_ATMEL - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_PLLBR_USBDIV_2; - gd->arch.pllb_rate_hz = at91_pll_rate(main_clock, - gd->arch.at91_pllb_usb_init); -#endif - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(&pmc->mckr); - gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); - freq = gd->arch.mck_rate_hz; - - freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ - /* mdiv */ - gd->arch.mck_rate_hz = freq / - (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); - gd->arch.cpu_clk_rate_hz = freq; - - return 0; -} diff --git a/arch/arm/cpu/arm920t/at91/cpu.c b/arch/arm/cpu/arm920t/at91/cpu.c deleted file mode 100644 index b0f411b1c36..00000000000 --- a/arch/arm/cpu/arm920t/at91/cpu.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c] - * - * (C) Copyright 2011 - * Andreas Bießmann, andreas.devel@googlemail.com - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * (C) Copyright 2009 - * Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 -#endif - -int arch_cpu_init(void) -{ - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); -} diff --git a/arch/arm/cpu/arm920t/at91/lowlevel_init.S b/arch/arm/cpu/arm920t/at91/lowlevel_init.S deleted file mode 100644 index d2934a3525a..00000000000 --- a/arch/arm/cpu/arm920t/at91/lowlevel_init.S +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Modified for the at91rm9200dk board by - * (C) Copyright 2004 - * Gary Jennejohn, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -#include -#include -#include -#include - -#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ - -_MTEXT_BASE: -#undef START_FROM_MEM -#ifdef START_FROM_MEM - .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1 -#else - .word CONFIG_SYS_TEXT_BASE -#endif - -.globl lowlevel_init -lowlevel_init: - ldr r1, =AT91_ASM_PMC_MOR - /* Main oscillator Enable register */ -#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR - ldr r0, =0x0000FF01 /* Enable main oscillator */ -#else - ldr r0, =0x0000FF00 /* Disable main oscillator */ -#endif - str r0, [r1] /*AT91C_CKGR_MOR] */ - /* Add loop to compensate Main Oscillator startup time */ - ldr r0, =0x00000010 -LoopOsc: - subs r0, r0, #1 - bhi LoopOsc - - /* memory control configuration */ - /* this isn't very elegant, but what the heck */ - ldr r0, =SMRDATA - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - ldr r2, =SMRDATAE - sub r2, r2, r1 -pllloop: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne pllloop - /* delay - this is all done by guess */ - ldr r0, =0x00010000 - /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ -lock: - subs r0, r0, #1 - bhi lock - ldr r0, =SMRDATA1 - ldr r1, _MTEXT_BASE - sub r0, r0, r1 - ldr r2, =SMRDATA1E - sub r2, r2, r1 -sdinit: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne sdinit - - /* switch from FastBus to Asynchronous clock mode */ - mrc p15, 0, r0, c1, c0, 0 - orr r0, r0, #ARM920T_CONTROL - mcr p15, 0, r0, c1, c0, 0 - - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word AT91_ASM_MC_EBI_CFG - .word CONFIG_SYS_EBI_CFGR_VAL - .word AT91_ASM_MC_SMC_CSR0 - .word CONFIG_SYS_SMC_CSR0_VAL - .word AT91_ASM_PMC_PLLAR - .word CONFIG_SYS_PLLAR_VAL - .word AT91_ASM_PMC_PLLBR - .word CONFIG_SYS_PLLBR_VAL - .word AT91_ASM_PMC_MCKR - .word CONFIG_SYS_MCKR_VAL -SMRDATAE: - /* here there's a delay */ -SMRDATA1: - .word AT91_ASM_PIOC_ASR - .word CONFIG_SYS_PIOC_ASR_VAL - .word AT91_ASM_PIOC_BSR - .word CONFIG_SYS_PIOC_BSR_VAL - .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL - .word AT91_ASM_MC_EBI_CSA - .word CONFIG_SYS_EBI_CSA_VAL - .word AT91_ASM_MC_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL - .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL - .word AT91_ASM_MC_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word AT91_ASM_MC_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL -SMRDATA1E: - /* SMRDATA1 is 176 bytes long */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/at91/reset.c b/arch/arm/cpu/arm920t/at91/reset.c deleted file mode 100644 index d47777a3678..00000000000 --- a/arch/arm/cpu/arm920t/at91/reset.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -void __attribute__((weak)) board_reset(void) -{ - /* true empty function for defining weak symbol */ -} - -void reset_cpu(ulong ignored) -{ - at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST; - - board_reset(); - - /* Reset the cpu by setting up the watchdog timer */ - writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2), - &st->wdmr); - writel(AT91_ST_CR_WDRST, &st->cr); - /* and let it timeout */ - while (1) - ; - /* Never reached */ -} diff --git a/arch/arm/cpu/arm920t/at91/timer.c b/arch/arm/cpu/arm920t/at91/timer.c deleted file mode 100644 index 6aa29947231..00000000000 --- a/arch/arm/cpu/arm920t/at91/timer.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * (C) Copyright 2002 - * Lineo, Inc. - * Bernhard Kuhn - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Alex Zuepke - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* the number of clocks per CONFIG_SYS_HZ */ -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) - -int timer_init(void) -{ - at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - /* enables TC1.0 clock */ - writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */ - - writel(0, &tc->bcr); - writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | - AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr); - - writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); - /* set to MCLK/2 and restart the timer - when the value in TC_RC is reached */ - writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); - - writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */ - writel(TIMER_LOAD_VAL, &tc->tc[0].rc); - - writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); - gd->arch.lastinc = 0; - gd->arch.tbl = 0; - - return 0; -} - -/* - * timer without interrupts - */ -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -void __udelay(unsigned long usec) -{ - udelay_masked(usec); -} - -ulong get_timer_raw(void) -{ - at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; - u32 now; - - now = readl(&tc->tc[0].cv) & 0x0000ffff; - - if (now >= gd->arch.lastinc) { - /* normal mode */ - gd->arch.tbl += now - gd->arch.lastinc; - } else { - /* we have an overflow ... */ - gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc; - } - gd->arch.lastinc = now; - - return gd->arch.tbl; -} - -ulong get_timer_masked(void) -{ - return get_timer_raw()/TIMER_LOAD_VAL; -} - -void udelay_masked(unsigned long usec) -{ - u32 tmo; - u32 endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= 1000; - - endtime = get_timer_raw() + tmo; - - do { - u32 now = get_timer_raw(); - diff = endtime - now; - } while (diff >= 0); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index adcea9f6834..f41357aaeb4 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -15,7 +15,6 @@ endif endif obj-$(CONFIG_ARMADA100) += armada100/ -obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(CONFIG_ARCH_DAVINCI) += davinci/ obj-$(CONFIG_KIRKWOOD) += kirkwood/ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile deleted file mode 100644 index ddc323f6415..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ /dev/null @@ -1,28 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o -obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o -obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o -obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o -obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o -obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o -obj-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o -obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o -obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o -obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o -obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o -obj-$(CONFIG_AT91_EFLASH) += eflash.o -obj-$(CONFIG_AT91_LED) += led.o -obj-y += clock.o -obj-y += cpu.o -obj-y += reset.o -obj-y += timer.o - -ifndef CONFIG_SKIP_LOWLEVEL_INIT -obj-y += lowlevel_init.o -endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c deleted file mode 100644 index efb53d673f4..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9260_devices.c +++ /dev/null @@ -1,245 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTC, 11, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTC, 16, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTC, 17, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTC, 11, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTC, 16, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTC, 17, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTC, 5, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTC, 4, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTC, 3, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTC, 5, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTC, 4, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTC, 3, 1); - } -} -#endif - -#ifdef CONFIG_MACB -void at91_macb_hw_init(void) -{ - /* Enable EMAC clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */ - -#ifndef CONFIG_RMII - at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */ -#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) - /* - * use PA10, PA11 for ETX2, ETX3. - * PA23 and PA24 are for TWI EEPROM - */ - at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */ -#else - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */ -#if defined(CONFIG_AT91SAM9G20) - /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0); - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0); -#endif -#endif - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */ -#endif -} -#endif - -#if defined(CONFIG_GENERIC_ATMEL_MCI) -void at91_mci_hw_init(void) -{ - /* Enable mci clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_MCI, &pmc->pcer); - - at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */ -#if defined(CONFIG_ATMEL_MCI_PORTB) - at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */ - at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */ - at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */ - at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */ - at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */ -#else - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */ -#endif -} -#endif - -void at91_sdram_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); - at91_set_a_periph(AT91_PIO_PORTC, 25, 0); - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); - at91_set_a_periph(AT91_PIO_PORTC, 31, 0); -} - -/* Platform data for the GPIOs */ -static const struct at91_port_platdata at91sam9260_plat[] = { - { ATMEL_BASE_PIOA, "PA" }, - { ATMEL_BASE_PIOB, "PB" }, - { ATMEL_BASE_PIOC, "PC" }, -}; - -U_BOOT_DEVICES(at91sam9260_gpios) = { - { "gpio_at91", &at91sam9260_plat[0] }, - { "gpio_at91", &at91sam9260_plat[1] }, - { "gpio_at91", &at91sam9260_plat[2] }, -}; diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c deleted file mode 100644 index a445c7507e2..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ /dev/null @@ -1,140 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_a_periph(AT91_PIO_PORTA, 4, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTA, 6, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTA, 4, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTA, 5, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTA, 6, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 28, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTA, 24, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTA, 25, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTA, 26, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 28, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTA, 24, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTA, 25, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTA, 26, 1); - } -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c deleted file mode 100644 index 6b51d5f355f..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9263_devices.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2009-2011 - * Daniel Gorsulowski - * esd electronic system design gmbh - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_b_periph(AT91_PIO_PORTA, 5, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTA, 4, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTB, 11, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTA, 5, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTA, 3, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTA, 4, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTB, 11, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 15, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_a_periph(AT91_PIO_PORTB, 16, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTB, 17, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTB, 18, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 15, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTB, 16, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTB, 17, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTB, 18, 1); - } -} -#endif - -#if defined(CONFIG_GENERIC_ATMEL_MCI) -void at91_mci_hw_init(void) -{ - /* Enable mci clock */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_MCI1, &pmc->pcer); - - at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */ - -#if defined(CONFIG_ATMEL_MCI_PORTB) - at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */ - at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */ - at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */ - at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */ - at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */ -#else - at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */ - at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */ -#endif -} -#endif - -#ifdef CONFIG_MACB -void at91_macb_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */ - at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */ - -#ifndef CONFIG_RMII - at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */ -#endif -} -#endif - -#ifdef CONFIG_USB_OHCI_NEW -void at91_uhp_hw_init(void) -{ - /* Enable VBus on UHP ports */ - at91_set_pio_output(AT91_PIO_PORTA, 21, 0); - at91_set_pio_output(AT91_PIO_PORTA, 24, 0); -} -#endif - -#ifdef CONFIG_AT91_CAN -void at91_can_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ - - /* Enable clock */ - writel(1 << ATMEL_ID_CAN, &pmc->pcer); -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c deleted file mode 100644 index 0e6c0da1bdd..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 3, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTB, 18, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_b_periph(AT91_PIO_PORTB, 19, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTD, 27, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 3, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTB, 18, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTB, 19, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 27, 1); - } -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ - at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ - at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTB, 17, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTD, 28, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTD, 18, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_a_periph(AT91_PIO_PORTD, 19, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTB, 17, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTD, 28, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTD, 18, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 19, 1); - } - -} -#endif - -#ifdef CONFIG_MACB -void at91_macb_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */ -#ifndef CONFIG_RMII - at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */ - at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */ - at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */ - at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */ - at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */ - at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */ - at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */ - at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */ -#endif -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -void at91_mci_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ - - /* Enable clock */ - writel(1 << ATMEL_ID_MCI0, &pmc->pcer); -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c deleted file mode 100644 index 39f17a1e11e..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9n12_devices.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * (C) Copyright 2013 Atmel Corporation - * Josh Wu - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -unsigned int has_lcdc() -{ - return 1; -} - -void at91_serial0_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_serial3_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ - at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ - writel(1 << ATMEL_ID_USART3, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#ifdef CONFIG_ATMEL_SPI -void at91_spi0_hw_init(unsigned long cs_mask) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) - at91_set_pio_output(AT91_PIO_PORTA, 14, 1); - if (cs_mask & (1 << 1)) - at91_set_pio_output(AT91_PIO_PORTA, 7, 1); - if (cs_mask & (1 << 2)) - at91_set_pio_output(AT91_PIO_PORTA, 1, 1); - if (cs_mask & (1 << 3)) - at91_set_pio_output(AT91_PIO_PORTB, 3, 1); -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) - at91_set_pio_output(AT91_PIO_PORTA, 8, 1); - if (cs_mask & (1 << 1)) - at91_set_pio_output(AT91_PIO_PORTA, 0, 1); - if (cs_mask & (1 << 2)) - at91_set_pio_output(AT91_PIO_PORTA, 31, 1); - if (cs_mask & (1 << 3)) - at91_set_pio_output(AT91_PIO_PORTA, 30, 1); -} -#endif - -void at91_mci_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ - - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); -} - -#ifdef CONFIG_LCD -void at91_lcd_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ - at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ - at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ - - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ - at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ - at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ - at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ - at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ - at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ - at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ - at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ - at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ - - writel(1 << ATMEL_ID_LCDC, &pmc->pcer); -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c deleted file mode 100644 index 0ec32c3ab9c..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ /dev/null @@ -1,103 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* - * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all - * peripheral pins. Good to have if hardware is soldered optionally - * or in case of SPI no slave is selected. Avoid lines to float - * needlessly. Use a short local PUP define. - * - * Due to errata "TXD floats when CTS is inactive" pullups are always - * on for TXD pins. - */ -#ifdef CONFIG_AT91_GPIO_PULLUP -# define PUP CONFIG_AT91_GPIO_PULLUP -#else -# define PUP 0 -#endif - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */ - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */ - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */ - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI, &pmc->pcer); - - if (cs_mask & (1 << 0)) { - at91_set_a_periph(AT91_PIO_PORTA, 28, 1); - } - if (cs_mask & (1 << 1)) { - at91_set_b_periph(AT91_PIO_PORTB, 7, 1); - } - if (cs_mask & (1 << 2)) { - at91_set_a_periph(AT91_PIO_PORTD, 8, 1); - } - if (cs_mask & (1 << 3)) { - at91_set_b_periph(AT91_PIO_PORTD, 9, 1); - } - if (cs_mask & (1 << 4)) { - at91_set_pio_output(AT91_PIO_PORTA, 28, 1); - } - if (cs_mask & (1 << 5)) { - at91_set_pio_output(AT91_PIO_PORTB, 7, 1); - } - if (cs_mask & (1 << 6)) { - at91_set_pio_output(AT91_PIO_PORTD, 8, 1); - } - if (cs_mask & (1 << 7)) { - at91_set_pio_output(AT91_PIO_PORTD, 9, 1); - } -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c deleted file mode 100644 index 6d94572237c..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9x5_devices.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - * Copyright (C) 2012 Atmel Corporation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -unsigned int get_chip_id(void) -{ - /* The 0x40 is the offset of cidr in DBGU */ - return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; -} - -unsigned int get_extension_chip_id(void) -{ - /* The 0x44 is the offset of exid in DBGU */ - return readl(ATMEL_BASE_DBGU + 0x44); -} - -unsigned int has_emac1() -{ - return cpu_is_at91sam9x25(); -} - -unsigned int has_emac0() -{ - return !(cpu_is_at91sam9g15()); -} - -unsigned int has_lcdc() -{ - return cpu_is_at91sam9g15() || cpu_is_at91sam9g35() - || cpu_is_at91sam9x35(); -} - -char *get_cpu_name() -{ - unsigned int extension_id = get_extension_chip_id(); - - if (cpu_is_at91sam9x5()) { - switch (extension_id) { - case ARCH_EXID_AT91SAM9G15: - return "AT91SAM9G15"; - case ARCH_EXID_AT91SAM9G25: - return "AT91SAM9G25"; - case ARCH_EXID_AT91SAM9G35: - return "AT91SAM9G35"; - case ARCH_EXID_AT91SAM9X25: - return "AT91SAM9X25"; - case ARCH_EXID_AT91SAM9X35: - return "AT91SAM9X35"; - default: - return "Unknown CPU type"; - } - } else { - return "Unknown CPU type"; - } -} - -void at91_seriald_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - - writel(1 << ATMEL_ID_SYS, &pmc->pcer); -} - -void at91_serial0_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ - - writel(1 << ATMEL_ID_USART0, &pmc->pcer); -} - -void at91_serial1_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ - - writel(1 << ATMEL_ID_USART1, &pmc->pcer); -} - -void at91_serial2_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ - - writel(1 << ATMEL_ID_USART2, &pmc->pcer); -} - -void at91_mci_hw_init(void) -{ - /* Initialize the MCI0 */ - at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ - at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ - at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ - at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ - at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ - - /* Enable clock for MCI0 */ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); -} - -#ifdef CONFIG_ATMEL_SPI -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI0, &pmc->pcer); - - if (cs_mask & (1 << 0)) - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); - if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 7, 0); - if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 1, 0); - if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTB, 3, 0); - if (cs_mask & (1 << 4)) - at91_set_pio_output(AT91_PIO_PORTA, 14, 0); - if (cs_mask & (1 << 5)) - at91_set_pio_output(AT91_PIO_PORTA, 7, 0); - if (cs_mask & (1 << 6)) - at91_set_pio_output(AT91_PIO_PORTA, 1, 0); - if (cs_mask & (1 << 7)) - at91_set_pio_output(AT91_PIO_PORTB, 3, 0); -} - -void at91_spi1_hw_init(unsigned long cs_mask) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ - at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ - at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ - - /* Enable clock */ - writel(1 << ATMEL_ID_SPI1, &pmc->pcer); - - if (cs_mask & (1 << 0)) - at91_set_b_periph(AT91_PIO_PORTA, 8, 0); - if (cs_mask & (1 << 1)) - at91_set_b_periph(AT91_PIO_PORTA, 0, 0); - if (cs_mask & (1 << 2)) - at91_set_b_periph(AT91_PIO_PORTA, 31, 0); - if (cs_mask & (1 << 3)) - at91_set_b_periph(AT91_PIO_PORTA, 30, 0); - if (cs_mask & (1 << 4)) - at91_set_pio_output(AT91_PIO_PORTA, 8, 0); - if (cs_mask & (1 << 5)) - at91_set_pio_output(AT91_PIO_PORTA, 0, 0); - if (cs_mask & (1 << 6)) - at91_set_pio_output(AT91_PIO_PORTA, 31, 0); - if (cs_mask & (1 << 7)) - at91_set_pio_output(AT91_PIO_PORTA, 30, 0); -} -#endif - -#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) -void at91_uhp_hw_init(void) -{ - /* Enable VBus on UHP ports */ - at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ - at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ -#if defined(CONFIG_USB_OHCI_NEW) - /* port C is OHCI only */ - at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ -#endif -} -#endif - -#ifdef CONFIG_MACB -void at91_macb_hw_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - - if (has_emac0()) { - /* Enable EMAC0 clock */ - writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - /* EMAC0 pins setup */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ - } - - if (has_emac1()) { - /* Enable EMAC1 clock */ - writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); - /* EMAC1 pins setup */ - at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ - at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ - at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ - at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ - at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ - at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ - at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ - at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ - at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ - } - -#ifndef CONFIG_RMII - /* Only emac0 support MII */ - if (has_emac0()) { - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ - } -#endif -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c deleted file mode 100644 index f363982d035..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/clock.c +++ /dev/null @@ -1,249 +0,0 @@ -/* - * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] - * - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#if !defined(CONFIG_AT91FAMILY) -# error You need to define CONFIG_AT91FAMILY in your board config! -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static unsigned long at91_css_to_rate(unsigned long css) -{ - switch (css) { - case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; - case AT91_PMC_MCKR_CSS_MAIN: - return gd->arch.main_clk_rate_hz; - case AT91_PMC_MCKR_CSS_PLLA: - return gd->arch.plla_rate_hz; - case AT91_PMC_MCKR_CSS_PLLB: - return gd->arch.pllb_rate_hz; - } - - return 0; -} - -#ifdef CONFIG_USB_ATMEL -static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) -{ - unsigned i, div = 0, mul = 0, diff = 1 << 30; - unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; - - /* PLL output max 240 MHz (or 180 MHz per errata) */ - if (out_freq > 240000000) - goto fail; - - for (i = 1; i < 256; i++) { - int diff1; - unsigned input, mul1; - - /* - * PLL input between 1MHz and 32MHz per spec, but lower - * frequences seem necessary in some cases so allow 100K. - * Warning: some newer products need 2MHz min. - */ - input = main_freq / i; -#if defined(CONFIG_AT91SAM9G20) - if (input < 2000000) - continue; -#endif - if (input < 100000) - continue; - if (input > 32000000) - continue; - - mul1 = out_freq / input; -#if defined(CONFIG_AT91SAM9G20) - if (mul > 63) - continue; -#endif - if (mul1 > 2048) - continue; - if (mul1 < 2) - goto fail; - - diff1 = out_freq - input * mul1; - if (diff1 < 0) - diff1 = -diff1; - if (diff > diff1) { - diff = diff1; - div = i; - mul = mul1; - if (diff == 0) - break; - } - } - if (i == 256 && diff > (out_freq >> 5)) - goto fail; - return ret | ((mul - 1) << 16) | div; -fail: - return 0; -} -#endif - -static u32 at91_pll_rate(u32 freq, u32 reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 16) & 0x7ff; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else - freq = 0; - - return freq; -} - -int at91_clock_init(unsigned long main_clock) -{ - unsigned freq, mckr; - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK - unsigned tmp; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(&pmc->mcfr); - } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); - tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); - } -#endif - gd->arch.main_clk_rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); - -#ifdef CONFIG_USB_ATMEL - /* - * USB clock init: choose 48 MHz PLLB value, - * disable 48MHz clock during usb peripheral suspend. - * - * REVISIT: assumes MCK doesn't derive from PLLB! - */ - gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | - AT91_PMC_PLLBR_USBDIV_2; - gd->arch.pllb_rate_hz = at91_pll_rate(main_clock, - gd->arch.at91_pllb_usb_init); -#endif - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(&pmc->mckr); -#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ - || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) - /* plla divisor by 2 */ - gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); -#endif - gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); - freq = gd->arch.mck_rate_hz; - - freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ -#if defined(CONFIG_AT91SAM9G20) - /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ - gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? - freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; - if (mckr & AT91_PMC_MCKR_MDIV_MASK) - freq /= 2; /* processor clock division */ -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ - || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) - /* mdiv <==> divisor - * 0 <==> 1 - * 1 <==> 2 - * 2 <==> 4 - * 3 <==> 3 - */ - gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == - (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) - ? freq / 3 - : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#else - gd->arch.mck_rate_hz = freq / - (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); -#endif - gd->arch.cpu_clk_rate_hz = freq; - - return 0; -} - -#if !defined(AT91_PLL_LOCK_TIMEOUT) -#define AT91_PLL_LOCK_TIMEOUT 1000000 -#endif - -void at91_plla_init(u32 pllar) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; - - writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } -} -void at91_pllb_init(u32 pllbr) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; - - writel(pllbr, &pmc->pllbr); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { - timeout--; - if (timeout == 0) - break; - } -} - -void at91_mck_init(u32 mckr) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - int timeout = AT91_PLL_LOCK_TIMEOUT; - u32 tmp; - - tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); - tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_MASK | - AT91_PMC_MCKR_CSS_MASK); - writel(tmp, &pmc->mckr); - - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { - timeout--; - if (timeout == 0) - break; - } -} - -void at91_periph_clk_enable(int id) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(1 << id, &pmc->pcer); -} diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk deleted file mode 100644 index 370630d4de0..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/config.mk +++ /dev/null @@ -1,2 +0,0 @@ -PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,) -PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE) diff --git a/arch/arm/cpu/arm926ejs/at91/cpu.c b/arch/arm/cpu/arm926ejs/at91/cpu.c deleted file mode 100644 index da1d35907e9..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/cpu.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * (C) Copyright 2009 - * Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 -#endif - -int arch_cpu_init(void) -{ - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); -} - -void arch_preboot_os(void) -{ - ulong cpiv; - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); - - /* - * Disable PITC - * Add 0x1000 to current counter to stop it faster - * without waiting for wrapping back to 0 - */ - writel(cpiv + 0x1000, &pit->mr); -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - char buf[32]; - - printf("CPU: %s\n", ATMEL_CPU_NAME); - printf("Crystal frequency: %8s MHz\n", - strmhz(buf, get_main_clk_rate())); - printf("CPU clock : %8s MHz\n", - strmhz(buf, get_cpu_clk_rate())); - printf("Master clock : %8s MHz\n", - strmhz(buf, get_mck_clk_rate())); - - return 0; -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c deleted file mode 100644 index 3f392642891..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/eflash.c +++ /dev/null @@ -1,254 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * this driver supports the enhanced embedded flash in the Atmel - * AT91SAM9XE devices with the following geometry: - * - * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) - * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) - * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) - * (the exact geometry is read from the flash at runtime, so any - * future devices should already be covered) - * - * Regions can be write/erase protected. - * Whole (!) pages can be individually written with erase on the fly. - * Writing partial pages will corrupt the rest of the page. - * - * The flash is presented to u-boot with each region being a sector, - * having the following effects: - * Each sector can be hardware protected (protect on/off). - * Each page in a sector can be rewritten anytime. - * Since pages are erased when written, the "erase" does nothing. - * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected - * by u-Boot commands. - * - * Note: Redundant environment will not work in this flash since - * it does use partial page writes. Make sure the environment spans - * whole pages! - */ - -/* - * optional TODOs (nice to have features): - * - * make the driver coexist with other NOR flash drivers - * (use an index into flash_info[], requires work - * in those other drivers, too) - * Make the erase command fill the sectors with 0xff - * (if the flashes grow larger in the future and - * someone puts a jffs2 into them) - * do a read-modify-write for partially programmed pages - */ -#include -#include -#include -#include -#include -#include - -/* checks to detect configuration errors */ -#if CONFIG_SYS_MAX_FLASH_BANKS!=1 -#error eflash: this driver can only handle 1 bank -#endif - -/* global structure */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; -static u32 pagesize; - -unsigned long flash_init (void) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU; - u32 id, size, nplanes, planesize, nlocks; - u32 addr, i, tmp=0; - - debug("eflash: init\n"); - - flash_info[0].flash_id = FLASH_UNKNOWN; - - /* check if its an AT91ARM9XE SoC */ - if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { - puts("eflash: not an AT91SAM9XE\n"); - return 0; - } - - /* now query the eflash for its structure */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - id = readl(&eefc->frr); /* word 0 */ - size = readl(&eefc->frr); /* word 1 */ - pagesize = readl(&eefc->frr); /* word 2 */ - nplanes = readl(&eefc->frr); /* word 3 */ - planesize = readl(&eefc->frr); /* word 4 */ - debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", - id, size, pagesize, nplanes, planesize); - for (i=1; ifrr); /* words 5..4+nplanes-1 */ - }; - nlocks = readl(&eefc->frr); /* word 4+nplanes */ - debug("nlocks=%u\n", nlocks); - /* since we are going to use the lock regions as sectors, check count */ - if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { - printf("eflash: number of lock regions(%u) "\ - "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", - nlocks); - nlocks = CONFIG_SYS_MAX_FLASH_SECT; - } - flash_info[0].size = size; - flash_info[0].sector_count = nlocks; - flash_info[0].flash_id = id; - - addr = ATMEL_BASE_FLASH; - for (i=0; ifrr); /* words 4+nplanes+1.. */ - flash_info[0].start[i] = addr; - flash_info[0].protect[i] = 0; - addr += tmp; - }; - - /* now read the protection information for all regions */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - for (i=0; ifrr); - flash_info[0].protect[i] = (tmp >> (i%32)) & 1; -#if defined(CONFIG_EFLASH_PROTSECTORS) - if (i < CONFIG_EFLASH_PROTSECTORS) - flash_info[0].protect[i] = 1; -#endif - } - - return size; -} - -void flash_print_info (flash_info_t *info) -{ - int i; - - puts("AT91SAM9XE embedded flash\n Size: "); - print_size(info->size, " in "); - printf("%d Sectors\n", info->sector_count); - - printf(" Sector Start Addresses:"); - for (i=0; isector_count; ++i) { - if ((i % 5) == 0) - printf("\n "); - printf(" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -int flash_real_protect (flash_info_t *info, long sector, int prot) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize; - u32 i, tmp=0; - - debug("protect sector=%ld prot=%d\n", sector, prot); - -#if defined(CONFIG_EFLASH_PROTSECTORS) - if (sector < CONFIG_EFLASH_PROTSECTORS) { - if (!prot) { - printf("eflash: sector %lu cannot be unprotected\n", - sector); - } - return 1; /* return anyway, caller does not care for result */ - } -#endif - if (prot) { - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - } else { - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - } - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - /* now re-read the protection information for all regions */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - for (i=0; isector_count; i++) { - if (i%32 == 0) - tmp = readl(&eefc->frr); - info->protect[i] = (tmp >> (i%32)) & 1; - } - return 0; -} - -static u32 erase_write_page (u32 pagenum) -{ - at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; - - debug("erase+write page=%u\n", pagenum); - - /* give erase and write page command */ - writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | - (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); - while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) - ; - /* return status */ - return readl(&eefc->fsr) - & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); -} - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - debug("erase first=%d last=%d\n", s_first, s_last); - puts("this flash does not need and support erasing!\n"); - return 0; -} - -/* - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - u32 pagenum; - u32 *src32, *dst32; - u32 i; - - debug("write src=%08lx addr=%08lx cnt=%lx\n", - (ulong)src, addr, cnt); - - /* REQUIRE addr to be on a page start, abort if not */ - if (addr % pagesize) { - printf ("eflash: start %08lx is not on page start\n"\ - " write aborted\n", addr); - return 1; - } - - /* now start copying data */ - pagenum = (addr-ATMEL_BASE_FLASH)/pagesize; - src32 = (u32 *) src; - dst32 = (u32 *) addr; - while (cnt > 0) { - i = pagesize / 4; - /* fill page buffer */ - while (i--) - *dst32++ = *src32++; - /* write page */ - if (erase_write_page(pagenum)) - return 1; - pagenum++; - if (cnt > pagesize) - cnt -= pagesize; - else - cnt = 0; - } - return 0; -} diff --git a/arch/arm/cpu/arm926ejs/at91/led.c b/arch/arm/cpu/arm926ejs/at91/led.c deleted file mode 100644 index b8d5c785df4..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/led.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifdef CONFIG_RED_LED -void red_led_on(void) -{ - gpio_set_value(CONFIG_RED_LED, 1); -} - -void red_led_off(void) -{ - gpio_set_value(CONFIG_RED_LED, 0); -} -#endif - -#ifdef CONFIG_GREEN_LED -void green_led_on(void) -{ - gpio_set_value(CONFIG_GREEN_LED, 0); -} - -void green_led_off(void) -{ - gpio_set_value(CONFIG_GREEN_LED, 1); -} -#endif - -#ifdef CONFIG_YELLOW_LED -void yellow_led_on(void) -{ - gpio_set_value(CONFIG_YELLOW_LED, 0); -} - -void yellow_led_off(void) -{ - gpio_set_value(CONFIG_YELLOW_LED, 1); -} -#endif diff --git a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S b/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S deleted file mode 100644 index a9ec81a75c8..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/lowlevel_init.S +++ /dev/null @@ -1,246 +0,0 @@ -/* - * Memory Setup stuff - taken from blob memsetup.S - * - * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and - * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) - * - * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#ifdef CONFIG_ATMEL_LEGACY -#include -#endif -#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL -#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL -#endif - -.globl lowlevel_init -.type lowlevel_init,function -lowlevel_init: - -POS1: - adr r5, POS1 /* r5 = POS1 run time */ - ldr r0, =POS1 /* r0 = POS1 compile */ - sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ - - /* memory control configuration 1 */ - ldr r0, =SMRDATA - ldr r2, =SMRDATA1 - add r0, r0, r5 - add r2, r2, r5 -0: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 0b - -/* ---------------------------------------------------------------------------- - * PMC Init Step 1. - * ---------------------------------------------------------------------------- - * - Check if the PLL is already initialized - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_ASM_PMC_MCKR) - ldr r0, [r1] - and r0, r0, #3 - cmp r0, #0 - bne PLL_setup_end - -/* --------------------------------------------------------------------------- - * - Enable the Main Oscillator - * --------------------------------------------------------------------------- - */ - ldr r1, =(AT91_ASM_PMC_MOR) - ldr r2, =(AT91_ASM_PMC_SR) - /* Main oscillator Enable register PMC_MOR: */ - ldr r0, =CONFIG_SYS_MOR_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Main Oscillator is enabled */ - mov r4, #AT91_PMC_IXR_MOSCS -MOSCS_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_IXR_MOSCS - bne MOSCS_Loop - -/* ---------------------------------------------------------------------------- - * PMC Init Step 2. - * ---------------------------------------------------------------------------- - * Setup PLLA - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_ASM_PMC_PLLAR) - ldr r0, =CONFIG_SYS_PLLAR_VAL - str r0, [r1] - - /* Reading the PMC Status register to detect when the PLLA is locked */ - mov r4, #AT91_PMC_IXR_LOCKA -MOSCS_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_IXR_LOCKA - bne MOSCS_Loop1 - -/* ---------------------------------------------------------------------------- - * PMC Init Step 3. - * ---------------------------------------------------------------------------- - * - Switch on the Main Oscillator - * ---------------------------------------------------------------------------- - */ - ldr r1, =(AT91_ASM_PMC_MCKR) - - /* -Master Clock Controller register PMC_MCKR */ - ldr r0, =CONFIG_SYS_MCKR1_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_IXR_MCKRDY -MCKRDY_Loop: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_IXR_MCKRDY - bne MCKRDY_Loop - - ldr r0, =CONFIG_SYS_MCKR2_VAL - str r0, [r1] - - /* Reading the PMC Status to detect when the Master clock is ready */ - mov r4, #AT91_PMC_IXR_MCKRDY -MCKRDY_Loop1: - ldr r3, [r2] - and r3, r4, r3 - cmp r3, #AT91_PMC_IXR_MCKRDY - bne MCKRDY_Loop1 -PLL_setup_end: - -/* ---------------------------------------------------------------------------- - * - memory control configuration 2 - * ---------------------------------------------------------------------------- - */ - ldr r0, =(AT91_ASM_SDRAMC_TR) - ldr r1, [r0] - cmp r1, #0 - bne SDRAM_setup_end - - ldr r0, =SMRDATA1 - ldr r2, =SMRDATA2 - add r0, r0, r5 - add r2, r2, r5 -2: - /* the address */ - ldr r1, [r0], #4 - /* the value */ - ldr r3, [r0], #4 - str r3, [r1] - cmp r2, r0 - bne 2b - -SDRAM_setup_end: - /* everything is fine now */ - mov pc, lr - - .ltorg - -SMRDATA: - .word AT91_ASM_WDT_MR - .word CONFIG_SYS_WDTC_WDMR_VAL - /* configure PIOx as EBI0 D[16-31] */ -#if defined(CONFIG_AT91SAM9263) - .word AT91_ASM_PIOD_PDR - .word CONFIG_SYS_PIOD_PDR_VAL1 - .word AT91_ASM_PIOD_PUDR - .word CONFIG_SYS_PIOD_PPUDR_VAL - .word AT91_ASM_PIOD_ASR - .word CONFIG_SYS_PIOD_PPUDR_VAL -#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ - || defined(CONFIG_AT91SAM9G20) - .word AT91_ASM_PIOC_PDR - .word CONFIG_SYS_PIOC_PDR_VAL1 - .word AT91_ASM_PIOC_PUDR - .word CONFIG_SYS_PIOC_PPUDR_VAL -#endif - .word AT91_ASM_MATRIX_CSA0 - .word CONFIG_SYS_MATRIX_EBICSA_VAL - - /* flash */ - .word AT91_ASM_SMC_MODE0 - .word CONFIG_SYS_SMC0_MODE0_VAL - - .word AT91_ASM_SMC_CYCLE0 - .word CONFIG_SYS_SMC0_CYCLE0_VAL - - .word AT91_ASM_SMC_PULSE0 - .word CONFIG_SYS_SMC0_PULSE0_VAL - - .word AT91_ASM_SMC_SETUP0 - .word CONFIG_SYS_SMC0_SETUP0_VAL - -SMRDATA1: - .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL1 - .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL1 - .word AT91_ASM_SDRAMC_CR - .word CONFIG_SYS_SDRC_CR_VAL - .word AT91_ASM_SDRAMC_MDR - .word CONFIG_SYS_SDRC_MDR_VAL - .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 - .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 - .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 - .word AT91_ASM_SDRAMC_MR - .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 - .word AT91_ASM_SDRAMC_TR - .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 - /* User reset enable*/ - .word AT91_ASM_RSTC_MR - .word CONFIG_SYS_RSTC_RMR_VAL -#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP - /* MATRIX_MCFG - REMAP all masters */ - .word AT91_ASM_MATRIX_MCFG - .word 0x1FF -#endif -SMRDATA2: - .word 0 diff --git a/arch/arm/cpu/arm926ejs/at91/reset.c b/arch/arm/cpu/arm926ejs/at91/reset.c deleted file mode 100644 index e67f47bd041..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) -{ - at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; - - writel(AT91_RSTC_KEY - | AT91_RSTC_CR_PROCRST /* Processor Reset */ - | AT91_RSTC_CR_PERRST /* Peripheral Reset */ -#ifdef CONFIG_AT91RESET_EXTRST - | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ -#endif - , &rstc->cr); - /* never reached */ - while (1) - ; -} diff --git a/arch/arm/cpu/arm926ejs/at91/timer.c b/arch/arm/cpu/arm926ejs/at91/timer.c deleted file mode 100644 index b0b7fb93fba..00000000000 --- a/arch/arm/cpu/arm926ejs/at91/timer.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#if !defined(CONFIG_AT91FAMILY) -# error You need to define CONFIG_AT91FAMILY in your board config! -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by - * setting the 20 bit counter period to its maximum (0xfffff). - * (See the relevant data sheets to understand that this really works) - * - * We do also mimic the typical powerpc way of incrementing - * two 32 bit registers called tbl and tbu. - * - * Those registers increment at 1/16 the main clock rate. - */ - -#define TIMER_LOAD_VAL 0xfffff - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - -/* - * Use the PITC in full 32 bit incrementing mode - */ -int timer_init(void) -{ - at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - /* Enable PITC Clock */ - writel(1 << ATMEL_ID_SYS, &pmc->pcer); - - /* Enable PITC */ - writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); - - gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; - gd->arch.tbu = gd->arch.tbl = 0; - - return 0; -} - -/* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 409e6f5651b..6dbca26ceb4 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -40,7 +40,6 @@ endif obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/ obj-$(if $(filter armada-xp,$(SOC)),y) += armada-xp/ -obj-$(CONFIG_AT91FAMILY) += at91/ obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/ obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/ obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/ diff --git a/arch/arm/cpu/armv7/at91/Makefile b/arch/arm/cpu/armv7/at91/Makefile deleted file mode 100644 index f4f35a4bc19..00000000000 --- a/arch/arm/cpu/armv7/at91/Makefile +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 -# Bo Shen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o -obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o -obj-y += clock.o -obj-y += cpu.o -obj-y += reset.o -obj-y += timer.o diff --git a/arch/arm/cpu/armv7/at91/clock.c b/arch/arm/cpu/armv7/at91/clock.c deleted file mode 100644 index 0bf453eff57..00000000000 --- a/arch/arm/cpu/armv7/at91/clock.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] - * - * Copyright (C) 2005 David Brownell - * Copyright (C) 2005 Ivan Kokshaysky - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD - * Copyright (C) 2013 Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#if !defined(CONFIG_AT91FAMILY) -# error You need to define CONFIG_AT91FAMILY in your board config! -#endif - -DECLARE_GLOBAL_DATA_PTR; - -static unsigned long at91_css_to_rate(unsigned long css) -{ - switch (css) { - case AT91_PMC_MCKR_CSS_SLOW: - return CONFIG_SYS_AT91_SLOW_CLOCK; - case AT91_PMC_MCKR_CSS_MAIN: - return gd->arch.main_clk_rate_hz; - case AT91_PMC_MCKR_CSS_PLLA: - return gd->arch.plla_rate_hz; - } - - return 0; -} - -static u32 at91_pll_rate(u32 freq, u32 reg) -{ - unsigned mul, div; - - div = reg & 0xff; - mul = (reg >> 18) & 0x7f; - if (div && mul) { - freq /= div; - freq *= mul + 1; - } else { - freq = 0; - } - - return freq; -} - -int at91_clock_init(unsigned long main_clock) -{ - unsigned freq, mckr; - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK - unsigned tmp; - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(&pmc->mcfr); - } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); - tmp &= AT91_PMC_MCFR_MAINF_MASK; - main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); - } -#endif - gd->arch.main_clk_rate_hz = main_clock; - - /* report if PLLA is more than mildly overclocked */ - gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(&pmc->mckr); - - /* plla divisor by 2 */ - if (mckr & (1 << 12)) - gd->arch.plla_rate_hz >>= 1; - - gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); - freq = gd->arch.mck_rate_hz; - - /* prescale */ - freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; - - switch (mckr & AT91_PMC_MCKR_MDIV_MASK) { - case AT91_PMC_MCKR_MDIV_2: - gd->arch.mck_rate_hz = freq / 2; - break; - case AT91_PMC_MCKR_MDIV_3: - gd->arch.mck_rate_hz = freq / 3; - break; - case AT91_PMC_MCKR_MDIV_4: - gd->arch.mck_rate_hz = freq / 4; - break; - default: - break; - } - - gd->arch.cpu_clk_rate_hz = freq; - - return 0; -} - -void at91_plla_init(u32 pllar) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - writel(pllar, &pmc->pllar); - while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) - ; -} - -void at91_mck_init(u32 mckr) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = readl(&pmc->mckr); - tmp &= ~(AT91_PMC_MCKR_CSS_MASK | - AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); -#ifdef CPU_HAS_H32MXDIV - tmp &= ~AT91_PMC_MCKR_H32MXDIV; -#endif - - tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | - AT91_PMC_MCKR_PRES_MASK | - AT91_PMC_MCKR_MDIV_MASK | - AT91_PMC_MCKR_PLLADIV_2); -#ifdef CPU_HAS_H32MXDIV - tmp |= mckr & AT91_PMC_MCKR_H32MXDIV; -#endif - - writel(tmp, &pmc->mckr); - - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; -} - -void at91_periph_clk_enable(int id) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 regval; - - if (id > AT91_PMC_PCR_PID_MASK) - return; - - regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id; - - writel(regval, &pmc->pcr); -} - -void at91_periph_clk_disable(int id) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 regval; - - if (id > AT91_PMC_PCR_PID_MASK) - return; - - regval = AT91_PMC_PCR_CMD_WRITE | id; - - writel(regval, &pmc->pcr); -} diff --git a/arch/arm/cpu/armv7/at91/config.mk b/arch/arm/cpu/armv7/at91/config.mk deleted file mode 100644 index db6030880fb..00000000000 --- a/arch/arm/cpu/armv7/at91/config.mk +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright (C) 2014, Andreas Bießmann -# -# SPDX-License-Identifier: GPL-2.0+ -# -ifndef CONFIG_SPL_BUILD -ALL-y += u-boot.img -endif diff --git a/arch/arm/cpu/armv7/at91/cpu.c b/arch/arm/cpu/armv7/at91/cpu.c deleted file mode 100644 index 8d86f97e3da..00000000000 --- a/arch/arm/cpu/armv7/at91/cpu.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * (C) Copyright 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * (C) Copyright 2009 - * Jean-Christophe PLAGNIOL-VILLARD - * (C) Copyright 2013 - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#ifndef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 0 -#endif - -int arch_cpu_init(void) -{ - return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); -} - -void arch_preboot_os(void) -{ - ulong cpiv; - at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; - - cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); - - /* - * Disable PITC - * Add 0x1000 to current counter to stop it faster - * without waiting for wrapping back to 0 - */ - writel(cpiv + 0x1000, &pit->mr); -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - char buf[32]; - - printf("CPU: %s\n", get_cpu_name()); - printf("Crystal frequency: %8s MHz\n", - strmhz(buf, get_main_clk_rate())); - printf("CPU clock : %8s MHz\n", - strmhz(buf, get_cpu_clk_rate())); - printf("Master clock : %8s MHz\n", - strmhz(buf, get_mck_clk_rate())); - - return 0; -} -#endif - -void enable_caches(void) -{ - icache_enable(); - dcache_enable(); -} - -unsigned int get_chip_id(void) -{ - return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK; -} - -unsigned int get_extension_chip_id(void) -{ - return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID); -} diff --git a/arch/arm/cpu/armv7/at91/reset.c b/arch/arm/cpu/armv7/at91/reset.c deleted file mode 100644 index b30e79b60ad..00000000000 --- a/arch/arm/cpu/armv7/at91/reset.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2013 - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -/* Reset the cpu by telling the reset controller to do so */ -void reset_cpu(ulong ignored) -{ - at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; - - writel(AT91_RSTC_KEY - | AT91_RSTC_CR_PROCRST /* Processor Reset */ - | AT91_RSTC_CR_PERRST /* Peripheral Reset */ -#ifdef CONFIG_AT91RESET_EXTRST - | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ -#endif - , &rstc->cr); - /* never reached */ - do { } while (1); -} diff --git a/arch/arm/cpu/armv7/at91/sama5d3_devices.c b/arch/arm/cpu/armv7/at91/sama5d3_devices.c deleted file mode 100644 index 78ecfc882a8..00000000000 --- a/arch/arm/cpu/armv7/at91/sama5d3_devices.c +++ /dev/null @@ -1,218 +0,0 @@ -/* - * Copyright (C) 2012-2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -unsigned int has_emac() -{ - return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36(); -} - -unsigned int has_gmac() -{ - return !cpu_is_sama5d31(); -} - -unsigned int has_lcdc() -{ - return !cpu_is_sama5d35(); -} - -char *get_cpu_name() -{ - unsigned int extension_id = get_extension_chip_id(); - - if (cpu_is_sama5d3()) - switch (extension_id) { - case ARCH_EXID_SAMA5D31: - return "SAMA5D31"; - case ARCH_EXID_SAMA5D33: - return "SAMA5D33"; - case ARCH_EXID_SAMA5D34: - return "SAMA5D34"; - case ARCH_EXID_SAMA5D35: - return "SAMA5D35"; - case ARCH_EXID_SAMA5D36: - return "SAMA5D36"; - default: - return "Unknown CPU type"; - } - else - return "Unknown CPU type"; -} - -void at91_serial0_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ - at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_USART0); -} - -void at91_serial1_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ - at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_USART1); -} - -void at91_serial2_hw_init(void) -{ - at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ - at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_USART2); -} - -void at91_seriald_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ - at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_DBGU); -} - -#if defined(CONFIG_ATMEL_SPI) -void at91_spi0_hw_init(unsigned long cs_mask) -{ - at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ - at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ - at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ - - if (cs_mask & (1 << 0)) - at91_set_pio_output(AT91_PIO_PORTD, 13, 1); - if (cs_mask & (1 << 1)) - at91_set_pio_output(AT91_PIO_PORTD, 14, 1); - if (cs_mask & (1 << 2)) - at91_set_pio_output(AT91_PIO_PORTD, 15, 1); - if (cs_mask & (1 << 3)) - at91_set_pio_output(AT91_PIO_PORTD, 16, 1); - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_SPI0); -} -#endif - -#ifdef CONFIG_GENERIC_ATMEL_MCI -void at91_mci_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ - at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ - at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ - at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ - at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ -#ifdef CONFIG_ATMEL_MCI_8BIT - at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ - at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ - at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ - at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ -#endif - at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_MCI0); -} -#endif - -#ifdef CONFIG_MACB -void at91_macb_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ - at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ - at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ - at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ - at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ - at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ - at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ - at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_EMAC); -} - -void at91_gmac_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ - at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ - at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ - at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ - at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ - - at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ - at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ - - at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ - at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ - at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_GMAC); -} -#endif - -#ifdef CONFIG_LCD -void at91_lcd_hw_init(void) -{ - at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ - at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ - at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ - at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ - at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ - - /* The lower 16-bit of LCD only available on Port A */ - at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ - at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ - at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ - at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ - at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ - at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ - at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ - at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ - at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ - at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ - at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ - at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ - at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ - at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ - at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ - at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ - - /* Enable clock */ - at91_periph_clk_enable(ATMEL_ID_LCDC); -} -#endif - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA -void at91_udp_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable UPLL clock */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); - /* Enable UDPHS clock */ - at91_periph_clk_enable(ATMEL_ID_UDPHS); -} -#endif diff --git a/arch/arm/cpu/armv7/at91/sama5d4_devices.c b/arch/arm/cpu/armv7/at91/sama5d4_devices.c deleted file mode 100644 index ef39cb7e089..00000000000 --- a/arch/arm/cpu/armv7/at91/sama5d4_devices.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (C) 2014 Atmel - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -char *get_cpu_name() -{ - unsigned int extension_id = get_extension_chip_id(); - - if (cpu_is_sama5d4()) - switch (extension_id) { - case ARCH_EXID_SAMA5D41: - return "SAMA5D41"; - case ARCH_EXID_SAMA5D42: - return "SAMA5D42"; - case ARCH_EXID_SAMA5D43: - return "SAMA5D43"; - case ARCH_EXID_SAMA5D44: - return "SAMA5D44"; - default: - return "Unknown CPU type"; - } - else - return "Unknown CPU type"; -} - -#ifdef CONFIG_USB_GADGET_ATMEL_USBA -void at91_udp_hw_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - /* Enable UPLL clock */ - writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); - /* Enable UDPHS clock */ - at91_periph_clk_enable(ATMEL_ID_UDPHS); -} -#endif - -#ifdef CONFIG_SPL_BUILD -void matrix_init(void) -{ - struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0; - struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1; - int i; - - /* Disable the write protect */ - writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); - writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); - - /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */ - for (i = 4; i <= 10; i++) { - writel(0x000f0f0f, &h64mx->ssr[i]); - writel(0x0000ffff, &h64mx->sassr[i]); - writel(0x0000000f, &h64mx->srtsr[i]); - } - - /* CS3 */ - writel(0x00c0c0c0, &h32mx->ssr[3]); - writel(0xff000000, &h32mx->sassr[3]); - writel(0xff000000, &h32mx->srtsr[3]); - - /* NFC SRAM */ - writel(0x00010101, &h32mx->ssr[4]); - writel(0x00000001, &h32mx->sassr[4]); - writel(0x00000001, &h32mx->srtsr[4]); - - /* Enable the write protect */ - writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); - writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); -} - -void redirect_int_from_saic_to_aic(void) -{ - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; - u32 key32; - - if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) { - key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY; - writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); - } -} -#endif diff --git a/arch/arm/cpu/armv7/at91/timer.c b/arch/arm/cpu/armv7/at91/timer.c deleted file mode 100644 index 19bf80ba7eb..00000000000 --- a/arch/arm/cpu/armv7/at91/timer.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2013 - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include - -#if !defined(CONFIG_AT91FAMILY) -# error You need to define CONFIG_AT91FAMILY in your board config! -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * We're using the SAMA5D3x PITC in 32 bit mode, by - * setting the 20 bit counter period to its maximum (0xfffff). - * (See the relevant data sheets to understand that this really works) - * - * We do also mimic the typical powerpc way of incrementing - * two 32 bit registers called tbl and tbu. - * - * Those registers increment at 1/16 the main clock rate. - */ - -#define TIMER_LOAD_VAL 0xfffff - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - -/* - * Use the PITC in full 32 bit incrementing mode - */ -int timer_init(void) -{ - at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; - - /* Enable PITC Clock */ - at91_periph_clk_enable(ATMEL_ID_PIT); - - /* Enable PITC */ - writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); - - gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; - - gd->arch.tbu = 0; - gd->arch.tbl = 0; - - return 0; -} - -/* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; - - ulong now = readl(&pit->piir); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/arch/arm/cpu/at91-common/Makefile b/arch/arm/cpu/at91-common/Makefile deleted file mode 100644 index 03614d41406..00000000000 --- a/arch/arm/cpu/at91-common/Makefile +++ /dev/null @@ -1,18 +0,0 @@ -# -# (C) Copyright 2000-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2013 Atmel Corporation -# Bo Shen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o -ifneq ($(CONFIG_SPL_BUILD),) -obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o -obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o -obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o -obj-y += spl.o -endif diff --git a/arch/arm/cpu/at91-common/mpddrc.c b/arch/arm/cpu/at91-common/mpddrc.c deleted file mode 100644 index beec13db8c1..00000000000 --- a/arch/arm/cpu/at91-common/mpddrc.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -static inline void atmel_mpddr_op(int mode, u32 ram_address) -{ - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - - writel(mode, &mpddr->mr); - writel(0, ram_address); -} - -static int ddr2_decodtype_is_seq(u32 cr) -{ -#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) - if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) - return 0; -#endif - return 1; -} - -int ddr2_init(const unsigned int ram_address, - const struct atmel_mpddr *mpddr_value) -{ - struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; - u32 ba_off, cr; - - /* Compute bank offset according to NC in configuration register */ - ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; - if (ddr2_decodtype_is_seq(mpddr_value->cr)) - ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; - - ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; - - /* Program the memory device type into the memory device register */ - writel(mpddr_value->md, &mpddr->md); - - /* Program the configuration register */ - writel(mpddr_value->cr, &mpddr->cr); - - /* Program the timing register */ - writel(mpddr_value->tpr0, &mpddr->tpr0); - writel(mpddr_value->tpr1, &mpddr->tpr1); - writel(mpddr_value->tpr2, &mpddr->tpr2); - - /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); - - /* A 200 us is provided to precede any signal toggle */ - udelay(200); - - /* Issue a NOP command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); - - /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); - - /* Issue an extended mode register set(EMRS2) to choose operation */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x2 << ba_off)); - - /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x3 << ba_off)); - - /* - * Issue an extended mode register set(EMRS1) to enable DLL and - * program D.I.C (output driver impedance control) - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* Enable DLL reset */ - cr = readl(&mpddr->cr); - writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); - - /* A mode register set(MRS) cycle is issued to reset DLL */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); - - /* Issue an all banks precharge command */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); - - /* Two auto-refresh (CBR) cycles are provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); - - /* Disable DLL reset */ - cr = readl(&mpddr->cr); - writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); - - /* A mode register set (MRS) cycle is issued to disable DLL reset */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); - - /* Set OCD calibration in default state */ - cr = readl(&mpddr->cr); - writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); - - /* - * An extended mode register set (EMRS1) cycle is issued - * to OCD default value - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* OCD calibration mode exit */ - cr = readl(&mpddr->cr); - writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); - - /* - * An extended mode register set (EMRS1) cycle is issued - * to enable OCD exit - */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, - ram_address + (0x1 << ba_off)); - - /* A nornal mode command is provided */ - atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); - - /* Perform a write access to any DDR2-SDRAM address */ - writel(0, ram_address); - - /* Write the refresh rate */ - writel(mpddr_value->rtr, &mpddr->rtr); - - return 0; -} diff --git a/arch/arm/cpu/at91-common/phy.c b/arch/arm/cpu/at91-common/phy.c deleted file mode 100644 index 2cba7169e4e..00000000000 --- a/arch/arm/cpu/at91-common/phy.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2012 - * Markus Hubig - * IMKO GmbH - * - * Copyright (C) 2013 DENX Software Engineering, hs@denx.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -void at91_phy_reset(void) -{ - unsigned long erstl; - unsigned long start = get_timer(0); - unsigned long const timeout = 1000; /* 1000ms */ - at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; - - erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; - - /* - * Need to reset PHY -> 500ms reset - * Reset PHY by pulling the NRST line for 500ms to low. To do so - * disable user reset for low level on NRST pin and poll the NRST - * level in reset status register. - */ - writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | - AT91_RSTC_MR_URSTEN, &rstc->mr); - - writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); - - /* Wait for end of hardware reset */ - while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { - /* avoid shutdown by watchdog */ - WATCHDOG_RESET(); - mdelay(10); - - /* timeout for not getting stuck in an endless loop */ - if (get_timer(start) >= timeout) { - puts("*** ERROR: Timeout waiting for PHY reset!\n"); - break; - } - }; - - /* Restore NRST value */ - writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); -} diff --git a/arch/arm/cpu/at91-common/sdram.c b/arch/arm/cpu/at91-common/sdram.c deleted file mode 100644 index 5758b066e46..00000000000 --- a/arch/arm/cpu/at91-common/sdram.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) -{ - struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; - unsigned int i; - - /* SDRAM feature must be in the configuration register */ - writel(p->cr, ®->cr); - - /* The SDRAM memory type must be set in the Memory Device Register */ - writel(p->mdr, ®->mdr); - - /* - * The minimum pause of 200 us is provided to precede any single - * toggle - */ - for (i = 0; i < 1000; i++) - ; - - /* A NOP command is issued to the SDRAM devices */ - writel(AT91_SDRAMC_MODE_NOP, ®->mr); - writel(0x00000000, sdram_address); - - /* An All Banks Precharge command is issued to the SDRAM devices */ - writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); - writel(0x00000000, sdram_address); - - for (i = 0; i < 10000; i++) - ; - - /* Eight auto-refresh cycles are provided */ - for (i = 0; i < 8; i++) { - writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); - writel(0x00000001 + i, sdram_address + 4 + 4 * i); - } - - /* - * A Mode Register set (MRS) cyscle is issued to program the - * SDRAM parameters(TCSR, PASR, DS) - */ - writel(AT91_SDRAMC_MODE_LMR, ®->mr); - writel(0xcafedede, sdram_address + 0x24); - - /* - * The application must go into Normal Mode, setting Mode - * to 0 in the Mode Register and perform a write access at - * any location in the SDRAM. - */ - writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); - writel(0x00000000, sdram_address); /* Perform Normal mode */ - - /* - * Write the refresh rate into the count field in the SDRAMC - * Refresh Timer Rgister. - */ - writel(p->tr, ®->tr); - - return 0; -} diff --git a/arch/arm/cpu/at91-common/spl.c b/arch/arm/cpu/at91-common/spl.c deleted file mode 100644 index aaa5eec2e66..00000000000 --- a/arch/arm/cpu/at91-common/spl.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include - -#if defined(CONFIG_AT91SAM9_WATCHDOG) -void at91_disable_wdt(void) { } -#else -void at91_disable_wdt(void) -{ - struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; - - writel(AT91_WDT_MR_WDDIS, &wdt->mr); -} -#endif - -u32 spl_boot_device(void) -{ -#ifdef CONFIG_SYS_USE_MMC - return BOOT_DEVICE_MMC1; -#elif CONFIG_SYS_USE_NANDFLASH - return BOOT_DEVICE_NAND; -#elif CONFIG_SYS_USE_SERIALFLASH - return BOOT_DEVICE_SPI; -#endif - return BOOT_DEVICE_NONE; -} - -u32 spl_boot_mode(void) -{ - switch (spl_boot_device()) { -#ifdef CONFIG_SYS_USE_MMC - case BOOT_DEVICE_MMC1: - return MMCSD_MODE_FS; - break; -#endif - case BOOT_DEVICE_NONE: - default: - hang(); - } -} diff --git a/arch/arm/cpu/at91-common/spl_at91.c b/arch/arm/cpu/at91-common/spl_at91.c deleted file mode 100644 index 89f588be45a..00000000000 --- a/arch/arm/cpu/at91-common/spl_at91.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - * (C) Copyright 2014 DENX Software Engineering - * Heiko Schocher - * - * Based on: - * Copyright (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void enable_ext_reset(void) -{ - struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; - - writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); -} - -void lowlevel_clock_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { - /* Enable Main Oscillator */ - writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); - - /* Wait until Main Oscillator is stable */ - while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) - ; - } - - /* After stabilization, switch to Main Oscillator */ - if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { - unsigned long tmp; - - tmp = readl(&pmc->mckr); - tmp &= ~AT91_PMC_CSS; - tmp |= AT91_PMC_CSS_MAIN; - writel(tmp, &pmc->mckr); - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; - - tmp &= ~AT91_PMC_PRES; - tmp |= AT91_PMC_PRES_1; - writel(tmp, &pmc->mckr); - while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) - ; - } - - return; -} - -void __weak matrix_init(void) -{ -} - -void __weak at91_spl_board_init(void) -{ -} - -void spl_board_init(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - - lowlevel_clock_init(); - at91_disable_wdt(); - - /* - * At this stage the main oscillator is supposed to be enabled - * PCK = MCK = MOSC - */ - writel(0x00, &pmc->pllicpr); - - /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ - at91_plla_init(CONFIG_SYS_AT91_PLLA); - - /* PCK = PLLA = 2 * MCK */ - at91_mck_init(CONFIG_SYS_MCKR); - - /* Switch MCK on PLLA output */ - at91_mck_init(CONFIG_SYS_MCKR_CSS); - -#if defined(CONFIG_SYS_AT91_PLLB) - /* Configure PLLB */ - at91_pllb_init(CONFIG_SYS_AT91_PLLB); -#endif - - /* Enable External Reset */ - enable_ext_reset(); - - /* Initialize matrix */ - matrix_init(); - - gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; - /* - * init timer long enough for using in spl. - */ - timer_init(); - - /* enable clocks for all PIOs */ - at91_periph_clk_enable(ATMEL_ID_PIOA); - at91_periph_clk_enable(ATMEL_ID_PIOB); - at91_periph_clk_enable(ATMEL_ID_PIOC); - /* init console */ - at91_seriald_hw_init(); - preloader_console_init(); - - mem_init(); - - at91_spl_board_init(); -} diff --git a/arch/arm/cpu/at91-common/spl_atmel.c b/arch/arm/cpu/at91-common/spl_atmel.c deleted file mode 100644 index 9cc1111234a..00000000000 --- a/arch/arm/cpu/at91-common/spl_atmel.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static void switch_to_main_crystal_osc(void) -{ - struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; - u32 tmp; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_MOSCEN; - tmp |= AT91_PMC_MOR_OSCOUNT(8); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) - ; - - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_OSCBYPASS; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - tmp = readl(&pmc->mor); - tmp |= AT91_PMC_MOR_MOSCSEL; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); - - while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) - ; - - /* Wait until MAINRDY field is set to make sure main clock is stable */ - while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) - ; - -#ifndef CONFIG_SAMA5D4 - tmp = readl(&pmc->mor); - tmp &= ~AT91_PMC_MOR_MOSCRCEN; - tmp &= ~AT91_PMC_MOR_KEY(0xff); - tmp |= AT91_PMC_MOR_KEY(0x37); - writel(tmp, &pmc->mor); -#endif -} - -__weak void matrix_init(void) -{ - /* This only be used for sama5d4 soc now */ -} - -__weak void redirect_int_from_saic_to_aic(void) -{ - /* This only be used for sama5d4 soc now */ -} - -void s_init(void) -{ - switch_to_main_crystal_osc(); - - /* disable watchdog */ - at91_disable_wdt(); - - /* PMC configuration */ - at91_pmc_init(); - - at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); - - matrix_init(); - - redirect_int_from_saic_to_aic(); - - timer_init(); - - board_early_init_f(); - - preloader_console_init(); - - mem_init(); -} diff --git a/arch/arm/cpu/at91-common/u-boot-spl.lds b/arch/arm/cpu/at91-common/u-boot-spl.lds deleted file mode 100644 index eccca43a423..00000000000 --- a/arch/arm/cpu/at91-common/u-boot-spl.lds +++ /dev/null @@ -1,55 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2010 - * Texas Instruments, - * Aneesh V - * - * (C) 2013 Atmel Corporation - * Bo Shen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ - LENGTH = CONFIG_SPL_MAX_SIZE } -MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ - LENGTH = CONFIG_SPL_BSS_MAX_SIZE } - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - .text : - { - __start = .; - *(.vectors) - arch/arm/cpu/armv7/start.o (.text*) - *(.text*) - } >.sram - - . = ALIGN(4); - .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram - - . = ALIGN(4); - .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram - - . = ALIGN(4); - __image_copy_end = .; - - .end : - { - *(.__end) - } >.sram - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } >.sdram -} diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile new file mode 100644 index 00000000000..e596ba6ce80 --- /dev/null +++ b/arch/arm/mach-at91/Makefile @@ -0,0 +1,12 @@ +obj-$(CONFIG_AT91_WANTS_COMMON_PHY) += phy.o +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o +obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o +obj-$(CONFIG_SAMA5D3) += mpddrc.o spl_atmel.o +obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o +obj-y += spl.o +endif + +obj-$(CONFIG_CPU_ARM920T) += arm920t/ +obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/ +obj-$(CONFIG_CPU_V7) += armv7/ diff --git a/arch/arm/mach-at91/arm920t/Makefile b/arch/arm/mach-at91/arm920t/Makefile new file mode 100644 index 00000000000..561b4b4cbb7 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += lowlevel_init.o +obj-y += reset.o +obj-y += timer.o +obj-y += clock.o +obj-y += cpu.o +obj-y += at91rm9200_devices.o diff --git a/arch/arm/mach-at91/arm920t/at91rm9200_devices.c b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c new file mode 100644 index 00000000000..fc54327c0d3 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/at91rm9200_devices.c @@ -0,0 +1,67 @@ +/* + * [partely copied from arch/arm/cpu/arm926ejs/at91/arm9260_devices.c] + * + * (C) Copyright 2011 + * Andreas Bießmann + * + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 30, PUP); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 31, 1); /* DTXD */ + /* writing SYS to PCER has no effect on AT91RM9200 */ +} diff --git a/arch/arm/mach-at91/arm920t/clock.c b/arch/arm/mach-at91/arm920t/clock.c new file mode 100644 index 00000000000..2813bf78216 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/clock.c @@ -0,0 +1,157 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2011 Andreas Bießmann + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_MCKR_CSS_SLOW: + return CONFIG_SYS_AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return gd->arch.main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return gd->arch.plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return gd->arch.pllb_rate_hz; + } + + return 0; +} + +#ifdef CONFIG_USB_ATMEL +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} +#endif + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + } +#endif + gd->arch.main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + +#ifdef CONFIG_USB_ATMEL + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + AT91_PMC_PLLBR_USBDIV_2; + gd->arch.pllb_rate_hz = at91_pll_rate(main_clock, + gd->arch.at91_pllb_usb_init); +#endif + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(&pmc->mckr); + gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = gd->arch.mck_rate_hz; + + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ + /* mdiv */ + gd->arch.mck_rate_hz = freq / + (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); + gd->arch.cpu_clk_rate_hz = freq; + + return 0; +} diff --git a/arch/arm/mach-at91/arm920t/cpu.c b/arch/arm/mach-at91/arm920t/cpu.c new file mode 100644 index 00000000000..b0f411b1c36 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/cpu.c @@ -0,0 +1,26 @@ +/* + * [origin: arch/arm/cpu/arm926ejs/at91/cpu.c] + * + * (C) Copyright 2011 + * Andreas Bießmann, andreas.devel@googlemail.com + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * (C) Copyright 2009 + * Jean-Christophe PLAGNIOL-VILLARD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#endif + +int arch_cpu_init(void) +{ + return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); +} diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S new file mode 100644 index 00000000000..d2934a3525a --- /dev/null +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -0,0 +1,152 @@ +/* + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Modified for the at91rm9200dk board by + * (C) Copyright 2004 + * Gary Jennejohn, DENX Software Engineering, + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + +#include +#include +#include +#include + +#define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */ + +_MTEXT_BASE: +#undef START_FROM_MEM +#ifdef START_FROM_MEM + .word CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1 +#else + .word CONFIG_SYS_TEXT_BASE +#endif + +.globl lowlevel_init +lowlevel_init: + ldr r1, =AT91_ASM_PMC_MOR + /* Main oscillator Enable register */ +#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR + ldr r0, =0x0000FF01 /* Enable main oscillator */ +#else + ldr r0, =0x0000FF00 /* Disable main oscillator */ +#endif + str r0, [r1] /*AT91C_CKGR_MOR] */ + /* Add loop to compensate Main Oscillator startup time */ + ldr r0, =0x00000010 +LoopOsc: + subs r0, r0, #1 + bhi LoopOsc + + /* memory control configuration */ + /* this isn't very elegant, but what the heck */ + ldr r0, =SMRDATA + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + ldr r2, =SMRDATAE + sub r2, r2, r1 +pllloop: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne pllloop + /* delay - this is all done by guess */ + ldr r0, =0x00010000 + /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */ +lock: + subs r0, r0, #1 + bhi lock + ldr r0, =SMRDATA1 + ldr r1, _MTEXT_BASE + sub r0, r0, r1 + ldr r2, =SMRDATA1E + sub r2, r2, r1 +sdinit: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne sdinit + + /* switch from FastBus to Asynchronous clock mode */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #ARM920T_CONTROL + mcr p15, 0, r0, c1, c0, 0 + + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word AT91_ASM_MC_EBI_CFG + .word CONFIG_SYS_EBI_CFGR_VAL + .word AT91_ASM_MC_SMC_CSR0 + .word CONFIG_SYS_SMC_CSR0_VAL + .word AT91_ASM_PMC_PLLAR + .word CONFIG_SYS_PLLAR_VAL + .word AT91_ASM_PMC_PLLBR + .word CONFIG_SYS_PLLBR_VAL + .word AT91_ASM_PMC_MCKR + .word CONFIG_SYS_MCKR_VAL +SMRDATAE: + /* here there's a delay */ +SMRDATA1: + .word AT91_ASM_PIOC_ASR + .word CONFIG_SYS_PIOC_ASR_VAL + .word AT91_ASM_PIOC_BSR + .word CONFIG_SYS_PIOC_BSR_VAL + .word AT91_ASM_PIOC_PDR + .word CONFIG_SYS_PIOC_PDR_VAL + .word AT91_ASM_MC_EBI_CSA + .word CONFIG_SYS_EBI_CSA_VAL + .word AT91_ASM_MC_SDRAMC_CR + .word CONFIG_SYS_SDRC_CR_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL1 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM1 + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_TR + .word CONFIG_SYS_SDRC_TR_VAL + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL + .word AT91_ASM_MC_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM + .word CONFIG_SYS_SDRAM_VAL +SMRDATA1E: + /* SMRDATA1 is 176 bytes long */ +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/mach-at91/arm920t/reset.c b/arch/arm/mach-at91/arm920t/reset.c new file mode 100644 index 00000000000..d47777a3678 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/reset.c @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +void __attribute__((weak)) board_reset(void) +{ + /* true empty function for defining weak symbol */ +} + +void reset_cpu(ulong ignored) +{ + at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST; + + board_reset(); + + /* Reset the cpu by setting up the watchdog timer */ + writel(AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN | AT91_ST_WDMR_WDV(2), + &st->wdmr); + writel(AT91_ST_CR_WDRST, &st->cr); + /* and let it timeout */ + while (1) + ; + /* Never reached */ +} diff --git a/arch/arm/mach-at91/arm920t/timer.c b/arch/arm/mach-at91/arm920t/timer.c new file mode 100644 index 00000000000..6aa29947231 --- /dev/null +++ b/arch/arm/mach-at91/arm920t/timer.c @@ -0,0 +1,127 @@ +/* + * (C) Copyright 2002 + * Lineo, Inc. + * Bernhard Kuhn + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Marius Groeger + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH + * Alex Zuepke + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +/* the number of clocks per CONFIG_SYS_HZ */ +#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ) + +int timer_init(void) +{ + at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + /* enables TC1.0 clock */ + writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */ + + writel(0, &tc->bcr); + writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE | + AT91_TC_BMR_TC2XC2S_NONE , &tc->bmr); + + writel(AT91_TC_CCR_CLKDIS, &tc->tc[0].ccr); + /* set to MCLK/2 and restart the timer + when the value in TC_RC is reached */ + writel(AT91_TC_CMR_TCCLKS_CLOCK1 | AT91_TC_CMR_CPCTRG, &tc->tc[0].cmr); + + writel(0xFFFFFFFF, &tc->tc[0].idr); /* disable interrupts */ + writel(TIMER_LOAD_VAL, &tc->tc[0].rc); + + writel(AT91_TC_CCR_SWTRG | AT91_TC_CCR_CLKEN, &tc->tc[0].ccr); + gd->arch.lastinc = 0; + gd->arch.tbl = 0; + + return 0; +} + +/* + * timer without interrupts + */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +void __udelay(unsigned long usec) +{ + udelay_masked(usec); +} + +ulong get_timer_raw(void) +{ + at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC; + u32 now; + + now = readl(&tc->tc[0].cv) & 0x0000ffff; + + if (now >= gd->arch.lastinc) { + /* normal mode */ + gd->arch.tbl += now - gd->arch.lastinc; + } else { + /* we have an overflow ... */ + gd->arch.tbl += now + TIMER_LOAD_VAL - gd->arch.lastinc; + } + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +ulong get_timer_masked(void) +{ + return get_timer_raw()/TIMER_LOAD_VAL; +} + +void udelay_masked(unsigned long usec) +{ + u32 tmo; + u32 endtime; + signed long diff; + + tmo = CONFIG_SYS_HZ_CLOCK / 1000; + tmo *= usec; + tmo /= 1000; + + endtime = get_timer_raw() + tmo; + + do { + u32 now = get_timer_raw(); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/mach-at91/arm926ejs/Makefile b/arch/arm/mach-at91/arm926ejs/Makefile new file mode 100644 index 00000000000..ddc323f6415 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/Makefile @@ -0,0 +1,28 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_AT91SAM9260) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9G20) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9XE) += at91sam9260_devices.o +obj-$(CONFIG_AT91SAM9261) += at91sam9261_devices.o +obj-$(CONFIG_AT91SAM9G10) += at91sam9261_devices.o +obj-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o +obj-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o +obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o +obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o +obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o +obj-$(CONFIG_AT91_EFLASH) += eflash.o +obj-$(CONFIG_AT91_LED) += led.o +obj-y += clock.o +obj-y += cpu.o +obj-y += reset.o +obj-y += timer.o + +ifndef CONFIG_SKIP_LOWLEVEL_INIT +obj-y += lowlevel_init.o +endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c new file mode 100644 index 00000000000..efb53d673f4 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c @@ -0,0 +1,245 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTC, 11, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_b_periph(AT91_PIO_PORTC, 16, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_b_periph(AT91_PIO_PORTC, 17, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTC, 11, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTC, 16, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTC, 17, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTB, 3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTC, 5, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_b_periph(AT91_PIO_PORTC, 4, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_b_periph(AT91_PIO_PORTC, 3, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTC, 5, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTC, 4, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); + } +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + /* Enable EMAC clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTA, 25, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 26, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ERXCK */ +#if defined(CONFIG_AT91SAM9260EK) || defined(CONFIG_AFEB9260) + /* + * use PA10, PA11 for ETX2, ETX3. + * PA23 and PA24 are for TWI EEPROM + */ + at91_set_b_periph(AT91_PIO_PORTA, 10, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 11, 0); /* ETX3 */ +#else + at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 24, 0); /* ETX3 */ +#if defined(CONFIG_AT91SAM9G20) + /* 9G20 BOOT ROM initializes those pins to multi-drive, undo that */ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 0); + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 0); +#endif +#endif + at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* ETXER */ +#endif +} +#endif + +#if defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + /* Enable mci clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_MCI, &pmc->pcer); + + at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */ +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_b_periph(AT91_PIO_PORTA, 1, 1); /* MCCDB */ + at91_set_b_periph(AT91_PIO_PORTA, 0, 1); /* MCDB0 */ + at91_set_b_periph(AT91_PIO_PORTA, 5, 1); /* MCDB1 */ + at91_set_b_periph(AT91_PIO_PORTA, 4, 1); /* MCDB2 */ + at91_set_b_periph(AT91_PIO_PORTA, 3, 1); /* MCDB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 1); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* MCDA3 */ +#endif +} +#endif + +void at91_sdram_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); + at91_set_a_periph(AT91_PIO_PORTC, 25, 0); + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); + at91_set_a_periph(AT91_PIO_PORTC, 31, 0); +} + +/* Platform data for the GPIOs */ +static const struct at91_port_platdata at91sam9260_plat[] = { + { ATMEL_BASE_PIOA, "PA" }, + { ATMEL_BASE_PIOB, "PB" }, + { ATMEL_BASE_PIOC, "PC" }, +}; + +U_BOOT_DEVICES(at91sam9260_gpios) = { + { "gpio_at91", &at91sam9260_plat[0] }, + { "gpio_at91", &at91sam9260_plat[1] }, + { "gpio_at91", &at91sam9260_plat[2] }, +}; diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c new file mode 100644 index 00000000000..a445c7507e2 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9261_devices.c @@ -0,0 +1,140 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_a_periph(AT91_PIO_PORTA, 4, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_a_periph(AT91_PIO_PORTA, 5, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTA, 4, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTA, 5, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTA, 6, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTB, 28, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTA, 24, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_b_periph(AT91_PIO_PORTA, 25, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTB, 28, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTA, 24, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTA, 25, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTA, 26, 1); + } +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c new file mode 100644 index 00000000000..6b51d5f355f --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9263_devices.c @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2009-2011 + * Daniel Gorsulowski + * esd electronic system design gmbh + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_b_periph(AT91_PIO_PORTA, 5, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_b_periph(AT91_PIO_PORTA, 4, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_b_periph(AT91_PIO_PORTB, 11, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTA, 5, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTA, 4, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTB, 11, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_a_periph(AT91_PIO_PORTB, 16, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_a_periph(AT91_PIO_PORTB, 18, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTB, 15, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTB, 16, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); + } +} +#endif + +#if defined(CONFIG_GENERIC_ATMEL_MCI) +void at91_mci_hw_init(void) +{ + /* Enable mci clock */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_MCI1, &pmc->pcer); + + at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */ + +#if defined(CONFIG_ATMEL_MCI_PORTB) + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* MCI1_CDB */ + at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* MCI1_DB0 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, PUP); /* MCI1_DB1 */ + at91_set_a_periph(AT91_PIO_PORTA, 24, PUP); /* MCI1_DB2 */ + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* MCI1_DB3 */ +#else + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* MCI1_CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 8, PUP); /* MCI1_DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, PUP); /* MCI1_DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, PUP); /* MCI1_DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, PUP); /* MCI1_DA3 */ +#endif +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTE, 21, 0); /* ETXCK_EREFCK */ + at91_set_b_periph(AT91_PIO_PORTC, 25, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTE, 25, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTE, 26, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTE, 27, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTE, 28, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTE, 23, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTE, 24, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTE, 30, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTE, 29, 0); /* EMDC */ + +#ifndef CONFIG_RMII + at91_set_a_periph(AT91_PIO_PORTE, 22, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTC, 26, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTC, 22, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTC, 24, 0); /* ETXER */ +#endif +} +#endif + +#ifdef CONFIG_USB_OHCI_NEW +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_pio_output(AT91_PIO_PORTA, 21, 0); + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); +} +#endif + +#ifdef CONFIG_AT91_CAN +void at91_can_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */ + + /* Enable clock */ + writel(1 << ATMEL_ID_CAN, &pmc->pcer); +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c new file mode 100644 index 00000000000..0e6c0da1bdd --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c @@ -0,0 +1,184 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTB, 3, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTB, 18, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_b_periph(AT91_PIO_PORTB, 19, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_b_periph(AT91_PIO_PORTD, 27, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTB, 18, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTB, 19, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTD, 27, 1); + } +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */ + at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */ + at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTB, 17, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTD, 28, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_a_periph(AT91_PIO_PORTD, 18, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_a_periph(AT91_PIO_PORTD, 19, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTB, 17, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTD, 28, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTD, 18, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTD, 19, 1); + } + +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* EMDC */ +#ifndef CONFIG_RMII + at91_set_b_periph(AT91_PIO_PORTA, 29, 0); /* ECRS */ + at91_set_b_periph(AT91_PIO_PORTA, 30, 0); /* ECOL */ + at91_set_b_periph(AT91_PIO_PORTA, 8, 0); /* ERX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 9, 0); /* ERX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 28, 0); /* ERXCK */ + at91_set_b_periph(AT91_PIO_PORTA, 6, 0); /* ETX2 */ + at91_set_b_periph(AT91_PIO_PORTA, 7, 0); /* ETX3 */ + at91_set_b_periph(AT91_PIO_PORTA, 27, 0); /* ETXER */ +#endif +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void at91_mci_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* MCI0 DA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */ + + /* Enable clock */ + writel(1 << ATMEL_ID_MCI0, &pmc->pcer); +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c new file mode 100644 index 00000000000..39f17a1e11e --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9n12_devices.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2013 Atmel Corporation + * Josh Wu + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +unsigned int has_lcdc() +{ + return 1; +} + +void at91_serial0_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_serial3_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */ + writel(1 << ATMEL_ID_USART3, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_pio_output(AT91_PIO_PORTA, 14, 1); + if (cs_mask & (1 << 1)) + at91_set_pio_output(AT91_PIO_PORTA, 7, 1); + if (cs_mask & (1 << 2)) + at91_set_pio_output(AT91_PIO_PORTA, 1, 1); + if (cs_mask & (1 << 3)) + at91_set_pio_output(AT91_PIO_PORTB, 3, 1); +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_pio_output(AT91_PIO_PORTA, 8, 1); + if (cs_mask & (1 << 1)) + at91_set_pio_output(AT91_PIO_PORTA, 0, 1); + if (cs_mask & (1 << 2)) + at91_set_pio_output(AT91_PIO_PORTA, 31, 1); + if (cs_mask & (1 << 3)) + at91_set_pio_output(AT91_PIO_PORTA, 30, 1); +} +#endif + +void at91_mci_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */ + + writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); +} + +#ifdef CONFIG_LCD +void at91_lcd_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 29, 0); /* LCDDEN */ + at91_set_a_periph(AT91_PIO_PORTC, 30, 0); /* LCDDOTCK */ + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD15 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c new file mode 100644 index 00000000000..0ec32c3ab9c --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9rl_devices.c @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +/* + * if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all + * peripheral pins. Good to have if hardware is soldered optionally + * or in case of SPI no slave is selected. Avoid lines to float + * needlessly. Use a short local PUP define. + * + * Due to errata "TXD floats when CTS is inactive" pullups are always + * on for TXD pins. + */ +#ifdef CONFIG_AT91_GPIO_PULLUP +# define PUP CONFIG_AT91_GPIO_PULLUP +#else +# define PUP 0 +#endif + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, PUP); /* RXD0 */ + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, PUP); /* RXD1 */ + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, PUP); /* RXD2 */ + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 21, PUP); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 25, PUP); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 26, PUP); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI, &pmc->pcer); + + if (cs_mask & (1 << 0)) { + at91_set_a_periph(AT91_PIO_PORTA, 28, 1); + } + if (cs_mask & (1 << 1)) { + at91_set_b_periph(AT91_PIO_PORTB, 7, 1); + } + if (cs_mask & (1 << 2)) { + at91_set_a_periph(AT91_PIO_PORTD, 8, 1); + } + if (cs_mask & (1 << 3)) { + at91_set_b_periph(AT91_PIO_PORTD, 9, 1); + } + if (cs_mask & (1 << 4)) { + at91_set_pio_output(AT91_PIO_PORTA, 28, 1); + } + if (cs_mask & (1 << 5)) { + at91_set_pio_output(AT91_PIO_PORTB, 7, 1); + } + if (cs_mask & (1 << 6)) { + at91_set_pio_output(AT91_PIO_PORTD, 8, 1); + } + if (cs_mask & (1 << 7)) { + at91_set_pio_output(AT91_PIO_PORTD, 9, 1); + } +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c new file mode 100644 index 00000000000..6d94572237c --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/at91sam9x5_devices.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2012 Atmel Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +unsigned int get_chip_id(void) +{ + /* The 0x40 is the offset of cidr in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK; +} + +unsigned int get_extension_chip_id(void) +{ + /* The 0x44 is the offset of exid in DBGU */ + return readl(ATMEL_BASE_DBGU + 0x44); +} + +unsigned int has_emac1() +{ + return cpu_is_at91sam9x25(); +} + +unsigned int has_emac0() +{ + return !(cpu_is_at91sam9g15()); +} + +unsigned int has_lcdc() +{ + return cpu_is_at91sam9g15() || cpu_is_at91sam9g35() + || cpu_is_at91sam9x35(); +} + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_at91sam9x5()) { + switch (extension_id) { + case ARCH_EXID_AT91SAM9G15: + return "AT91SAM9G15"; + case ARCH_EXID_AT91SAM9G25: + return "AT91SAM9G25"; + case ARCH_EXID_AT91SAM9G35: + return "AT91SAM9G35"; + case ARCH_EXID_AT91SAM9X25: + return "AT91SAM9X25"; + case ARCH_EXID_AT91SAM9X35: + return "AT91SAM9X35"; + default: + return "Unknown CPU type"; + } + } else { + return "Unknown CPU type"; + } +} + +void at91_seriald_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ + + writel(1 << ATMEL_ID_SYS, &pmc->pcer); +} + +void at91_serial0_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART0, &pmc->pcer); +} + +void at91_serial1_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART1, &pmc->pcer); +} + +void at91_serial2_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD */ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD */ + + writel(1 << ATMEL_ID_USART2, &pmc->pcer); +} + +void at91_mci_hw_init(void) +{ + /* Initialize the MCI0 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* MCCK */ + at91_set_a_periph(AT91_PIO_PORTA, 16, 1); /* MCCDA */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 1); /* MCDA0 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 1); /* MCDA1 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 1); /* MCDA2 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 1); /* MCDA3 */ + + /* Enable clock for MCI0 */ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer); +} + +#ifdef CONFIG_ATMEL_SPI +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); + if (cs_mask & (1 << 1)) + at91_set_b_periph(AT91_PIO_PORTA, 7, 0); + if (cs_mask & (1 << 2)) + at91_set_b_periph(AT91_PIO_PORTA, 1, 0); + if (cs_mask & (1 << 3)) + at91_set_b_periph(AT91_PIO_PORTB, 3, 0); + if (cs_mask & (1 << 4)) + at91_set_pio_output(AT91_PIO_PORTA, 14, 0); + if (cs_mask & (1 << 5)) + at91_set_pio_output(AT91_PIO_PORTA, 7, 0); + if (cs_mask & (1 << 6)) + at91_set_pio_output(AT91_PIO_PORTA, 1, 0); + if (cs_mask & (1 << 7)) + at91_set_pio_output(AT91_PIO_PORTB, 3, 0); +} + +void at91_spi1_hw_init(unsigned long cs_mask) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */ + at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */ + at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */ + + /* Enable clock */ + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); + + if (cs_mask & (1 << 0)) + at91_set_b_periph(AT91_PIO_PORTA, 8, 0); + if (cs_mask & (1 << 1)) + at91_set_b_periph(AT91_PIO_PORTA, 0, 0); + if (cs_mask & (1 << 2)) + at91_set_b_periph(AT91_PIO_PORTA, 31, 0); + if (cs_mask & (1 << 3)) + at91_set_b_periph(AT91_PIO_PORTA, 30, 0); + if (cs_mask & (1 << 4)) + at91_set_pio_output(AT91_PIO_PORTA, 8, 0); + if (cs_mask & (1 << 5)) + at91_set_pio_output(AT91_PIO_PORTA, 0, 0); + if (cs_mask & (1 << 6)) + at91_set_pio_output(AT91_PIO_PORTA, 31, 0); + if (cs_mask & (1 << 7)) + at91_set_pio_output(AT91_PIO_PORTA, 30, 0); +} +#endif + +#if defined(CONFIG_USB_OHCI_NEW) || defined(CONFIG_USB_EHCI) +void at91_uhp_hw_init(void) +{ + /* Enable VBus on UHP ports */ + at91_set_pio_output(AT91_PIO_PORTD, 18, 0); /* port A */ + at91_set_pio_output(AT91_PIO_PORTD, 19, 0); /* port B */ +#if defined(CONFIG_USB_OHCI_NEW) + /* port C is OHCI only */ + at91_set_pio_output(AT91_PIO_PORTD, 20, 0); /* port C */ +#endif +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + if (has_emac0()) { + /* Enable EMAC0 clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + /* EMAC0 pins setup */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */ + } + + if (has_emac1()) { + /* Enable EMAC1 clock */ + writel(1 << ATMEL_ID_EMAC1, &pmc->pcer); + /* EMAC1 pins setup */ + at91_set_b_periph(AT91_PIO_PORTC, 29, 0); /* ETXCK */ + at91_set_b_periph(AT91_PIO_PORTC, 28, 0); /* ECRSDV */ + at91_set_b_periph(AT91_PIO_PORTC, 20, 0); /* ERXO */ + at91_set_b_periph(AT91_PIO_PORTC, 21, 0); /* ERX1 */ + at91_set_b_periph(AT91_PIO_PORTC, 16, 0); /* ERXER */ + at91_set_b_periph(AT91_PIO_PORTC, 27, 0); /* ETXEN */ + at91_set_b_periph(AT91_PIO_PORTC, 18, 0); /* ETX0 */ + at91_set_b_periph(AT91_PIO_PORTC, 19, 0); /* ETX1 */ + at91_set_b_periph(AT91_PIO_PORTC, 31, 0); /* EMDIO */ + at91_set_b_periph(AT91_PIO_PORTC, 30, 0); /* EMDC */ + } + +#ifndef CONFIG_RMII + /* Only emac0 support MII */ + if (has_emac0()) { + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* ECRS */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* ECOL */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ERX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* ERX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* ERXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* ETX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ETXER */ + } +#endif +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/clock.c b/arch/arm/mach-at91/arm926ejs/clock.c new file mode 100644 index 00000000000..f363982d035 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/clock.c @@ -0,0 +1,249 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_MCKR_CSS_SLOW: + return CONFIG_SYS_AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return gd->arch.main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return gd->arch.plla_rate_hz; + case AT91_PMC_MCKR_CSS_PLLB: + return gd->arch.pllb_rate_hz; + } + + return 0; +} + +#ifdef CONFIG_USB_ATMEL +static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq) +{ + unsigned i, div = 0, mul = 0, diff = 1 << 30; + unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00; + + /* PLL output max 240 MHz (or 180 MHz per errata) */ + if (out_freq > 240000000) + goto fail; + + for (i = 1; i < 256; i++) { + int diff1; + unsigned input, mul1; + + /* + * PLL input between 1MHz and 32MHz per spec, but lower + * frequences seem necessary in some cases so allow 100K. + * Warning: some newer products need 2MHz min. + */ + input = main_freq / i; +#if defined(CONFIG_AT91SAM9G20) + if (input < 2000000) + continue; +#endif + if (input < 100000) + continue; + if (input > 32000000) + continue; + + mul1 = out_freq / input; +#if defined(CONFIG_AT91SAM9G20) + if (mul > 63) + continue; +#endif + if (mul1 > 2048) + continue; + if (mul1 < 2) + goto fail; + + diff1 = out_freq - input * mul1; + if (diff1 < 0) + diff1 = -diff1; + if (diff > diff1) { + diff = diff1; + div = i; + mul = mul1; + if (diff == 0) + break; + } + } + if (i == 256 && diff > (out_freq >> 5)) + goto fail; + return ret | ((mul - 1) << 16) | div; +fail: + return 0; +} +#endif + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 16) & 0x7ff; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else + freq = 0; + + return freq; +} + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + } +#endif + gd->arch.main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + +#ifdef CONFIG_USB_ATMEL + /* + * USB clock init: choose 48 MHz PLLB value, + * disable 48MHz clock during usb peripheral suspend. + * + * REVISIT: assumes MCK doesn't derive from PLLB! + */ + gd->arch.at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | + AT91_PMC_PLLBR_USBDIV_2; + gd->arch.pllb_rate_hz = at91_pll_rate(main_clock, + gd->arch.at91_pllb_usb_init); +#endif + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(&pmc->mckr); +#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) + /* plla divisor by 2 */ + gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); +#endif + gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = gd->arch.mck_rate_hz; + + freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ +#if defined(CONFIG_AT91SAM9G20) + /* mdiv ; (x >> 7) = ((x >> 8) * 2) */ + gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? + freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; + if (mckr & AT91_PMC_MCKR_MDIV_MASK) + freq /= 2; /* processor clock division */ +#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) \ + || defined(CONFIG_AT91SAM9N12) || defined(CONFIG_AT91SAM9X5) + /* mdiv <==> divisor + * 0 <==> 1 + * 1 <==> 2 + * 2 <==> 4 + * 3 <==> 3 + */ + gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == + (AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4) + ? freq / 3 + : freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); +#else + gd->arch.mck_rate_hz = freq / + (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); +#endif + gd->arch.cpu_clk_rate_hz = freq; + + return 0; +} + +#if !defined(AT91_PLL_LOCK_TIMEOUT) +#define AT91_PLL_LOCK_TIMEOUT 1000000 +#endif + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} +void at91_pllb_init(u32 pllbr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + + writel(pllbr, &pmc->pllbr); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKB | AT91_PMC_MCKRDY))) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + int timeout = AT91_PLL_LOCK_TIMEOUT; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + tmp |= mckr & (AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_MASK | + AT91_PMC_MCKR_CSS_MASK); + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) { + timeout--; + if (timeout == 0) + break; + } +} + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(1 << id, &pmc->pcer); +} diff --git a/arch/arm/mach-at91/arm926ejs/cpu.c b/arch/arm/mach-at91/arm926ejs/cpu.c new file mode 100644 index 00000000000..da1d35907e9 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/cpu.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * (C) Copyright 2009 + * Jean-Christophe PLAGNIOL-VILLARD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#endif + +int arch_cpu_init(void) +{ + return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); +} + +void arch_preboot_os(void) +{ + ulong cpiv; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + + cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); + + /* + * Disable PITC + * Add 0x1000 to current counter to stop it faster + * without waiting for wrapping back to 0 + */ + writel(cpiv + 0x1000, &pit->mr); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU: %s\n", ATMEL_CPU_NAME); + printf("Crystal frequency: %8s MHz\n", + strmhz(buf, get_main_clk_rate())); + printf("CPU clock : %8s MHz\n", + strmhz(buf, get_cpu_clk_rate())); + printf("Master clock : %8s MHz\n", + strmhz(buf, get_mck_clk_rate())); + + return 0; +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/eflash.c b/arch/arm/mach-at91/arm926ejs/eflash.c new file mode 100644 index 00000000000..3f392642891 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/eflash.c @@ -0,0 +1,254 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * this driver supports the enhanced embedded flash in the Atmel + * AT91SAM9XE devices with the following geometry: + * + * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) + * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) + * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) + * (the exact geometry is read from the flash at runtime, so any + * future devices should already be covered) + * + * Regions can be write/erase protected. + * Whole (!) pages can be individually written with erase on the fly. + * Writing partial pages will corrupt the rest of the page. + * + * The flash is presented to u-boot with each region being a sector, + * having the following effects: + * Each sector can be hardware protected (protect on/off). + * Each page in a sector can be rewritten anytime. + * Since pages are erased when written, the "erase" does nothing. + * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected + * by u-Boot commands. + * + * Note: Redundant environment will not work in this flash since + * it does use partial page writes. Make sure the environment spans + * whole pages! + */ + +/* + * optional TODOs (nice to have features): + * + * make the driver coexist with other NOR flash drivers + * (use an index into flash_info[], requires work + * in those other drivers, too) + * Make the erase command fill the sectors with 0xff + * (if the flashes grow larger in the future and + * someone puts a jffs2 into them) + * do a read-modify-write for partially programmed pages + */ +#include +#include +#include +#include +#include +#include + +/* checks to detect configuration errors */ +#if CONFIG_SYS_MAX_FLASH_BANKS!=1 +#error eflash: this driver can only handle 1 bank +#endif + +/* global structure */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static u32 pagesize; + +unsigned long flash_init (void) +{ + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + at91_dbu_t *dbu = (at91_dbu_t *) ATMEL_BASE_DBGU; + u32 id, size, nplanes, planesize, nlocks; + u32 addr, i, tmp=0; + + debug("eflash: init\n"); + + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* check if its an AT91ARM9XE SoC */ + if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { + puts("eflash: not an AT91SAM9XE\n"); + return 0; + } + + /* now query the eflash for its structure */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + id = readl(&eefc->frr); /* word 0 */ + size = readl(&eefc->frr); /* word 1 */ + pagesize = readl(&eefc->frr); /* word 2 */ + nplanes = readl(&eefc->frr); /* word 3 */ + planesize = readl(&eefc->frr); /* word 4 */ + debug("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", + id, size, pagesize, nplanes, planesize); + for (i=1; ifrr); /* words 5..4+nplanes-1 */ + }; + nlocks = readl(&eefc->frr); /* word 4+nplanes */ + debug("nlocks=%u\n", nlocks); + /* since we are going to use the lock regions as sectors, check count */ + if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { + printf("eflash: number of lock regions(%u) "\ + "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", + nlocks); + nlocks = CONFIG_SYS_MAX_FLASH_SECT; + } + flash_info[0].size = size; + flash_info[0].sector_count = nlocks; + flash_info[0].flash_id = id; + + addr = ATMEL_BASE_FLASH; + for (i=0; ifrr); /* words 4+nplanes+1.. */ + flash_info[0].start[i] = addr; + flash_info[0].protect[i] = 0; + addr += tmp; + }; + + /* now read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; ifrr); + flash_info[0].protect[i] = (tmp >> (i%32)) & 1; +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (i < CONFIG_EFLASH_PROTSECTORS) + flash_info[0].protect[i] = 1; +#endif + } + + return size; +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + puts("AT91SAM9XE embedded flash\n Size: "); + print_size(info->size, " in "); + printf("%d Sectors\n", info->sector_count); + + printf(" Sector Start Addresses:"); + for (i=0; isector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +int flash_real_protect (flash_info_t *info, long sector, int prot) +{ + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + u32 pagenum = (info->start[sector]-ATMEL_BASE_FLASH)/pagesize; + u32 i, tmp=0; + + debug("protect sector=%ld prot=%d\n", sector, prot); + +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (sector < CONFIG_EFLASH_PROTSECTORS) { + if (!prot) { + printf("eflash: sector %lu cannot be unprotected\n", + sector); + } + return 1; /* return anyway, caller does not care for result */ + } +#endif + if (prot) { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } else { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* now re-read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; isector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + info->protect[i] = (tmp >> (i%32)) & 1; + } + return 0; +} + +static u32 erase_write_page (u32 pagenum) +{ + at91_eefc_t *eefc = (at91_eefc_t *) ATMEL_BASE_EEFC; + + debug("erase+write page=%u\n", pagenum); + + /* give erase and write page command */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* return status */ + return readl(&eefc->fsr) + & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + debug("erase first=%d last=%d\n", s_first, s_last); + puts("this flash does not need and support erasing!\n"); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + u32 pagenum; + u32 *src32, *dst32; + u32 i; + + debug("write src=%08lx addr=%08lx cnt=%lx\n", + (ulong)src, addr, cnt); + + /* REQUIRE addr to be on a page start, abort if not */ + if (addr % pagesize) { + printf ("eflash: start %08lx is not on page start\n"\ + " write aborted\n", addr); + return 1; + } + + /* now start copying data */ + pagenum = (addr-ATMEL_BASE_FLASH)/pagesize; + src32 = (u32 *) src; + dst32 = (u32 *) addr; + while (cnt > 0) { + i = pagesize / 4; + /* fill page buffer */ + while (i--) + *dst32++ = *src32++; + /* write page */ + if (erase_write_page(pagenum)) + return 1; + pagenum++; + if (cnt > pagesize) + cnt -= pagesize; + else + cnt = 0; + } + return 0; +} diff --git a/arch/arm/mach-at91/arm926ejs/led.c b/arch/arm/mach-at91/arm926ejs/led.c new file mode 100644 index 00000000000..b8d5c785df4 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/led.c @@ -0,0 +1,48 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +#ifdef CONFIG_RED_LED +void red_led_on(void) +{ + gpio_set_value(CONFIG_RED_LED, 1); +} + +void red_led_off(void) +{ + gpio_set_value(CONFIG_RED_LED, 0); +} +#endif + +#ifdef CONFIG_GREEN_LED +void green_led_on(void) +{ + gpio_set_value(CONFIG_GREEN_LED, 0); +} + +void green_led_off(void) +{ + gpio_set_value(CONFIG_GREEN_LED, 1); +} +#endif + +#ifdef CONFIG_YELLOW_LED +void yellow_led_on(void) +{ + gpio_set_value(CONFIG_YELLOW_LED, 0); +} + +void yellow_led_off(void) +{ + gpio_set_value(CONFIG_YELLOW_LED, 1); +} +#endif diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S new file mode 100644 index 00000000000..a9ec81a75c8 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -0,0 +1,246 @@ +/* + * Memory Setup stuff - taken from blob memsetup.S + * + * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and + * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) + * + * Copyright (C) 2008 Ronetix Ilko Iliev (www.ronetix.at) + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifdef CONFIG_ATMEL_LEGACY +#include +#endif +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL +#endif + +.globl lowlevel_init +.type lowlevel_init,function +lowlevel_init: + +POS1: + adr r5, POS1 /* r5 = POS1 run time */ + ldr r0, =POS1 /* r0 = POS1 compile */ + sub r5, r5, r0 /* r0 = CONFIG_SYS_TEXT_BASE-1 */ + + /* memory control configuration 1 */ + ldr r0, =SMRDATA + ldr r2, =SMRDATA1 + add r0, r0, r5 + add r2, r2, r5 +0: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 0b + +/* ---------------------------------------------------------------------------- + * PMC Init Step 1. + * ---------------------------------------------------------------------------- + * - Check if the PLL is already initialized + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_ASM_PMC_MCKR) + ldr r0, [r1] + and r0, r0, #3 + cmp r0, #0 + bne PLL_setup_end + +/* --------------------------------------------------------------------------- + * - Enable the Main Oscillator + * --------------------------------------------------------------------------- + */ + ldr r1, =(AT91_ASM_PMC_MOR) + ldr r2, =(AT91_ASM_PMC_SR) + /* Main oscillator Enable register PMC_MOR: */ + ldr r0, =CONFIG_SYS_MOR_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Main Oscillator is enabled */ + mov r4, #AT91_PMC_IXR_MOSCS +MOSCS_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IXR_MOSCS + bne MOSCS_Loop + +/* ---------------------------------------------------------------------------- + * PMC Init Step 2. + * ---------------------------------------------------------------------------- + * Setup PLLA + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_ASM_PMC_PLLAR) + ldr r0, =CONFIG_SYS_PLLAR_VAL + str r0, [r1] + + /* Reading the PMC Status register to detect when the PLLA is locked */ + mov r4, #AT91_PMC_IXR_LOCKA +MOSCS_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IXR_LOCKA + bne MOSCS_Loop1 + +/* ---------------------------------------------------------------------------- + * PMC Init Step 3. + * ---------------------------------------------------------------------------- + * - Switch on the Main Oscillator + * ---------------------------------------------------------------------------- + */ + ldr r1, =(AT91_ASM_PMC_MCKR) + + /* -Master Clock Controller register PMC_MCKR */ + ldr r0, =CONFIG_SYS_MCKR1_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_IXR_MCKRDY +MCKRDY_Loop: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IXR_MCKRDY + bne MCKRDY_Loop + + ldr r0, =CONFIG_SYS_MCKR2_VAL + str r0, [r1] + + /* Reading the PMC Status to detect when the Master clock is ready */ + mov r4, #AT91_PMC_IXR_MCKRDY +MCKRDY_Loop1: + ldr r3, [r2] + and r3, r4, r3 + cmp r3, #AT91_PMC_IXR_MCKRDY + bne MCKRDY_Loop1 +PLL_setup_end: + +/* ---------------------------------------------------------------------------- + * - memory control configuration 2 + * ---------------------------------------------------------------------------- + */ + ldr r0, =(AT91_ASM_SDRAMC_TR) + ldr r1, [r0] + cmp r1, #0 + bne SDRAM_setup_end + + ldr r0, =SMRDATA1 + ldr r2, =SMRDATA2 + add r0, r0, r5 + add r2, r2, r5 +2: + /* the address */ + ldr r1, [r0], #4 + /* the value */ + ldr r3, [r0], #4 + str r3, [r1] + cmp r2, r0 + bne 2b + +SDRAM_setup_end: + /* everything is fine now */ + mov pc, lr + + .ltorg + +SMRDATA: + .word AT91_ASM_WDT_MR + .word CONFIG_SYS_WDTC_WDMR_VAL + /* configure PIOx as EBI0 D[16-31] */ +#if defined(CONFIG_AT91SAM9263) + .word AT91_ASM_PIOD_PDR + .word CONFIG_SYS_PIOD_PDR_VAL1 + .word AT91_ASM_PIOD_PUDR + .word CONFIG_SYS_PIOD_PPUDR_VAL + .word AT91_ASM_PIOD_ASR + .word CONFIG_SYS_PIOD_PPUDR_VAL +#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9261) \ + || defined(CONFIG_AT91SAM9G20) + .word AT91_ASM_PIOC_PDR + .word CONFIG_SYS_PIOC_PDR_VAL1 + .word AT91_ASM_PIOC_PUDR + .word CONFIG_SYS_PIOC_PPUDR_VAL +#endif + .word AT91_ASM_MATRIX_CSA0 + .word CONFIG_SYS_MATRIX_EBICSA_VAL + + /* flash */ + .word AT91_ASM_SMC_MODE0 + .word CONFIG_SYS_SMC0_MODE0_VAL + + .word AT91_ASM_SMC_CYCLE0 + .word CONFIG_SYS_SMC0_CYCLE0_VAL + + .word AT91_ASM_SMC_PULSE0 + .word CONFIG_SYS_SMC0_PULSE0_VAL + + .word AT91_ASM_SMC_SETUP0 + .word CONFIG_SYS_SMC0_SETUP0_VAL + +SMRDATA1: + .word AT91_ASM_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL1 + .word AT91_ASM_SDRAMC_TR + .word CONFIG_SYS_SDRC_TR_VAL1 + .word AT91_ASM_SDRAMC_CR + .word CONFIG_SYS_SDRC_CR_VAL + .word AT91_ASM_SDRAMC_MDR + .word CONFIG_SYS_SDRC_MDR_VAL + .word AT91_ASM_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL2 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL1 + .word AT91_ASM_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL3 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL2 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL3 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL4 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL5 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL6 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL7 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL8 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL9 + .word AT91_ASM_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL4 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL10 + .word AT91_ASM_SDRAMC_MR + .word CONFIG_SYS_SDRC_MR_VAL5 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL11 + .word AT91_ASM_SDRAMC_TR + .word CONFIG_SYS_SDRC_TR_VAL2 + .word CONFIG_SYS_SDRAM_BASE + .word CONFIG_SYS_SDRAM_VAL12 + /* User reset enable*/ + .word AT91_ASM_RSTC_MR + .word CONFIG_SYS_RSTC_RMR_VAL +#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP + /* MATRIX_MCFG - REMAP all masters */ + .word AT91_ASM_MATRIX_MCFG + .word 0x1FF +#endif +SMRDATA2: + .word 0 diff --git a/arch/arm/mach-at91/arm926ejs/reset.c b/arch/arm/mach-at91/arm926ejs/reset.c new file mode 100644 index 00000000000..e67f47bd041 --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/reset.c @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* Reset the cpu by telling the reset controller to do so */ +void reset_cpu(ulong ignored) +{ + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY + | AT91_RSTC_CR_PROCRST /* Processor Reset */ + | AT91_RSTC_CR_PERRST /* Peripheral Reset */ +#ifdef CONFIG_AT91RESET_EXTRST + | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ +#endif + , &rstc->cr); + /* never reached */ + while (1) + ; +} diff --git a/arch/arm/mach-at91/arm926ejs/timer.c b/arch/arm/mach-at91/arm926ejs/timer.c new file mode 100644 index 00000000000..b0b7fb93fba --- /dev/null +++ b/arch/arm/mach-at91/arm926ejs/timer.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by + * setting the 20 bit counter period to its maximum (0xfffff). + * (See the relevant data sheets to understand that this really works) + * + * We do also mimic the typical powerpc way of incrementing + * two 32 bit registers called tbl and tbu. + * + * Those registers increment at 1/16 the main clock rate. + */ + +#define TIMER_LOAD_VAL 0xfffff + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, gd->arch.timer_rate_hz); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= gd->arch.timer_rate_hz; + do_div(usec, 1000000); + + return usec; +} + +/* + * Use the PITC in full 32 bit incrementing mode + */ +int timer_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + + /* Enable PITC Clock */ + writel(1 << ATMEL_ID_SYS, &pmc->pcer); + + /* Enable PITC */ + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); + + gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; + gd->arch.tbu = gd->arch.tbl = 0; + + return 0; +} + +/* + * Get the current 64 bit timer tick count + */ +unsigned long long get_ticks(void) +{ + at91_pit_t *pit = (at91_pit_t *) ATMEL_BASE_PIT; + + ulong now = readl(&pit->piir); + + /* increment tbu if tbl has rolled over */ + if (now < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl = now; + return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; +} + +void __udelay(unsigned long usec) +{ + unsigned long long start; + ulong tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = usec_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ +} + +/* + * get_timer(base) can be used to check for timeouts or + * to measure elasped time relative to an event: + * + * ulong start_time = get_timer(0) sets start_time to the current + * time value. + * get_timer(start_time) returns the time elapsed since then. + * + * The time is used in CONFIG_SYS_HZ units! + */ +ulong get_timer(ulong base) +{ + return tick_to_time(get_ticks()) - base; +} + +/* + * Return the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} diff --git a/arch/arm/mach-at91/armv7/Makefile b/arch/arm/mach-at91/armv7/Makefile new file mode 100644 index 00000000000..f4f35a4bc19 --- /dev/null +++ b/arch/arm/mach-at91/armv7/Makefile @@ -0,0 +1,16 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# (C) Copyright 2013 +# Bo Shen +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_SAMA5D3) += sama5d3_devices.o +obj-$(CONFIG_SAMA5D4) += sama5d4_devices.o +obj-y += clock.o +obj-y += cpu.o +obj-y += reset.o +obj-y += timer.o diff --git a/arch/arm/mach-at91/armv7/clock.c b/arch/arm/mach-at91/armv7/clock.c new file mode 100644 index 00000000000..0bf453eff57 --- /dev/null +++ b/arch/arm/mach-at91/armv7/clock.c @@ -0,0 +1,175 @@ +/* + * [origin: Linux kernel linux/arch/arm/mach-at91/clock.c] + * + * Copyright (C) 2005 David Brownell + * Copyright (C) 2005 Ivan Kokshaysky + * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD + * Copyright (C) 2013 Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned long at91_css_to_rate(unsigned long css) +{ + switch (css) { + case AT91_PMC_MCKR_CSS_SLOW: + return CONFIG_SYS_AT91_SLOW_CLOCK; + case AT91_PMC_MCKR_CSS_MAIN: + return gd->arch.main_clk_rate_hz; + case AT91_PMC_MCKR_CSS_PLLA: + return gd->arch.plla_rate_hz; + } + + return 0; +} + +static u32 at91_pll_rate(u32 freq, u32 reg) +{ + unsigned mul, div; + + div = reg & 0xff; + mul = (reg >> 18) & 0x7f; + if (div && mul) { + freq /= div; + freq *= mul + 1; + } else { + freq = 0; + } + + return freq; +} + +int at91_clock_init(unsigned long main_clock) +{ + unsigned freq, mckr; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK + unsigned tmp; + /* + * When the bootloader initialized the main oscillator correctly, + * there's no problem using the cycle counter. But if it didn't, + * or when using oscillator bypass mode, we must be told the speed + * of the main clock. + */ + if (!main_clock) { + do { + tmp = readl(&pmc->mcfr); + } while (!(tmp & AT91_PMC_MCFR_MAINRDY)); + tmp &= AT91_PMC_MCFR_MAINF_MASK; + main_clock = tmp * (CONFIG_SYS_AT91_SLOW_CLOCK / 16); + } +#endif + gd->arch.main_clk_rate_hz = main_clock; + + /* report if PLLA is more than mildly overclocked */ + gd->arch.plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar)); + + /* + * MCK and CPU derive from one of those primary clocks. + * For now, assume this parentage won't change. + */ + mckr = readl(&pmc->mckr); + + /* plla divisor by 2 */ + if (mckr & (1 << 12)) + gd->arch.plla_rate_hz >>= 1; + + gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); + freq = gd->arch.mck_rate_hz; + + /* prescale */ + freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; + + switch (mckr & AT91_PMC_MCKR_MDIV_MASK) { + case AT91_PMC_MCKR_MDIV_2: + gd->arch.mck_rate_hz = freq / 2; + break; + case AT91_PMC_MCKR_MDIV_3: + gd->arch.mck_rate_hz = freq / 3; + break; + case AT91_PMC_MCKR_MDIV_4: + gd->arch.mck_rate_hz = freq / 4; + break; + default: + break; + } + + gd->arch.cpu_clk_rate_hz = freq; + + return 0; +} + +void at91_plla_init(u32 pllar) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + writel(pllar, &pmc->pllar); + while (!(readl(&pmc->sr) & (AT91_PMC_LOCKA | AT91_PMC_MCKRDY))) + ; +} + +void at91_mck_init(u32 mckr) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~(AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); +#ifdef CPU_HAS_H32MXDIV + tmp &= ~AT91_PMC_MCKR_H32MXDIV; +#endif + + tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | + AT91_PMC_MCKR_PRES_MASK | + AT91_PMC_MCKR_MDIV_MASK | + AT91_PMC_MCKR_PLLADIV_2); +#ifdef CPU_HAS_H32MXDIV + tmp |= mckr & AT91_PMC_MCKR_H32MXDIV; +#endif + + writel(tmp, &pmc->mckr); + + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; +} + +void at91_periph_clk_enable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id; + + writel(regval, &pmc->pcr); +} + +void at91_periph_clk_disable(int id) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 regval; + + if (id > AT91_PMC_PCR_PID_MASK) + return; + + regval = AT91_PMC_PCR_CMD_WRITE | id; + + writel(regval, &pmc->pcr); +} diff --git a/arch/arm/mach-at91/armv7/cpu.c b/arch/arm/mach-at91/armv7/cpu.c new file mode 100644 index 00000000000..8d86f97e3da --- /dev/null +++ b/arch/arm/mach-at91/armv7/cpu.c @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, reinhard.meyer@emk-elektronik.de + * (C) Copyright 2009 + * Jean-Christophe PLAGNIOL-VILLARD + * (C) Copyright 2013 + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 0 +#endif + +int arch_cpu_init(void) +{ + return at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); +} + +void arch_preboot_os(void) +{ + ulong cpiv; + at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; + + cpiv = AT91_PIT_MR_PIV_MASK(readl(&pit->piir)); + + /* + * Disable PITC + * Add 0x1000 to current counter to stop it faster + * without waiting for wrapping back to 0 + */ + writel(cpiv + 0x1000, &pit->mr); +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +int print_cpuinfo(void) +{ + char buf[32]; + + printf("CPU: %s\n", get_cpu_name()); + printf("Crystal frequency: %8s MHz\n", + strmhz(buf, get_main_clk_rate())); + printf("CPU clock : %8s MHz\n", + strmhz(buf, get_cpu_clk_rate())); + printf("Master clock : %8s MHz\n", + strmhz(buf, get_mck_clk_rate())); + + return 0; +} +#endif + +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + +unsigned int get_chip_id(void) +{ + return readl(ATMEL_BASE_DBGU + AT91_DBU_CIDR) & ~AT91_DBU_CIDR_MASK; +} + +unsigned int get_extension_chip_id(void) +{ + return readl(ATMEL_BASE_DBGU + AT91_DBU_EXID); +} diff --git a/arch/arm/mach-at91/armv7/reset.c b/arch/arm/mach-at91/armv7/reset.c new file mode 100644 index 00000000000..b30e79b60ad --- /dev/null +++ b/arch/arm/mach-at91/armv7/reset.c @@ -0,0 +1,31 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2013 + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +/* Reset the cpu by telling the reset controller to do so */ +void reset_cpu(ulong ignored) +{ + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY + | AT91_RSTC_CR_PROCRST /* Processor Reset */ + | AT91_RSTC_CR_PERRST /* Peripheral Reset */ +#ifdef CONFIG_AT91RESET_EXTRST + | AT91_RSTC_CR_EXTRST /* External Reset (assert nRST pin) */ +#endif + , &rstc->cr); + /* never reached */ + do { } while (1); +} diff --git a/arch/arm/mach-at91/armv7/sama5d3_devices.c b/arch/arm/mach-at91/armv7/sama5d3_devices.c new file mode 100644 index 00000000000..78ecfc882a8 --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama5d3_devices.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2012-2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +unsigned int has_emac() +{ + return cpu_is_sama5d31() || cpu_is_sama5d35() || cpu_is_sama5d36(); +} + +unsigned int has_gmac() +{ + return !cpu_is_sama5d31(); +} + +unsigned int has_lcdc() +{ + return !cpu_is_sama5d35(); +} + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d3()) + switch (extension_id) { + case ARCH_EXID_SAMA5D31: + return "SAMA5D31"; + case ARCH_EXID_SAMA5D33: + return "SAMA5D33"; + case ARCH_EXID_SAMA5D34: + return "SAMA5D34"; + case ARCH_EXID_SAMA5D35: + return "SAMA5D35"; + case ARCH_EXID_SAMA5D36: + return "SAMA5D36"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; +} + +void at91_serial0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 18, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTD, 17, 0); /* RXD0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART0); +} + +void at91_serial1_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 29, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTB, 28, 0); /* RXD1 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART1); +} + +void at91_serial2_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 26, 1); /* TXD2 */ + at91_set_b_periph(AT91_PIO_PORTE, 25, 0); /* RXD2 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART2); +} + +void at91_seriald_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 31, 1); /* DTXD */ + at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* DRXD */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_DBGU); +} + +#if defined(CONFIG_ATMEL_SPI) +void at91_spi0_hw_init(unsigned long cs_mask) +{ + at91_set_a_periph(AT91_PIO_PORTD, 10, 0); /* SPI0_MISO */ + at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* SPI0_MOSI */ + at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* SPI0_SPCK */ + + if (cs_mask & (1 << 0)) + at91_set_pio_output(AT91_PIO_PORTD, 13, 1); + if (cs_mask & (1 << 1)) + at91_set_pio_output(AT91_PIO_PORTD, 14, 1); + if (cs_mask & (1 << 2)) + at91_set_pio_output(AT91_PIO_PORTD, 15, 1); + if (cs_mask & (1 << 3)) + at91_set_pio_output(AT91_PIO_PORTD, 16, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_SPI0); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void at91_mci_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 0, 0); /* MCI0 CMD */ + at91_set_a_periph(AT91_PIO_PORTD, 1, 0); /* MCI0 DA0 */ + at91_set_a_periph(AT91_PIO_PORTD, 2, 0); /* MCI0 DA1 */ + at91_set_a_periph(AT91_PIO_PORTD, 3, 0); /* MCI0 DA2 */ + at91_set_a_periph(AT91_PIO_PORTD, 4, 0); /* MCI0 DA3 */ +#ifdef CONFIG_ATMEL_MCI_8BIT + at91_set_a_periph(AT91_PIO_PORTD, 5, 0); /* MCI0 DA4 */ + at91_set_a_periph(AT91_PIO_PORTD, 6, 0); /* MCI0 DA5 */ + at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* MCI0 DA6 */ + at91_set_a_periph(AT91_PIO_PORTD, 8, 0); /* MCI0 DA7 */ +#endif + at91_set_a_periph(AT91_PIO_PORTD, 9, 0); /* MCI0 CLK */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI0); +} +#endif + +#ifdef CONFIG_MACB +void at91_macb_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* EMDC */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_EMAC); +} + +void at91_gmac_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* GTX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* GTX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* GTX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 3, 0); /* GTX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 4, 0); /* GRX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* GRX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* GRX2 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* GRX3 */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* GTXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* GTXEN */ + + at91_set_a_periph(AT91_PIO_PORTB, 11, 0); /* GRXCK */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* GRXER */ + + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* GMDC */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* GMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* G125CK */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC); +} +#endif + +#ifdef CONFIG_LCD +void at91_lcd_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* LCDDISP */ + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + /* The lower 16-bit of LCD only available on Port A */ + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c b/arch/arm/mach-at91/armv7/sama5d4_devices.c new file mode 100644 index 00000000000..ef39cb7e089 --- /dev/null +++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2014 Atmel + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +char *get_cpu_name() +{ + unsigned int extension_id = get_extension_chip_id(); + + if (cpu_is_sama5d4()) + switch (extension_id) { + case ARCH_EXID_SAMA5D41: + return "SAMA5D41"; + case ARCH_EXID_SAMA5D42: + return "SAMA5D42"; + case ARCH_EXID_SAMA5D43: + return "SAMA5D43"; + case ARCH_EXID_SAMA5D44: + return "SAMA5D44"; + default: + return "Unknown CPU type"; + } + else + return "Unknown CPU type"; +} + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +void at91_udp_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable UPLL clock */ + writel(AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); + /* Enable UDPHS clock */ + at91_periph_clk_enable(ATMEL_ID_UDPHS); +} +#endif + +#ifdef CONFIG_SPL_BUILD +void matrix_init(void) +{ + struct atmel_matrix *h64mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX0; + struct atmel_matrix *h32mx = (struct atmel_matrix *)ATMEL_BASE_MATRIX1; + int i; + + /* Disable the write protect */ + writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); + writel(ATMEL_MATRIX_WPMR_WPKEY & ~ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); + + /* DDR port 1 ~ poart 7, slave number is: 4 ~ 10 */ + for (i = 4; i <= 10; i++) { + writel(0x000f0f0f, &h64mx->ssr[i]); + writel(0x0000ffff, &h64mx->sassr[i]); + writel(0x0000000f, &h64mx->srtsr[i]); + } + + /* CS3 */ + writel(0x00c0c0c0, &h32mx->ssr[3]); + writel(0xff000000, &h32mx->sassr[3]); + writel(0xff000000, &h32mx->srtsr[3]); + + /* NFC SRAM */ + writel(0x00010101, &h32mx->ssr[4]); + writel(0x00000001, &h32mx->sassr[4]); + writel(0x00000001, &h32mx->srtsr[4]); + + /* Enable the write protect */ + writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h64mx->wpmr); + writel(ATMEL_MATRIX_WPMR_WPKEY | ATMEL_MATRIX_WPMR_WPEN, &h32mx->wpmr); +} + +void redirect_int_from_saic_to_aic(void) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + u32 key32; + + if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) { + key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY; + writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir); + } +} +#endif diff --git a/arch/arm/mach-at91/armv7/timer.c b/arch/arm/mach-at91/armv7/timer.c new file mode 100644 index 00000000000..19bf80ba7eb --- /dev/null +++ b/arch/arm/mach-at91/armv7/timer.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2013 + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include + +#if !defined(CONFIG_AT91FAMILY) +# error You need to define CONFIG_AT91FAMILY in your board config! +#endif + +DECLARE_GLOBAL_DATA_PTR; + +/* + * We're using the SAMA5D3x PITC in 32 bit mode, by + * setting the 20 bit counter period to its maximum (0xfffff). + * (See the relevant data sheets to understand that this really works) + * + * We do also mimic the typical powerpc way of incrementing + * two 32 bit registers called tbl and tbu. + * + * Those registers increment at 1/16 the main clock rate. + */ + +#define TIMER_LOAD_VAL 0xfffff + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, gd->arch.timer_rate_hz); + + return tick; +} + +static inline unsigned long long usec_to_tick(unsigned long long usec) +{ + usec *= gd->arch.timer_rate_hz; + do_div(usec, 1000000); + + return usec; +} + +/* + * Use the PITC in full 32 bit incrementing mode + */ +int timer_init(void) +{ + at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; + + /* Enable PITC Clock */ + at91_periph_clk_enable(ATMEL_ID_PIT); + + /* Enable PITC */ + writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); + + gd->arch.timer_rate_hz = get_pit_clk_rate() / 16; + + gd->arch.tbu = 0; + gd->arch.tbl = 0; + + return 0; +} + +/* + * Get the current 64 bit timer tick count + */ +unsigned long long get_ticks(void) +{ + at91_pit_t *pit = (at91_pit_t *)ATMEL_BASE_PIT; + + ulong now = readl(&pit->piir); + + /* increment tbu if tbl has rolled over */ + if (now < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl = now; + return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; +} + +void __udelay(unsigned long usec) +{ + unsigned long long start; + ulong tmo; + + start = get_ticks(); /* get current timestamp */ + tmo = usec_to_tick(usec); /* convert usecs to ticks */ + while ((get_ticks() - start) < tmo) + ; /* loop till time has passed */ +} + +/* + * get_timer(base) can be used to check for timeouts or + * to measure elasped time relative to an event: + * + * ulong start_time = get_timer(0) sets start_time to the current + * time value. + * get_timer(start_time) returns the time elapsed since then. + * + * The time is used in CONFIG_SYS_HZ units! + */ +ulong get_timer(ulong base) +{ + return tick_to_time(get_ticks()) - base; +} + +/* + * Return the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return gd->arch.timer_rate_hz; +} diff --git a/arch/arm/mach-at91/config.mk b/arch/arm/mach-at91/config.mk new file mode 100644 index 00000000000..7168abbd584 --- /dev/null +++ b/arch/arm/mach-at91/config.mk @@ -0,0 +1,9 @@ +ifeq ($(CONFIG_CPU_ARM926EJS),y) +PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) +endif + +ifeq ($(CONFIG_CPU_V7),y) +ifndef CONFIG_SPL_BUILD +ALL-y += u-boot.img +endif +endif diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c new file mode 100644 index 00000000000..beec13db8c1 --- /dev/null +++ b/arch/arm/mach-at91/mpddrc.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +static inline void atmel_mpddr_op(int mode, u32 ram_address) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + + writel(mode, &mpddr->mr); + writel(0, ram_address); +} + +static int ddr2_decodtype_is_seq(u32 cr) +{ +#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) + if (cr & ATMEL_MPDDRC_CR_DECOD_INTERLEAVED) + return 0; +#endif + return 1; +} + +int ddr2_init(const unsigned int ram_address, + const struct atmel_mpddr *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + u32 ba_off, cr; + + /* Compute bank offset according to NC in configuration register */ + ba_off = (mpddr_value->cr & ATMEL_MPDDRC_CR_NC_MASK) + 9; + if (ddr2_decodtype_is_seq(mpddr_value->cr)) + ba_off += ((mpddr_value->cr & ATMEL_MPDDRC_CR_NR_MASK) >> 2) + 11; + + ba_off += (mpddr_value->md & ATMEL_MPDDRC_MD_DBW_MASK) ? 1 : 2; + + /* Program the memory device type into the memory device register */ + writel(mpddr_value->md, &mpddr->md); + + /* Program the configuration register */ + writel(mpddr_value->cr, &mpddr->cr); + + /* Program the timing register */ + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* A 200 us is provided to precede any signal toggle */ + udelay(200); + + /* Issue a NOP command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Issue an extended mode register set(EMRS2) to choose operation */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x2 << ba_off)); + + /* Issue an extended mode register set(EMRS3) to set EMSR to 0 */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x3 << ba_off)); + + /* + * Issue an extended mode register set(EMRS1) to enable DLL and + * program D.I.C (output driver impedance control) + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* Enable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_DLL_RESET_ENABLED, &mpddr->cr); + + /* A mode register set(MRS) cycle is issued to reset DLL */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Issue an all banks precharge command */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_PRCGALL_CMD, ram_address); + + /* Two auto-refresh (CBR) cycles are provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_RFSH_CMD, ram_address); + + /* Disable DLL reset */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_DLL_RESET_ENABLED), &mpddr->cr); + + /* A mode register set (MRS) cycle is issued to disable DLL reset */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_LMR_CMD, ram_address); + + /* Set OCD calibration in default state */ + cr = readl(&mpddr->cr); + writel(cr | ATMEL_MPDDRC_CR_OCD_DEFAULT, &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to OCD default value + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* OCD calibration mode exit */ + cr = readl(&mpddr->cr); + writel(cr & (~ATMEL_MPDDRC_CR_OCD_DEFAULT), &mpddr->cr); + + /* + * An extended mode register set (EMRS1) cycle is issued + * to enable OCD exit + */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD, + ram_address + (0x1 << ba_off)); + + /* A nornal mode command is provided */ + atmel_mpddr_op(ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* Perform a write access to any DDR2-SDRAM address */ + writel(0, ram_address); + + /* Write the refresh rate */ + writel(mpddr_value->rtr, &mpddr->rtr); + + return 0; +} diff --git a/arch/arm/mach-at91/phy.c b/arch/arm/mach-at91/phy.c new file mode 100644 index 00000000000..2cba7169e4e --- /dev/null +++ b/arch/arm/mach-at91/phy.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * (C) Copyright 2012 + * Markus Hubig + * IMKO GmbH + * + * Copyright (C) 2013 DENX Software Engineering, hs@denx.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +void at91_phy_reset(void) +{ + unsigned long erstl; + unsigned long start = get_timer(0); + unsigned long const timeout = 1000; /* 1000ms */ + at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC; + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* + * Need to reset PHY -> 500ms reset + * Reset PHY by pulling the NRST line for 500ms to low. To do so + * disable user reset for low level on NRST pin and poll the NRST + * level in reset status register. + */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end of hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) { + /* avoid shutdown by watchdog */ + WATCHDOG_RESET(); + mdelay(10); + + /* timeout for not getting stuck in an endless loop */ + if (get_timer(start) >= timeout) { + puts("*** ERROR: Timeout waiting for PHY reset!\n"); + break; + } + }; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); +} diff --git a/arch/arm/mach-at91/sdram.c b/arch/arm/mach-at91/sdram.c new file mode 100644 index 00000000000..5758b066e46 --- /dev/null +++ b/arch/arm/mach-at91/sdram.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2014 + * Heiko Schocher, DENX Software Engineering, hs@denx.de. + * + * Based on: + * (C) Copyright 2007-2008 + * Stelian Pop + * Lead Tech Design + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +int sdramc_initialize(unsigned int sdram_address, const struct sdramc_reg *p) +{ + struct sdramc_reg *reg = (struct sdramc_reg *)ATMEL_BASE_SDRAMC; + unsigned int i; + + /* SDRAM feature must be in the configuration register */ + writel(p->cr, ®->cr); + + /* The SDRAM memory type must be set in the Memory Device Register */ + writel(p->mdr, ®->mdr); + + /* + * The minimum pause of 200 us is provided to precede any single + * toggle + */ + for (i = 0; i < 1000; i++) + ; + + /* A NOP command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_NOP, ®->mr); + writel(0x00000000, sdram_address); + + /* An All Banks Precharge command is issued to the SDRAM devices */ + writel(AT91_SDRAMC_MODE_PRECHARGE, ®->mr); + writel(0x00000000, sdram_address); + + for (i = 0; i < 10000; i++) + ; + + /* Eight auto-refresh cycles are provided */ + for (i = 0; i < 8; i++) { + writel(AT91_SDRAMC_MODE_REFRESH, ®->mr); + writel(0x00000001 + i, sdram_address + 4 + 4 * i); + } + + /* + * A Mode Register set (MRS) cyscle is issued to program the + * SDRAM parameters(TCSR, PASR, DS) + */ + writel(AT91_SDRAMC_MODE_LMR, ®->mr); + writel(0xcafedede, sdram_address + 0x24); + + /* + * The application must go into Normal Mode, setting Mode + * to 0 in the Mode Register and perform a write access at + * any location in the SDRAM. + */ + writel(AT91_SDRAMC_MODE_NORMAL, ®->mr); + writel(0x00000000, sdram_address); /* Perform Normal mode */ + + /* + * Write the refresh rate into the count field in the SDRAMC + * Refresh Timer Rgister. + */ + writel(p->tr, ®->tr); + + return 0; +} diff --git a/arch/arm/mach-at91/spl.c b/arch/arm/mach-at91/spl.c new file mode 100644 index 00000000000..aaa5eec2e66 --- /dev/null +++ b/arch/arm/mach-at91/spl.c @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_AT91SAM9_WATCHDOG) +void at91_disable_wdt(void) { } +#else +void at91_disable_wdt(void) +{ + struct at91_wdt *wdt = (struct at91_wdt *)ATMEL_BASE_WDT; + + writel(AT91_WDT_MR_WDDIS, &wdt->mr); +} +#endif + +u32 spl_boot_device(void) +{ +#ifdef CONFIG_SYS_USE_MMC + return BOOT_DEVICE_MMC1; +#elif CONFIG_SYS_USE_NANDFLASH + return BOOT_DEVICE_NAND; +#elif CONFIG_SYS_USE_SERIALFLASH + return BOOT_DEVICE_SPI; +#endif + return BOOT_DEVICE_NONE; +} + +u32 spl_boot_mode(void) +{ + switch (spl_boot_device()) { +#ifdef CONFIG_SYS_USE_MMC + case BOOT_DEVICE_MMC1: + return MMCSD_MODE_FS; + break; +#endif + case BOOT_DEVICE_NONE: + default: + hang(); + } +} diff --git a/arch/arm/mach-at91/spl_at91.c b/arch/arm/mach-at91/spl_at91.c new file mode 100644 index 00000000000..89f588be45a --- /dev/null +++ b/arch/arm/mach-at91/spl_at91.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2014 DENX Software Engineering + * Heiko Schocher + * + * Based on: + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void enable_ext_reset(void) +{ + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + + writel(AT91_RSTC_KEY | AT91_RSTC_MR_URSTEN, &rstc->mr); +} + +void lowlevel_clock_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + if (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) { + /* Enable Main Oscillator */ + writel(AT91_PMC_MOSCS | (0x40 << 8), &pmc->mor); + + /* Wait until Main Oscillator is stable */ + while (!(readl(&pmc->sr) & AT91_PMC_MOSCS)) + ; + } + + /* After stabilization, switch to Main Oscillator */ + if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { + unsigned long tmp; + + tmp = readl(&pmc->mckr); + tmp &= ~AT91_PMC_CSS; + tmp |= AT91_PMC_CSS_MAIN; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + + tmp &= ~AT91_PMC_PRES; + tmp |= AT91_PMC_PRES_1; + writel(tmp, &pmc->mckr); + while (!(readl(&pmc->sr) & AT91_PMC_MCKRDY)) + ; + } + + return; +} + +void __weak matrix_init(void) +{ +} + +void __weak at91_spl_board_init(void) +{ +} + +void spl_board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + lowlevel_clock_init(); + at91_disable_wdt(); + + /* + * At this stage the main oscillator is supposed to be enabled + * PCK = MCK = MOSC + */ + writel(0x00, &pmc->pllicpr); + + /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ + at91_plla_init(CONFIG_SYS_AT91_PLLA); + + /* PCK = PLLA = 2 * MCK */ + at91_mck_init(CONFIG_SYS_MCKR); + + /* Switch MCK on PLLA output */ + at91_mck_init(CONFIG_SYS_MCKR_CSS); + +#if defined(CONFIG_SYS_AT91_PLLB) + /* Configure PLLB */ + at91_pllb_init(CONFIG_SYS_AT91_PLLB); +#endif + + /* Enable External Reset */ + enable_ext_reset(); + + /* Initialize matrix */ + matrix_init(); + + gd->arch.mck_rate_hz = CONFIG_SYS_MASTER_CLOCK; + /* + * init timer long enough for using in spl. + */ + timer_init(); + + /* enable clocks for all PIOs */ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + /* init console */ + at91_seriald_hw_init(); + preloader_console_init(); + + mem_init(); + + at91_spl_board_init(); +} diff --git a/arch/arm/mach-at91/spl_atmel.c b/arch/arm/mach-at91/spl_atmel.c new file mode 100644 index 00000000000..9cc1111234a --- /dev/null +++ b/arch/arm/mach-at91/spl_atmel.c @@ -0,0 +1,96 @@ +/* + * Copyright (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static void switch_to_main_crystal_osc(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCOUNT(0xff); + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_MOSCEN; + tmp |= AT91_PMC_MOR_OSCOUNT(8); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCS)) + ; + + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_OSCBYPASS; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + tmp = readl(&pmc->mor); + tmp |= AT91_PMC_MOR_MOSCSEL; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); + + while (!(readl(&pmc->sr) & AT91_PMC_IXR_MOSCSELS)) + ; + + /* Wait until MAINRDY field is set to make sure main clock is stable */ + while (!(readl(&pmc->mcfr) & AT91_PMC_MAINRDY)) + ; + +#ifndef CONFIG_SAMA5D4 + tmp = readl(&pmc->mor); + tmp &= ~AT91_PMC_MOR_MOSCRCEN; + tmp &= ~AT91_PMC_MOR_KEY(0xff); + tmp |= AT91_PMC_MOR_KEY(0x37); + writel(tmp, &pmc->mor); +#endif +} + +__weak void matrix_init(void) +{ + /* This only be used for sama5d4 soc now */ +} + +__weak void redirect_int_from_saic_to_aic(void) +{ + /* This only be used for sama5d4 soc now */ +} + +void s_init(void) +{ + switch_to_main_crystal_osc(); + + /* disable watchdog */ + at91_disable_wdt(); + + /* PMC configuration */ + at91_pmc_init(); + + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); + + matrix_init(); + + redirect_int_from_saic_to_aic(); + + timer_init(); + + board_early_init_f(); + + preloader_console_init(); + + mem_init(); +} diff --git a/arch/arm/mach-at91/u-boot-spl.lds b/arch/arm/mach-at91/u-boot-spl.lds new file mode 100644 index 00000000000..eccca43a423 --- /dev/null +++ b/arch/arm/mach-at91/u-boot-spl.lds @@ -0,0 +1,55 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * (C) Copyright 2010 + * Texas Instruments, + * Aneesh V + * + * (C) 2013 Atmel Corporation + * Bo Shen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + *(.vectors) + arch/arm/cpu/armv7/start.o (.text*) + *(.text*) + } >.sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + + .end : + { + *(.__end) + } >.sram + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } >.sdram +} diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 5a0ab284ab2..5dab61d56df 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -227,7 +227,7 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/u-boot-spl.lds #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index cccc1edbb81..bd288beaeba 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -274,7 +274,7 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) #ifdef CONFIG_SYS_USE_MMC -#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds +#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/u-boot-spl.lds #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 -- cgit v1.3.1 From ea3857230c2d7428e8c22a9d063b4a5b86b34a0c Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Fri, 20 Feb 2015 17:04:15 +0900 Subject: ARM: kirkwood: move SoC headers to mach-kirkwood/include/mach Move arch/arm/include/asm/arch-kirkwood/* -> arch/arm/mach-kirkwood/include/mach/* Signed-off-by: Masahiro Yamada Acked-by: Stefan Roese Cc: Prafulla Wadaskar Cc: Luka Perkov --- MAINTAINERS | 1 - arch/arm/include/asm/arch-kirkwood/config.h | 138 ----------- arch/arm/include/asm/arch-kirkwood/cpu.h | 155 ------------ arch/arm/include/asm/arch-kirkwood/gpio.h | 49 ---- arch/arm/include/asm/arch-kirkwood/kw88f6192.h | 21 -- arch/arm/include/asm/arch-kirkwood/kw88f6281.h | 23 -- arch/arm/include/asm/arch-kirkwood/mpp.h | 301 ------------------------ arch/arm/include/asm/arch-kirkwood/soc.h | 74 ------ arch/arm/mach-kirkwood/include/mach/config.h | 138 +++++++++++ arch/arm/mach-kirkwood/include/mach/cpu.h | 155 ++++++++++++ arch/arm/mach-kirkwood/include/mach/gpio.h | 49 ++++ arch/arm/mach-kirkwood/include/mach/kw88f6192.h | 21 ++ arch/arm/mach-kirkwood/include/mach/kw88f6281.h | 23 ++ arch/arm/mach-kirkwood/include/mach/mpp.h | 301 ++++++++++++++++++++++++ arch/arm/mach-kirkwood/include/mach/soc.h | 74 ++++++ include/configs/km/km_arm.h | 2 +- 16 files changed, 762 insertions(+), 763 deletions(-) delete mode 100644 arch/arm/include/asm/arch-kirkwood/config.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/cpu.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/gpio.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/kw88f6192.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/kw88f6281.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/mpp.h delete mode 100644 arch/arm/include/asm/arch-kirkwood/soc.h create mode 100644 arch/arm/mach-kirkwood/include/mach/config.h create mode 100644 arch/arm/mach-kirkwood/include/mach/cpu.h create mode 100644 arch/arm/mach-kirkwood/include/mach/gpio.h create mode 100644 arch/arm/mach-kirkwood/include/mach/kw88f6192.h create mode 100644 arch/arm/mach-kirkwood/include/mach/kw88f6281.h create mode 100644 arch/arm/mach-kirkwood/include/mach/mpp.h create mode 100644 arch/arm/mach-kirkwood/include/mach/soc.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 7a3e9631002..eef70d0f681 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -99,7 +99,6 @@ M: Luka Perkov S: Maintained T: git git://git.denx.de/u-boot-marvell.git F: arch/arm/mach-kirkwood/ -F: arch/arm/include/asm/arch-kirkwood/ ARM MARVELL PXA M: Marek Vasut diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h deleted file mode 100644 index e77ac400d8d..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ /dev/null @@ -1,138 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * This file should be included in board config header file. - * - * It supports common definitions for Kirkwood platform - */ - -#ifndef _KW_CONFIG_H -#define _KW_CONFIG_H - -#if defined (CONFIG_KW88F6281) -#include -#elif defined (CONFIG_KW88F6192) -#include -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ - -#include -#define CONFIG_SYS_CACHELINE_SIZE 32 - /* default Dcache Line length for kirkwood */ -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ - -/* - * By default kwbimage.cfg from board specific folder is used - * If for some board, different configuration file need to be used, - * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file - */ -#ifndef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#endif /* CONFIG_SYS_KWD_CONFIG */ - -/* Kirkwood has 2k of Security SRAM, use it for SP */ -#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE -#define MV_UART_CONSOLE_BASE KW_UART0_BASE -#define MV_SATA_BASE KW_SATA_BASE -#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET -#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET - -/* - * NAND configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_KIRKWOOD -#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ -#define NAND_ALLOW_ERASE_ALL 1 -#endif - -/* - * SPI Flash configuration - */ -#ifdef CONFIG_CMD_SF -#define CONFIG_HARD_SPI 1 -#define CONFIG_KIRKWOOD_SPI 1 -#ifndef CONFIG_ENV_SPI_BUS -# define CONFIG_ENV_SPI_BUS 0 -#endif -#ifndef CONFIG_ENV_SPI_CS -# define CONFIG_ENV_SPI_CS 0 -#endif -#ifndef CONFIG_ENV_SPI_MAX_HZ -# define CONFIG_ENV_SPI_MAX_HZ 50000000 -#endif -#endif - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_MII /* expose smi ove miiphy interface */ -#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#endif /* CONFIG_CMD_NET */ - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MARVELL -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* - * IDE Support on SATA ports - */ -#ifdef CONFIG_CMD_IDE -#define __io -#define CONFIG_CMD_EXT2 -#define CONFIG_MVSATA_IDE -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* CONFIG_CMD_IDE requires some #defines for ATA registers */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE -#endif /* CONFIG_CMD_IDE */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#ifndef CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#endif -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#endif /* _KW_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/cpu.h b/arch/arm/include/asm/arch-kirkwood/cpu.h deleted file mode 100644 index 926d347110f..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/cpu.h +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _KWCPU_H -#define _KWCPU_H - -#include - -#ifndef __ASSEMBLY__ - -#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ - | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) - -#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ - ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) - -#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) -#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) -#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) -#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) -#define SYSRST_CNT_1SEC_VAL (25*1000000) -#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) - -enum memory_bank { - BANK0, - BANK1, - BANK2, - BANK3 -}; - -enum kwcpu_winen { - KWCPU_WIN_DISABLE, - KWCPU_WIN_ENABLE -}; - -enum kwcpu_target { - KWCPU_TARGET_RESERVED, - KWCPU_TARGET_MEMORY, - KWCPU_TARGET_1RESERVED, - KWCPU_TARGET_SASRAM, - KWCPU_TARGET_PCIE -}; - -enum kwcpu_attrib { - KWCPU_ATTR_SASRAM = 0x01, - KWCPU_ATTR_DRAM_CS0 = 0x0e, - KWCPU_ATTR_DRAM_CS1 = 0x0d, - KWCPU_ATTR_DRAM_CS2 = 0x0b, - KWCPU_ATTR_DRAM_CS3 = 0x07, - KWCPU_ATTR_NANDFLASH = 0x2f, - KWCPU_ATTR_SPIFLASH = 0x1e, - KWCPU_ATTR_BOOTROM = 0x1d, - KWCPU_ATTR_PCIE_IO = 0xe0, - KWCPU_ATTR_PCIE_MEM = 0xe8 -}; - -/* - * Default Device Address MAP BAR values - */ -#define KW_DEFADR_PCI_MEM 0x90000000 -#define KW_DEFADR_PCI_IO 0xC0000000 -#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 -#define KW_DEFADR_SASRAM 0xC8010000 -#define KW_DEFADR_NANDF 0xD8000000 -#define KW_DEFADR_SPIF 0xE8000000 -#define KW_DEFADR_BOOTROM 0xF8000000 - -/* - * read feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline unsigned int readfr_extra_feature_reg(void) -{ - unsigned int val; - asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" - (val)::"cc"); - return val; -} - -/* - * write feroceon/sheeva core extra feature register - * using co-proc instruction - */ -static inline void writefr_extra_feature_reg(unsigned int val) -{ - asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" - (val):"cc"); - isb(); -} - -/* - * MBus-L to Mbus Bridge Registers - * Ref: Datasheet sec:A.3 - */ -struct kwwin_registers { - u32 ctrl; - u32 base; - u32 remap_lo; - u32 remap_hi; -}; - -/* - * CPU control and status Registers - * Ref: Datasheet sec:A.3.2 - */ -struct kwcpu_registers { - u32 config; /*0x20100 */ - u32 ctrl_stat; /*0x20104 */ - u32 rstoutn_mask; /* 0x20108 */ - u32 sys_soft_rst; /* 0x2010C */ - u32 ahb_mbus_cause_irq; /* 0x20110 */ - u32 ahb_mbus_mask_irq; /* 0x20114 */ - u32 pad1[2]; - u32 ftdll_config; /* 0x20120 */ - u32 pad2; - u32 l2_cfg; /* 0x20128 */ -}; - -/* - * GPIO Registers - * Ref: Datasheet sec:A.19 - */ -struct kwgpio_registers { - u32 dout; - u32 oe; - u32 blink_en; - u32 din_pol; - u32 din; - u32 irq_cause; - u32 irq_mask; - u32 irq_level; -}; - -/* - * functions - */ -unsigned char get_random_hex(void); -unsigned int mvebu_sdram_bar(enum memory_bank bank); -unsigned int mvebu_sdram_bs(enum memory_bank bank); -void mvebu_sdram_size_adjust(enum memory_bank bank); -int kw_config_adr_windows(void); -void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, - unsigned int gpp0_oe, unsigned int gpp1_oe); -int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, - unsigned int mpp16_23, unsigned int mpp24_31, - unsigned int mpp32_39, unsigned int mpp40_47, - unsigned int mpp48_55); -unsigned int kw_winctrl_calcsize(unsigned int sizeval); -#endif /* __ASSEMBLY__ */ -#endif /* _KWCPU_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h b/arch/arm/include/asm/arch-kirkwood/gpio.h deleted file mode 100644 index aa8c5da36d3..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/gpio.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * arch/asm-arm/mach-kirkwood/include/mach/gpio.h - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. - * Removed kernel level irq handling. Took some macros from kernel to - * allow build. - * - * Dieter Kiermaier dk-arm-linux@gmx.de - */ - -#ifndef __KIRKWOOD_GPIO_H -#define __KIRKWOOD_GPIO_H - -/* got from kernel include/linux/bitops.h */ -#define BITS_PER_BYTE 8 -#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) - -#define GPIO_MAX 50 -#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) -#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) -#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) -#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) -#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) -#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) -#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) -#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) -#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) - -/* - * Kirkwood-specific GPIO API - */ - -void kw_gpio_set_valid(unsigned pin, int mode); -int kw_gpio_is_valid(unsigned pin, int mode); -int kw_gpio_direction_input(unsigned pin); -int kw_gpio_direction_output(unsigned pin, int value); -int kw_gpio_get_value(unsigned pin); -void kw_gpio_set_value(unsigned pin, int value); -void kw_gpio_set_blink(unsigned pin, int blink); -void kw_gpio_set_unused(unsigned pin); - -#define GPIO_INPUT_OK (1 << 0) -#define GPIO_OUTPUT_OK (1 << 1) - -#endif diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h b/arch/arm/include/asm/arch-kirkwood/kw88f6192.h deleted file mode 100644 index de220d57d4a..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/kw88f6192.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _CONFIG_KW88F6192_H -#define _CONFIG_KW88F6192_H - -/* SOC specific definations */ -#define KW88F6192_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE - -/* TCLK Core Clock defination */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -#endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h b/arch/arm/include/asm/arch-kirkwood/kw88f6281.h deleted file mode 100644 index ca88a300e0b..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/kw88f6281.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_KW88F6281_H -#define _ASM_ARCH_KW88F6281_H - -/* SOC specific definitions */ -#define KW88F6281_REGS_PHYS_BASE 0xf1000000 -#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE - -/* TCLK Core Clock definition */ -#ifndef CONFIG_SYS_TCLK -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ -#endif - -#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/include/asm/arch-kirkwood/mpp.h b/arch/arm/include/asm/arch-kirkwood/mpp.h deleted file mode 100644 index 7c8f6eba976..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/mpp.h +++ /dev/null @@ -1,301 +0,0 @@ -/* - * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins - * - * Copyright 2009: Marvell Technology Group Ltd. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __KIRKWOOD_MPP_H -#define __KIRKWOOD_MPP_H - -#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ - /* MPP number */ ((_num) & 0xff) | \ - /* MPP select value */ (((_sel) & 0xf) << 8) | \ - /* may be input signal */ ((!!(_in)) << 12) | \ - /* may be output signal */ ((!!(_out)) << 13) | \ - /* available on F6180 */ ((!!(_F6180)) << 14) | \ - /* available on F6190 */ ((!!(_F6190)) << 15) | \ - /* available on F6192 */ ((!!(_F6192)) << 16) | \ - /* available on F6281 */ ((!!(_F6281)) << 17)) - -#define MPP_NUM(x) ((x) & 0xff) -#define MPP_SEL(x) (((x) >> 8) & 0xf) - - /* num sel i o 6180 6190 6192 6281 */ - -#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) -#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) - -#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) -#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) -#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) -#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) - -#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) - -#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) - -#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) -#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) -#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) -#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) -#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) -#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) -#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) - -#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) -#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) -#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) -#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) - -#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) - -#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) -#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) -#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) -#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) -#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) - -#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) -#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) - -#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) -#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) - -#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) -#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) - -#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) -#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) - -#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) - -#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) - -#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) -#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) -#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) -#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) -#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) -#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) - -#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) -#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) -#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) -#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) -#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) - -#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) -#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) - -#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) -#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) -#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) - -#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) - -#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) - -#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) - -#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) -#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) -#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) - -#define MPP_MAX 49 - -void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); - -#endif diff --git a/arch/arm/include/asm/arch-kirkwood/soc.h b/arch/arm/include/asm/arch-kirkwood/soc.h deleted file mode 100644 index 58ed71b1864..00000000000 --- a/arch/arm/include/asm/arch-kirkwood/soc.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * - * Header file for the Marvell's Feroceon CPU core. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _ASM_ARCH_KIRKWOOD_H -#define _ASM_ARCH_KIRKWOOD_H - -#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) - -/* SOC specific definations */ -#define INTREG_BASE 0xd0000000 -#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) -#define KW_OFFSET_REG (INTREG_BASE + 0x20080) - -/* undocumented registers */ -#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) -#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) - -#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) -#define KW_TWSI_BASE (KW_REGISTER(0x11000)) -#define KW_UART0_BASE (KW_REGISTER(0x12000)) -#define KW_UART1_BASE (KW_REGISTER(0x12100)) -#define KW_MPP_BASE (KW_REGISTER(0x10000)) -#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) -#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) -#define KW_RTC_BASE (KW_REGISTER(0x10300)) -#define KW_NANDF_BASE (KW_REGISTER(0x10418)) -#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) -#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) -#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) -#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) -#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) -#define KW_USB20_BASE (KW_REGISTER(0x50000)) -#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) -#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) -#define KW_SATA_BASE (KW_REGISTER(0x80000)) -#define KW_SDIO_BASE (KW_REGISTER(0x90000)) - -/* Kirkwood Sata controller has two ports */ -#define KW_SATA_PORT0_OFFSET 0x2000 -#define KW_SATA_PORT1_OFFSET 0x4000 - -/* Kirkwood GbE controller has two ports */ -#define MAX_MVGBE_DEVS 2 -#define MVGBE0_BASE KW_EGIGA0_BASE -#define MVGBE1_BASE KW_EGIGA1_BASE - -/* Kirkwood USB Host controller */ -#define MVUSB0_BASE KW_USB20_BASE -#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 -#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 -#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 -#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 - -/* Kirkwood CPU memory windows */ -#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA -#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE -#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE - -#if defined (CONFIG_KW88F6281) -#include -#elif defined (CONFIG_KW88F6192) -#include -#else -#error "SOC Name not defined" -#endif /* CONFIG_KW88F6281 */ -#endif /* CONFIG_FEROCEON_88FR131 */ -#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/config.h b/arch/arm/mach-kirkwood/include/mach/config.h new file mode 100644 index 00000000000..e77ac400d8d --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/config.h @@ -0,0 +1,138 @@ +/* + * (C) Copyright 2011 + * Marvell Semiconductor + * Written-by: Lei Wen + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file should be included in board config header file. + * + * It supports common definitions for Kirkwood platform + */ + +#ifndef _KW_CONFIG_H +#define _KW_CONFIG_H + +#if defined (CONFIG_KW88F6281) +#include +#elif defined (CONFIG_KW88F6192) +#include +#else +#error "SOC Name not defined" +#endif /* CONFIG_KW88F6281 */ + +#include +#define CONFIG_SYS_CACHELINE_SIZE 32 + /* default Dcache Line length for kirkwood */ +#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ +#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ +#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ +#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */ + +/* + * By default kwbimage.cfg from board specific folder is used + * If for some board, different configuration file need to be used, + * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file + */ +#ifndef CONFIG_SYS_KWD_CONFIG +#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg +#endif /* CONFIG_SYS_KWD_CONFIG */ + +/* Kirkwood has 2k of Security SRAM, use it for SP */ +#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000 +#define CONFIG_NR_DRAM_BANKS_MAX 2 + +#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE +#define MV_UART_CONSOLE_BASE KW_UART0_BASE +#define MV_SATA_BASE KW_SATA_BASE +#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET +#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET + +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_KIRKWOOD +#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */ +#define NAND_ALLOW_ERASE_ALL 1 +#endif + +/* + * SPI Flash configuration + */ +#ifdef CONFIG_CMD_SF +#define CONFIG_HARD_SPI 1 +#define CONFIG_KIRKWOOD_SPI 1 +#ifndef CONFIG_ENV_SPI_BUS +# define CONFIG_ENV_SPI_BUS 0 +#endif +#ifndef CONFIG_ENV_SPI_CS +# define CONFIG_ENV_SPI_CS 0 +#endif +#ifndef CONFIG_ENV_SPI_MAX_HZ +# define CONFIG_ENV_SPI_MAX_HZ 50000000 +#endif +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_NETCONSOLE /* include NetConsole support */ +#define CONFIG_MII /* expose smi ove miiphy interface */ +#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */ +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ +#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ +#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ +#endif /* CONFIG_CMD_NET */ + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI_MARVELL +#define CONFIG_EHCI_IS_TDI +#endif /* CONFIG_CMD_USB */ + +/* + * IDE Support on SATA ports + */ +#ifdef CONFIG_CMD_IDE +#define __io +#define CONFIG_CMD_EXT2 +#define CONFIG_MVSATA_IDE +#define CONFIG_IDE_PREINIT +#define CONFIG_MVSATA_IDE_USE_PORT1 +/* Needs byte-swapping for ATA data register */ +#define CONFIG_IDE_SWAP_IO +/* Data, registers and alternate blocks are at the same offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) +#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) +#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) +/* Each 8-bit ATA register is aligned to a 4-bytes address */ +#define CONFIG_SYS_ATA_STRIDE 4 +/* Controller supports 48-bits LBA addressing */ +#define CONFIG_LBA48 +/* CONFIG_CMD_IDE requires some #defines for ATA registers */ +#define CONFIG_SYS_IDE_MAXBUS 2 +#define CONFIG_SYS_IDE_MAXDEVICE 2 +/* ATA registers base is at SATA controller base */ +#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE +#endif /* CONFIG_CMD_IDE */ + +/* + * I2C related stuff + */ +#ifdef CONFIG_CMD_I2C +#ifndef CONFIG_SYS_I2C_SOFT +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MVTWSI +#endif +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define CONFIG_SYS_I2C_SPEED 100000 +#endif + +#endif /* _KW_CONFIG_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/cpu.h b/arch/arm/mach-kirkwood/include/mach/cpu.h new file mode 100644 index 00000000000..926d347110f --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/cpu.h @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KWCPU_H +#define _KWCPU_H + +#include + +#ifndef __ASSEMBLY__ + +#define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \ + | (attr << 8) | (kw_winctrl_calcsize(size) << 16)) + +#define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \ + ((_x ? KW_EGIGA1_BASE : KW_EGIGA0_BASE) + 0x44c) + +#define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00) +#define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08) +#define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34) +#define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50) +#define SYSRST_CNT_1SEC_VAL (25*1000000) +#define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0) + +enum memory_bank { + BANK0, + BANK1, + BANK2, + BANK3 +}; + +enum kwcpu_winen { + KWCPU_WIN_DISABLE, + KWCPU_WIN_ENABLE +}; + +enum kwcpu_target { + KWCPU_TARGET_RESERVED, + KWCPU_TARGET_MEMORY, + KWCPU_TARGET_1RESERVED, + KWCPU_TARGET_SASRAM, + KWCPU_TARGET_PCIE +}; + +enum kwcpu_attrib { + KWCPU_ATTR_SASRAM = 0x01, + KWCPU_ATTR_DRAM_CS0 = 0x0e, + KWCPU_ATTR_DRAM_CS1 = 0x0d, + KWCPU_ATTR_DRAM_CS2 = 0x0b, + KWCPU_ATTR_DRAM_CS3 = 0x07, + KWCPU_ATTR_NANDFLASH = 0x2f, + KWCPU_ATTR_SPIFLASH = 0x1e, + KWCPU_ATTR_BOOTROM = 0x1d, + KWCPU_ATTR_PCIE_IO = 0xe0, + KWCPU_ATTR_PCIE_MEM = 0xe8 +}; + +/* + * Default Device Address MAP BAR values + */ +#define KW_DEFADR_PCI_MEM 0x90000000 +#define KW_DEFADR_PCI_IO 0xC0000000 +#define KW_DEFADR_PCI_IO_REMAP 0xC0000000 +#define KW_DEFADR_SASRAM 0xC8010000 +#define KW_DEFADR_NANDF 0xD8000000 +#define KW_DEFADR_SPIF 0xE8000000 +#define KW_DEFADR_BOOTROM 0xF8000000 + +/* + * read feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline unsigned int readfr_extra_feature_reg(void) +{ + unsigned int val; + asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r" + (val)::"cc"); + return val; +} + +/* + * write feroceon/sheeva core extra feature register + * using co-proc instruction + */ +static inline void writefr_extra_feature_reg(unsigned int val) +{ + asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r" + (val):"cc"); + isb(); +} + +/* + * MBus-L to Mbus Bridge Registers + * Ref: Datasheet sec:A.3 + */ +struct kwwin_registers { + u32 ctrl; + u32 base; + u32 remap_lo; + u32 remap_hi; +}; + +/* + * CPU control and status Registers + * Ref: Datasheet sec:A.3.2 + */ +struct kwcpu_registers { + u32 config; /*0x20100 */ + u32 ctrl_stat; /*0x20104 */ + u32 rstoutn_mask; /* 0x20108 */ + u32 sys_soft_rst; /* 0x2010C */ + u32 ahb_mbus_cause_irq; /* 0x20110 */ + u32 ahb_mbus_mask_irq; /* 0x20114 */ + u32 pad1[2]; + u32 ftdll_config; /* 0x20120 */ + u32 pad2; + u32 l2_cfg; /* 0x20128 */ +}; + +/* + * GPIO Registers + * Ref: Datasheet sec:A.19 + */ +struct kwgpio_registers { + u32 dout; + u32 oe; + u32 blink_en; + u32 din_pol; + u32 din; + u32 irq_cause; + u32 irq_mask; + u32 irq_level; +}; + +/* + * functions + */ +unsigned char get_random_hex(void); +unsigned int mvebu_sdram_bar(enum memory_bank bank); +unsigned int mvebu_sdram_bs(enum memory_bank bank); +void mvebu_sdram_size_adjust(enum memory_bank bank); +int kw_config_adr_windows(void); +void mvebu_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val, + unsigned int gpp0_oe, unsigned int gpp1_oe); +int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15, + unsigned int mpp16_23, unsigned int mpp24_31, + unsigned int mpp32_39, unsigned int mpp40_47, + unsigned int mpp48_55); +unsigned int kw_winctrl_calcsize(unsigned int sizeval); +#endif /* __ASSEMBLY__ */ +#endif /* _KWCPU_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h new file mode 100644 index 00000000000..aa8c5da36d3 --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/gpio.h @@ -0,0 +1,49 @@ +/* + * arch/asm-arm/mach-kirkwood/include/mach/gpio.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver. + * Removed kernel level irq handling. Took some macros from kernel to + * allow build. + * + * Dieter Kiermaier dk-arm-linux@gmx.de + */ + +#ifndef __KIRKWOOD_GPIO_H +#define __KIRKWOOD_GPIO_H + +/* got from kernel include/linux/bitops.h */ +#define BITS_PER_BYTE 8 +#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) + +#define GPIO_MAX 50 +#define GPIO_OFF(pin) (((pin) >> 5) ? 0x0040 : 0x0000) +#define GPIO_OUT(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x00) +#define GPIO_IO_CONF(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x04) +#define GPIO_BLINK_EN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x08) +#define GPIO_IN_POL(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x0c) +#define GPIO_DATA_IN(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x10) +#define GPIO_EDGE_CAUSE(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x14) +#define GPIO_EDGE_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x18) +#define GPIO_LEVEL_MASK(pin) (MVEBU_GPIO0_BASE + GPIO_OFF(pin) + 0x1c) + +/* + * Kirkwood-specific GPIO API + */ + +void kw_gpio_set_valid(unsigned pin, int mode); +int kw_gpio_is_valid(unsigned pin, int mode); +int kw_gpio_direction_input(unsigned pin); +int kw_gpio_direction_output(unsigned pin, int value); +int kw_gpio_get_value(unsigned pin); +void kw_gpio_set_value(unsigned pin, int value); +void kw_gpio_set_blink(unsigned pin, int blink); +void kw_gpio_set_unused(unsigned pin); + +#define GPIO_INPUT_OK (1 << 0) +#define GPIO_OUTPUT_OK (1 << 1) + +#endif diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6192.h b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h new file mode 100644 index 00000000000..de220d57d4a --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6192.h @@ -0,0 +1,21 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for Feroceon CPU core 88FR131 Based KW88F6192 SOC. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _CONFIG_KW88F6192_H +#define _CONFIG_KW88F6192_H + +/* SOC specific definations */ +#define KW88F6192_REGS_PHYS_BASE 0xf1000000 +#define KW_REGS_PHY_BASE KW88F6192_REGS_PHYS_BASE + +/* TCLK Core Clock defination */ +#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ + +#endif /* _CONFIG_KW88F6192_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/kw88f6281.h b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h new file mode 100644 index 00000000000..ca88a300e0b --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/kw88f6281.h @@ -0,0 +1,23 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for Feroceon CPU core 88FR131 Based KW88F6281 SOC. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_KW88F6281_H +#define _ASM_ARCH_KW88F6281_H + +/* SOC specific definitions */ +#define KW88F6281_REGS_PHYS_BASE 0xf1000000 +#define KW_REGS_PHY_BASE KW88F6281_REGS_PHYS_BASE + +/* TCLK Core Clock definition */ +#ifndef CONFIG_SYS_TCLK +#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ +#endif + +#endif /* _ASM_ARCH_KW88F6281_H */ diff --git a/arch/arm/mach-kirkwood/include/mach/mpp.h b/arch/arm/mach-kirkwood/include/mach/mpp.h new file mode 100644 index 00000000000..7c8f6eba976 --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/mpp.h @@ -0,0 +1,301 @@ +/* + * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins + * + * Copyright 2009: Marvell Technology Group Ltd. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __KIRKWOOD_MPP_H +#define __KIRKWOOD_MPP_H + +#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \ + /* MPP number */ ((_num) & 0xff) | \ + /* MPP select value */ (((_sel) & 0xf) << 8) | \ + /* may be input signal */ ((!!(_in)) << 12) | \ + /* may be output signal */ ((!!(_out)) << 13) | \ + /* available on F6180 */ ((!!(_F6180)) << 14) | \ + /* available on F6190 */ ((!!(_F6190)) << 15) | \ + /* available on F6192 */ ((!!(_F6192)) << 16) | \ + /* available on F6281 */ ((!!(_F6281)) << 17)) + +#define MPP_NUM(x) ((x) & 0xff) +#define MPP_SEL(x) (((x) >> 8) & 0xf) + + /* num sel i o 6180 6190 6192 6281 */ + +#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0 ) +#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0 ) + +#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0 ) +#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0 ) +#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0 ) +#define MPP_F6281_MASK MPP( 0, 0x0, 0, 0, 0, 0, 0, 1 ) + +#define MPP0_GPIO MPP( 0, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP0_NF_IO2 MPP( 0, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP0_SPI_SCn MPP( 0, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP1_GPO MPP( 1, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP1_NF_IO3 MPP( 1, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP1_SPI_MOSI MPP( 1, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP2_GPO MPP( 2, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP2_NF_IO4 MPP( 2, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP2_SPI_SCK MPP( 2, 0x2, 0, 1, 1, 1, 1, 1 ) + +#define MPP3_GPO MPP( 3, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP3_NF_IO5 MPP( 3, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP3_SPI_MISO MPP( 3, 0x2, 1, 0, 1, 1, 1, 1 ) + +#define MPP4_GPIO MPP( 4, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP4_NF_IO6 MPP( 4, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP4_UART0_RXD MPP( 4, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP4_SATA1_ACTn MPP( 4, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP4_PTP_CLK MPP( 4, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP5_GPO MPP( 5, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP5_NF_IO7 MPP( 5, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP5_UART0_TXD MPP( 5, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP5_PTP_TRIG_GEN MPP( 5, 0x4, 0, 1, 1, 1, 1, 1 ) +#define MPP5_SATA0_ACTn MPP( 5, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP6_SYSRST_OUTn MPP( 6, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP6_SPI_MOSI MPP( 6, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP6_PTP_TRIG_GEN MPP( 6, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP7_GPO MPP( 7, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PEX_RST_OUTn MPP( 7, 0x1, 0, 1, 1, 1, 1, 1 ) +#define MPP7_SPI_SCn MPP( 7, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP7_PTP_TRIG_GEN MPP( 7, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP8_GPIO MPP( 8, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP8_TW_SDA MPP( 8, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP8_UART0_RTS MPP( 8, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP8_UART1_RTS MPP( 8, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP8_MII0_RXERR MPP( 8, 0x4, 1, 0, 0, 1, 1, 1 ) +#define MPP8_SATA1_PRESENTn MPP( 8, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP8_PTP_CLK MPP( 8, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP8_MII0_COL MPP( 8, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP9_GPIO MPP( 9, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP9_TW_SCK MPP( 9, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP9_UART0_CTS MPP( 9, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP9_UART1_CTS MPP( 9, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP9_SATA0_PRESENTn MPP( 9, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP9_PTP_EVENT_REQ MPP( 9, 0xc, 1, 0, 1, 1, 1, 1 ) +#define MPP9_MII0_CRS MPP( 9, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP10_GPO MPP( 10, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SPI_SCK MPP( 10, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP10_UART0_TXD MPP( 10, 0X3, 0, 1, 1, 1, 1, 1 ) +#define MPP10_SATA1_ACTn MPP( 10, 0x5, 0, 1, 0, 0, 1, 1 ) +#define MPP10_PTP_TRIG_GEN MPP( 10, 0xc, 0, 1, 1, 1, 1, 1 ) + +#define MPP11_GPIO MPP( 11, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP11_SPI_MISO MPP( 11, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP11_UART0_RXD MPP( 11, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_EVENT_REQ MPP( 11, 0x4, 1, 0, 1, 1, 1, 1 ) +#define MPP11_PTP_TRIG_GEN MPP( 11, 0xc, 0, 1, 1, 1, 1, 1 ) +#define MPP11_PTP_CLK MPP( 11, 0xd, 1, 0, 1, 1, 1, 1 ) +#define MPP11_SATA0_ACTn MPP( 11, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP12_GPO MPP( 12, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP12_SD_CLK MPP( 12, 0x1, 0, 1, 1, 1, 1, 1 ) + +#define MPP13_GPIO MPP( 13, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP13_SD_CMD MPP( 13, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP13_UART1_TXD MPP( 13, 0x3, 0, 1, 1, 1, 1, 1 ) + +#define MPP14_GPIO MPP( 14, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP14_SD_D0 MPP( 14, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP14_UART1_RXD MPP( 14, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP14_SATA1_PRESENTn MPP( 14, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP14_MII0_COL MPP( 14, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP15_GPIO MPP( 15, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP15_SD_D1 MPP( 15, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP15_UART0_RTS MPP( 15, 0x2, 0, 1, 1, 1, 1, 1 ) +#define MPP15_UART1_TXD MPP( 15, 0x3, 0, 1, 1, 1, 1, 1 ) +#define MPP15_SATA0_ACTn MPP( 15, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP16_GPIO MPP( 16, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP16_SD_D2 MPP( 16, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP16_UART0_CTS MPP( 16, 0x2, 1, 0, 1, 1, 1, 1 ) +#define MPP16_UART1_RXD MPP( 16, 0x3, 1, 0, 1, 1, 1, 1 ) +#define MPP16_SATA1_ACTn MPP( 16, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP16_MII0_CRS MPP( 16, 0xd, 1, 0, 1, 1, 1, 1 ) + +#define MPP17_GPIO MPP( 17, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SD_D3 MPP( 17, 0x1, 1, 1, 1, 1, 1, 1 ) +#define MPP17_SATA0_PRESENTn MPP( 17, 0x4, 0, 1, 0, 1, 1, 1 ) + +#define MPP18_GPO MPP( 18, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP18_NF_IO0 MPP( 18, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP19_GPO MPP( 19, 0x0, 0, 1, 1, 1, 1, 1 ) +#define MPP19_NF_IO1 MPP( 19, 0x1, 1, 1, 1, 1, 1, 1 ) + +#define MPP20_GPIO MPP( 20, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP20_TSMP0 MPP( 20, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP20_TDM_CH0_TX_QL MPP( 20, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP20_GE1_0 MPP( 20, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP20_AUDIO_SPDIFI MPP( 20, 0x4, 1, 0, 0, 0, 1, 1 ) +#define MPP20_SATA1_ACTn MPP( 20, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP21_GPIO MPP( 21, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP21_TSMP1 MPP( 21, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP21_TDM_CH0_RX_QL MPP( 21, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP21_GE1_1 MPP( 21, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP21_AUDIO_SPDIFO MPP( 21, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP21_SATA0_ACTn MPP( 21, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP22_GPIO MPP( 22, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP22_TSMP2 MPP( 22, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP22_TDM_CH2_TX_QL MPP( 22, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP22_GE1_2 MPP( 22, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP22_AUDIO_SPDIFRMKCLK MPP( 22, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP22_SATA1_PRESENTn MPP( 22, 0x5, 0, 1, 0, 0, 1, 1 ) + +#define MPP23_GPIO MPP( 23, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP23_TSMP3 MPP( 23, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP23_TDM_CH2_RX_QL MPP( 23, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP23_GE1_3 MPP( 23, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP23_AUDIO_I2SBCLK MPP( 23, 0x4, 0, 1, 0, 0, 1, 1 ) +#define MPP23_SATA0_PRESENTn MPP( 23, 0x5, 0, 1, 0, 1, 1, 1 ) + +#define MPP24_GPIO MPP( 24, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP24_TSMP4 MPP( 24, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP24_TDM_SPI_CS0 DEV( 24, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP24_GE1_4 MPP( 24, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP24_AUDIO_I2SDO MPP( 24, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP25_GPIO MPP( 25, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP25_TSMP5 MPP( 25, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP25_TDM_SPI_SCK MPP( 25, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP25_GE1_5 MPP( 25, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP25_AUDIO_I2SLRCLK MPP( 25, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP26_GPIO MPP( 26, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP26_TSMP6 MPP( 26, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP26_TDM_SPI_MISO MPP( 26, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP26_GE1_6 MPP( 26, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP26_AUDIO_I2SMCLK MPP( 26, 0x4, 0, 1, 0, 0, 1, 1 ) + +#define MPP27_GPIO MPP( 27, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP27_TSMP7 MPP( 27, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP27_TDM_SPI_MOSI MPP( 27, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP27_GE1_7 MPP( 27, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP27_AUDIO_I2SDI MPP( 27, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP28_GPIO MPP( 28, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP28_TSMP8 MPP( 28, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP28_TDM_CODEC_INTn MPP( 28, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP28_GE1_8 MPP( 28, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP28_AUDIO_EXTCLK MPP( 28, 0x4, 1, 0, 0, 0, 1, 1 ) + +#define MPP29_GPIO MPP( 29, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP29_TSMP9 MPP( 29, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP29_TDM_CODEC_RSTn MPP( 29, 0x2, 0, 0, 0, 0, 1, 1 ) +#define MPP29_GE1_9 MPP( 29, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP30_GPIO MPP( 30, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP30_TSMP10 MPP( 30, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP30_TDM_PCLK MPP( 30, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP30_GE1_10 MPP( 30, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP31_GPIO MPP( 31, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP31_TSMP11 MPP( 31, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP31_TDM_FS MPP( 31, 0x2, 1, 1, 0, 0, 1, 1 ) +#define MPP31_GE1_11 MPP( 31, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP32_GPIO MPP( 32, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP32_TSMP12 MPP( 32, 0x1, 1, 1, 0, 0, 1, 1 ) +#define MPP32_TDM_DRX MPP( 32, 0x2, 1, 0, 0, 0, 1, 1 ) +#define MPP32_GE1_12 MPP( 32, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP33_GPIO MPP( 33, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP33_TDM_DTX MPP( 33, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP33_GE1_13 MPP( 33, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP34_GPIO MPP( 34, 0x0, 1, 1, 0, 1, 1, 1 ) +#define MPP34_TDM_SPI_CS1 MPP( 34, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP34_GE1_14 MPP( 34, 0x3, 0, 0, 0, 1, 1, 1 ) + +#define MPP35_GPIO MPP( 35, 0x0, 1, 1, 1, 1, 1, 1 ) +#define MPP35_TDM_CH0_TX_QL MPP( 35, 0x2, 0, 1, 0, 0, 1, 1 ) +#define MPP35_GE1_15 MPP( 35, 0x3, 0, 0, 0, 1, 1, 1 ) +#define MPP35_SATA0_ACTn MPP( 35, 0x5, 0, 1, 0, 1, 1, 1 ) +#define MPP35_MII0_RXERR MPP( 35, 0xc, 1, 0, 1, 1, 1, 1 ) + +#define MPP36_GPIO MPP( 36, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP36_TSMP0 MPP( 36, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP36_TDM_SPI_CS1 MPP( 36, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP36_AUDIO_SPDIFI MPP( 36, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP37_GPIO MPP( 37, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP37_TSMP1 MPP( 37, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP37_TDM_CH2_TX_QL MPP( 37, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP37_AUDIO_SPDIFO MPP( 37, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP38_GPIO MPP( 38, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP38_TSMP2 MPP( 38, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP38_TDM_CH2_RX_QL MPP( 38, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP38_AUDIO_SPDIFRMLCLK MPP( 38, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP39_GPIO MPP( 39, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP39_TSMP3 MPP( 39, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP39_TDM_SPI_CS0 MPP( 39, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP39_AUDIO_I2SBCLK MPP( 39, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP40_GPIO MPP( 40, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP40_TSMP4 MPP( 40, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP40_TDM_SPI_SCK MPP( 40, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP40_AUDIO_I2SDO MPP( 40, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP41_GPIO MPP( 41, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP41_TSMP5 MPP( 41, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP41_TDM_SPI_MISO MPP( 41, 0x2, 1, 0, 0, 0, 0, 1 ) +#define MPP41_AUDIO_I2SLRC MPP( 41, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP42_GPIO MPP( 42, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP42_TSMP6 MPP( 42, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP42_TDM_SPI_MOSI MPP( 42, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP42_AUDIO_I2SMCLK MPP( 42, 0x4, 0, 1, 1, 0, 0, 1 ) + +#define MPP43_GPIO MPP( 43, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP43_TSMP7 MPP( 43, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP43_TDM_CODEC_INTn MPP( 43, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP43_AUDIO_I2SDI MPP( 43, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP44_GPIO MPP( 44, 0x0, 1, 1, 1, 0, 0, 1 ) +#define MPP44_TSMP8 MPP( 44, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP44_TDM_CODEC_RSTn MPP( 44, 0x2, 0, 0, 0, 0, 0, 1 ) +#define MPP44_AUDIO_EXTCLK MPP( 44, 0x4, 1, 0, 1, 0, 0, 1 ) + +#define MPP45_GPIO MPP( 45, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TSMP9 MPP( 45, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP45_TDM_PCLK MPP( 45, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP46_GPIO MPP( 46, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TSMP10 MPP( 46, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP46_TDM_FS MPP( 46, 0x2, 1, 1, 0, 0, 0, 1 ) + +#define MPP47_GPIO MPP( 47, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TSMP11 MPP( 47, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP47_TDM_DRX MPP( 47, 0x2, 1, 0, 0, 0, 0, 1 ) + +#define MPP48_GPIO MPP( 48, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TSMP12 MPP( 48, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP48_TDM_DTX MPP( 48, 0x2, 0, 1, 0, 0, 0, 1 ) + +#define MPP49_GPIO MPP( 49, 0x0, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TSMP9 MPP( 49, 0x1, 1, 1, 0, 0, 0, 1 ) +#define MPP49_TDM_CH0_RX_QL MPP( 49, 0x2, 0, 1, 0, 0, 0, 1 ) +#define MPP49_PTP_CLK MPP( 49, 0x5, 1, 0, 0, 0, 0, 1 ) + +#define MPP_MAX 49 + +void kirkwood_mpp_conf(const u32 *mpp_list, u32 *mpp_save); + +#endif diff --git a/arch/arm/mach-kirkwood/include/mach/soc.h b/arch/arm/mach-kirkwood/include/mach/soc.h new file mode 100644 index 00000000000..58ed71b1864 --- /dev/null +++ b/arch/arm/mach-kirkwood/include/mach/soc.h @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor + * Written-by: Prafulla Wadaskar + * + * Header file for the Marvell's Feroceon CPU core. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_KIRKWOOD_H +#define _ASM_ARCH_KIRKWOOD_H + +#if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131) + +/* SOC specific definations */ +#define INTREG_BASE 0xd0000000 +#define KW_REGISTER(x) (KW_REGS_PHY_BASE + x) +#define KW_OFFSET_REG (INTREG_BASE + 0x20080) + +/* undocumented registers */ +#define KW_REG_UNDOC_0x1470 (KW_REGISTER(0x1470)) +#define KW_REG_UNDOC_0x1478 (KW_REGISTER(0x1478)) + +#define MVEBU_SDRAM_BASE (KW_REGISTER(0x1500)) +#define KW_TWSI_BASE (KW_REGISTER(0x11000)) +#define KW_UART0_BASE (KW_REGISTER(0x12000)) +#define KW_UART1_BASE (KW_REGISTER(0x12100)) +#define KW_MPP_BASE (KW_REGISTER(0x10000)) +#define MVEBU_GPIO0_BASE (KW_REGISTER(0x10100)) +#define MVEBU_GPIO1_BASE (KW_REGISTER(0x10140)) +#define KW_RTC_BASE (KW_REGISTER(0x10300)) +#define KW_NANDF_BASE (KW_REGISTER(0x10418)) +#define MVEBU_SPI_BASE (KW_REGISTER(0x10600)) +#define KW_CPU_WIN_BASE (KW_REGISTER(0x20000)) +#define KW_CPU_REG_BASE (KW_REGISTER(0x20100)) +#define MVEBU_TIMER_BASE (KW_REGISTER(0x20300)) +#define KW_REG_PCIE_BASE (KW_REGISTER(0x40000)) +#define KW_USB20_BASE (KW_REGISTER(0x50000)) +#define KW_EGIGA0_BASE (KW_REGISTER(0x72000)) +#define KW_EGIGA1_BASE (KW_REGISTER(0x76000)) +#define KW_SATA_BASE (KW_REGISTER(0x80000)) +#define KW_SDIO_BASE (KW_REGISTER(0x90000)) + +/* Kirkwood Sata controller has two ports */ +#define KW_SATA_PORT0_OFFSET 0x2000 +#define KW_SATA_PORT1_OFFSET 0x4000 + +/* Kirkwood GbE controller has two ports */ +#define MAX_MVGBE_DEVS 2 +#define MVGBE0_BASE KW_EGIGA0_BASE +#define MVGBE1_BASE KW_EGIGA1_BASE + +/* Kirkwood USB Host controller */ +#define MVUSB0_BASE KW_USB20_BASE +#define MVUSB0_CPU_ATTR_DRAM_CS0 KWCPU_ATTR_DRAM_CS0 +#define MVUSB0_CPU_ATTR_DRAM_CS1 KWCPU_ATTR_DRAM_CS1 +#define MVUSB0_CPU_ATTR_DRAM_CS2 KWCPU_ATTR_DRAM_CS2 +#define MVUSB0_CPU_ATTR_DRAM_CS3 KWCPU_ATTR_DRAM_CS3 + +/* Kirkwood CPU memory windows */ +#define MVCPU_WIN_CTRL_DATA KWCPU_WIN_CTRL_DATA +#define MVCPU_WIN_ENABLE KWCPU_WIN_ENABLE +#define MVCPU_WIN_DISABLE KWCPU_WIN_DISABLE + +#if defined (CONFIG_KW88F6281) +#include +#elif defined (CONFIG_KW88F6192) +#include +#else +#error "SOC Name not defined" +#endif /* CONFIG_KW88F6281 */ +#endif /* CONFIG_FEROCEON_88FR131 */ +#endif /* _ASM_ARCH_KIRKWOOD_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h index f780f8b5bba..2ed0855fdd8 100644 --- a/include/configs/km/km_arm.h +++ b/include/configs/km/km_arm.h @@ -195,7 +195,7 @@ } #ifndef __ASSEMBLY__ -#include +#include extern void __set_direction(unsigned pin, int high); void set_sda(int state); void set_scl(int state); -- cgit v1.3.1 From a033171b2ece1f3575ab7277e7b862e7f611b3f6 Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 16 Feb 2015 12:16:13 -0700 Subject: bcm2835/rpi: add SPDX license tags for some files Signed-off-by: Stephen Warren --- arch/arm/cpu/arm1176/bcm2835/Makefile | 12 ++---------- arch/arm/include/asm/arch-bcm2835/sdhci.h | 12 +----------- arch/arm/include/asm/arch-bcm2835/timer.h | 12 +----------- arch/arm/include/asm/arch-bcm2835/wdog.h | 12 +----------- board/raspberrypi/rpi/Makefile | 12 ++---------- board/raspberrypi/rpi/rpi.c | 12 +----------- include/configs/rpi.h | 12 +----------- 7 files changed, 9 insertions(+), 75 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/arm1176/bcm2835/Makefile b/arch/arm/cpu/arm1176/bcm2835/Makefile index 0ad36906dfc..7e5dbe1fdea 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Makefile +++ b/arch/arm/cpu/arm1176/bcm2835/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := lowlevel_init.o diff --git a/arch/arm/include/asm/arch-bcm2835/sdhci.h b/arch/arm/include/asm/arch-bcm2835/sdhci.h index a4f867b2e9a..da4d5cd5a88 100644 --- a/arch/arm/include/asm/arch-bcm2835/sdhci.h +++ b/arch/arm/include/asm/arch-bcm2835/sdhci.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_SDHCI_H_ diff --git a/arch/arm/include/asm/arch-bcm2835/timer.h b/arch/arm/include/asm/arch-bcm2835/timer.h index c2001b6f932..2d7cfe5c56f 100644 --- a/arch/arm/include/asm/arch-bcm2835/timer.h +++ b/arch/arm/include/asm/arch-bcm2835/timer.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_TIMER_H diff --git a/arch/arm/include/asm/arch-bcm2835/wdog.h b/arch/arm/include/asm/arch-bcm2835/wdog.h index 303a65f32e0..f369ab589c9 100644 --- a/arch/arm/include/asm/arch-bcm2835/wdog.h +++ b/arch/arm/include/asm/arch-bcm2835/wdog.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef _BCM2835_TIMER_H diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile index c53c92b1ddb..4ce2c983b38 100644 --- a/board/raspberrypi/rpi/Makefile +++ b/board/raspberrypi/rpi/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := rpi.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index 948078b958f..fdbf87d6fa7 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -1,17 +1,7 @@ /* * (C) Copyright 2012-2013 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 7ad8d080215..9b32149b0ea 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -1,17 +1,7 @@ /* * (C) Copyright 2012 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #ifndef __CONFIG_H -- cgit v1.3.1 From 46414296953410706e917cef9238926084e83a4b Mon Sep 17 00:00:00 2001 From: Stephen Warren Date: Mon, 16 Feb 2015 12:16:15 -0700 Subject: rpi: add support for Raspberry Pi 2 model B USB doesn't seem to work yet; the controller detects the on-board Hub/ Ethernet device but can't read the descriptors from it. I haven't investigated yet. Signed-off-by: Stephen Warren --- arch/arm/Kconfig | 5 + arch/arm/cpu/arm1176/bcm2835/Kconfig | 2 +- arch/arm/include/asm/arch-bcm2835/mbox.h | 4 + board/raspberrypi/rpi/rpi.c | 28 ++++- board/raspberrypi/rpi_2/Kconfig | 15 +++ board/raspberrypi/rpi_2/MAINTAINERS | 6 + board/raspberrypi/rpi_2/Makefile | 7 ++ configs/rpi_2_defconfig | 4 + include/configs/rpi-common.h | 186 +++++++++++++++++++++++++++++++ include/configs/rpi.h | 168 +--------------------------- include/configs/rpi_2.h | 15 +++ 11 files changed, 271 insertions(+), 169 deletions(-) create mode 100644 board/raspberrypi/rpi_2/Kconfig create mode 100644 board/raspberrypi/rpi_2/MAINTAINERS create mode 100644 board/raspberrypi/rpi_2/Makefile create mode 100644 configs/rpi_2_defconfig create mode 100644 include/configs/rpi-common.h create mode 100644 include/configs/rpi_2.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 083823e8c41..820ba1ccaba 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -310,6 +310,10 @@ config TARGET_RPI bool "Support rpi" select CPU_ARM1176 +config TARGET_RPI_2 + bool "Support rpi_2" + select CPU_V7 + config TARGET_TNETV107X_EVM bool "Support tnetv107x_evm" select CPU_ARM1176 @@ -830,6 +834,7 @@ source "board/phytec/pcm051/Kconfig" source "board/ppcag/bg0900/Kconfig" source "board/pxa255_idp/Kconfig" source "board/raspberrypi/rpi/Kconfig" +source "board/raspberrypi/rpi_2/Kconfig" source "board/samsung/smdk2410/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig index 94f57d732fe..162f973f6cc 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -1,4 +1,4 @@ -if TARGET_RPI +if TARGET_RPI || TARGET_RPI_2 config DM default y if !SPL_BUILD diff --git a/arch/arm/include/asm/arch-bcm2835/mbox.h b/arch/arm/include/asm/arch-bcm2835/mbox.h index c4bbacaf3c3..04bf480a549 100644 --- a/arch/arm/include/asm/arch-bcm2835/mbox.h +++ b/arch/arm/include/asm/arch-bcm2835/mbox.h @@ -125,6 +125,9 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_MBOX_TAG_GET_BOARD_REV 0x00010002 +#ifdef CONFIG_BCM2836 +#define BCM2836_BOARD_REV_2_B 0x4 +#else /* * 0x2..0xf from: * http://raspberryalphaomega.org.uk/2013/02/06/automatic-raspberry-pi-board-revision-detection-model-a-b1-and-b2/ @@ -145,6 +148,7 @@ struct bcm2835_mbox_tag_hdr { #define BCM2835_BOARD_REV_B_PLUS 0x10 #define BCM2835_BOARD_REV_CM 0x11 #define BCM2835_BOARD_REV_A_PLUS 0x12 +#endif struct bcm2835_mbox_tag_get_board_rev { struct bcm2835_mbox_tag_hdr tag_hdr; diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index fdbf87d6fa7..50a699bb9e0 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2012-2013 Stephen Warren + * (C) Copyright 2012-2013,2015 Stephen Warren * * SPDX-License-Identifier: GPL-2.0 */ @@ -29,7 +29,11 @@ U_BOOT_DEVICE(bcm2835_gpios) = { }; static const struct pl01x_serial_platdata serial_platdata = { +#ifdef CONFIG_BCM2836 + .base = 0x3f201000, +#else .base = 0x20201000, +#endif .type = TYPE_PL011, .clock = 3000000, }; @@ -77,9 +81,20 @@ static const struct { } models[] = { [0] = { "Unknown model", +#ifdef CONFIG_BCM2836 + "bcm2836-rpi-other.dtb", +#else "bcm2835-rpi-other.dtb", +#endif false, }, +#ifdef CONFIG_BCM2836 + [BCM2836_BOARD_REV_2_B] = { + "2 Model B", + "bcm2836-rpi-2-b.dtb", + true, + }, +#else [BCM2835_BOARD_REV_B_I2C0_2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", @@ -150,6 +165,7 @@ static const struct { "bcm2835-rpi-a-plus.dtb", false, }, +#endif }; u32 rpi_board_rev = 0; @@ -257,7 +273,15 @@ static void get_board_rev(void) return; } + /* + * For details of old-vs-new scheme, see: + * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282 + * (a few posts down) + */ rpi_board_rev = msg->get_board_rev.body.resp.rev; + if (rpi_board_rev & 0x800000) + rpi_board_rev = (rpi_board_rev >> 4) & 0xff; if (rpi_board_rev >= ARRAY_SIZE(models)) { printf("RPI: Board rev %u outside known range\n", rpi_board_rev); @@ -269,7 +293,7 @@ static void get_board_rev(void) } name = models[rpi_board_rev].name; - printf("RPI model: %s\n", name); + printf("RPI %s\n", name); } int board_init(void) diff --git a/board/raspberrypi/rpi_2/Kconfig b/board/raspberrypi/rpi_2/Kconfig new file mode 100644 index 00000000000..032184d5ad5 --- /dev/null +++ b/board/raspberrypi/rpi_2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_RPI_2 + +config SYS_BOARD + default "rpi_2" + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm2835" + +config SYS_CONFIG_NAME + default "rpi_2" + +endif diff --git a/board/raspberrypi/rpi_2/MAINTAINERS b/board/raspberrypi/rpi_2/MAINTAINERS new file mode 100644 index 00000000000..85a480c9d1b --- /dev/null +++ b/board/raspberrypi/rpi_2/MAINTAINERS @@ -0,0 +1,6 @@ +RPI_2 BOARD +M: Stephen Warren +S: Maintained +F: board/raspberrypi/rpi_2/ +F: include/configs/rpi_2.h +F: configs/rpi_2_defconfig diff --git a/board/raspberrypi/rpi_2/Makefile b/board/raspberrypi/rpi_2/Makefile new file mode 100644 index 00000000000..d82cd21f4cf --- /dev/null +++ b/board/raspberrypi/rpi_2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2012,2015 Stephen Warren +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := ../rpi/rpi.o diff --git a/configs/rpi_2_defconfig b/configs/rpi_2_defconfig new file mode 100644 index 00000000000..b539d4a689e --- /dev/null +++ b/configs/rpi_2_defconfig @@ -0,0 +1,4 @@ +CONFIG_ARM=y +CONFIG_TARGET_RPI_2=y +CONFIG_SYS_MALLOC_F=y +CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/include/configs/rpi-common.h b/include/configs/rpi-common.h new file mode 100644 index 00000000000..3121ac9874a --- /dev/null +++ b/include/configs/rpi-common.h @@ -0,0 +1,186 @@ +/* + * (C) Copyright 2012,2015 Stephen Warren + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _RPI_COMMON_H_ +#define _RPI_COMMON_H_ + +#include + +/* Architecture, CPU, etc.*/ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_BCM2835 +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_SYS_DCACHE_OFF +/* + * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, + * so 2708 has historically been used rather than a dedicated 2835 ID. + * + * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation + * chose to use someone else's previously registered machine ID (3139, MX51_GGC) + * rather than obtaining a valid ID:-/ + */ +#ifndef CONFIG_BCM2836 +#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 +#endif + +/* Memory layout */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_TEXT_BASE 0x00008000 +#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE +/* + * The board really has 256M. However, the VC (VideoCore co-processor) shares + * the RAM, and uses a configurable portion at the top. We tell U-Boot that a + * smaller amount of RAM is present in order to avoid stomping on the area + * the VC uses. + */ +#define CONFIG_SYS_SDRAM_SIZE SZ_128M +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_SDRAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_MEMTEST_START 0x00100000 +#define CONFIG_SYS_MEMTEST_END 0x00200000 +#define CONFIG_LOADADDR 0x00200000 + +/* Flash */ +#define CONFIG_SYS_NO_FLASH + +/* Devices */ +/* GPIO */ +#define CONFIG_BCM2835_GPIO +/* LCD */ +#define CONFIG_LCD +#define CONFIG_LCD_DT_SIMPLEFB +#define LCD_BPP LCD_COLOR16 +/* + * Prevent allocation of RAM for FB; the real FB address is queried + * dynamically from the VideoCore co-processor, and comes from RAM + * not owned by the ARM CPU. + */ +#define CONFIG_FB_ADDR 0 +#define CONFIG_VIDEO_BCM2835 +#define CONFIG_SYS_WHITE_ON_BLACK + +/* SD/MMC configuration */ +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_SDHCI +#define CONFIG_MMC_SDHCI_IO_ACCESSORS +#define CONFIG_BCM2835_SDHCI + +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#ifdef CONFIG_BCM2836 +#define CONFIG_USB_DWC2_REG_ADDR 0x3f980000 +#else +#define CONFIG_USB_DWC2_REG_ADDR 0x20980000 +#endif +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MISC_INIT_R +#endif + +/* Console UART */ +#define CONFIG_PL01X_SERIAL +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* Environment */ +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_ENV_IS_IN_FAT +#define FAT_ENV_INTERFACE "mmc" +#define FAT_ENV_DEVICE_AND_PART "0:1" +#define FAT_ENV_FILE "uboot.env" +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG +#define CONFIG_SYS_LOAD_ADDR 0x1000000 +#define CONFIG_CONSOLE_MUX +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +/* Shell */ +#define CONFIG_SYS_MAXARGS 8 +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_COMMAND_HISTORY + +/* Commands */ +#include +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MMC +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +/* Device tree support */ +#define CONFIG_OF_BOARD_SETUP +/* ATAGs support for bootm/bootz */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG + +#include + +/* Some things don't make sense on this HW or yet */ +#undef CONFIG_CMD_FPGA + +/* Environment */ +#define ENV_DEVICE_SETTINGS \ + "stdin=serial,lcd\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +/* + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it low in memory to avoid conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it low in memory to avoid conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 16M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for + * the compressed kernel to be up to 16M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. + */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "kernel_addr_r=0x01000000\0" \ + "fdt_addr_r=0x02000000\0" \ + "ramdisk_addr_r=0x02100000\0" \ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(PXE, pxe, na) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + ENV_DEVICE_SETTINGS \ + ENV_MEM_LAYOUT_SETTINGS \ + BOOTENV + +#define CONFIG_BOOTDELAY 2 + +#endif diff --git a/include/configs/rpi.h b/include/configs/rpi.h index 9b32149b0ea..ab2f4db39fe 100644 --- a/include/configs/rpi.h +++ b/include/configs/rpi.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2012 Stephen Warren + * (C) Copyright 2012,2015 Stephen Warren * * SPDX-License-Identifier: GPL-2.0 */ @@ -7,170 +7,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include - -/* Architecture, CPU, etc.*/ -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_BCM2835 -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_DCACHE_OFF -/* - * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, - * so 2708 has historically been used rather than a dedicated 2835 ID. - */ -#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 - -/* Memory layout */ -#define CONFIG_NR_DRAM_BANKS 1 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_TEXT_BASE 0x00008000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* - * The board really has 256M. However, the VC (VideoCore co-processor) shares - * the RAM, and uses a configurable portion at the top. We tell U-Boot that a - * smaller amount of RAM is present in order to avoid stomping on the area - * the VC uses. - */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00200000 -#define CONFIG_LOADADDR 0x00200000 - -/* Flash */ -#define CONFIG_SYS_NO_FLASH - -/* Devices */ -/* GPIO */ -#define CONFIG_BCM2835_GPIO -/* LCD */ -#define CONFIG_LCD -#define CONFIG_LCD_DT_SIMPLEFB -#define LCD_BPP LCD_COLOR16 -/* - * Prevent allocation of RAM for FB; the real FB address is queried - * dynamically from the VideoCore co-processor, and comes from RAM - * not owned by the ARM CPU. - */ -#define CONFIG_FB_ADDR 0 -#define CONFIG_VIDEO_BCM2835 -#define CONFIG_SYS_WHITE_ON_BLACK - -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_MMC_SDHCI_IO_ACCESSORS -#define CONFIG_BCM2835_SDHCI - -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2 -#define CONFIG_USB_DWC2_REG_ADDR 0x20980000 -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MISC_INIT_R -#endif - -/* Console UART */ -#define CONFIG_PL01X_SERIAL -#define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 115200 - -/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Environment */ -#define CONFIG_ENV_SIZE SZ_16K -#define CONFIG_ENV_IS_IN_FAT -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_DEVICE_AND_PART "0:1" -#define FAT_ENV_FILE "uboot.env" -#define CONFIG_FAT_WRITE -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_SYS_LOAD_ADDR 0x1000000 -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Shell */ -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_PROMPT "U-Boot> " -#define CONFIG_COMMAND_HISTORY - -/* Commands */ -#include -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_MMC -#define CONFIG_PARTITION_UUIDS -#define CONFIG_CMD_PART - -/* Device tree support */ -#define CONFIG_OF_BOARD_SETUP -/* ATAGs support for bootm/bootz */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -#include - -/* Some things don't make sense on this HW or yet */ -#undef CONFIG_CMD_FPGA - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial,lcd\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it low in memory to avoid conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it low in memory to avoid conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00000000\0" \ - "pxefile_addr_r=0x00100000\0" \ - "kernel_addr_r=0x01000000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02100000\0" \ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_DEVICE_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV - -#define CONFIG_BOOTDELAY 2 +#include "rpi-common.h" #endif diff --git a/include/configs/rpi_2.h b/include/configs/rpi_2.h new file mode 100644 index 00000000000..2e7e74fd563 --- /dev/null +++ b/include/configs/rpi_2.h @@ -0,0 +1,15 @@ +/* + * (C) Copyright 2012,2015 Stephen Warren + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BCM2836 + +#include "rpi-common.h" + +#endif -- cgit v1.3.1 From f3133962f469a8b6b9ba237ba670f0ca7c88a02e Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Fri, 20 Feb 2015 16:55:12 +0100 Subject: sunxi: Set the /chosen/stdout-path fdt property for sunxi boards While discussing with some people how to get the Linux kernel to do the right thing wrt sending output to both the serial console and the hdmi out / lcd screen when booting on ARM devices, Grant Likely pointed out that there already is a solution for this. All we need to do is set the /chosen/stdout-path fdt property, and if no console= arguments were specified on the kernel commandline the kernel will honor this and add this device as a console (next to the primary video output on hdmi). And u-boot already has support for setting this, all we need to do is define OF_STDOUT_PATH and then everything will just work ootb, without people needing to meddle with adding console= arguments in extlinux.conf . Signed-off-by: Hans de Goede Acked-by: Ian Campbell Reviewed-by: Tom Rini --- include/configs/sunxi-common.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'include') diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index f5efebbf282..0b4f0a07b73 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -210,6 +210,20 @@ extern int soft_i2c_gpio_scl; #define CONFIG_CONS_INDEX 1 /* UART0 */ #endif +#if CONFIG_CONS_INDEX == 1 +#ifdef CONFIG_MACH_SUN9I +#define OF_STDOUT_PATH "/soc/serial@07000000:115200" +#else +#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" +#endif +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) +#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" +#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) +#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" +#else +#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. +#endif + /* GPIO */ #define CONFIG_SUNXI_GPIO #define CONFIG_SPL_GPIO_SUPPORT -- cgit v1.3.1 From 77ef136950b4649ff4844c3b72dab107a9c565a0 Mon Sep 17 00:00:00 2001 From: Siarhei Siamashka Date: Sat, 21 Feb 2015 07:34:09 +0200 Subject: sunxi: Machine id hack to prevent loading buggy sunxi-3.4 kernels Right now U-Boot supports the CONFIG_OLD_SUNXI_KERNEL_COMPAT option, which makes it go out of its way in limiting the selection of PLL clock frequencies and PMIC voltages in order not to upset outdated buggy sunxi-3.4 kernel releases. And if the CONFIG_OLD_SUNXI_KERNEL_COMPAT option is not set, then booting such old kernels exhibits various failures at runtime. This is very user unfriendly, and there were already several incidents when people wasted their time being hit by these runtime failures and trying to debug them. The right solution is not to add hacks and workarounds to the mainline U-Boot, but to fix these bugs in the sunxi-3.4 kernel. And in fact, the updated sunxi-3.4 kernels already exist. Still we need to follow the 'Principle of Least Surprise' and U-Boot needs to ensure that the old buggy kernels are not getting happily booted when the CONFIG_OLD_SUNXI_KERNEL_COMPAT option is not set. And this patch addresses this particular issue. This patch makes U-Boot store the 'compatibility revision' number in the top 4 bits of the machine id and pass it to the kernel. The old buggy kernels will fail to load with a very much googlable error message on the serial console (the "r1 = 0x100010bb" part of it): "Error: unrecognized/unsupported machine ID (r1 = 0x100010bb)" This error message can be documented in the linux-sunxi wiki with proper explanations about how to resolve this situation and where to get the necessary bugfixes for the sunxi-3.4 kernel. The fixed sunxi-3.4 kernels implement a revision compatibility check and clear the top 4 bits of the machine id if everything is alright. By accepting the machine id with the bits 31:28 set to 1, the sunxi-3.4 kernel effectively certifies that it has the PLL5 clock speed and AXP209 DCDC3 voltage fixes applied. It is still possible to set the CONFIG_OLD_SUNXI_KERNEL_COMPAT option in U-Boot if the user desires to use an outdated unpatched sunxi-3.4 kernel. Signed-off-by: Siarhei Siamashka Acked-by: Ian Campbell Acked-by: Hans de Goede Signed-off-by: Hans de Goede --- include/configs/sun4i.h | 4 ++-- include/configs/sun5i.h | 4 ++-- include/configs/sun7i.h | 4 ++-- include/configs/sunxi-common.h | 16 ++++++++++++++++ 4 files changed, 22 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 87d269b041c..1537e536f92 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -13,8 +13,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_MACH_TYPE 4104 - #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -25,4 +23,6 @@ */ #include +#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + #endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h index 52e3a6ff01b..e7555313dbe 100644 --- a/include/configs/sun5i.h +++ b/include/configs/sun5i.h @@ -13,8 +13,6 @@ */ #define CONFIG_CLK_FULL_SPEED 1008000000 -#define CONFIG_MACH_TYPE 4138 - #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 1 @@ -25,4 +23,6 @@ */ #include +#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + #endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h index 7cd78903412..f817f73076e 100644 --- a/include/configs/sun7i.h +++ b/include/configs/sun7i.h @@ -14,8 +14,6 @@ */ #define CONFIG_CLK_FULL_SPEED 912000000 -#define CONFIG_MACH_TYPE 4283 - #ifdef CONFIG_USB_EHCI #define CONFIG_USB_EHCI_SUNXI #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 @@ -31,4 +29,6 @@ */ #include +#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) + #endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 0b4f0a07b73..bd7d049277c 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -13,6 +13,22 @@ #ifndef _SUNXI_COMMON_CONFIG_H #define _SUNXI_COMMON_CONFIG_H +#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT +/* + * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the + * expense of restricting some features, so the regular machine id values can + * be used. + */ +# define CONFIG_MACH_TYPE_COMPAT_REV 0 +#else +/* + * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. + * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass + * beyond the machine id check. + */ +# define CONFIG_MACH_TYPE_COMPAT_REV 1 +#endif + /* * High Level Configuration Options */ -- cgit v1.3.1 From 4b7cee533630202095748ecb396bd9eacf47ff3f Mon Sep 17 00:00:00 2001 From: Pantelis Antoniou Date: Fri, 23 Jan 2015 12:12:01 +0200 Subject: mmc: Implement SD/MMC versioning properly The SD/MMC version scheme was buggy when dealing with standard major.minor.change cases. Fix it by using something similar to the linux's kernel versioning method. Signed-off-by: Pantelis Antoniou Tested-by: Jaehoon Chung Reported-by: Stephen Warren Tested-by: Stephen Warren --- common/cmd_mmc.c | 8 ++++++-- include/mmc.h | 56 +++++++++++++++++++++++++++++++++++++------------------- 2 files changed, 43 insertions(+), 21 deletions(-) (limited to 'include') diff --git a/common/cmd_mmc.c b/common/cmd_mmc.c index 4e28c9d7a4d..1335e3d344c 100644 --- a/common/cmd_mmc.c +++ b/common/cmd_mmc.c @@ -85,8 +85,12 @@ static void print_mmcinfo(struct mmc *mmc) printf("Tran Speed: %d\n", mmc->tran_speed); printf("Rd Block Len: %d\n", mmc->read_bl_len); - printf("%s version %d.%d\n", IS_SD(mmc) ? "SD" : "MMC", - (mmc->version >> 8) & 0xf, mmc->version & 0xff); + printf("%s version %d.%d", IS_SD(mmc) ? "SD" : "MMC", + EXTRACT_SDMMC_MAJOR_VERSION(mmc->version), + EXTRACT_SDMMC_MINOR_VERSION(mmc->version)); + if (EXTRACT_SDMMC_CHANGE_VERSION(mmc->version) != 0) + printf(".%d", EXTRACT_SDMMC_CHANGE_VERSION(mmc->version)); + printf("\n"); printf("High Capacity: %s\n", mmc->high_capacity ? "Yes" : "No"); puts("Capacity: "); diff --git a/include/mmc.h b/include/mmc.h index 56d97bbdcf5..7d6feca5b40 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -14,24 +14,41 @@ #include #include -#define SD_VERSION_SD 0x20000 -#define SD_VERSION_3 (SD_VERSION_SD | 0x300) -#define SD_VERSION_2 (SD_VERSION_SD | 0x200) -#define SD_VERSION_1_0 (SD_VERSION_SD | 0x100) -#define SD_VERSION_1_10 (SD_VERSION_SD | 0x10a) -#define MMC_VERSION_MMC 0x10000 -#define MMC_VERSION_UNKNOWN (MMC_VERSION_MMC) -#define MMC_VERSION_1_2 (MMC_VERSION_MMC | 0x102) -#define MMC_VERSION_1_4 (MMC_VERSION_MMC | 0x104) -#define MMC_VERSION_2_2 (MMC_VERSION_MMC | 0x202) -#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x300) -#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x400) -#define MMC_VERSION_4_1 (MMC_VERSION_MMC | 0x401) -#define MMC_VERSION_4_2 (MMC_VERSION_MMC | 0x402) -#define MMC_VERSION_4_3 (MMC_VERSION_MMC | 0x403) -#define MMC_VERSION_4_41 (MMC_VERSION_MMC | 0x429) -#define MMC_VERSION_4_5 (MMC_VERSION_MMC | 0x405) -#define MMC_VERSION_5_0 (MMC_VERSION_MMC | 0x500) +/* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */ +#define SD_VERSION_SD (1U << 31) +#define MMC_VERSION_MMC (1U << 30) + +#define MAKE_SDMMC_VERSION(a, b, c) \ + ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c)) +#define MAKE_SD_VERSION(a, b, c) \ + (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c)) +#define MAKE_MMC_VERSION(a, b, c) \ + (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c)) + +#define EXTRACT_SDMMC_MAJOR_VERSION(x) \ + (((u32)(x) >> 16) & 0xff) +#define EXTRACT_SDMMC_MINOR_VERSION(x) \ + (((u32)(x) >> 8) & 0xff) +#define EXTRACT_SDMMC_CHANGE_VERSION(x) \ + ((u32)(x) & 0xff) + +#define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0) +#define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0) +#define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0) +#define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0) + +#define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0) +#define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0) +#define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0) +#define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0) +#define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0) +#define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0) +#define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0) +#define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0) +#define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0) +#define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1) +#define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0) +#define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0) #define MMC_MODE_HS (1 << 0) #define MMC_MODE_HS_52MHz (1 << 1) @@ -43,7 +60,8 @@ #define SD_DATA_4BIT 0x00040000 -#define IS_SD(x) (x->version & SD_VERSION_SD) +#define IS_SD(x) ((x)->version & SD_VERSION_SD) +#define IS_MMC(x) ((x)->version & SD_VERSION_MMC) #define MMC_DATA_READ 1 #define MMC_DATA_WRITE 2 -- cgit v1.3.1 From 5dab81cea5500558b7bfc43a7364ae7ed706d2fc Mon Sep 17 00:00:00 2001 From: Jaehoon Chung Date: Wed, 4 Feb 2015 15:48:40 +0900 Subject: mmc: exynos_dw_mmc: use the exynos specific data structure Clksel value is exynos specific value. It removed "clksel_val" into dwmci_host and created the "dwmci_exynos_priv_data" structure for exynos specific data. Signed-off-by: Jaehoon Chung --- drivers/mmc/exynos_dw_mmc.c | 60 +++++++++++++++++++++++++++++++++++---------- include/dwmmc.h | 2 +- 2 files changed, 48 insertions(+), 14 deletions(-) (limited to 'include') diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c index 3936660892e..c66c0b0bf83 100644 --- a/drivers/mmc/exynos_dw_mmc.c +++ b/drivers/mmc/exynos_dw_mmc.c @@ -19,8 +19,13 @@ #define DWMMC_MAX_CH_NUM 4 #define DWMMC_MAX_FREQ 52000000 #define DWMMC_MIN_FREQ 400000 -#define DWMMC_MMC0_CLKSEL_VAL 0x03030001 -#define DWMMC_MMC2_CLKSEL_VAL 0x03020001 +#define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001 +#define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001 + +/* Exynos implmentation specific drver private data */ +struct dwmci_exynos_priv_data { + u32 sdr_timing; +}; /* * Function used as callback function to initialise the @@ -28,7 +33,9 @@ */ static void exynos_dwmci_clksel(struct dwmci_host *host) { - dwmci_writel(host, DWMCI_CLKSEL, host->clksel_val); + struct dwmci_exynos_priv_data *priv = host->priv; + + dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing); } unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) @@ -55,6 +62,8 @@ unsigned int exynos_dwmci_get_clk(struct dwmci_host *host) static void exynos_dwmci_board_init(struct dwmci_host *host) { + struct dwmci_exynos_priv_data *priv = host->priv; + if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) { dwmci_writel(host, EMMCP_MPSBEGIN0, 0); dwmci_writel(host, EMMCP_SEND0, 0); @@ -65,8 +74,8 @@ static void exynos_dwmci_board_init(struct dwmci_host *host) MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID); } - /* Set to clksel_val at initial time */ - if (host->clksel_val) + /* Set to timing value at initial time */ + if (priv->sdr_timing) exynos_dwmci_clksel(host); } @@ -74,6 +83,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) { unsigned int div; unsigned long freq, sclk; + struct dwmci_exynos_priv_data *priv = host->priv; if (host->bus_hz) freq = host->bus_hz; @@ -92,11 +102,11 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) #endif host->board_init = exynos_dwmci_board_init; - if (!host->clksel_val) { + if (!priv->sdr_timing) { if (index == 0) - host->clksel_val = DWMMC_MMC0_CLKSEL_VAL; + priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; else if (index == 2) - host->clksel_val = DWMMC_MMC2_CLKSEL_VAL; + priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; } host->caps = MMC_MODE_DDR_52MHz; @@ -122,6 +132,7 @@ static int exynos_dwmci_core_init(struct dwmci_host *host, int index) int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) { struct dwmci_host *host = NULL; + struct dwmci_exynos_priv_data *priv; host = malloc(sizeof(struct dwmci_host)); if (!host) { @@ -129,11 +140,19 @@ int exynos_dwmci_add_port(int index, u32 regbase, int bus_width, u32 clksel) return -ENOMEM; } + priv = malloc(sizeof(struct dwmci_exynos_priv_data)); + if (!priv) { + error("dwmci_exynos_priv_data malloc fail!\n"); + return -ENOMEM; + } + host->ioaddr = (void *)regbase; host->buswidth = bus_width; if (clksel) - host->clksel_val = clksel; + priv->sdr_timing = clksel; + + host->priv = priv; return exynos_dwmci_core_init(host, index); } @@ -161,7 +180,14 @@ static int exynos_dwmci_get_config(const void *blob, int node, struct dwmci_host *host) { int err = 0; - u32 base, clksel_val, timing[3]; + u32 base, timing[3]; + struct dwmci_exynos_priv_data *priv; + + priv = malloc(sizeof(struct dwmci_exynos_priv_data)); + if (!priv) { + error("dwmci_exynos_priv_data malloc fail!\n"); + return -ENOMEM; + } /* Extract device id for each mmc channel */ host->dev_id = pinmux_decode_periph_id(blob, node); @@ -194,16 +220,24 @@ static int exynos_dwmci_get_config(const void *blob, int node, return -EINVAL; } - clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) | + priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) | DWMCI_SET_DRV_CLK(timing[1]) | DWMCI_SET_DIV_RATIO(timing[2])); - if (clksel_val) - host->clksel_val = clksel_val; + + /* sdr_timing didn't assigned anything, use the default value */ + if (!priv->sdr_timing) { + if (host->dev_index == 0) + priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL; + else if (host->dev_index == 2) + priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL; + } host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0); host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0); host->div = fdtdec_get_int(blob, node, "div", 0); + host->priv = priv; + return 0; } diff --git a/include/dwmmc.h b/include/dwmmc.h index 109f7c8ac7f..86a54918f90 100644 --- a/include/dwmmc.h +++ b/include/dwmmc.h @@ -141,9 +141,9 @@ struct dwmci_host { int dev_index; int dev_id; int buswidth; - u32 clksel_val; u32 fifoth_val; struct mmc *mmc; + void *priv; void (*clksel)(struct dwmci_host *host); void (*board_init)(struct dwmci_host *host); -- cgit v1.3.1 From 9c66ce662c076fc1f5e57c4e72126e41d56d0b80 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 6 Jan 2015 13:11:21 -0800 Subject: fsl-ch3/lowlevel: TZPC and TZASC programming to configure non-secure accesses This patch ensures that the TZPC (BP147) and TZASC-400 programming happens for LS2085A SoC only when the desired config flags are enabled and ensures that the TZPC programming is done to allow Non-secure (NS) + secure (S) transactions only for DCGF registers. The TZASC component is not present on LS2085A-Rev1, so the TZASC-400 config flag is turned OFF for now. Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S | 54 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-fsl-lsch3/config.h | 28 +++++++++++++++ doc/README.fsl-trustzone-components | 25 +++++++++++++ include/configs/ls2085a_common.h | 1 + 4 files changed, 108 insertions(+) create mode 100644 doc/README.fsl-trustzone-components (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S index 2a88aab283d..c2837876b16 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S @@ -42,6 +42,60 @@ ENTRY(lowlevel_init) ldr x0, =secondary_boot_func blr x0 2: + +#ifdef CONFIG_FSL_TZPC_BP147 + /* Set Non Secure access for all devices protected via TZPC */ + ldr x1, =TZPCDECPROT_0_SET_BASE /* Decode Protection-0 Set Reg */ + orr w0, w0, #1 << 3 /* DCFG_RESET is accessible from NS world */ + str w0, [x1] + + isb + dsb sy +#endif + +#ifdef CONFIG_FSL_TZASC_400 + /* Set TZASC so that: + * a. We use only Region0 whose global secure write/read is EN + * b. We use only Region0 whose NSAID write/read is EN + * + * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just + * placeholders. + */ + ldr x1, =TZASC_GATE_KEEPER(0) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_GATE_KEEPER(1) + ldr x0, [x1] /* Filter 0 Gate Keeper Register */ + orr x0, x0, #1 << 0 /* Set open_request for Filter 0 */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(0) + ldr x0, [x1] /* Region-0 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ATTRIBUTES_0(1) + ldr x0, [x1] /* Region-1 Attributes Register */ + orr x0, x0, #1 << 31 /* Set Sec global write en, Bit[31] */ + orr x0, x0, #1 << 30 /* Set Sec global read en, Bit[30] */ + str x0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(0) + ldr w0, [x1] /* Region-0 Access Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + ldr x1, =TZASC_REGION_ID_ACCESS_0(1) + ldr w0, [x1] /* Region-1 Attributes Register */ + mov w0, #0xFFFFFFFF /* Set nsaid_wr_en and nsaid_rd_en */ + str w0, [x1] + + isb + dsb sy +#endif mov lr, x29 /* Restore LR */ ret ENDPROC(lowlevel_init) diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h index da551e88399..d4f688b3305 100644 --- a/arch/arm/include/asm/arch-fsl-lsch3/config.h +++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h @@ -35,6 +35,34 @@ #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) +/* TZ Protection Controller Definitions */ +#define TZPC_BASE 0x02200000 +#define TZPCR0SIZE_BASE (TZPC_BASE) +#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) +#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) +#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) +#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) +#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) +#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) +#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) +#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) +#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) + +/* TZ Address Space Controller Definitions */ +#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ +#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ +#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ +#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ +#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) +#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) +#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) +#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) +#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) +#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) +#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) +#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) +#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) + /* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 #define GICR_BASE 0x06100000 diff --git a/doc/README.fsl-trustzone-components b/doc/README.fsl-trustzone-components new file mode 100644 index 00000000000..a3afd1f5f45 --- /dev/null +++ b/doc/README.fsl-trustzone-components @@ -0,0 +1,25 @@ +Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like +TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone +Address Space Controller). + +While most of the configuration related programming of these peripherals +is left to a root-of-trust security software layer (running in EL3 +privilege mode), but still some configurations of these peripherals +might be required while the bootloader is executing in EL3 privilege +mode. The following sections define how to turn on these features for +LS2085A like SoCs. + +TZPC-BP147 (TrustZone Protection Controller) +============================================ +- Depends on CONFIG_FSL_TZPC_BP147 configuration flag. +- Separates Secure World and Normal World on-chip RAM (OCRAM) spaces. +- Provides a programming model to set access control policy via the TZPC + TZDECPROT Registers. + +TZASC-400 (TrustZone Address Space Controller) +============================================== +- Depends on CONFIG_FSL_TZASC_400 configuration flag. +- Separates Secure World and Normal World external memory spaces for bus masters + such as processors and DMA-equipped peripherals. +- Supports 8 fully programmable address regions, initially inactive at reset, + and one base region, always active, that covers the remaining address space. diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 6fe032c9ff6..38984432b5a 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -13,6 +13,7 @@ #define CONFIG_FSL_LSCH3 #define CONFIG_LS2085A #define CONFIG_GICV3 +#define CONFIG_FSL_TZPC_BP147 /* Link Definitions */ #define CONFIG_SYS_TEXT_BASE 0x30001000 -- cgit v1.3.1 From 03e664d8f4065010ccb6c75648192200a832fd8b Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:50 -0800 Subject: driver/ddr/fsl: Add support for multiple DDR clocks Controller number is passed for function calls to support individual DDR clock, depending on SoC implementation. It is backward compatible with exising platforms. Multiple clocks have been verifyed on LS2085A emulator. Signed-off-by: York Sun --- drivers/ddr/fsl/arm_ddr_gen3.c | 2 +- drivers/ddr/fsl/ctrl_regs.c | 208 +++++++++++++++++--------------- drivers/ddr/fsl/ddr1_dimm_params.c | 18 +-- drivers/ddr/fsl/ddr2_dimm_params.c | 12 +- drivers/ddr/fsl/ddr3_dimm_params.c | 8 +- drivers/ddr/fsl/ddr4_dimm_params.c | 8 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 2 +- drivers/ddr/fsl/lc_common_dimm_params.c | 27 +++-- drivers/ddr/fsl/main.c | 25 ++-- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 4 +- drivers/ddr/fsl/options.c | 6 +- drivers/ddr/fsl/util.c | 12 +- include/fsl_ddr.h | 15 ++- include/fsl_ddr_dimm_params.h | 2 +- 14 files changed, 190 insertions(+), 159 deletions(-) (limited to 'include') diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index c139da6da94..7160da4ec89 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -222,7 +222,7 @@ step2: bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; + (get_ddr_freq(ctrl_num) >> 20)) << 1; total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index b3477f04b71..713c3ed7619 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -17,8 +17,6 @@ #include #include -unsigned int picos_to_mclk(unsigned int picos); - /* * Determine Rtt value. * @@ -78,10 +76,11 @@ static inline int fsl_ddr_get_rtt(void) * 16 for <= 2933MT/s * 18 for higher */ -static inline unsigned int compute_cas_write_latency(void) +static inline unsigned int compute_cas_write_latency( + const unsigned int ctrl_num) { unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (mclk_ps >= 1250) cwl = 9; else if (mclk_ps >= 1070) @@ -111,10 +110,11 @@ static inline unsigned int compute_cas_write_latency(void) * 11 if 0.935ns > tCK >= 0.833ns * 12 if 0.833ns > tCK >= 0.75ns */ -static inline unsigned int compute_cas_write_latency(void) +static inline unsigned int compute_cas_write_latency( + const unsigned int ctrl_num) { unsigned int cwl; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (mclk_ps >= 2500) cwl = 5; @@ -287,7 +287,8 @@ static inline int avoid_odt_overlap(const dimm_params_t *dimm_params) * Avoid writing for DDR I. The new PQ38 DDR controller * dreams up non-zero default values to be backwards compatible. */ -static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, +static void set_timing_cfg_0(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const dimm_params_t *dimm_params) { @@ -306,7 +307,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, /* Mode register set cycle time (tMRD). */ unsigned char tmrd_mclk; #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3) - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #endif #ifdef CONFIG_SYS_FSL_DDR4 @@ -314,15 +315,15 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */ trwt_mclk = 2; twrt_mclk = 1; - act_pd_exit_mclk = picos_to_mclk(txp); + act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); pre_pd_exit_mclk = act_pd_exit_mclk; /* * MRS_CYC = max(tMRD, tMOD) * tMRD = 8nCK, tMOD = max(24nCK, 15ns) */ - tmrd_mclk = max(24U, picos_to_mclk(15000)); + tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); #elif defined(CONFIG_SYS_FSL_DDR3) - unsigned int data_rate = get_ddr_freq(0); + unsigned int data_rate = get_ddr_freq(ctrl_num); int txp; unsigned int ip_rev; int odt_overlap; @@ -344,7 +345,8 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, * tMRD = 4nCK (8nCK for RDIMM) * tMOD = max(12nCK, 15ns) */ - tmrd_mclk = max((unsigned int)12, picos_to_mclk(15000)); + tmrd_mclk = max((unsigned int)12, + picos_to_mclk(ctrl_num, 15000)); } else { /* * MRS_CYC = tMRD @@ -388,7 +390,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, taxpd_mclk = 1; } else { /* act_pd_exit_mclk = tXARD, see above */ - act_pd_exit_mclk = picos_to_mclk(txp); + act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); /* Mode register MR0[A12] is '1' - fast exit */ pre_pd_exit_mclk = act_pd_exit_mclk; taxpd_mclk = 1; @@ -424,11 +426,12 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr, #endif /* !defined(CONFIG_SYS_FSL_DDR1) */ /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */ -static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) +static void set_timing_cfg_3(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) { /* Extended precharge to activate interval (tRP) */ unsigned int ext_pretoact = 0; @@ -447,18 +450,18 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, /* Control Adjust */ unsigned int cntl_adj = 0; - ext_pretoact = picos_to_mclk(common_dimm->trp_ps) >> 4; - ext_acttopre = picos_to_mclk(common_dimm->tras_ps) >> 4; - ext_acttorw = picos_to_mclk(common_dimm->trcd_ps) >> 4; + ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; + ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; + ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; ext_caslat = (2 * cas_latency - 1) >> 4; ext_add_lat = additive_latency >> 4; #ifdef CONFIG_SYS_FSL_DDR4 - ext_refrec = (picos_to_mclk(common_dimm->trfc1_ps) - 8) >> 4; + ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; #else - ext_refrec = (picos_to_mclk(common_dimm->trfc_ps) - 8) >> 4; + ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */ #endif - ext_wrrec = (picos_to_mclk(common_dimm->twr_ps) + + ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + (popts->otf_burst_chop_en ? 2 : 0)) >> 4; ddr->timing_cfg_3 = (0 @@ -475,10 +478,11 @@ static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */ -static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency) +static void set_timing_cfg_1(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency) { /* Precharge-to-activate interval (tRP) */ unsigned char pretoact_mclk; @@ -510,9 +514,9 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0}; #endif - pretoact_mclk = picos_to_mclk(common_dimm->trp_ps); - acttopre_mclk = picos_to_mclk(common_dimm->tras_ps); - acttorw_mclk = picos_to_mclk(common_dimm->trcd_ps); + pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); + acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); + acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); /* * Translate CAS Latency to a DDR controller field value: @@ -547,19 +551,19 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, #endif #ifdef CONFIG_SYS_FSL_DDR4 - refrec_ctrl = picos_to_mclk(common_dimm->trfc1_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - acttoact_mclk = max(picos_to_mclk(common_dimm->trrds_ps), 4U); - wrtord_mclk = max(2U, picos_to_mclk(2500)); + refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; + wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); + acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); + wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); if ((wrrec_mclk < 1) || (wrrec_mclk > 24)) printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else wrrec_mclk = wrrec_table[wrrec_mclk - 1]; #else - refrec_ctrl = picos_to_mclk(common_dimm->trfc_ps) - 8; - wrrec_mclk = picos_to_mclk(common_dimm->twr_ps); - acttoact_mclk = picos_to_mclk(common_dimm->trrd_ps); - wrtord_mclk = picos_to_mclk(common_dimm->twtr_ps); + refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; + wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); + acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); + wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); if ((wrrec_mclk < 1) || (wrrec_mclk > 16)) printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk); else @@ -602,11 +606,12 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */ -static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm, - unsigned int cas_latency, - unsigned int additive_latency) +static void set_timing_cfg_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm, + unsigned int cas_latency, + unsigned int additive_latency) { /* Additive latency */ unsigned char add_lat_mclk; @@ -623,7 +628,7 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, /* Window for four activates (tFAW) */ unsigned short four_act; #ifdef CONFIG_SYS_FSL_DDR3 - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #endif /* FIXME add check that this must be less than acttorw_mclk */ @@ -641,13 +646,13 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR2) wr_lat = cas_latency - 1; #else - wr_lat = compute_cas_write_latency(); + wr_lat = compute_cas_write_latency(ctrl_num); #endif #ifdef CONFIG_SYS_FSL_DDR4 - rd_to_pre = picos_to_mclk(7500); + rd_to_pre = picos_to_mclk(ctrl_num, 7500); #else - rd_to_pre = picos_to_mclk(common_dimm->trtp_ps); + rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); #endif /* * JEDEC has some min requirements for tRTP @@ -665,19 +670,20 @@ static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr, wr_data_delay = popts->write_data_delay; #ifdef CONFIG_SYS_FSL_DDR4 cpo = 0; - cke_pls = max(3U, picos_to_mclk(5000)); + cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); #elif defined(CONFIG_SYS_FSL_DDR3) /* * cke pulse = max(3nCK, 7.5ns) for DDR3-800 * max(3nCK, 5.625ns) for DDR3-1066, 1333 * max(3nCK, 5ns) for DDR3-1600, 1866, 2133 */ - cke_pls = max(3U, picos_to_mclk(mclk_ps > 1870 ? 7500 : - (mclk_ps > 1245 ? 5625 : 5000))); + cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : + (mclk_ps > 1245 ? 5625 : 5000))); #else cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR; #endif - four_act = picos_to_mclk(popts->tfaw_window_four_activates_ps); + four_act = picos_to_mclk(ctrl_num, + popts->tfaw_window_four_activates_ps); ddr->timing_cfg_2 = (0 | ((add_lat_mclk & 0xf) << 28) @@ -818,7 +824,8 @@ static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */ -static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const unsigned int unq_mrs_en) { @@ -865,7 +872,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #endif #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7) - slow = get_ddr_freq(0) < 1249000000; + slow = get_ddr_freq(ctrl_num) < 1249000000; #endif if (popts->registered_dimm_en) { @@ -915,7 +922,8 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -926,10 +934,10 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, unsigned int wr_crc = 0; /* Disable */ unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ - unsigned int cwl = compute_cas_write_latency() - 9; + unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; unsigned int mpr = 0; /* serial */ unsigned int wc_lat; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); if (popts->rtt_override) rtt_wr = popts->rtt_wr_override_value; @@ -1002,7 +1010,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, } #elif defined(CONFIG_SYS_FSL_DDR3) /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1013,7 +1022,7 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ - unsigned int cwl = compute_cas_write_latency() - 5; + unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; unsigned int pasr = 0; /* partial array self refresh disable */ if (popts->rtt_override) @@ -1077,7 +1086,8 @@ static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, #else /* for DDR2 and DDR1 */ /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1144,7 +1154,8 @@ static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */ -static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, const unsigned int unq_mrs_en) @@ -1152,7 +1163,7 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, int i; unsigned short esdmode6 = 0; /* Extended SDRAM mode 6 */ unsigned short esdmode7 = 0; /* Extended SDRAM mode 7 */ - unsigned int tccdl_min = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); esdmode6 = ((tccdl_min - 4) & 0x7) << 10; @@ -1196,14 +1207,15 @@ static void set_ddr_sdram_mode_10(fsl_ddr_cfg_regs_t *ddr, #endif /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */ -static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, - const memctl_options_t *popts, - const common_timing_params_t *common_dimm) +static void set_ddr_sdram_interval(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts, + const common_timing_params_t *common_dimm) { unsigned int refint; /* Refresh interval */ unsigned int bstopre; /* Precharge interval */ - refint = picos_to_mclk(common_dimm->refresh_rate_ps); + refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); bstopre = popts->bstopre; @@ -1217,7 +1229,8 @@ static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr, #ifdef CONFIG_SYS_FSL_DDR4 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1292,7 +1305,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, * 1=fast exit DLL on (tXP) */ - wr_mclk = picos_to_mclk(common_dimm->twr_ps); + wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); if (wr_mclk <= 24) { wr = wr_table[wr_mclk - 10]; } else { @@ -1387,7 +1400,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #elif defined(CONFIG_SYS_FSL_DDR3) /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1466,7 +1480,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, */ dll_on = 1; - wr_mclk = picos_to_mclk(common_dimm->twr_ps); + wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); if (wr_mclk <= 16) { wr = wr_table[wr_mclk - 5]; } else { @@ -1582,7 +1596,8 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #else /* !CONFIG_SYS_FSL_DDR3 */ /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */ -static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, +static void set_ddr_sdram_mode(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency, @@ -1654,7 +1669,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr, #if defined(CONFIG_SYS_FSL_DDR1) wr = 0; /* Historical */ #elif defined(CONFIG_SYS_FSL_DDR2) - wr = picos_to_mclk(common_dimm->twr_ps); + wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); #endif dll_res = 0; mode = 0; @@ -1842,15 +1857,16 @@ static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr) debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6); } -static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, - const common_timing_params_t *common_dimm) +static void set_timing_cfg_7(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, + const common_timing_params_t *common_dimm) { unsigned int txpr, tcksre, tcksrx; unsigned int cke_rst, cksre, cksrx, par_lat, cs_to_cmd; - txpr = max(5U, picos_to_mclk(common_dimm->trfc1_ps + 10000)); - tcksre = max(5U, picos_to_mclk(10000)); - tcksrx = max(5U, picos_to_mclk(10000)); + txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); + tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); + tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); par_lat = 0; cs_to_cmd = 0; @@ -1883,14 +1899,15 @@ static void set_timing_cfg_7(fsl_ddr_cfg_regs_t *ddr, debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); } -static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, +static void set_timing_cfg_8(const unsigned int ctrl_num, + fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts, const common_timing_params_t *common_dimm, unsigned int cas_latency) { unsigned int rwt_bg, wrt_bg, rrt_bg, wwt_bg; unsigned int acttoact_bg, wrtord_bg, pre_all_rec; - unsigned int tccdl = picos_to_mclk(common_dimm->tccdl_ps); + unsigned int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) + ((ddr->timing_cfg_2 & 0x00040000) >> 14); @@ -1914,8 +1931,8 @@ static void set_timing_cfg_8(fsl_ddr_cfg_regs_t *ddr, wwt_bg = tccdl - 4; } - acttoact_bg = picos_to_mclk(common_dimm->trrdl_ps); - wrtord_bg = max(4U, picos_to_mclk(7500)); + acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); + wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); if (popts->otf_burst_chop_en) wrtord_bg += 2; @@ -2147,7 +2164,8 @@ check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr) } unsigned int -compute_fsl_memctl_config_regs(const memctl_options_t *popts, +compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_params, @@ -2319,14 +2337,14 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_eor(ddr, popts); #if !defined(CONFIG_SYS_FSL_DDR1) - set_timing_cfg_0(ddr, popts, dimm_params); + set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); #endif - set_timing_cfg_3(ddr, popts, common_dimm, cas_latency, + set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, additive_latency); - set_timing_cfg_1(ddr, popts, common_dimm, cas_latency); - set_timing_cfg_2(ddr, popts, common_dimm, - cas_latency, additive_latency); + set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); + set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, + cas_latency, additive_latency); set_ddr_cdr1(ddr, popts); set_ddr_cdr2(ddr, popts); @@ -2338,15 +2356,15 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, if ((ip_rev > 0x40700) && (popts->cswl_override != 0)) ddr->debug[18] = popts->cswl_override; - set_ddr_sdram_cfg_2(ddr, popts, unq_mrs_en); - set_ddr_sdram_mode(ddr, popts, common_dimm, - cas_latency, additive_latency, unq_mrs_en); - set_ddr_sdram_mode_2(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); + set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, + cas_latency, additive_latency, unq_mrs_en); + set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); #ifdef CONFIG_SYS_FSL_DDR4 set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en); - set_ddr_sdram_mode_10(ddr, popts, common_dimm, unq_mrs_en); + set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); #endif - set_ddr_sdram_interval(ddr, popts, common_dimm); + set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); set_ddr_init_addr(ddr); @@ -2356,8 +2374,8 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, #ifdef CONFIG_SYS_FSL_DDR4 set_ddr_sdram_cfg_3(ddr, popts); set_timing_cfg_6(ddr); - set_timing_cfg_7(ddr, common_dimm); - set_timing_cfg_8(ddr, popts, common_dimm, cas_latency); + set_timing_cfg_7(ctrl_num, ddr, common_dimm); + set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); set_timing_cfg_9(ddr); set_ddr_dq_mapping(ddr, dimm_params); #endif diff --git a/drivers/ddr/fsl/ddr1_dimm_params.c b/drivers/ddr/fsl/ddr1_dimm_params.c index 7df27b90b76..7f1c3afcc47 100644 --- a/drivers/ddr/fsl/ddr1_dimm_params.c +++ b/drivers/ddr/fsl/ddr1_dimm_params.c @@ -228,10 +228,10 @@ compute_derated_DDR1_CAS_latency(unsigned int mclk_ps) * * FIXME: use #define for the retvals */ -unsigned int -ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr1_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; @@ -311,16 +311,16 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR1_CAS_latency(get_memory_clk_period_ps()); + pdimm->caslat_lowest_derated = compute_derated_DDR1_CAS_latency( + get_memory_clk_period_ps(ctrl_num)); /* Compute timing parameters */ pdimm->trcd_ps = spd->trcd * 250; pdimm->trp_ps = spd->trp * 250; pdimm->tras_ps = spd->tras * 1000; - pdimm->twr_ps = mclk_to_picos(3); - pdimm->twtr_ps = mclk_to_picos(1); + pdimm->twr_ps = mclk_to_picos(ctrl_num, 3); + pdimm->twtr_ps = mclk_to_picos(ctrl_num, 1); pdimm->trfc_ps = compute_trfc_ps_from_spd(0, spd->trfc); pdimm->trrd_ps = spd->trrd * 250; @@ -335,7 +335,7 @@ ddr_compute_dimm_parameters(const ddr1_spd_eeprom_t *spd, pdimm->tdh_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold); - pdimm->trtp_ps = mclk_to_picos(2); /* By the book. */ + pdimm->trtp_ps = mclk_to_picos(ctrl_num, 2); /* By the book. */ pdimm->tdqsq_max_ps = spd->tdqsq * 10; pdimm->tqhs_ps = spd->tqhs * 10; diff --git a/drivers/ddr/fsl/ddr2_dimm_params.c b/drivers/ddr/fsl/ddr2_dimm_params.c index d865df78a8d..49cc1a07ffd 100644 --- a/drivers/ddr/fsl/ddr2_dimm_params.c +++ b/drivers/ddr/fsl/ddr2_dimm_params.c @@ -211,10 +211,10 @@ compute_derated_DDR2_CAS_latency(unsigned int mclk_ps) * * FIXME: use #define for the retvals */ -unsigned int -ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr2_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; @@ -310,8 +310,8 @@ ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd, & ~(1 << pdimm->caslat_x_minus_1)); /* Compute CAS latencies below that defined by SPD */ - pdimm->caslat_lowest_derated - = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps()); + pdimm->caslat_lowest_derated = compute_derated_DDR2_CAS_latency( + get_memory_clk_period_ps(ctrl_num)); /* Compute timing parameters */ pdimm->trcd_ps = spd->trcd * 250; diff --git a/drivers/ddr/fsl/ddr3_dimm_params.c b/drivers/ddr/fsl/ddr3_dimm_params.c index a4b8c101f53..69177150ec5 100644 --- a/drivers/ddr/fsl/ddr3_dimm_params.c +++ b/drivers/ddr/fsl/ddr3_dimm_params.c @@ -83,10 +83,10 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd) * Writes the results to the dimm_params_t structure pointed by pdimm. * */ -unsigned int -ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const ddr3_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; unsigned int mtb_ps; diff --git a/drivers/ddr/fsl/ddr4_dimm_params.c b/drivers/ddr/fsl/ddr4_dimm_params.c index aaddc8fa087..bbfb4ee4179 100644 --- a/drivers/ddr/fsl/ddr4_dimm_params.c +++ b/drivers/ddr/fsl/ddr4_dimm_params.c @@ -119,10 +119,10 @@ compute_ranksize(const struct ddr4_spd_eeprom_s *spd) * Writes the results to the dimm_params_t structure pointed by pdimm. * */ -unsigned int -ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd, - dimm_params_t *pdimm, - unsigned int dimm_number) +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, + dimm_params_t *pdimm, + unsigned int dimm_number) { unsigned int retval; int i; diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 9cca4a06dd5..d9fce7d2f34 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -287,7 +287,7 @@ step2: bus_width = 3 - ((ddr_in32(&ddr->sdram_cfg) & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 2; + (get_ddr_freq(ctrl_num) >> 20)) << 2; total_gb_size_per_controller >>= 4; /* shift down to gb size */ debug("total %d GB\n", total_gb_size_per_controller); debug("Need to wait up to %d * 10ms\n", timeout); diff --git a/drivers/ddr/fsl/lc_common_dimm_params.c b/drivers/ddr/fsl/lc_common_dimm_params.c index 73db4446153..b295344c4de 100644 --- a/drivers/ddr/fsl/lc_common_dimm_params.c +++ b/drivers/ddr/fsl/lc_common_dimm_params.c @@ -13,7 +13,8 @@ #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4) static unsigned int -compute_cas_latency(const dimm_params_t *dimm_params, +compute_cas_latency(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) { @@ -22,7 +23,7 @@ compute_cas_latency(const dimm_params_t *dimm_params, unsigned int caslat_actual; unsigned int retry = 16; unsigned int tmp; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); #ifdef CONFIG_SYS_FSL_DDR3 const unsigned int taamax = 20000; #else @@ -72,12 +73,13 @@ compute_cas_latency(const dimm_params_t *dimm_params, } #else /* for DDR1 and DDR2 */ static unsigned int -compute_cas_latency(const dimm_params_t *dimm_params, +compute_cas_latency(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms) { int i; - const unsigned int mclk_ps = get_memory_clk_period_ps(); + const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); unsigned int lowest_good_caslat; unsigned int not_ok; unsigned int temp1, temp2; @@ -212,7 +214,8 @@ compute_cas_latency(const dimm_params_t *dimm_params, * by dimm_params. */ unsigned int -compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, +compute_lowest_common_dimm_parameters(const unsigned int ctrl_num, + const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, const unsigned int number_of_dimms) { @@ -442,7 +445,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, printf("ERROR: Mix different RDIMM detected!\n"); /* calculate cas latency for all DDR types */ - if (compute_cas_latency(dimm_params, outpdimm, number_of_dimms)) + if (compute_cas_latency(ctrl_num, dimm_params, + outpdimm, number_of_dimms)) return 1; /* Determine if all DIMMs ECC capable. */ @@ -518,11 +522,12 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, #if defined(CONFIG_SYS_FSL_DDR2) if ((outpdimm->lowest_common_spd_caslat < 4) && - (picos_to_mclk(trcd_ps) > outpdimm->lowest_common_spd_caslat)) { - additive_latency = picos_to_mclk(trcd_ps) - + (picos_to_mclk(ctrl_num, trcd_ps) > + outpdimm->lowest_common_spd_caslat)) { + additive_latency = picos_to_mclk(ctrl_num, trcd_ps) - outpdimm->lowest_common_spd_caslat; - if (mclk_to_picos(additive_latency) > trcd_ps) { - additive_latency = picos_to_mclk(trcd_ps); + if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { + additive_latency = picos_to_mclk(ctrl_num, trcd_ps); debug("setting additive_latency to %u because it was " " greater than tRCD_ps\n", additive_latency); } @@ -534,7 +539,7 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params, * * AL <= tRCD(min) */ - if (mclk_to_picos(additive_latency) > trcd_ps) { + if (mclk_to_picos(ctrl_num, additive_latency) > trcd_ps) { printf("Error: invalid additive latency exceeds tRCD(min).\n"); return 1; } diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index 6f291ebc032..f49939b1359 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -450,7 +450,8 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, &(pinfo->spd_installed_dimms[i][j]); dimm_params_t *pdimm = &(pinfo->dimm_params[i][j]); - retval = compute_dimm_parameters(spd, pdimm, i); + retval = compute_dimm_parameters( + i, spd, pdimm, j); #ifdef CONFIG_SYS_DDR_RAW_TIMING if (!i && !j && retval) { printf("SPD error on controller %d! " @@ -507,10 +508,11 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, for (i = first_ctrl; i <= last_ctrl; i++) { debug("Computing lowest common DIMM" " parameters for memctl=%u\n", i); - compute_lowest_common_dimm_parameters( - pinfo->dimm_params[i], - &timing_params[i], - CONFIG_DIMM_SLOTS_PER_CTLR); + compute_lowest_common_dimm_parameters + (i, + pinfo->dimm_params[i], + &timing_params[i], + CONFIG_DIMM_SLOTS_PER_CTLR); } case STEP_GATHER_OPTS: @@ -562,12 +564,13 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, continue; } - compute_fsl_memctl_config_regs( - &pinfo->memctl_opts[i], - &ddr_reg[i], &timing_params[i], - pinfo->dimm_params[i], - dbw_capacity_adjust[i], - size_only); + compute_fsl_memctl_config_regs + (i, + &pinfo->memctl_opts[i], + &ddr_reg[i], &timing_params[i], + pinfo->dimm_params[i], + dbw_capacity_adjust[i], + size_only); } default: diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 8f4d01ad856..6752d4d29e0 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -426,7 +426,7 @@ step2: bus_width = 3 - ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) >> SDRAM_CFG_DBW_SHIFT); timeout = ((total_gb_size_per_controller << (6 - bus_width)) * 100 / - (get_ddr_freq(0) >> 20)) << 1; + (get_ddr_freq(ctrl_num) >> 20)) << 1; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 timeout_save = timeout; #endif @@ -538,12 +538,14 @@ step2: case 1: out_be32(&ddr->cs1_bnds, regs->cs[csn].bnds); break; +#if CONFIG_CHIP_SELECTS_PER_CTRL > 2 case 2: out_be32(&ddr->cs2_bnds, regs->cs[csn].bnds); break; case 3: out_be32(&ddr->cs3_bnds, regs->cs[csn].bnds); break; +#endif } clrbits_be32(&ddr->sdram_cfg, 0x2); } diff --git a/drivers/ddr/fsl/options.c b/drivers/ddr/fsl/options.c index 6d098d1fa2f..5beb11b02b4 100644 --- a/drivers/ddr/fsl/options.c +++ b/drivers/ddr/fsl/options.c @@ -732,7 +732,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, #endif /* Global Timing Parameters. */ - debug("mclk_ps = %u ps\n", get_memory_clk_period_ps()); + debug("mclk_ps = %u ps\n", get_memory_clk_period_ps(ctrl_num)); /* Pick a caslat override. */ popts->cas_latency_override = 0; @@ -785,7 +785,7 @@ unsigned int populate_memctl_options(int all_dimms_registered, * FIXME: width, was considering looking at pdimm->primary_sdram_width */ #if defined(CONFIG_SYS_FSL_DDR1) - popts->tfaw_window_four_activates_ps = mclk_to_picos(1); + popts->tfaw_window_four_activates_ps = mclk_to_picos(ctrl_num, 1); #elif defined(CONFIG_SYS_FSL_DDR2) /* @@ -1036,7 +1036,7 @@ done: if (pdimm[0].n_ranks == 4) popts->quad_rank_present = 1; - ddr_freq = get_ddr_freq(0) / 1000000; + ddr_freq = get_ddr_freq(ctrl_num) / 1000000; if (popts->registered_dimm_en) { popts->rcw_override = 1; popts->rcw_1 = 0x000a5a00; diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 58b519b4036..ad569de27a4 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -43,9 +43,9 @@ u32 fsl_ddr_get_version(void) * propagation, compute a suitably rounded mclk_ps to compute * a working memory controller configuration. */ -unsigned int get_memory_clk_period_ps(void) +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num) { - unsigned int data_rate = get_ddr_freq(0); + unsigned int data_rate = get_ddr_freq(ctrl_num); unsigned int result; /* Round to nearest 10ps, being careful about 64-bit multiply/divide */ @@ -59,10 +59,10 @@ unsigned int get_memory_clk_period_ps(void) } /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */ -unsigned int picos_to_mclk(unsigned int picos) +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos) { unsigned long long clks, clks_rem; - unsigned long data_rate = get_ddr_freq(0); + unsigned long data_rate = get_ddr_freq(ctrl_num); /* Short circuit for zero picos */ if (!picos) @@ -88,9 +88,9 @@ unsigned int picos_to_mclk(unsigned int picos) return (unsigned int) clks; } -unsigned int mclk_to_picos(unsigned int mclk) +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk) { - return get_memory_clk_period_ps() * mclk; + return get_memory_clk_period_ps(ctrl_num) * mclk; } #ifdef CONFIG_PPC diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 3286c95907c..96fde91687d 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -44,11 +44,12 @@ u32 fsl_ddr_get_version(void); * to this specific DDR technology. */ static __inline__ int -compute_dimm_parameters(const generic_spd_eeprom_t *spd, +compute_dimm_parameters(const unsigned int ctrl_num, + const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number) { - return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); + return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number); } #endif @@ -92,13 +93,15 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); const char *step_to_string(unsigned int step); -unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, +unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num, + const memctl_options_t *popts, fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, unsigned int dbw_capacity_adjust, unsigned int size_only); unsigned int compute_lowest_common_dimm_parameters( + const unsigned int ctrl_num, const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); @@ -108,9 +111,9 @@ unsigned int populate_memctl_options(int all_dimms_registered, unsigned int ctrl_num); void check_interleaving_options(fsl_ddr_info_t *pinfo); -unsigned int mclk_to_picos(unsigned int mclk); -unsigned int get_memory_clk_period_ps(void); -unsigned int picos_to_mclk(unsigned int picos); +unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk); +unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num); +unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos); void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, diff --git a/include/fsl_ddr_dimm_params.h b/include/fsl_ddr_dimm_params.h index 09a67a68029..751e9351174 100644 --- a/include/fsl_ddr_dimm_params.h +++ b/include/fsl_ddr_dimm_params.h @@ -112,7 +112,7 @@ typedef struct dimm_params_s { #endif } dimm_params_t; -extern unsigned int ddr_compute_dimm_parameters( +unsigned int ddr_compute_dimm_parameters(const unsigned int ctrl_num, const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number); -- cgit v1.3.1 From 27f277fe33eb824308a4547d2e96bf511fb91d6b Mon Sep 17 00:00:00 2001 From: Kuldip Giroh Date: Tue, 6 Jan 2015 13:18:53 -0800 Subject: ARMv8/LS2085A: HugeTLB support is required by default in LS NADK LS NADK memory manager by default works on HugeTLB. Hence bootargs must include parameters default_hugepagesz (default hugepagesize, hugepagesz (hugepage size) and hugepages (number of hugepages to be reserved in kernel for the given size). Signed-off-by: Kuldip Giroh Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 38984432b5a..55e7307cbc2 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -274,7 +274,9 @@ "console=ttyAMA0,38400n8\0" #define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlyprintk=uart8250-8bit,0x21c0600" + "earlyprintk=uart8250-8bit,0x21c0600 " \ + "default_hugepagesz=2m hugepagesz=2m " \ + "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 1 -- cgit v1.3.1 From 064d031ca6490d9641bbe308690b1f15b1f56077 Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:54 -0800 Subject: ARMv8/LS2085A: Adjust system clock and DDR clock Set system clock to 100MHz and DDR clock to 133MHz. Signed-off-by: York Sun --- include/configs/ls2085a_common.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 55e7307cbc2..387f9047058 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -249,7 +249,8 @@ /* Physical Memory Map */ /* fixme: these need to be checked against the board */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_SYS_CLK_FREQ 133333333 +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 133333333 #define CONFIG_NR_DRAM_BANKS 3 -- cgit v1.3.1 From e32d59a2fa6446b64167bba31c0dd40eb023e8bb Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:18:55 -0800 Subject: driver/ddr/fsl: Add sync of refresh Add sync of refresh for multiple DDR controllers. DDRC initialization needs to complete first. Code is re-ordered to keep refresh close. Signed-off-by: York Sun --- README | 3 +++ drivers/ddr/fsl/main.c | 4 ++++ drivers/ddr/fsl/util.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++ include/fsl_ddr.h | 2 ++ 4 files changed, 64 insertions(+) (limited to 'include') diff --git a/README b/README index ba57dc5617a..6800b959ca5 100644 --- a/README +++ b/README @@ -4916,6 +4916,9 @@ Low Level (hardware related) configuration options: - CONFIG_FSL_DDR_INTERACTIVE Enable interactive DDR debugging. See doc/README.fsl-ddr. +- CONFIG_FSL_DDR_SYNC_REFRESH + Enable sync of refresh for multiple controllers. + - CONFIG_SYS_83XX_DDR_USES_CS0 Only for 83xx systems. If specified, then DDR should be configured using CS0 and CS1 instead of CS2 and CS3. diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index f49939b1359..b72b24290ec 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -692,6 +692,10 @@ phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo) } } +#ifdef CONFIG_FSL_DDR_SYNC_REFRESH + fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl); +#endif + #ifdef CONFIG_PPC /* program LAWs */ for (i = first_ctrl; i <= last_ctrl; i++) { diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index ad569de27a4..664081b1b83 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -308,3 +308,58 @@ void board_add_ram_info(int use_default) { detail_board_ddr_info(); } + +#ifdef CONFIG_FSL_DDR_SYNC_REFRESH +#define DDRC_DEBUG20_INIT_DONE 0x80000000 +#define DDRC_DEBUG2_RF 0x00000040 +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl) +{ + unsigned int i; + u32 ddrc_debug20; + u32 ddrc_debug2[CONFIG_NUM_DDR_CONTROLLERS] = {}; + u32 *ddrc_debug2_p[CONFIG_NUM_DDR_CONTROLLERS] = {}; + struct ccsr_ddr __iomem *ddr; + + for (i = first_ctrl; i <= last_ctrl; i++) { + switch (i) { + case 0: + ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + break; +#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1) + case 1: + ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2) + case 2: + ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + break; +#endif +#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3) + case 3: + ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; + break; +#endif + default: + printf("%s unexpected ctrl = %u\n", __func__, i); + return; + } + ddrc_debug20 = ddr_in32(&ddr->debug[19]); + ddrc_debug2_p[i] = &ddr->debug[1]; + while (!(ddrc_debug20 & DDRC_DEBUG20_INIT_DONE)) { + /* keep polling until DDRC init is done */ + udelay(100); + ddrc_debug20 = ddr_in32(&ddr->debug[19]); + } + ddrc_debug2[i] = ddr_in32(&ddr->debug[1]) | DDRC_DEBUG2_RF; + } + /* + * Sync refresh + * This is put together to make sure the refresh reqeusts are sent + * closely to each other. + */ + for (i = first_ctrl; i <= last_ctrl; i++) + ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]); +} +#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */ diff --git a/include/fsl_ddr.h b/include/fsl_ddr.h index 96fde91687d..feccef9c9cd 100644 --- a/include/fsl_ddr.h +++ b/include/fsl_ddr.h @@ -118,6 +118,8 @@ void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); +void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, + unsigned int last_ctrl); int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); -- cgit v1.3.1 From 40e61f8e54f8262a6e85c127c5d9dc240253382a Mon Sep 17 00:00:00 2001 From: Arnab Basu Date: Tue, 6 Jan 2015 13:18:56 -0800 Subject: ARMv8/ls2085a: Switch to passing earlycon to kernel Since Linux v3.16-rc1 earlyprintk has been removed for arm64. Switch to using earlycon. Signed-off-by: Arnab Basu Signed-off-by: York Sun --- include/configs/ls2085a_common.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 387f9047058..7e8d944dff7 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -274,10 +274,10 @@ "kernel_size=0x1000000\0" \ "console=ttyAMA0,38400n8\0" -#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ - "earlyprintk=uart8250-8bit,0x21c0600 " \ - "default_hugepagesz=2m hugepagesz=2m " \ - "hugepages=16" +#define CONFIG_BOOTARGS "console=ttyS1,115200 root=/dev/ram0 " \ + "earlycon=uart8250,mmio,0x21c0600,115200 " \ + "default_hugepagesz=2m hugepagesz=2m " \ + "hugepages=16" #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ "$kernel_size && bootm $kernel_load" #define CONFIG_BOOTDELAY 1 -- cgit v1.3.1 From 052ddd5c812ad9f30e7cf9023e50fde882bd65da Mon Sep 17 00:00:00 2001 From: Stuart Yoder Date: Tue, 6 Jan 2015 13:18:57 -0800 Subject: ARMv8/ls2085a: Move kernel image load address Move the load address of the kernel image to get it away from the region of the uncompressed kernel. Signed-off-by: Stuart Yoder Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 7e8d944dff7..befd4c72577 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -270,7 +270,7 @@ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ "kernel_start=0x581200000\0" \ - "kernel_load=0x806f0000\0" \ + "kernel_load=0xa0000000\0" \ "kernel_size=0x1000000\0" \ "console=ttyAMA0,38400n8\0" -- cgit v1.3.1 From bbeeb8bec084d9fff2cd16d2577ca285f8e66b72 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Tue, 6 Jan 2015 13:18:58 -0800 Subject: ls2085/configs: Ensure right banners are printed for EMU and SIMU This patch enusres that right banners are printed for LS2085A emulator and simulator platforms. Signed-off-by: Bhupesh Sharma Reviewed-by: York Sun --- include/configs/ls2085a_common.h | 3 --- include/configs/ls2085a_emu.h | 3 +++ include/configs/ls2085a_simu.h | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index befd4c72577..55f4c963608 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -27,9 +27,6 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F 1 -#define CONFIG_IDENT_STRING " LS2085A-EMU" -#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" - /* Flat Device Tree Definitions */ #define CONFIG_OF_LIBFDT #define CONFIG_OF_BOARD_SETUP diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 487cd99c5dc..2d2e1ea0bdc 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-EMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-EMU" + #define CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ #define SPD_EEPROM_ADDRESS1 0x51 diff --git a/include/configs/ls2085a_simu.h b/include/configs/ls2085a_simu.h index 0f40b787b47..af34f3f95d6 100644 --- a/include/configs/ls2085a_simu.h +++ b/include/configs/ls2085a_simu.h @@ -9,6 +9,9 @@ #include "ls2085a_common.h" +#define CONFIG_IDENT_STRING " LS2085A-SIMU" +#define CONFIG_BOOTP_VCI_STRING "U-boot.LS2085A-SIMU" + /* SMSC 91C111 ethernet configuration */ #define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x2210000) -- cgit v1.3.1 From 4f2532c4a4a34f0241ef9bc921044772f19f928d Mon Sep 17 00:00:00 2001 From: York Sun Date: Tue, 6 Jan 2015 13:19:01 -0800 Subject: armv8/ls2085a_emu: Enable sync of refresh Enable sync of DDR refresh for LS2085a platform. GPP DDR controllers stay in sync. DP-DDR has only one controller so it does no harm. Signed-off-by: York Sun --- include/configs/ls2085a_emu.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/ls2085a_emu.h b/include/configs/ls2085a_emu.h index 2d2e1ea0bdc..a02d69450b7 100644 --- a/include/configs/ls2085a_emu.h +++ b/include/configs/ls2085a_emu.h @@ -20,4 +20,5 @@ #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ +#define CONFIG_FSL_DDR_SYNC_REFRESH #endif /* __LS2_EMU_H */ -- cgit v1.3.1 From 7b3bd9a7988a8b4c8ba22a52b4927e8e59819b12 Mon Sep 17 00:00:00 2001 From: "J. German Rivera" Date: Tue, 6 Jan 2015 13:19:02 -0800 Subject: drivers/mc: Migrated MC Flibs to 0.5.2 Upgrade Manage Complex (MC) flib API to 0.5.2. Rename directory fsl_mc to fsl-mc. Change the fsl-mc node in Linux device tree from "fsl,dprcr" to "fsl-mc". Print MC version info when appropriate. Signed-off-by: J. German Rivera Signed-off-by: Lijun Pan Reviewed-by: York Sun --- arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 2 +- board/freescale/ls2085a/ls2085a.c | 18 ++- drivers/net/Makefile | 2 +- drivers/net/fsl-mc/Makefile | 10 ++ drivers/net/fsl-mc/dpmng.c | 91 +++++++++++ drivers/net/fsl-mc/fsl_dpmng_cmd.h | 49 ++++++ drivers/net/fsl-mc/mc.c | 310 +++++++++++++++++++++++++++++++++++++ drivers/net/fsl-mc/mc_sys.c | 63 ++++++++ drivers/net/fsl_mc/Makefile | 8 - drivers/net/fsl_mc/mc.c | 266 ------------------------------- include/configs/ls2085a_common.h | 4 +- include/fsl-mc/fsl_dpmng.h | 121 +++++++++++++++ include/fsl-mc/fsl_mc.h | 59 +++++++ include/fsl-mc/fsl_mc_cmd.h | 132 ++++++++++++++++ include/fsl-mc/fsl_mc_sys.h | 26 ++++ include/fsl_mc.h | 59 ------- 16 files changed, 880 insertions(+), 340 deletions(-) create mode 100644 drivers/net/fsl-mc/Makefile create mode 100644 drivers/net/fsl-mc/dpmng.c create mode 100644 drivers/net/fsl-mc/fsl_dpmng_cmd.h create mode 100644 drivers/net/fsl-mc/mc.c create mode 100644 drivers/net/fsl-mc/mc_sys.c delete mode 100644 drivers/net/fsl_mc/Makefile delete mode 100644 drivers/net/fsl_mc/mc.c create mode 100644 include/fsl-mc/fsl_dpmng.h create mode 100644 include/fsl-mc/fsl_mc.h create mode 100644 include/fsl-mc/fsl_mc_cmd.h create mode 100644 include/fsl-mc/fsl_mc_sys.h delete mode 100644 include/fsl_mc.h (limited to 'include') diff --git a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c index 42cee655462..49974878b9c 100644 --- a/arch/arm/cpu/armv8/fsl-lsch3/cpu.c +++ b/arch/arm/cpu/armv8/fsl-lsch3/cpu.c @@ -10,10 +10,10 @@ #include #include #include +#include #include "cpu.h" #include "mp.h" #include "speed.h" -#include DECLARE_GLOBAL_DATA_PTR; diff --git a/board/freescale/ls2085a/ls2085a.c b/board/freescale/ls2085a/ls2085a.c index ee75d1b7eda..519d61cb1e8 100644 --- a/board/freescale/ls2085a/ls2085a.c +++ b/board/freescale/ls2085a/ls2085a.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -98,7 +98,21 @@ void fdt_fixup_board_enet(void *fdt) { int offset; - offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + offset = fdt_path_offset(fdt, "/fsl-mc"); + + /* + * TODO: Remove this when backward compatibility + * with old DT node (fsl,dprc@0) is no longer needed. + */ + if (offset < 0) + offset = fdt_path_offset(fdt, "/fsl,dprc@0"); + + if (offset < 0) { + printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n", + __func__, offset); + return; + } + if (get_mc_boot_status() == 0) fdt_status_okay(fdt, offset); else diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 46c4ac697d6..6e1ccdbb3d2 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -65,5 +65,5 @@ obj-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o obj-$(CONFIG_XILINX_LL_TEMAC) += xilinx_ll_temac.o xilinx_ll_temac_mdio.o \ xilinx_ll_temac_fifo.o xilinx_ll_temac_sdma.o obj-$(CONFIG_ZYNQ_GEM) += zynq_gem.o -obj-$(CONFIG_FSL_MC_ENET) += fsl_mc/ +obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/ obj-$(CONFIG_VSC9953) += vsc9953.o diff --git a/drivers/net/fsl-mc/Makefile b/drivers/net/fsl-mc/Makefile new file mode 100644 index 00000000000..206ac6be07a --- /dev/null +++ b/drivers/net/fsl-mc/Makefile @@ -0,0 +1,10 @@ +# +# Copyright 2014 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +# Layerscape MC driver +obj-y += mc.o \ + mc_sys.o \ + dpmng.o diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c new file mode 100644 index 00000000000..cc14c7b7559 --- /dev/null +++ b/drivers/net/fsl-mc/dpmng.c @@ -0,0 +1,91 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include +#include +#include "fsl_dpmng_cmd.h" + +int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info) +{ + struct mc_command cmd = { 0 }; + int err; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_GET_VERSION, + MC_CMD_PRI_LOW, 0); + + /* send command to mc*/ + err = mc_send_command(mc_io, &cmd); + if (err) + return err; + + /* retrieve response parameters */ + DPMNG_RSP_GET_VERSION(cmd, mc_ver_info); + + return 0; +} + +int dpmng_reset_aiop(struct fsl_mc_io *mc_io, int container_id, + int aiop_tile_id) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_AIOP, + MC_CMD_PRI_LOW, 0); + DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_load_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + uint64_t img_iova, + uint32_t img_size) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_LOAD_AIOP, + MC_CMD_PRI_LOW, + 0); + DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, + img_iova); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_run_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + const struct dpmng_aiop_run_cfg *cfg) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RUN_AIOP, + MC_CMD_PRI_LOW, + 0); + DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} + +int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io) +{ + struct mc_command cmd = { 0 }; + + /* prepare command */ + cmd.header = mc_encode_cmd_header(DPMNG_CMDID_RESET_MC_PORTAL, + MC_CMD_PRI_LOW, + 0); + + /* send command to mc*/ + return mc_send_command(mc_io, &cmd); +} diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h new file mode 100644 index 00000000000..c9fe021f455 --- /dev/null +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -0,0 +1,49 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_DPMNG_CMD_H +#define __FSL_DPMNG_CMD_H + +/* Command IDs */ +#define DPMNG_CMDID_GET_VERSION 0x831 +#define DPMNG_CMDID_RESET_AIOP 0x832 +#define DPMNG_CMDID_LOAD_AIOP 0x833 +#define DPMNG_CMDID_RUN_AIOP 0x834 +#define DPMNG_CMDID_RESET_MC_PORTAL 0x835 + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \ +do { \ + MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \ + MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \ + MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_RESET_AIOP(cmd, container_id, aiop_tile_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_LOAD_AIOP(cmd, container_id, aiop_tile_id, img_size, \ + img_iova) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, img_size); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, img_iova); \ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPMNG_CMD_RUN_AIOP(cmd, container_id, aiop_tile_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, aiop_tile_id); \ + MC_CMD_OP(cmd, 0, 32, 32, int, container_id); \ + MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->cores_mask); \ + MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options); \ +} while (0) + +#endif /* __FSL_DPMNG_CMD_H */ diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c new file mode 100644 index 00000000000..74b0085301c --- /dev/null +++ b/drivers/net/fsl-mc/mc.c @@ -0,0 +1,310 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; +static int mc_boot_status; + +/** + * Copying MC firmware or DPL image to DDR + */ +static int mc_copy_image(const char *title, + u64 image_addr, u32 image_size, u64 mc_ram_addr) +{ + debug("%s copied to address %p\n", title, (void *)mc_ram_addr); + memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); + return 0; +} + +/** + * MC firmware FIT image parser checks if the image is in FIT + * format, verifies integrity of the image and calculates + * raw image address and size values. + * Returns 0 on success and a negative errno on error. + * task fail. + **/ +int parse_mc_firmware_fit_image(const void **raw_image_addr, + size_t *raw_image_size) +{ + int format; + void *fit_hdr; + int node_offset; + const void *data; + size_t size; + const char *uname = "firmware"; + + /* Check if the image is in NOR flash */ +#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR + fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" +#endif + + /* Check if Image is in FIT format */ + format = genimg_get_format(fit_hdr); + + if (format != IMAGE_FORMAT_FIT) { + printf("fsl-mc: ERROR: Bad firmware image (not a FIT image)\n"); + return -EINVAL; + } + + if (!fit_check_format(fit_hdr)) { + printf("fsl-mc: ERROR: Bad firmware image (bad FIT header)\n"); + return -EINVAL; + } + + node_offset = fit_image_get_node(fit_hdr, uname); + + if (node_offset < 0) { + printf("fsl-mc: ERROR: Bad firmware image (missing subimage)\n"); + return -ENOENT; + } + + /* Verify MC firmware image */ + if (!(fit_image_verify(fit_hdr, node_offset))) { + printf("fsl-mc: ERROR: Bad firmware image (bad CRC)\n"); + return -EINVAL; + } + + /* Get address and size of raw image */ + fit_image_get_data(fit_hdr, node_offset, &data, &size); + + *raw_image_addr = data; + *raw_image_size = size; + + return 0; +} + +int mc_init(bd_t *bis) +{ + int error = 0; + int timeout = 200000; + struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; + u64 mc_ram_addr; + u64 mc_dpl_offset; + u32 reg_gsr; + u32 mc_fw_boot_status; + void *dpl_fdt_hdr; + int dpl_size; + const void *raw_image_addr; + size_t raw_image_size = 0; + struct fsl_mc_io mc_io; + int portal_id; + struct mc_version mc_ver_info; + + /* + * The MC private DRAM block was already carved at the end of DRAM + * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: + */ + if (gd->bd->bi_dram[1].start) { + mc_ram_addr = + gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; + } else { + mc_ram_addr = + gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; + } + + /* + * Management Complex cores should be held at reset out of POR. + * U-boot should be the first software to touch MC. To be safe, + * we reset all cores again by setting GCR1 to 0. It doesn't do + * anything if they are held at reset. After we setup the firmware + * we kick off MC by deasserting the reset bit for core 0, and + * deasserting the reset bits for Command Portal Managers. + * The stop bits are not touched here. They are used to stop the + * cores when they are active. Setting stop bits doesn't stop the + * cores from fetching instructions when they are released from + * reset. + */ + out_le32(&mc_ccsr_regs->reg_gcr1, 0); + dmb(); + + error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); + if (error != 0) + goto out; + /* + * Load the MC FW at the beginning of the MC private DRAM block: + */ + mc_copy_image("MC Firmware", + (u64)raw_image_addr, raw_image_size, mc_ram_addr); + + /* + * Get address and size of the DPL blob stored in flash: + */ +#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR + dpl_fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; +#else +#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" +#endif + + error = fdt_check_header(dpl_fdt_hdr); + if (error != 0) { + printf("fsl-mc: ERROR: Bad DPL image (bad header)\n"); + goto out; + } + + dpl_size = fdt_totalsize(dpl_fdt_hdr); + if (dpl_size > CONFIG_SYS_LS_MC_DPL_MAX_LENGTH) { + printf("fsl-mc: ERROR: Bad DPL image (too large: %d)\n", + dpl_size); + error = -EINVAL; + goto out; + } + + /* + * Calculate offset in the MC private DRAM block at which the MC DPL + * blob is to be placed: + */ +#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET + BUILD_BUG_ON((CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || + CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); + + mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; +#else + mc_dpl_offset = mc_get_dram_block_size() - + roundup(CONFIG_SYS_LS_MC_DPL_MAX_LENGTH, 4096); + + if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) { + printf("%s: Invalid MC DPL offset: %llu\n", + __func__, mc_dpl_offset); + error = -EINVAL; + goto out; + } +#endif + + /* + * Load the MC DPL blob at the far end of the MC private DRAM block: + * + * TODO: Should we place the DPL at a different location to match + * assumptions of MC firmware about its memory layout? + */ + mc_copy_image("MC DPL blob", + (u64)dpl_fdt_hdr, dpl_size, mc_ram_addr + mc_dpl_offset); + + debug("mc_ccsr_regs %p\n", mc_ccsr_regs); + + /* + * Tell MC where the MC Firmware image was loaded in DDR: + */ + out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr); + out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32)); + out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK); + + /* + * Tell MC where the DPL blob was loaded in DDR, by indicating + * its offset relative to the beginning of the DDR block + * allocated to the MC firmware. The MC firmware is responsible + * for checking that there is no overlap between the DPL blob + * and the runtime heap and stack of the MC firmware itself. + * + * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of + * the GSR MC CCSR register. So, this offset is assumed to be 4-byte + * aligned. + * Care must be taken not to write 1s into bits 31 and 30 of the GSR in + * this case as the SoC COP or PIC will be signaled. + */ + out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2)); + + printf("\nfsl-mc: Booting Management Complex ...\n"); + + /* + * Deassert reset and release MC core 0 to run + */ + out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); + dmb(); + debug("Polling mc_ccsr_regs->reg_gsr ...\n"); + + for (;;) { + reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); + mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); + if (mc_fw_boot_status & 0x1) + break; + + udelay(1000); /* throttle polling */ + if (timeout-- <= 0) + break; + } + + if (timeout <= 0) { + printf("fsl-mc: timeout booting management complex firmware\n"); + + /* TODO: Get an error status from an MC CCSR register */ + error = -ETIMEDOUT; + goto out; + } + + if (mc_fw_boot_status != 0x1) { + /* + * TODO: Identify critical errors from the GSR register's FS + * field and for those errors, set error to -ENODEV or other + * appropriate errno, so that the status property is set to + * failure in the fsl,dprc device tree node. + */ + printf("fsl-mc: WARNING: Firmware booted with error (GSR: %#x)\n", + reg_gsr); + } + + /* + * TODO: need to obtain the portal_id for the root container from the + * DPL + */ + portal_id = 0; + + /* + * Check that the MC firmware is responding portal commands: + */ + mc_io.mmio_regs = SOC_MC_PORTAL_ADDR(portal_id); + debug("Checking access to MC portal of root DPRC container (portal_id %d, portal physical addr %p)\n", + portal_id, mc_io.mmio_regs); + + error = mc_get_version(&mc_io, &mc_ver_info); + if (error != 0) { + printf("fsl-mc: ERROR: Firmware version check failed (error: %d)\n", + error); + goto out; + } + + if (MC_VER_MAJOR != mc_ver_info.major) + printf("fsl-mc: ERROR: Firmware major version mismatch (found: %d, expected: %d)\n", + mc_ver_info.major, MC_VER_MAJOR); + + if (MC_VER_MINOR != mc_ver_info.minor) + printf("fsl-mc: WARNING: Firmware minor version mismatch (found: %d, expected: %d)\n", + mc_ver_info.minor, MC_VER_MINOR); + + printf("fsl-mc: Management Complex booted (version: %d.%d.%d, boot status: %#x)\n", + mc_ver_info.major, mc_ver_info.minor, mc_ver_info.revision, + mc_fw_boot_status); +out: + if (error != 0) + mc_boot_status = -error; + else + mc_boot_status = 0; + + return error; +} + +int get_mc_boot_status(void) +{ + return mc_boot_status; +} + +/** + * Return the actual size of the MC private DRAM block. + * + * NOTE: For now this function always returns the minimum required size, + * However, in the future, the actual size may be obtained from an environment + * variable. + */ +unsigned long mc_get_dram_block_size(void) +{ + return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; +} diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c new file mode 100644 index 00000000000..7c8e003ad00 --- /dev/null +++ b/drivers/net/fsl-mc/mc_sys.c @@ -0,0 +1,63 @@ +/* + * Freescale Layerscape MC I/O wrapper + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * Author: German Rivera + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include + +#define MC_CMD_HDR_READ_CMDID(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S)) + +/** + * mc_send_command - Send MC command and wait for response + * + * @mc_io: Pointer to MC I/O object to be used + * @cmd: MC command buffer. On input, it contains the command to send to the MC. + * On output, it contains the response from the MC if any. + * + * Depending on the sharing option specified when creating the MC portal + * wrapper, this function will use a spinlock or mutex to ensure exclusive + * access to the MC portal from the point when the command is sent until a + * response is received from the MC. + */ +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd) +{ + enum mc_cmd_status status; + int timeout = 2000; + + mc_write_command(mc_io->mmio_regs, cmd); + + for ( ; ; ) { + status = mc_read_response(mc_io->mmio_regs, cmd); + if (status != MC_CMD_STATUS_READY) + break; + + if (--timeout == 0) { + printf("Error: Timeout waiting for MC response\n"); + return -ETIMEDOUT; + } + + udelay(500); + } + + if (status != MC_CMD_STATUS_OK) { + printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n", + mc_io->mmio_regs, + (unsigned int)MC_CMD_HDR_READ_AUTHID(cmd->header), + (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), + (unsigned int)status); + + return -EIO; + } + + return 0; +} diff --git a/drivers/net/fsl_mc/Makefile b/drivers/net/fsl_mc/Makefile deleted file mode 100644 index 483408623c4..00000000000 --- a/drivers/net/fsl_mc/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# Copyright 2014 Freescale Semiconductor, Inc. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Layerscape MC driver -obj-y += mc.o diff --git a/drivers/net/fsl_mc/mc.c b/drivers/net/fsl_mc/mc.c deleted file mode 100644 index df84568a945..00000000000 --- a/drivers/net/fsl_mc/mc.c +++ /dev/null @@ -1,266 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; -static int mc_boot_status; - -/** - * Copying MC firmware or DPL image to DDR - */ -static int mc_copy_image(const char *title, - u64 image_addr, u32 image_size, u64 mc_ram_addr) -{ - debug("%s copied to address %p\n", title, (void *)mc_ram_addr); - memcpy((void *)mc_ram_addr, (void *)image_addr, image_size); - return 0; -} - -/** - * MC firmware FIT image parser checks if the image is in FIT - * format, verifies integrity of the image and calculates - * raw image address and size values. - * Returns 0 if success and 1 if any of the above mentioned - * task fail. - **/ - -int parse_mc_firmware_fit_image(const void **raw_image_addr, - size_t *raw_image_size) -{ - int format; - void *fit_hdr; - int node_offset; - const void *data; - size_t size; - const char *uname = "firmware"; - - /* Check if the image is in NOR flash*/ -#ifdef CONFIG_SYS_LS_MC_FW_IN_NOR - fit_hdr = (void *)CONFIG_SYS_LS_MC_FW_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_FW_IN_xxx defined" -#endif - - /* Check if Image is in FIT format */ - format = genimg_get_format(fit_hdr); - - if (format != IMAGE_FORMAT_FIT) { - debug("Not a FIT image\n"); - return 1; - } - - if (!fit_check_format(fit_hdr)) { - debug("Bad FIT image format\n"); - return 1; - } - - node_offset = fit_image_get_node(fit_hdr, uname); - - if (node_offset < 0) { - debug("Can not find %s subimage\n", uname); - return 1; - } - - /* Verify MC firmware image */ - if (!(fit_image_verify(fit_hdr, node_offset))) { - debug("Bad MC firmware hash"); - return 1; - } - - /* Get address and size of raw image */ - fit_image_get_data(fit_hdr, node_offset, &data, &size); - - *raw_image_addr = data; - *raw_image_size = size; - - return 0; -} - -int mc_init(bd_t *bis) -{ - int error = 0; - int timeout = 200000; - struct mc_ccsr_registers __iomem *mc_ccsr_regs = MC_CCSR_BASE_ADDR; - u64 mc_ram_addr; - u64 mc_dpl_offset; - u32 reg_gsr; - u32 mc_fw_boot_status; - void *fdt_hdr; - int dpl_size; - const void *raw_image_addr; - size_t raw_image_size = 0; - - BUILD_BUG_ON(CONFIG_SYS_LS_MC_FW_LENGTH % 4 != 0); - - /* - * The MC private DRAM block was already carved at the end of DRAM - * by board_init_f() using CONFIG_SYS_MEM_TOP_HIDE: - */ - if (gd->bd->bi_dram[1].start) { - mc_ram_addr = - gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size; - } else { - mc_ram_addr = - gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; - } - - /* - * Management Complex cores should be held at reset out of POR. - * U-boot should be the first software to touch MC. To be safe, - * we reset all cores again by setting GCR1 to 0. It doesn't do - * anything if they are held at reset. After we setup the firmware - * we kick off MC by deasserting the reset bit for core 0, and - * deasserting the reset bits for Command Portal Managers. - * The stop bits are not touched here. They are used to stop the - * cores when they are active. Setting stop bits doesn't stop the - * cores from fetching instructions when they are released from - * reset. - */ - out_le32(&mc_ccsr_regs->reg_gcr1, 0); - dmb(); - - error = parse_mc_firmware_fit_image(&raw_image_addr, &raw_image_size); - if (error != 0) - goto out; - /* - * Load the MC FW at the beginning of the MC private DRAM block: - */ - mc_copy_image( - "MC Firmware", - (u64)raw_image_addr, - raw_image_size, - mc_ram_addr); - - /* - * Calculate offset in the MC private DRAM block at which the MC DPL - * blob is to be placed: - */ -#ifdef CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET - BUILD_BUG_ON( - (CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET & 0x3) != 0 || - CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET > 0xffffffff); - - mc_dpl_offset = CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET; -#else - mc_dpl_offset = mc_get_dram_block_size() - - roundup(CONFIG_SYS_LS_MC_DPL_LENGTH, 4096); - - if ((mc_dpl_offset & 0x3) != 0 || mc_dpl_offset > 0xffffffff) { - printf("%s: Invalid MC DPL offset: %llu\n", - __func__, mc_dpl_offset); - error = -EINVAL; - goto out; - } -#endif - - /* Check if DPL image is in NOR flash */ -#ifdef CONFIG_SYS_LS_MC_DPL_IN_NOR - fdt_hdr = (void *)CONFIG_SYS_LS_MC_DPL_ADDR; -#else -#error "No CONFIG_SYS_LS_MC_DPL_IN_xxx defined" -#endif - - dpl_size = fdt_totalsize(fdt_hdr); - - /* - * Load the MC DPL blob at the far end of the MC private DRAM block: - */ - mc_copy_image( - "MC DPL blob", - (u64)fdt_hdr, - dpl_size, - mc_ram_addr + mc_dpl_offset); - - debug("mc_ccsr_regs %p\n", mc_ccsr_regs); - - /* - * Tell MC where the MC Firmware image was loaded in DDR: - */ - out_le32(&mc_ccsr_regs->reg_mcfbalr, (u32)mc_ram_addr); - out_le32(&mc_ccsr_regs->reg_mcfbahr, (u32)((u64)mc_ram_addr >> 32)); - out_le32(&mc_ccsr_regs->reg_mcfapr, MCFAPR_BYPASS_ICID_MASK); - - /* - * Tell MC where the DPL blob was loaded in DDR, by indicating - * its offset relative to the beginning of the DDR block - * allocated to the MC firmware. The MC firmware is responsible - * for checking that there is no overlap between the DPL blob - * and the runtime heap and stack of the MC firmware itself. - * - * NOTE: bits [31:2] of this offset need to be stored in bits [29:0] of - * the GSR MC CCSR register. So, this offset is assumed to be 4-byte - * aligned. - * Care must be taken not to write 1s into bits 31 and 30 of the GSR in - * this case as the SoC COP or PIC will be signaled. - */ - out_le32(&mc_ccsr_regs->reg_gsr, (u32)(mc_dpl_offset >> 2)); - - /* - * Deassert reset and release MC core 0 to run - */ - out_le32(&mc_ccsr_regs->reg_gcr1, GCR1_P1_DE_RST | GCR1_M_ALL_DE_RST); - dmb(); - debug("Polling mc_ccsr_regs->reg_gsr ...\n"); - - for (;;) { - reg_gsr = in_le32(&mc_ccsr_regs->reg_gsr); - mc_fw_boot_status = (reg_gsr & GSR_FS_MASK); - if (mc_fw_boot_status & 0x1) - break; - - udelay(1000); /* throttle polling */ - if (timeout-- <= 0) - break; - } - - if (timeout <= 0) { - printf("%s: timeout booting management complex firmware\n", - __func__); - - /* TODO: Get an error status from an MC CCSR register */ - error = -ETIMEDOUT; - goto out; - } - - printf("Management complex booted (boot status: %#x)\n", - mc_fw_boot_status); - - if (mc_fw_boot_status != 0x1) { - /* - * TODO: Identify critical errors from the GSR register's FS - * field and for those errors, set error to -ENODEV or other - * appropriate errno, so that the status property is set to - * failure in the fsl,dprc device tree node. - */ - } - -out: - if (error != 0) - mc_boot_status = -error; - else - mc_boot_status = 0; - - return error; -} - -int get_mc_boot_status(void) -{ - return mc_boot_status; -} - -/** - * Return the actual size of the MC private DRAM block. - * - * NOTE: For now this function always returns the minimum required size, - * However, in the future, the actual size may be obtained from an environment - * variable. - */ -unsigned long mc_get_dram_block_size(void) -{ - return CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE; -} diff --git a/include/configs/ls2085a_common.h b/include/configs/ls2085a_common.h index 55f4c963608..17a1cde0399 100644 --- a/include/configs/ls2085a_common.h +++ b/include/configs/ls2085a_common.h @@ -207,12 +207,10 @@ #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_LS_MC_FW_IN_NOR #define CONFIG_SYS_LS_MC_FW_ADDR 0x580200000ULL -/* TODO Actual FW length needs to be determined at runtime from FW header */ -#define CONFIG_SYS_LS_MC_FW_LENGTH (4U * 1024 * 1024) #define CONFIG_SYS_LS_MC_DPL_IN_NOR #define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL /* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPL_LENGTH 4096 +#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH (256 * 1024) #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0xe00000 /* Carve the MC private DRAM block from the end of DRAM */ diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h new file mode 100644 index 00000000000..c2e1ddd18b9 --- /dev/null +++ b/include/fsl-mc/fsl_dpmng.h @@ -0,0 +1,121 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +/*! + * @file fsl_dpmng.h + * @brief Management Complex General API + */ + +#ifndef __FSL_DPMNG_H +#define __FSL_DPMNG_H + +/*! + * @Group grp_dpmng Management Complex General API + * + * @brief Contains general API for the Management Complex firmware + * @{ + */ + +struct fsl_mc_io; + +/** + * @brief Management Complex firmware version information + */ +#define MC_VER_MAJOR 4 +#define MC_VER_MINOR 0 + +struct mc_version { + uint32_t major; + /*!< Major version number: incremented on API compatibility changes */ + uint32_t minor; + /*!< Minor version number: incremented on API additions (that are + * backward compatible); reset when major version is incremented + */ + uint32_t revision; + /*!< Internal revision number: incremented on implementation changes + * and/or bug fixes that have no impact on API + */ +}; + +/** + * @brief Retrieves the Management Complex firmware version information + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[out] mc_ver_info Pointer to version information structure + * + * @returns '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, struct mc_version *mc_ver_info); + +/** + * @brief Resets an AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id); + +/** + * @brief Loads an image to AIOP tile + * + * @param[in] mc_io Pointer to opaque I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] img_iova I/O virtual address of AIOP ELF image + * @param[in] img_size Size of AIOP ELF image in memory (in bytes) + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_load_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + uint64_t img_iova, + uint32_t img_size); + +/** + * @brief AIOP run configuration + */ +struct dpmng_aiop_run_cfg { + uint32_t cores_mask; + /*!< Mask of AIOP cores to run (core 0 in most significant bit) */ + uint64_t options; + /*!< Execution options (currently none defined) */ +}; + +/** + * @brief Starts AIOP tile execution + * + * @param[in] mc_io Pointer to MC portal's I/O object + * @param[in] container_id AIOP container ID + * @param[in] aiop_tile_id AIOP tile ID to reset + * @param[in] cfg AIOP run configuration + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_run_aiop(struct fsl_mc_io *mc_io, + int container_id, + int aiop_tile_id, + const struct dpmng_aiop_run_cfg *cfg); + +/** + * @brief Resets MC portal + * + * This function closes all object handles (tokens) that are currently + * open in the MC portal on which the command is submitted. This allows + * cleanup of stale handles that belong to non-functional user processes. + * + * @param[in] mc_io Pointer to MC portal's I/O object + * + * @returns '0' on Success; Error code otherwise. + */ +int dpmng_reset_mc_portal(struct fsl_mc_io *mc_io); + +/** @} */ + +#endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h new file mode 100644 index 00000000000..b9f089e5f32 --- /dev/null +++ b/include/fsl-mc/fsl_mc.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2014 Freescale Semiconductor + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __FSL_MC_H__ +#define __FSL_MC_H__ + +#include + +#define MC_CCSR_BASE_ADDR \ + ((struct mc_ccsr_registers __iomem *)0x8340000) + +#define BIT(x) (1 << (x)) +#define GCR1_P1_STOP BIT(31) +#define GCR1_P2_STOP BIT(30) +#define GCR1_P1_DE_RST BIT(23) +#define GCR1_P2_DE_RST BIT(22) +#define GCR1_M1_DE_RST BIT(15) +#define GCR1_M2_DE_RST BIT(14) +#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) +#define GSR_FS_MASK 0x3fffffff +#define MCFAPR_PL_MASK (0x1 << 18) +#define MCFAPR_BMT_MASK (0x1 << 17) +#define MCFAPR_BYPASS_ICID_MASK \ + (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) + +#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) +#define SOC_MC_PORTAL_STRIDE 0x10000 + +#define SOC_MC_PORTAL_ADDR(_portal_id) \ + ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ + (_portal_id) * SOC_MC_PORTAL_STRIDE)) + +struct mc_ccsr_registers { + u32 reg_gcr1; + u32 reserved1; + u32 reg_gsr; + u32 reserved2; + u32 reg_sicbalr; + u32 reg_sicbahr; + u32 reg_sicapr; + u32 reserved3; + u32 reg_mcfbalr; + u32 reg_mcfbahr; + u32 reg_mcfapr; + u32 reserved4[0x2f1]; + u32 reg_psr; + u32 reserved5; + u32 reg_brr[2]; + u32 reserved6[0x80]; + u32 reg_error[]; +}; + +int mc_init(bd_t *bis); + +int get_mc_boot_status(void); +#endif diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h new file mode 100644 index 00000000000..e7fcb5b142b --- /dev/null +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -0,0 +1,132 @@ +/* Copyright 2014 Freescale Semiconductor Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __FSL_MC_CMD_H +#define __FSL_MC_CMD_H + +#define MC_CMD_NUM_OF_PARAMS 7 + +#define MAKE_UMASK64(_width) \ + ((uint64_t)((_width) < 64 ? ((uint64_t)1 << (_width)) - 1 : -1)) + +static inline uint64_t u64_enc(int lsoffset, int width, uint64_t val) +{ + return (uint64_t)(((uint64_t)val & MAKE_UMASK64(width)) << lsoffset); +} +static inline uint64_t u64_dec(uint64_t val, int lsoffset, int width) +{ + return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); +} + +struct mc_command { + uint64_t header; + uint64_t params[MC_CMD_NUM_OF_PARAMS]; +}; + +enum mc_cmd_status { + MC_CMD_STATUS_OK = 0x0, /*!< Completed successfully */ + MC_CMD_STATUS_READY = 0x1, /*!< Ready to be processed */ + MC_CMD_STATUS_AUTH_ERR = 0x3, /*!< Authentication error */ + MC_CMD_STATUS_NO_PRIVILEGE = 0x4, /*!< No privilege */ + MC_CMD_STATUS_DMA_ERR = 0x5, /*!< DMA or I/O error */ + MC_CMD_STATUS_CONFIG_ERR = 0x6, /*!< Configuration error */ + MC_CMD_STATUS_TIMEOUT = 0x7, /*!< Operation timed out */ + MC_CMD_STATUS_NO_RESOURCE = 0x8, /*!< No resources */ + MC_CMD_STATUS_NO_MEMORY = 0x9, /*!< No memory available */ + MC_CMD_STATUS_BUSY = 0xA, /*!< Device is busy */ + MC_CMD_STATUS_UNSUPPORTED_OP = 0xB, /*!< Unsupported operation */ + MC_CMD_STATUS_INVALID_STATE = 0xC /*!< Invalid state */ +}; + +#define MC_CMD_HDR_CMDID_O 52 /* Command ID field offset */ +#define MC_CMD_HDR_CMDID_S 12 /* Command ID field size */ +#define MC_CMD_HDR_AUTHID_O 38 /* Authentication ID field offset */ +#define MC_CMD_HDR_AUTHID_S 10 /* Authentication ID field size */ +#define MC_CMD_HDR_STATUS_O 16 /* Status field offset */ +#define MC_CMD_HDR_STATUS_S 8 /* Status field size*/ +#define MC_CMD_HDR_PRI_O 15 /* Priority field offset */ +#define MC_CMD_HDR_PRI_S 1 /* Priority field size */ + +#define MC_CMD_HDR_READ_STATUS(_hdr) \ + ((enum mc_cmd_status)u64_dec((_hdr), \ + MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) + +#define MC_CMD_HDR_READ_AUTHID(_hdr) \ + ((uint16_t)u64_dec((_hdr), MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S)) + +#define MC_CMD_PRI_LOW 0 /*!< Low Priority command indication */ +#define MC_CMD_PRI_HIGH 1 /*!< High Priority command indication */ + +#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ + ((_cmd).params[_param] |= u64_enc((_offset), (_width), _arg)) + +#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ + (_arg = (_type)u64_dec(_cmd.params[_param], (_offset), (_width))) + +static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, + uint8_t priority, + uint16_t auth_id) +{ + uint64_t hdr; + + hdr = u64_enc(MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S, cmd_id); + hdr |= u64_enc(MC_CMD_HDR_AUTHID_O, MC_CMD_HDR_AUTHID_S, auth_id); + hdr |= u64_enc(MC_CMD_HDR_PRI_O, MC_CMD_HDR_PRI_S, priority); + hdr |= u64_enc(MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S, + MC_CMD_STATUS_READY); + + return hdr; +} + +/** + * mc_write_command - writes a command to a Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @cmd: pointer to a filled command + */ +static inline void mc_write_command(struct mc_command __iomem *portal, + struct mc_command *cmd) +{ + int i; + + /* copy command parameters into the portal */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + writeq(cmd->params[i], &portal->params[i]); + + /* submit the command by writing the header */ + writeq(cmd->header, &portal->header); +} + +/** + * mc_read_response - reads the response for the last MC command from a + * Management Complex (MC) portal + * + * @portal: pointer to an MC portal + * @resp: pointer to command response buffer + * + * Returns MC_CMD_STATUS_OK on Success; Error code otherwise. + */ +static inline enum mc_cmd_status mc_read_response( + struct mc_command __iomem *portal, + struct mc_command *resp) +{ + int i; + enum mc_cmd_status status; + + /* Copy command response header from MC portal: */ + resp->header = readq(&portal->header); + status = MC_CMD_HDR_READ_STATUS(resp->header); + if (status != MC_CMD_STATUS_OK) + return status; + + /* Copy command response data from MC portal: */ + for (i = 0; i < MC_CMD_NUM_OF_PARAMS; i++) + resp->params[i] = readq(&portal->params[i]); + + return status; +} + +int mc_send_command(struct fsl_mc_io *mc_io, struct mc_command *cmd); + +#endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl-mc/fsl_mc_sys.h b/include/fsl-mc/fsl_mc_sys.h new file mode 100644 index 00000000000..c0befe01d28 --- /dev/null +++ b/include/fsl-mc/fsl_mc_sys.h @@ -0,0 +1,26 @@ +/* + * Freescale Layerscape Management Complex (MC) Environment-specific code + * + * Copyright (C) 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _FSL_MC_SYS_H +#define _FSL_MC_SYS_H + +#include + +struct mc_command; + +/* + * struct mc_portal_wrapper - MC command portal wrapper object + */ +struct fsl_mc_io { + struct mc_command __iomem *mmio_regs; +}; + +int mc_send_command(struct fsl_mc_io *mc_io, + struct mc_command *cmd); + +#endif /* _FSL_MC_SYS_H */ diff --git a/include/fsl_mc.h b/include/fsl_mc.h deleted file mode 100644 index b9f089e5f32..00000000000 --- a/include/fsl_mc.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright (C) 2014 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __FSL_MC_H__ -#define __FSL_MC_H__ - -#include - -#define MC_CCSR_BASE_ADDR \ - ((struct mc_ccsr_registers __iomem *)0x8340000) - -#define BIT(x) (1 << (x)) -#define GCR1_P1_STOP BIT(31) -#define GCR1_P2_STOP BIT(30) -#define GCR1_P1_DE_RST BIT(23) -#define GCR1_P2_DE_RST BIT(22) -#define GCR1_M1_DE_RST BIT(15) -#define GCR1_M2_DE_RST BIT(14) -#define GCR1_M_ALL_DE_RST (GCR1_M1_DE_RST | GCR1_M2_DE_RST) -#define GSR_FS_MASK 0x3fffffff -#define MCFAPR_PL_MASK (0x1 << 18) -#define MCFAPR_BMT_MASK (0x1 << 17) -#define MCFAPR_BYPASS_ICID_MASK \ - (MCFAPR_PL_MASK | MCFAPR_BMT_MASK) - -#define SOC_MC_PORTALS_BASE_ADDR ((void __iomem *)0x00080C000000) -#define SOC_MC_PORTAL_STRIDE 0x10000 - -#define SOC_MC_PORTAL_ADDR(_portal_id) \ - ((void __iomem *)((uintptr_t)SOC_MC_PORTALS_BASE_ADDR + \ - (_portal_id) * SOC_MC_PORTAL_STRIDE)) - -struct mc_ccsr_registers { - u32 reg_gcr1; - u32 reserved1; - u32 reg_gsr; - u32 reserved2; - u32 reg_sicbalr; - u32 reg_sicbahr; - u32 reg_sicapr; - u32 reserved3; - u32 reg_mcfbalr; - u32 reg_mcfbahr; - u32 reg_mcfapr; - u32 reserved4[0x2f1]; - u32 reg_psr; - u32 reserved5; - u32 reg_brr[2]; - u32 reserved6[0x80]; - u32 reg_error[]; -}; - -int mc_init(bd_t *bis); - -int get_mc_boot_status(void); -#endif -- cgit v1.3.1 From 180b8688dca2a7731a291a7660ae188e6eec84b8 Mon Sep 17 00:00:00 2001 From: Minghuan Lian Date: Wed, 21 Jan 2015 17:29:19 +0800 Subject: arm/ls1021a: add PCIe settings The patch enables and adds PCIe settings for boards LS1021AQDS and LS1021ATWR. Signed-off-by: Minghuan Lian Reviewed-by: York Sun --- include/configs/ls1021aqds.h | 24 ++++++++++++++++++++++++ include/configs/ls1021atwr.h | 24 ++++++++++++++++++++++++ 2 files changed, 48 insertions(+) (limited to 'include') diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 2874ccc6fad..3dc4da391b3 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -510,6 +510,30 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 0a0bb5f1099..a13876b5501 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -303,6 +303,30 @@ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#define CONFIG_SYS_PCI_64BIT + +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ + +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP +#define CONFIG_E1000 +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII -- cgit v1.3.1 From 0e1bf614d5045b060db8e1bf9e7f69afdf1c592f Mon Sep 17 00:00:00 2001 From: Volodymyr Riazantsev Date: Tue, 20 Jan 2015 10:16:44 -0500 Subject: mmc: fsl_esdhc: Add support for DDR mode Add support of the DDR mode for eSDHC driver. Enable it for i.MX6 SoC family only. Signed-off-by: Volodymyr Riazantsev Reviewed-by: York Sun --- drivers/mmc/fsl_esdhc.c | 8 ++++++-- include/configs/mx6_common.h | 2 ++ include/fsl_esdhc.h | 1 + 3 files changed, 9 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c55eb28217b..f5d2ccba159 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -319,7 +319,8 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) esdhc_write32(®s->cmdarg, cmd->cmdarg); #if defined(CONFIG_FSL_USDHC) esdhc_write32(®s->mixctrl, - (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)); + (esdhc_read32(®s->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F) + | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); esdhc_write32(®s->xfertyp, xfertyp & 0xFFFF0000); #else esdhc_write32(®s->xfertyp, xfertyp); @@ -442,7 +443,7 @@ static void set_sysctl(struct mmc *mmc, uint clock) if ((sdhc_clk / (div * pre_div)) <= clock) break; - pre_div >>= 1; + pre_div >>= mmc->ddr_mode ? 2 : 1; div -= 1; clk = (pre_div << 8) | (div << 4); @@ -601,6 +602,9 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) } cfg->cfg.host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC; +#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + cfg->cfg.host_caps |= MMC_MODE_DDR_52MHz; +#endif if (cfg->max_bus_width > 0) { if (cfg->max_bus_width < 8) diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index e0528ce4b92..29b72b2e9dd 100644 --- a/include/configs/mx6_common.h +++ b/include/configs/mx6_common.h @@ -28,6 +28,8 @@ #define CONFIG_SYS_PL310_BASE L2_PL310_BASE #endif +#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE + #define CONFIG_MP #define CONFIG_MXC_GPT_HCLK diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index c1b6648591e..313fa1e312a 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -108,6 +108,7 @@ #define XFERTYP_RSPTYP_48_BUSY 0x00030000 #define XFERTYP_MSBSEL 0x00000020 #define XFERTYP_DTDSEL 0x00000010 +#define XFERTYP_DDREN 0x00000008 #define XFERTYP_AC12EN 0x00000004 #define XFERTYP_BCEN 0x00000002 #define XFERTYP_DMAEN 0x00000001 -- cgit v1.3.1 From 50bb94c9496113c8bb588c4d82f3d6c61279dc02 Mon Sep 17 00:00:00 2001 From: Enric Balletbo i Serra Date: Tue, 24 Feb 2015 19:27:15 +0100 Subject: OMAP3: igep0032: Fix regression due commit f3b4bc45. Commit referenced in subject breaks IGEP0032 build with the following error: drivers/misc/status_led.c:30:7: error: 'RED_LED_GPIO' undeclared here (not in a function) scripts/Makefile.build:275: recipe for target 'drivers/misc/status_led.o' failed make[2]: *** [drivers/misc/status_led.o] Error 1 scripts/Makefile.build:420: recipe for target 'drivers/misc' failed make[1]: *** [drivers/misc] Error 2 Makefile:1093: recipe for target 'drivers' failed make: *** [drivers] Error 2 Fix this by skipping the status led on IGEP0032 machine as is not available and throw an error for future machines if the status led is not configured to avoid build breakage. Reported-by: Albert ARIBAUD Signed-off-by: Enric Balletbo i Serra --- include/configs/omap3_igep00x0.h | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h index 6295ec505f8..a5e7d8f6a41 100644 --- a/include/configs/omap3_igep00x0.h +++ b/include/configs/omap3_igep00x0.h @@ -29,21 +29,24 @@ #define CONFIG_REVISION_TAG 1 -/* Status LED */ +/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */ +#if (CONFIG_MACH_TYPE != MACH_TYPE_IGEP0032) #define CONFIG_STATUS_LED #define CONFIG_BOARD_SPECIFIC_LED #define CONFIG_GPIO_LED #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) #define RED_LED_GPIO 27 -#endif -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) +#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) #define RED_LED_GPIO 16 +#else +#error "status LED not defined for this machine." #endif #define RED_LED_DEV 0 #define STATUS_LED_BIT RED_LED_GPIO #define STATUS_LED_STATE STATUS_LED_ON #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) #define STATUS_LED_BOOT RED_LED_DEV +#endif /* GPIO banks */ #define CONFIG_OMAP3_GPIO_3 /* GPIO64 .. 95 is in GPIO bank 3 */ -- cgit v1.3.1 From e02ee2548afe22f7d197b89df2ae7bd72f1df630 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 22:26:20 +0900 Subject: kconfig: switch to single .config configuration When Kconfig for U-boot was examined, one of the biggest issues was how to support multiple images (Normal, SPL, TPL). There were actually two options, "single .config" and "multiple .config". After some discussions and thought experiments, I chose the latter, i.e. to create ".config", "spl/.config", "tpl/.config" for Normal, SPL, TPL, respectively. It is true that the "multiple .config" strategy provided us the maximum flexibility and helped to avoid duplicating CONFIGs among Normal, SPL, TPL, but I have noticed some fatal problems: [1] It is impossible to share CONFIG options across the images. If you change the configuration of Main image, you often have to adjust some SPL configurations correspondingly. Currently, we cannot handle the dependencies between them. It means one of the biggest advantages of Kconfig is lost. [2] It is too painful to change both ".config" and "spl/.config". Sunxi guys started to work around this problem by creating a new configuration target. Commit cbdd9a9737cc (sunxi: kconfig: Add %_felconfig rule to enable FEL build of sunxi platforms.) added "make *_felconfig" to enable CONFIG_SPL_FEL on both images. Changing the configuration of multiple images in one command is a generic demand. The current implementation cannot propose any good solution about this. [3] Kconfig files are getting ugly and difficult to understand. Commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to Kconfig) has sprinkled "if !SPL_BUILD" over the Kconfig files. [4] The build system got more complicated than it should be. To adjust Linux-originated Kconfig to U-Boot, the helper script "scripts/multiconfig.sh" was introduced. Writing a complicated text processor is a shell script sometimes caused problems. Now I believe the "single .config" will serve us better. With it, all the problems above would go away. Instead, we will have to add some CONFIG_SPL_* (and CONFIG_TPL_*) options such as CONFIG_SPL_DM, but we will not have much. Anyway, this is what we do now in scripts/Makefile.spl. I admit my mistake with my apology and this commit switches to the single .config configuration. It is not so difficult to do that: - Remove unnecessary processings from scripts/multiconfig.sh This file will remain for a while to support the current defconfig format. It will be removed after more cleanups are done. - Adjust some makefiles and Kconfigs - Add some entries to include/config_uncmd_spl.h and the new file scripts/Makefile.uncmd_spl. Some CONFIG options that are not supported on SPL must be disabled because one .config is shared between SPL and U-Boot proper going forward. I know this is not a beautiful solution and I think we can do better, but let's see how much we will have to describe them. - update doc/README.kconfig More cleaning up patches will follow this. Signed-off-by: Masahiro Yamada Reviewed-by: Simon Glass --- Kconfig | 14 -- arch/arm/cpu/armv7/uniphier/Kconfig | 1 - arch/arm/mach-tegra/Kconfig | 2 +- config.mk | 5 + configs/ph1_ld4_defconfig | 2 +- configs/ph1_pro4_defconfig | 2 +- configs/ph1_sld8_defconfig | 2 +- doc/README.kconfig | 132 +++++------------- drivers/mtd/nand/Kconfig | 2 +- include/config_uncmd_spl.h | 9 ++ scripts/Makefile.autoconf | 36 +++-- scripts/Makefile.build | 3 +- scripts/Makefile.spl | 10 +- scripts/Makefile.uncmd_spl | 16 +++ scripts/multiconfig.sh | 261 +----------------------------------- 15 files changed, 108 insertions(+), 389 deletions(-) create mode 100644 scripts/Makefile.uncmd_spl (limited to 'include') diff --git a/Kconfig b/Kconfig index 823f1e2b212..bb9b5c27fff 100644 --- a/Kconfig +++ b/Kconfig @@ -8,10 +8,6 @@ config UBOOTVERSION string option env="UBOOTVERSION" -config KCONFIG_OBJDIR - string - option env="KCONFIG_OBJDIR" - # Allow defaults in arch-specific code to override any given here source "arch/Kconfig" @@ -90,16 +86,6 @@ endmenu # General setup menu "Boot images" -config SPL_BUILD - bool - depends on $KCONFIG_OBJDIR="spl" || $KCONFIG_OBJDIR="tpl" - default y - -config TPL_BUILD - bool - depends on $KCONFIG_OBJDIR="tpl" - default y - config SUPPORT_SPL bool diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 8fdef28c02d..9bbc011eeea 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -71,7 +71,6 @@ config CMD_DDRPHY_DUMP choice prompt "DDR3 Frequency select" - depends on SPL_BUILD config DDR_FREQ_1600 bool "DDR3 1600" diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 3a8e2b19d67..8569167369c 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -24,7 +24,7 @@ config SYS_MALLOC_F_LEN default 0x1800 config USE_PRIVATE_LIBGCC - default y if SPL_BUILD + default y config DM default y if !SPL_BUILD diff --git a/config.mk b/config.mk index 64c2951ac1e..6282919482b 100644 --- a/config.mk +++ b/config.mk @@ -24,6 +24,11 @@ VENDOR := ARCH := $(CONFIG_SYS_ARCH:"%"=%) CPU := $(CONFIG_SYS_CPU:"%"=%) +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_TEGRA +CPU := arm720t +endif +endif BOARD := $(CONFIG_SYS_BOARD:"%"=%) ifneq ($(CONFIG_SYS_VENDOR),) VENDOR := $(CONFIG_SYS_VENDOR:"%"=%) diff --git a/configs/ph1_ld4_defconfig b/configs/ph1_ld4_defconfig index 86b4b15724b..fa8d291ca19 100644 --- a/configs/ph1_ld4_defconfig +++ b/configs/ph1_ld4_defconfig @@ -39,4 +39,4 @@ CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -S:CONFIG_SPL_NAND_DENALI=y +CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_pro4_defconfig b/configs/ph1_pro4_defconfig index 242bcf92635..12f069400f0 100644 --- a/configs/ph1_pro4_defconfig +++ b/configs/ph1_pro4_defconfig @@ -39,4 +39,4 @@ CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -S:CONFIG_SPL_NAND_DENALI=y +CONFIG_SPL_NAND_DENALI=y diff --git a/configs/ph1_sld8_defconfig b/configs/ph1_sld8_defconfig index 8e95f17e6d1..e66d1665662 100644 --- a/configs/ph1_sld8_defconfig +++ b/configs/ph1_sld8_defconfig @@ -39,4 +39,4 @@ CONFIG_DM_I2C=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -S:CONFIG_SPL_NAND_DENALI=y +CONFIG_SPL_NAND_DENALI=y diff --git a/doc/README.kconfig b/doc/README.kconfig index 69dc45970b8..288d17d2324 100644 --- a/doc/README.kconfig +++ b/doc/README.kconfig @@ -17,109 +17,45 @@ source directory for a basic specification of Kconfig. Difference from Linux's Kconfig ------------------------------- -The biggest difference between Linux Kernel and U-Boot in terms of the -configuration is that U-Boot has to configure multiple boot images per board: -Normal, SPL, TPL. -Kconfig functions need to be expanded for U-Boot to handle multiple images. -The files scripts/kconfig/* were imported from Linux Kernel and adjusted -for that purpose. +Here are some worth-mentioning configuration targets. -See below for how each configuration target works in U-Boot: +- silentoldconfig -- config, nconfig, menuconfig, xconfig, gconfig + This target updates .config, include/generated/autoconf.h and + include/configs/* as in Linux. In U-Boot, it also does the followings + for the compatibility with the old configuration system: - These targets are used to configure Normal and create (or modify) the - .config file. For SPL configuration, the configutation targets are prefixed - with "spl/", for example "make spl/config", "make spl/menuconfig", etc. - Those targets create or modify the spl/.config file. Likewise, run - "make tpl/config", "make tpl/menuconfig", etc. for TPL. + * create a symbolic link "arch/${ARCH}/include/asm/arch" pointing to + the SoC/CPU specific header directory + * create include/config.h + * create include/autoconf.mk + * create spl/include/autoconf.mk (SPL and TPL only) + * create tpl/include/autoconf.mk (TPL only) -- silentoldconfig + If we could completely switch to Kconfig in a long run + (i.e. remove all the include/configs/*.h), those additional processings + above would be removed. - This target updates .config, include/generated/autoconf.h and - include/configs/*. In U-Boot, the same thing is done for SPL, TPL, - if supported by the target board. Depending on whether CONFIG_SPL and - CONFIG_TPL are defined, "make silentoldconfig" iterates three times at most - changing the work directory. - - To sum up, "make silentoldconfig" possibly updates: - - .config, include/generated/autoconf.h, include/config/* - - spl/.config, spl/include/generated/autoconf.h, spl/include/config/* - (in case CONFIG_SPL=y) - - tpl/.config, tpl/include/generated/autoconf.h, tpl/include/config/* - (in case CONFIG_TPL=y) - -- defconfig, _defconfig - - The target "_defconfig" is used to create the .config based on the - file configs/_defconfig. The "defconfig" target is the same - except it checks for a file specified with KBUILD_DEFCONFIG environment. - - Note: - The defconfig files are placed under the "configs" directory, - not "arch/$(ARCH)/configs". This is because "ARCH" is not necessarily - given from the command line for the U-Boot configuration and build. - - The defconfig file format in U-Boot has the special syntax; each line has - ":" prefix to show which image(s) the line is valid for. - For example, - - CONFIG_FOO=100 - S:CONFIG_FOO=200 - T:CONFIG_FOO=300 - ST:CONFIG_BAR=y - +S:CONFIG_BAZ=y - +T:CONFIG_QUX=y - +ST:CONFIG_QUUX=y - - Here, the ":" prefix is one of: - None - the line is valid only for Normal image - S: - the line is valid only for SPL image - T: - the line is valid only for TPL image - ST: - the line is valid for SPL and TPL images - +S: - the line is valid for Normal and SPL images - +T: - the line is valid for Normal and TPL images - +ST: - the line is valid for Normal, SPL and TPL images - - So, if neither CONFIG_SPL nor CONFIG_TPL is defined, the defconfig file - has no ":" part and therefore has the same form as in Linux. - From the example defconfig shown above, three separete configuration sets - are generated and used for creating .config, spl/.config and tpl/.config. - - - Input for the default configuration of Normal - CONFIG_FOO=100 - CONFIG_BAZ=y - CONFIG_QUX=y - CONFIG_QUUX=y - - - Input for the default configuration of SPL - CONFIG_FOO=200 - CONFIG_BAR=y - CONFIG_BAZ=y - CONFIG_QUUX=y - - - Input for the default configuration of TPL - CONFIG_FOO=300 - CONFIG_BAR=y - CONFIG_QUX=y - CONFIG_QUUX=y - -- savedefconfig - - This is the reverse operation of "make defconfig". If neither CONFIG_SPL - nor CONFIG_TPL is defined in the .config file, it works like "savedefconfig" - in Linux Kernel: creates the minimal set of config based on the .config - and saves it into the "defconfig" file. If CONFIG_SPL (and CONFIG_TPL) is - defined, the common lines among .config, spl/.config (and tpl/.config) are - coalesced together with "" prefix for each line as shown above. - This file can be used as an input of "defconfig" target. +- defconfig + + In U-Boot, "make defconfig" is a shorthand of "make sandbox_defconfig" + +- _defconfig + + Now it works as in Linux. + The prefixes such as "+S:" in *_defconfig are deprecated. + You can simply remove the prefixes. Do not add them for new boards. - _config This does not exist in Linux's Kconfig. + "make _config" works the same as "make _defconfig". Prior to Kconfig, in U-Boot, "make _config" was used for the - configuration. It is still supported for backward compatibility and - its behavior is the same as "make _defconfig". + configuration. It is still supported for backward compatibility, so + we do not need to update the distro recipes. + + +The other configuration targets work as in Linux Kernel. Migration steps to Kconfig @@ -137,14 +73,10 @@ based configuration as follows: Configuration files for use in C sources - include/generated/autoconf.h (generated by Kconfig for Normal) - - spl/include/generated/autoconf.h (generated by Kconfig for SPL) - - tpl/include/generated/autoconf.h (generated by Kconfig for TPL) - include/configs/.h (exists for all boards) Configuration file for use in makefiles - - include/config/auto.conf (generated by Kconfig for Normal) - - spl/include/config/auto.conf (generated by Kconfig for SPL) - - tpl/include/config/auto.conf (generated by Kconfig for TPL) + - include/config/auto.conf (generated by Kconfig) - include/autoconf.mk (generated by the old config for Normal) - spl/include/autoconfig.mk (generated by the old config for SPL) - tpl/include/autoconfig.mk (generated by the old config for TPL) @@ -215,8 +147,8 @@ TODO CONFIG_SYS_EXTRA_OPTIONS should not be used for new boards. - In the pre-Kconfig, a single board had multiple entries in the boards.cfg - file with differences in the option fields. The correspoing defconfig files - were auto-generated when switching to Kconfig. Now we have too many + file with differences in the option fields. The corresponding defconfig + files were auto-generated when switching to Kconfig. Now we have too many defconfig files compared with the number of the supported boards. It is recommended to have only one defconfig per board and allow users to select the config options. diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index c24221499bf..ccd8211eb29 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -36,7 +36,7 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES endif -if SPL_BUILD +if SPL config SPL_NAND_DENALI bool "Support Denali NAND controller for SPL" diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 9cb7a9a1fcf..9f0fe444433 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -20,5 +20,14 @@ #undef CONFIG_CMD_SNTP #undef CONFIG_CMD_TFTPPUT #undef CONFIG_CMD_TFTPSRV +#undef CONFIG_OF_CONTROL + +#ifndef CONFIG_SPL_DM +#undef CONFIG_DM_SERIAL +#undef CONFIG_DM_GPIO +#undef CONFIG_DM_I2C +#undef CONFIG_DM_SPI +#endif + #endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf index 58e1642fb93..f054081c989 100644 --- a/scripts/Makefile.autoconf +++ b/scripts/Makefile.autoconf @@ -7,9 +7,17 @@ # (= When we move all CONFIGs from header files to Kconfig) # this makefile can be deleted. -# obj is "include" or "spl/include" or "tpl/include" -# for non-SPL, SPL, TPL, respectively -include $(obj)/config/auto.conf +__all: include/autoconf.mk include/autoconf.mk.dep + +ifeq ($(shell grep -q '^CONFIG_SPL=y' include/config/auto.conf 2>/dev/null && echo y),y) +__all: spl/include/autoconf.mk +endif + +ifeq ($(shell grep -q '^CONFIG_TPL=y' include/config/auto.conf 2>/dev/null && echo y),y) +__all: tpl/include/autoconf.mk +endif + +include include/config/auto.conf include scripts/Kbuild.include @@ -22,7 +30,6 @@ CPP = $(CC) -E include config.mk UBOOTINCLUDE := \ - -I$(obj) \ -Iinclude \ $(if $(KBUILD_SRC), -I$(srctree)/include) \ -I$(srctree)/arch/$(ARCH)/include \ @@ -48,10 +55,10 @@ include/autoconf.mk.dep: FORCE # same CONFIG macros quiet_cmd_autoconf = GEN $@ cmd_autoconf = \ - $(CPP) $(c_flags) -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ + $(CPP) $(c_flags) $2 -DDO_DEPS_ONLY -dM $(srctree)/include/common.h > $@.tmp && { \ sed -n -f $(srctree)/tools/scripts/define2mk.sed $@.tmp | \ while read line; do \ - if ! grep -q "$${line%=*}=" $(obj)/config/auto.conf; then \ + if ! grep -q "$${line%=*}=" include/config/auto.conf; then \ echo "$$line"; \ fi \ done > $@; \ @@ -60,10 +67,19 @@ quiet_cmd_autoconf = GEN $@ rm $@.tmp; false; \ } -$(obj)/autoconf.mk: FORCE +include/autoconf.mk: FORCE $(call cmd,autoconf) -include/autoconf.mk include/autoconf.mk.dep: include/config.h +spl/include/autoconf.mk: FORCE + $(Q)mkdir -p $(dir $@) + $(call cmd,autoconf,-DCONFIG_SPL_BUILD) + +tpl/include/autoconf.mk: FORCE + $(Q)mkdir -p $(dir $@) + $(call cmd,autoconf,-DCONFIG_SPL_BUILD -DCONFIG_TPL_BUILD) + +include/autoconf.mk include/autoconf.mk.dep \ + spl/include/autoconf.mk tpl/include/autoconf.mk: include/config.h # include/config.h # Prior to Kconfig, it was generated by mkconfig. Now it is created here. @@ -75,10 +91,10 @@ define filechk_config_h done; \ echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\ echo \#include \; \ + echo \#include \; \ echo \#include \; \ echo \#include \; \ - echo \#include \; \ - echo \#include \; ) + echo \#include \;) endef include/config.h: scripts/Makefile.autoconf create_symlink FORCE diff --git a/scripts/Makefile.build b/scripts/Makefile.build index 14cf0925d2f..ac0554eeae1 100644 --- a/scripts/Makefile.build +++ b/scripts/Makefile.build @@ -41,8 +41,9 @@ subdir-ccflags-y := # Read auto.conf if it exists, otherwise ignore # Modified for U-Boot --include $(prefix)/include/config/auto.conf +-include include/config/auto.conf -include $(prefix)/include/autoconf.mk +include scripts/Makefile.uncmd_spl include scripts/Kbuild.include diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index cc189adc0c6..fcacb7fcb49 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -21,13 +21,15 @@ _dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj)) include $(srctree)/scripts/Kbuild.include -UBOOTINCLUDE := -I$(obj)/include $(UBOOTINCLUDE) - --include $(obj)/include/config/auto.conf +-include include/config/auto.conf -include $(obj)/include/autoconf.mk +KBUILD_CPPFLAGS += -DCONFIG_SPL_BUILD +ifeq ($(CONFIG_TPL_BUILD),y) +KBUILD_CPPFLAGS += -DCONFIG_TPL_BUILD +endif + ifeq ($(CONFIG_TPL_BUILD),y) -export CONFIG_TPL_BUILD SPL_BIN := u-boot-tpl else SPL_BIN := u-boot-spl diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl new file mode 100644 index 00000000000..86c938e1f9d --- /dev/null +++ b/scripts/Makefile.uncmd_spl @@ -0,0 +1,16 @@ +# Makefile version of include/config_uncmd_spl.h +# +# TODO: Invent a better way + +ifdef CONFIG_SPL_BUILD +CONFIG_OF_CONTROL= + +ifndef CONFIG_SPL_DM +CONFIG_DM_SERIAL= +CONFIG_DM_GPIO= +CONIFG_DM_I2C= +CONFIG_DM_SPI= +CONFIG_DM_SPI_FLASH= +endif + +endif diff --git a/scripts/multiconfig.sh b/scripts/multiconfig.sh index 366e8faaa66..cc8a787f886 100755 --- a/scripts/multiconfig.sh +++ b/scripts/multiconfig.sh @@ -2,11 +2,7 @@ # # A wrapper script to adjust Kconfig for U-Boot # -# Instead of touching various parts under the scripts/kconfig/ directory, -# pushing necessary adjustments into this single script would be better -# for code maintainance. All the make targets related to the configuration -# (make %config) should be invoked via this script. -# See doc/README.kconfig for further information of Kconfig. +# This file will be removed after cleaning up defconfig files # # Copyright (C) 2014, Masahiro Yamada # @@ -15,77 +11,23 @@ set -e -# Set "DEBUG" enavironment variable to show debug messages -debug () { - if [ $DEBUG ]; then - echo "$@" - fi -} - -# Useful shorthands -build () { - debug $progname: $MAKE -f $srctree/scripts/Makefile.build obj="$@" - $MAKE -f $srctree/scripts/Makefile.build obj="$@" -} - -autoconf () { - debug $progname: $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" - $MAKE -f $srctree/scripts/Makefile.autoconf obj="$@" -} - # Make a configuration target # Usage: # run_make_config # : Make target such as "config", "menuconfig", "defconfig", etc. -# : Target directory where the make command is run. -# Typically "", "spl", "tpl" for Normal, SPL, TPL, respectively. run_make_config () { - target=$1 - objdir=$2 - # Linux expects defconfig files in arch/$(SRCARCH)/configs/ directory, # but U-Boot has them in configs/ directory. # Give SRCARCH=.. to fake scripts/kconfig/Makefile. - options="SRCARCH=.. KCONFIG_OBJDIR=$objdir" - if [ "$objdir" ]; then - options="$options KCONFIG_CONFIG=$objdir/$KCONFIG_CONFIG" - mkdir -p $objdir - fi - - build scripts/kconfig $options $target -} - -# Parse .config file to detect if CONFIG_SPL, CONFIG_TPL is enabled -# and returns: -# "" if neither CONFIG_SPL nor CONFIG_TPL is defined -# "spl" if CONFIG_SPL is defined but CONFIG_TPL is not -# "spl tpl" if both CONFIG_SPL and CONFIG_TPL are defined -get_enabled_subimages() { - if [ ! -r "$KCONFIG_CONFIG" ]; then - # This should never happen - echo "$progname: $KCONFIG_CONFIG not found" >&2 - exit 1 - fi - - # CONFIG_SPL=y -> spl - # CONFIG_TPL=y -> tpl - sed -n -e 's/^CONFIG_SPL=y$/spl/p' -e 's/^CONFIG_TPL=y$/tpl/p' \ - $KCONFIG_CONFIG + $MAKE -f $srctree/scripts/Makefile.build obj=scripts/kconfig SRCARCH=.. $1 } do_silentoldconfig () { run_make_config silentoldconfig - subimages=$(get_enabled_subimages) - - for obj in $subimages - do - mkdir -p $obj/include/config $obj/include/generated - run_make_config silentoldconfig $obj - done # If the following part fails, include/config/auto.conf should be # deleted so "make silentoldconfig" will be re-run on the next build. - autoconf include include/autoconf.mk include/autoconf.mk.dep || { + $MAKE -f $srctree/scripts/Makefile.autoconf || { rm -f include/config/auto.conf exit 1 } @@ -95,14 +37,6 @@ do_silentoldconfig () { # than include/config.h. # Otherwise, 'make silentoldconfig' would be invoked twice. touch include/config/auto.conf - - for obj in $subimages - do - autoconf $obj/include $obj/include/autoconf.mk || { - rm -f include/config/auto.conf - exit 1 - } - done } cleanup_after_defconfig () { @@ -116,7 +50,6 @@ cleanup_after_defconfig () { # do_board_defconfig _defconfig do_board_defconfig () { defconfig_path=$srctree/configs/$1 - tmp_defconfig_path=configs/.tmp_defconfig if [ ! -r $defconfig_path ]; then echo >&2 "***" @@ -126,42 +59,17 @@ do_board_defconfig () { fi mkdir -p arch configs - # defconfig for Normal: - # pick lines without prefixes and lines starting '+' prefix - # and rip the prefixes off. - sed -n -e '/^[+A-Z]*:/!p' -e 's/^+[A-Z]*://p' $defconfig_path \ - > configs/.tmp_defconfig + # prefix "*:" is deprecated. Drop it simply. + sed -e 's/^[+A-Z]*://' $defconfig_path > configs/.tmp_defconfig run_make_config .tmp_defconfig || { cleanup_after_defconfig exit 1 } - for img in $(get_enabled_subimages) - do - symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') - # defconfig for SPL, TPL: - # pick lines with 'S', 'T' prefix and rip the prefixes off - sed -n -e 's/^[+A-Z]*'$symbol'[A-Z]*://p' $defconfig_path \ - > configs/.tmp_defconfig - run_make_config .tmp_defconfig $img || { - cleanup_after_defconfig - exit 1 - } - done - cleanup_after_defconfig } -do_defconfig () { - if [ "$KBUILD_DEFCONFIG" ]; then - do_board_defconfig $KBUILD_DEFCONFIG - echo "*** Default configuration is based on '$KBUILD_DEFCONFIG'" - else - run_make_config defconfig - fi -} - do_board_felconfig () { do_board_defconfig ${1%%_felconfig}_defconfig if ! grep -q CONFIG_ARCH_SUNXI=y .config || ! grep -q CONFIG_SPL=y .config ; then @@ -169,162 +77,11 @@ do_board_felconfig () { exit 1 fi sed -i -e 's/\# CONFIG_SPL_FEL is not set/CONFIG_SPL_FEL=y\nCONFIG_UART0_PORT_F=n/g' \ - .config spl/.config + .config } -do_savedefconfig () { - if [ -r "$KCONFIG_CONFIG" ]; then - subimages=$(get_enabled_subimages) - else - subimages= - fi - - run_make_config savedefconfig - - output_lines= - - # -r option is necessay because some string-type configs may include - # backslashes as an escape character - while read -r line - do - output_lines="$output_lines%$line" - done < defconfig - - for img in $subimages - do - run_make_config savedefconfig $img - - symbol=$(echo $img | cut -c 1 | tr '[a-z]' '[A-Z]') - unmatched= - - while read -r line - do - tmp= - match= - - # "# CONFIG_FOO is not set" should not be divided. - # Use "%" as a separator, instead of a whitespace. - # "%" is unlikely to appear in defconfig context. - save_IFS=$IFS - IFS=% - # coalesce common lines together - for i in $output_lines - do - case "$i" in - [+A-Z]*:$line) - tmp="$tmp%$unmatched" - i=$(echo "$i" | \ - sed -e "s/^\([^:]*\)/\1$symbol/") - tmp="$tmp%$i" - match=1 - ;; - $line) - tmp="$tmp%$unmatched" - tmp="$tmp%+$symbol:$i" - match=1 - ;; - *) - tmp="$tmp%$i" - ;; - esac - done - - # Restore the default separator for the outer for loop. - IFS=$save_IFS - - if [ "$match" ]; then - output_lines="$tmp" - unmatched= - else - unmatched="$unmatched%$symbol:$line" - fi - done < defconfig - - output_lines="$output_lines%$unmatched" - done - - rm -f defconfig - touch defconfig - - save_IFS=$IFS - IFS=% - - for line in $output_lines - do - case "$line" in - "") - # do not output blank lines - ;; - *) - echo $line >> defconfig - ;; - esac - done - - IFS=$save_IFS -} - -# Some sanity checks before running "make /", -# where should be either "spl" or "tpl". -# Doing "make spl/menuconfig" etc. on a non-SPL board makes no sense. -# It should be allowed only when ".config" exists and "CONFIG_SPL" is enabled. -# -# Usage: -# check_enabled_sumbimage / -check_enabled_subimage () { - - case $2 in - spl|tpl) ;; - *) - echo >&2 "***" - echo >&2 "*** \"make $1\" is not supported." - echo >&2 "***" - exit 1 - ;; - esac - test -r "$KCONFIG_CONFIG" && get_enabled_subimages | grep -q $2 || { - config=CONFIG_$(echo $2 | tr '[a-z]' '[A-Z]') - - echo >&2 "***" - echo >&2 "*** Create \"$KCONFIG_CONFIG\" with \"$config\" enabled" - echo >&2 "*** before \"make $1\"." - echo >&2 "***" - exit 1 - } -} - -# Usage: -# do_others / -# The field "/" is typically empy, "spl/", "tpl/" for Normal, SPL, TPL, -# respectively. -# The field "" is a configuration target such as "config", -# "menuconfig", etc. do_others () { - target=${1##*/} - - if [ "$target" = "$1" ]; then - objdir= - else - objdir=${1%/*} - check_enabled_subimage $1 $objdir - - if [ -f "$objdir/$KCONFIG_CONFIG" ]; then - timestamp_before=$(stat --printf="%Y" \ - $objdir/$KCONFIG_CONFIG) - fi - fi - - run_make_config $target $objdir - - if [ "$timestamp_before" -a -f "$objdir/$KCONFIG_CONFIG" ]; then - timestamp_after=$(stat --printf="%Y" $objdir/$KCONFIG_CONFIG) - - if [ "$timestamp_after" -gt "$timestamp_before" ]; then - # $objdir/.config has been updated. - # touch .config to invoke "make silentoldconfig" - touch $KCONFIG_CONFIG - fi - fi + run_make_config $1 } progname=$(basename $0) @@ -340,10 +97,6 @@ case $target in do_board_defconfig ${target%_config}_defconfig;; silentoldconfig) do_silentoldconfig;; -defconfig) - do_defconfig;; -savedefconfig) - do_savedefconfig;; *) do_others $target;; esac -- cgit v1.3.1 From d648964fc2495f1184af5782a0b7fc670ba5826e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 22:26:21 +0900 Subject: kconfig: remove unneeded dependency on !SPL_BUILD Now CONFIG_SPL_BUILD is not defined in Kconfig, so "!depends on SPL_BUILD" and "if !SPL_BUILD" are redundant. Signed-off-by: Masahiro Yamada --- Kconfig | 12 ++---------- arch/arm/Kconfig | 7 +++---- arch/arm/cpu/arm1176/bcm2835/Kconfig | 6 +++--- arch/arm/cpu/armv7/exynos/Kconfig | 28 ++++++++++++++-------------- arch/arm/cpu/armv7/omap3/Kconfig | 10 +++++----- arch/arm/cpu/armv7/s5pc1xx/Kconfig | 4 ++-- arch/arm/cpu/armv7/uniphier/Kconfig | 1 - arch/arm/mach-tegra/Kconfig | 12 ++++++------ board/compulab/cm_t335/Kconfig | 6 +++--- board/gumstix/pepper/Kconfig | 6 +++--- board/isee/igep0033/Kconfig | 6 +++--- board/phytec/pcm051/Kconfig | 6 +++--- board/samsung/goni/Kconfig | 6 +++--- board/samsung/smdkc100/Kconfig | 6 +++--- board/silica/pengwyn/Kconfig | 6 +++--- board/ti/am335x/Kconfig | 10 +++++----- common/Kconfig | 1 - drivers/core/Kconfig | 16 ++++++---------- drivers/mtd/nand/Kconfig | 4 ---- dts/Kconfig | 1 - include/config_uncmd_spl.h | 4 ++++ scripts/Makefile.uncmd_spl | 2 ++ 22 files changed, 73 insertions(+), 87 deletions(-) (limited to 'include') diff --git a/Kconfig b/Kconfig index bb9b5c27fff..d0318cc8797 100644 --- a/Kconfig +++ b/Kconfig @@ -15,7 +15,6 @@ menu "General setup" config LOCALVERSION string "Local version - append to U-Boot release" - depends on !SPL_BUILD help Append an extra string to the end of your U-Boot version. This will show up on your boot log, for example. @@ -26,7 +25,6 @@ config LOCALVERSION config LOCALVERSION_AUTO bool "Automatically append version information to the version string" - depends on !SPL_BUILD default y help This will try to automatically determine if the current tree is a @@ -47,7 +45,6 @@ config LOCALVERSION_AUTO config CC_OPTIMIZE_FOR_SIZE bool "Optimize for size" - depends on !SPL_BUILD default y help Enabling this option will pass "-Os" instead of "-O2" to gcc @@ -95,23 +92,19 @@ config SUPPORT_TPL config SPL bool depends on SUPPORT_SPL - prompt "Enable SPL" if !SPL_BUILD - default y if SPL_BUILD + prompt "Enable SPL" help If you want to build SPL as well as the normal image, say Y. config TPL bool depends on SPL && SUPPORT_TPL - prompt "Enable TPL" if !SPL_BUILD - default y if TPL_BUILD - default n + prompt "Enable TPL" help If you want to build TPL as well as the normal image and SPL, say Y. config FIT bool "Support Flattened Image Tree" - depends on !SPL_BUILD help This option allows to boot the new uImage structrure, Flattened Image Tree. FIT is formally a FDT, which can include @@ -135,7 +128,6 @@ config FIT_SIGNATURE config SYS_EXTRA_OPTIONS string "Extra Options (DEPRECATED)" - depends on !SPL_BUILD help The old configuration infrastructure (= mkconfig + boards.cfg) provided the extra options field. If you have something like diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 820ba1ccaba..34083192b63 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -620,9 +620,8 @@ config TEGRA bool "NVIDIA Tegra" select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD - select CPU_ARM720T if SPL_BUILD - select CPU_V7 if !SPL_BUILD + select OF_CONTROL + select CPU_V7 config TARGET_VEXPRESS64_AEMV8A bool "Support vexpress_aemv8a" @@ -714,7 +713,7 @@ config ARCH_UNIPHIER select CPU_V7 select SUPPORT_SPL select SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice diff --git a/arch/arm/cpu/arm1176/bcm2835/Kconfig b/arch/arm/cpu/arm1176/bcm2835/Kconfig index 162f973f6cc..73cc72b4118 100644 --- a/arch/arm/cpu/arm1176/bcm2835/Kconfig +++ b/arch/arm/cpu/arm1176/bcm2835/Kconfig @@ -1,12 +1,12 @@ if TARGET_RPI || TARGET_RPI_2 config DM - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y endif diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index 2064efa7619..eb86a7fe7dc 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -6,7 +6,7 @@ choice config TARGET_SMDKV310 select SUPPORT_SPL bool "Exynos4210 SMDKV310 board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_TRATS bool "Exynos4210 Trats board" @@ -33,32 +33,32 @@ config TARGET_ARNDALE select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDK5250 bool "SMDK5250 board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SNOW bool "Snow board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDK5420 bool "SMDK5420 board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_PEACH_PI bool "Peach Pi board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_PEACH_PIT bool "Peach Pit board" select SUPPORT_SPL - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice @@ -66,25 +66,25 @@ config SYS_SOC default "exynos" config DM - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y config DM_SPI - default y if !SPL_BUILD + default y config DM_SPI_FLASH - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config SYS_MALLOC_F - default y if !SPL_BUILD + default y config SYS_MALLOC_F_LEN - default 0x400 if !SPL_BUILD + default 0x400 source "board/samsung/smdkv310/Kconfig" source "board/samsung/trats/Kconfig" diff --git a/arch/arm/cpu/armv7/omap3/Kconfig b/arch/arm/cpu/armv7/omap3/Kconfig index 46440981b37..4a0ac2c987a 100644 --- a/arch/arm/cpu/armv7/omap3/Kconfig +++ b/arch/arm/cpu/armv7/omap3/Kconfig @@ -94,19 +94,19 @@ config TARGET_TWISTER endchoice config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if DM && !SPL_BUILD + default y if DM config DM_SERIAL - default y if DM && !SPL_BUILD + default y if DM config SYS_MALLOC_F - default y if DM && !SPL_BUILD + default y if DM config SYS_MALLOC_F_LEN - default 0x400 if DM && !SPL_BUILD + default 0x400 if DM config SYS_SOC default "omap3" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig index 628813423fe..bc738138328 100644 --- a/arch/arm/cpu/armv7/s5pc1xx/Kconfig +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -5,11 +5,11 @@ choice config TARGET_S5P_GONI bool "S5P Goni board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL config TARGET_SMDKC100 bool "Support smdkc100 board" - select OF_CONTROL if !SPL_BUILD + select OF_CONTROL endchoice diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 9bbc011eeea..8335685e329 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -64,7 +64,6 @@ config CMD_PINMON config CMD_DDRPHY_DUMP bool "Enable dump command of DDR PHY parameters" - depends on !SPL_BUILD help The command "ddrphy" shows the resulting parameters of DDR PHY training; it is useful for the evaluation of DDR PHY training. diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8569167369c..8615248377e 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -27,22 +27,22 @@ config USE_PRIVATE_LIBGCC default y config DM - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y config DM_SPI - default y if !SPL_BUILD + default y config DM_SPI_FLASH - default y if !SPL_BUILD + default y config DM_I2C - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y source "arch/arm/mach-tegra/tegra20/Kconfig" source "arch/arm/mach-tegra/tegra30/Kconfig" diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig index aadbfbc84dc..3a8f304bd93 100644 --- a/board/compulab/cm_t335/Kconfig +++ b/board/compulab/cm_t335/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "cm_t335" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig index 3099a9eae15..750db8585d9 100644 --- a/board/gumstix/pepper/Kconfig +++ b/board/gumstix/pepper/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "pepper" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig index 2fe2ef17062..9a8421eb7a4 100644 --- a/board/isee/igep0033/Kconfig +++ b/board/isee/igep0033/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "am335x_igep0033" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig index 65094cf9fde..bb987156e6a 100644 --- a/board/phytec/pcm051/Kconfig +++ b/board/phytec/pcm051/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "pcm051" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig index 2c5d3fc3be5..006e864e0b0 100644 --- a/board/samsung/goni/Kconfig +++ b/board/samsung/goni/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "s5p_goni" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig index 996fe3cc450..ea87166d037 100644 --- a/board/samsung/smdkc100/Kconfig +++ b/board/samsung/smdkc100/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "smdkc100" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig index 6ecda8041c9..2e9a2b303f3 100644 --- a/board/silica/pengwyn/Kconfig +++ b/board/silica/pengwyn/Kconfig @@ -13,12 +13,12 @@ config SYS_CONFIG_NAME default "pengwyn" config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if !SPL_BUILD + default y config DM_SERIAL - default y if !SPL_BUILD + default y endif diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index a20e0c1ab95..722f9d57c4d 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -39,18 +39,18 @@ config NOR_BOOT NOR for environment. config DM - default y if !SPL_BUILD + default y config DM_GPIO - default y if DM && !SPL_BUILD + default y if DM config DM_SERIAL - default y if DM && !SPL_BUILD + default y if DM config SYS_MALLOC_F - default y if DM && !SPL_BUILD + default y if DM config SYS_MALLOC_F_LEN - default 0x400 if DM && !SPL_BUILD + default 0x400 if DM endif diff --git a/common/Kconfig b/common/Kconfig index 2ca002de270..f82bc88a12b 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -1,5 +1,4 @@ menu "Command line interface" - depends on !SPL_BUILD config HUSH_PARSER bool "Use hush shell" diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig index f0d611007af..75d182d27f7 100644 --- a/drivers/core/Kconfig +++ b/drivers/core/Kconfig @@ -1,6 +1,5 @@ config DM bool "Enable Driver Model" - depends on !SPL_BUILD help This config option enables Driver Model. This brings in the core support, including scanning of platform data on start-up. If @@ -22,31 +21,28 @@ config SPL_DM config DM_WARN bool "Enable warnings in driver model" + depends on DM + default y help The dm_warn() function can use up quite a bit of space for its strings. By default this is disabled for SPL builds to save space. This will cause dm_warn() to be compiled out - it will do nothing when called. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD config DM_DEVICE_REMOVE bool "Support device removal" + depends on DM + default y help We can save some code space by dropping support for removing a device. This is not normally required in SPL, so by default this option is disabled for SPL. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD config DM_STDIO bool "Support stdio registration" + depends on DM + default y help Normally serial drivers register with stdio so that they can be used as normal output devices. In SPL we don't normally use stdio, so we can omit this feature. - depends on DM - default y if !SPL_BUILD - default n if SPL_BUILD diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index ccd8211eb29..72825c3e2ed 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -6,8 +6,6 @@ config SYS_NAND_SELF_INIT This option, if enabled, provides more flexible and linux-like NAND initialization process. -if !SPL_BUILD - config NAND_DENALI bool "Support Denali NAND controller" select SYS_NAND_SELF_INIT @@ -34,8 +32,6 @@ config NAND_DENALI_SPARE_AREA_SKIP_BYTES of OOB area before last ECC sector data starts. This is potentially used to preserve the bad block marker in the OOB area. -endif - if SPL config SPL_NAND_DENALI diff --git a/dts/Kconfig b/dts/Kconfig index 5fe63f80258..ca5bd6fb466 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -9,7 +9,6 @@ config SUPPORT_OF_CONTROL bool menu "Device Tree Control" - depends on !SPL_BUILD depends on SUPPORT_OF_CONTROL config OF_CONTROL diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index 9f0fe444433..a9106f4f3b7 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -29,5 +29,9 @@ #undef CONFIG_DM_SPI #endif +#undef CONFIG_DM_WARN +#undef CONFIG_DM_DEVICE_REMOVE +#undef CONFIG_DM_STDIO + #endif /* CONFIG_SPL_BUILD */ #endif /* __CONFIG_UNCMD_SPL_H__ */ diff --git a/scripts/Makefile.uncmd_spl b/scripts/Makefile.uncmd_spl index 86c938e1f9d..343c3fc1993 100644 --- a/scripts/Makefile.uncmd_spl +++ b/scripts/Makefile.uncmd_spl @@ -13,4 +13,6 @@ CONFIG_DM_SPI= CONFIG_DM_SPI_FLASH= endif +CONFIG_DM_DEVICE_REMOVE= + endif -- cgit v1.3.1 From 41fbbbbc71161e0c0479d7c6c5598e760d70f624 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:05 +0900 Subject: ARM: remove jadecpu board support This is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Matthias Weisser Acked-by: Marek Vasut --- arch/arm/Kconfig | 5 - arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/mb86r0x/Makefile | 8 - arch/arm/cpu/arm926ejs/mb86r0x/clock.c | 27 -- arch/arm/cpu/arm926ejs/mb86r0x/reset.c | 24 -- arch/arm/cpu/arm926ejs/mb86r0x/timer.c | 115 ----- arch/arm/include/asm/arch-mb86r0x/hardware.h | 15 - arch/arm/include/asm/arch-mb86r0x/mb86r0x.h | 599 --------------------------- arch/arm/lib/asm-offsets.c | 46 -- board/syteco/jadecpu/Kconfig | 15 - board/syteco/jadecpu/MAINTAINERS | 6 - board/syteco/jadecpu/Makefile | 13 - board/syteco/jadecpu/jadecpu.c | 160 ------- board/syteco/jadecpu/lowlevel_init.S | 249 ----------- configs/jadecpu_defconfig | 2 - doc/README.scrapyard | 35 +- drivers/video/Makefile | 1 - drivers/video/mb86r0xgdc.c | 168 -------- include/configs/jadecpu.h | 273 ------------ include/serial.h | 2 +- 20 files changed, 19 insertions(+), 1745 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/clock.c delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/reset.c delete mode 100644 arch/arm/cpu/arm926ejs/mb86r0x/timer.c delete mode 100644 arch/arm/include/asm/arch-mb86r0x/hardware.h delete mode 100644 arch/arm/include/asm/arch-mb86r0x/mb86r0x.h delete mode 100644 board/syteco/jadecpu/Kconfig delete mode 100644 board/syteco/jadecpu/MAINTAINERS delete mode 100644 board/syteco/jadecpu/Makefile delete mode 100644 board/syteco/jadecpu/jadecpu.c delete mode 100644 board/syteco/jadecpu/lowlevel_init.S delete mode 100644 configs/jadecpu_defconfig delete mode 100644 drivers/video/mb86r0xgdc.c delete mode 100644 include/configs/jadecpu.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 34083192b63..089bef22e85 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -144,10 +144,6 @@ config TARGET_DEVKIT3250 bool "Support devkit3250" select CPU_ARM926EJS -config TARGET_JADECPU - bool "Support jadecpu" - select CPU_ARM926EJS - config TARGET_MX25PDK bool "Support mx25pdk" select CPU_ARM926EJS @@ -852,7 +848,6 @@ source "board/st-ericsson/snowball/Kconfig" source "board/st-ericsson/u8500/Kconfig" source "board/st/stv0991/Kconfig" source "board/sunxi/Kconfig" -source "board/syteco/jadecpu/Kconfig" source "board/syteco/zmx25/Kconfig" source "board/tbs/tbs2910/Kconfig" source "board/ti/am335x/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index f5944cc965e..ac23116955e 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -16,7 +16,6 @@ endif obj-$(CONFIG_ARMADA100) += armada100/ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ -obj-$(CONFIG_MB86R0x) += mb86r0x/ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile b/arch/arm/cpu/arm926ejs/mb86r0x/Makefile deleted file mode 100644 index 365892c413b..00000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = clock.o reset.o timer.o diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c b/arch/arm/cpu/arm926ejs/mb86r0x/clock.c deleted file mode 100644 index 1f6f66eba23..00000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/clock.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Get the peripheral bus frequency depending on pll pin settings - */ -ulong get_bus_freq(ulong dummy) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - uint32_t pllmode; - - pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; - - if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) - return 40000000; - - return 41164767; -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c b/arch/arm/cpu/arm926ejs/mb86r0x/reset.c deleted file mode 100644 index 7bd77ff202f..00000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/reset.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Reset the cpu by setting software reset request bit - */ -void reset_cpu(ulong ignored) -{ - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) - MB86R0x_CRG_BASE; - - writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); - while (1) - /* NOP */; - /* Never reached */ -} diff --git a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c b/arch/arm/cpu/arm926ejs/mb86r0x/timer.c deleted file mode 100644 index bb078196d00..00000000000 --- a/arch/arm/cpu/arm926ejs/mb86r0x/timer.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2010 - * Matthias Weisser, Graf-Syteco - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define TIMER_LOAD_VAL 0xffffffff -#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) - -DECLARE_GLOBAL_DATA_PTR; - -#define timestamp gd->arch.tbl -#define lastdec gd->arch.lastinc - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, TIMER_FREQ); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= TIMER_FREQ; - do_div(usec, 1000000); - - return usec; -} - -/* nothing really to do with interrupts, just starts up a counter. */ -int timer_init(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong ctrl = readl(&timer->control); - - writel(TIMER_LOAD_VAL, &timer->load); - - ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | - MB86R0x_TIMER_SIZE_32; - - writel(ctrl, &timer->control); - - /* capture current value time */ - lastdec = readl(&timer->value); - timestamp = 0; /* start "advancing" time stamp from 0 */ - - return 0; -} - -/* - * timer without interrupts - */ -unsigned long long get_ticks(void) -{ - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) - MB86R0x_TIMER_BASE; - ulong now = readl(&timer->value); - - if (now <= lastdec) { - /* normal mode (non roll) */ - /* move stamp forward with absolut diff ticks */ - timestamp += lastdec - now; - } else { - /* we have rollover of incrementer */ - timestamp += lastdec + TIMER_LOAD_VAL - now; - } - lastdec = now; - return timestamp; -} - -ulong get_timer_masked(void) -{ - return tick_to_time(get_ticks()); -} - -void __udelay(unsigned long usec) -{ - unsigned long long tmp; - ulong tmo; - - tmo = usec_to_tick(usec); - tmp = get_ticks(); /* get current timestamp */ - - while ((get_ticks() - tmp) < tmo) /* loop till event */ - /*NOP*/; -} - -ulong get_timer(ulong base) -{ - return get_timer_masked() - base; -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - ulong tbclk; - - tbclk = TIMER_FREQ; - return tbclk; -} diff --git a/arch/arm/include/asm/arch-mb86r0x/hardware.h b/arch/arm/include/asm/arch-mb86r0x/hardware.h deleted file mode 100644 index 42a52bc36c4..00000000000 --- a/arch/arm/include/asm/arch-mb86r0x/hardware.h +++ /dev/null @@ -1,15 +0,0 @@ -/* - * (C) Copyright 2007 - * - * Author : Carsten Schneider, mycable GmbH - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#include -#include - -#endif diff --git a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h b/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h deleted file mode 100644 index 7fec9715b1f..00000000000 --- a/arch/arm/include/asm/arch-mb86r0x/mb86r0x.h +++ /dev/null @@ -1,599 +0,0 @@ -/* - * (C) Copyright 2007 - * - * mb86r0x definitions - * - * Author : Carsten Schneider, mycable GmbH - * - * - * (C) Copyright 2010 - * Matthias Weisser - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef MB86R0X_H -#define MB86R0X_H - -#ifndef __ASSEMBLY__ - -/* GPIO registers */ -struct mb86r0x_gpio { - uint32_t gpdr0; - uint32_t gpdr1; - uint32_t gpdr2; - uint32_t res; - uint32_t gpddr0; - uint32_t gpddr1; - uint32_t gpddr2; -}; - -/* PWM registers */ -struct mb86r0x_pwm { - uint32_t bcr; - uint32_t tpr; - uint32_t pr; - uint32_t dr; - uint32_t cr; - uint32_t sr; - uint32_t ccr; - uint32_t ir; -}; - -/* The mb86r0x chip control (CCNT) register set. */ -struct mb86r0x_ccnt { - uint32_t ccid; - uint32_t csrst; - uint32_t pad0[2]; - uint32_t cist; - uint32_t cistm; - uint32_t cgpio_ist; - uint32_t cgpio_istm; - uint32_t cgpio_ip; - uint32_t cgpio_im; - uint32_t caxi_bw; - uint32_t caxi_ps; - uint32_t cmux_md; - uint32_t cex_pin_st; - uint32_t cmlb; - uint32_t pad1[1]; - uint32_t cusb; - uint32_t pad2[41]; - uint32_t cbsc; - uint32_t cdcrc; - uint32_t cmsr0; - uint32_t cmsr1; - uint32_t pad3[2]; -}; - -/* The mb86r0x clock reset generator */ -struct mb86r0x_crg { - uint32_t crpr; - uint32_t pad0; - uint32_t crwr; - uint32_t crsr; - uint32_t crda; - uint32_t crdb; - uint32_t crha; - uint32_t crpa; - uint32_t crpb; - uint32_t crhb; - uint32_t cram; -}; - -/* The mb86r0x timer */ -struct mb86r0x_timer { - uint32_t load; - uint32_t value; - uint32_t control; - uint32_t intclr; - uint32_t ris; - uint32_t mis; - uint32_t bgload; -}; - -/* mb86r0x gdc display controller */ -struct mb86r0x_gdc_dsp { - /* Display settings */ - uint32_t dcm0; - uint16_t pad00; - uint16_t htp; - uint16_t hdp; - uint16_t hdb; - uint16_t hsp; - uint8_t hsw; - uint8_t vsw; - uint16_t pad01; - uint16_t vtr; - uint16_t vsp; - uint16_t vdp; - uint16_t wx; - uint16_t wy; - uint16_t ww; - uint16_t wh; - - /* Layer 0 */ - uint32_t l0m; - uint32_t l0oa; - uint32_t l0da; - uint16_t l0dx; - uint16_t l0dy; - - /* Layer 1 */ - uint32_t l1m; - uint32_t cbda0; - uint32_t cbda1; - uint32_t pad02; - - /* Layer 2 */ - uint32_t l2m; - uint32_t l2oa0; - uint32_t l2da0; - uint32_t l2oa1; - uint32_t l2da1; - uint16_t l2dx; - uint16_t l2dy; - - /* Layer 3 */ - uint32_t l3m; - uint32_t l3oa0; - uint32_t l3da0; - uint32_t l3oa1; - uint32_t l3da1; - uint16_t l3dx; - uint16_t l3dy; - - /* Layer 4 */ - uint32_t l4m; - uint32_t l4oa0; - uint32_t l4da0; - uint32_t l4oa1; - uint32_t l4da1; - uint16_t l4dx; - uint16_t l4dy; - - /* Layer 5 */ - uint32_t l5m; - uint32_t l5oa0; - uint32_t l5da0; - uint32_t l5oa1; - uint32_t l5da1; - uint16_t l5dx; - uint16_t l5dy; - - /* Cursor */ - uint16_t cutc; - uint8_t cpm; - uint8_t csize; - uint32_t cuoa0; - uint16_t cux0; - uint16_t cuy0; - uint32_t cuoa1; - uint16_t cux1; - uint16_t cuy1; - - /* Layer blending */ - uint32_t l0bld; - uint32_t pad03; - uint32_t l0tc; - uint16_t l3tc; - uint16_t l2tc; - uint32_t pad04[15]; - - /* Display settings */ - uint32_t dcm1; - uint32_t dcm2; - uint32_t dcm3; - uint32_t pad05; - - /* Layer 0 extended */ - uint32_t l0em; - uint16_t l0wx; - uint16_t l0wy; - uint16_t l0ww; - uint16_t l0wh; - uint32_t pad06; - - /* Layer 1 extended */ - uint32_t l1em; - uint16_t l1wx; - uint16_t l1wy; - uint16_t l1ww; - uint16_t l1wh; - uint32_t pad07; - - /* Layer 2 extended */ - uint32_t l2em; - uint16_t l2wx; - uint16_t l2wy; - uint16_t l2ww; - uint16_t l2wh; - uint32_t pad08; - - /* Layer 3 extended */ - uint32_t l3em; - uint16_t l3wx; - uint16_t l3wy; - uint16_t l3ww; - uint16_t l3wh; - uint32_t pad09; - - /* Layer 4 extended */ - uint32_t l4em; - uint16_t l4wx; - uint16_t l4wy; - uint16_t l4ww; - uint16_t l4wh; - uint32_t pad10; - - /* Layer 5 extended */ - uint32_t l5em; - uint16_t l5wx; - uint16_t l5wy; - uint16_t l5ww; - uint16_t l5wh; - uint32_t pad11; - - /* Multi screen control */ - uint32_t msc; - uint32_t pad12[3]; - uint32_t dls; - uint32_t dbgc; - - /* Layer blending */ - uint32_t l1bld; - uint32_t l2bld; - uint32_t l3bld; - uint32_t l4bld; - uint32_t l5bld; - uint32_t pad13; - - /* Extended transparency control */ - uint32_t l0etc; - uint32_t l1etc; - uint32_t l2etc; - uint32_t l3etc; - uint32_t l4etc; - uint32_t l5etc; - uint32_t pad14[10]; - - /* YUV coefficients */ - uint32_t l1ycr0; - uint32_t l1ycr1; - uint32_t l1ycg0; - uint32_t l1ycg1; - uint32_t l1ycb0; - uint32_t l1ycb1; - uint32_t pad15[130]; - - /* Layer palletes */ - uint32_t l0pal[256]; - uint32_t l1pal[256]; - uint32_t pad16[256]; - uint32_t l2pal[256]; - uint32_t l3pal[256]; - uint32_t pad17[256]; - - /* PWM settings */ - uint32_t vpwmm; - uint16_t vpwms; - uint16_t vpwme; - uint32_t vpwmc; - uint32_t pad18[253]; -}; - -/* mb86r0x gdc capture controller */ -struct mb86r0x_gdc_cap { - uint32_t vcm; - uint32_t csc; - uint32_t vcs; - uint32_t pad01; - - uint32_t cbm; - uint32_t cboa; - uint32_t cbla; - uint16_t cihstr; - uint16_t civstr; - uint16_t cihend; - uint16_t civend; - uint32_t pad02; - - uint32_t chp; - uint32_t cvp; - uint32_t pad03[4]; - - uint32_t clpf; - uint32_t pad04; - uint32_t cmss; - uint32_t cmds; - uint32_t pad05[12]; - - uint32_t rgbhc; - uint32_t rgbhen; - uint32_t rgbven; - uint32_t pad06; - uint32_t rgbs; - uint32_t pad07[11]; - - uint32_t rgbcmy; - uint32_t rgbcmcb; - uint32_t rgbcmcr; - uint32_t rgbcmb; - uint32_t pad08[12 + 1984]; -}; - -/* mb86r0x gdc draw */ -struct mb86r0x_gdc_draw { - uint32_t ys; - uint32_t xs; - uint32_t dxdy; - uint32_t xus; - uint32_t dxudy; - uint32_t xls; - uint32_t dxldy; - uint32_t usn; - uint32_t lsn; - uint32_t pad01[7]; - uint32_t rs; - uint32_t drdx; - uint32_t drdy; - uint32_t gs; - uint32_t dgdx; - uint32_t dgdy; - uint32_t bs; - uint32_t dbdx; - uint32_t dbdy; - uint32_t pad02[7]; - uint32_t zs; - uint32_t dzdx; - uint32_t dzdy; - uint32_t pad03[13]; - uint32_t ss; - uint32_t dsdx; - uint32_t dsdy; - uint32_t ts; - uint32_t dtdx; - uint32_t dtdy; - uint32_t qs; - uint32_t dqdx; - uint32_t dqdy; - uint32_t pad04[23]; - uint32_t lpn; - uint32_t lxs; - uint32_t lxde; - uint32_t lys; - uint32_t lyde; - uint32_t lzs; - uint32_t lzde; - uint32_t pad05[13]; - uint32_t pxdc; - uint32_t pydc; - uint32_t pzdc; - uint32_t pad06[25]; - uint32_t rxs; - uint32_t rys; - uint32_t rsizex; - uint32_t rsizey; - uint32_t pad07[12]; - uint32_t saddr; - uint32_t sstride; - uint32_t srx; - uint32_t sry; - uint32_t daddr; - uint32_t dstride; - uint32_t drx; - uint32_t dry; - uint32_t brsizex; - uint32_t brsizey; - uint32_t tcolor; - uint32_t pad08[93]; - uint32_t blpo; - uint32_t pad09[7]; - uint32_t ctr; - uint32_t ifsr; - uint32_t ifcnt; - uint32_t sst; - uint32_t ds; - uint32_t pst; - uint32_t est; - uint32_t pad10; - uint32_t mdr0; - uint32_t mdr1; - uint32_t mdr2; - uint32_t mdr3; - uint32_t mdr4; - uint32_t pad14[2]; - uint32_t mdr7; - uint32_t fbr; - uint32_t xres; - uint32_t zbr; - uint32_t tbr; - uint32_t pfbr; - uint32_t cxmin; - uint32_t cxmax; - uint32_t cymin; - uint32_t cymax; - uint32_t txs; - uint32_t tis; - uint32_t toa; - uint32_t sho; - uint32_t abr; - uint32_t pad15[2]; - uint32_t fc; - uint32_t bc; - uint32_t alf; - uint32_t blp; - uint32_t pad16; - uint32_t tbc; - uint32_t pad11[42]; - uint32_t lx0dc; - uint32_t ly0dc; - uint32_t lx1dc; - uint32_t ly1dc; - uint32_t pad12[12]; - uint32_t x0dc; - uint32_t y0dc; - uint32_t x1dc; - uint32_t y1dc; - uint32_t x2dc; - uint32_t y2dc; - uint32_t pad13[666]; -}; - -/* mb86r0x gdc geometry engine */ -struct mb86r0x_gdc_geom { - uint32_t gctr; - uint32_t pad00[15]; - uint32_t gmdr0; - uint32_t gmdr1; - uint32_t gmdr2; - uint32_t pad01[237]; - uint32_t dfifog; - uint32_t pad02[767]; -}; - -/* mb86r0x gdc */ -struct mb86r0x_gdc { - uint32_t pad00[2]; - uint32_t lts; - uint32_t pad01; - uint32_t lsta; - uint32_t pad02[3]; - uint32_t ist; - uint32_t imask; - uint32_t pad03[6]; - uint32_t lsa; - uint32_t lco; - uint32_t lreq; - - uint32_t pad04[16*1024 - 19]; - struct mb86r0x_gdc_dsp dsp0; - struct mb86r0x_gdc_dsp dsp1; - uint32_t pad05[4*1024 - 2]; - uint32_t vccc; - uint32_t vcsr; - struct mb86r0x_gdc_cap cap0; - struct mb86r0x_gdc_cap cap1; - uint32_t pad06[4*1024]; - uint32_t texture_base[16*1024]; - struct mb86r0x_gdc_draw draw; - uint32_t pad07[7*1024]; - struct mb86r0x_gdc_geom geom; - uint32_t pad08[7*1024]; -}; - -/* mb86r0x ddr2c */ -struct mb86r0x_ddr2c { - uint16_t dric; - uint16_t dric1; - uint16_t dric2; - uint16_t drca; - uint16_t drcm; - uint16_t drcst1; - uint16_t drcst2; - uint16_t drcr; - uint16_t pad00[8]; - uint16_t drcf; - uint16_t pad01[7]; - uint16_t drasr; - uint16_t pad02[15]; - uint16_t drims; - uint16_t pad03[7]; - uint16_t dros; - uint16_t pad04; - uint16_t dribsodt1; - uint16_t dribsocd; - uint16_t dribsocd2; - uint16_t pad05[3]; - uint16_t droaba; - uint16_t pad06[9]; - uint16_t drobs; - uint16_t pad07[5]; - uint16_t drimr1; - uint16_t drimr2; - uint16_t drimr3; - uint16_t drimr4; - uint16_t droisr1; - uint16_t droisr2; -}; - -/* mb86r0x memc */ -struct mb86r0x_memc { - uint32_t mcfmode[8]; - uint32_t mcftim[8]; - uint32_t mcfarea[8]; -}; - -#endif /* __ASSEMBLY__ */ - -/* - * Physical Address Defines - */ -#define MB86R0x_DDR2_BASE 0xf3000000 -#define MB86R0x_GDC_BASE 0xf1fc0000 -#define MB86R0x_CCNT_BASE 0xfff42000 -#define MB86R0x_CAN0_BASE 0xfff54000 -#define MB86R0x_CAN1_BASE 0xfff55000 -#define MB86R0x_I2C0_BASE 0xfff56000 -#define MB86R0x_I2C1_BASE 0xfff57000 -#define MB86R0x_EHCI_BASE 0xfff80000 -#define MB86R0x_OHCI_BASE 0xfff81000 -#define MB86R0x_IRC1_BASE 0xfffb0000 -#define MB86R0x_MEMC_BASE 0xfffc0000 -#define MB86R0x_TIMER_BASE 0xfffe0000 -#define MB86R0x_UART0_BASE 0xfffe1000 -#define MB86R0x_UART1_BASE 0xfffe2000 -#define MB86R0x_IRCE_BASE 0xfffe4000 -#define MB86R0x_CRG_BASE 0xfffe7000 -#define MB86R0x_IRC0_BASE 0xfffe8000 -#define MB86R0x_GPIO_BASE 0xfffe9000 -#define MB86R0x_PWM0_BASE 0xfff41000 -#define MB86R0x_PWM1_BASE 0xfff41100 - -#define MB86R0x_CRSR_SWRSTREQ (1 << 1) - -/* - * Timer register bits - */ -#define MB86R0x_TIMER_ENABLE (1 << 7) -#define MB86R0x_TIMER_MODE_MSK (1 << 6) -#define MB86R0x_TIMER_MODE_FR (0 << 6) -#define MB86R0x_TIMER_MODE_PD (1 << 6) - -#define MB86R0x_TIMER_INT_EN (1 << 5) -#define MB86R0x_TIMER_PRS_MSK (3 << 2) -#define MB86R0x_TIMER_PRS_4S (1 << 2) -#define MB86R0x_TIMER_PRS_8S (1 << 3) -#define MB86R0x_TIMER_SIZE_32 (1 << 1) -#define MB86R0x_TIMER_ONE_SHT (1 << 0) - -/* - * Clock reset generator bits - */ -#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) -#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) -#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) -/* - * DDR2 controller bits - */ -#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) -#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) -#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) -#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN | \ - MB86R0x_DDR2_DRCI_DRCMD) -#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ - MB86R0x_DDR2_DRCI_CKEN) -#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN -#endif /* MB86R0X_H */ diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c index b0c26e5d689..e5bcaea1aee 100644 --- a/arch/arm/lib/asm-offsets.c +++ b/arch/arm/lib/asm-offsets.c @@ -15,9 +15,6 @@ #include #include -#if defined(CONFIG_MB86R0x) -#include -#endif #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ || defined(CONFIG_MX51) || defined(CONFIG_MX53) #include @@ -27,8 +24,6 @@ int main(void) { /* * TODO : Check if each entry in this file is really necessary. - * - struct mb86r0x_ddr2 - * - struct mb86r0x_memc * - struct esdramc_regs * - struct max_regs * - struct aips_regs @@ -40,47 +35,6 @@ int main(void) * code. Is it better to define the macros directly in headers? */ -#if defined(CONFIG_MB86R0x) - /* ddr2 controller */ - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); - - /* clock reset generator */ - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); - - /* chip control module */ - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); - - /* external bus interface */ - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); -#endif - #if defined(CONFIG_MX25) /* Clock Control Module */ DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); diff --git a/board/syteco/jadecpu/Kconfig b/board/syteco/jadecpu/Kconfig deleted file mode 100644 index 6e9392e21fc..00000000000 --- a/board/syteco/jadecpu/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_JADECPU - -config SYS_BOARD - default "jadecpu" - -config SYS_VENDOR - default "syteco" - -config SYS_SOC - default "mb86r0x" - -config SYS_CONFIG_NAME - default "jadecpu" - -endif diff --git a/board/syteco/jadecpu/MAINTAINERS b/board/syteco/jadecpu/MAINTAINERS deleted file mode 100644 index b53e7cad428..00000000000 --- a/board/syteco/jadecpu/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -JADECPU BOARD -M: Matthias Weisser -S: Maintained -F: board/syteco/jadecpu/ -F: include/configs/jadecpu.h -F: configs/jadecpu_defconfig diff --git a/board/syteco/jadecpu/Makefile b/board/syteco/jadecpu/Makefile deleted file mode 100644 index 74264361e5a..00000000000 --- a/board/syteco/jadecpu/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# (C) Copyright 2003-2008 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# (C) Copyright 2008 -# Stelian Pop -# Lead Tech Design -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += jadecpu.o -obj-y += lowlevel_init.o diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c deleted file mode 100644 index 6c60a41e3dc..00000000000 --- a/board/syteco/jadecpu/jadecpu.c +++ /dev/null @@ -1,160 +0,0 @@ -/* - * (c) 2010 Graf-Syteco, Matthias Weisser - * - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider , Alexander Bigga - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ -int board_init(void) -{ - struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) - MB86R0x_CCNT_BASE; - - /* We select mode 0 for group 2 and mode 1 for group 4 */ - writel(0x00000010, &ccnt->cmux_md); - - gd->flags = 0; - gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; - - icache_enable(); - dcache_enable(); - - return 0; -} - -static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, - unsigned long pwm_base) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; - const char *e; - - writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); - - e = getenv(pwm_opts); - if (e != NULL) { - const char *s; - uint32_t freq, init; - - freq = 0; - init = 0; - - s = strchr(e, 'f'); - if (s != NULL) - freq = simple_strtol(s + 2, NULL, 0); - - s = strchr(e, 'i'); - if (s != NULL) - init = simple_strtol(s + 2, NULL, 0); - - if (freq > 0) { - writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, - &pwm->bcr); - writel(1002, &pwm->tpr); - writel(1, &pwm->pr); - writel(init * 10 + 1, &pwm->dr); - writel(1, &pwm->cr); - writel(1, &pwm->sr); - } - } -} - -int board_late_init(void) -{ - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) - MB86R0x_GPIO_BASE; - uint32_t in_word; - -#ifdef CONFIG_VIDEO_MB86R0xGDC - /* Check if we have valid display settings and turn on power if so */ - /* Display 0 */ - if (getenv("gs_dsp_0_param") || getenv("videomode")) - setup_display_power((1 << 3), "gs_dsp_0_pwm", - MB86R0x_PWM0_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); - - /* Display 1 */ - if (getenv("gs_dsp_1_param") || getenv("videomode1")) - setup_display_power((1 << 4), "gs_dsp_1_pwm", - MB86R0x_PWM1_BASE); - - /* The corresponding GPIO is always an output */ - writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); -#endif /* CONFIG_VIDEO_MB86R0xGDC */ - - /* 5V enable */ - writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); - writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); - - /* We have special boot options if told by GPIOs */ - in_word = readl(&gpio->gpdr1); - - if ((in_word & 0xC0) == 0xC0) { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - setenv("preboot", "run gs_slow_boot"); - } else if ((in_word & 0xC0) != 0) { - setenv("stdout", "vga"); - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("stdin", "serial"); - setenv("stdout", "serial"); - setenv("stderr", "serial"); - if (getenv("gs_devel")) { - setenv("preboot", "run gs_slow_boot"); - } else { - setenv("preboot", "run gs_fast_boot"); - } - } - - return 0; -} - -int misc_init_r(void) -{ - return 0; -} - -/* - * DRAM configuration - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, - PHYS_SDRAM_SIZE); - - return 0; -} - -void dram_init_banksize(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = gd->ram_size; -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/syteco/jadecpu/lowlevel_init.S b/board/syteco/jadecpu/lowlevel_init.S deleted file mode 100644 index 9568cec9a86..00000000000 --- a/board/syteco/jadecpu/lowlevel_init.S +++ /dev/null @@ -1,249 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2007, mycable GmbH - * Carsten Schneider , Alexander Bigga - * - * (C) Copyright 2003, ARM Ltd. - * Philippe Robin, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -/* Set up the platform, once the cpu has been initialized */ -.globl lowlevel_init -lowlevel_init: -/* - * Initialize Clock Reset Generator (CRG) - */ - - ldr r0, =MB86R0x_CRG_BASE - - /* Not change the initial value that is set by external pin.*/ -WAIT_PLL: - ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ - tst r2, #MB86R0x_CRG_CRPR_PLLRDY - beq WAIT_PLL - - /* Set clock gate control */ - ldr r1, =CONFIG_SYS_CRG_CRHA_INIT - str r1, [r0, #CRG_CRHA] - ldr r1, =CONFIG_SYS_CRG_CRPA_INIT - str r1, [r0, #CRG_CRPA] - ldr r1, =CONFIG_SYS_CRG_CRPB_INIT - str r1, [r0, #CRG_CRPB] - ldr r1, =CONFIG_SYS_CRG_CRHB_INIT - str r1, [r0, #CRG_CRHB] - ldr r1, =CONFIG_SYS_CRG_CRAM_INIT - str r1, [r0, #CRG_CRAM] - -/* - * Initialize External Bus Interface - */ - ldr r0, =MB86R0x_MEMC_BASE - - ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT - str r1, [r0, #MEMC_MCFMODE0] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT - str r1, [r0, #MEMC_MCFMODE2] - ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT - str r1, [r0, #MEMC_MCFMODE4] - - ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT - str r1, [r0, #MEMC_MCFTIM0] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT - str r1, [r0, #MEMC_MCFTIM2] - ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT - str r1, [r0, #MEMC_MCFTIM4] - - ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT - str r1, [r0, #MEMC_MCFAREA0] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT - str r1, [r0, #MEMC_MCFAREA2] - ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT - str r1, [r0, #MEMC_MCFAREA4] - -/* - * Initialize DDR2 Controller - */ - - /* Wait for PLL LOCK up time or more */ - wait_timer 20 - - /* - * (2) Initialize DDRIF - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT - strh r1, [r0, #DDR2_DRIMS] - - /* - * (3) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (4) IRESET/IUSRRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 - str r1, [r0, #CCNT_CDCRC] - - /* - * (5) Wait for 20MCKPs(120nsec) or more - */ - wait_timer 20 - - /* - * (6) IDLLRST release - */ - ldr r0, =MB86R0x_CCNT_BASE - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 - str r1, [r0, #CCNT_CDCRC] - - /* - * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) - */ - wait_timer 33536 - - /* - * (9) MCKE ON - */ - ldr r0, =MB86R0x_DDR2_BASE - ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT - strh r1, [r0, #DDR2_DRCA] - ldr r1, =MB86R0x_DDR2_DRCI_INIT - strh r1, [r0, #DDR2_DRIC] - - /* - * (10) Initialize SDRAM - */ - - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 67 /* 400ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 18 /* 105ns wait */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - wait_timer 200 /* MRS to OCD: 200clock */ - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 - strh r1, [r0, #DDR2_DRIC1] - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 - strh r1, [r0, #DDR2_DRIC2] - ldr r1, =MB86R0x_DDR2_DRCI_CMD - strh r1, [r0, #DDR2_DRIC] - - ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT - strh r1, [r0, #DDR2_DRCM] - - ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT - strh r1, [r0, #DDR2_DRCST1] - - ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT - strh r1, [r0, #DDR2_DRCST2] - - ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT - strh r1, [r0, #DDR2_DRCR] - - ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT - strh r1, [r0, #DDR2_DRCF] - - ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT - strh r1, [r0, #DDR2_DRASR] - - /* - * (11) ODT setting - */ - ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT - strh r1, [r0, #DDR2_DROBS] - ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT - strh r1, [r0, #DDR2_DROABA] - ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT - strh r1, [r0, #DDR2_DRIBSODT1] - - /* - * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode - */ - ldr r1, =CONFIG_SYS_DDR2_DROS_INIT - strh r1, [r0, #DDR2_DROS] - ldr r1, =MB86R0x_DDR2_DRCI_NORMAL - strh r1, [r0, #DDR2_DRIC] - - mov pc, lr diff --git a/configs/jadecpu_defconfig b/configs/jadecpu_defconfig deleted file mode 100644 index 4348e0e5df2..00000000000 --- a/configs/jadecpu_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_JADECPU=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 952ab871c29..0fc6ac7fda2 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,23 +12,24 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -icecube_5200 powerpc mpc5xxx - - Wolfgang Denk -Lite5200 powerpc mpc5xxx - - -cpci5200 powerpc mpc5xxx - - Reinhard Arlt -mecp5200 powerpc mpc5xxx - - Reinhard Arlt -pf5200 powerpc mpc5xxx - - Reinhard Arlt -PM520 powerpc mpc5xxx - - Josef Wagner -Total5200 powerpc mpc5xxx - - -CATcenter powerpc ppc4xx - - -PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson -P2020DS powerpc mpc85xx - - -P2020COME powerpc mpc85xx - - Ira W. Snyder -P2020RDB powerpc mpc85xx - - Poonam Aggrwal -P2010RDB powerpc mpc85xx - - -P1020RDB powerpc mpc85xx - - -P1011RDB powerpc mpc85xx - - -MPC8360EMDS powerpc mpc83xx - - Dave Liu -MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov +jadecpu arm arm926ejs - - Matthias Weisser +icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk +Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23 +cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt +mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt +pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt +PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner +Total5200 powerpc mpc5xxx ad734f7d 2015-01-23 +CATcenter powerpc ppc4xx 5344cc1a 2015-01-23 +PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson +P2020DS powerpc mpc85xx 168dcc6c 2015-01-23 +P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder +P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal +P2010RDB powerpc mpc85xx 743d4815 2015-01-23 +P1020RDB powerpc mpc85xx 743d4815 2015-01-23 +P1011RDB powerpc mpc85xx 743d4815 2015-01-23 +MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu +MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16 diff --git a/drivers/video/Makefile b/drivers/video/Makefile index af2d47bd75f..22a316b5366 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -32,7 +32,6 @@ obj-$(CONFIG_VIDEO_IMX25LCDC) += imx25lcdc.o videomodes.o obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o -obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o diff --git a/drivers/video/mb86r0xgdc.c b/drivers/video/mb86r0xgdc.c deleted file mode 100644 index bb7a7497cc5..00000000000 --- a/drivers/video/mb86r0xgdc.c +++ /dev/null @@ -1,168 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic - * controller. - */ - -#include - -#include -#include -#include -#include -#include "videomodes.h" - -/* - * 4MB (at the end of system RAM) - */ -#define VIDEO_MEM_SIZE 0x400000 - -#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ - -/* - * Graphic Device - */ -static GraphicDevice mb86r0x; - -static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, - u32 *videomem) -{ - struct ctfb_res_modes var_mode; - u32 dcm1, dcm2, dcm3; - u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; - u8 hsw, vsw; - u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; - u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; - unsigned long div; - int bpp; - - bpp = video_get_params(&var_mode, modestr); - - if (bpp == 0) { - var_mode.xres = 640; - var_mode.yres = 480; - var_mode.pixclock = 39721; /* 25MHz */ - var_mode.left_margin = 48; - var_mode.right_margin = 16; - var_mode.upper_margin = 33; - var_mode.lower_margin = 10; - var_mode.hsync_len = 96; - var_mode.vsync_len = 2; - var_mode.sync = 0; - var_mode.vmode = 0; - bpp = 15; - } - - /* Fill memory with white */ - memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); - - mb86r0x.winSizeX = var_mode.xres; - mb86r0x.winSizeY = var_mode.yres; - - /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ - div = 660000 / (1000000000L / var_mode.pixclock); - if (div > 64) - div = 64; - if (0 == div) - div = 1; - - dcm1 = (div - 1) << 8; - dcm2 = 0x00000000; - if (var_mode.sync & FB_SYNC_CLK_INV) - dcm3 = 0x00000100; - else - dcm3 = 0x00000000; - - htp = var_mode.left_margin + var_mode.xres + - var_mode.hsync_len + var_mode.right_margin; - hdp = var_mode.xres; - hdb = var_mode.xres; - hsp = var_mode.xres + var_mode.right_margin; - hsw = var_mode.hsync_len; - - vsw = var_mode.vsync_len; - vtr = var_mode.upper_margin + var_mode.yres + - var_mode.vsync_len + var_mode.lower_margin; - vsp = var_mode.yres + var_mode.lower_margin; - vdp = var_mode.yres; - - l2m = ((var_mode.yres - 1) << (0)) | - (((var_mode.xres * 2) / 64) << (16)) | - ((1) << (31)); - - l2em = (1 << 0) | (1 << 1); - - l2oa0 = mb86r0x.frameAdrs; - l2da0 = mb86r0x.frameAdrs; - l2oa1 = mb86r0x.frameAdrs; - l2da1 = mb86r0x.frameAdrs; - l2dx = 0; - l2dy = 0; - l2wx = 0; - l2wy = 0; - l2ww = var_mode.xres; - l2wh = var_mode.yres - 1; - - writel(dcm1, &dsp->dcm1); - writel(dcm2, &dsp->dcm2); - writel(dcm3, &dsp->dcm3); - - writew(htp, &dsp->htp); - writew(hdp, &dsp->hdp); - writew(hdb, &dsp->hdb); - writew(hsp, &dsp->hsp); - writeb(hsw, &dsp->hsw); - - writeb(vsw, &dsp->vsw); - writew(vtr, &dsp->vtr); - writew(vsp, &dsp->vsp); - writew(vdp, &dsp->vdp); - - writel(l2m, &dsp->l2m); - writel(l2em, &dsp->l2em); - writel(l2oa0, &dsp->l2oa0); - writel(l2da0, &dsp->l2da0); - writel(l2oa1, &dsp->l2oa1); - writel(l2da1, &dsp->l2da1); - writew(l2dx, &dsp->l2dx); - writew(l2dy, &dsp->l2dy); - writew(l2wx, &dsp->l2wx); - writew(l2wy, &dsp->l2wy); - writew(l2ww, &dsp->l2ww); - writew(l2wh, &dsp->l2wh); - - writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); -} - -void *video_hw_init(void) -{ - struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; - GraphicDevice *pGD = &mb86r0x; - char *s; - u32 *vid; - - memset(pGD, 0, sizeof(GraphicDevice)); - - pGD->gdfIndex = GDF_15BIT_555RGB; - pGD->gdfBytesPP = 2; - pGD->memSize = VIDEO_MEM_SIZE; - pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; - - vid = (u32 *)pGD->frameAdrs; - - s = getenv("videomode"); - if (s != NULL) - dsp_init(&gdc->dsp0, s, vid); - - s = getenv("videomode1"); - if (s != NULL) - dsp_init(&gdc->dsp1, s, vid); - - return pGD; -} diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h deleted file mode 100644 index 8175621338f..00000000000 --- a/include/configs/jadecpu.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2010 - * Matthias Weisser - * - * Configuation settings for the jadecpu board - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MB86R0x -#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) -#define CONFIG_SYS_TEXT_BASE 0x10000000 - - -#define CONFIG_USE_ARCH_MEMCPY -#define CONFIG_USE_ARCH_MEMSET - -#define MACH_TYPE_JADECPU 2636 - -#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ - "bootelf 0x40000000\0" \ - "" - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_BOARD_LATE_INIT - -/* - * Compressions - */ -#define CONFIG_LZO - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ -#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ -#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ -#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ - -#define CONFIG_CONS_INDEX 4 - -/* - * Ethernet - */ -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x02000000 -#define CONFIG_SMC911X_16_BIT - -/* - * Video - */ -#define CONFIG_VIDEO -#define CONFIG_VIDEO_MB86R0xGDC -#define CONFIG_SYS_WHITE_ON_BLACK -#define CONFIG_CFB_CONSOLE -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) -#define VIDEO_FB_16BPP_WORD_SWAP -#define VIDEO_KBD_INIT_FCT 0 -#define VIDEO_TSTC_FCT serial_stub_tstc -#define VIDEO_GETC_FCT serial_stub_getc - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 -#define CONFIG_BOOTP_BOOTPATH 1 -#define CONFIG_BOOTP_GATEWAY 1 -#define CONFIG_BOOTP_HOSTNAME 1 - -/* - * Command line configuration. - */ -#include -#undef CONFIG_CMD_BDI -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_SOURCE -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG - -#define CONFIG_CMD_BMP -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FAT -#define CONFIG_CMD_PING -#define CONFIG_CMD_USB -#define CONFIG_CMD_CACHE - -#define CONFIG_SYS_HUSH_PARSER - -/* USB */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION - -/* SDRAM */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* - * CFI FLASH driver setup - */ -#define CONFIG_SYS_FLASH_CFI 1 -#define CONFIG_FLASH_CFI_DRIVER 1 -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ - -#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PROMPT "jade> " -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LONGHELP 1 -#define CONFIG_CMDLINE_EDITING 1 - -#define CONFIG_PREBOOT "" - -#define CONFIG_BOOTDELAY 5 -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay -#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" -#define CONFIG_AUTOBOOT_STOP_STR "stopgs" - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 << 20) -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20) - -/* - * Clock reset generator init - */ -#define CONFIG_SYS_CRG_CRHA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPA_INIT 0xffff -#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe -#define CONFIG_SYS_CRG_CRHB_INIT 0xffff -#define CONFIG_SYS_CRG_CRAM_INIT 0xffef - -/* - * Memory controller settings - */ -#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ -#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ -#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 -#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 -#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 -#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ -#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ - -/* - * DDR2 controller init settings - */ -#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 -#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 -#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 -#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f -#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 -#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ -#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 -#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 -#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 -#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 -#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 -#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 -#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 -#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F -#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 - -/* - * DRAM init sequence - */ - -/* PALL Command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 - -/* EMR(2) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 -#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 - -/* EMR(3) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 -#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 - -/* PALL command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 -#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 - -/* REF command 1 */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f -#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 - -/* MRS command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 -#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 - -/* EMR(1) command */ -#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 -#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 - -#endif /* __CONFIG_H */ diff --git a/include/serial.h b/include/serial.h index 66ed12c9c21..3d2e5697f48 100644 --- a/include/serial.h +++ b/include/serial.h @@ -29,7 +29,7 @@ extern struct serial_device *default_serial_console(void); #if defined(CONFIG_405GP) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_405EX) || defined(CONFIG_440) || \ - defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ + defined(CONFIG_MPC5xxx) || \ defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ -- cgit v1.3.1 From 346cfba4f013c34e1dc16948d1ed89dc8c44c478 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:06 +0900 Subject: ARM: remove dkb board support This is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Lei Wen Acked-by: Marek Vasut --- arch/arm/Kconfig | 5 - arch/arm/cpu/arm926ejs/Makefile | 1 - arch/arm/cpu/arm926ejs/pantheon/Makefile | 9 -- arch/arm/cpu/arm926ejs/pantheon/cpu.c | 85 ----------- arch/arm/cpu/arm926ejs/pantheon/dram.c | 117 --------------- arch/arm/cpu/arm926ejs/pantheon/timer.c | 201 -------------------------- arch/arm/include/asm/arch-pantheon/config.h | 53 ------- arch/arm/include/asm/arch-pantheon/cpu.h | 77 ---------- arch/arm/include/asm/arch-pantheon/gpio.h | 0 arch/arm/include/asm/arch-pantheon/mfp.h | 39 ----- arch/arm/include/asm/arch-pantheon/pantheon.h | 38 ----- board/Marvell/dkb/Kconfig | 15 -- board/Marvell/dkb/MAINTAINERS | 6 - board/Marvell/dkb/Makefile | 9 -- board/Marvell/dkb/dkb.c | 85 ----------- configs/dkb_defconfig | 2 - doc/README.scrapyard | 1 + include/configs/dkb.h | 51 ------- 18 files changed, 1 insertion(+), 793 deletions(-) delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/Makefile delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/cpu.c delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/dram.c delete mode 100644 arch/arm/cpu/arm926ejs/pantheon/timer.c delete mode 100644 arch/arm/include/asm/arch-pantheon/config.h delete mode 100644 arch/arm/include/asm/arch-pantheon/cpu.h delete mode 100644 arch/arm/include/asm/arch-pantheon/gpio.h delete mode 100644 arch/arm/include/asm/arch-pantheon/mfp.h delete mode 100644 arch/arm/include/asm/arch-pantheon/pantheon.h delete mode 100644 board/Marvell/dkb/Kconfig delete mode 100644 board/Marvell/dkb/MAINTAINERS delete mode 100644 board/Marvell/dkb/Makefile delete mode 100644 board/Marvell/dkb/dkb.c delete mode 100644 configs/dkb_defconfig delete mode 100644 include/configs/dkb.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 089bef22e85..0bed390f0de 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -223,10 +223,6 @@ config ORION5X bool "Marvell Orion" select CPU_ARM926EJS -config TARGET_DKB - bool "Support dkb" - select CPU_ARM926EJS - config TARGET_SPEAR300 bool "Support spear300" select CPU_ARM926EJS @@ -757,7 +753,6 @@ source "board/BuR/tseries/Kconfig" source "board/CarMediaLab/flea3/Kconfig" source "board/Marvell/aspenite/Kconfig" source "board/Marvell/db-mv784mp-gp/Kconfig" -source "board/Marvell/dkb/Kconfig" source "board/Marvell/gplugd/Kconfig" source "board/altera/socfpga/Kconfig" source "board/armadeus/apf27/Kconfig" diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile index ac23116955e..63fa159db6a 100644 --- a/arch/arm/cpu/arm926ejs/Makefile +++ b/arch/arm/cpu/arm926ejs/Makefile @@ -19,5 +19,4 @@ obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/ obj-$(CONFIG_MX25) += mx25/ obj-$(CONFIG_MX27) += mx27/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/ -obj-$(CONFIG_PANTHEON) += pantheon/ obj-$(if $(filter spear,$(SOC)),y) += spear/ diff --git a/arch/arm/cpu/arm926ejs/pantheon/Makefile b/arch/arm/cpu/arm926ejs/pantheon/Makefile deleted file mode 100644 index 988341f8fb6..00000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Marvell Semiconductor -# Written-by: Lei Wen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = cpu.o timer.o dram.o diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c deleted file mode 100644 index 4e2a177c0d1..00000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1)) -#define SET_MRVL_ID (1<<8) -#define L2C_RAM_SEL (1<<4) - -int arch_cpu_init(void) -{ - u32 val; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - struct panthapb_registers *apbclkres = - (struct panthapb_registers*) PANTHEON_APBC_BASE; - - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers*) PANTHEON_MPMU_BASE; - - struct panthapmu_registers *apmu = - (struct panthapmu_registers *) PANTHEON_APMU_BASE; - - /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */ - val = readl(&cpuregs->cpu_conf); - val = val | SET_MRVL_ID; - writel(val, &cpuregs->cpu_conf); - - /* Turn on clock gating (PMUM_CCGR) */ - writel(0xFFFFFFFF, &mpmu->ccgr); - - /* Turn on clock gating (PMUM_ACGR) */ - writel(0xFFFFFFFF, &mpmu->acgr); - - /* Turn on uart2 clock */ - writel(UARTCLK14745KHZ, &apbclkres->uart0); - - /* Enable GPIO clock */ - writel(APBC_APBCLK, &apbclkres->gpio); - -#ifdef CONFIG_I2C_MV - /* Enable I2C clock */ - writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); - writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi); -#endif - -#ifdef CONFIG_MV_SDHCI - /* Enable mmc clock */ - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd1); - writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST, - &apmu->sd3); -#endif - - icache_enable(); - - return 0; -} - -#if defined(CONFIG_DISPLAY_CPUINFO) -int print_cpuinfo(void) -{ - u32 id; - struct panthcpu_registers *cpuregs = - (struct panthcpu_registers*) PANTHEON_CPU_BASE; - - id = readl(&cpuregs->chip_id); - printf("SoC: PANTHEON 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10)); - return 0; -} -#endif - -#ifdef CONFIG_I2C_MV -void i2c_clk_enable(void) -{ -} -#endif diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c deleted file mode 100644 index f77e3d0ab5c..00000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/dram.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen , - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Pantheon DRAM controller supports upto 8 banks - * for chip select 0 and 1 - */ - -/* - * DDR Memory Control Registers - * Refer Datasheet 4.4 - */ -struct panthddr_map_registers { - u32 cs; /* Memory Address Map Register -CS */ - u32 pad[3]; -}; - -struct panthddr_registers { - u8 pad[0x100 - 0x000]; - struct panthddr_map_registers mmap[2]; -}; - -/* - * panth_sdram_base - reads SDRAM Base Address Register - */ -u32 panth_sdram_base(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000; - return result; -} - -/* - * panth_sdram_size - reads SDRAM size - */ -u32 panth_sdram_size(int chip_sel) -{ - struct panthddr_registers *ddr_regs = - (struct panthddr_registers *)PANTHEON_DRAM_BASE; - u32 result = 0; - u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs); - - if (!CS_valid) - return 0; - - result = readl(&ddr_regs->mmap[chip_sel].cs); - result = (result >> 16) & 0xF; - if (result < 0x7) { - printf("Unknown DRAM Size\n"); - return -1; - } else { - return ((0x8 << (result - 0x7)) * 1024 * 1024); - } -} - -#ifndef CONFIG_SYS_BOARD_DRAM_INIT -int dram_init(void) -{ - int i; - - gd->ram_size = 0; - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - gd->bd->bi_dram[i].start = panth_sdram_base(i); - gd->bd->bi_dram[i].size = panth_sdram_size(i); - /* - * It is assumed that all memory banks are consecutive - * and without gaps. - * If the gap is found, ram_size will be reported for - * consecutive memory only - */ - if (gd->bd->bi_dram[i].start != gd->ram_size) - break; - - gd->ram_size += gd->bd->bi_dram[i].size; - - } - - for (; i < CONFIG_NR_DRAM_BANKS; i++) { - /* - * If above loop terminated prematurely, we need to set - * remaining banks' start address & size as 0. Otherwise other - * u-boot functions and Linux kernel gets wrong values which - * could result in crash - */ - gd->bd->bi_dram[i].start = 0; - gd->bd->bi_dram[i].size = 0; - } - return 0; -} - -/* - * If this function is not defined here, - * board.c alters dram bank zero configuration defined above. - */ -void dram_init_banksize(void) -{ - dram_init(); -} -#endif /* CONFIG_SYS_BOARD_DRAM_INIT */ diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c deleted file mode 100644 index 6382d3b0cfb..00000000000 --- a/arch/arm/cpu/arm926ejs/pantheon/timer.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -/* - * Timer registers - * Refer 6.2.9 in Datasheet - */ -struct panthtmr_registers { - u32 clk_ctrl; /* Timer clk control reg */ - u32 match[9]; /* Timer match registers */ - u32 count[3]; /* Timer count registers */ - u32 status[3]; - u32 ie[3]; - u32 preload[3]; /* Timer preload value */ - u32 preload_ctrl[3]; - u32 wdt_match_en; - u32 wdt_match_r; - u32 wdt_val; - u32 wdt_sts; - u32 icr[3]; - u32 wdt_icr; - u32 cer; /* Timer count enable reg */ - u32 cmr; - u32 ilr[3]; - u32 wcr; - u32 wfar; - u32 wsar; - u32 cvwr[3]; -}; - -#define TIMER 0 /* Use TIMER 0 */ -/* Each timer has 3 match registers */ -#define MATCH_CMP(x) ((3 * TIMER) + x) -#define TIMER_LOAD_VAL 0xffffffff -#define COUNT_RD_REQ 0x1 - -DECLARE_GLOBAL_DATA_PTR; -/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */ - -/* - * For preventing risk of instability in reading counter value, - * first set read request to register cvwr and then read same - * register after it captures counter value. - */ -ulong read_timer(void) -{ - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - volatile int loop=100; - ulong val; - - writel(COUNT_RD_REQ, &panthtimers->cvwr); - while (loop--) - val = readl(&panthtimers->cvwr); - - /* - * This stop gcc complain and prevent loop mistake init to 0 - */ - val = readl(&panthtimers->cvwr); - - return val; -} - -ulong get_timer_masked(void) -{ - ulong now = read_timer(); - - if (now >= gd->arch.tbl) { - /* normal mode */ - gd->arch.tbu += now - gd->arch.tbl; - } else { - /* we have an overflow ... */ - gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl; - } - gd->arch.tbl = now; - - return gd->arch.tbu; -} - -ulong get_timer(ulong base) -{ - return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - - base); -} - -void __udelay(unsigned long usec) -{ - ulong delayticks; - ulong endtime; - - delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000)); - endtime = get_timer_masked() + delayticks; - - while (get_timer_masked() < endtime) - ; -} - -/* - * init the Timer - */ -int timer_init(void) -{ - struct panthapb_registers *apb1clkres = - (struct panthapb_registers *) PANTHEON_APBC_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_TIMER_BASE; - - /* Enable Timer clock at 3.25 MHZ */ - writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers); - - /* load value into timer */ - writel(0x0, &panthtimers->clk_ctrl); - /* Use Timer 0 Match Resiger 0 */ - writel(TIMER_LOAD_VAL, &panthtimers->match[MATCH_CMP(0)]); - /* Preload value is 0 */ - writel(0x0, &panthtimers->preload[TIMER]); - /* Enable match comparator 0 for Timer 0 */ - writel(0x1, &panthtimers->preload_ctrl[TIMER]); - - /* Enable timer 0 */ - writel(0x1, &panthtimers->cer); - /* init the gd->arch.tbu and gd->arch.tbl value */ - gd->arch.tbl = read_timer(); - gd->arch.tbu = 0; - - return 0; -} - -#define MPMU_APRR_WDTR (1<<4) -#define TMR_WFAR 0xbaba /* WDT Register First key */ -#define TMP_WSAR 0xeb10 /* WDT Register Second key */ - -/* - * This function uses internal Watchdog Timer - * based reset mechanism. - * Steps to write watchdog registers (protected access) - * 1. Write key value to TMR_WFAR reg. - * 2. Write key value to TMP_WSAR reg. - * 3. Perform write operation. - */ -void reset_cpu (unsigned long ignored) -{ - struct panthmpmu_registers *mpmu = - (struct panthmpmu_registers *) PANTHEON_MPMU_BASE; - struct panthtmr_registers *panthtimers = - (struct panthtmr_registers *) PANTHEON_WD_TIMER_BASE; - u32 val; - - /* negate hardware reset to the WDT after system reset */ - val = readl(&mpmu->aprr); - val = val | MPMU_APRR_WDTR; - writel(val, &mpmu->aprr); - - /* reset/enable WDT clock */ - writel(APBC_APBCLK, &mpmu->wdtpcr); - - /* clear previous WDT status */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0, &panthtimers->wdt_sts); - - /* set match counter */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0xf, &panthtimers->wdt_match_r); - - /* enable WDT reset */ - writel(TMR_WFAR, &panthtimers->wfar); - writel(TMP_WSAR, &panthtimers->wsar); - writel(0x3, &panthtimers->wdt_match_en); - - /*enable functional WDT clock */ - writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr); -} - -/* - * This function is derived from PowerPC code (read timebase as long long). - * On ARM it just returns the timer value. - */ -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -/* - * This function is derived from PowerPC code (timebase clock frequency). - * On ARM it returns the number of timer ticks per second. - */ -ulong get_tbclk (void) -{ - return (ulong)CONFIG_SYS_HZ; -} diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h deleted file mode 100644 index 1eed7b1d569..00000000000 --- a/arch/arm/include/asm/arch-pantheon/config.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CONFIG_H -#define _PANTHEON_CONFIG_H - -#include - -/* default Dcache Line length for pantheon */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ -#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ -#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */ -#define MV_MFPR_BASE PANTHEON_MFPR_BASE -#define MV_UART_CONSOLE_BASE PANTHEON_UART1_BASE -#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register - represents UART Unit Enable */ -/* - * I2C definition - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_I2C_MV 1 -#define CONFIG_MV_I2C_REG 0xd4011000 -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 0 -#define CONFIG_SYS_I2C_SLAVE 0xfe -#endif - -/* - * MMC definition - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_CMD_FAT 1 -#define CONFIG_MMC 1 -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_SDHCI 1 -#define CONFIG_MMC_SDHCI_IO_ACCESSORS 1 -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 0x1000 -#define CONFIG_MMC_SDMA 1 -#define CONFIG_MV_SDHCI 1 -#define CONFIG_DOS_PARTITION 1 -#define CONFIG_EFI_PARTITION 1 -#define CONFIG_SYS_MMC_NUM 2 -#define CONFIG_SYS_MMC_BASE {0xD4280000, 0xd4281000} -#endif - -#endif /* _PANTHEON_CONFIG_H */ diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h deleted file mode 100644 index 3ccdf8a359f..00000000000 --- a/arch/arm/include/asm/arch-pantheon/cpu.h +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_CPU_H -#define _PANTHEON_CPU_H - -#include -#include - -/* - * Main Power Management (MPMU) Registers - * Refer Register Datasheet 9.1 - */ -struct panthmpmu_registers { - u8 pad0[0x0024]; - u32 ccgr; /*0x0024*/ - u8 pad1[0x0200 - 0x024 - 4]; - u32 wdtpcr; /*0x0200*/ - u8 pad2[0x1020 - 0x200 - 4]; - u32 aprr; /*0x1020*/ - u32 acgr; /*0x1024*/ -}; - -/* - * Application Power Management (APMU) Registers - * Refer Register Datasheet 9.2 - */ -struct panthapmu_registers { - u8 pad0[0x0054]; - u32 sd1; /*0x0054*/ - u8 pad1[0x00e0 - 0x054 - 4]; - u32 sd3; /*0x00e0*/ -}; - -/* - * APB Clock Reset/Control Registers - * Refer Register Datasheet 6.14 - */ -struct panthapb_registers { - u32 uart0; /*0x000*/ - u32 uart1; /*0x004*/ - u32 gpio; /*0x008*/ - u8 pad0[0x02c - 0x08 - 4]; - u32 twsi; /*0x02c*/ - u8 pad1[0x034 - 0x2c - 4]; - u32 timers; /*0x034*/ -}; - -/* - * CPU Interface Registers - * Refer Register Datasheet 4.3 - */ -struct panthcpu_registers { - u32 chip_id; /* Chip Id Reg */ - u32 pad; - u32 cpu_conf; /* CPU Conf Reg */ - u32 pad1; - u32 cpu_sram_spd; /* CPU SRAM Speed Reg */ - u32 pad2; - u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */ - u32 mcb_conf; /* MCB Conf Reg */ - u32 sys_boot_ctl; /* Sytem Boot Control */ -}; - -/* - * Functions - */ -u32 panth_sdram_base(int); -u32 panth_sdram_size(int); -int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks); - -#endif /* _PANTHEON_CPU_H */ diff --git a/arch/arm/include/asm/arch-pantheon/gpio.h b/arch/arm/include/asm/arch-pantheon/gpio.h deleted file mode 100644 index e69de29bb2d..00000000000 diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h deleted file mode 100644 index 7909d53d466..00000000000 --- a/arch/arm/include/asm/arch-pantheon/mfp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Based on arch/arm/include/asm/arch-armada100/mfp.h - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __PANTHEON_MFP_H -#define __PANTHEON_MFP_H - -/* - * Frequently used MFP Configuration macros for all PANTHEON family of SoCs - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -/* UART2 */ -#define MFP47_UART2_RXD (MFP_REG(0x198) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP48_UART2_TXD (MFP_REG(0x19c) | MFP_AF6 | MFP_DRIVE_MEDIUM) -#define MFP53_CI2C_SCL (MFP_REG(0x1b0) | MFP_AF2 | MFP_DRIVE_MEDIUM) -#define MFP54_CI2C_SDA (MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM) - -/* More macros can be defined here... */ -#define MFP_MMC1_DAT7 (MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT6 (MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT5 (MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT4 (MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_DAT3 (MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT2 (MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT1 (MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_DAT0 (MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CMD (MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CLK (MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST) -#define MFP_MMC1_CD (MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM) -#define MFP_MMC1_WP (MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM) - -#define MFP_PIN_MAX 117 -#endif diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h deleted file mode 100644 index c3a71bfce49..00000000000 --- a/arch/arm/include/asm/arch-pantheon/pantheon.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _PANTHEON_H -#define _PANTHEON_H - -/* Common APB clock register bit definitions */ -#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */ -#define APBC_FNCLK (1<<1) /* Functional Clock Enable */ -#define APBC_RST (1<<2) /* Reset Generation */ -/* Functional Clock Selection Mask */ -#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) - -/* Common APMU register bit definitions */ -#define APMU_PERI_CLK (1<<4) /* Peripheral Clock Enable */ -#define APMU_AXI_CLK (1<<3) /* AXI Clock Enable*/ -#define APMU_PERI_RST (1<<1) /* Peripheral Reset */ -#define APMU_AXI_RST (1<<0) /* AXI Reset */ - -/* Register Base Addresses */ -#define PANTHEON_DRAM_BASE 0xB0000000 -#define PANTHEON_TIMER_BASE 0xD4014000 -#define PANTHEON_WD_TIMER_BASE 0xD4080000 -#define PANTHEON_APBC_BASE 0xD4015000 -#define PANTHEON_UART1_BASE 0xD4017000 -#define PANTHEON_UART2_BASE 0xD4018000 -#define PANTHEON_GPIO_BASE 0xD4019000 -#define PANTHEON_MFPR_BASE 0xD401E000 -#define PANTHEON_MPMU_BASE 0xD4050000 -#define PANTHEON_APMU_BASE 0xD4282800 -#define PANTHEON_CPU_BASE 0xD4282C00 - -#endif /* _PANTHEON_H */ diff --git a/board/Marvell/dkb/Kconfig b/board/Marvell/dkb/Kconfig deleted file mode 100644 index f6748941c69..00000000000 --- a/board/Marvell/dkb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_DKB - -config SYS_BOARD - default "dkb" - -config SYS_VENDOR - default "Marvell" - -config SYS_SOC - default "pantheon" - -config SYS_CONFIG_NAME - default "dkb" - -endif diff --git a/board/Marvell/dkb/MAINTAINERS b/board/Marvell/dkb/MAINTAINERS deleted file mode 100644 index c272b7ae743..00000000000 --- a/board/Marvell/dkb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -DKB BOARD -M: Lei Wen -S: Maintained -F: board/Marvell/dkb/ -F: include/configs/dkb.h -F: configs/dkb_defconfig diff --git a/board/Marvell/dkb/Makefile b/board/Marvell/dkb/Makefile deleted file mode 100644 index 9d885791206..00000000000 --- a/board/Marvell/dkb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2011 -# Marvell Semiconductor -# Written-by: Lei Wen -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := dkb.o diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c deleted file mode 100644 index c0c31259a32..00000000000 --- a/board/Marvell/dkb/dkb.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#ifdef CONFIG_GENERIC_MMC -#include -#endif - -DECLARE_GLOBAL_DATA_PTR; - -int board_early_init_f(void) -{ - u32 mfp_cfg[] = { - /* Enable Console on UART2 */ - MFP47_UART2_RXD, - MFP48_UART2_TXD, - - /* I2C */ - MFP53_CI2C_SCL, - MFP54_CI2C_SDA, - - /* MMC1 */ - MFP_MMC1_DAT7, - MFP_MMC1_DAT6, - MFP_MMC1_DAT5, - MFP_MMC1_DAT4, - MFP_MMC1_DAT3, - MFP_MMC1_DAT2, - MFP_MMC1_DAT1, - MFP_MMC1_DAT0, - MFP_MMC1_CMD, - MFP_MMC1_CLK, - MFP_MMC1_CD, - MFP_MMC1_WP, - - MFP_EOC /*End of configureation*/ - }; - /* configure MFP's */ - mfp_config(mfp_cfg); - - return 0; -} - -int board_init(void) -{ - /* arch number of Board */ - gd->bd->bi_arch_number = MACH_TYPE_TTC_DKB; - /* adress of boot parameters */ - gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100; - return 0; -} - -#ifdef CONFIG_GENERIC_MMC -#define I2C_SLAVE_ADDR 0x34 -#define LDO13_REG 0x28 -#define LDO_V30 0x6 -#define LDO_VOLTAGE(x) ((x & 0x7) << 1) -#define LDO_EN 0x1 -int board_mmc_init(bd_t *bd) -{ - ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE; - u8 i, data; - - /* set LDO 13 to 3.0v */ - data = LDO_VOLTAGE(LDO_V30) | LDO_EN; - i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1); - - for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) { - if (mv_sdh_init(mmc_base_address[i], 0, 0, - SDHCI_QUIRK_32BIT_DMA_ADDR)) - return 1; - } - - return 0; -} -#endif diff --git a/configs/dkb_defconfig b/configs/dkb_defconfig deleted file mode 100644 index 0be9578f4f1..00000000000 --- a/configs/dkb_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_DKB=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 0fc6ac7fda2..d206251d7fb 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +dkb arm arm926ejs - - Lei Wen jadecpu arm arm926ejs - - Matthias Weisser icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23 diff --git a/include/configs/dkb.h b/include/configs/dkb.h deleted file mode 100644 index 7ffbb14e309..00000000000 --- a/include/configs/dkb.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * (C) Copyright 2011 - * Marvell Semiconductor - * Written-by: Lei Wen - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_DKB_H -#define __CONFIG_DKB_H - -/* - * Version number information - */ -#define CONFIG_IDENT_STRING "\nMarvell-TTC DKB" - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_PANTHEON 1 /* SOC Family Name */ -#define CONFIG_MACH_TTC_DKB 1 /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) -#define CONFIG_NR_DRAM_BANKS_MAX 2 - -/* - * Commands configuration - */ -#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ -#include -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MMC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#undef CONFIG_ARCH_MISC_INIT - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */ -#define CONFIG_ENV_SIZE 0x20000 /* 64k */ - -#endif /* __CONFIG_DKB_H */ -- cgit v1.3.1 From a2f39e830e509cb63aad2c752573d1c871a1d4bf Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:07 +0900 Subject: ARM: remove cm4008 and cm41xx board support These are still non-generic boards. Signed-off-by: Masahiro Yamada Cc: Greg Ungerer Acked-by: Marek Vasut --- arch/arm/Kconfig | 10 - arch/arm/cpu/arm920t/Makefile | 1 - arch/arm/cpu/arm920t/ks8695/Makefile | 9 - arch/arm/cpu/arm920t/ks8695/lowlevel_init.S | 189 ------------- arch/arm/cpu/arm920t/ks8695/timer.c | 77 ------ arch/arm/include/asm/arch-ks8695/platform.h | 294 --------------------- board/cm4008/Kconfig | 12 - board/cm4008/MAINTAINERS | 6 - board/cm4008/Makefile | 8 - board/cm4008/cm4008.c | 88 ------- board/cm4008/config.mk | 1 - board/cm4008/flash.c | 395 ---------------------------- board/cm41xx/Kconfig | 12 - board/cm41xx/MAINTAINERS | 6 - board/cm41xx/Makefile | 8 - board/cm41xx/cm41xx.c | 88 ------- board/cm41xx/config.mk | 1 - board/cm41xx/flash.c | 395 ---------------------------- configs/cm4008_defconfig | 2 - configs/cm41xx_defconfig | 2 - doc/README.scrapyard | 2 + drivers/net/Makefile | 1 - drivers/net/ks8695eth.c | 229 ---------------- drivers/serial/Makefile | 1 - drivers/serial/serial.c | 2 - drivers/serial/serial_ks8695.c | 121 --------- include/configs/cm4008.h | 104 -------- include/configs/cm41xx.h | 104 -------- include/netdev.h | 1 - include/serial.h | 1 - 30 files changed, 2 insertions(+), 2168 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/ks8695/Makefile delete mode 100644 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm920t/ks8695/timer.c delete mode 100644 arch/arm/include/asm/arch-ks8695/platform.h delete mode 100644 board/cm4008/Kconfig delete mode 100644 board/cm4008/MAINTAINERS delete mode 100644 board/cm4008/Makefile delete mode 100644 board/cm4008/cm4008.c delete mode 100644 board/cm4008/config.mk delete mode 100644 board/cm4008/flash.c delete mode 100644 board/cm41xx/Kconfig delete mode 100644 board/cm41xx/MAINTAINERS delete mode 100644 board/cm41xx/Makefile delete mode 100644 board/cm41xx/cm41xx.c delete mode 100644 board/cm41xx/config.mk delete mode 100644 board/cm41xx/flash.c delete mode 100644 configs/cm4008_defconfig delete mode 100644 configs/cm41xx_defconfig delete mode 100644 drivers/net/ks8695eth.c delete mode 100644 drivers/serial/serial_ks8695.c delete mode 100644 include/configs/cm4008.h delete mode 100644 include/configs/cm41xx.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 0bed390f0de..db31be9217f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -88,14 +88,6 @@ config TARGET_SCB9328 bool "Support scb9328" select CPU_ARM920T -config TARGET_CM4008 - bool "Support cm4008" - select CPU_ARM920T - -config TARGET_CM41XX - bool "Support cm41xx" - select CPU_ARM920T - config TARGET_VCMA9 bool "Support VCMA9" select CPU_ARM920T @@ -769,8 +761,6 @@ source "board/broadcom/bcm28155_ap/Kconfig" source "board/broadcom/bcmcygnus/Kconfig" source "board/broadcom/bcmnsp/Kconfig" source "board/cirrus/edb93xx/Kconfig" -source "board/cm4008/Kconfig" -source "board/cm41xx/Kconfig" source "board/compulab/cm_t335/Kconfig" source "board/compulab/cm_fx6/Kconfig" source "board/congatec/cgtqmx6eval/Kconfig" diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index a16838b4797..29a350c9a6f 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -13,5 +13,4 @@ obj-$(CONFIG_USE_IRQ) += interrupts.o obj-$(if $(filter a320,$(SOC)),y) += a320/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ -obj-$(CONFIG_KS8695) += ks8695/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/ks8695/Makefile b/arch/arm/cpu/arm920t/ks8695/Makefile deleted file mode 100644 index 400aa89e99a..00000000000 --- a/arch/arm/cpu/arm920t/ks8695/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = lowlevel_init.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S deleted file mode 100644 index a2a07f2f23c..00000000000 --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S +++ /dev/null @@ -1,189 +0,0 @@ -/* - * lowlevel_init.S - basic hardware initialization for the KS8695 CPU - * - * Copyright (c) 2004-2005, Greg Ungerer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT - -/* - ************************************************************************* - * - * Handy dandy macros - * - ************************************************************************* - */ - -/* Delay a bit */ -.macro DELAY_FOR cycles, reg0 - ldr \reg0, =\cycles - subs \reg0, \reg0, #1 - subne pc, pc, #0xc -.endm - -/* - ************************************************************************* - * - * Some local storage. - * - ************************************************************************* - */ - -/* Should we boot with an interactive console or not */ -.globl serial_console - -/* - ************************************************************************* - * - * Raw hardware initialization code. The important thing is to get - * SDRAM setup and running. We do some other basic things here too, - * like getting the PLL set for high speed, and init the LEDs. - * - ************************************************************************* - */ - -.globl lowlevel_init -lowlevel_init: - -#if DEBUG - /* - * enable UART for early debug trace - */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_DIVISOR) - mov r2, #((25000000+CONFIG_BAUDRATE/2) / CONFIG_BAUDRATE) - str r2, [r1] - ldr r1, =(KS8695_IO_BASE+KS8695_UART_LINE_CTRL) - mov r2, #KS8695_UART_LINEC_WLEN8 - str r2, [r1] /* 8 data bits, no parity, 1 stop */ - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x41 - str r2, [r1] /* write 'A' */ -#endif -#if DEBUG - ldr r1, =(KS8695_IO_BASE+KS8695_UART_TX_HOLDING) - mov r2, #0x42 - str r2, [r1] -#endif - - /* - * remap the memory and flash regions. we want to end up with - * ram from address 0, and flash at 32MB. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL0) - ldr r2, =0xbfc00040 - str r2, [r1] /* large flash map */ - ldr pc, =(highflash+0x02000000-0x00f00000) /* jump to high flash address */ -highflash: - ldr r2, =0x8fe00040 - str r2, [r1] /* remap flash range */ - - /* - * remap the second select region to the 4MB immediately after - * the first region. This way if you have a larger flash (say 8Mb) - * then you can have it all mapped nicely. Has no effect if you - * only have a 4Mb or smaller flash. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_CTRL1) - ldr r2, =0x9fe40040 - str r2, [r1] /* remap flash2 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30000005 - str r2, [r1] /* enable both flash selects */ - -#ifdef CONFIG_CM41xx - /* - * map the second flash chip, using the external IO lines. - */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL0) - ldr r2, =0xafe80b6d - str r2, [r1] /* remap io0 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_IO_CTRL1) - ldr r2, =0xbfec0b6d - str r2, [r1] /* remap io1 region, contiguous */ - ldr r1, =(KS8695_IO_BASE+KS8695_MEM_GENERAL) - ldr r2, =0x30050005 - str r2, [r1] /* enable second flash */ -#endif - - /* - * before relocating, we have to setup RAM timing - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0) -#if (PHYS_SDRAM_1_SIZE == 0x02000000) - ldr r2, =0x7fc0000e /* 32MB */ -#else - ldr r2, =0x3fc0000e /* 16MB */ -#endif - str r2, [r1] /* configure sdram bank0 setup */ - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1) - mov r2, #0 - str r2, [r1] /* configure sdram bank1 setup */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL) - ldr r2, =0x0000000a - str r2, [r1] /* set RAS/CAS timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00030000 - str r2, [r1] /* send NOP command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00010000 - str r2, [r1] /* send PRECHARGE-ALL */ - DELAY_FOR 0x100, r0 - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_REFRESH) - ldr r2, =0x00000020 - str r2, [r1] /* set for fast refresh */ - DELAY_FOR 0x100, r0 - ldr r2, =0x00000190 - str r2, [r1] /* set normal refresh timing */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER) - ldr r2, =0x00020033 - str r2, [r1] /* send mode command */ - DELAY_FOR 0x100, r0 - ldr r2, =0x01f00000 - str r2, [r1] /* enable sdram fifos */ - - /* - * set pll to top speed - */ - ldr r1, =(KS8695_IO_BASE+KS8695_SYSTEN_BUS_CLOCK) - mov r2, #0 - str r2, [r1] /* set pll clock to 166MHz */ - - ldr r1, =(KS8695_IO_BASE+KS8695_SWITCH_CTRL0) - ldr r2, [r1] /* Get switch ctrl0 register */ - and r2, r2, #0x0fc00000 /* Mask out LED control bits */ - orr r2, r2, #0x01800000 /* Set Link/activity/speed actions */ - str r2, [r1] - -#ifdef CONFIG_CM4008 - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_MODE) - ldr r2, =0x0000fe30 - str r2, [r1] /* enable LED's as outputs */ - ldr r1, =(KS8695_IO_BASE+KS8695_GPIO_DATA) - ldr r2, =0x0000fe20 - str r2, [r1] /* turn on power LED */ -#endif -#if defined(CONFIG_CM4008) || defined(CONFIG_CM41xx) - ldr r2, [r1] /* get current GPIO input data */ - tst r2, #0x8 /* check if "erase" depressed */ - beq nobutton - mov r2, #0 /* be quiet on boot, no console */ - ldr r1, =serial_console - str r2, [r1] -nobutton: -#endif - - add lr, lr, #0x02000000 /* flash is now mapped high */ - add ip, ip, #0x02000000 /* this is a hack */ - mov pc, lr /* all done, return */ - -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ diff --git a/arch/arm/cpu/arm920t/ks8695/timer.c b/arch/arm/cpu/arm920t/ks8695/timer.c deleted file mode 100644 index 23db5572de5..00000000000 --- a/arch/arm/cpu/arm920t/ks8695/timer.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * (C) Copyright 2004-2005, Greg Ungerer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -/* - * Initial timer set constants. Nothing complicated, just set for a 1ms - * tick. - */ -#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_1) -#define TIMER_COUNT (TIMER_INTERVAL / 2) -#define TIMER_PULSE TIMER_COUNT - -/* - * Handy KS8695 register access functions. - */ -#define ks8695_read(a) *((volatile ulong *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile ulong *) (KS8695_IO_BASE + (a))) = (v) - -ulong timer_ticks; - -int timer_init (void) -{ - /* Set the hadware timer for 1ms */ - ks8695_write(KS8695_TIMER1, TIMER_COUNT); - ks8695_write(KS8695_TIMER1_PCOUNT, TIMER_PULSE); - ks8695_write(KS8695_TIMER_CTRL, 0x2); - timer_ticks = 0; - - return 0; -} - -ulong get_timer_masked(void) -{ - /* Check for timer wrap */ - if (ks8695_read(KS8695_INT_STATUS) & KS8695_INTMASK_TIMERINT1) { - /* Clear interrupt condition */ - ks8695_write(KS8695_INT_STATUS, KS8695_INTMASK_TIMERINT1); - timer_ticks++; - } - return timer_ticks; -} - -ulong get_timer(ulong base) -{ - return (get_timer_masked() - base); -} - -void __udelay(ulong usec) -{ - ulong start = get_timer_masked(); - ulong end; - - /* Only 1ms resolution :-( */ - end = usec / 1000; - while (get_timer(start) < end) - ; -} - -void reset_cpu (ulong ignored) -{ - ulong tc; - - /* Set timer0 to watchdog, and let it timeout */ - tc = ks8695_read(KS8695_TIMER_CTRL) & 0x2; - ks8695_write(KS8695_TIMER_CTRL, tc); - ks8695_write(KS8695_TIMER0, ((10 << 8) | 0xff)); - ks8695_write(KS8695_TIMER_CTRL, (tc | 0x1)); - - /* Should only wait here till watchdog resets */ - for (;;) - ; -} diff --git a/arch/arm/include/asm/arch-ks8695/platform.h b/arch/arm/include/asm/arch-ks8695/platform.h deleted file mode 100644 index 02f60492639..00000000000 --- a/arch/arm/include/asm/arch-ks8695/platform.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __address_h -#define __address_h 1 - -#define KS8695_SDRAM_START 0x00000000 -#define KS8695_SDRAM_SIZE 0x01000000 -#define KS8695_MEM_SIZE KS8695_SDRAM_SIZE -#define KS8695_MEM_START KS8695_SDRAM_START - -#define KS8695_PCMCIA_IO_BASE 0x03800000 -#define KS8695_PCMCIA_IO_SIZE 0x00040000 - -#define KS8695_IO_BASE 0x03FF0000 -#define KS8695_IO_SIZE 0x00010000 - -#define KS8695_SYSTEN_CONFIG 0x00 -#define KS8695_SYSTEN_BUS_CLOCK 0x04 - -#define KS8695_FLASH_START 0x02800000 -#define KS8695_FLASH_SIZE 0x00400000 - -/*i/o control registers offset difinitions*/ -#define KS8695_IO_CTRL0 0x4000 -#define KS8695_IO_CTRL1 0x4004 -#define KS8695_IO_CTRL2 0x4008 -#define KS8695_IO_CTRL3 0x400C - -/*memory control registers offset difinitions*/ -#define KS8695_MEM_CTRL0 0x4010 -#define KS8695_MEM_CTRL1 0x4014 -#define KS8695_MEM_CTRL2 0x4018 -#define KS8695_MEM_CTRL3 0x401C -#define KS8695_MEM_GENERAL 0x4020 -#define KS8695_SDRAM_CTRL0 0x4030 -#define KS8695_SDRAM_CTRL1 0x4034 -#define KS8695_SDRAM_GENERAL 0x4038 -#define KS8695_SDRAM_BUFFER 0x403C -#define KS8695_SDRAM_REFRESH 0x4040 - -/*WAN control registers offset difinitions*/ -#define KS8695_WAN_DMA_TX 0x6000 -#define KS8695_WAN_DMA_RX 0x6004 -#define KS8695_WAN_DMA_TX_START 0x6008 -#define KS8695_WAN_DMA_RX_START 0x600C -#define KS8695_WAN_TX_LIST 0x6010 -#define KS8695_WAN_RX_LIST 0x6014 -#define KS8695_WAN_MAC_LOW 0x6018 -#define KS8695_WAN_MAC_HIGH 0x601C -#define KS8695_WAN_MAC_ELOW 0x6080 -#define KS8695_WAN_MAC_EHIGH 0x6084 - -/*LAN control registers offset difinitions*/ -#define KS8695_LAN_DMA_TX 0x8000 -#define KS8695_LAN_DMA_RX 0x8004 -#define KS8695_LAN_DMA_TX_START 0x8008 -#define KS8695_LAN_DMA_RX_START 0x800C -#define KS8695_LAN_TX_LIST 0x8010 -#define KS8695_LAN_RX_LIST 0x8014 -#define KS8695_LAN_MAC_LOW 0x8018 -#define KS8695_LAN_MAC_HIGH 0x801C -#define KS8695_LAN_MAC_ELOW 0X8080 -#define KS8695_LAN_MAC_EHIGH 0X8084 - -/*HPNA control registers offset difinitions*/ -#define KS8695_HPNA_DMA_TX 0xA000 -#define KS8695_HPNA_DMA_RX 0xA004 -#define KS8695_HPNA_DMA_TX_START 0xA008 -#define KS8695_HPNA_DMA_RX_START 0xA00C -#define KS8695_HPNA_TX_LIST 0xA010 -#define KS8695_HPNA_RX_LIST 0xA014 -#define KS8695_HPNA_MAC_LOW 0xA018 -#define KS8695_HPNA_MAC_HIGH 0xA01C -#define KS8695_HPNA_MAC_ELOW 0xA080 -#define KS8695_HPNA_MAC_EHIGH 0xA084 - -/*UART control registers offset difinitions*/ -#define KS8695_UART_RX_BUFFER 0xE000 -#define KS8695_UART_TX_HOLDING 0xE004 - -#define KS8695_UART_FIFO_CTRL 0xE008 -#define KS8695_UART_FIFO_TRIG01 0x00 -#define KS8695_UART_FIFO_TRIG04 0x80 -#define KS8695_UART_FIFO_TXRST 0x03 -#define KS8695_UART_FIFO_RXRST 0x02 -#define KS8695_UART_FIFO_FEN 0x01 - -#define KS8695_UART_LINE_CTRL 0xE00C -#define KS8695_UART_LINEC_BRK 0x40 -#define KS8695_UART_LINEC_EPS 0x10 -#define KS8695_UART_LINEC_PEN 0x08 -#define KS8695_UART_LINEC_STP2 0x04 -#define KS8695_UART_LINEC_WLEN8 0x03 -#define KS8695_UART_LINEC_WLEN7 0x02 -#define KS8695_UART_LINEC_WLEN6 0x01 -#define KS8695_UART_LINEC_WLEN5 0x00 - -#define KS8695_UART_MODEM_CTRL 0xE010 -#define KS8695_UART_MODEMC_RTS 0x02 -#define KS8695_UART_MODEMC_DTR 0x01 - -#define KS8695_UART_LINE_STATUS 0xE014 -#define KS8695_UART_LINES_TXFE 0x20 -#define KS8695_UART_LINES_BE 0x10 -#define KS8695_UART_LINES_FE 0x08 -#define KS8695_UART_LINES_PE 0x04 -#define KS8695_UART_LINES_OE 0x02 -#define KS8695_UART_LINES_RXFE 0x01 -#define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE) - -#define KS8695_UART_MODEM_STATUS 0xE018 -#define KS8695_UART_MODEM_DCD 0x80 -#define KS8695_UART_MODEM_DSR 0x20 -#define KS8695_UART_MODEM_CTS 0x10 -#define KS8695_UART_MODEM_DDCD 0x08 -#define KS8695_UART_MODEM_DDSR 0x02 -#define KS8695_UART_MODEM_DCTS 0x01 -#define UART8695_MODEM_ANY 0xFF - -#define KS8695_UART_DIVISOR 0xE01C -#define KS8695_UART_STATUS 0xE020 - -/*Interrupt controlller registers offset difinitions*/ -#define KS8695_INT_CONTL 0xE200 -#define KS8695_INT_ENABLE 0xE204 -#define KS8695_INT_ENABLE_MODEM 0x0800 -#define KS8695_INT_ENABLE_ERR 0x0400 -#define KS8695_INT_ENABLE_RX 0x0200 -#define KS8695_INT_ENABLE_TX 0x0100 - -#define KS8695_INT_STATUS 0xE208 -#define KS8695_INT_WAN_PRIORITY 0xE20C -#define KS8695_INT_HPNA_PRIORITY 0xE210 -#define KS8695_INT_LAN_PRIORITY 0xE214 -#define KS8695_INT_TIMER_PRIORITY 0xE218 -#define KS8695_INT_UART_PRIORITY 0xE21C -#define KS8695_INT_EXT_PRIORITY 0xE220 -#define KS8695_INT_CHAN_PRIORITY 0xE224 -#define KS8695_INT_BUSERROR_PRO 0xE228 -#define KS8695_INT_MASK_STATUS 0xE22C -#define KS8695_FIQ_PEND_PRIORITY 0xE230 -#define KS8695_IRQ_PEND_PRIORITY 0xE234 - -/*timer registers offset difinitions*/ -#define KS8695_TIMER_CTRL 0xE400 -#define KS8695_TIMER1 0xE404 -#define KS8695_TIMER0 0xE408 -#define KS8695_TIMER1_PCOUNT 0xE40C -#define KS8695_TIMER0_PCOUNT 0xE410 - -/*GPIO registers offset difinitions*/ -#define KS8695_GPIO_MODE 0xE600 -#define KS8695_GPIO_CTRL 0xE604 -#define KS8695_GPIO_DATA 0xE608 - -/*SWITCH registers offset difinitions*/ -#define KS8695_SWITCH_CTRL0 0xE800 -#define KS8695_SWITCH_CTRL1 0xE804 -#define KS8695_SWITCH_PORT1 0xE808 -#define KS8695_SWITCH_PORT2 0xE80C -#define KS8695_SWITCH_PORT3 0xE810 -#define KS8695_SWITCH_PORT4 0xE814 -#define KS8695_SWITCH_PORT5 0xE818 -#define KS8695_SWITCH_AUTO0 0xE81C -#define KS8695_SWITCH_AUTO1 0xE820 -#define KS8695_SWITCH_LUE_CTRL 0xE824 -#define KS8695_SWITCH_LUE_HIGH 0xE828 -#define KS8695_SWITCH_LUE_LOW 0xE82C -#define KS8695_SWITCH_ADVANCED 0xE830 - -#define KS8695_SWITCH_LPPM12 0xE874 -#define KS8695_SWITCH_LPPM34 0xE878 - -/*host communication registers difinitions*/ -#define KS8695_DSCP_HIGH 0xE834 -#define KS8695_DSCP_LOW 0xE838 -#define KS8695_SWITCH_MAC_HIGH 0xE83C -#define KS8695_SWITCH_MAC_LOW 0xE840 - -/*miscellaneours registers difinitions*/ -#define KS8695_MANAGE_COUNTER 0xE844 -#define KS8695_MANAGE_DATA 0xE848 -#define KS8695_LAN12_POWERMAGR 0xE84C -#define KS8695_LAN34_POWERMAGR 0xE850 - -#define KS8695_DEVICE_ID 0xEA00 -#define KS8695_REVISION_ID 0xEA04 - -#define KS8695_MISC_CONTROL 0xEA08 -#define KS8695_WAN_CONTROL 0xEA0C -#define KS8695_WAN_POWERMAGR 0xEA10 -#define KS8695_WAN_PHY_CONTROL 0xEA14 -#define KS8695_WAN_PHY_STATUS 0xEA18 - -/* bus clock definitions*/ -#define KS8695_BUS_CLOCK_125MHZ 0x0 -#define KS8695_BUS_CLOCK_100MHZ 0x1 -#define KS8695_BUS_CLOCK_62MHZ 0x2 -#define KS8695_BUS_CLOCK_50MHZ 0x3 -#define KS8695_BUS_CLOCK_41MHZ 0x4 -#define KS8695_BUS_CLOCK_33MHZ 0x5 -#define KS8695_BUS_CLOCK_31MHZ 0x6 -#define KS8695_BUS_CLOCK_25MHZ 0x7 - -/* ------------------------------------------------------------------------------- - * definations for IRQ - * -------------------------------------------------------------------------------*/ - -#define KS8695_INT_EXT_INT0 2 -#define KS8695_INT_EXT_INT1 3 -#define KS8695_INT_EXT_INT2 4 -#define KS8695_INT_EXT_INT3 5 -#define KS8695_INT_TIMERINT0 6 -#define KS8695_INT_TIMERINT1 7 -#define KS8695_INT_UART_TX 8 -#define KS8695_INT_UART_RX 9 -#define KS8695_INT_UART_LINE_ERR 10 -#define KS8695_INT_UART_MODEMS 11 -#define KS8695_INT_LAN_STOP_RX 12 -#define KS8695_INT_LAN_STOP_TX 13 -#define KS8695_INT_LAN_BUF_RX_STATUS 14 -#define KS8695_INT_LAN_BUF_TX_STATUS 15 -#define KS8695_INT_LAN_RX_STATUS 16 -#define KS8695_INT_LAN_TX_STATUS 17 -#define KS8695_INT_HPAN_STOP_RX 18 -#define KS8695_INT_HPNA_STOP_TX 19 -#define KS8695_INT_HPNA_BUF_RX_STATUS 20 -#define KS8695_INT_HPNA_BUF_TX_STATUS 21 -#define KS8695_INT_HPNA_RX_STATUS 22 -#define KS8695_INT_HPNA_TX_STATUS 23 -#define KS8695_INT_BUS_ERROR 24 -#define KS8695_INT_WAN_STOP_RX 25 -#define KS8695_INT_WAN_STOP_TX 26 -#define KS8695_INT_WAN_BUF_RX_STATUS 27 -#define KS8695_INT_WAN_BUF_TX_STATUS 28 -#define KS8695_INT_WAN_RX_STATUS 29 -#define KS8695_INT_WAN_TX_STATUS 30 - -#define KS8695_INT_UART KS8695_INT_UART_TX - -/* ------------------------------------------------------------------------------- - * Interrupt bit positions - * - * ------------------------------------------------------------------------------- - */ - -#define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 ) -#define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 ) -#define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 ) -#define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 ) -#define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 ) -#define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 ) -#define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX ) -#define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX ) -#define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR ) -#define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS ) -#define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX ) -#define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX ) -#define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS ) -#define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX ) -#define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX ) -#define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS ) -#define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS -#define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS ) -#define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS ) -#define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR ) -#define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX ) -#define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX ) -#define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS ) -#define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS ) -#define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS ) -#define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS ) - -#define KS8695_SC_VALID_INT 0xFFFFFFFF -#define MAXIRQNUM 31 - -/* - * Timer definitions - * - * Use timer 1 & 2 - * (both run at 25MHz). - * - */ -#define TICKS_PER_uSEC 25 -#define mSEC_1 1000 -#define mSEC_10 (mSEC_1 * 10) - -#endif - -/* END */ diff --git a/board/cm4008/Kconfig b/board/cm4008/Kconfig deleted file mode 100644 index de87d5bc12d..00000000000 --- a/board/cm4008/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM4008 - -config SYS_BOARD - default "cm4008" - -config SYS_SOC - default "ks8695" - -config SYS_CONFIG_NAME - default "cm4008" - -endif diff --git a/board/cm4008/MAINTAINERS b/board/cm4008/MAINTAINERS deleted file mode 100644 index 5f08bc3b5c9..00000000000 --- a/board/cm4008/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM4008 BOARD -M: Greg Ungerer -S: Maintained -F: board/cm4008/ -F: include/configs/cm4008.h -F: configs/cm4008_defconfig diff --git a/board/cm4008/Makefile b/board/cm4008/Makefile deleted file mode 100644 index 04b152917bf..00000000000 --- a/board/cm4008/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm4008.o flash.o diff --git a/board/cm4008/cm4008.c b/board/cm4008/cm4008.c deleted file mode 100644 index 740e16443ee..00000000000 --- a/board/cm4008/cm4008.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - char *sp = (char *) 0x0201c020; - char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=16M initrd=0x400000,6M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ks8695_eth_initialize(); -} - -int board_init (void) -{ - /* arch number of CM4008 */ - gd->bd->bi_arch_number = 624; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm4008/config.mk b/board/cm4008/config.mk deleted file mode 100644 index 0d5923b941b..00000000000 --- a/board/cm4008/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00f00000 diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c deleted file mode 100644 index 8315a57ed9a..00000000000 --- a/board/cm4008/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type; - int rcode = 0; - ulong start; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/cm41xx/Kconfig b/board/cm41xx/Kconfig deleted file mode 100644 index 99e675b12d9..00000000000 --- a/board/cm41xx/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_CM41XX - -config SYS_BOARD - default "cm41xx" - -config SYS_SOC - default "ks8695" - -config SYS_CONFIG_NAME - default "cm41xx" - -endif diff --git a/board/cm41xx/MAINTAINERS b/board/cm41xx/MAINTAINERS deleted file mode 100644 index f10eeb58f36..00000000000 --- a/board/cm41xx/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -CM41XX BOARD -#M: - -S: Maintained -F: board/cm41xx/ -F: include/configs/cm41xx.h -F: configs/cm41xx_defconfig diff --git a/board/cm41xx/Makefile b/board/cm41xx/Makefile deleted file mode 100644 index b71ea055666..00000000000 --- a/board/cm41xx/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := cm41xx.o flash.o diff --git a/board/cm41xx/cm41xx.c b/board/cm41xx/cm41xx.c deleted file mode 100644 index eabad48a3c9..00000000000 --- a/board/cm41xx/cm41xx.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, - * - * (C) Copyright 2002 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* ------------------------------------------------------------------------- */ - -#define ks8695_read(a) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) -#define ks8695_write(a,b) *((volatile unsigned int *) (KS8695_IO_BASE+(a))) = (b) - -/* ------------------------------------------------------------------------- */ - - -/* - * Miscelaneous platform dependent initialisations - */ -int env_flash_cmdline (void) -{ - char *sp = (char *) 0x0201c020; - char *ep; - int len; - - /* Check if "erase" push button is depressed */ - if ((ks8695_read(KS8695_GPIO_DATA) & 0x8) == 0) { - printf("### Entering network recovery mode...\n"); - setenv("bootargs", "console=ttyAM0,115200 mem=32M initrd=0x400000,8M root=/dev/ram0"); - setenv("bootcmd", "bootp 0x400000; gofsk 0x400000"); - setenv("bootdelay", "2"); - return 0; - } - - /* Check for flash based kernel boot args to use as default */ - for (ep = sp, len = 0; ((len < 1024) && (*ep != 0)); ep++, len++) - ; - - if ((len > 0) && (len <1024)) - setenv("bootargs", sp); - - return 0; -} - -int board_late_init (void) -{ - return 0; -} - -int board_eth_init(bd_t *bis) -{ - return ks8695_eth_initialize(); -} - -int board_init (void) -{ - /* arch number of CM41xx */ - gd->bd->bi_arch_number = 672; - - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - /* power down all but port 0 on the switch */ - ks8695_write(KS8695_SWITCH_LPPM12, 0x00000005); - ks8695_write(KS8695_SWITCH_LPPM34, 0x00050005); - - return 0; -} - -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} diff --git a/board/cm41xx/config.mk b/board/cm41xx/config.mk deleted file mode 100644 index 0d5923b941b..00000000000 --- a/board/cm41xx/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x00f00000 diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c deleted file mode 100644 index 8315a57ed9a..00000000000 --- a/board/cm41xx/flash.c +++ /dev/null @@ -1,395 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer, OpenGear Inc, greg.ungerer@opengear.com - * - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -#define mb() __asm__ __volatile__ ("" : : : "memory") - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, unsigned char data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]); - flash_get_offsets (PHYS_FLASH_1, &flash_info[i]); - break; - case 1: - /* ignore for now */ - flash_info[i].flash_id = FLASH_UNKNOWN; - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + (__bss_end - __bss_start), - &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) - return; - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - info->start[i] = base + (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F128J3A: - printf ("28F128J3A\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (unsigned char * addr, flash_info_t * info) -{ - volatile unsigned char value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = 0xAA; - addr[0x2AAA] = 0x55; - addr[0x5555] = 0x90; - - mb (); - value = addr[0]; - - switch (value) { - - case (unsigned char)INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = 0xFF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[2]; /* device ID */ - - switch (value) { - - case (unsigned char)INTEL_ID_28F640J3A: - info->flash_id += FLASH_28F640J3A; - info->sector_count = 64; - info->size = 0x00800000; - break; /* => 8 MB */ - - case (unsigned char)INTEL_ID_28F128J3A: - info->flash_id += FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000; - break; /* => 16 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = 0xFF; /* restore read mode */ - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int prot, sect; - ulong type; - int rcode = 0; - ulong start; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) - printf ("- Warning: %d protected sectors will not be erased!\n", prot); - else - printf ("\n"); - - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - volatile unsigned char *addr; - unsigned char status; - - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - addr = (volatile unsigned char *) (info->start[sect]); - *addr = 0x50; /* clear status register */ - *addr = 0x20; /* erase setup */ - *addr = 0xD0; /* erase confirm */ - - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - *addr = 0xB0; /* suspend erase */ - *addr = 0xFF; /* reset to read mode */ - rcode = 1; - break; - } - } - - *addr = 0x50; /* clear status register cmd */ - *addr = 0xFF; /* resest to read mode */ - - printf (" done\n"); - } - } - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - unsigned char data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) - return 4; - - wp = addr; - port_width = 1; - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, data)) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, unsigned char data) -{ - volatile unsigned char *addr = (volatile unsigned char *) dest; - ulong status; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf ("not erased at %08lx (%lx)\n", (ulong) addr, - (ulong) * addr); - return (2); - } - /* Disable interrupts which might cause a timeout here */ - disable_interrupts(); - - *addr = 0x40; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & 0x80) != 0x80) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - *addr = 0xFF; /* restore read mode */ - return (1); - } - } - - *addr = 0xFF; /* restore read mode */ - - return (0); -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/configs/cm4008_defconfig b/configs/cm4008_defconfig deleted file mode 100644 index 487589d4a31..00000000000 --- a/configs/cm4008_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_CM4008=y diff --git a/configs/cm41xx_defconfig b/configs/cm41xx_defconfig deleted file mode 100644 index 15e93623978..00000000000 --- a/configs/cm41xx_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_CM41XX=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index d206251d7fb..aa9ed41db5d 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,8 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +cm4008 arm arm920t - - Greg Ungerer +cm41xx arm arm920t - - dkb arm arm926ejs - - Lei Wen jadecpu arm arm926ejs - - Matthias Weisser icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 46c4ac697d6..da5e2bc3ab7 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o -obj-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o obj-$(CONFIG_MACB) += macb.o diff --git a/drivers/net/ks8695eth.c b/drivers/net/ks8695eth.c deleted file mode 100644 index b4822e95048..00000000000 --- a/drivers/net/ks8695eth.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * ks8695eth.c -- KS8695 ethernet driver - * - * (C) Copyright 2004-2005, Greg Ungerer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/****************************************************************************/ - -#include -#include -#include -#include -#include - -/****************************************************************************/ - -/* - * Hardware register access to the KS8695 LAN ethernet port - * (well, it is the 4 port switch really). - */ -#define ks8695_read(a) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) -#define ks8695_write(a,v) *((volatile unsigned long *) (KS8695_IO_BASE + (a))) = (v) - -/****************************************************************************/ - -/* - * Define the descriptor in-memory data structures. - */ -struct ks8695_txdesc { - uint32_t owner; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -struct ks8695_rxdesc { - uint32_t status; - uint32_t ctrl; - uint32_t addr; - uint32_t next; -}; - -/****************************************************************************/ - -/* - * Allocate local data structures to use for receiving and sending - * packets. Just to keep it all nice and simple. - */ - -#define TXDESCS 4 -#define RXDESCS 4 -#define BUFSIZE 2048 - -volatile struct ks8695_txdesc ks8695_tx[TXDESCS] __attribute__((aligned(256))); -volatile struct ks8695_rxdesc ks8695_rx[RXDESCS] __attribute__((aligned(256))); -volatile uint8_t ks8695_bufs[BUFSIZE*(TXDESCS+RXDESCS)] __attribute__((aligned(2048)));; - -/****************************************************************************/ - -/* - * Ideally we want to use the MAC address stored in flash. - * But we do some sanity checks in case they are not present - * first. - */ -unsigned char eth_mac[] = { - 0x00, 0x13, 0xc6, 0x00, 0x00, 0x00 -}; - -void ks8695_getmac(void) -{ - unsigned char *fp; - int i; - - /* Check if flash MAC is valid */ - fp = (unsigned char *) 0x0201c000; - for (i = 0; (i < 6); i++) { - if ((fp[i] != 0) && (fp[i] != 0xff)) - break; - } - - /* If we found a valid looking MAC address then use it */ - if (i < 6) - memcpy(ð_mac[0], fp, 6); -} - -/****************************************************************************/ - -static int ks8695_eth_init(struct eth_device *dev, bd_t *bd) -{ - int i; - - debug ("%s(%d): eth_reset()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines first */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); - - ks8695_getmac(); - - /* Set MAC address */ - ks8695_write(KS8695_LAN_MAC_LOW, (eth_mac[5] | (eth_mac[4] << 8) | - (eth_mac[3] << 16) | (eth_mac[2] << 24))); - ks8695_write(KS8695_LAN_MAC_HIGH, (eth_mac[1] | (eth_mac[0] << 8))); - - /* Turn the 4 port switch on */ - i = ks8695_read(KS8695_SWITCH_CTRL0); - ks8695_write(KS8695_SWITCH_CTRL0, (i | 0x1)); - /* ks8695_write(KS8695_WAN_CONTROL, 0x3f000066); */ - - /* Initialize descriptor rings */ - for (i = 0; (i < TXDESCS); i++) { - ks8695_tx[i].owner = 0; - ks8695_tx[i].ctrl = 0; - ks8695_tx[i].addr = (uint32_t) &ks8695_bufs[i*BUFSIZE]; - ks8695_tx[i].next = (uint32_t) &ks8695_tx[i+1]; - } - ks8695_tx[TXDESCS-1].ctrl = 0x02000000; - ks8695_tx[TXDESCS-1].next = (uint32_t) &ks8695_tx[0]; - - for (i = 0; (i < RXDESCS); i++) { - ks8695_rx[i].status = 0x80000000; - ks8695_rx[i].ctrl = BUFSIZE - 4; - ks8695_rx[i].addr = (uint32_t) &ks8695_bufs[(i+TXDESCS)*BUFSIZE]; - ks8695_rx[i].next = (uint32_t) &ks8695_rx[i+1]; - } - ks8695_rx[RXDESCS-1].ctrl |= 0x00080000; - ks8695_rx[RXDESCS-1].next = (uint32_t) &ks8695_rx[0]; - - /* The KS8695 is pretty slow reseting the ethernets... */ - udelay(2000000); - - /* Enable the ethernet engine */ - ks8695_write(KS8695_LAN_TX_LIST, (uint32_t) &ks8695_tx[0]); - ks8695_write(KS8695_LAN_RX_LIST, (uint32_t) &ks8695_rx[0]); - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_RX, 0x71); - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - - printf("KS8695 ETHERNET: %pM\n", eth_mac); - return 0; -} - -/****************************************************************************/ - -static void ks8695_eth_halt(struct eth_device *dev) -{ - debug ("%s(%d): eth_halt()\n", __FILE__, __LINE__); - - /* Reset the ethernet engines */ - ks8695_write(KS8695_LAN_DMA_TX, 0x80000000); - ks8695_write(KS8695_LAN_DMA_RX, 0x80000000); -} - -/****************************************************************************/ - -static int ks8695_eth_recv(struct eth_device *dev) -{ - volatile struct ks8695_rxdesc *dp; - int i, len = 0; - - debug ("%s(%d): eth_rx()\n", __FILE__, __LINE__); - - for (i = 0; (i < RXDESCS); i++) { - dp= &ks8695_rx[i]; - if ((dp->status & 0x80000000) == 0) { - len = (dp->status & 0x7ff) - 4; - NetReceive((void *) dp->addr, len); - dp->status = 0x80000000; - ks8695_write(KS8695_LAN_DMA_RX_START, 0x1); - break; - } - } - - return len; -} - -/****************************************************************************/ - -static int ks8695_eth_send(struct eth_device *dev, void *packet, int len) -{ - volatile struct ks8695_txdesc *dp; - static int next = 0; - - debug ("%s(%d): eth_send(packet=%p,len=%d)\n", __FILE__, __LINE__, - packet, len); - - dp = &ks8695_tx[next]; - memcpy((void *) dp->addr, (void *) packet, len); - - if (len < 64) { - memset((void *) (dp->addr + len), 0, 64-len); - len = 64; - } - - dp->ctrl = len | 0xe0000000; - dp->owner = 0x80000000; - - ks8695_write(KS8695_LAN_DMA_TX, 0x3); - ks8695_write(KS8695_LAN_DMA_TX_START, 0x1); - - if (++next >= TXDESCS) - next = 0; - - return 0; -} - -/****************************************************************************/ - -int ks8695_eth_initialize(void) -{ - struct eth_device *dev; - - dev = malloc(sizeof(*dev)); - if (dev == NULL) - return -1; - memset(dev, 0, sizeof(*dev)); - - dev->iobase = KS8695_IO_BASE + KS8695_LAN_DMA_TX; - dev->init = ks8695_eth_init; - dev->halt = ks8695_eth_halt; - dev->send = ks8695_eth_send; - dev->recv = ks8695_eth_recv; - strcpy(dev->name, "ks8695eth"); - - eth_register(dev); - return 0; -} diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 63b0cbf5da8..b385852eee4 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -27,7 +27,6 @@ obj-$(CONFIG_OPENCORES_YANU) += opencores_yanu.o obj-$(CONFIG_SYS_NS16550) += ns16550.o obj-$(CONFIG_S5P) += serial_s5p.o obj-$(CONFIG_IMX_SERIAL) += serial_imx.o -obj-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o obj-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o obj-$(CONFIG_MXC_UART) += serial_mxc.o obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 95c992a5a30..9f78492298d 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -127,7 +127,6 @@ serial_initfunc(evb64260_serial_initialize); serial_initfunc(imx_serial_initialize); serial_initfunc(iop480_serial_initialize); serial_initfunc(jz_serial_initialize); -serial_initfunc(ks8695_serial_initialize); serial_initfunc(leon2_serial_initialize); serial_initfunc(leon3_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); @@ -220,7 +219,6 @@ void serial_initialize(void) imx_serial_initialize(); iop480_serial_initialize(); jz_serial_initialize(); - ks8695_serial_initialize(); leon2_serial_initialize(); leon3_serial_initialize(); lh7a40x_serial_initialize(); diff --git a/drivers/serial/serial_ks8695.c b/drivers/serial/serial_ks8695.c deleted file mode 100644 index 13adabd1126..00000000000 --- a/drivers/serial/serial_ks8695.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * serial.c -- KS8695 serial driver - * - * (C) Copyright 2004, Greg Ungerer - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#ifndef CONFIG_SERIAL1 -#error "Bad: you didn't configure serial ..." -#endif - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define the UART hardware register access structure. - */ -struct ks8695uart { - unsigned int RX; /* 0x00 - Receive data (r) */ - unsigned int TX; /* 0x04 - Transmit data (w) */ - unsigned int FCR; /* 0x08 - Fifo Control (r/w) */ - unsigned int LCR; /* 0x0c - Line Control (r/w) */ - unsigned int MCR; /* 0x10 - Modem Control (r/w) */ - unsigned int LSR; /* 0x14 - Line Status (r/w) */ - unsigned int MSR; /* 0x18 - Modem Status (r/w) */ - unsigned int BD; /* 0x1c - Baud Rate (r/w) */ - unsigned int SR; /* 0x20 - Status (r/w) */ -}; - -#define KS8695_UART_ADDR ((void *) (KS8695_IO_BASE + KS8695_UART_RX_BUFFER)) -#define KS8695_UART_CLK 25000000 - - -/* - * Under some circumstances we want to be "quiet" and not issue any - * serial output - though we want u-boot to otherwise work and behave - * the same. By default be noisy. - */ -int serial_console = 1; - - -static void ks8695_serial_setbrg(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - /* Set to global baud rate and 8 data bits, no parity, 1 stop bit*/ - uartp->BD = KS8695_UART_CLK / gd->baudrate; - uartp->LCR = KS8695_UART_LINEC_WLEN8; -} - -static int ks8695_serial_init(void) -{ - serial_console = 1; - serial_setbrg(); - return 0; -} - -static void ks8695_serial_raw_putc(const char c) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - int i; - - for (i = 0; (i < 0x100000); i++) { - if (uartp->LSR & KS8695_UART_LINES_TXFE) - break; - } - - uartp->TX = c; -} - -static void ks8695_serial_putc(const char c) -{ - if (serial_console) { - ks8695_serial_raw_putc(c); - if (c == '\n') - ks8695_serial_raw_putc('\r'); - } -} - -static int ks8695_serial_tstc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - if (serial_console) - return ((uartp->LSR & KS8695_UART_LINES_RXFE) ? 1 : 0); - return 0; -} - -static int ks8695_serial_getc(void) -{ - volatile struct ks8695uart *uartp = KS8695_UART_ADDR; - - while ((uartp->LSR & KS8695_UART_LINES_RXFE) == 0) - ; - return (uartp->RX); -} - -static struct serial_device ks8695_serial_drv = { - .name = "ks8695_serial", - .start = ks8695_serial_init, - .stop = NULL, - .setbrg = ks8695_serial_setbrg, - .putc = ks8695_serial_putc, - .puts = default_serial_puts, - .getc = ks8695_serial_getc, - .tstc = ks8695_serial_tstc, -}; - -void ks8695_serial_initialize(void) -{ - serial_register(&ks8695_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &ks8695_serial_drv; -} diff --git a/include/configs/cm4008.h b/include/configs/cm4008.h deleted file mode 100644 index 1cb54b3225f..00000000000 --- a/include/configs/cm4008.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2004 - * Greg Ungerer . - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM4008 1 /* it is an OpenGear CM4008 boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=16M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm41xx.h b/include/configs/cm41xx.h deleted file mode 100644 index adebd4b7b0e..00000000000 --- a/include/configs/cm41xx.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * (C) Copyright 2005 - * Greg Ungerer . - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_KS8695 1 /* it is a KS8695 CPU */ -#define CONFIG_CM41xx 1 /* it is an OpenGear CM41xx boad */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_DRIVER_KS8695ETH /* use KS8695 ethernet driver */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ - -/* - * select serial console configuration - */ -#define CONFIG_ENV_IS_NOWHERE -#define CONFIG_KS8695_SERIAL -#define CONFIG_SERIAL1 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include - -#undef CONFIG_CMD_SAVEENV - - -#define CONFIG_BOOTDELAY 0 -#define CONFIG_BOOTARGS "mem=32M console=ttyAM0,115200" -#define CONFIG_BOOTCOMMAND "gofsk 0x02200000" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "boot > " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 16 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x00008000 /* default load address */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00020000 /* lowest 128k of RAM */ - -#define PHYS_FLASH_1 0x02000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 128 KB sectors (x1) */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */ - -#endif /* __CONFIG_H */ diff --git a/include/netdev.h b/include/netdev.h index daffc1222d6..90140bd9bbb 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -55,7 +55,6 @@ int ftmac100_initialize(bd_t *bits); int ftmac110_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); -int ks8695_eth_initialize(void); int ks8851_mll_initialize(u8 dev_num, int base_addr); int lan91c96_initialize(u8 dev_num, int base_addr); int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); diff --git a/include/serial.h b/include/serial.h index 3d2e5697f48..de40e9406f8 100644 --- a/include/serial.h +++ b/include/serial.h @@ -182,7 +182,6 @@ void evb64260_serial_initialize(void); void imx_serial_initialize(void); void iop480_serial_initialize(void); void jz_serial_initialize(void); -void ks8695_serial_initialize(void); void leon2_serial_initialize(void); void leon3_serial_initialize(void); void lh7a40x_serial_initialize(void); -- cgit v1.3.1 From 29fc6f24926e2c9d37dbbc37a2e2df2eced4c678 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:08 +0900 Subject: ARM: remove a320evb board support This is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Po-Yu Chuang Acked-by: Marek Vasut --- arch/arm/Kconfig | 5 - arch/arm/cpu/arm920t/Makefile | 1 - arch/arm/cpu/arm920t/a320/Makefile | 9 -- arch/arm/cpu/arm920t/a320/reset.S | 10 -- arch/arm/cpu/arm920t/a320/timer.c | 118 ------------------- arch/arm/include/asm/arch-a320/a320.h | 22 ---- board/faraday/a320evb/Kconfig | 15 --- board/faraday/a320evb/MAINTAINERS | 6 - board/faraday/a320evb/Makefile | 9 -- board/faraday/a320evb/a320evb.c | 59 ---------- board/faraday/a320evb/lowlevel_init.S | 106 ----------------- configs/a320evb_defconfig | 2 - doc/README.scrapyard | 1 + include/configs/a320evb.h | 211 ---------------------------------- 14 files changed, 1 insertion(+), 573 deletions(-) delete mode 100644 arch/arm/cpu/arm920t/a320/Makefile delete mode 100644 arch/arm/cpu/arm920t/a320/reset.S delete mode 100644 arch/arm/cpu/arm920t/a320/timer.c delete mode 100644 arch/arm/include/asm/arch-a320/a320.h delete mode 100644 board/faraday/a320evb/Kconfig delete mode 100644 board/faraday/a320evb/MAINTAINERS delete mode 100644 board/faraday/a320evb/Makefile delete mode 100644 board/faraday/a320evb/a320evb.c delete mode 100644 board/faraday/a320evb/lowlevel_init.S delete mode 100644 configs/a320evb_defconfig delete mode 100644 include/configs/a320evb.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index db31be9217f..f6a17207a96 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -73,10 +73,6 @@ config TARGET_INTEGRATORCP_CM920T bool "Support integratorcp_cm920t" select CPU_ARM920T -config TARGET_A320EVB - bool "Support a320evb" - select CPU_ARM920T - config ARCH_AT91 bool "Atmel AT91" @@ -770,7 +766,6 @@ source "board/denx/m28evk/Kconfig" source "board/denx/m53evk/Kconfig" source "board/embest/mx6boards/Kconfig" source "board/esg/ima3-mx53/Kconfig" -source "board/faraday/a320evb/Kconfig" source "board/freescale/ls2085a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" diff --git a/arch/arm/cpu/arm920t/Makefile b/arch/arm/cpu/arm920t/Makefile index 29a350c9a6f..6582938db0e 100644 --- a/arch/arm/cpu/arm920t/Makefile +++ b/arch/arm/cpu/arm920t/Makefile @@ -10,7 +10,6 @@ extra-y = start.o obj-y += cpu.o obj-$(CONFIG_USE_IRQ) += interrupts.o -obj-$(if $(filter a320,$(SOC)),y) += a320/ obj-$(CONFIG_EP93XX) += ep93xx/ obj-$(CONFIG_IMX) += imx/ obj-$(CONFIG_S3C24X0) += s3c24x0/ diff --git a/arch/arm/cpu/arm920t/a320/Makefile b/arch/arm/cpu/arm920t/a320/Makefile deleted file mode 100644 index bbdab588c5e..00000000000 --- a/arch/arm/cpu/arm920t/a320/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += reset.o -obj-y += timer.o diff --git a/arch/arm/cpu/arm920t/a320/reset.S b/arch/arm/cpu/arm920t/a320/reset.S deleted file mode 100644 index 81f9dc983f3..00000000000 --- a/arch/arm/cpu/arm920t/a320/reset.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.global reset_cpu -reset_cpu: - b reset_cpu diff --git a/arch/arm/cpu/arm920t/a320/timer.c b/arch/arm/cpu/arm920t/a320/timer.c deleted file mode 100644 index 1ac5b601293..00000000000 --- a/arch/arm/cpu/arm920t/a320/timer.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -#define TIMER_CLOCK 32768 -#define TIMER_LOAD_VAL 0xffffffff - -static inline unsigned long long tick_to_time(unsigned long long tick) -{ - tick *= CONFIG_SYS_HZ; - do_div(tick, gd->arch.timer_rate_hz); - - return tick; -} - -static inline unsigned long long usec_to_tick(unsigned long long usec) -{ - usec *= gd->arch.timer_rate_hz; - do_div(usec, 1000000); - - return usec; -} - -int timer_init(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - unsigned int cr; - - debug("%s()\n", __func__); - - /* disable timers */ - writel(0, &tmr->cr); - - /* use 32768Hz oscillator for RTC, WDT, TIMER */ - ftpmu010_32768osc_enable(); - - /* setup timer */ - writel(TIMER_LOAD_VAL, &tmr->timer3_load); - writel(TIMER_LOAD_VAL, &tmr->timer3_counter); - writel(0, &tmr->timer3_match1); - writel(0, &tmr->timer3_match2); - - /* we don't want timer to issue interrupts */ - writel(FTTMR010_TM3_MATCH1 | - FTTMR010_TM3_MATCH2 | - FTTMR010_TM3_OVERFLOW, - &tmr->interrupt_mask); - - cr = readl(&tmr->cr); - cr |= FTTMR010_TM3_CLOCK; /* use external clock */ - cr |= FTTMR010_TM3_ENABLE; - writel(cr, &tmr->cr); - - gd->arch.timer_rate_hz = TIMER_CLOCK; - gd->arch.tbu = gd->arch.tbl = 0; - - return 0; -} - -/* - * Get the current 64 bit timer tick count - */ -unsigned long long get_ticks(void) -{ - struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_FTTMR010_BASE; - ulong now = TIMER_LOAD_VAL - readl(&tmr->timer3_counter); - - /* increment tbu if tbl has rolled over */ - if (now < gd->arch.tbl) - gd->arch.tbu++; - gd->arch.tbl = now; - return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl; -} - -void __udelay(unsigned long usec) -{ - unsigned long long start; - ulong tmo; - - start = get_ticks(); /* get current timestamp */ - tmo = usec_to_tick(usec); /* convert usecs to ticks */ - while ((get_ticks() - start) < tmo) - ; /* loop till time has passed */ -} - -/* - * get_timer(base) can be used to check for timeouts or - * to measure elasped time relative to an event: - * - * ulong start_time = get_timer(0) sets start_time to the current - * time value. - * get_timer(start_time) returns the time elapsed since then. - * - * The time is used in CONFIG_SYS_HZ units! - */ -ulong get_timer(ulong base) -{ - return tick_to_time(get_ticks()) - base; -} - -/* - * Return the number of timer ticks per second. - */ -ulong get_tbclk(void) -{ - return gd->arch.timer_rate_hz; -} diff --git a/arch/arm/include/asm/arch-a320/a320.h b/arch/arm/include/asm/arch-a320/a320.h deleted file mode 100644 index f2db8e1061f..00000000000 --- a/arch/arm/include/asm/arch-a320/a320.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __A320_H -#define __A320_H - -/* - * Hardware register bases - */ -#define CONFIG_FTSMC020_BASE 0x90200000 /* Static Memory Controller */ -#define CONFIG_DEBUG_LED 0x902ffffc /* Debug LED */ -#define CONFIG_FTSDMC020_BASE 0x90300000 /* SDRAM Controller */ -#define CONFIG_FTMAC100_BASE 0x90900000 /* Ethernet */ -#define CONFIG_FTPMU010_BASE 0x98100000 /* Power Management Unit */ -#define CONFIG_FTTMR010_BASE 0x98400000 /* Timer */ -#define CONFIG_FTRTC010_BASE 0x98600000 /* Real Time Clock*/ - -#endif /* __A320_H */ diff --git a/board/faraday/a320evb/Kconfig b/board/faraday/a320evb/Kconfig deleted file mode 100644 index 02c42cb0a29..00000000000 --- a/board/faraday/a320evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_A320EVB - -config SYS_BOARD - default "a320evb" - -config SYS_VENDOR - default "faraday" - -config SYS_SOC - default "a320" - -config SYS_CONFIG_NAME - default "a320evb" - -endif diff --git a/board/faraday/a320evb/MAINTAINERS b/board/faraday/a320evb/MAINTAINERS deleted file mode 100644 index f13b015bb40..00000000000 --- a/board/faraday/a320evb/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -A320EVB BOARD -M: Po-Yu Chuang -S: Maintained -F: board/faraday/a320evb/ -F: include/configs/a320evb.h -F: configs/a320evb_defconfig diff --git a/board/faraday/a320evb/Makefile b/board/faraday/a320evb/Makefile deleted file mode 100644 index 518ce3fcb4b..00000000000 --- a/board/faraday/a320evb/Makefile +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y := a320evb.o -obj-y += lowlevel_init.o diff --git a/board/faraday/a320evb/a320evb.c b/board/faraday/a320evb/a320evb.c deleted file mode 100644 index c42635b705b..00000000000 --- a/board/faraday/a320evb/a320evb.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#include - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - ftsmc020_init(); /* initialize Flash */ - return 0; -} - -int dram_init(void) -{ - unsigned long sdram_base = PHYS_SDRAM_1; - unsigned long expected_size = PHYS_SDRAM_1_SIZE; - unsigned long actual_size; - - actual_size = get_ram_size((void *)sdram_base, expected_size); - - gd->ram_size = actual_size; - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return 0; -} - -int board_eth_init(bd_t *bd) -{ - return ftmac100_initialize(bd); -} - -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - if (banknum == 0) { /* non-CFI boot flash */ - info->portwidth = FLASH_CFI_8BIT; - info->chipwidth = FLASH_CFI_BY8; - info->interface = FLASH_CFI_X8; - return 1; - } else - return 0; -} diff --git a/board/faraday/a320evb/lowlevel_init.S b/board/faraday/a320evb/lowlevel_init.S deleted file mode 100644 index d366260a80e..00000000000 --- a/board/faraday/a320evb/lowlevel_init.S +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -#include -#include - -/* - * parameters for the SDRAM controller - */ -#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0) -#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1) -#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR) -#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR) -#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR) - -#define TP0_D CONFIG_SYS_FTSDMC020_TP0 -#define TP1_D CONFIG_SYS_FTSDMC020_TP1 -#define CR_D1 FTSDMC020_CR_IPREC -#define CR_D2 FTSDMC020_CR_ISMR -#define CR_D3 FTSDMC020_CR_IREF - -#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ - FTSDMC020_BANK_BASE(PHYS_SDRAM_1)) -#define ACR_D FTSDMC020_ACR_TOC(0x18) - -/* - * numeric 7 segment display - */ -.macro led, num - write32 CONFIG_DEBUG_LED, \num -.endm - -/* - * Waiting for SDRAM to set up - */ -.macro wait_sdram - ldr r0, =CONFIG_FTSDMC020_BASE -1: - ldr r1, [r0, #FTSDMC020_OFFSET_CR] - cmp r1, #0 - bne 1b -.endm - -.globl lowlevel_init -lowlevel_init: - mov r11, lr - - led 0x0 - - bl init_sdmc - - led 0x1 - - /* everything is fine now */ - mov lr, r11 - mov pc, lr - -/* - * memory initialization - */ -init_sdmc: - led 0x10 - - /* set SDRAM register */ - - write32 TP0_A, TP0_D - led 0x11 - - write32 TP1_A, TP1_D - led 0x12 - - /* set to precharge */ - write32 CR_A, CR_D1 - led 0x13 - - wait_sdram - led 0x14 - - /* set mode register */ - write32 CR_A, CR_D2 - led 0x15 - - wait_sdram - led 0x16 - - /* set to refresh */ - write32 CR_A, CR_D3 - led 0x17 - - wait_sdram - led 0x18 - - write32 B0_BSR_A, B0_BSR_D - led 0x19 - - write32 ACR_A, ACR_D - led 0x1a - - mov pc, lr diff --git a/configs/a320evb_defconfig b/configs/a320evb_defconfig deleted file mode 100644 index 5ebf5e6a710..00000000000 --- a/configs/a320evb_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_A320EVB=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index aa9ed41db5d..1528b9b9283 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +a320evb arm arm920t - - Po-Yu Chuang cm4008 arm arm920t - - Greg Ungerer cm41xx arm arm920t - - dkb arm arm926ejs - - Lei Wen diff --git a/include/configs/a320evb.h b/include/configs/a320evb.h deleted file mode 100644 index 0d3cf369b69..00000000000 --- a/include/configs/a320evb.h +++ /dev/null @@ -1,211 +0,0 @@ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang - * - * Configuation settings for the Faraday A320 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * mach-type definition - */ -#define MACH_TYPE_FARADAY 758 -#define CONFIG_MACH_TYPE MACH_TYPE_FARADAY - -/* - * Linux kernel tagged list - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * CPU and Board Configuration Options - */ -#undef CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Power Management Unit - */ -#define CONFIG_FTPMU010_POWER - -/* - * Timer - */ - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART */ -#define CONFIG_BAUDRATE 38400 -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 0x98200000 -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_CLK 18432000 - -/* - * Ethernet - */ -#define CONFIG_FTMAC100 - -#define CONFIG_BOOTDELAY 3 - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_DATE -#define CONFIG_CMD_PING - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 16 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/* - * SDRAM controller configuration - */ -#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ - FTSDMC020_TP0_TRP(1) | \ - FTSDMC020_TP0_TRCD(1) | \ - FTSDMC020_TP0_TRF(3) | \ - FTSDMC020_TP0_TWR(1) | \ - FTSDMC020_TP0_TCL(2)) - -#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ - FTSDMC020_TP1_INI_REFT(8) | \ - FTSDMC020_TP1_REF_INTV(0x180)) - -#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ - FTSDMC020_BANK_DDW_X16 | \ - FTSDMC020_BANK_DSZ_256M | \ - FTSDMC020_BANK_MBW_32 | \ - FTSDMC020_BANK_SIZE_64M) - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Load address and memory test area should agree with - * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000) - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000) - -#define CONFIG_SYS_TEXT_BASE 0 - -/* - * Static memory controller configuration - */ - -#define CONFIG_FTSMC020 -#include - -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ - FTSMC020_BANK_SIZE_1M | \ - FTSMC020_BANK_MBW_8) - -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} - -/* - * FLASH and environment organization - */ - -/* use CFI framework */ -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_FLASH_CFI_DRIVER - -/* support JEDEC */ -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx8 - -#define PHYS_FLASH_1 0x00000000 -#define PHYS_FLASH_2 0x00400000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } - -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -#undef CONFIG_SYS_FLASH_EMPTY_INFO - -/* environments */ -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) -#define CONFIG_ENV_SIZE 0x20000 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 50b82c4b702c59599c567fa82decb20d60f5110d Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:09 +0900 Subject: ARM: remove tnetv107x board support This is still a non-generic board. Signed-off-by: Masahiro Yamada Cc: Chan-Taek Park Acked-by: Marek Vasut --- arch/arm/Kconfig | 5 - arch/arm/cpu/arm1176/Makefile | 1 - arch/arm/cpu/arm1176/start.S | 22 -- arch/arm/cpu/arm1176/tnetv107x/Makefile | 6 - arch/arm/cpu/arm1176/tnetv107x/aemif.c | 78 ----- arch/arm/cpu/arm1176/tnetv107x/clock.c | 432 ------------------------- arch/arm/cpu/arm1176/tnetv107x/init.c | 22 -- arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S | 10 - arch/arm/cpu/arm1176/tnetv107x/mux.c | 319 ------------------ arch/arm/cpu/arm1176/tnetv107x/timer.c | 93 ------ arch/arm/include/asm/arch-tnetv107x/clock.h | 53 --- arch/arm/include/asm/arch-tnetv107x/hardware.h | 160 --------- arch/arm/include/asm/arch-tnetv107x/mux.h | 291 ----------------- board/ti/tnetv107xevm/Kconfig | 15 - board/ti/tnetv107xevm/MAINTAINERS | 6 - board/ti/tnetv107xevm/Makefile | 5 - board/ti/tnetv107xevm/config.mk | 5 - board/ti/tnetv107xevm/sdb_board.c | 134 -------- configs/tnetv107x_evm_defconfig | 2 - doc/README.scrapyard | 1 + drivers/watchdog/Makefile | 1 - drivers/watchdog/tnetv107x_wdt.c | 165 ---------- include/configs/tnetv107x_evm.h | 139 -------- 23 files changed, 1 insertion(+), 1964 deletions(-) delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/Makefile delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/aemif.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/clock.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/init.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/mux.c delete mode 100644 arch/arm/cpu/arm1176/tnetv107x/timer.c delete mode 100644 arch/arm/include/asm/arch-tnetv107x/clock.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/hardware.h delete mode 100644 arch/arm/include/asm/arch-tnetv107x/mux.h delete mode 100644 board/ti/tnetv107xevm/Kconfig delete mode 100644 board/ti/tnetv107xevm/MAINTAINERS delete mode 100644 board/ti/tnetv107xevm/Makefile delete mode 100644 board/ti/tnetv107xevm/config.mk delete mode 100644 board/ti/tnetv107xevm/sdb_board.c delete mode 100644 configs/tnetv107x_evm_defconfig delete mode 100644 drivers/watchdog/tnetv107x_wdt.c delete mode 100644 include/configs/tnetv107x_evm.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f6a17207a96..7a2f91c48ef 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -294,10 +294,6 @@ config TARGET_RPI_2 bool "Support rpi_2" select CPU_V7 -config TARGET_TNETV107X_EVM - bool "Support tnetv107x_evm" - select CPU_ARM1176 - config TARGET_INTEGRATORAP_CM946ES bool "Support integratorap_cm946es" select CPU_ARM946ES @@ -834,7 +830,6 @@ source "board/ti/am335x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/ti814x/Kconfig" source "board/ti/ti816x/Kconfig" -source "board/ti/tnetv107xevm/Kconfig" source "board/timll/devkit3250/Kconfig" source "board/toradex/colibri_pxa270/Kconfig" source "board/tqc/tqma6/Kconfig" diff --git a/arch/arm/cpu/arm1176/Makefile b/arch/arm/cpu/arm1176/Makefile index ead2303373e..480e1304891 100644 --- a/arch/arm/cpu/arm1176/Makefile +++ b/arch/arm/cpu/arm1176/Makefile @@ -12,4 +12,3 @@ extra-y = start.o obj-y = cpu.o obj-$(CONFIG_BCM2835) += bcm2835/ -obj-$(CONFIG_TNETV107X) += tnetv107x/ diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 0704bdde27e..ac937bf5b08 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -96,28 +96,6 @@ mmu_disable: mov pc, r2 mmu_disable_phys: -#ifdef CONFIG_DISABLE_TCM - /* - * Disable the TCMs - */ - mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ - cmp r0, #0 - beq skip_tcmdisable - mov r1, #0 - mov r2, #1 - tst r0, r2 - mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ - tst r0, r2, LSL #16 - mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ -skip_tcmdisable: -#endif -#endif - -#ifdef CONFIG_PERIPORT_REMAP - /* Peri port setup */ - ldr r0, =CONFIG_PERIPORT_BASE - orr r0, r0, #CONFIG_PERIPORT_SIZE - mcr p15,0,r0,c15,c2,4 #endif /* diff --git a/arch/arm/cpu/arm1176/tnetv107x/Makefile b/arch/arm/cpu/arm1176/tnetv107x/Makefile deleted file mode 100644 index a4c1edfc71d..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += aemif.o clock.o init.o mux.o timer.o -obj-y += lowlevel_init.o diff --git a/arch/arm/cpu/arm1176/tnetv107x/aemif.c b/arch/arm/cpu/arm1176/tnetv107x/aemif.c deleted file mode 100644 index a0f57289e96..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/aemif.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * TNETV107X: Asynchronous EMIF Configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define ASYNC_EMIF_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE -#define ASYNC_EMIF_CONFIG(cs) (ASYNC_EMIF_BASE+0x10+(cs)*4) -#define ASYNC_EMIF_ONENAND_CONTROL (ASYNC_EMIF_BASE+0x5c) -#define ASYNC_EMIF_NAND_CONTROL (ASYNC_EMIF_BASE+0x60) -#define ASYNC_EMIF_WAITCYCLE_CONFIG (ASYNC_EMIF_BASE+0x4) - -#define CONFIG_SELECT_STROBE(v) ((v) ? 1 << 31 : 0) -#define CONFIG_EXTEND_WAIT(v) ((v) ? 1 << 30 : 0) -#define CONFIG_WR_SETUP(v) (((v) & 0x0f) << 26) -#define CONFIG_WR_STROBE(v) (((v) & 0x3f) << 20) -#define CONFIG_WR_HOLD(v) (((v) & 0x07) << 17) -#define CONFIG_RD_SETUP(v) (((v) & 0x0f) << 13) -#define CONFIG_RD_STROBE(v) (((v) & 0x3f) << 7) -#define CONFIG_RD_HOLD(v) (((v) & 0x07) << 4) -#define CONFIG_TURN_AROUND(v) (((v) & 0x03) << 2) -#define CONFIG_WIDTH(v) (((v) & 0x03) << 0) - -#define NUM_CS 4 - -#define set_config_field(reg, field, val) \ - do { \ - if (val != -1) { \ - reg &= ~CONFIG_##field(0xffffffff); \ - reg |= CONFIG_##field(val); \ - } \ - } while (0) - -void configure_async_emif(int cs, struct async_emif_config *cfg) -{ - unsigned long tmp; - - if (cfg->mode == ASYNC_EMIF_MODE_NAND) { - tmp = __raw_readl(ASYNC_EMIF_NAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_NAND_CONTROL); - - } else if (cfg->mode == ASYNC_EMIF_MODE_ONENAND) { - tmp = __raw_readl(ASYNC_EMIF_ONENAND_CONTROL); - tmp |= (1 << cs); - __raw_writel(tmp, ASYNC_EMIF_ONENAND_CONTROL); - } - - tmp = __raw_readl(ASYNC_EMIF_CONFIG(cs)); - - set_config_field(tmp, SELECT_STROBE, cfg->select_strobe); - set_config_field(tmp, EXTEND_WAIT, cfg->extend_wait); - set_config_field(tmp, WR_SETUP, cfg->wr_setup); - set_config_field(tmp, WR_STROBE, cfg->wr_strobe); - set_config_field(tmp, WR_HOLD, cfg->wr_hold); - set_config_field(tmp, RD_SETUP, cfg->rd_setup); - set_config_field(tmp, RD_STROBE, cfg->rd_strobe); - set_config_field(tmp, RD_HOLD, cfg->rd_hold); - set_config_field(tmp, TURN_AROUND, cfg->turn_around); - set_config_field(tmp, WIDTH, cfg->width); - - __raw_writel(tmp, ASYNC_EMIF_CONFIG(cs)); -} - -void init_async_emif(int num_cs, struct async_emif_config *config) -{ - int cs; - - clk_enable(TNETV107X_LPSC_AEMIF); - - for (cs = 0; cs < num_cs; cs++) - configure_async_emif(cs, config + cs); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/clock.c b/arch/arm/cpu/arm1176/tnetv107x/clock.c deleted file mode 100644 index 7ba28d329fa..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/clock.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * TNETV107X: Clock management APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include - -#define CLOCK_BASE TNETV107X_CLOCK_CONTROL_BASE -#define PSC_BASE TNETV107X_PSC_BASE - -#define BIT(x) (1 << (x)) - -#define MAX_PREDIV 64 -#define MAX_POSTDIV 8UL -#define MAX_MULT 512 -#define MAX_DIV (MAX_PREDIV * MAX_POSTDIV) - -/* LPSC registers */ -#define PSC_PTCMD 0x120 -#define PSC_PTSTAT 0x128 -#define PSC_MDSTAT(n) (0x800 + (n) * 4) -#define PSC_MDCTL(n) (0xA00 + (n) * 4) - -#define PSC_MDCTL_LRSTZ BIT(8) - -#define psc_reg_read(reg) __raw_readl((u32 *)(PSC_BASE + (reg))) -#define psc_reg_write(reg, val) __raw_writel(val, (u32 *)(PSC_BASE + (reg))) - -/* SSPLL registers */ -struct sspll_regs { - u32 modes; - u32 postdiv; - u32 prediv; - u32 mult_factor; - u32 divider_range; - u32 bw_divider; - u32 spr_amount; - u32 spr_rate_div; - u32 diag; -}; - -/* SSPLL base addresses */ -static struct sspll_regs *sspll_regs[] = { - (struct sspll_regs *)(CLOCK_BASE + 0x040), - (struct sspll_regs *)(CLOCK_BASE + 0x080), - (struct sspll_regs *)(CLOCK_BASE + 0x0c0), -}; - -#define sspll_reg(pll, reg) (&(sspll_regs[pll]->reg)) -#define sspll_reg_read(pll, reg) __raw_readl(sspll_reg(pll, reg)) -#define sspll_reg_write(pll, reg, val) __raw_writel(val, sspll_reg(pll, reg)) - - -/* PLL Control Registers */ -struct pllctl_regs { - u32 ctl; /* 00 */ - u32 ocsel; /* 04 */ - u32 secctl; /* 08 */ - u32 __pad0; - u32 mult; /* 10 */ - u32 prediv; /* 14 */ - u32 div1; /* 18 */ - u32 div2; /* 1c */ - u32 div3; /* 20 */ - u32 oscdiv1; /* 24 */ - u32 postdiv; /* 28 */ - u32 bpdiv; /* 2c */ - u32 wakeup; /* 30 */ - u32 __pad1; - u32 cmd; /* 38 */ - u32 stat; /* 3c */ - u32 alnctl; /* 40 */ - u32 dchange; /* 44 */ - u32 cken; /* 48 */ - u32 ckstat; /* 4c */ - u32 systat; /* 50 */ - u32 ckctl; /* 54 */ - u32 __pad2[2]; - u32 div4; /* 60 */ - u32 div5; /* 64 */ - u32 div6; /* 68 */ - u32 div7; /* 6c */ - u32 div8; /* 70 */ -}; - -struct lpsc_map { - int pll, div; -}; - -static struct pllctl_regs *pllctl_regs[] = { - (struct pllctl_regs *)(CLOCK_BASE + 0x700), - (struct pllctl_regs *)(CLOCK_BASE + 0x300), - (struct pllctl_regs *)(CLOCK_BASE + 0x500), -}; - -#define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) -#define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) -#define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) - -#define pllctl_reg_rmw(pll, reg, mask, val) \ - pllctl_reg_write(pll, reg, \ - (pllctl_reg_read(pll, reg) & ~(mask)) | val) - -#define pllctl_reg_setbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, 0, mask) - -#define pllctl_reg_clrbits(pll, reg, mask) \ - pllctl_reg_rmw(pll, reg, mask, 0) - -/* PLLCTL Bits */ -#define PLLCTL_CLKMODE BIT(8) -#define PLLCTL_PLLSELB BIT(7) -#define PLLCTL_PLLENSRC BIT(5) -#define PLLCTL_PLLDIS BIT(4) -#define PLLCTL_PLLRST BIT(3) -#define PLLCTL_PLLPWRDN BIT(1) -#define PLLCTL_PLLEN BIT(0) - -#define PLLDIV_ENABLE BIT(15) - -static int pll_div_offset[] = { -#define div_offset(reg) offsetof(struct pllctl_regs, reg) - div_offset(div1), div_offset(div2), div_offset(div3), - div_offset(div4), div_offset(div5), div_offset(div6), - div_offset(div7), div_offset(div8), -}; - -static unsigned long pll_bypass_mask[] = { 1, 4, 2 }; -static unsigned long pll_div_mask[] = { 0x01ff, 0x00ff, 0x00ff }; - -/* Mappings from PLL+DIV to subsystem clocks */ -#define sys_arm1176_clk {SYS_PLL, 0} -#define sys_dsp_clk {SYS_PLL, 1} -#define sys_ddr_clk {SYS_PLL, 2} -#define sys_full_clk {SYS_PLL, 3} -#define sys_lcd_clk {SYS_PLL, 4} -#define sys_vlynq_ref_clk {SYS_PLL, 5} -#define sys_tsc_clk {SYS_PLL, 6} -#define sys_half_clk {SYS_PLL, 7} - -#define eth_clk_5 {ETH_PLL, 0} -#define eth_clk_50 {ETH_PLL, 1} -#define eth_clk_125 {ETH_PLL, 2} -#define eth_clk_250 {ETH_PLL, 3} -#define eth_clk_25 {ETH_PLL, 4} - -#define tdm_clk {TDM_PLL, 0} -#define tdm_extra_clk {TDM_PLL, 1} -#define tdm1_clk {TDM_PLL, 2} - -static const struct lpsc_map lpsc_clk_map[] = { - [TNETV107X_LPSC_ARM] = sys_arm1176_clk, - [TNETV107X_LPSC_GEM] = sys_dsp_clk, - [TNETV107X_LPSC_DDR2_PHY] = sys_ddr_clk, - [TNETV107X_LPSC_TPCC] = sys_full_clk, - [TNETV107X_LPSC_TPTC0] = sys_full_clk, - [TNETV107X_LPSC_TPTC1] = sys_full_clk, - [TNETV107X_LPSC_RAM] = sys_full_clk, - [TNETV107X_LPSC_MBX_LITE] = sys_arm1176_clk, - [TNETV107X_LPSC_LCD] = sys_lcd_clk, - [TNETV107X_LPSC_ETHSS] = eth_clk_125, - [TNETV107X_LPSC_AEMIF] = sys_full_clk, - [TNETV107X_LPSC_CHIP_CFG] = sys_half_clk, - [TNETV107X_LPSC_TSC] = sys_tsc_clk, - [TNETV107X_LPSC_ROM] = sys_half_clk, - [TNETV107X_LPSC_UART2] = sys_half_clk, - [TNETV107X_LPSC_PKTSEC] = sys_half_clk, - [TNETV107X_LPSC_SECCTL] = sys_half_clk, - [TNETV107X_LPSC_KEYMGR] = sys_half_clk, - [TNETV107X_LPSC_KEYPAD] = sys_half_clk, - [TNETV107X_LPSC_GPIO] = sys_half_clk, - [TNETV107X_LPSC_MDIO] = sys_half_clk, - [TNETV107X_LPSC_SDIO0] = sys_half_clk, - [TNETV107X_LPSC_UART0] = sys_half_clk, - [TNETV107X_LPSC_UART1] = sys_half_clk, - [TNETV107X_LPSC_TIMER0] = sys_half_clk, - [TNETV107X_LPSC_TIMER1] = sys_half_clk, - [TNETV107X_LPSC_WDT_ARM] = sys_half_clk, - [TNETV107X_LPSC_WDT_DSP] = sys_half_clk, - [TNETV107X_LPSC_SSP] = sys_half_clk, - [TNETV107X_LPSC_TDM0] = tdm_clk, - [TNETV107X_LPSC_VLYNQ] = sys_vlynq_ref_clk, - [TNETV107X_LPSC_MCDMA] = sys_half_clk, - [TNETV107X_LPSC_USB0] = sys_half_clk, - [TNETV107X_LPSC_TDM1] = tdm1_clk, - [TNETV107X_LPSC_DEBUGSS] = sys_half_clk, - [TNETV107X_LPSC_ETHSS_RGMII] = eth_clk_250, - [TNETV107X_LPSC_SYSTEM] = sys_half_clk, - [TNETV107X_LPSC_IMCOP] = sys_dsp_clk, - [TNETV107X_LPSC_SPARE] = sys_half_clk, - [TNETV107X_LPSC_SDIO1] = sys_half_clk, - [TNETV107X_LPSC_USB1] = sys_half_clk, - [TNETV107X_LPSC_USBSS] = sys_half_clk, - [TNETV107X_LPSC_DDR2_EMIF1_VRST] = sys_ddr_clk, - [TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST] = sys_ddr_clk, -}; - -static const unsigned long pll_ext_freq[] = { - [SYS_PLL] = CONFIG_PLL_SYS_EXT_FREQ, - [ETH_PLL] = CONFIG_PLL_ETH_EXT_FREQ, - [TDM_PLL] = CONFIG_PLL_TDM_EXT_FREQ, -}; - -static unsigned long pll_freq_get(int pll) -{ - unsigned long mult = 1, prediv = 1, postdiv = 1; - unsigned long ref = CONFIG_SYS_INT_OSC_FREQ; - unsigned long ret; - u32 bypass; - - bypass = __raw_readl((u32 *)(CLOCK_BASE)); - if (!(bypass & pll_bypass_mask[pll])) { - mult = sspll_reg_read(pll, mult_factor); - prediv = sspll_reg_read(pll, prediv) + 1; - postdiv = sspll_reg_read(pll, postdiv) + 1; - } - - if (pllctl_reg_read(pll, ctl) & PLLCTL_CLKMODE) - ref = pll_ext_freq[pll]; - - if (!(pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN)) - return ref; - - ret = (unsigned long)(ref + ((unsigned long long)ref * mult) / 256); - ret /= (prediv * postdiv); - - return ret; -} - -static unsigned long __pll_div_freq_get(int pll, unsigned int fpll, - int div) -{ - int divider = 1; - unsigned long divreg; - - divreg = __raw_readl((void *)pllctl_regs[pll] + pll_div_offset[div]); - - if (divreg & PLLDIV_ENABLE) - divider = (divreg & pll_div_mask[pll]) + 1; - - return fpll / divider; -} - -static unsigned long pll_div_freq_get(int pll, int div) -{ - unsigned int fpll = pll_freq_get(pll); - - return __pll_div_freq_get(pll, fpll, div); -} - -static void __pll_div_freq_set(int pll, unsigned int fpll, int div, - unsigned long hz) -{ - int divider = (fpll / hz - 1); - - divider &= pll_div_mask[pll]; - divider |= PLLDIV_ENABLE; - - __raw_writel(divider, (void *)pllctl_regs[pll] + pll_div_offset[div]); - pllctl_reg_setbits(pll, alnctl, (1 << div)); - pllctl_reg_setbits(pll, dchange, (1 << div)); -} - -static unsigned long pll_div_freq_set(int pll, int div, unsigned long hz) -{ - unsigned int fpll = pll_freq_get(pll); - - __pll_div_freq_set(pll, fpll, div, hz); - - pllctl_reg_write(pll, cmd, 1); - - /* Wait until new divider takes effect */ - while (pllctl_reg_read(pll, stat) & 0x01); - - return __pll_div_freq_get(pll, fpll, div); -} - -unsigned long clk_get_rate(unsigned int clk) -{ - return pll_div_freq_get(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div); -} - -unsigned long clk_round_rate(unsigned int clk, unsigned long hz) -{ - unsigned long fpll, divider, pll; - - pll = lpsc_clk_map[clk].pll; - fpll = pll_freq_get(pll); - divider = (fpll / hz - 1); - divider &= pll_div_mask[pll]; - - return fpll / (divider + 1); -} - -int clk_set_rate(unsigned int clk, unsigned long _hz) -{ - unsigned long hz; - - hz = clk_round_rate(clk, _hz); - if (hz != _hz) - return -EINVAL; /* Cannot set to target freq */ - - pll_div_freq_set(lpsc_clk_map[clk].pll, lpsc_clk_map[clk].div, hz); - return 0; -} - -void lpsc_control(int mod, unsigned long state, int lrstz) -{ - u32 mdctl; - - mdctl = psc_reg_read(PSC_MDCTL(mod)); - mdctl &= ~0x1f; - mdctl |= state; - - if (lrstz == 0) - mdctl &= ~PSC_MDCTL_LRSTZ; - else if (lrstz == 1) - mdctl |= PSC_MDCTL_LRSTZ; - - psc_reg_write(PSC_MDCTL(mod), mdctl); - - psc_reg_write(PSC_PTCMD, 1); - - /* wait for power domain transition to end */ - while (psc_reg_read(PSC_PTSTAT) & 1); - - /* Wait for module state change */ - while ((psc_reg_read(PSC_MDSTAT(mod)) & 0x1f) != state); -} - -int lpsc_status(unsigned int id) -{ - return psc_reg_read(PSC_MDSTAT(id)) & 0x1f; -} - -static void init_pll(const struct pll_init_data *data) -{ - unsigned long fpll; - unsigned long best_pre = 0, best_post = 0, best_mult = 0; - unsigned long div, prediv, postdiv, mult; - unsigned long delta, actual; - long best_delta = -1; - int i; - u32 tmp; - - if (data->pll == SYS_PLL) - return; /* cannot reconfigure system pll on the fly */ - - tmp = pllctl_reg_read(data->pll, ctl); - if (data->internal_osc) { - tmp &= ~PLLCTL_CLKMODE; - fpll = CONFIG_SYS_INT_OSC_FREQ; - } else { - tmp |= PLLCTL_CLKMODE; - fpll = pll_ext_freq[data->pll]; - } - pllctl_reg_write(data->pll, ctl, tmp); - - mult = data->pll_freq / fpll; - for (mult = max(mult, 1UL); mult <= MAX_MULT; mult++) { - div = (fpll * mult) / data->pll_freq; - if (div < 1 || div > MAX_DIV) - continue; - - for (postdiv = 1; postdiv <= min(div, MAX_POSTDIV); postdiv++) { - prediv = div / postdiv; - if (prediv < 1 || prediv > MAX_PREDIV) - continue; - - actual = (fpll / prediv) * (mult / postdiv); - delta = (actual - data->pll_freq); - if (delta < 0) - delta = -delta; - if ((delta < best_delta) || (best_delta == -1)) { - best_delta = delta; - best_mult = mult; - best_pre = prediv; - best_post = postdiv; - if (delta == 0) - goto done; - } - } - } -done: - - if (best_delta == -1) { - printf("pll cannot derive %lu from %lu\n", - data->pll_freq, fpll); - return; - } - - fpll = fpll * best_mult; - fpll /= best_pre * best_post; - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN); - - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLDIS); - - sspll_reg_write(data->pll, mult_factor, (best_mult - 1) << 8); - sspll_reg_write(data->pll, prediv, best_pre - 1); - sspll_reg_write(data->pll, postdiv, best_post - 1); - - for (i = 0; i < 10; i++) - if (data->div_freq[i]) - __pll_div_freq_set(data->pll, fpll, i, - data->div_freq[i]); - - pllctl_reg_write(data->pll, cmd, 1); - - /* Wait until pll "go" operation completes */ - while (pllctl_reg_read(data->pll, stat) & 0x01); - - pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); - pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); -} - -void init_plls(int num_pll, struct pll_init_data *config) -{ - int i; - - for (i = 0; i < num_pll; i++) - init_pll(&config[i]); -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/init.c b/arch/arm/cpu/arm1176/tnetv107x/init.c deleted file mode 100644 index d8708267d7b..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/init.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * TNETV107X: Architecture initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include - -void chip_configuration_unlock(void) -{ - __raw_writel(TNETV107X_KICK0_MAGIC, TNETV107X_KICK0); - __raw_writel(TNETV107X_KICK1_MAGIC, TNETV107X_KICK1); -} - -int arch_cpu_init(void) -{ - icache_enable(); - chip_configuration_unlock(); - - return 0; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S b/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S deleted file mode 100644 index a8bce4784c9..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/lowlevel_init.S +++ /dev/null @@ -1,10 +0,0 @@ -/* - * TNETV107X: Low-level pre-relocation initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.globl lowlevel_init -lowlevel_init: - /* nothing for now, maybe needed for more exotic boot modes */ - mov pc, lr diff --git a/arch/arm/cpu/arm1176/tnetv107x/mux.c b/arch/arm/cpu/arm1176/tnetv107x/mux.c deleted file mode 100644 index 310d84dfb43..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/mux.c +++ /dev/null @@ -1,319 +0,0 @@ -/* - * TNETV107X: Pinmux configuration - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include - -#define MUX_MODE_1 0x00 -#define MUX_MODE_2 0x04 -#define MUX_MODE_3 0x0c -#define MUX_MODE_4 0x1c - -#define MUX_DEBUG 0 - -static const struct pin_config pin_table[] = { - /* reg shift mode */ - TNETV107X_MUX_CFG(0, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(0, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(1, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(2, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(3, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(4, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(4, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(5, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(6, 25, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(7, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(8, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(8, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 0, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 5, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 10, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(9, 20, MUX_MODE_4), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(10, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(11, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(11, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(12, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(13, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(14, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(15, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(15, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(16, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(16, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(17, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(18, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(19, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(19, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(20, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(20, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(21, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(22, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 20, MUX_MODE_3), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(22, 25, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(23, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(24, 25, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 0, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 5, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 10, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_3), - TNETV107X_MUX_CFG(25, 15, MUX_MODE_4), - TNETV107X_MUX_CFG(26, 0, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 5, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 10, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 15, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 20, MUX_MODE_2), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_1), - TNETV107X_MUX_CFG(26, 25, MUX_MODE_2), -}; - -const int pin_table_size = sizeof(pin_table) / sizeof(pin_table[0]); - -int mux_select_pin(short index) -{ - const struct pin_config *cfg; - unsigned long mask, mode, reg; - - if (index >= pin_table_size) - return 0; - - cfg = &pin_table[index]; - - mask = 0x1f << cfg->mask_offset; - mode = cfg->mode << cfg->mask_offset; - - reg = __raw_readl(TNETV107X_PINMUX(cfg->reg_index)); - reg = (reg & ~mask) | mode; - __raw_writel(reg, TNETV107X_PINMUX(cfg->reg_index)); - - return 1; -} - -int mux_select_pins(const short *pins) -{ - int i, ret = 1; - - for (i = 0; pins[i] >= 0; i++) - ret &= mux_select_pin(pins[i]); - - return ret; -} diff --git a/arch/arm/cpu/arm1176/tnetv107x/timer.c b/arch/arm/cpu/arm1176/tnetv107x/timer.c deleted file mode 100644 index 6e0dd0d2bd4..00000000000 --- a/arch/arm/cpu/arm1176/tnetv107x/timer.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * TNETV107X: Timer implementation - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -struct timer_regs { - u_int32_t pid12; - u_int32_t pad[3]; - u_int32_t tim12; - u_int32_t tim34; - u_int32_t prd12; - u_int32_t prd34; - u_int32_t tcr; - u_int32_t tgcr; - u_int32_t wdtcr; -}; - -#define regs ((struct timer_regs *)CONFIG_SYS_TIMERBASE) - -#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ) -#define TIM_CLK_DIV 16 - -static ulong timestamp; -static ulong lastinc; - -int timer_init(void) -{ - clk_enable(TNETV107X_LPSC_TIMER0); - - lastinc = timestamp = 0; - - /* We are using timer34 in unchained 32-bit mode, full speed */ - __raw_writel(0x0, ®s->tcr); - __raw_writel(0x0, ®s->tgcr); - __raw_writel(0x06 | ((TIM_CLK_DIV - 1) << 8), ®s->tgcr); - __raw_writel(0x0, ®s->tim34); - __raw_writel(TIMER_LOAD_VAL, ®s->prd34); - __raw_writel(2 << 22, ®s->tcr); - - return 0; -} - -static ulong get_timer_raw(void) -{ - ulong now = __raw_readl(®s->tim34); - - if (now >= lastinc) - timestamp += now - lastinc; - else - timestamp += now + TIMER_LOAD_VAL - lastinc; - - lastinc = now; - - return timestamp; -} - -ulong get_timer(ulong base) -{ - return (get_timer_raw() / (TIMER_LOAD_VAL / TIM_CLK_DIV)) - base; -} - -unsigned long long get_ticks(void) -{ - return get_timer(0); -} - -void __udelay(unsigned long usec) -{ - ulong tmo; - ulong endtime; - signed long diff; - - tmo = CONFIG_SYS_HZ_CLOCK / 1000; - tmo *= usec; - tmo /= (1000 * TIM_CLK_DIV); - - endtime = get_timer_raw() + tmo; - - do { - ulong now = get_timer_raw(); - diff = endtime - now; - } while (diff >= 0); -} - -ulong get_tbclk(void) -{ - return CONFIG_SYS_HZ; -} diff --git a/arch/arm/include/asm/arch-tnetv107x/clock.h b/arch/arm/include/asm/arch-tnetv107x/clock.h deleted file mode 100644 index dfc3b1bfa59..00000000000 --- a/arch/arm/include/asm/arch-tnetv107x/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * TNETV107X: Clock APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_CLOCK_H -#define __ASM_ARCH_CLOCK_H - -#define PSC_MDCTL_NEXT_SWRSTDISABLE 0x0 -#define PSC_MDCTL_NEXT_SYNCRST 0x1 -#define PSC_MDCTL_NEXT_DISABLE 0x2 -#define PSC_MDCTL_NEXT_ENABLE 0x3 - -#define CONFIG_SYS_INT_OSC_FREQ 24000000 - -#ifndef __ASSEMBLY__ - -/* PLL identifiers */ -enum pll_type_e { - SYS_PLL, - TDM_PLL, - ETH_PLL -}; - -/* PLL configuration data */ -struct pll_init_data { - int pll; - int internal_osc; - unsigned long pll_freq; - unsigned long div_freq[10]; -}; - -void init_plls(int num_pll, struct pll_init_data *config); -int lpsc_status(unsigned int mod); -void lpsc_control(int mod, unsigned long state, int lrstz); -unsigned long clk_get_rate(unsigned int clk); -unsigned long clk_round_rate(unsigned int clk, unsigned long hz); -int clk_set_rate(unsigned int clk, unsigned long hz); - -static inline void clk_enable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_ENABLE, -1); -} - -static inline void clk_disable(unsigned int mod) -{ - lpsc_control(mod, PSC_MDCTL_NEXT_DISABLE, -1); -} - -#endif - -#endif diff --git a/arch/arm/include/asm/arch-tnetv107x/hardware.h b/arch/arm/include/asm/arch-tnetv107x/hardware.h deleted file mode 100644 index d458e0bdf09..00000000000 --- a/arch/arm/include/asm/arch-tnetv107x/hardware.h +++ /dev/null @@ -1,160 +0,0 @@ -/* - * TNETV107X: Hardware information - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_HARDWARE_H -#define __ASM_ARCH_HARDWARE_H - -#ifndef __ASSEMBLY__ - -#include - -#define ASYNC_EMIF_NUM_CS 4 -#define ASYNC_EMIF_MODE_NOR 0 -#define ASYNC_EMIF_MODE_NAND 1 -#define ASYNC_EMIF_MODE_ONENAND 2 -#define ASYNC_EMIF_PRESERVE -1 - -struct async_emif_config { - unsigned mode; - unsigned select_strobe; - unsigned extend_wait; - unsigned wr_setup; - unsigned wr_strobe; - unsigned wr_hold; - unsigned rd_setup; - unsigned rd_strobe; - unsigned rd_hold; - unsigned turn_around; - enum { - ASYNC_EMIF_8 = 0, - ASYNC_EMIF_16 = 1, - ASYNC_EMIF_32 = 2, - } width; -}; - -void init_async_emif(int num_cs, struct async_emif_config *config); - -int wdt_start(unsigned long msecs); -int wdt_stop(void); -int wdt_kick(void); - -#endif - -/* Chip configuration unlock codes and registers */ -#define TNETV107X_KICK0 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x38) -#define TNETV107X_KICK1 (TNETV107X_CHIP_CONFIG_SYS_BASE+0x3c) -#define TNETV107X_PINMUX(n) (TNETV107X_CHIP_CONFIG_SYS_BASE+0x150+(n)*4) -#define TNETV107X_KICK0_MAGIC 0x83e70b13 -#define TNETV107X_KICK1_MAGIC 0x95a4f1e0 - -/* Module base addresses */ -#define TNETV107X_TPCC_BASE 0x01C00000 -#define TNETV107X_TPTC0_BASE 0x01C10000 -#define TNETV107X_TPTC1_BASE 0x01C10400 -#define TNETV107X_INTC_BASE 0x03000000 -#define TNETV107X_LCD_CONTROLLER_BASE 0x08030000 -#define TNETV107X_INTD_BASE 0x08038000 -#define TNETV107X_INTD_IPC_BASE 0x08038000 -#define TNETV107X_INTD_FAST_BASE 0x08039000 -#define TNETV107X_INTD_ASYNC_BASE 0x0803A000 -#define TNETV107X_INTD_SLOW_BASE 0x0803B000 -#define TNETV107X_PKA_BASE 0x08040000 -#define TNETV107X_RNG_BASE 0x08044000 -#define TNETV107X_TIMER0_BASE 0x08086500 -#define TNETV107X_TIMER1_BASE 0x08086600 -#define TNETV107X_WDT0_ARM_BASE 0x08086700 -#define TNETV107X_WDT1_DSP_BASE 0x08086800 -#define TNETV107X_CHIP_CONFIG_SYS_BASE 0x08087000 -#define TNETV107X_GPIO_BASE 0x08088000 -#define TNETV107X_UART1_BASE 0x08088400 -#define TNETV107X_TOUCHSCREEN_BASE 0x08088500 -#define TNETV107X_SDIO0_BASE 0x08088700 -#define TNETV107X_SDIO1_BASE 0x08088800 -#define TNETV107X_MDIO_BASE 0x08088900 -#define TNETV107X_KEYPAD_BASE 0x08088A00 -#define TNETV107X_SSP_BASE 0x08088C00 -#define TNETV107X_CLOCK_CONTROL_BASE 0x0808A000 -#define TNETV107X_PSC_BASE 0x0808B000 -#define TNETV107X_TDM0_BASE 0x08100000 -#define TNETV107X_TDM1_BASE 0x08100100 -#define TNETV107X_MCDMA_BASE 0x08108000 -#define TNETV107X_UART0_DMA_BASE 0x08108200 -#define TNETV107X_USBSS_BASE 0x08120000 -#define TNETV107X_VLYNQ_CONTROL_BASE 0x0810D000 -#define TNETV107X_ASYNC_EMIF_CNTRL_BASE 0x08200000 -#define TNETV107X_VLYNQ_MEM_MAP_BASE 0x0C000000 -#define TNETV107X_IMCOP_BASE 0x01CC0000 -#define TNETV107X_MBX_LITE_BASE 0x07000000 -#define TNETV107X_ETHSS_BASE 0x0803C000 -#define TNETV107X_CPSW_BASE 0x0803C000 -#define TNETV107X_SPF_BASE 0x0803C800 -#define TNETV107X_IOPU_ETHSS_BASE 0x0803D000 -#define TNETV107X_VTP_CNTRL_0 0x0803D800 -#define TNETV107X_VTP_CNTRL_1 0x0803D900 -#define TNETV107X_UART2_DMA_BASE 0x08108400 -#define TNETV107X_INTERNAL_MEMORY 0x20000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE0_BASE 0x30000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE1_BASE 0x40000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE2_BASE 0x44000000 -#define TNETV107X_ASYNC_EMIF_DATA_CE3_BASE 0x48000000 -#define TNETV107X_DDR_EMIF_DATA_BASE 0x80000000 -#define TNETV107X_DDR_EMIF_CONTROL_BASE 0x90000000 - -/* LPSC module definitions */ -#define TNETV107X_LPSC_ARM 0 -#define TNETV107X_LPSC_GEM 1 -#define TNETV107X_LPSC_DDR2_PHY 2 -#define TNETV107X_LPSC_TPCC 3 -#define TNETV107X_LPSC_TPTC0 4 -#define TNETV107X_LPSC_TPTC1 5 -#define TNETV107X_LPSC_RAM 6 -#define TNETV107X_LPSC_MBX_LITE 7 -#define TNETV107X_LPSC_LCD 8 -#define TNETV107X_LPSC_ETHSS 9 -#define TNETV107X_LPSC_AEMIF 10 -#define TNETV107X_LPSC_CHIP_CFG 11 -#define TNETV107X_LPSC_TSC 12 -#define TNETV107X_LPSC_ROM 13 -#define TNETV107X_LPSC_UART2 14 -#define TNETV107X_LPSC_PKTSEC 15 -#define TNETV107X_LPSC_SECCTL 16 -#define TNETV107X_LPSC_KEYMGR 17 -#define TNETV107X_LPSC_KEYPAD 18 -#define TNETV107X_LPSC_GPIO 19 -#define TNETV107X_LPSC_MDIO 20 -#define TNETV107X_LPSC_SDIO0 21 -#define TNETV107X_LPSC_UART0 22 -#define TNETV107X_LPSC_UART1 23 -#define TNETV107X_LPSC_TIMER0 24 -#define TNETV107X_LPSC_TIMER1 25 -#define TNETV107X_LPSC_WDT_ARM 26 -#define TNETV107X_LPSC_WDT_DSP 27 -#define TNETV107X_LPSC_SSP 28 -#define TNETV107X_LPSC_TDM0 29 -#define TNETV107X_LPSC_VLYNQ 30 -#define TNETV107X_LPSC_MCDMA 31 -#define TNETV107X_LPSC_USB0 32 -#define TNETV107X_LPSC_TDM1 33 -#define TNETV107X_LPSC_DEBUGSS 34 -#define TNETV107X_LPSC_ETHSS_RGMII 35 -#define TNETV107X_LPSC_SYSTEM 36 -#define TNETV107X_LPSC_IMCOP 37 -#define TNETV107X_LPSC_SPARE 38 -#define TNETV107X_LPSC_SDIO1 39 -#define TNETV107X_LPSC_USB1 40 -#define TNETV107X_LPSC_USBSS 41 -#define TNETV107X_LPSC_DDR2_EMIF1_VRST 42 -#define TNETV107X_LPSC_DDR2_EMIF2_VCTL_RST 43 -#define TNETV107X_LPSC_MAX 44 - -/* Interrupt controller */ -#define INTC_GLB_EN (TNETV107X_INTC_BASE + 0x10) -#define INTC_HINT_EN (TNETV107X_INTC_BASE + 0x1500) -#define INTC_EN_CLR0 (TNETV107X_INTC_BASE + 0x380) - -#define DAVINCI_ASYNC_EMIF_CNTRL_BASE TNETV107X_ASYNC_EMIF_CNTRL_BASE - -#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-tnetv107x/mux.h b/arch/arm/include/asm/arch-tnetv107x/mux.h deleted file mode 100644 index 3f832c4147c..00000000000 --- a/arch/arm/include/asm/arch-tnetv107x/mux.h +++ /dev/null @@ -1,291 +0,0 @@ -/* - * TNETV107X: Pinmux APIs - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __ASM_ARCH_MUX_H -#define __ASM_ARCH_MUX_H - -struct pin_config { - unsigned char reg_index; - unsigned char mask_offset; - unsigned char mode; -}; - -#define TNETV107X_MUX_CFG(reg, offset, mux_mode) \ - { reg, offset, mux_mode } - -int mux_select_pin(short index); -int mux_select_pins(const short *pins); - -enum tnetv107x_pin_mux_index { - TNETV107X_PIN_ASR_A00, - TNETV107X_PIN_GPIO32, - TNETV107X_PIN_ASR_A01, - TNETV107X_PIN_GPIO33, - TNETV107X_PIN_ASR_A02, - TNETV107X_PIN_GPIO34, - TNETV107X_PIN_ASR_A03, - TNETV107X_PIN_GPIO35, - TNETV107X_PIN_ASR_A04, - TNETV107X_PIN_GPIO36, - TNETV107X_PIN_ASR_A05, - TNETV107X_PIN_GPIO37, - TNETV107X_PIN_ASR_A06, - TNETV107X_PIN_GPIO38, - TNETV107X_PIN_ASR_A07, - TNETV107X_PIN_GPIO39, - TNETV107X_PIN_ASR_A08, - TNETV107X_PIN_GPIO40, - TNETV107X_PIN_ASR_A09, - TNETV107X_PIN_GPIO41, - TNETV107X_PIN_ASR_A10, - TNETV107X_PIN_GPIO42, - TNETV107X_PIN_ASR_A11, - TNETV107X_PIN_BOOT_STRP_0, - TNETV107X_PIN_ASR_A12, - TNETV107X_PIN_BOOT_STRP_1, - TNETV107X_PIN_ASR_A13, - TNETV107X_PIN_GPIO43, - TNETV107X_PIN_ASR_A14, - TNETV107X_PIN_GPIO44, - TNETV107X_PIN_ASR_A15, - TNETV107X_PIN_GPIO45, - TNETV107X_PIN_ASR_A16, - TNETV107X_PIN_GPIO46, - TNETV107X_PIN_ASR_A17, - TNETV107X_PIN_GPIO47, - TNETV107X_PIN_ASR_A18, - TNETV107X_PIN_GPIO48, - TNETV107X_PIN_SDIO1_DATA3_0, - TNETV107X_PIN_ASR_A19, - TNETV107X_PIN_GPIO49, - TNETV107X_PIN_SDIO1_DATA2_0, - TNETV107X_PIN_ASR_A20, - TNETV107X_PIN_GPIO50, - TNETV107X_PIN_SDIO1_DATA1_0, - TNETV107X_PIN_ASR_A21, - TNETV107X_PIN_GPIO51, - TNETV107X_PIN_SDIO1_DATA0_0, - TNETV107X_PIN_ASR_A22, - TNETV107X_PIN_GPIO52, - TNETV107X_PIN_SDIO1_CMD_0, - TNETV107X_PIN_ASR_A23, - TNETV107X_PIN_GPIO53, - TNETV107X_PIN_SDIO1_CLK_0, - TNETV107X_PIN_ASR_BA_1, - TNETV107X_PIN_GPIO54, - TNETV107X_PIN_SYS_PLL_CLK, - TNETV107X_PIN_ASR_CS0, - TNETV107X_PIN_ASR_CS1, - TNETV107X_PIN_ASR_CS2, - TNETV107X_PIN_TDM_PLL_CLK, - TNETV107X_PIN_ASR_CS3, - TNETV107X_PIN_ETH_PHY_CLK, - TNETV107X_PIN_ASR_D00, - TNETV107X_PIN_GPIO55, - TNETV107X_PIN_ASR_D01, - TNETV107X_PIN_GPIO56, - TNETV107X_PIN_ASR_D02, - TNETV107X_PIN_GPIO57, - TNETV107X_PIN_ASR_D03, - TNETV107X_PIN_GPIO58, - TNETV107X_PIN_ASR_D04, - TNETV107X_PIN_GPIO59_0, - TNETV107X_PIN_ASR_D05, - TNETV107X_PIN_GPIO60_0, - TNETV107X_PIN_ASR_D06, - TNETV107X_PIN_GPIO61_0, - TNETV107X_PIN_ASR_D07, - TNETV107X_PIN_GPIO62_0, - TNETV107X_PIN_ASR_D08, - TNETV107X_PIN_GPIO63_0, - TNETV107X_PIN_ASR_D09, - TNETV107X_PIN_GPIO64_0, - TNETV107X_PIN_ASR_D10, - TNETV107X_PIN_SDIO1_DATA3_1, - TNETV107X_PIN_ASR_D11, - TNETV107X_PIN_SDIO1_DATA2_1, - TNETV107X_PIN_ASR_D12, - TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_ASR_D13, - TNETV107X_PIN_SDIO1_DATA0_1, - TNETV107X_PIN_ASR_D14, - TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_ASR_D15, - TNETV107X_PIN_SDIO1_CLK_1, - TNETV107X_PIN_ASR_OE, - TNETV107X_PIN_BOOT_STRP_2, - TNETV107X_PIN_ASR_RNW, - TNETV107X_PIN_GPIO29_0, - TNETV107X_PIN_ASR_WAIT, - TNETV107X_PIN_GPIO30_0, - TNETV107X_PIN_ASR_WE, - TNETV107X_PIN_BOOT_STRP_3, - TNETV107X_PIN_ASR_WE_DQM0, - TNETV107X_PIN_GPIO31, - TNETV107X_PIN_LCD_PD17_0, - TNETV107X_PIN_ASR_WE_DQM1, - TNETV107X_PIN_ASR_BA0_0, - TNETV107X_PIN_VLYNQ_CLK, - TNETV107X_PIN_GPIO14, - TNETV107X_PIN_LCD_PD19_0, - TNETV107X_PIN_VLYNQ_RXD0, - TNETV107X_PIN_GPIO15, - TNETV107X_PIN_LCD_PD20_0, - TNETV107X_PIN_VLYNQ_RXD1, - TNETV107X_PIN_GPIO16, - TNETV107X_PIN_LCD_PD21_0, - TNETV107X_PIN_VLYNQ_TXD0, - TNETV107X_PIN_GPIO17, - TNETV107X_PIN_LCD_PD22_0, - TNETV107X_PIN_VLYNQ_TXD1, - TNETV107X_PIN_GPIO18, - TNETV107X_PIN_LCD_PD23_0, - TNETV107X_PIN_SDIO0_CLK, - TNETV107X_PIN_GPIO19, - TNETV107X_PIN_SDIO0_CMD, - TNETV107X_PIN_GPIO20, - TNETV107X_PIN_SDIO0_DATA0, - TNETV107X_PIN_GPIO21, - TNETV107X_PIN_SDIO0_DATA1, - TNETV107X_PIN_GPIO22, - TNETV107X_PIN_SDIO0_DATA2, - TNETV107X_PIN_GPIO23, - TNETV107X_PIN_SDIO0_DATA3, - TNETV107X_PIN_GPIO24, - TNETV107X_PIN_EMU0, - TNETV107X_PIN_EMU1, - TNETV107X_PIN_RTCK, - TNETV107X_PIN_TRST_N, - TNETV107X_PIN_TCK, - TNETV107X_PIN_TDI, - TNETV107X_PIN_TDO, - TNETV107X_PIN_TMS, - TNETV107X_PIN_TDM1_CLK, - TNETV107X_PIN_TDM1_RX, - TNETV107X_PIN_TDM1_TX, - TNETV107X_PIN_TDM1_FS, - TNETV107X_PIN_KEYPAD_R0, - TNETV107X_PIN_KEYPAD_R1, - TNETV107X_PIN_KEYPAD_R2, - TNETV107X_PIN_KEYPAD_R3, - TNETV107X_PIN_KEYPAD_R4, - TNETV107X_PIN_KEYPAD_R5, - TNETV107X_PIN_KEYPAD_R6, - TNETV107X_PIN_GPIO12, - TNETV107X_PIN_KEYPAD_R7, - TNETV107X_PIN_GPIO10, - TNETV107X_PIN_KEYPAD_C0, - TNETV107X_PIN_KEYPAD_C1, - TNETV107X_PIN_KEYPAD_C2, - TNETV107X_PIN_KEYPAD_C3, - TNETV107X_PIN_KEYPAD_C4, - TNETV107X_PIN_KEYPAD_C5, - TNETV107X_PIN_KEYPAD_C6, - TNETV107X_PIN_GPIO13, - TNETV107X_PIN_TEST_CLK_IN, - TNETV107X_PIN_KEYPAD_C7, - TNETV107X_PIN_GPIO11, - TNETV107X_PIN_SSP0_0, - TNETV107X_PIN_SCC_DCLK, - TNETV107X_PIN_LCD_PD20_1, - TNETV107X_PIN_SSP0_1, - TNETV107X_PIN_SCC_CS_N, - TNETV107X_PIN_LCD_PD21_1, - TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SCC_D, - TNETV107X_PIN_LCD_PD22_1, - TNETV107X_PIN_SSP0_3, - TNETV107X_PIN_SCC_RESETN, - TNETV107X_PIN_LCD_PD23_1, - TNETV107X_PIN_SSP1_0, - TNETV107X_PIN_GPIO25, - TNETV107X_PIN_UART2_CTS, - TNETV107X_PIN_SSP1_1, - TNETV107X_PIN_GPIO26, - TNETV107X_PIN_UART2_RD, - TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_GPIO27, - TNETV107X_PIN_UART2_RTS, - TNETV107X_PIN_SSP1_3, - TNETV107X_PIN_GPIO28, - TNETV107X_PIN_UART2_TD, - TNETV107X_PIN_UART0_CTS, - TNETV107X_PIN_UART0_RD, - TNETV107X_PIN_UART0_RTS, - TNETV107X_PIN_UART0_TD, - TNETV107X_PIN_UART1_RD, - TNETV107X_PIN_UART1_TD, - TNETV107X_PIN_LCD_AC_NCS, - TNETV107X_PIN_LCD_HSYNC_RNW, - TNETV107X_PIN_LCD_VSYNC_A0, - TNETV107X_PIN_LCD_MCLK, - TNETV107X_PIN_LCD_PD16_0, - TNETV107X_PIN_LCD_PCLK_E, - TNETV107X_PIN_LCD_PD00, - TNETV107X_PIN_LCD_PD01, - TNETV107X_PIN_LCD_PD02, - TNETV107X_PIN_LCD_PD03, - TNETV107X_PIN_LCD_PD04, - TNETV107X_PIN_LCD_PD05, - TNETV107X_PIN_LCD_PD06, - TNETV107X_PIN_LCD_PD07, - TNETV107X_PIN_LCD_PD08, - TNETV107X_PIN_GPIO59_1, - TNETV107X_PIN_LCD_PD09, - TNETV107X_PIN_GPIO60_1, - TNETV107X_PIN_LCD_PD10, - TNETV107X_PIN_ASR_BA0_1, - TNETV107X_PIN_GPIO61_1, - TNETV107X_PIN_LCD_PD11, - TNETV107X_PIN_GPIO62_1, - TNETV107X_PIN_LCD_PD12, - TNETV107X_PIN_GPIO63_1, - TNETV107X_PIN_LCD_PD13, - TNETV107X_PIN_GPIO64_1, - TNETV107X_PIN_LCD_PD14, - TNETV107X_PIN_GPIO29_1, - TNETV107X_PIN_LCD_PD15, - TNETV107X_PIN_GPIO30_1, - TNETV107X_PIN_EINT0, - TNETV107X_PIN_GPIO08, - TNETV107X_PIN_EINT1, - TNETV107X_PIN_GPIO09, - TNETV107X_PIN_GPIO00, - TNETV107X_PIN_LCD_PD20_2, - TNETV107X_PIN_TDM_CLK_IN_2, - TNETV107X_PIN_GPIO01, - TNETV107X_PIN_LCD_PD21_2, - TNETV107X_PIN_24M_CLK_OUT_1, - TNETV107X_PIN_GPIO02, - TNETV107X_PIN_LCD_PD22_2, - TNETV107X_PIN_GPIO03, - TNETV107X_PIN_LCD_PD23_2, - TNETV107X_PIN_GPIO04, - TNETV107X_PIN_LCD_PD16_1, - TNETV107X_PIN_USB0_RXERR, - TNETV107X_PIN_GPIO05, - TNETV107X_PIN_LCD_PD17_1, - TNETV107X_PIN_TDM_CLK_IN_1, - TNETV107X_PIN_GPIO06, - TNETV107X_PIN_LCD_PD18, - TNETV107X_PIN_24M_CLK_OUT_2, - TNETV107X_PIN_GPIO07, - TNETV107X_PIN_LCD_PD19_1, - TNETV107X_PIN_USB1_RXERR, - TNETV107X_PIN_ETH_PLL_CLK, - TNETV107X_PIN_MDIO, - TNETV107X_PIN_MDC, - TNETV107X_PIN_AIC_MUTE_STAT_N, - TNETV107X_PIN_TDM0_CLK, - TNETV107X_PIN_AIC_HNS_EN_N, - TNETV107X_PIN_TDM0_FS, - TNETV107X_PIN_AIC_HDS_EN_STAT_N, - TNETV107X_PIN_TDM0_TX, - TNETV107X_PIN_AIC_HNF_EN_STAT_N, - TNETV107X_PIN_TDM0_RX, -}; - -#endif diff --git a/board/ti/tnetv107xevm/Kconfig b/board/ti/tnetv107xevm/Kconfig deleted file mode 100644 index 637f20e847e..00000000000 --- a/board/ti/tnetv107xevm/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TNETV107X_EVM - -config SYS_BOARD - default "tnetv107xevm" - -config SYS_VENDOR - default "ti" - -config SYS_SOC - default "tnetv107x" - -config SYS_CONFIG_NAME - default "tnetv107x_evm" - -endif diff --git a/board/ti/tnetv107xevm/MAINTAINERS b/board/ti/tnetv107xevm/MAINTAINERS deleted file mode 100644 index 8a92c6bf874..00000000000 --- a/board/ti/tnetv107xevm/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TNETV107XEVM BOARD -#M: Chan-Taek Park -S: Orphan (since 2014-06) -F: board/ti/tnetv107xevm/ -F: include/configs/tnetv107x_evm.h -F: configs/tnetv107x_evm_defconfig diff --git a/board/ti/tnetv107xevm/Makefile b/board/ti/tnetv107xevm/Makefile deleted file mode 100644 index 0a6128f85f7..00000000000 --- a/board/ti/tnetv107xevm/Makefile +++ /dev/null @@ -1,5 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y += sdb_board.o diff --git a/board/ti/tnetv107xevm/config.mk b/board/ti/tnetv107xevm/config.mk deleted file mode 100644 index 51c2886b345..00000000000 --- a/board/ti/tnetv107xevm/config.mk +++ /dev/null @@ -1,5 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -CONFIG_SYS_TEXT_BASE = 0x83FC0000 diff --git a/board/ti/tnetv107xevm/sdb_board.c b/board/ti/tnetv107xevm/sdb_board.c deleted file mode 100644 index a84ec84baeb..00000000000 --- a/board/ti/tnetv107xevm/sdb_board.c +++ /dev/null @@ -1,134 +0,0 @@ -/* - * TNETV107X-EVM: Board initialization - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -static struct async_emif_config async_emif_config[ASYNC_EMIF_NUM_CS] = { - { /* CS0 */ - .mode = ASYNC_EMIF_MODE_NAND, - .wr_setup = 5, - .wr_strobe = 5, - .wr_hold = 2, - .rd_setup = 5, - .rd_strobe = 5, - .rd_hold = 2, - .turn_around = 5, - .width = ASYNC_EMIF_8, - }, - { /* CS1 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 2, - .wr_strobe = 27, - .wr_hold = 4, - .rd_setup = 2, - .rd_strobe = 27, - .rd_hold = 4, - .turn_around = 2, - .width = ASYNC_EMIF_PRESERVE, - }, - { /* CS2 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 2, - .wr_strobe = 27, - .wr_hold = 4, - .rd_setup = 2, - .rd_strobe = 27, - .rd_hold = 4, - .turn_around = 2, - .width = ASYNC_EMIF_PRESERVE, - }, - { /* CS3 */ - .mode = ASYNC_EMIF_MODE_NOR, - .wr_setup = 1, - .wr_strobe = 90, - .wr_hold = 3, - .rd_setup = 1, - .rd_strobe = 26, - .rd_hold = 3, - .turn_around = 1, - .width = ASYNC_EMIF_8, - }, -}; - -static struct pll_init_data pll_config[] = { - { - .pll = ETH_PLL, - .internal_osc = 1, - .pll_freq = 500000000, - .div_freq = { - 5000000, 50000000, 125000000, 250000000, 25000000, - }, - }, -}; - -static const short sdio1_pins[] = { - TNETV107X_PIN_SDIO1_CLK_1, TNETV107X_PIN_SDIO1_CMD_1, - TNETV107X_PIN_SDIO1_DATA0_1, TNETV107X_PIN_SDIO1_DATA1_1, - TNETV107X_PIN_SDIO1_DATA2_1, TNETV107X_PIN_SDIO1_DATA3_1, - -1 -}; - -static const short uart1_pins[] = { - TNETV107X_PIN_UART1_RD, TNETV107X_PIN_UART1_TD, -1 -}; - -static const short ssp_pins[] = { - TNETV107X_PIN_SSP0_0, TNETV107X_PIN_SSP0_1, TNETV107X_PIN_SSP0_2, - TNETV107X_PIN_SSP1_0, TNETV107X_PIN_SSP1_1, TNETV107X_PIN_SSP1_2, - TNETV107X_PIN_SSP1_3, -1 -}; - -int board_init(void) -{ -#ifndef CONFIG_USE_IRQ - __raw_writel(0, INTC_GLB_EN); /* Global disable */ - __raw_writel(0, INTC_HINT_EN); /* Disable host ints */ - __raw_writel(0, INTC_EN_CLR0 + 0); /* Clear enable */ - __raw_writel(0, INTC_EN_CLR0 + 4); /* Clear enable */ - __raw_writel(0, INTC_EN_CLR0 + 8); /* Clear enable */ -#endif - - gd->bd->bi_arch_number = MACH_TYPE_TNETV107X; - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - init_plls(ARRAY_SIZE(pll_config), pll_config); - - init_async_emif(ARRAY_SIZE(async_emif_config), async_emif_config); - - mux_select_pin(TNETV107X_PIN_ASR_CS3); - mux_select_pins(sdio1_pins); - mux_select_pins(uart1_pins); - mux_select_pins(ssp_pins); - - return 0; -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -#ifdef CONFIG_NAND_DAVINCI -int board_nand_init(struct nand_chip *nand) -{ - davinci_nand_init(nand); - - return 0; -} -#endif diff --git a/configs/tnetv107x_evm_defconfig b/configs/tnetv107x_evm_defconfig deleted file mode 100644 index b0915d2026e..00000000000 --- a/configs/tnetv107x_evm_defconfig +++ /dev/null @@ -1,2 +0,0 @@ -CONFIG_ARM=y -CONFIG_TARGET_TNETV107X_EVM=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 1528b9b9283..766d7123e53 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +tnetv107x arm arm1176 - - Chan-Taek Park a320evb arm arm920t - - Po-Yu Chuang cm4008 arm arm920t - - Greg Ungerer cm41xx arm arm920t - - diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 1dc0f5aa101..482a4bd5be3 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -10,7 +10,6 @@ obj-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o ifneq (,$(filter $(SOC), mx31 mx35 mx5 mx6 vf610 ls102xa)) obj-y += imx_watchdog.o endif -obj-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o obj-$(CONFIG_S5P) += s5p_wdt.o obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o diff --git a/drivers/watchdog/tnetv107x_wdt.c b/drivers/watchdog/tnetv107x_wdt.c deleted file mode 100644 index 3d3f366c021..00000000000 --- a/drivers/watchdog/tnetv107x_wdt.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * TNETV107X: Watchdog timer implementation (for reset) - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include -#include -#include - -#define MAX_DIV 0xFFFE0001 - -struct wdt_regs { - u32 kick_lock; -#define KICK_LOCK_1 0x5555 -#define KICK_LOCK_2 0xaaaa - u32 kick; - - u32 change_lock; -#define CHANGE_LOCK_1 0x6666 -#define CHANGE_LOCK_2 0xbbbb - u32 change; - - u32 disable_lock; -#define DISABLE_LOCK_1 0x7777 -#define DISABLE_LOCK_2 0xcccc -#define DISABLE_LOCK_3 0xdddd - u32 disable; - - u32 prescale_lock; -#define PRESCALE_LOCK_1 0x5a5a -#define PRESCALE_LOCK_2 0xa5a5 - u32 prescale; -}; - -static struct wdt_regs* regs = (struct wdt_regs *)TNETV107X_WDT0_ARM_BASE; - -#define wdt_reg_read(reg) __raw_readl(®s->reg) -#define wdt_reg_write(reg, val) __raw_writel((val), ®s->reg) - -static int write_prescale_reg(unsigned long prescale_value) -{ - wdt_reg_write(prescale_lock, PRESCALE_LOCK_1); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(prescale_lock, PRESCALE_LOCK_2); - if ((wdt_reg_read(prescale_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(prescale, prescale_value); - - return 0; -} - -static int write_change_reg(unsigned long initial_timer_value) -{ - wdt_reg_write(change_lock, CHANGE_LOCK_1); - if ((wdt_reg_read(change_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(change_lock, CHANGE_LOCK_2); - if ((wdt_reg_read(change_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(change, initial_timer_value); - - return 0; -} - -static int wdt_control(unsigned long disable_value) -{ - wdt_reg_write(disable_lock, DISABLE_LOCK_1); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_2); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x2) - return -1; - - wdt_reg_write(disable_lock, DISABLE_LOCK_3); - if ((wdt_reg_read(disable_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(disable, disable_value); - return 0; -} - -static int wdt_set_period(unsigned long msec) -{ - unsigned long change_value, count_value; - unsigned long prescale_value = 1; - unsigned long refclk_khz, maxdiv; - int ret; - - refclk_khz = clk_get_rate(TNETV107X_LPSC_WDT_ARM); - maxdiv = (MAX_DIV / refclk_khz); - - if ((!msec) || (msec > maxdiv)) - return -1; - - count_value = refclk_khz * msec; - if (count_value > 0xffff) { - change_value = count_value / 0xffff + 1; - prescale_value = count_value / change_value; - } else { - change_value = count_value; - } - - ret = write_prescale_reg(prescale_value - 1); - if (ret) - return ret; - - ret = write_change_reg(change_value); - if (ret) - return ret; - - return 0; -} - -unsigned long last_wdt = -1; - -int wdt_start(unsigned long msecs) -{ - int ret; - ret = wdt_control(0); - if (ret) - return ret; - ret = wdt_set_period(msecs); - if (ret) - return ret; - ret = wdt_control(1); - if (ret) - return ret; - ret = wdt_kick(); - last_wdt = msecs; - return ret; -} - -int wdt_stop(void) -{ - last_wdt = -1; - return wdt_control(0); -} - -int wdt_kick(void) -{ - wdt_reg_write(kick_lock, KICK_LOCK_1); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x1) - return -1; - - wdt_reg_write(kick_lock, KICK_LOCK_2); - if ((wdt_reg_read(kick_lock) & 0x3) != 0x3) - return -1; - - wdt_reg_write(kick, 1); - return 0; -} - -void reset_cpu(ulong addr) -{ - clk_enable(TNETV107X_LPSC_WDT_ARM); - wdt_start(1); - wdt_kick(); -} diff --git a/include/configs/tnetv107x_evm.h b/include/configs/tnetv107x_evm.h deleted file mode 100644 index 00a1a9e0026..00000000000 --- a/include/configs/tnetv107x_evm.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2008 Texas Instruments, Inc - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include -#include - -/* Architecture, CPU, etc */ -#define CONFIG_TNETV107X -#define CONFIG_TNETV107X_EVM -#define CONFIG_TNETV107X_WATCHDOG -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_DISABLE_TCM -#define CONFIG_PERIPORT_REMAP -#define CONFIG_PERIPORT_BASE 0x2000000 -#define CONFIG_PERIPORT_SIZE 0x10 -#define CONFIG_SYS_CLK_FREQ clk_get_rate(TNETV107X_LPSC_ARM) - -#define CONFIG_SYS_TIMERBASE TNETV107X_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get_rate(TNETV107X_LPSC_TIMER0) - -#define CONFIG_PLL_SYS_EXT_FREQ 25000000 -#define CONFIG_PLL_TDM_EXT_FREQ 19200000 -#define CONFIG_PLL_ETH_EXT_FREQ 25000000 - -/* Memory Info */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) -#define PHYS_SDRAM_1 TNETV107X_DDR_EMIF_DATA_BASE -#define PHYS_SDRAM_1_SIZE 0x04000000 -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Serial Driver Info */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 TNETV107X_UART1_BASE -#define CONFIG_SYS_NS16550_CLK clk_get_rate(TNETV107X_LPSC_UART1) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* Flash and environment info */ -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_NAND_DAVINCI -#define CONFIG_ENV_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_NAND_1BIT_ECC -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_SYS_NAND_BASE TNETV107X_ASYNC_EMIF_DATA_CE0_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_PARTITIONS -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE -#define CONFIG_JFFS2_NAND -#define CONFIG_ENV_OFFSET 0x180000 - -/* - * davinci_nand is a bit of a misnomer since this particular EMIF block is - * commonly used across multiple TI devices. Unfortunately, this misnomer - * (amongst others) carries forward into the kernel too. Consequently, if we - * use a different device name here, the mtdparts variable won't be usable as - * a kernel command-line argument. - */ -#define MTDIDS_DEFAULT "nand0=davinci_nand.0" -#define MTDPARTS_DEFAULT "mtdparts=davinci_nand.0:" \ - "1536k(uboot)ro," \ - "128k(params)ro," \ - "4m(kernel)," \ - "-(filesystem)" - -/* General U-Boot configuration */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_SYS_PROMPT "U-Boot > " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + \ - 0x700000) -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS "mem=32M console=ttyS1,115200n8 " \ - "root=/dev/mmcblk0p1 rw noinitrd" -#define CONFIG_BOOTCOMMAND "" -#define CONFIG_BOOTDELAY 1 - -#define CONFIG_CMD_BDI -#define CONFIG_CMD_BOOTD -#define CONFIG_CMD_CONSOLE -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EDITENV -#define CONFIG_CMD_IMI -#define CONFIG_CMD_ITEST -#define CONFIG_CMD_LOADB -#define CONFIG_CMD_LOADS -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC -#define CONFIG_CMD_RUN -#define CONFIG_CMD_SAVEENV -#define CONFIG_CMD_SOURCE -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_NAND -#define CONFIG_CMD_JFFS2 - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From cb957cda2bedc31209f5c483cacb5ddc4f5754c8 Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Tue, 24 Feb 2015 11:45:10 +0900 Subject: ARM: davinci: remove hawkboard support This is still a non-generic board. Signed-off-by: Masahiro Yamada Acked-by: Sughosh Ganu Cc: Syed Mohammed Khasim Acked-by: Marek Vasut --- arch/arm/mach-davinci/Kconfig | 4 - board/davinci/da8xxevm/Kconfig | 13 -- board/davinci/da8xxevm/MAINTAINERS | 8 - board/davinci/da8xxevm/Makefile | 1 - board/davinci/da8xxevm/README.hawkboard | 92 ----------- board/davinci/da8xxevm/hawkboard-ais-nand.cfg | 4 - board/davinci/da8xxevm/hawkboard.c | 120 -------------- board/davinci/da8xxevm/u-boot-spl-hawk.lds | 69 -------- configs/hawkboard_defconfig | 4 - configs/hawkboard_uart_defconfig | 5 - doc/README.scrapyard | 1 + include/configs/hawkboard.h | 220 -------------------------- 12 files changed, 1 insertion(+), 540 deletions(-) delete mode 100644 board/davinci/da8xxevm/README.hawkboard delete mode 100644 board/davinci/da8xxevm/hawkboard-ais-nand.cfg delete mode 100644 board/davinci/da8xxevm/hawkboard.c delete mode 100644 board/davinci/da8xxevm/u-boot-spl-hawk.lds delete mode 100644 configs/hawkboard_defconfig delete mode 100644 configs/hawkboard_uart_defconfig delete mode 100644 include/configs/hawkboard.h (limited to 'include') diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index 613f04d8b03..68277217bfc 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -21,10 +21,6 @@ config TARGET_CAM_ENC_4XX bool "CAM ENC 4xx board" select SUPPORT_SPL -config TARGET_HAWKBOARD - bool "Hawkboard" - select SUPPORT_SPL - config TARGET_DAVINCI_DM355EVM bool "DM355 EVM board" diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig index 1a841ce6e07..1108e4b164f 100644 --- a/board/davinci/da8xxevm/Kconfig +++ b/board/davinci/da8xxevm/Kconfig @@ -23,16 +23,3 @@ config SYS_CONFIG_NAME default "da850evm" endif - -if TARGET_HAWKBOARD - -config SYS_BOARD - default "da8xxevm" - -config SYS_VENDOR - default "davinci" - -config SYS_CONFIG_NAME - default "hawkboard" - -endif diff --git a/board/davinci/da8xxevm/MAINTAINERS b/board/davinci/da8xxevm/MAINTAINERS index dd66f07e727..10c4e2ffc0b 100644 --- a/board/davinci/da8xxevm/MAINTAINERS +++ b/board/davinci/da8xxevm/MAINTAINERS @@ -12,11 +12,3 @@ F: include/configs/da850evm.h F: configs/da850_am18xxevm_defconfig F: configs/da850evm_defconfig F: configs/da850evm_direct_nor_defconfig - -HAWKBOARD BOARD -M: Syed Mohammed Khasim -M: Sughosh Ganu -S: Maintained -F: include/configs/hawkboard.h -F: configs/hawkboard_defconfig -F: configs/hawkboard_uart_defconfig diff --git a/board/davinci/da8xxevm/Makefile b/board/davinci/da8xxevm/Makefile index d3acacc33de..4da509b5e19 100644 --- a/board/davinci/da8xxevm/Makefile +++ b/board/davinci/da8xxevm/Makefile @@ -9,4 +9,3 @@ obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += da830evm.o obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += da850evm.o -obj-$(CONFIG_MACH_DAVINCI_HAWK) += hawkboard.o diff --git a/board/davinci/da8xxevm/README.hawkboard b/board/davinci/da8xxevm/README.hawkboard deleted file mode 100644 index d6ae02ec028..00000000000 --- a/board/davinci/da8xxevm/README.hawkboard +++ /dev/null @@ -1,92 +0,0 @@ -Summary -======= -The README is for the boot procedure used for TI's OMAP-L138 based -hawkboard. The hawkboard comes with a 128MiB Nand flash and a 128MiB -DDR SDRAM along with a host of other controllers. - -The hawkboard is booted in three stages. The initial bootloader which -executes upon reset is the Rom Boot Loader(RBL) which sits in the -internal ROM of the omap. The RBL initialises the memory and the nand -controller, and copies the image stored at a predefined location(block -1) of the nand flash. The image loaded by the RBL to the memory is the -AIS signed spl image. This, in turns copies the u-boot binary from the -nand flash to the memory and jumps to the u-boot entry point. - -AIS is an image format defined by TI for the images that are to be -loaded to memory by the RBL. The image is divided into a series of -sections and the image's entry point is specified. Each section comes -with meta data like the target address the section is to be copied to -and the size of the section, which is used by the RBL to load the -image. At the end of the image the RBL jumps to the image entry -point. - -The secondary stage bootloader(spl) which is loaded by the RBL then -loads the u-boot from a predefined location in the nand to the memory -and jumps to the u-boot entry point. - -The reason a secondary stage bootloader is used is because the ECC -layout expected by the RBL is not the same as that used by -u-boot/linux. This also implies that for flashing the spl image,we -need to use the u-boot which uses the ECC layout expected by the -RBL[1]. Booting u-boot over UART(UART boot) is explained here[2]. - - -Compilation -=========== -Three images might be needed - -* spl - This is the secondary bootloader which boots the u-boot - binary. - -* u-boot binary - This is the image flashed to the nand and copied to - the memory by the spl. - - Both the images get compiled with hawkboard_config, with the TOPDIR - containing the u-boot images, and the spl image under the spl - directory. - - The spl image needs to be processed with the AISGen tool for - generating the AIS signed image to be flashed. Steps for generating - the AIS image are explained here[3]. - -* u-boot for uart boot - This is same as the u-boot binary generated - above, with the sole difference of the CONFIG_SYS_TEXT_BASE being - 0xc1080000, as expected by the RBL. - - hawkboard_uart_config - - -Flashing the images to Nand -=========================== -The spl AIS image needs to be flashed to the block 1 of the Nand -flash, as that is the location the RBL expects the image[4]. For -flashing the spl, boot over the u-boot specified in [1], and flash the -image - -=> tftpboot 0xc0700000 -=> nand erase 0x20000 0x20000 -=> nand write.e 0xc0700000 0x20000 - -The u-boot binary is flashed at location 0xe0000(block 6) of the nand -flash. The spl loader expects the u-boot at this location. For -flashing the u-boot binary - -=> tftpboot 0xc0700000 u-boot.bin -=> nand erase 0xe0000 0x40000 -=> nand write.e 0xc0700000 0xe0000 - - -Links -===== - -[1] - http://code.google.com/p/hawkboard/downloads/detail?name=u-boot_uart_ais_v1.bin - -[2] - http://elinux.org/Hawkboard#Booting_u-boot_over_UART - -[3] - http://elinux.org/Hawkboard#Signing_u-boot_for_UART_boot - -[4] - http://processors.wiki.ti.com/index.php/RBL_UBL_and_host_program#RBL_booting_from_NAND_and_ECC.2FBad_blocks diff --git a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg b/board/davinci/da8xxevm/hawkboard-ais-nand.cfg deleted file mode 100644 index 2b12b6c08ac..00000000000 --- a/board/davinci/da8xxevm/hawkboard-ais-nand.cfg +++ /dev/null @@ -1,4 +0,0 @@ -# PLL0CFG0 PLL0CFG1 -PLL0 0x00180001 0x00000205 -# PLL1CFG0 PLL1CFG1 DRPYC1R SDCR SDTIMR1 SDTIMR2 SDRCR CLK2XSRC -DDR2 0x15010001 0x00000002 0x00000043 0x00134632 0x26492a09 0x7d13c722 0x00000249 0x00000000 diff --git a/board/davinci/da8xxevm/hawkboard.c b/board/davinci/da8xxevm/hawkboard.c deleted file mode 100644 index d5992a55646..00000000000 --- a/board/davinci/da8xxevm/hawkboard.c +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Modified for Hawkboard - Syed Mohammed Khasim - * - * Copyright (C) 2008 Sekhar Nori, Texas Instruments, Inc. - * Copyright (C) 2007 Sergey Kubushyn - * Copyright (C) 2004 Texas Instruments. - * Copyright (C) 2012 Sughosh Ganu . - * - * ---------------------------------------------------------------------------- - * SPDX-License-Identifier: GPL-2.0+ - * ---------------------------------------------------------------------------- - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; - -const struct pinmux_resource pinmuxes[] = { - PINMUX_ITEM(emac_pins_mii), - PINMUX_ITEM(emac_pins_mdio), - PINMUX_ITEM(emifa_pins_cs3), - PINMUX_ITEM(emifa_pins_cs4), - PINMUX_ITEM(emifa_pins_nand), - PINMUX_ITEM(uart2_pins_txrx), - PINMUX_ITEM(uart2_pins_rtscts), -}; - -const int pinmuxes_size = ARRAY_SIZE(pinmuxes); - -const struct lpsc_resource lpsc[] = { - { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */ - { DAVINCI_LPSC_SPI1 }, /* Serial Flash */ - { DAVINCI_LPSC_EMAC }, /* image download */ - { DAVINCI_LPSC_UART2 }, /* console */ - { DAVINCI_LPSC_GPIO }, -}; - -const int lpsc_size = ARRAY_SIZE(lpsc); - -int board_init(void) -{ - /* arch number of the board */ - gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_HAWKBOARD; - - /* address of boot parameters */ - gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; - - return 0; -} - -int board_early_init_f(void) -{ - /* - * Kick Registers need to be set to allow access to Pin Mux registers - */ - writel(DV_SYSCFG_KICK0_UNLOCK, &davinci_syscfg_regs->kick0); - writel(DV_SYSCFG_KICK1_UNLOCK, &davinci_syscfg_regs->kick1); - - /* set cfgchip3 to select mii */ - writel(readl(&davinci_syscfg_regs->cfgchip3) & - ~(1 << 8), &davinci_syscfg_regs->cfgchip3); - - return 0; -} - -int misc_init_r(void) -{ - char buf[32]; - - printf("ARM Clock : %s MHz\n", - strmhz(buf, clk_get(DAVINCI_ARM_CLKID))); - - return 0; -} - -int usb_phy_on(void) -{ - u32 timeout; - u32 cfgchip2; - - cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); - - cfgchip2 &= ~(CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | - CFGCHIP2_OTGMODE | CFGCHIP2_REFFREQ | - CFGCHIP2_USB1PHYCLKMUX); - cfgchip2 |= CFGCHIP2_SESENDEN | CFGCHIP2_VBDTCTEN | CFGCHIP2_PHY_PLLON | - CFGCHIP2_REFFREQ_24MHZ | CFGCHIP2_USB2PHYCLKMUX | - CFGCHIP2_USB1SUSPENDM; - - writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); - - /* wait until the usb phy pll locks */ - timeout = DA8XX_USB_OTG_TIMEOUT; - while (timeout--) - if (readl(&davinci_syscfg_regs->cfgchip2) & CFGCHIP2_PHYCLKGD) - return 1; - - /* USB phy was not turned on */ - return 0; -} - -void usb_phy_off(void) -{ - u32 cfgchip2; - - /* - * Power down the on-chip PHY. - */ - cfgchip2 = readl(&davinci_syscfg_regs->cfgchip2); - cfgchip2 &= ~(CFGCHIP2_PHY_PLLON | CFGCHIP2_USB1SUSPENDM); - cfgchip2 |= CFGCHIP2_PHYPWRDN | CFGCHIP2_OTGPWRDN | CFGCHIP2_RESET; - writel(cfgchip2, &davinci_syscfg_regs->cfgchip2); -} diff --git a/board/davinci/da8xxevm/u-boot-spl-hawk.lds b/board/davinci/da8xxevm/u-boot-spl-hawk.lds deleted file mode 100644 index 5c629db139b..00000000000 --- a/board/davinci/da8xxevm/u-boot-spl-hawk.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2002 - * Gary Jennejohn, DENX Software Engineering, - * - * (C) Copyright 2008 - * Guennadi Liakhovetki, DENX Software Engineering, - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") -OUTPUT_ARCH(arm) -ENTRY(_start) -SECTIONS -{ - . = 0xc1080000; - - . = ALIGN(4); - .text : - { - *(.vectors) - arch/arm/cpu/arm926ejs/start.o (.text*) - arch/arm/cpu/arm926ejs/built-in.o (.text*) - drivers/mtd/nand/built-in.o (.text*) - - *(.text*) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { - *(.data) - __datarel_start = .; - *(.data.rel) - __datarelrolocal_start = .; - *(.data.rel.ro.local) - __datarellocal_start = .; - *(.data.rel.local) - __datarelro_start = .; - *(.data.rel.ro) - } - - . = ALIGN(4); - __image_copy_end = .; - __rel_dyn_start = .; - __rel_dyn_end = .; - - __got_start = .; - . = ALIGN(4); - .got : { *(.got) } - - __got_end = .; - - .bss : - { - . = ALIGN(4); - __bss_start = .; - *(.bss*) - . = ALIGN(4); - __bss_end = .; - } - - .end : - { - *(.__end) - } -} diff --git a/configs/hawkboard_defconfig b/configs/hawkboard_defconfig deleted file mode 100644 index 4084f9c019b..00000000000 --- a/configs/hawkboard_defconfig +++ /dev/null @@ -1,4 +0,0 @@ -CONFIG_SPL=y -+S:CONFIG_ARM=y -+S:CONFIG_ARCH_DAVINCI=y -+S:CONFIG_TARGET_HAWKBOARD=y diff --git a/configs/hawkboard_uart_defconfig b/configs/hawkboard_uart_defconfig deleted file mode 100644 index d7eeae7a29d..00000000000 --- a/configs/hawkboard_uart_defconfig +++ /dev/null @@ -1,5 +0,0 @@ -CONFIG_SPL=y -CONFIG_SYS_EXTRA_OPTIONS="UART_U_BOOT" -+S:CONFIG_ARM=y -+S:CONFIG_ARCH_DAVINCI=y -+S:CONFIG_TARGET_HAWKBOARD=y diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 766d7123e53..cd8f4aeaf32 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order. Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= +hawkboard arm arm926ejs - - Syed Mohammed Khasim :Sughosh Ganu tnetv107x arm arm1176 - - Chan-Taek Park a320evb arm arm920t - - Po-Yu Chuang cm4008 arm arm920t - - Greg Ungerer diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h deleted file mode 100644 index 1d78e725e3c..00000000000 --- a/include/configs/hawkboard.h +++ /dev/null @@ -1,220 +0,0 @@ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -#define CONFIG_SYS_USE_NAND 1 - -/* - * SoC Configuration - */ -#define CONFIG_MACH_DAVINCI_HAWK -#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */ -#define CONFIG_SOC_DA850 /* TI DA850 SoC */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_AIS_CONFIG_FILE "board/$(BOARDDIR)/hawkboard-ais-nand.cfg" - -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_EMAC | \ - DAVINCI_SYSCFG_SUSPSRC_I2C | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2) - -#if defined(CONFIG_UART_U_BOOT) -#define CONFIG_SYS_TEXT_BASE 0xc1080000 -#elif !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_TEXT_BASE 0xc1180000 -#endif - -/* Spl */ -#define CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_BOARD_INIT -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_LIBGENERIC_SUPPORT /* for udelay and __div64_32 for NAND */ -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_LDSCRIPT "board/$(BOARDDIR)/u-boot-spl-hawk.lds" -#define CONFIG_SPL_TEXT_BASE 0xc1080000 -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE -#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 -\ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN 0x60000 - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) - -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -/* - * Network & Ethernet Configuration - */ -#define CONFIG_DRIVER_TI_EMAC -#define CONFIG_MII -#define CONFIG_BOOTP_DNS -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* - * Nand Flash - */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_CLE_MASK 0x10 -#define CONFIG_ALE_MASK 0x8 -#define CONFIG_SYS_NAND_USE_FLASH_BBT -#define CONFIG_NAND_DAVINCI -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST /* SPL nand driver configuration */ -#define CFG_DAVINCI_STD_NAND_LAYOUT -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_PAGE_2K -/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE_LIST { 0x62000000, } -/* Block 0--not used by bootcode */ -#define CONFIG_ENV_OFFSET 0x0 - -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0xe0000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1180000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ - 24, 25, 26, 27, 28, \ - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ - 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ - 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 -#define CONFIG_SYS_NAND_OOBSIZE 64 - -#endif /* CONFIG_SYS_USE_NAND */ - -/* USB Configs */ -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_OHCI_DA8XX -#define CONFIG_USB_STORAGE -#define CONFIG_DOS_PARTITION -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x01E25000 -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "hawkboard" - -/* - * U-Boot general configuration - */ -#define CONFIG_MISC_INIT_R -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_PROMPT "hawkboard > " /* Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) -#define CONFIG_VERSION_VARIABLE -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_HUSH_PARSER -#define CONFIG_CMDLINE_EDITING -#define CONFIG_SYS_LONGHELP -#define CONFIG_CRC32_VERIFY -#define CONFIG_MX_CYCLIC - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (CONFIG_SYS_MEMTEST_START + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=128M console=ttyS2,115200n8 root=/dev/ram0 rw initrd=0xc1180000,"\ - "4M ip=static" -#define CONFIG_BOOTDELAY 3 - -/* - * U-Boot commands - */ -#include -#define CONFIG_CMD_ENV -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DIAG -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING -#define CONFIG_CMD_SAVES -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_USB -#define CONFIG_CMD_EXT2 - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#ifdef CONFIG_SYS_USE_NAND -#undef CONFIG_CMD_FLASH -#undef CONFIG_CMD_IMLS -#define CONFIG_CMD_NAND -#endif - -#ifndef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_DHCP -#undef CONFIG_CMD_MII -#undef CONFIG_CMD_PING -#endif - -#endif /* __CONFIG_H */ -- cgit v1.3.1 From 87db635161e86670f9c1119a1faf1d5059564989 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Feb 2015 08:51:36 -0300 Subject: mx31ads: Convert to generic board Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Acked-by: Anatolij Gustschin Signed-off-by: Fabio Estevam --- include/configs/mx31ads.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index 0f4bd91c645..bed071fa669 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -14,6 +14,8 @@ /* High Level Configuration Options */ #define CONFIG_MX31 1 /* This is a mx31 */ +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.3.1 From 9d4a161046284774ef3f85f7b94d5ed7ee85c808 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Feb 2015 08:51:37 -0300 Subject: imx31_phycore: Convert to generic board Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Acked-by: Anatolij Gustschin Signed-off-by: Fabio Estevam --- include/configs/imx31_phycore.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 4195fa35330..49039d6dfb8 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -18,6 +18,8 @@ #define CONFIG_MX31 /* This is a mx31 */ #define CONFIG_MX31_CLK32 32000 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -- cgit v1.3.1 From 47d8ae4069b47ce966c0c5e0d8dd041e69ee1f86 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Mon, 23 Feb 2015 08:51:38 -0300 Subject: zmx25: Convert to generic board Boards need to select CONFIG_SYS_GENERIC_BOARD in order to prevent removal from the project. Cc: Matthias Weisser Signed-off-by: Fabio Estevam --- include/configs/zmx25.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h index 356ac886f26..342fa2c40a2 100644 --- a/include/configs/zmx25.h +++ b/include/configs/zmx25.h @@ -15,6 +15,8 @@ #define CONFIG_MX25 #define CONFIG_SYS_TEXT_BASE 0xA0000000 +#define CONFIG_SYS_GENERIC_BOARD + #define CONFIG_SYS_TIMER_RATE 32768 #define CONFIG_SYS_TIMER_COUNTER \ (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) -- cgit v1.3.1 From 94e3c8c4fd7bfe395fa467973cd647551d6d98c7 Mon Sep 17 00:00:00 2001 From: gaurav rana Date: Fri, 20 Feb 2015 12:51:46 +0530 Subject: crypto/fsl - Add progressive hashing support using hardware acceleration. Currently only normal hashing is supported using hardware acceleration. Added support for progressive hashing using hardware. Signed-off-by: Ruchika Gupta Signed-off-by: Gaurav Rana CC: Simon Glass Reviewed-by: Simon Glass Reviewed-by: York Sun --- Kconfig | 4 +- README | 20 ++++-- common/hash.c | 10 +++ drivers/crypto/fsl/fsl_hash.c | 138 +++++++++++++++++++++++++++++++++++++++++- drivers/crypto/fsl/fsl_hash.h | 34 +++++++++++ include/fsl_sec.h | 26 ++++++++ include/hw_sha.h | 41 ++++++++++++- lib/Kconfig | 36 +++++++++++ 8 files changed, 302 insertions(+), 7 deletions(-) create mode 100644 drivers/crypto/fsl/fsl_hash.h (limited to 'include') diff --git a/Kconfig b/Kconfig index 75bab7f6cc0..fb012cfb3eb 100644 --- a/Kconfig +++ b/Kconfig @@ -141,7 +141,9 @@ config FIT_SIGNATURE select RSA help This option enables signature verification of FIT uImages, - using a hash signed and verified using RSA. + using a hash signed and verified using RSA. If + CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive + hashing is available using hardware, RSA library will use it. See doc/uImage.FIT/signature.txt for more details. config SYS_EXTRA_OPTIONS diff --git a/README b/README index 6800b959ca5..febefb50c24 100644 --- a/README +++ b/README @@ -3152,8 +3152,18 @@ CBFS (Coreboot Filesystem) support Enable the hash verify command (hash -v). This adds to code size a little. - CONFIG_SHA1 - support SHA1 hashing - CONFIG_SHA256 - support SHA256 hashing + CONFIG_SHA1 - This option enables support of hashing using SHA1 + algorithm. The hash is calculated in software. + CONFIG_SHA256 - This option enables support of hashing using + SHA256 algorithm. The hash is calculated in software. + CONFIG_SHA_HW_ACCEL - This option enables hardware acceleration + for SHA1/SHA256 hashing. + This affects the 'hash' command and also the + hash_lookup_algo() function. + CONFIG_SHA_PROG_HW_ACCEL - This option enables + hardware-acceleration for SHA1/SHA256 progressive hashing. + Data can be streamed in a block at a time and the hashing + is performed in hardware. Note: There is also a sha1sum command, which should perhaps be deprecated in favour of 'hash sha1'. @@ -3447,8 +3457,10 @@ FIT uImage format: CONFIG_FIT_SIGNATURE This option enables signature verification of FIT uImages, - using a hash signed and verified using RSA. See - doc/uImage.FIT/signature.txt for more details. + using a hash signed and verified using RSA. If + CONFIG_SHA_PROG_HW_ACCEL is defined, i.e support for progressive + hashing is available using hardware, RSA library will use it. + See doc/uImage.FIT/signature.txt for more details. WARNING: When relying on signed FIT images with required signature check the legacy image format is default diff --git a/common/hash.c b/common/hash.c index d154d029e9c..9e9f84b9fb4 100644 --- a/common/hash.c +++ b/common/hash.c @@ -127,11 +127,21 @@ static struct hash_algo hash_algo[] = { SHA1_SUM_LEN, hw_sha1, CHUNKSZ_SHA1, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, { "sha256", SHA256_SUM_LEN, hw_sha256, CHUNKSZ_SHA256, +#ifdef CONFIG_SHA_PROG_HW_ACCEL + hw_sha_init, + hw_sha_update, + hw_sha_finish, +#endif }, #endif #ifdef CONFIG_SHA1 diff --git a/drivers/crypto/fsl/fsl_hash.c b/drivers/crypto/fsl/fsl_hash.c index d77f2573d0f..c298404f252 100644 --- a/drivers/crypto/fsl/fsl_hash.c +++ b/drivers/crypto/fsl/fsl_hash.c @@ -10,6 +10,9 @@ #include "jobdesc.h" #include "desc.h" #include "jr.h" +#include "fsl_hash.h" +#include +#include #define CRYPTO_MAX_ALG_NAME 80 #define SHA1_DIGEST_SIZE 20 @@ -39,6 +42,122 @@ static struct caam_hash_template driver_hash[] = { }, }; +static enum caam_hash_algos get_hash_type(struct hash_algo *algo) +{ + if (!strcmp(algo->name, driver_hash[SHA1].name)) + return SHA1; + else + return SHA256; +} + +/* Create the context for progressive hashing using h/w acceleration. + * + * @ctxp: Pointer to the pointer of the context for hashing + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -ENOMEM on error + */ +static int caam_hash_init(void **ctxp, enum caam_hash_algos caam_algo) +{ + *ctxp = calloc(1, sizeof(struct sha_ctx)); + if (*ctxp == NULL) { + debug("Cannot allocate memory for context\n"); + return -ENOMEM; + } + return 0; +} + +/* + * Update sg table for progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * We support at most 32 Scatter/Gather Entries. + * + * @hash_ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_update(void *hash_ctx, const void *buf, + unsigned int size, int is_last, + enum caam_hash_algos caam_algo) +{ + uint32_t final = 0; + dma_addr_t addr = virt_to_phys((void *)buf); + struct sha_ctx *ctx = hash_ctx; + + if (ctx->sg_num >= MAX_SG_32) { + free(ctx); + return -EINVAL; + } + +#ifdef CONFIG_PHYS_64BIT + ctx->sg_tbl[ctx->sg_num].addr_hi = addr >> 32; +#else + ctx->sg_tbl[ctx->sg_num].addr_hi = 0x0; +#endif + ctx->sg_tbl[ctx->sg_num].addr_lo = addr; + + sec_out32(&ctx->sg_tbl[ctx->sg_num].len_flag, + (size & SG_ENTRY_LENGTH_MASK)); + + ctx->sg_num++; + + if (is_last) { + final = sec_in32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag) | + SG_ENTRY_FINAL_BIT; + sec_out32(&ctx->sg_tbl[ctx->sg_num - 1].len_flag, final); + } + + return 0; +} + +/* + * Perform progressive hashing on the given buffer and copy hash at + * destination buffer + * + * The context is freed after completion of hash operation. + * + * @hash_ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @caam_algo: Enum for SHA1 or SHA256 + * @return 0 if ok, -EINVAL on error + */ +static int caam_hash_finish(void *hash_ctx, void *dest_buf, + int size, enum caam_hash_algos caam_algo) +{ + uint32_t len = 0; + struct sha_ctx *ctx = hash_ctx; + int i = 0, ret = 0; + + if (size < driver_hash[caam_algo].digestsize) { + free(ctx); + return -EINVAL; + } + + for (i = 0; i < ctx->sg_num; i++) + len += (sec_in32(&ctx->sg_tbl[i].len_flag) & + SG_ENTRY_LENGTH_MASK); + + inline_cnstr_jobdesc_hash(ctx->sha_desc, (uint8_t *)ctx->sg_tbl, len, + ctx->hash, + driver_hash[caam_algo].alg_type, + driver_hash[caam_algo].digestsize, + 1); + + ret = run_descriptor_jr(ctx->sha_desc); + + if (ret) + debug("Error %x\n", ret); + else + memcpy(dest_buf, ctx->hash, sizeof(ctx->hash)); + + free(ctx); + return ret; +} + int caam_hash(const unsigned char *pbuf, unsigned int buf_len, unsigned char *pout, enum caam_hash_algos algo) { @@ -48,7 +167,7 @@ int caam_hash(const unsigned char *pbuf, unsigned int buf_len, desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; } inline_cnstr_jobdesc_hash(desc, pbuf, buf_len, pout, @@ -75,3 +194,20 @@ void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, if (caam_hash(pbuf, buf_len, pout, SHA1)) printf("CAAM was not setup properly or it is faulty\n"); } + +int hw_sha_init(struct hash_algo *algo, void **ctxp) +{ + return caam_hash_init(ctxp, get_hash_type(algo)); +} + +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last) +{ + return caam_hash_update(ctx, buf, size, is_last, get_hash_type(algo)); +} + +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size) +{ + return caam_hash_finish(ctx, dest_buf, size, get_hash_type(algo)); +} diff --git a/drivers/crypto/fsl/fsl_hash.h b/drivers/crypto/fsl/fsl_hash.h new file mode 100644 index 00000000000..f5be651d7af --- /dev/null +++ b/drivers/crypto/fsl/fsl_hash.h @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + * + */ + +#ifndef _SHA_H +#define _SHA_H + +#include +#include +#include "jr.h" + +/* We support at most 32 Scatter/Gather Entries.*/ +#define MAX_SG_32 32 + +/* + * Hash context contains the following fields + * @sha_desc: Sha Descriptor + * @sg_num: number of entries in sg table + * @len: total length of buffer + * @sg_tbl: sg entry table + * @hash: index to the hash calculated + */ +struct sha_ctx { + uint32_t sha_desc[64]; + uint32_t sg_num; + uint32_t len; + struct sg_entry sg_tbl[MAX_SG_32]; + u8 hash[HASH_MAX_DIGEST_SIZE]; +}; + +#endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index aa850a3bf13..b6e6f04a34c 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -175,6 +175,32 @@ struct jr_regs { u32 jrcr; }; +/* + * Scatter Gather Entry - Specifies the the Scatter Gather Format + * related information + */ +struct sg_entry { +#ifdef CONFIG_SYS_FSL_SEC_LE + uint32_t addr_lo; /* Memory Address - lo */ + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint16_t reserved_zero; +#else + uint16_t reserved_zero; + uint16_t addr_hi; /* Memory Address of start of buffer - hi */ + uint32_t addr_lo; /* Memory Address - lo */ +#endif + + uint32_t len_flag; /* Length of the data in the frame */ +#define SG_ENTRY_LENGTH_MASK 0x3FFFFFFF +#define SG_ENTRY_EXTENSION_BIT 0x80000000 +#define SG_ENTRY_FINAL_BIT 0x40000000 + uint32_t bpid_offset; +#define SG_ENTRY_BPID_MASK 0x00FF0000 +#define SG_ENTRY_BPID_SHIFT 16 +#define SG_ENTRY_OFFSET_MASK 0x00001FFF +#define SG_ENTRY_OFFSET_SHIFT 0 +}; + int sec_init(void); #endif diff --git a/include/hw_sha.h b/include/hw_sha.h index 783350d5136..ab19a991889 100644 --- a/include/hw_sha.h +++ b/include/hw_sha.h @@ -7,7 +7,7 @@ */ #ifndef __HW_SHA_H #define __HW_SHA_H - +#include /** * Computes hash value of input pbuf using h/w acceleration @@ -34,4 +34,43 @@ void hw_sha256(const uchar * in_addr, uint buflen, */ void hw_sha1(const uchar * in_addr, uint buflen, uchar * out_addr, uint chunk_size); + +/* + * Create the context for sha progressive hashing using h/w acceleration + * + * @algo: Pointer to the hash_algo struct + * @ctxp: Pointer to the pointer of the context for hashing + * @return 0 if ok, -ve on error + */ +int hw_sha_init(struct hash_algo *algo, void **ctxp); + +/* + * Update buffer for sha progressive hashing using h/w acceleration + * + * The context is freed by this function if an error occurs. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @buf: Pointer to the buffer being hashed + * @size: Size of the buffer being hashed + * @is_last: 1 if this is the last update; 0 otherwise + * @return 0 if ok, -ve on error + */ +int hw_sha_update(struct hash_algo *algo, void *ctx, const void *buf, + unsigned int size, int is_last); + +/* + * Copy sha hash result at destination location + * + * The context is freed after completion of hash operation or after an error. + * + * @algo: Pointer to the hash_algo struct + * @ctx: Pointer to the context for hashing + * @dest_buf: Pointer to the destination buffer where hash is to be copied + * @size: Size of the buffer being hashed + * @return 0 if ok, -ve on error + */ +int hw_sha_finish(struct hash_algo *algo, void *ctx, void *dest_buf, + int size); + #endif diff --git a/lib/Kconfig b/lib/Kconfig index a1f30a2c4ef..c9d2767d1da 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -29,4 +29,40 @@ config SYS_HZ source lib/rsa/Kconfig +menu "Hashing Support" + +config SHA1 + bool "Enable SHA1 support" + help + This option enables support of hashing using SHA1 algorithm. + The hash is calculated in software. + The SHA1 algorithm produces a 160-bit (20-byte) hash value + (digest). + +config SHA256 + bool "Enable SHA256 support" + help + This option enables support of hashing using SHA256 algorithm. + The hash is calculated in software. + The SHA256 algorithm produces a 256-bit (32-byte) hash value + (digest). + +config SHA_HW_ACCEL + bool "Enable hashing using hardware" + help + This option enables hardware acceleration + for SHA1/SHA256 hashing. + This affects the 'hash' command and also the + hash_lookup_algo() function. + +config SHA_PROG_HW_ACCEL + bool "Enable Progressive hashing support using hardware" + depends on SHA_HW_ACCEL + help + This option enables hardware-acceleration for + SHA1/SHA256 progressive hashing. + Data can be streamed in a block at a time and the hashing + is performed in hardware. +endmenu + endmenu -- cgit v1.3.1