From 76d4ae251e4a2f7724f4462baccc2779074fa937 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Fri, 13 Jan 2012 10:11:44 +0300 Subject: zipitz2: fix boot issue introduced by PXA low level init rework CONFIG_SYS_INIT_SP_ADDR points to RAM, but it's used before DRAM controller init. Fix it by setting CONFIG_SYS_INIT_SP_ADDR to SRAM Signed-off-by: Vasily Khoruzhick --- include/configs/zipitz2.h | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 26204af2c29..80d78b67170 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -161,6 +161,12 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif +/* + * SRAM Map + */ +#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */ +#define PHYS_SRAM_SIZE 0x00040000 /* 256k */ + /* * DRAM Map */ @@ -177,7 +183,7 @@ unsigned char zipitz2_spi_read(void); #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1 + 2048) +#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048) /* * NOR FLASH -- cgit v1.3.1 From 81f731ca7c387d6ae1560a27118a4c6a09b6e722 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick Date: Wed, 25 Jan 2012 22:54:33 +0300 Subject: zipitz2: use pxa_mmc_gen as MMC driver Signed-off-by: Vasily Khoruzhick --- board/zipitz2/zipitz2.c | 8 ++++++++ include/configs/zipitz2.h | 6 ++++-- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/zipitz2/zipitz2.c b/board/zipitz2/zipitz2.c index b093c2f51f8..4075fb659c5 100644 --- a/board/zipitz2/zipitz2.c +++ b/board/zipitz2/zipitz2.c @@ -79,6 +79,14 @@ void dram_init_banksize(void) gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; } +#ifdef CONFIG_CMD_MMC +int board_mmc_init(bd_t *bis) +{ + pxa_mmc_register(0); + return 0; +} +#endif + #ifdef CONFIG_CMD_SPI struct { diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h index 80d78b67170..afe1e891dda 100644 --- a/include/configs/zipitz2.h +++ b/include/configs/zipitz2.h @@ -45,7 +45,8 @@ #define CONFIG_ARCH_CPU_INIT #define CONFIG_BOOTCOMMAND \ - "if mmc init && fatload mmc 0 0xa0000000 uboot.script ; then " \ + "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\ + "then " \ "source 0xa0000000; " \ "else " \ "bootm 0x60000; " \ @@ -85,7 +86,8 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC -#define CONFIG_PXA_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_PXA_MMC_GENERIC #define CONFIG_SYS_MMC_BASE 0xF0000000 #define CONFIG_CMD_FAT #define CONFIG_CMD_EXT2 -- cgit v1.3.1 From c1ff6d8872401dd421a329440debba8fb91ecf2b Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 13 Feb 2012 09:05:16 +0100 Subject: PXA: Remove PXA PCMCIA support Say good bye to some ancient, very broken and unused code. Signed-off-by: Marek Vasut --- doc/README.PXA_CF | 56 --------------------------- drivers/pcmcia/Makefile | 1 - drivers/pcmcia/pxa_pcmcia.c | 93 --------------------------------------------- include/pcmcia.h | 3 +- 4 files changed, 1 insertion(+), 152 deletions(-) delete mode 100644 doc/README.PXA_CF delete mode 100644 drivers/pcmcia/pxa_pcmcia.c (limited to 'include') diff --git a/doc/README.PXA_CF b/doc/README.PXA_CF deleted file mode 100644 index 1d76b32dd7a..00000000000 --- a/doc/README.PXA_CF +++ /dev/null @@ -1,56 +0,0 @@ - -These are brief instructions on how to add support for CF adapters to -custom designed PXA boards. You need to set the parameters in the -config file. This should work for most implementations especially if you -follow the connections of the standard lubbock. Anyway just the block -marked memory configuration should be touched since the other parameters -are imposed by the PXA architecture. - -EDIT 2010-07-01: in common/cmd_ide.c, having CONFIG_PXA_PCMCIA defined -would cause looping on inw()/outw() rather than using insw()/outsw(), -thus making sure IDE / ATA bytes are properly swapped. This behaviour -is now controlled by CONFIG_IDE_SWAP_IO, therefore PXA boards with -PCMCIA should #define CONFIG_IDE_SWAP_IO. - -#define CONFIG_IDE_SWAP_IO - -#define CONFIG_PXA_PCMCIA 1 -#define CONFIG_PXA_IDE 1 - -#define CONFIG_PCMCIA_SLOT_A 1 -/* just to keep build system happy */ - -#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x28000000 -#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00004204 -#define CONFIG_SYS_MCMEM1_VAL 0x00000000 -#define CONFIG_SYS_MCATT0_VAL 0x00010504 -#define CONFIG_SYS_MCATT1_VAL 0x00000000 -#define CONFIG_SYS_MCIO0_VAL 0x00008407 -#define CONFIG_SYS_MCIO1_VAL 0x00000000 -/* memory configuration */ - -#define CONFIG_SYS_IDE_MAXBUS 1 -/* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x20000000 - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1f0 - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1f0 - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x3f0 - - -Another important point is that maybe you have to power the pcmcia -subsystem. This is very board specific, for an example on how to -do it please search for CONFIG_EXADRON1 in cmd_pcmcia.c diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index 03495087dc9..aa477d4f933 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -27,7 +27,6 @@ LIB := $(obj)libpcmcia.o COBJS-$(CONFIG_I82365) += i82365.o COBJS-$(CONFIG_8xx) += mpc8xx_pcmcia.o -COBJS-$(CONFIG_PXA_PCMCIA) += pxa_pcmcia.o COBJS-y += rpx_pcmcia.o COBJS-$(CONFIG_IDE_TI_CARDBUS) += ti_pci1410a.o COBJS-y += tqm8xx_pcmcia.o diff --git a/drivers/pcmcia/pxa_pcmcia.c b/drivers/pcmcia/pxa_pcmcia.c deleted file mode 100644 index d06ab746c8a..00000000000 --- a/drivers/pcmcia/pxa_pcmcia.c +++ /dev/null @@ -1,93 +0,0 @@ -#include -#include - -#include -#include -#include - -static inline void msWait(unsigned msVal) -{ - udelay(msVal*1000); -} - -int pcmcia_on (void) -{ - unsigned int reg_arr[] = { - 0x48000028, CONFIG_SYS_MCMEM0_VAL, - 0x4800002c, CONFIG_SYS_MCMEM1_VAL, - 0x48000030, CONFIG_SYS_MCATT0_VAL, - 0x48000034, CONFIG_SYS_MCATT1_VAL, - 0x48000038, CONFIG_SYS_MCIO0_VAL, - 0x4800003c, CONFIG_SYS_MCIO1_VAL, - - 0, 0 - }; - int i, rc; - -#ifdef CONFIG_EXADRON1 - int cardDetect; - volatile unsigned int *v_pBCRReg = - (volatile unsigned int *) 0x08000000; -#endif - - debug ("%s\n", __FUNCTION__); - - i = 0; - while (reg_arr[i]) { - (*(volatile unsigned int *) reg_arr[i]) |= reg_arr[i + 1]; - i += 2; - } - udelay (1000); - - debug ("%s: programmed mem controller \n", __FUNCTION__); - -#ifdef CONFIG_EXADRON1 - -/*define useful BCR masks */ -#define BCR_CF_INIT_VAL 0x00007230 -#define BCR_CF_PWRON_BUSOFF_RESETOFF_VAL 0x00007231 -#define BCR_CF_PWRON_BUSOFF_RESETON_VAL 0x00007233 -#define BCR_CF_PWRON_BUSON_RESETON_VAL 0x00007213 -#define BCR_CF_PWRON_BUSON_RESETOFF_VAL 0x00007211 - - /* we see from the GPIO bit if the card is present */ - cardDetect = !(GPLR0 & GPIO_bit (14)); - - if (cardDetect) { - printf ("No PCMCIA card found!\n"); - } - - /* reset the card via the BCR line */ - *v_pBCRReg = (unsigned) BCR_CF_INIT_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETOFF_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSOFF_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETON_VAL; - msWait (500); - - *v_pBCRReg = (unsigned) BCR_CF_PWRON_BUSON_RESETOFF_VAL; - msWait (1500); - - /* enable address bus */ - GPCR1 = 0x01; - /* and the first CF slot */ - MECR = 0x00000002; - -#endif /* EXADRON 1 */ - - rc = check_ide_device (0); /* use just slot 0 */ - - return rc; -} - -#if defined(CONFIG_CMD_PCMCIA) -int pcmcia_off (void) -{ - return 0; -} -#endif diff --git a/include/pcmcia.h b/include/pcmcia.h index b60323d3c09..ca0bf224f15 100644 --- a/include/pcmcia.h +++ b/include/pcmcia.h @@ -313,8 +313,7 @@ extern u_int *pcmcia_pgcrx[]; #define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot]) #endif -#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) \ - || defined(CONFIG_PXA_PCMCIA) +#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_8xx_PCCARD) extern int check_ide_device(int slot); #endif -- cgit v1.3.1 From 2ea73e9e38befa872d215c919f766d837d7a1312 Mon Sep 17 00:00:00 2001 From: Wolfgang Grandegger Date: Wed, 8 Feb 2012 22:33:26 +0000 Subject: mx6qsabrelite: add and enable USB Host 1 support Cc: Stefano Babic Cc: Jason Liu Signed-off-by: Wolfgang Grandegger --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 18 ++++++++++++++++++ include/configs/mx6qsabrelite.h | 13 +++++++++++++ 2 files changed, 31 insertions(+) (limited to 'include') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index f884bb53a09..db1bea98306 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -140,12 +140,30 @@ static void setup_iomux_enet(void) imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); } +iomux_v3_cfg_t usb_pads[] = { + MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); } +#ifdef CONFIG_USB_EHCI_MX6 +int board_ehci_hcd_init(int port) +{ + imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); + + /* Reset USB hub */ + gpio_direction_output(GPIO_NUMBER(7, 12), 0); + mdelay(2); + gpio_set_value(GPIO_NUMBER(7, 12), 1); + + return 0; +} +#endif + #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg usdhc_cfg[2] = { {USDHC3_BASE_ADDR, 1}, diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 982f03f7104..93000f03766 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -80,6 +80,19 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_MICREL +/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_MXC_USB_PORT 1 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 -- cgit v1.3.1 From 763cf0a3d24124916824e31793fbafbbb4311597 Mon Sep 17 00:00:00 2001 From: Matt Porter Date: Tue, 31 Jan 2012 12:03:58 +0000 Subject: SPL: Enable YMODEM support on BeagleBone and AM335x EVM Cc: Chandan Nath Tested-by: Tom Rini Signed-off-by: Matt Porter --- include/configs/am335x_evm.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index 6683b3ec29a..d0fbc882148 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -145,6 +145,7 @@ #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_YMODEM_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" /* -- cgit v1.3.1 From 8e807ec3aa977fd50bea18ce0b51b15877a6bde5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Tue, 6 Mar 2012 00:45:35 +0100 Subject: IXP: Fix missing MACH_TYPE_{ACTUX?,PNB3,DVLHOST} These symbols are no longer defined in Linux-ARM's mach-types files. Replace these with CONFIG_MACH_TYPE instead. Signed-off-by: Marek Vasut Cc: Bryan Hundven Cc: Michael Schwingen --- board/actux1/actux1.c | 2 -- board/actux2/actux2.c | 2 -- board/actux3/actux3.c | 2 -- board/actux4/actux4.c | 2 -- board/dvlhost/dvlhost.c | 2 -- board/prodrive/pdnb3/pdnb3.c | 3 --- include/configs/actux1.h | 2 ++ include/configs/actux2.h | 2 ++ include/configs/actux3.h | 2 ++ include/configs/actux4.h | 2 ++ include/configs/dvlhost.h | 2 ++ include/configs/pdnb3.h | 2 ++ 12 files changed, 12 insertions(+), 13 deletions(-) (limited to 'include') diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c index 2f631b70853..bc68eb3d042 100644 --- a/board/actux1/actux1.c +++ b/board/actux1/actux1.c @@ -59,8 +59,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c index 9040a098deb..9e9e6005143 100644 --- a/board/actux2/actux2.c +++ b/board/actux2/actux2.c @@ -59,8 +59,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX2; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c index 64e5215f364..7559c1d4358 100644 --- a/board/actux3/actux3.c +++ b/board/actux3/actux3.c @@ -57,8 +57,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c index d20d881eaf3..6303c1e5efa 100644 --- a/board/actux4/actux4.c +++ b/board/actux4/actux4.c @@ -54,8 +54,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_ACTUX4; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/dvlhost/dvlhost.c b/board/dvlhost/dvlhost.c index 561e47f9354..c2c67cc444b 100644 --- a/board/dvlhost/dvlhost.c +++ b/board/dvlhost/dvlhost.c @@ -46,8 +46,6 @@ int board_early_init_f(void) int board_init(void) { - gd->bd->bi_arch_number = MACH_TYPE_DVLHOST; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c index 3aaebf24396..d3ee13376b4 100644 --- a/board/prodrive/pdnb3/pdnb3.c +++ b/board/prodrive/pdnb3/pdnb3.c @@ -46,9 +46,6 @@ static unsigned long old_val = 0; */ int board_init(void) { - /* arch number of PDNB3 */ - gd->bd->bi_arch_number = MACH_TYPE_PDNB3; - /* adress of boot parameters */ gd->bd->bi_boot_params = 0x00000100; diff --git a/include/configs/actux1.h b/include/configs/actux1.h index 00780d0d8b3..bdd2239d8e2 100644 --- a/include/configs/actux1.h +++ b/include/configs/actux1.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX1 1 +#define CONFIG_MACH_TYPE 1479 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux2.h b/include/configs/actux2.h index cb97434c3ef..c55571c1285 100644 --- a/include/configs/actux2.h +++ b/include/configs/actux2.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX2 1 +#define CONFIG_MACH_TYPE 1480 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux3.h b/include/configs/actux3.h index 816d982a317..78ee2b598f6 100644 --- a/include/configs/actux3.h +++ b/include/configs/actux3.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX3 1 +#define CONFIG_MACH_TYPE 1481 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/actux4.h b/include/configs/actux4.h index 90badd39c59..c1105df5956 100644 --- a/include/configs/actux4.h +++ b/include/configs/actux4.h @@ -29,6 +29,8 @@ #define CONFIG_IXP425 1 #define CONFIG_ACTUX4 1 +#define CONFIG_MACH_TYPE 1532 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/dvlhost.h b/include/configs/dvlhost.h index 86fecd15a68..4eda91e7f40 100644 --- a/include/configs/dvlhost.h +++ b/include/configs/dvlhost.h @@ -30,6 +30,8 @@ #define CONFIG_IXP425 1 #define CONFIG_DVLHOST 1 +#define CONFIG_MACH_TYPE 1343 + #define CONFIG_DISPLAY_CPUINFO 1 #define CONFIG_DISPLAY_BOARDINFO 1 diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 56bb4641fca..43ec38f5d4e 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -33,6 +33,8 @@ #define CONFIG_IXP425 1 /* This is an IXP425 CPU */ #define CONFIG_PDNB3 1 /* on an PDNB3 board */ +#define CONFIG_MACH_TYPE 1002 + #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ -- cgit v1.3.1 From 9ff323df76b677fb64ae8490e5fafd3a2e51e8da Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Fri, 2 Mar 2012 12:55:09 +0000 Subject: i.MX6: mx6qsabrelite: add ext2 support Current Ubuntu releases from Freescale contain a boot script in ext3 filesystem. Signed-off-by: Eric Nelson --- include/configs/mx6qsabrelite.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index 93000f03766..bb3a46b2f50 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -64,6 +64,7 @@ #define CONFIG_MMC #define CONFIG_CMD_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION -- cgit v1.3.1 From 0bd14dea635e95eb7c16bb93fac38a76095fb586 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:08 +0000 Subject: mx51evk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam --- include/configs/mx51evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index 3b18a18d3e8..1477b213bd1 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -199,7 +199,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x90010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From bc9d5ef107b3feca44eacd18b321e8b4547462f9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:09 +0000 Subject: mx53evk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Cc: Jason Liu Signed-off-by: Fabio Estevam --- include/configs/mx53evk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 11fe6efe626..a77e5b206d3 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -161,7 +161,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From 869aed7bcea04e449521fdf5f494207b13afed6b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:10 +0000 Subject: mx53smd: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam --- include/configs/mx53smd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h index 032f72261e6..a04db3ff450 100644 --- a/include/configs/mx53smd.h +++ b/include/configs/mx53smd.h @@ -149,7 +149,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x70010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From f361a5c0753f910f1bc3db51970120df77499b2e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:11 +0000 Subject: efikamx: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Cc: Marek Vasut Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Tested-by: Marek Vasut --- include/configs/efikamx.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index e2f0f7465d8..af542fadcec 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -240,7 +240,7 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x90010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -- cgit v1.3.1 From 304e49e6cbec7ce8577a528e5be36930d098243b Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 9 Feb 2012 14:25:07 +0000 Subject: mx31pdk: Fix CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_END should be higher than CONFIG_SYS_MEMTEST_START. Signed-off-by: Fabio Estevam --- include/configs/mx31pdk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 4da6020c8cf..49d440b9ae3 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -141,7 +141,7 @@ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x80010000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 -- cgit v1.3.1 From 1c9ceff8ca896bd04cc2c85f762662dceecd7927 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Mon, 12 Mar 2012 15:04:12 +0000 Subject: i.MX6: mx6q_sabrelite: add CONFIG_REVISION_TAG This is needed to support Freescale-supplied userspaces. At the moment, both the IPU and VPU libraries provided by Freescale in the "imx-lib" package contain routines which scrape the system revision from /proc/cpuinfo. In the VPU library, this information is used to load the proper firmware, allowing a single binary to be used across various i.MX processors. Signed-off-by: Eric Nelson Acked-by: Marek Vasut Acked-by: Stefano Babic --- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 5 +++++ include/configs/mx6qsabrelite.h | 1 + 2 files changed, 6 insertions(+) (limited to 'include') diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 7fe2dc99cb0..1d09a72552f 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -215,6 +215,11 @@ int board_mmc_init(bd_t *bis) } #endif +u32 get_board_rev(void) +{ + return 0x63000 ; +} + #ifdef CONFIG_MXC_SPI iomux_v3_cfg_t ecspi1_pads[] = { /* SS1 */ diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index bb3a46b2f50..a1a2267bd4d 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -33,6 +33,7 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -- cgit v1.3.1 From c338f0b5c60d3b133139539fdfc39d2f2cb29b06 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Sun, 4 Mar 2012 10:51:36 +0000 Subject: i.MX6: mx6qsabrelite: add MACH_TYPE_MX6Q_SABRELITE Allow non-dt kernels to boot Signed-off-by: Troy Kisky --- include/configs/mx6qsabrelite.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/mx6qsabrelite.h b/include/configs/mx6qsabrelite.h index a1a2267bd4d..8bc8a837029 100644 --- a/include/configs/mx6qsabrelite.h +++ b/include/configs/mx6qsabrelite.h @@ -28,6 +28,8 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_MACH_TYPE 3769 + #include #define CONFIG_CMDLINE_TAG -- cgit v1.3.1 From 1fc3bbd17a9812998a7d7c2a3990b0fe2e605a2c Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 22 Mar 2012 14:29:03 +0000 Subject: mx28evk: Provide default values for SPI bus and chip select Provide default values for SPI bus and chip select. This allows the command "sf probe" to work without passing SPI bus and chip select numbers as arguments. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut --- include/configs/mx28evk.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 04967d7d2c6..30814c6c0cb 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -186,6 +186,8 @@ /* SPI Flash */ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 /* this may vary and depends on the installed chip */ #define CONFIG_SPI_FLASH_SST #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 -- cgit v1.3.1 From 94f0003f654fb490ee4be2e2aef1811835f1fb8d Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Thu, 22 Mar 2012 14:29:04 +0000 Subject: configs: imx: Use CONFIG_SF_DEFAULT_CS CONFIG_SPI_FLASH_CS is not used anywhere. Use CONFIG_SF_DEFAULT_CS instead. Signed-off-by: Fabio Estevam Acked-by: Marek Vasut Acked-by: Stefano Babic --- include/configs/efikamx.h | 2 +- include/configs/m28evk.h | 2 +- include/configs/vision2.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h index af542fadcec..120055f1d75 100644 --- a/include/configs/efikamx.h +++ b/include/configs/efikamx.h @@ -113,7 +113,7 @@ #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) #define CONFIG_SF_DEFAULT_SPEED 25000000 diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4d59153706e..4b97c7140d0 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -252,7 +252,7 @@ #ifdef CONFIG_CMD_SF #define CONFIG_SPI_FLASH #define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_CS 2 +#define CONFIG_SF_DEFAULT_CS 2 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 24000000 diff --git a/include/configs/vision2.h b/include/configs/vision2.h index 35b71f79e63..f6904f3f6ab 100644 --- a/include/configs/vision2.h +++ b/include/configs/vision2.h @@ -72,7 +72,7 @@ * Use gpio 4 pin 25 as chip select for SPI flash * This corresponds to gpio 121 */ -#define CONFIG_SPI_FLASH_CS (1 | (121 << 8)) +#define CONFIG_SF_DEFAULT_CS (1 | (121 << 8)) #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define CONFIG_SF_DEFAULT_SPEED 25000000 -- cgit v1.3.1 From 1648a37505e84fc4e5268b026c3f1db862107e00 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:34 +0000 Subject: Add cmd_spl command This adds a spl command to the u-boot. Related config: CONFIG_CMD_SPL activate/deactivate the command CONFIG_CMD_SPL_NAND_OFS Offset in NAND to use Signed-off-by: Simon Schwarz Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk --- common/Makefile | 1 + common/cmd_spl.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++++ doc/README.commands.spl | 31 ++++++++ include/cmd_spl.h | 31 ++++++++ include/image.h | 2 + 5 files changed, 253 insertions(+) create mode 100644 common/cmd_spl.c create mode 100644 doc/README.commands.spl create mode 100644 include/cmd_spl.h (limited to 'include') diff --git a/common/Makefile b/common/Makefile index 04faa0b1de3..ed2fb451497 100644 --- a/common/Makefile +++ b/common/Makefile @@ -162,6 +162,7 @@ COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o endif COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o +COBJS-$(CONFIG_CMD_SPL) += cmd_spl.o # others ifdef CONFIG_DDR_SPD diff --git a/common/cmd_spl.c b/common/cmd_spl.c new file mode 100644 index 00000000000..9ec054af3b3 --- /dev/null +++ b/common/cmd_spl.c @@ -0,0 +1,188 @@ +/* + * Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static const char **subcmd_list[] = { + + [SPL_EXPORT_FDT] = (const char * []) { +#ifdef CONFIG_OF_LIBFDT + "start", + "loados", + #ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + "ramdisk", + #endif + "fdt", + "cmdline", + "bdt", + "prep", +#endif + NULL, + }, + [SPL_EXPORT_ATAGS] = (const char * []) { +#if defined(CONFIG_SETUP_MEMORY_TAGS) || \ + defined(CONFIG_CMDLINE_TAG) || \ + defined(CONFIG_INITRD_TAG) || \ + defined(CONFIG_SERIAL_TAG) || \ + defined(CONFIG_REVISION_TAG) + "start", + "loados", +#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH + "ramdisk", +#endif + "cmdline", + "bdt", + "prep", +#endif + NULL, + }, + NULL +}; + +/* Calls bootm with the parameters given */ +static int call_bootm(int argc, char * const argv[], const char *subcommand[]) +{ + char *bootm_argv[5]; + + int i = 0; + int ret = 0; + int j; + + /* create paramter array */ + bootm_argv[0] = "do_bootm"; + switch (argc) { + case 3: + bootm_argv[4] = argv[2]; /* fdt addr */ + case 2: + bootm_argv[3] = argv[1]; /* initrd addr */ + case 1: + bootm_argv[2] = argv[0]; /* kernel addr */ + } + + + /* + * - do the work - + * exec subcommands of do_bootm to init the images + * data structure + */ + while (subcommand[i] != NULL) { + bootm_argv[1] = (char *)subcommand[i]; + debug("args %d: %s %s ", argc, bootm_argv[0], bootm_argv[1]); + for (j = 0; j < argc; j++) + debug("%s ", bootm_argv[j + 2]); + debug("\n"); + + ret = do_bootm(find_cmd("do_bootm"), 0, argc+2, + bootm_argv); + debug("Subcommand retcode: %d\n", ret); + i++; + } + + if (ret) { + printf("ERROR prep subcommand failed!\n"); + return -1; + } + + return 0; +} + +static cmd_tbl_t cmd_spl_export_sub[] = { + U_BOOT_CMD_MKENT(fdt, 0, 1, (void *)SPL_EXPORT_FDT, "", ""), + U_BOOT_CMD_MKENT(atags, 0, 1, (void *)SPL_EXPORT_ATAGS, "", ""), +}; + +static int spl_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const cmd_tbl_t *c; + + if (argc < 2) /* no subcommand */ + return cmd_usage(cmdtp); + + c = find_cmd_tbl(argv[1], &cmd_spl_export_sub[0], + ARRAY_SIZE(cmd_spl_export_sub)); + if ((c) && ((int)c->cmd <= SPL_EXPORT_LAST)) { + argc -= 2; + argv += 2; + if (call_bootm(argc, argv, subcmd_list[(int)c->cmd])) + return -1; + switch ((int)c->cmd) { + case SPL_EXPORT_FDT: + printf("Argument image is now in RAM: 0x%p\n", + (void *)images.ft_addr); + break; + case SPL_EXPORT_ATAGS: + printf("Argument image is now in RAM at: 0x%p\n", + (void *)gd->bd->bi_boot_params); + break; + } + } else { + /* Unrecognized command */ + return cmd_usage(cmdtp); + } + + return 0; +} + +static cmd_tbl_t cmd_spl_sub[] = { + U_BOOT_CMD_MKENT(export, 0, 1, (void *)SPL_EXPORT, "", ""), +}; + +static int do_spl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + const cmd_tbl_t *c; + int cmd; + + if (argc < 2) /* no subcommand */ + return cmd_usage(cmdtp); + + c = find_cmd_tbl(argv[1], &cmd_spl_sub[0], ARRAY_SIZE(cmd_spl_sub)); + if (c) { + cmd = (int)c->cmd; + switch (cmd) { + case SPL_EXPORT: + argc--; + argv++; + if (spl_export(cmdtp, flag, argc, argv)) + printf("Subcommand failed\n"); + break; + default: + /* unrecognized command */ + return cmd_usage(cmdtp); + } + } else { + /* Unrecognized command */ + return cmd_usage(cmdtp); + } + return 0; +} + +U_BOOT_CMD( + spl, 6 , 1, do_spl, "SPL configuration", + "export [kernel_addr] [initrd_addr] " + "[fdt_addr if = fdt] - export a kernel parameter image\n" + "\t initrd_img can be set to \"-\" if fdt_addr without initrd img is" + "used"); diff --git a/doc/README.commands.spl b/doc/README.commands.spl new file mode 100644 index 00000000000..ac332731eee --- /dev/null +++ b/doc/README.commands.spl @@ -0,0 +1,31 @@ +The spl command is used to export a boot parameter image to RAM. Later +it may implement more functions connected to the SPL. + +SUBCOMMAND EXPORT +To execute the command everything has to be in place as if bootm should be +used. (kernel image, initrd-image, fdt-image etc.) + +export has two subcommands: + atags: exports the ATAGS + fdt: exports the FDT + +Call is: +spl export [kernel_addr] [initrd_addr] [fdt_addr if fdt] + + +TYPICAL CALL + +on OMAP3: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +spl export atags /* export ATAGS */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write 0x80000100 0x680000 0x20000 /* write the image - one page */ + +call with FDT: +nandecc hw +nand read 0x82000000 0x280000 0x400000 /* Read kernel image from NAND*/ +tftpboot 0x80000100 devkit8000.dtb /* Read fdt */ +spl export fdt 0x82000000 - 0x80000100 /* export FDT */ +nand erase 0x680000 0x20000 /* erase - one page */ +nand write 0x680000 0x20000 diff --git a/include/cmd_spl.h b/include/cmd_spl.h new file mode 100644 index 00000000000..6d6206d81b5 --- /dev/null +++ b/include/cmd_spl.h @@ -0,0 +1,31 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _NAND_SPL_H_ +#define _NAND_SPL_H_ + +#define SPL_EXPORT (0x00000001) + +#define SPL_EXPORT_FDT (0x00000001) +#define SPL_EXPORT_ATAGS (0x00000002) +#define SPL_EXPORT_LAST SPL_EXPORT_ATAGS + +#endif /* _NAND_SPL_H_ */ diff --git a/include/image.h b/include/image.h index bbf80f0cac9..a1c6e4e9adb 100644 --- a/include/image.h +++ b/include/image.h @@ -268,6 +268,8 @@ typedef struct bootm_headers { #endif } bootm_headers_t; +extern bootm_headers_t images; + /* * Some systems (for example LWMON) have very short watchdog periods; * we must make sure to split long operations like memmove() or -- cgit v1.3.1 From d38bc97dafe1f98650a674f2d62bcf2a3584a2bb Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:35 +0000 Subject: devkit8000: add config for spl command This adds some configs for devkit8000 to use the new spl command Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk --- include/configs/devkit8000.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 2b6a6ee0918..e323877e269 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -351,4 +351,12 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +/* SPL OS boot options */ +#define CONFIG_CMD_SPL +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ +#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ + 0x400000) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 2d52a9a38c20697b4aeecac0541c7496809e8238 Mon Sep 17 00:00:00 2001 From: Simon Schwarz Date: Thu, 15 Mar 2012 04:01:40 +0000 Subject: devkit8000: Implement and activate direct OS boot - Implements spl_start_uboot() for devkit8000 - Add configs to activate direct OS boot from SPL Signed-off-by: Simon Schwarz CC: Tom Rini CC: Stefano Babic CC: Wolfgang Denk --- board/timll/devkit8000/devkit8000.c | 18 ++++++++++++++++++ include/configs/devkit8000.h | 7 +++++-- 2 files changed, 23 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index dded697f95e..d75e86b32e6 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -41,6 +41,7 @@ #include #include #include "devkit8000.h" +#include #ifdef CONFIG_DRIVER_DM9000 #include #include @@ -161,6 +162,23 @@ void spl_board_prepare_for_linux(void) gpmc_dm9000_config(); } +/* + * devkit8000 specific implementation of spl_start_uboot() + * + * RETURN + * 0 if the button is not pressed + * 1 if the button is pressed + */ +int spl_start_uboot(void) +{ + int val = 0; + if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) { + gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY); + val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY); + gpio_free(CONFIG_SPL_OS_BOOT_KEY); + } + return !val; +} #endif /* diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index e323877e269..eb7c376780d 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -35,7 +35,7 @@ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ - +#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 /* * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM * 64 bytes before this address should be set aside for u-boot.img's @@ -327,7 +327,7 @@ #define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ +#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* NAND boot config */ @@ -352,6 +352,9 @@ #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ /* SPL OS boot options */ +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_OS_BOOT_KEY 26 + #define CONFIG_CMD_SPL #define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ #define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ -- cgit v1.3.1 From 84c21fb16fe474f72109bf665a7cd841e17a2409 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Thu, 15 Mar 2012 04:01:44 +0000 Subject: OMAP3: twister: add support to boot Linux from SPL Signed-off-by: Stefano Babic CC: Tom Rini CC: Wolfgang Denk CC: Simon Schwarz --- board/technexion/twister/twister.c | 23 +++++++++++++++++++++++ include/configs/twister.h | 12 ++++++++++++ 2 files changed, 35 insertions(+) (limited to 'include') diff --git a/board/technexion/twister/twister.c b/board/technexion/twister/twister.c index 50c70ab6031..b92758692d5 100644 --- a/board/technexion/twister/twister.c +++ b/board/technexion/twister/twister.c @@ -136,3 +136,26 @@ int board_mmc_init(bd_t *bis) return omap_mmc_init(0); } #endif + +#ifdef CONFIG_SPL_OS_BOOT +/* + * Do board specific preperation before SPL + * Linux boot + */ +void spl_board_prepare_for_linux(void) +{ + /* init cs for extern lan */ + enable_gpmc_cs_config(gpmc_smc911, &gpmc_cfg->cs[5], + CONFIG_SMC911X_BASE, GPMC_SIZE_16M); +} +int spl_start_uboot(void) +{ + int val = 0; + if (!gpio_request(CONFIG_SPL_OS_BOOT_KEY, "U-Boot key")) { + gpio_direction_input(CONFIG_SPL_OS_BOOT_KEY); + val = gpio_get_value(CONFIG_SPL_OS_BOOT_KEY); + gpio_free(CONFIG_SPL_OS_BOOT_KEY); + } + return val; +} +#endif diff --git a/include/configs/twister.h b/include/configs/twister.h index 64a886d3a4f..a8524816a85 100644 --- a/include/configs/twister.h +++ b/include/configs/twister.h @@ -51,4 +51,16 @@ #define CONFIG_EXTRA_ENV_SETTINGS CONFIG_TAM3517_SETTINGS \ "bootcmd=run nandboot\0" +/* SPL OS boot options */ +#define CONFIG_CMD_SPL +#define CONFIG_CMD_SPL_WRITE_SIZE 0x400 /* 1024 byte */ +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 +#define CONFIG_CMD_SPL_NAND_OFS (CONFIG_SYS_NAND_SPL_KERNEL_OFFS+\ + 0x600000) +#define CONFIG_SPL_OS_BOOT +#define CONFIG_SPL_OS_BOOT_KEY 55 + +#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) +#define CONFIG_SPL_BOARD_INIT + #endif /* __CONFIG_H */ -- cgit v1.3.1 From 88b821bbef64f0b69710ff7d857fc490f72a6d3c Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 21 Mar 2012 00:14:25 +0000 Subject: OMAP3: mt_ventoux: sets its own mtdparts Signed-off-by: Stefano Babic Cc: Tom Rini --- include/configs/mt_ventoux.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/mt_ventoux.h b/include/configs/mt_ventoux.h index 2034b59f476..5db6d576664 100644 --- a/include/configs/mt_ventoux.h +++ b/include/configs/mt_ventoux.h @@ -39,6 +39,16 @@ #define V_PROMPT "mt_ventoux => " #define CONFIG_SYS_PROMPT V_PROMPT +/* + * Set its own mtdparts, different from common + */ +#undef MTDIDS_DEFAULT +#undef MTDPARTS_DEFAULT +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:512k(MLO)," \ + "1m(u-boot),256k(env1)," \ + "256k(env2),8m(ubisystem),-(rootfs)" + /* * FPGA */ -- cgit v1.3.1 From 1441aa6ae8a77ada40407cdfbec783f5559f1646 Mon Sep 17 00:00:00 2001 From: Stefano Babic Date: Wed, 5 Oct 2011 03:08:24 +0000 Subject: Davinci: ea20: use gpio framework to access gpios Drop direct access to SOC's registers and use the function of the GPIO driver for da8xx. [Tom: Remove gpio[68]_base as it's now unused] Signed-off-by: Stefano Babic CC: Bastian Ruppert CC: dzu@denx.de CC: Sandeep Paulraj Signed-off-by: Tom Rini --- board/davinci/ea20/ea20.c | 38 +++++++++----------------------------- include/configs/ea20.h | 2 ++ 2 files changed, 11 insertions(+), 29 deletions(-) (limited to 'include') diff --git a/board/davinci/ea20/ea20.c b/board/davinci/ea20/ea20.c index 9b6c4c047dd..43632c2fd80 100644 --- a/board/davinci/ea20/ea20.c +++ b/board/davinci/ea20/ea20.c @@ -35,7 +35,7 @@ #include #include #include -#include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -172,37 +172,24 @@ static const struct lpsc_resource lpsc[] = { int board_early_init_f(void) { - struct davinci_gpio *gpio6_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK67; - /* PinMux for GPIO */ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) return 1; /* Set the RESETOUTn low */ - writel((readl(&gpio6_base->set_data) & ~(1 << 15)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 15)), &gpio6_base->dir); + gpio_direction_output(111, 0); /* Set U0_SW0 low for UART0 as console*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 10)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 10)), &gpio6_base->dir); + gpio_direction_output(106, 0); /* Set U0_SW1 low for UART0 as console*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 12)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 12)), &gpio6_base->dir); + gpio_direction_output(108, 0); /* Set LCD_B_PWR low to power down LCD Backlight*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 6)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 6)), &gpio6_base->dir); + gpio_direction_output(102, 0); /* Set DISP_ON low to disable LCD output*/ - writel((readl(&gpio6_base->set_data) & ~(1 << 1)), - &gpio6_base->set_data); - writel((readl(&gpio6_base->dir) & ~(1 << 1)), &gpio6_base->dir); + gpio_direction_output(97, 0); #ifndef CONFIG_USE_IRQ irq_init(); @@ -264,12 +251,10 @@ int board_early_init_f(void) &davinci_syscfg_regs->mstpri[2]); /* Set LCD_B_PWR low to power up LCD Backlight*/ - writel((readl(&gpio6_base->set_data) | (1 << 6)), - &gpio6_base->set_data); + gpio_set_value(102, 1); /* Set DISP_ON low to disable LCD output*/ - writel((readl(&gpio6_base->set_data) | (1 << 1)), - &gpio6_base->set_data); + gpio_set_value(97, 1); return 0; } @@ -291,17 +276,12 @@ int board_init(void) int board_late_init(void) { - struct davinci_gpio *gpio8_base = - (struct davinci_gpio *)DAVINCI_GPIO_BANK8; - /* PinMux for HALTEN */ if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0) return 1; /* Set HALTEN to high */ - writel((readl(&gpio8_base->set_data) | (1 << 6)), - &gpio8_base->set_data); - writel((readl(&gpio8_base->dir) & ~(1 << 6)), &gpio8_base->dir); + gpio_direction_output(134, 1); setenv("stdout", "serial"); diff --git a/include/configs/ea20.h b/include/configs/ea20.h index b4610d9474f..e059b308266 100644 --- a/include/configs/ea20.h +++ b/include/configs/ea20.h @@ -48,6 +48,7 @@ #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_SYS_TEXT_BASE 0xc1080000 +#define CONFIG_DA8XX_GPIO /* * Memory Info @@ -167,6 +168,7 @@ #define CONFIG_CMD_SAVES #define CONFIG_CMD_MEMORY #define CONFIG_CMD_I2C +#define CONFIG_CMD_GPIO #ifdef CONFIG_CMD_BDI #define CONFIG_CLOCKS -- cgit v1.3.1 From 24efef90c4c9ddc65ae3bd982b09b99b2d0cd4e0 Mon Sep 17 00:00:00 2001 From: Heiko Schocher Date: Wed, 7 Mar 2012 04:10:00 +0000 Subject: ARM: davinci: fixes for cam_enc_4xx board - change CONFIG_ENV_RANGE to contain 2 nand erase blocks, one for bad block reserve. - remove from the envvariable "img_writeramdisk" the ubifsmount command, as it is not needed. - erase the hole mtd partition containing u-boot - save environment variable "dvn_app_vers" and "dvn_boot_vers" only after installing the new image. changes requested from Marek Vasut: - arm, davinci: fix eldk-4.2 warnings for cam_enc_4xx board - get rid of run_command2 usage needed since patch: commit 009dde1955583e306cf904c864068f3acb0db499 Author: Simon Glass Date: Tue Feb 14 19:59:20 2012 +0000 Rename run_command2() to run_command() is now in mainline. - add CONFIG_SPL_LIBGENERIC_SUPPORT support - remove CONFIG_CMD_PXE support - fix warning: cam_enc_4xx.c: In function 'menu_handle': cam_enc_4xx.c:609: warning: dereferencing type-punned pointer will break strict-aliasing rules - fix error: arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking with -N Signed-off-by: Heiko Schocher Cc: Marek Vasut Cc: Tom Rini Cc: Fletzer Martin Cc: Wolfgang Denk --- board/ait/cam_enc_4xx/cam_enc_4xx.c | 55 +++++++++++++++++++++++++----------- board/ait/cam_enc_4xx/config.mk | 7 +++++ board/ait/cam_enc_4xx/u-boot-spl.lds | 2 +- include/configs/cam_enc_4xx.h | 13 +++++---- 4 files changed, 54 insertions(+), 23 deletions(-) (limited to 'include') diff --git a/board/ait/cam_enc_4xx/cam_enc_4xx.c b/board/ait/cam_enc_4xx/cam_enc_4xx.c index bb29cf3f58b..32b28f92705 100644 --- a/board/ait/cam_enc_4xx/cam_enc_4xx.c +++ b/board/ait/cam_enc_4xx/cam_enc_4xx.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -554,7 +555,7 @@ static char *menu_handle(struct menu_display *display) { struct menu *m; int i; - char *choice = NULL; + void *choice = NULL; char key[2]; int ret; char *s; @@ -606,7 +607,7 @@ static char *menu_handle(struct menu_display *display) sprintf(key, "%d", 1); menu_default_set(m, key); - if (menu_get_choice(m, (void **)&choice) != 1) + if (menu_get_choice(m, &choice) != 1) debug("Problem picking a choice!\n"); menu_destroy(m); @@ -653,7 +654,7 @@ static int ait_writeublheader(void) sprintf(s, "%lx", i); ret = setenv("header_addr", s); if (ret == 0) - ret = run_command2("run img_writeheader", 0); + ret = run_command("run img_writeheader", 0); if (ret != 0) break; } @@ -697,7 +698,7 @@ static int ait_menu_install_images(void) setenv("filesize", s); switch (imgs[count].subtype) { case FIT_SUBTYPE_DF_ENV_IMAGE: - ret = run_command2("run img_writedfenv", 0); + ret = run_command("run img_writedfenv", 0); break; case FIT_SUBTYPE_RAMDISK_IMAGE: t = getenv("img_volume"); @@ -713,16 +714,16 @@ static int ait_menu_install_images(void) if (ret != 0) break; - ret = run_command2("run img_writeramdisk", 0); + ret = run_command("run img_writeramdisk", 0); break; case FIT_SUBTYPE_SPL_IMAGE: - ret = run_command2("run img_writespl", 0); + ret = run_command("run img_writespl", 0); break; case FIT_SUBTYPE_UBL_HEADER: ret = ait_writeublheader(); break; case FIT_SUBTYPE_UBOOT_IMAGE: - ret = run_command2("run img_writeuboot", 0); + ret = run_command("run img_writeuboot", 0); break; default: /* not supported type */ @@ -731,8 +732,19 @@ static int ait_menu_install_images(void) count++; } /* now save dvn_* and img_volume env vars to new values */ - if (ret == 0) - ret = run_command2("run savenewvers", 0); + if (ret == 0) { + t = getenv("x_dvn_boot_vers"); + if (t) + setenv("dvn_boot_vers", t); + + t = getenv("x_dvn_app_vers"); + if (t) + setenv("dvn_boot_vers", t); + + setenv("x_dvn_boot_vers", NULL); + setenv("x_dvn_app_vers", NULL); + ret = run_command("run savenewvers", 0); + } return ret; } @@ -749,6 +761,8 @@ static int ait_menu_evaluate_load(char *choice) break; case '2': /* cancel, back to main */ + setenv("x_dvn_boot_vers", NULL); + setenv("x_dvn_app_vers", NULL); break; } @@ -961,7 +975,7 @@ static int ait_menu_check_image(void) if (s) { ret = strcmp(s, imgs[found_uboot].desc); if (ret != 0) { - setenv("dvn_boot_vers", + setenv("x_dvn_boot_vers", imgs[found_uboot].desc); } else { found_uboot = -1; @@ -976,7 +990,7 @@ static int ait_menu_check_image(void) if (s) { ret = strcmp(s, imgs[found_ramdisk].desc); if (ret != 0) { - setenv("dvn_app_vers", + setenv("x_dvn_app_vers", imgs[found_ramdisk].desc); } else { found_ramdisk = -1; @@ -1005,7 +1019,7 @@ static int ait_menu_evaluate_update(char *choice) break; case '2': /* load image */ - ret = run_command2("run load_img", 0); + ret = run_command("run load_img", 0); printf("ret: %d\n", ret); if (ret) return MENU_UPDATE; @@ -1073,9 +1087,9 @@ int menu_show(int bootdelay) { int ret; - run_command2("run saveparms", 0); + run_command("run saveparms", 0); ret = ait_menu_show(&ait_main, bootdelay); - run_command2("run restoreparms", 0); + run_command("run restoreparms", 0); if (ret == MENU_EXIT_BOOTCMD) return 0; @@ -1085,8 +1099,17 @@ int menu_show(int bootdelay) void menu_display_statusline(struct menu *m) { - printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", - getenv("dvn_boot_vers"), getenv("dvn_app_vers")); + char *s1, *s2; + + s1 = getenv("x_dvn_boot_vers"); + if (!s1) + s1 = getenv("dvn_boot_vers"); + + s2 = getenv("x_dvn_app_vers"); + if (!s2) + s2 = getenv("dvn_app_vers"); + + printf("State: dvn_boot_vers: %s dvn_app_vers: %s\n", s1, s2); return; } #endif diff --git a/board/ait/cam_enc_4xx/config.mk b/board/ait/cam_enc_4xx/config.mk index b1f9b6c221d..744b927f1e2 100644 --- a/board/ait/cam_enc_4xx/config.mk +++ b/board/ait/cam_enc_4xx/config.mk @@ -12,4 +12,11 @@ PAD_TO := 12320 UBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/ublimage.cfg ifndef CONFIG_SPL_BUILD ALL-y += $(obj)u-boot.ubl +else +# as SPL_TEXT_BASE is not page-aligned, we need for some +# linkers the -n flag (Do not page align data), to prevent +# the following error message: +# arm-linux-ld: u-boot-spl: Not enough room for program headers, try linking +# with -N +LDFLAGS_u-boot-spl += -n endif diff --git a/board/ait/cam_enc_4xx/u-boot-spl.lds b/board/ait/cam_enc_4xx/u-boot-spl.lds index 6f6e065a9f1..52c986e8a9e 100644 --- a/board/ait/cam_enc_4xx/u-boot-spl.lds +++ b/board/ait/cam_enc_4xx/u-boot-spl.lds @@ -32,7 +32,7 @@ OUTPUT_ARCH(arm) ENTRY(_start) SECTIONS { - . = 0x00000000; + . = CONFIG_SPL_TEXT_BASE; . = ALIGN(4); .text : diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h index 0fee53f750c..99856ebfdf2 100644 --- a/include/configs/cam_enc_4xx.h +++ b/include/configs/cam_enc_4xx.h @@ -161,15 +161,14 @@ #define CONFIG_MENU #define CONFIG_MENU_SHOW #define CONFIG_FIT -#define CONFIG_CMD_PXE #define CONFIG_BOARD_IMG_ADDR_R 0x80000000 #ifdef CONFIG_NAND_DAVINCI #define CONFIG_ENV_SIZE (16 << 10) #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x180000 +#define CONFIG_ENV_RANGE 0x040000 #define CONFIG_ENV_OFFSET_REDUND 0x1c0000 -#define CONFIG_ENV_RANGE 0x020000 #undef CONFIG_ENV_IS_IN_FLASH #endif @@ -220,6 +219,7 @@ /* Defines for SPL */ #define CONFIG_SPL +#define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_NAND_LOAD @@ -229,7 +229,7 @@ #define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds" #define CONFIG_SPL_STACK (0x00010000 + 0x7f00) -#define CONFIG_SPL_TEXT_BASE 0x0000020 /*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/ #define CONFIG_SPL_MAX_SIZE 12320 #ifndef CONFIG_SPL_BUILD @@ -274,6 +274,7 @@ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 +#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000 /* for UBL header */ #define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE) @@ -429,7 +430,7 @@ " 0 3000;nandrbl uboot\0" \ "writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ - xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \ ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \ " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ @@ -466,14 +467,14 @@ "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \ "img_writeuboot=nandrbl uboot;" \ "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ - xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) \ + xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \ ";nand write ${img_addr_r} " \ xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \ xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \ "img_writedfenv=ubi part ubi 2048;" \ "ubi write ${img_addr_r} default ${filesize}\0" \ "img_volume=rootfs1\0" \ - "img_writeramdisk=ubi part ubi 2048;ubifsmount ${img_volume};" \ + "img_writeramdisk=ubi part ubi 2048;" \ "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \ "load_img=tftp ${fit_addr_r} ${img_file}\0" \ "net_nfs=run load_kernel; " \ -- cgit v1.3.1 From 7b81649a053826dc31804d3260a44ff599a9542a Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:53 +0000 Subject: ARM: highbank: change TEXT_BASE to 0x8000 Make some space at the beginning of RAM so the FDT can be loaded to a known fixed address at 0x1000. Signed-off-by: Rob Herring --- include/configs/highbank.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 56047330361..e7172734916 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -120,7 +120,7 @@ #define CONFIG_ENV_IS_NOWHERE #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_TEXT_BASE 0x00001000 +#define CONFIG_SYS_TEXT_BASE 0x00008000 #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 #define CONFIG_SKIP_LOWLEVEL_INIT -- cgit v1.3.1 From 877012df309329a9264e6e9558d4f71bfa0cddbe Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 1 Feb 2012 16:57:54 +0000 Subject: ARM: highbank: Add boot counter support Add boot counter support using an sysreg which is persistent across reset. Signed-off-by: Rob Herring --- arch/arm/cpu/armv7/highbank/Makefile | 2 +- arch/arm/cpu/armv7/highbank/bootcount.c | 36 +++++++++++++++++++++++++++++++++ board/highbank/highbank.c | 1 + include/configs/highbank.h | 3 +++ 4 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/highbank/bootcount.c (limited to 'include') diff --git a/arch/arm/cpu/armv7/highbank/Makefile b/arch/arm/cpu/armv7/highbank/Makefile index 76faeb0fe10..917c3a36ba5 100644 --- a/arch/arm/cpu/armv7/highbank/Makefile +++ b/arch/arm/cpu/armv7/highbank/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS := timer.o +COBJS := timer.o bootcount.o SOBJS := SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/arch/arm/cpu/armv7/highbank/bootcount.c b/arch/arm/cpu/armv7/highbank/bootcount.c new file mode 100644 index 00000000000..9ca06567a8e --- /dev/null +++ b/arch/arm/cpu/armv7/highbank/bootcount.c @@ -0,0 +1,36 @@ +/* + * Copyright 2011 Calxeda, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include +#include + +#ifdef CONFIG_BOOTCOUNT_LIMIT +void bootcount_store(ulong a) +{ + writel((BOOTCOUNT_MAGIC & 0xffff0000) | a, CONFIG_SYS_BOOTCOUNT_ADDR); +} + +ulong bootcount_load(void) +{ + u32 tmp = readl(CONFIG_SYS_BOOTCOUNT_ADDR); + + if ((tmp & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return tmp & 0x0000ffff; +} +#endif diff --git a/board/highbank/highbank.c b/board/highbank/highbank.c index 5f34fec4501..096e2f63727 100644 --- a/board/highbank/highbank.c +++ b/board/highbank/highbank.c @@ -21,6 +21,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; diff --git a/include/configs/highbank.h b/include/configs/highbank.h index e7172734916..801f4ae67c1 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -41,6 +41,9 @@ #define CONFIG_BAUDRATE 38400 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfff3cf0c + #define CONFIG_MISC_INIT_R #define CONFIG_SCSI_AHCI #define CONFIG_SCSI_AHCI_PLAT -- cgit v1.3.1 From a34e8549480c41057aa47cea50c0785fd9ce4f4a Mon Sep 17 00:00:00 2001 From: Jason Hobbs Date: Wed, 1 Feb 2012 16:57:56 +0000 Subject: ARM: highbank: change env config to use nvram Update the highbank config to use env from NVRAM. Also remove extra env settings as they are not used unless the default env is used. Signed-off-by: Jason Hobbs Signed-off-by: Rob Herring --- include/configs/highbank.h | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) (limited to 'include') diff --git a/include/configs/highbank.h b/include/configs/highbank.h index 801f4ae67c1..520fa4cc9ed 100644 --- a/include/configs/highbank.h +++ b/include/configs/highbank.h @@ -93,12 +93,6 @@ #define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtaddr_r=0x600000\0" \ - "pxefile_addr_r=0x700000\0" \ - "kernel_addr_r=0x800000\0" \ - "ramdisk_addr_r=0x01000000\0" \ - /*----------------------------------------------------------------------- * Stack sizes * @@ -118,9 +112,13 @@ #define CONFIG_SYS_MEMTEST_START 0x100000 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_IS_NOWHERE +/* Environment data setup +*/ +#define CONFIG_ENV_IS_IN_NVRAM +#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ +#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ +#define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */ +#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_TEXT_BASE 0x00008000 -- cgit v1.3.1 From b3541c1ac93d4e4b786d28ef2f6dc5976a580af5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Thu, 15 Mar 2012 18:33:22 +0000 Subject: i.MX28: Make use of the bounce buffer This allows i.MX28 MMC host to fully utilize DMA transfers and caches, greatly improving speed. Signed-off-by: Marek Vasut Cc: Fabio Estevam --- include/configs/m28evk.h | 1 + include/configs/mx28evk.h | 1 + 2 files changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 4b97c7140d0..8b83180da83 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -140,6 +140,7 @@ */ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC +#define CONFIG_MMC_BOUNCE_BUFFER #define CONFIG_GENERIC_MMC #define CONFIG_MXS_MMC #endif diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h index 30814c6c0cb..cdcc6e0eab3 100644 --- a/include/configs/mx28evk.h +++ b/include/configs/mx28evk.h @@ -138,6 +138,7 @@ #ifdef CONFIG_CMD_MMC #define CONFIG_MMC #define CONFIG_GENERIC_MMC +#define CONFIG_MMC_BOUNCE_BUFFER #define CONFIG_MXS_MMC #endif -- cgit v1.3.1 From 2c4b3c19a1fe1c4e9ef1ec457cf34821368288d7 Mon Sep 17 00:00:00 2001 From: Eric Nelson Date: Thu, 15 Mar 2012 18:33:24 +0000 Subject: net: force PKTALIGN to ARCH_DMA_MINALIGN This will prevent the need for architectures whose DMA alignment is greater than 32 to have bounce buffers. Signed-off-by: Eric Nelson --- include/net.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/net.h b/include/net.h index 556078518b5..ee11f82ccc8 100644 --- a/include/net.h +++ b/include/net.h @@ -16,6 +16,7 @@ #include #endif /* CONFIG_8xx */ +#include #include /* for nton* / ntoh* stuff */ @@ -31,7 +32,7 @@ # define PKTBUFSRX 4 #endif -#define PKTALIGN 32 +#define PKTALIGN ARCH_DMA_MINALIGN /* IPv4 addresses are always 32 bits in size */ typedef u32 IPaddr_t; -- cgit v1.3.1 From a53f4a29ac62a2e83d35a4a7b6d6969cf95a5902 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Tue, 17 Jan 2012 08:20:50 +0000 Subject: fdt: Add fdtdec_find_aliases() to deal with alias nodes Stephen Warren pointed out that we should use nodes whether or not they have an alias in the /aliases section. The aliases section specifies the order so far as it can, but is not essential. Operating without alisses is useful when the enumerated order of nodes does not matter (admittedly rare in U-Boot). This is considerably more complex, and it is important to keep this complexity out of driver code. This patch creates a function fdtdec_find_aliases() which returns an ordered list of node offsets for a particular compatible ID, taking account of alias nodes. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 47 ++++++++++++++++++++++ lib/fdtdec.c | 116 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index d871cdd1c10..492431c69b1 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -126,3 +126,50 @@ int fdtdec_get_is_enabled(const void *blob, int node, int default_val); * if not. */ int fdtdec_check_fdt(void); + +/** + * Find the nodes for a peripheral and return a list of them in the correct + * order. This is used to enumerate all the peripherals of a certain type. + * + * To use this, optionally set up a /aliases node with alias properties for + * a peripheral. For example, for usb you could have: + * + * aliases { + * usb0 = "/ehci@c5008000"; + * usb1 = "/ehci@c5000000"; + * }; + * + * Pass "usb" as the name to this function and will return a list of two + * nodes offsets: /ehci@c5008000 and ehci@c5000000. + * + * All nodes returned will match the compatible ID, as it is assumed that + * all peripherals use the same driver. + * + * If no alias node is found, then the node list will be returned in the + * order found in the fdt. If the aliases mention a node which doesn't + * exist, then this will be ignored. If nodes are found with no aliases, + * they will be added in any order. + * + * If there is a gap in the aliases, then this function return a 0 node at + * that position. The return value will also count these gaps. + * + * This function checks node properties and will not return nodes which are + * marked disabled (status = "disabled"). + * + * @param blob FDT blob to use + * @param name Root name of alias to search for + * @param id Compatible ID to look for + * @param node_list Place to put list of found nodes + * @param maxcount Maximum number of nodes to find + * @return number of nodes found on success, FTD_ERR_... on error + */ +int fdtdec_find_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + +/* + * Get the name for a compatible ID + * + * @param id Compatible ID to look for + * @return compatible string for that id + */ +const char *fdtdec_get_compatible(enum fdt_compat_id id); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 0f871638c63..55d5bdf645f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -35,6 +35,13 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { }; +const char *fdtdec_get_compatible(enum fdt_compat_id id) +{ + /* We allow reading of the 'unknown' ID for testing purposes */ + assert(id >= 0 && id < COMPAT_COUNT); + return compat_names[id]; +} + /** * Look in the FDT for an alias with the given name and return its node. * @@ -132,6 +139,115 @@ int fdtdec_next_alias(const void *blob, const char *name, return err ? -FDT_ERR_NOTFOUND : node; } +/* TODO: Can we tighten this code up a little? */ +int fdtdec_find_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount) +{ + int name_len = strlen(name); + int nodes[maxcount]; + int num_found = 0; + int offset, node; + int alias_node; + int count; + int i, j; + + /* find the alias node if present */ + alias_node = fdt_path_offset(blob, "/aliases"); + + /* + * start with nothing, and we can assume that the root node can't + * match + */ + memset(nodes, '\0', sizeof(nodes)); + + /* First find all the compatible nodes */ + for (node = count = 0; node >= 0 && count < maxcount;) { + node = fdtdec_next_compatible(blob, node, id); + if (node >= 0) + nodes[count++] = node; + } + if (node >= 0) + debug("%s: warning: maxcount exceeded with alias '%s'\n", + __func__, name); + + /* Now find all the aliases */ + memset(node_list, '\0', sizeof(*node_list) * maxcount); + + for (offset = fdt_first_property_offset(blob, alias_node); + offset > 0; + offset = fdt_next_property_offset(blob, offset)) { + const struct fdt_property *prop; + const char *path; + int number; + int found; + + node = 0; + prop = fdt_get_property_by_offset(blob, offset, NULL); + path = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + if (prop->len && 0 == strncmp(path, name, name_len)) + node = fdt_path_offset(blob, prop->data); + if (node <= 0) + continue; + + /* Get the alias number */ + number = simple_strtoul(path + name_len, NULL, 10); + if (number < 0 || number >= maxcount) { + debug("%s: warning: alias '%s' is out of range\n", + __func__, path); + continue; + } + + /* Make sure the node we found is actually in our list! */ + found = -1; + for (j = 0; j < count; j++) + if (nodes[j] == node) { + found = j; + break; + } + + if (found == -1) { + debug("%s: warning: alias '%s' points to a node " + "'%s' that is missing or is not compatible " + " with '%s'\n", __func__, path, + fdt_get_name(blob, node, NULL), + compat_names[id]); + continue; + } + + /* + * Add this node to our list in the right place, and mark + * it as done. + */ + if (fdtdec_get_is_enabled(blob, node)) { + node_list[number] = node; + if (number >= num_found) + num_found = number + 1; + } + nodes[j] = 0; + } + + /* Add any nodes not mentioned by an alias */ + for (i = j = 0; i < maxcount; i++) { + if (!node_list[i]) { + for (; j < maxcount; j++) + if (nodes[j] && + fdtdec_get_is_enabled(blob, nodes[j])) + break; + + /* Have we run out of nodes to add? */ + if (j == maxcount) + break; + + assert(!node_list[i]); + node_list[i] = nodes[j++]; + if (i >= num_found) + num_found = i + 1; + } + } + + return num_found; +} + /* * This function is a little odd in that it accesses global data. At some * point if the architecture board.c files merge this will make more sense. -- cgit v1.3.1 From f88fe2ded4acd035826018f33c6a67033a8f5d07 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:34 +0000 Subject: fdt: Tidy up a few fdtdec problems This fixes five trivial issues in fdtdec.c: 1. fdtdec_get_is_enabled() doesn't really need a default value 2. The fdt must be word-aligned, since otherwise it will fail on ARM 3. The compat_names[] array is missing its first element. This is needed only because the first fdt_compat_id is defined to be invalid. 4. Added a header prototype for fdtdec_next_compatible() 5. Change fdtdec_next_alias() to only increment its 'upto' parameter on success, to make the display error messages in the caller easier. Signed-off-by: Simon Glass Acked-by: Gerald Van Baren Acked-by: Stephen Warren Signed-off-by: Tom Warren --- include/fdtdec.h | 23 +++++++++++++++++++---- lib/fdtdec.c | 22 ++++++++++++++++------ 2 files changed, 35 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 492431c69b1..5469c16abd0 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -81,6 +81,21 @@ enum fdt_compat_id { int fdtdec_next_alias(const void *blob, const char *name, enum fdt_compat_id id, int *upto); +/** + * Find the next compatible node for a peripheral. + * + * Do the first call with node = 0. This function will return a pointer to + * the next compatible node. Next time you call this function, pass the + * value returned, and the next node will be provided. + * + * @param blob FDT blob to use + * @param node Start node for search + * @param id Compatible ID to look for (enum fdt_compat_id) + * @return offset of next compatible node, or -FDT_ERR_NOTFOUND if no more + */ +int fdtdec_next_compatible(const void *blob, int node, + enum fdt_compat_id id); + /** * Look up an address property in a node and return it as an address. * The property must hold either one address with no trailing data or @@ -112,14 +127,14 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, * Checks whether a node is enabled. * This looks for a 'status' property. If this exists, then returns 1 if * the status is 'ok' and 0 otherwise. If there is no status property, - * it returns the default value. + * it returns 1 on the assumption that anything mentioned should be enabled + * by default. * * @param blob FDT blob * @param node node to examine - * @param default_val default value to return if no 'status' property exists - * @return integer value 0/1, if found, or default_val if not + * @return integer value 0 (not enabled) or 1 (enabled) */ -int fdtdec_get_is_enabled(const void *blob, int node, int default_val); +int fdtdec_get_is_enabled(const void *blob, int node); /** * Checks whether we have a valid fdt available to control U-Boot, and panic diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 55d5bdf645f..bf3171730c4 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; */ #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { + COMPAT(UNKNOWN, ""), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) @@ -91,14 +92,21 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, return default_val; } -int fdtdec_get_is_enabled(const void *blob, int node, int default_val) +int fdtdec_get_is_enabled(const void *blob, int node) { const char *cell; + /* + * It should say "okay", so only allow that. Some fdts use "ok" but + * this is a bug. Please fix your device tree source file. See here + * for discussion: + * + * http://www.mail-archive.com/u-boot@lists.denx.de/msg71598.html + */ cell = fdt_getprop(blob, node, "status", NULL); if (cell) - return 0 == strcmp(cell, "ok"); - return default_val; + return 0 == strcmp(cell, "okay"); + return 1; } enum fdt_compat_id fd_dec_lookup(const void *blob, int node) @@ -129,14 +137,16 @@ int fdtdec_next_alias(const void *blob, const char *name, /* snprintf() is not available */ assert(strlen(name) < MAX_STR_LEN); sprintf(str, "%.*s%d", MAX_STR_LEN, name, *upto); - (*upto)++; node = find_alias_node(blob, str); if (node < 0) return node; err = fdt_node_check_compatible(blob, node, compat_names[id]); if (err < 0) return err; - return err ? -FDT_ERR_NOTFOUND : node; + if (err) + return -FDT_ERR_NOTFOUND; + (*upto)++; + return node; } /* TODO: Can we tighten this code up a little? */ @@ -256,7 +266,7 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, int fdtdec_check_fdt(void) { /* We must have an fdt */ - if (fdt_check_header(gd->fdt_blob)) + if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) panic("No valid fdt found - please append one to U-Boot\n" "binary or define CONFIG_OF_EMBED\n"); return 0; -- cgit v1.3.1 From d17da65560f15f74f8efe321044b9cdf45e24c9b Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:35 +0000 Subject: fdt: Add functions to access phandles, arrays and bools Add a function to look up a property which is a phandle in a node, and another to read a fixed-length integer array from an fdt property. Also add a function to read boolean properties, although there is no actual boolean type in U-Boot. Signed-off-by: Simon Glass Acked-by: Gerald Van Baren Acked-by: Stephen Warren Signed-off-by: Tom Warren --- include/fdtdec.h | 39 +++++++++++++++++++++++++++++++++ lib/fdtdec.c | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 106 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 5469c16abd0..a4467000b7f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -188,3 +188,42 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, * @return compatible string for that id */ const char *fdtdec_get_compatible(enum fdt_compat_id id); + +/* Look up a phandle and follow it to its node. Then return the offset + * of that node. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return node offset if found, -ve error code on error + */ +int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name); + +/** + * Look up a property in a node and return its contents in an integer + * array of given length. The property must have at least enough data for + * the array (4*count bytes). It may have more, but this will be ignored. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param array array to fill with data + * @param count number of array elements + * @return 0 if ok, or -FDT_ERR_NOTFOUND if the property is not found, + * or -FDT_ERR_BADLAYOUT if not enough data + */ +int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, + u32 *array, int count); + +/** + * Look up a boolean property in a node and return it. + * + * A boolean properly is true if present in the device tree and false if not + * present, regardless of its value. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @return 1 if the properly is present; 0 if it isn't present + */ +int fdtdec_get_bool(const void *blob, int node, const char *prop_name); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index bf3171730c4..13bb47002e4 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -271,3 +271,70 @@ int fdtdec_check_fdt(void) "binary or define CONFIG_OF_EMBED\n"); return 0; } + +int fdtdec_lookup_phandle(const void *blob, int node, const char *prop_name) +{ + const u32 *phandle; + int lookup; + + phandle = fdt_getprop(blob, node, prop_name, NULL); + if (!phandle) + return -FDT_ERR_NOTFOUND; + + lookup = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*phandle)); + return lookup; +} + +/** + * Look up a property in a node and check that it has a minimum length. + * + * @param blob FDT blob + * @param node node to examine + * @param prop_name name of property to find + * @param min_len minimum property length in bytes + * @param err 0 if ok, or -FDT_ERR_NOTFOUND if the property is not + found, or -FDT_ERR_BADLAYOUT if not enough data + * @return pointer to cell, which is only valid if err == 0 + */ +static const void *get_prop_check_min_len(const void *blob, int node, + const char *prop_name, int min_len, int *err) +{ + const void *cell; + int len; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + *err = -FDT_ERR_NOTFOUND; + else if (len < min_len) + *err = -FDT_ERR_BADLAYOUT; + else + *err = 0; + return cell; +} + +int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, + u32 *array, int count) +{ + const u32 *cell; + int i, err = 0; + + debug("%s: %s\n", __func__, prop_name); + cell = get_prop_check_min_len(blob, node, prop_name, + sizeof(u32) * count, &err); + if (!err) { + for (i = 0; i < count; i++) + array[i] = fdt32_to_cpu(cell[i]); + } + return err; +} + +int fdtdec_get_bool(const void *blob, int node, const char *prop_name) +{ + const s32 *cell; + int len; + + debug("%s: %s\n", __func__, prop_name); + cell = fdt_getprop(blob, node, prop_name, &len); + return cell != NULL; +} -- cgit v1.3.1 From ed3ee5cd0640979a200710b9eefa210a617b19ff Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:36 +0000 Subject: fdt: Add basic support for decoding GPIO definitions This adds some support into fdtdec for reading GPIO definitions from the fdt. We permit up to FDT_GPIO_MAX GPIOs in the system. Each GPIO is of the form: gpio-function-name = ; where: phandle is a pointer to the GPIO node gpio_num is the number of the GPIO (0 to 223) flags is a flag, as follows: bit meaning 0 0=polarity normal, 1=active low (inverted) An example is: enable-propounder-gpios = <&gpio 43 0>; which means that GPIO 43 is used to enable the propounder (setting the GPIO high), or that you can detect that the propounder is enabled by checking if the GPIO is high (the fdt does not indicate input/output). Two main functions are provided: fdtdec_decode_gpio() reads a GPIO property from an fdt node and decodes it into a structure. fdtdec_setup_gpio() sets up the GPIO by calling gpio_request for you. Both functions can cope with the property being missing, which is taken to mean that that GPIO function is not available or is not needed. [For reference, from Stephen Warren . It may be that we add this extra complexity later if needed: The correct way to parse such a GPIO property in general is: * Read the first cell. * Find the node referenced by the phandle (the controller). * Ensure property gpio-controller is present in the controller node. * Read property #gpio-cells from the controller node. * Extract #gpio-cells from the original property. * Keep processing more cells from the original property; there may be multiple GPIOs listed. According to the binding documentation in the Linux kernel, Samsung Exynos4 doesn't use this format, and while all other chips do have a flags cell, about 50% of the controllers indicate the cell is unused. ] Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 45 ++++++++++++++++++++++++++++++++ lib/fdtdec.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 124 insertions(+) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index a4467000b7f..2f3842d9a30 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -61,6 +61,23 @@ enum fdt_compat_id { COMPAT_COUNT, }; +/* GPIOs are numbered from 0 */ +enum { + FDT_GPIO_NONE = -1U, /* an invalid GPIO used to end our list */ + + FDT_GPIO_ACTIVE_LOW = 1 << 0, /* input is active low (else high) */ +}; + +/* This is the state of a GPIO pin as defined by the fdt */ +struct fdt_gpio_state { + const char *name; /* name of the fdt property defining this */ + uint gpio; /* GPIO number, or FDT_GPIO_NONE if none */ + u8 flags; /* FDT_GPIO_... flags */ +}; + +/* This tells us whether a fdt_gpio_state record is valid or not */ +#define fdt_gpio_isvalid(x) ((x)->gpio != FDT_GPIO_NONE) + /** * Find the next numbered alias for a peripheral. This is used to enumerate * all the peripherals of a certain type. @@ -227,3 +244,31 @@ int fdtdec_get_int_array(const void *blob, int node, const char *prop_name, * @return 1 if the properly is present; 0 if it isn't present */ int fdtdec_get_bool(const void *blob, int node, const char *prop_name); + +/** + * Decode a single GPIOs from an FDT. + * + * If the property is not found, then the GPIO structure will still be + * initialised, with gpio set to FDT_GPIO_NONE. This makes it easy to + * provide optional GPIOs. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio gpio elements to fill from FDT + * @return 0 if ok, -FDT_ERR_NOTFOUND if the property is missing. + */ +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio); + +/** + * Set up a GPIO pin according to the provided gpio information. At present this + * just requests the GPIO. + * + * If the gpio is FDT_GPIO_NONE, no action is taken. This makes it easy to + * deal with optional GPIOs. + * + * @param gpio GPIO info to use for set up + * @return 0 if all ok or gpio was FDT_GPIO_NONE; -1 on error + */ +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 13bb47002e4..de83226ed1f 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -24,6 +24,9 @@ #include #include +/* we need the generic GPIO interface here */ +#include + DECLARE_GLOBAL_DATA_PTR; /* @@ -338,3 +341,79 @@ int fdtdec_get_bool(const void *blob, int node, const char *prop_name) cell = fdt_getprop(blob, node, prop_name, &len); return cell != NULL; } + +/** + * Decode a list of GPIOs from an FDT. This creates a list of GPIOs with no + * terminating item. + * + * @param blob FDT blob to use + * @param node Node to look at + * @param prop_name Node property name + * @param gpio Array of gpio elements to fill from FDT. This will be + * untouched if either 0 or an error is returned + * @param max_count Maximum number of elements allowed + * @return number of GPIOs read if ok, -FDT_ERR_BADLAYOUT if max_count would + * be exceeded, or -FDT_ERR_NOTFOUND if the property is missing. + */ +static int fdtdec_decode_gpios(const void *blob, int node, + const char *prop_name, struct fdt_gpio_state *gpio, + int max_count) +{ + const struct fdt_property *prop; + const u32 *cell; + const char *name; + int len, i; + + debug("%s: %s\n", __func__, prop_name); + assert(max_count > 0); + prop = fdt_get_property(blob, node, prop_name, &len); + if (!prop) { + debug("FDT: %s: property '%s' missing\n", __func__, prop_name); + return -FDT_ERR_NOTFOUND; + } + + /* We will use the name to tag the GPIO */ + name = fdt_string(blob, fdt32_to_cpu(prop->nameoff)); + cell = (u32 *)prop->data; + len /= sizeof(u32) * 3; /* 3 cells per GPIO record */ + if (len > max_count) { + debug("FDT: %s: too many GPIOs / cells for " + "property '%s'\n", __func__, prop_name); + return -FDT_ERR_BADLAYOUT; + } + + /* Read out the GPIO data from the cells */ + for (i = 0; i < len; i++, cell += 3) { + gpio[i].gpio = fdt32_to_cpu(cell[1]); + gpio[i].flags = fdt32_to_cpu(cell[2]); + gpio[i].name = name; + } + + return len; +} + +int fdtdec_decode_gpio(const void *blob, int node, const char *prop_name, + struct fdt_gpio_state *gpio) +{ + int err; + + debug("%s: %s\n", __func__, prop_name); + gpio->gpio = FDT_GPIO_NONE; + gpio->name = NULL; + err = fdtdec_decode_gpios(blob, node, prop_name, gpio, 1); + return err == 1 ? 0 : err; +} + +int fdtdec_setup_gpio(struct fdt_gpio_state *gpio) +{ + /* + * Return success if there is no GPIO defined. This is used for + * optional GPIOs) + */ + if (!fdt_gpio_isvalid(gpio)) + return 0; + + if (gpio_request(gpio->gpio, gpio->name)) + return -1; + return 0; +} -- cgit v1.3.1 From 87f938c9f7372f587a43fe7babcb171ee0a0672f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:49 +0000 Subject: tegra: usb: Add support for Tegra USB peripheral This adds basic support for the Tegra2 USB controller. Board files should call board_usb_init() to set things up. Configuration is performed through the FDT, with aliases used to set the order of the ports, like this fragment: aliases { /* This defines the order of our USB ports */ usb0 = "/usb@0xc5008000"; usb1 = "/usb@0xc5000000"; }; drivers/usb/host files ONLY: Acked-by: Remy Bohmer Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- arch/arm/cpu/armv7/tegra2/Makefile | 4 +- arch/arm/cpu/armv7/tegra2/usb.c | 460 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 2 + arch/arm/include/asm/arch-tegra2/usb.h | 252 ++++++++++++++++ drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-tegra.c | 62 ++++ include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 8 files changed, 782 insertions(+), 1 deletion(-) create mode 100644 arch/arm/cpu/armv7/tegra2/usb.c create mode 100644 arch/arm/include/asm/arch-tegra2/usb.h create mode 100644 drivers/usb/host/ehci-tegra.c (limited to 'include') diff --git a/arch/arm/cpu/armv7/tegra2/Makefile b/arch/arm/cpu/armv7/tegra2/Makefile index f668a818fbf..e9ac6c9a710 100644 --- a/arch/arm/cpu/armv7/tegra2/Makefile +++ b/arch/arm/cpu/armv7/tegra2/Makefile @@ -33,8 +33,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o SOBJS := lowlevel_init.o -COBJS := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-y := ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/tegra2/usb.c b/arch/arm/cpu/armv7/tegra2/usb.c new file mode 100644 index 00000000000..c80de7f6a37 --- /dev/null +++ b/arch/arm/cpu/armv7/tegra2/usb.c @@ -0,0 +1,460 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * (C) Copyright 2010,2011 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +enum { + USB_PORTS_MAX = 4, /* Maximum ports we allow */ +}; + +/* Parameters we need for USB */ +enum { + PARAM_DIVN, /* PLL FEEDBACK DIVIDer */ + PARAM_DIVM, /* PLL INPUT DIVIDER */ + PARAM_DIVP, /* POST DIVIDER (2^N) */ + PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */ + PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */ + PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */ + PARAM_STABLE_COUNT, /* PLL-U STABLE count */ + PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */ + PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */ + PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */ + PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */ + + PARAM_COUNT +}; + +/* Possible port types (dual role mode) */ +enum dr_mode { + DR_MODE_NONE = 0, + DR_MODE_HOST, /* supports host operation */ + DR_MODE_DEVICE, /* supports device operation */ + DR_MODE_OTG, /* supports both */ +}; + +/* Information about a USB port */ +struct fdt_usb { + struct usb_ctlr *reg; /* address of registers in physical memory */ + unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */ + unsigned enabled:1; /* 1 to enable, 0 to disable */ + unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */ + enum dr_mode dr_mode; /* dual role mode */ + enum periph_id periph_id;/* peripheral id */ + struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */ +}; + +static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */ +static unsigned port_count; /* Number of available ports */ +static int port_current; /* Current port (-1 = none) */ + +/* + * This table has USB timing parameters for each Oscillator frequency we + * support. There are four sets of values: + * + * 1. PLLU configuration information (reference clock is osc/clk_m and + * PLLU-FOs are fixed at 12MHz/60MHz/480MHz). + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * ---------------------------------------------------------------------- + * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0) + * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a) + * Filter frequency (MHz) 1 4.8 6 2 + * CPCON 1100b 0011b 1100b 1100b + * LFCON0 0 0 0 0 + * + * 2. PLL CONFIGURATION & PARAMETERS for different clock generators: + * + * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz + * --------------------------------------------------------------------------- + * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04) + * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66) + * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09) + * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE) + * + * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and + * SessEnd. Each of these signals have their own debouncer and for each of + * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or + * BIAS_DEBOUNCE_B). + * + * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows: + * 0xffff -> No debouncing at all + * ms = *1000 / (1/19.2MHz) / 4 + * + * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have: + * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0 + * + * We need to use only DebounceA for BOOTROM. We don't need the DebounceB + * values, so we can keep those to default. + * + * 4. The 20 microsecond delay after bias cell operation. + */ +static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = { + /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */ + { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 }, + { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 }, + { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 }, + { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 } +}; + +/* UTMIP Idle Wait Delay */ +static const u8 utmip_idle_wait_delay = 17; + +/* UTMIP Elastic limit */ +static const u8 utmip_elastic_limit = 16; + +/* UTMIP High Speed Sync Start Delay */ +static const u8 utmip_hs_sync_start_delay = 9; + +/* Put the port into host mode (this only works for OTG ports) */ +static void set_host_mode(struct fdt_usb *config) +{ + if (config->dr_mode == DR_MODE_OTG) { + /* Check whether remote host from USB1 is driving VBus */ + if (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS) + return; + + /* + * If not driving, we set the GPIO to enable VBUS. We assume + * that the pinmux is set up correctly for this. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + fdtdec_setup_gpio(&config->vbus_gpio); + gpio_direction_output(config->vbus_gpio.gpio, 1); + debug("set_host_mode: GPIO %d high\n", + config->vbus_gpio.gpio); + } + } +} + +void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr) +{ + /* Reset the USB controller with 2us delay */ + reset_periph(config->periph_id, 2); + + /* + * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under + * base address + */ + if (config->has_legacy_mode) + setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); + + /* Put UTMIP1/3 in reset */ + setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Enable the UTMIP PHY */ + if (config->utmi) + setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); + + /* + * TODO: where do we take the USB1 out of reset? The old code would + * take USB3 out of reset, but not USB1. This code doesn't do either. + */ +} + +/* set up the USB controller with the parameters provided */ +static int init_usb_controller(struct fdt_usb *config, + struct usb_ctlr *usbctlr, const u32 timing[]) +{ + u32 val; + int loop_count; + + clock_enable(config->periph_id); + + /* Reset the usb controller */ + usbf_reset_controller(config, usbctlr); + + /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ + clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Follow the crystal clock disable by >100ns delay */ + udelay(1); + + /* + * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP + * mux must be switched to actually use a_sess_vld threshold. + */ + if (fdt_gpio_isvalid(&config->vbus_gpio)) { + clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, + VBUS_SENSE_CTL_MASK, + VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); + } + + /* + * PLL Delay CONFIGURATION settings. The following parameters control + * the bring up of the plls. + */ + val = readl(&usbctlr->utmip_misc_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, + timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, + timing[PARAM_ACTIVE_DELAY_COUNT] << + UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); + writel(val, &usbctlr->utmip_misc_cfg1); + + /* Set PLL enable delay count and crystal frequency count */ + val = readl(&usbctlr->utmip_pll_cfg1); + clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, + timing[PARAM_ENABLE_DELAY_COUNT] << + UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); + clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, + timing[PARAM_XTAL_FREQ_COUNT] << + UTMIP_XTAL_FREQ_COUNT_SHIFT); + writel(val, &usbctlr->utmip_pll_cfg1); + + /* Setting the tracking length time */ + clrsetbits_le32(&usbctlr->utmip_bias_cfg1, + UTMIP_BIAS_PDTRK_COUNT_MASK, + timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); + + /* Program debounce time for VBUS to become valid */ + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, + UTMIP_DEBOUNCE_CFG0_MASK, + timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); + + setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); + + /* Disable battery charge enabling bit */ + setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); + + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); + setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); + + /* + * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT + * Setting these fields, together with default values of the + * other fields, results in programming the registers below as + * follows: + * UTMIP_HSRX_CFG0 = 0x9168c000 + * UTMIP_HSRX_CFG1 = 0x13 + */ + + /* Set PLL enable delay count and Crystal frequency count */ + val = readl(&usbctlr->utmip_hsrx_cfg0); + clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, + utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); + clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, + utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); + writel(val, &usbctlr->utmip_hsrx_cfg0); + + /* Configure the UTMIP_HS_SYNC_START_DLY */ + clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, + UTMIP_HS_SYNC_START_DLY_MASK, + utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); + + /* Preceed the crystal clock disable by >100ns delay. */ + udelay(1); + + /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ + setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); + + /* Finished the per-controller init. */ + + /* De-assert UTMIP_RESET to bring out of reset. */ + clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); + + /* Wait for the phy clock to become valid in 100 ms */ + for (loop_count = 100000; loop_count != 0; loop_count--) { + if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) + break; + udelay(1); + } + if (loop_count == 100000) + return -1; + + return 0; +} + +static void power_up_port(struct usb_ctlr *usbctlr) +{ + /* Deassert power down state */ + clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | + UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); + clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | + UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); +} + +static void config_clock(const u32 timing[]) +{ + clock_start_pll(CLOCK_ID_USB, + timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP], + timing[PARAM_CPCON], timing[PARAM_LFCON]); +} + +/** + * Add a new USB port to the list of available ports. + * + * @param config USB port configuration + * @return 0 if ok, -1 if error (too many ports) + */ +static int add_port(struct fdt_usb *config, const u32 timing[]) +{ + struct usb_ctlr *usbctlr = config->reg; + + if (port_count == USB_PORTS_MAX) { + debug("tegrausb: Cannot register more than %d ports\n", + USB_PORTS_MAX); + return -1; + } + if (init_usb_controller(config, usbctlr, timing)) { + debug("tegrausb: Cannot init port\n"); + return -1; + } + if (config->utmi) { + /* Disable ICUSB FS/LS transceiver */ + clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); + + /* Select UTMI parallel interface */ + clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, + PTS_UTMI << PTS_SHIFT); + clrbits_le32(&usbctlr->port_sc1, STS); + power_up_port(usbctlr); + } + port[port_count++] = *config; + + return 0; +} + +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor) +{ + struct usb_ctlr *usbctlr; + + if (portnum >= port_count) + return -1; + tegrausb_stop_port(); + set_host_mode(&port[portnum]); + + usbctlr = port[portnum].reg; + *hccr = (u32)&usbctlr->cap_length; + *hcor = (u32)&usbctlr->usb_cmd; + port_current = portnum; + return 0; +} + +int tegrausb_stop_port(void) +{ + struct usb_ctlr *usbctlr; + + if (port_current == -1) + return -1; + + usbctlr = port[port_current].reg; + + /* Stop controller */ + writel(0, &usbctlr->usb_cmd); + udelay(1000); + + /* Initiate controller reset */ + writel(2, &usbctlr->usb_cmd); + udelay(1000); + port_current = -1; + return 0; +} + +int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz, + struct fdt_usb *config) +{ + const char *phy, *mode; + + config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg"); + mode = fdt_getprop(blob, node, "dr_mode", NULL); + if (mode) { + if (0 == strcmp(mode, "host")) + config->dr_mode = DR_MODE_HOST; + else if (0 == strcmp(mode, "peripheral")) + config->dr_mode = DR_MODE_DEVICE; + else if (0 == strcmp(mode, "otg")) + config->dr_mode = DR_MODE_OTG; + else { + debug("%s: Cannot decode dr_mode '%s'\n", __func__, + mode); + return -FDT_ERR_NOTFOUND; + } + } else { + config->dr_mode = DR_MODE_HOST; + } + + phy = fdt_getprop(blob, node, "phy_type", NULL); + config->utmi = phy && 0 == strcmp("utmi", phy); + config->enabled = fdtdec_get_is_enabled(blob, node); + config->has_legacy_mode = fdtdec_get_bool(blob, node, + "nvidia,has-legacy-mode"); + config->periph_id = clock_decode_periph_id(blob, node); + if (config->periph_id == PERIPH_ID_NONE) { + debug("%s: Missing/invalid peripheral ID\n", __func__); + return -FDT_ERR_NOTFOUND; + } + fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio); + debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, " + "dr_mode=%d\n", config->enabled, config->has_legacy_mode, + config->utmi, config->periph_id, config->vbus_gpio.gpio, + config->dr_mode); + + return 0; +} + +int board_usb_init(const void *blob) +{ + struct fdt_usb config; + unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC); + enum clock_osc_freq freq; + int node_list[USB_PORTS_MAX]; + int node, count, i; + + /* Set up the USB clocks correctly based on our oscillator frequency */ + freq = clock_get_osc_freq(); + config_clock(usb_pll[freq]); + + /* count may return <0 on error */ + count = fdtdec_find_aliases_for_id(blob, "usb", + COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX); + for (i = 0; i < count; i++) { + debug("USB %d: ", i); + node = node_list[i]; + if (!node) + continue; + if (fdt_decode_usb(blob, node, osc_freq, &config)) { + debug("Cannot decode USB node %s\n", + fdt_get_name(blob, node, NULL)); + return -1; + } + + if (add_port(&config, usb_pll[freq])) + return -1; + set_host_mode(&config); + } + port_current = -1; + + return 0; +} diff --git a/arch/arm/include/asm/arch-tegra2/tegra2.h b/arch/arm/include/asm/arch-tegra2/tegra2.h index 8941443ad8e..baae2ebed38 100644 --- a/arch/arm/include/asm/arch-tegra2/tegra2.h +++ b/arch/arm/include/asm/arch-tegra2/tegra2.h @@ -41,6 +41,8 @@ #define TEGRA2_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380) #define NV_PA_PMC_BASE 0x7000E400 #define NV_PA_CSITE_BASE 0x70040000 +#define TEGRA_USB1_BASE 0xC5000000 +#define TEGRA_USB3_BASE 0xC5008000 #define TEGRA2_SDRC_CS0 NV_PA_SDRAM_BASE #define LOW_LEVEL_SRAM_STACK 0x4000FFFC diff --git a/arch/arm/include/asm/arch-tegra2/usb.h b/arch/arm/include/asm/arch-tegra2/usb.h new file mode 100644 index 00000000000..638033be503 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/usb.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_USB_H_ +#define _TEGRA_USB_H_ + + +/* USB Controller (USBx_CONTROLLER_) regs */ +struct usb_ctlr { + /* 0x000 */ + uint id; + uint reserved0; + uint host; + uint device; + + /* 0x010 */ + uint txbuf; + uint rxbuf; + uint reserved1[2]; + + /* 0x020 */ + uint reserved2[56]; + + /* 0x100 */ + u16 cap_length; + u16 hci_version; + uint hcs_params; + uint hcc_params; + uint reserved3[5]; + + /* 0x120 */ + uint dci_version; + uint dcc_params; + uint reserved4[6]; + + /* 0x140 */ + uint usb_cmd; + uint usb_sts; + uint usb_intr; + uint frindex; + + /* 0x150 */ + uint reserved5; + uint periodic_list_base; + uint async_list_addr; + uint async_tt_sts; + + /* 0x160 */ + uint burst_size; + uint tx_fill_tuning; + uint reserved6; /* is this port_sc1 on some controllers? */ + uint icusb_ctrl; + + /* 0x170 */ + uint ulpi_viewport; + uint reserved7; + uint endpt_nak; + uint endpt_nak_enable; + + /* 0x180 */ + uint reserved; + uint port_sc1; + uint reserved8[6]; + + /* 0x1a0 */ + uint reserved9; + uint otgsc; + uint usb_mode; + uint endpt_setup_stat; + + /* 0x1b0 */ + uint reserved10[20]; + + /* 0x200 */ + uint reserved11[0x80]; + + /* 0x400 */ + uint susp_ctrl; + uint phy_vbus_sensors; + uint phy_vbus_wakeup_id; + uint phy_alt_vbus_sys; + + /* 0x410 */ + uint usb1_legacy_ctrl; + uint reserved12[3]; + + /* 0x420 */ + uint reserved13[56]; + + /* 0x500 */ + uint reserved14[64 * 3]; + + /* 0x800 */ + uint utmip_pll_cfg0; + uint utmip_pll_cfg1; + uint utmip_xcvr_cfg0; + uint utmip_bias_cfg0; + + /* 0x810 */ + uint utmip_hsrx_cfg0; + uint utmip_hsrx_cfg1; + uint utmip_fslsrx_cfg0; + uint utmip_fslsrx_cfg1; + + /* 0x820 */ + uint utmip_tx_cfg0; + uint utmip_misc_cfg0; + uint utmip_misc_cfg1; + uint utmip_debounce_cfg0; + + /* 0x830 */ + uint utmip_bat_chrg_cfg0; + uint utmip_spare_cfg0; + uint utmip_xcvr_cfg1; + uint utmip_bias_cfg1; +}; + + +/* USB1_LEGACY_CTRL */ +#define USB1_NO_LEGACY_MODE 1 + +#define VBUS_SENSE_CTL_SHIFT 1 +#define VBUS_SENSE_CTL_MASK (3 << VBUS_SENSE_CTL_SHIFT) +#define VBUS_SENSE_CTL_VBUS_WAKEUP 0 +#define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP 1 +#define VBUS_SENSE_CTL_AB_SESS_VLD 2 +#define VBUS_SENSE_CTL_A_SESS_VLD 3 + +/* USBx_IF_USB_SUSP_CTRL_0 */ +#define UTMIP_PHY_ENB (1 << 12) +#define UTMIP_RESET (1 << 11) +#define USB_PHY_CLK_VALID (1 << 7) + +/* USBx_UTMIP_MISC_CFG1 */ +#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6 +#define UTMIP_PLLU_STABLE_COUNT_MASK \ + (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT) +#define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT 18 +#define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK \ + (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT) +#define UTMIP_PHY_XTAL_CLOCKEN (1 << 30) + +/* USBx_UTMIP_PLL_CFG1_0 */ +#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27 +#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \ + (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT) +#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0 +#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff + +/* USBx_UTMIP_BIAS_CFG1_0 */ +#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3 +#define UTMIP_BIAS_PDTRK_COUNT_MASK \ + (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT) + +#define UTMIP_DEBOUNCE_CFG0_SHIFT 0 +#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff + +/* USBx_UTMIP_TX_CFG0_0 */ +#define UTMIP_FS_PREAMBLE_J (1 << 19) + +/* USBx_UTMIP_BAT_CHRG_CFG0_0 */ +#define UTMIP_PD_CHRG 1 + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_XCVR_LSBIAS_SE (1 << 21) + +/* USBx_UTMIP_SPARE_CFG0_0 */ +#define FUSE_SETUP_SEL (1 << 3) + +/* USBx_UTMIP_HSRX_CFG0_0 */ +#define UTMIP_IDLE_WAIT_SHIFT 15 +#define UTMIP_IDLE_WAIT_MASK (0x1f << UTMIP_IDLE_WAIT_SHIFT) +#define UTMIP_ELASTIC_LIMIT_SHIFT 10 +#define UTMIP_ELASTIC_LIMIT_MASK \ + (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT) + +/* USBx_UTMIP_HSRX_CFG0_1 */ +#define UTMIP_HS_SYNC_START_DLY_SHIFT 1 +#define UTMIP_HS_SYNC_START_DLY_MASK \ + (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT) + +/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */ +#define IC_ENB1 (1 << 3) + +/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */ +#define PTS_SHIFT 30 +#define PTS_MASK (3U << PTS_SHIFT) +#define PTS_UTMI 0 +#define PTS_RESERVED 1 +#define PTS_ULP 2 +#define PTS_ICUSB_SER 3 + +#define STS (1 << 29) + +/* USBx_UTMIP_XCVR_CFG0_0 */ +#define UTMIP_FORCE_PD_POWERDOWN (1 << 14) +#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) +#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) + +/* USBx_UTMIP_XCVR_CFG1_0 */ +#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0) +#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2) +#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4) + +/* USB3_IF_USB_PHY_VBUS_SENSORS_0 */ +#define VBUS_VLD_STS (1 << 26) + + +/* Change the USB host port into host mode */ +void usb_set_host_mode(void); + +/* Setup USB on the board */ +int board_usb_init(const void *blob); + +/** + * Start up the given port number (ports are numbered from 0 on each board). + * This returns values for the appropriate hccr and hcor addresses to use for + * USB EHCI operations. + * + * @param portnum port number to start + * @param hccr returns start address of EHCI HCCR registers + * @param hcor returns start address of EHCI HCOR registers + * @return 0 if ok, -1 on error (generally invalid port number) + */ +int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor); + +/** + * Stop the current port + * + * @return 0 if ok, -1 if no port was active + */ +int tegrausb_stop_port(void); + +#endif /* _TEGRA_USB_H_ */ diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 53ad70af23c..0d4657edf2f 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -50,6 +50,7 @@ COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o COBJS-$(CONFIG_USB_EHCI_PCI) += ehci-pci.o +COBJS-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o COBJS-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o COBJS := $(COBJS-y) diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c new file mode 100644 index 00000000000..a7e105b9921 --- /dev/null +++ b/drivers/usb/host/ehci-tegra.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2009 NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include + +#include "ehci.h" +#include "ehci-core.h" + +#include +#include + + +/* + * Create the appropriate control structures to manage + * a new EHCI host controller. + */ +int ehci_hcd_init(void) +{ + u32 our_hccr, our_hcor; + + /* + * Select the first port, as we don't have a way of selecting others + * yet + */ + if (tegrausb_start_port(0, &our_hccr, &our_hcor)) + return -1; + + hccr = (struct ehci_hccr *)our_hccr; + hcor = (struct ehci_hcor *)our_hcor; + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + tegrausb_stop_port(); + return 0; +} diff --git a/include/fdtdec.h b/include/fdtdec.h index 2f3842d9a30..bde9873656a 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -57,6 +57,7 @@ struct fdt_memory { */ enum fdt_compat_id { COMPAT_UNKNOWN, + COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index de83226ed1f..4ca442a2afd 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -37,6 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; #define COMPAT(id, name) name static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, ""), + COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1 From 9a263e55dc00f3277d8e82c906ee5c7a1dca0ba5 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 28 Mar 2012 10:08:24 +0000 Subject: fdt: Avoid early panic() when there is no FDT present CONFIG_OF_CONTROL requires a valid device tree. However, we cannot call panic() before the console is set up since the message does not appear, and we get a silent failure. Remove the panic from fdtdec_check_fdt() and provide a new function to prepare the fdt for use. This will be called after the console is ready. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 17 +++++++++++++++-- lib/fdtdec.c | 24 +++++++++++++++++++----- 2 files changed, 34 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index bde9873656a..6249f22e817 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -155,8 +155,21 @@ s32 fdtdec_get_int(const void *blob, int node, const char *prop_name, int fdtdec_get_is_enabled(const void *blob, int node); /** - * Checks whether we have a valid fdt available to control U-Boot, and panic - * if not. + * Make sure we have a valid fdt available to control U-Boot. + * + * If not, a message is printed to the console if the console is ready. + * + * @return 0 if all ok, -1 if not + */ +int fdtdec_prepare_fdt(void); + +/** + * Checks that we have a valid fdt available to control U-Boot. + + * However, if not then for the moment nothing is done, since this function + * is called too early to panic(). + * + * @returns 0 */ int fdtdec_check_fdt(void); diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 4ca442a2afd..5239e79479b 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -262,17 +262,31 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, return num_found; } +int fdtdec_check_fdt(void) +{ + /* + * We must have an FDT, but we cannot panic() yet since the console + * is not ready. So for now, just assert(). Boards which need an early + * FDT (prior to console ready) will need to make their own + * arrangements and do their own checks. + */ + assert(!fdtdec_prepare_fdt()); + return 0; +} + /* * This function is a little odd in that it accesses global data. At some * point if the architecture board.c files merge this will make more sense. * Even now, it is common code. */ -int fdtdec_check_fdt(void) +int fdtdec_prepare_fdt(void) { - /* We must have an fdt */ - if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) - panic("No valid fdt found - please append one to U-Boot\n" - "binary or define CONFIG_OF_EMBED\n"); + if (((uintptr_t)gd->fdt_blob & 3) || fdt_check_header(gd->fdt_blob)) { + printf("No valid FDT found - please append one to U-Boot " + "binary, use u-boot-dtb.bin or define " + "CONFIG_OF_EMBED\n"); + return -1; + } return 0; } -- cgit v1.3.1 From 0291091c9e4dffce1f278d6b87ac123f389595df Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:51 +0000 Subject: tegra: usb: Add common USB defines for tegra2 boards All Tegra2 boards should include tegra2-common. This adds the required USB config to that file. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/tegra2-common.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'include') diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index e6f385fac38..266d0e58804 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -84,6 +84,16 @@ #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 115200} +/* + * This parameter affects a TXFILLTUNING field that controls how much data is + * sent to the latency fifo before it is sent to the wire. Without this + * parameter, the default (2) causes occasional Data Buffer Errors in OUT + * packets depending on the buffer address and size. + */ +#define CONFIG_USB_EHCI_TXFIFO_THRESH 10 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_EHCI_DCACHE + /* include default commands */ #include -- cgit v1.3.1 From db44ebdb5cf7a82ce19d639cad27d9eac13c3a2f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:52 +0000 Subject: tegra: usb: Enable USB on Seaboard Seaboard has a top port which is USB host or device, and a side port which is host only. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/seaboard.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 261f9521add..b6d9f7a88f4 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -72,4 +72,11 @@ #define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE #define CONFIG_ENV_OFFSET (CONFIG_SPI_FLASH_SIZE - CONFIG_ENV_SECT_SIZE) + +/* USB Host support */ +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_TEGRA +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_USB + #endif /* __CONFIG_H */ -- cgit v1.3.1 From d9fdfe0aa598978054f108ba42ca928aceb8c090 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Mon, 27 Feb 2012 10:52:53 +0000 Subject: tegra: fdt: Enable FDT support for Seaboard This switches Seaboard over to use FDT for run-time config instead of CONFIG options. USB is the only user at present. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/seaboard.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index b6d9f7a88f4..1dc775a52f5 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -27,6 +27,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Seaboard. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (SeaBoard) # " -- cgit v1.3.1 From 66d6a91dc2aa6554c0ad0cdf8b13b18abead8155 Mon Sep 17 00:00:00 2001 From: Tom Warren Date: Tue, 6 Mar 2012 17:10:33 +0000 Subject: tegra: fdt: Enable FDT support for Ventana This switches Ventana over to use FDT for run-time config instead of CONFIG options. At present Ventana does not have its own device tree file - it just uses the Seaboard one. Signed-off-by: Tom Warren Signed-off-by: Simon Glass Acked-by: Simon Glass Signed-off-by: Tom Warren --- include/configs/ventana.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/ventana.h b/include/configs/ventana.h index acc9b434bbc..3e55fe5d1ad 100644 --- a/include/configs/ventana.h +++ b/include/configs/ventana.h @@ -27,6 +27,11 @@ #include #include "tegra2-common.h" +/* Enable fdt support for Ventana. Flash the image in u-boot-dtb.bin */ +#define CONFIG_DEFAULT_DEVICE_TREE tegra2-seaboard +#define CONFIG_OF_CONTROL +#define CONFIG_OF_SEPARATE + /* High-level configuration options */ #define TEGRA2_SYSMEM "mem=384M@0M nvmem=128M@384M mem=512M@512M" #define V_PROMPT "Tegra2 (Ventana) # " -- cgit v1.3.1 From c67822704b73dcfb86debf4c25151e43309af844 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:53 +0000 Subject: fdt: Add function to allow aliases to refer to multiple nodes Some devices can deal with multiple compatible properties. The devices need to know which nodes to bind to which features. For example an I2C driver which supports two different controller types will want to know which type it is dealing with in each case. The new fdtdec_add_aliases_for_id() function deals with this by allowing the driver to search for additional compatible nodes for a different ID. It can then detect the new ones and perform appropriate processing. Another option considered was to return a tuple (node offset, compat id) and have the function be passed a list of compatible IDs. This is more overhead for the common case though. We may add such a function later if more drivers in U-Boot require it. Signed-off-by: Simon Glass Signed-off-by: Tom Warren --- include/fdtdec.h | 23 +++++++++++++++++++++++ lib/fdtdec.c | 22 ++++++++++++++++++---- 2 files changed, 41 insertions(+), 4 deletions(-) (limited to 'include') diff --git a/include/fdtdec.h b/include/fdtdec.h index 6249f22e817..1e198f8c630 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -212,6 +212,29 @@ int fdtdec_check_fdt(void); int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount); +/* + * This function is similar to fdtdec_find_aliases_for_id() except that it + * adds to the node_list that is passed in. Any 0 elements are considered + * available for allocation - others are considered already used and are + * skipped. + * + * You can use this by calling fdtdec_find_aliases_for_id() with an + * uninitialised array, then setting the elements that are returned to -1, + * say, then calling this function, perhaps with a different compat id. + * Any elements you get back that are >0 are new nodes added by the call + * to this function. + * + * Note that if you have some nodes with aliases and some without, you are + * sailing close to the wind. The call to fdtdec_find_aliases_for_id() with + * one compat_id may fill in positions for which you have aliases defined + * for another compat_id. When you later call *this* function with the second + * compat_id, the alias positions may already be used. A debug warning may + * be generated in this case, but it is safest to define aliases for all + * nodes when you care about the ordering. + */ +int fdtdec_add_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount); + /* * Get the name for a compatible ID * diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 5239e79479b..2149bd70684 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -153,9 +153,17 @@ int fdtdec_next_alias(const void *blob, const char *name, return node; } -/* TODO: Can we tighten this code up a little? */ int fdtdec_find_aliases_for_id(const void *blob, const char *name, enum fdt_compat_id id, int *node_list, int maxcount) +{ + memset(node_list, '\0', sizeof(*node_list) * maxcount); + + return fdtdec_add_aliases_for_id(blob, name, id, node_list, maxcount); +} + +/* TODO: Can we tighten this code up a little? */ +int fdtdec_add_aliases_for_id(const void *blob, const char *name, + enum fdt_compat_id id, int *node_list, int maxcount) { int name_len = strlen(name); int nodes[maxcount]; @@ -185,8 +193,6 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, __func__, name); /* Now find all the aliases */ - memset(node_list, '\0', sizeof(*node_list) * maxcount); - for (offset = fdt_first_property_offset(blob, alias_node); offset > 0; offset = fdt_next_property_offset(blob, offset)) { @@ -233,11 +239,19 @@ int fdtdec_find_aliases_for_id(const void *blob, const char *name, * it as done. */ if (fdtdec_get_is_enabled(blob, node)) { + if (node_list[number]) { + debug("%s: warning: alias '%s' requires that " + "a node be placed in the list in a " + "position which is already filled by " + "node '%s'\n", __func__, path, + fdt_get_name(blob, node, NULL)); + continue; + } node_list[number] = node; if (number >= num_found) num_found = number + 1; } - nodes[j] = 0; + nodes[found] = 0; } /* Add any nodes not mentioned by an alias */ -- cgit v1.3.1 From c360033ffb3b15d64405c9a3aa5216fbf188ff0a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:13:59 +0000 Subject: tegra: i2c: Select number of controllers for Tegra2 boards The Tegra 2x SOC has four ports, so define TEGRA_I2C_NUM_CONTROLLERS in the shared config file. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Signed-off-by: Tom Warren --- include/configs/tegra2-common.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'include') diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 266d0e58804..837f859c7cc 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -94,6 +94,9 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_EHCI_DCACHE +/* Total I2C ports on Tegra2 */ +#define TEGRA_I2C_NUM_CONTROLLERS 4 + /* include default commands */ #include -- cgit v1.3.1 From 905fe99b9f7f63f33cb4e669708d29f83ba9676f Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Fri, 3 Feb 2012 15:14:00 +0000 Subject: tegra: i2c: Enable I2C on Seaboard This enables I2C on Seaboard. Signed-off-by: Simon Glass Acked-by: Heiko Schocher Signed-off-by: Tom Warren --- include/configs/seaboard.h | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'include') diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index 1dc775a52f5..ae075e786ef 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -59,6 +59,14 @@ #define CONFIG_CMD_SF #define CONFIG_SPI_FLASH_SIZE (4 << 20) +/* I2C */ +#define CONFIG_TEGRA_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_MAX_I2C_BUS 4 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_CMD_I2C + /* SD/MMC */ #define CONFIG_MMC #define CONFIG_GENERIC_MMC -- cgit v1.3.1 From 96a78ac0c445999ce21fb42ecab061479b4d7056 Mon Sep 17 00:00:00 2001 From: Yen Lin Date: Tue, 6 Mar 2012 19:00:23 +0000 Subject: tegra: i2c: Add I2C driver Add basic i2c driver for Tegra2 with 8- and 16-bit address support. The driver requires CONFIG_OF_CONTROL to obtain its configuration from the device tree. (Simon Glass: sjg@chromium.org modified for upstream) Signed-off-by: Simon Glass Acked-by: Heiko Schocher Acked-by: Stephen Warren Signed-off-by: Tom Warren --- arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 157 ++++++++ drivers/i2c/Makefile | 1 + drivers/i2c/tegra_i2c.c | 569 +++++++++++++++++++++++++++ include/fdtdec.h | 2 + lib/fdtdec.c | 2 + 5 files changed, 731 insertions(+) create mode 100644 arch/arm/include/asm/arch-tegra2/tegra_i2c.h create mode 100644 drivers/i2c/tegra_i2c.c (limited to 'include') diff --git a/arch/arm/include/asm/arch-tegra2/tegra_i2c.h b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h new file mode 100644 index 00000000000..0a7d99c5858 --- /dev/null +++ b/arch/arm/include/asm/arch-tegra2/tegra_i2c.h @@ -0,0 +1,157 @@ +/* + * NVIDIA Tegra2 I2C controller + * + * Copyright 2010-2011 NVIDIA Corporation + * + * This software may be used and distributed according to the + * terms of the GNU Public License, Version 2, incorporated + * herein by reference. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _TEGRA_I2C_H_ +#define _TEGRA_I2C_H_ + +#include + +enum { + I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */ + I2C_FIFO_DEPTH = 8, /* I2C fifo depth */ +}; + +enum i2c_transaction_flags { + I2C_IS_WRITE = 0x1, /* for I2C write operation */ + I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */ + I2C_USE_REPEATED_START = 0x4, /* for repeat start */ + I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */ + I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */ + I2C_NO_STOP = 0x20, +}; + +/* Contians the I2C transaction details */ +struct i2c_trans_info { + /* flags to indicate the transaction details */ + enum i2c_transaction_flags flags; + u32 address; /* I2C slave device address */ + u32 num_bytes; /* number of bytes to be transferred */ + /* + * Send/receive buffer. For the I2C send operation this buffer should + * be filled with the data to be sent to the slave device. For the I2C + * receive operation this buffer is filled with the data received from + * the slave device. + */ + u8 *buf; + int is_10bit_address; +}; + +struct i2c_control { + u32 tx_fifo; + u32 rx_fifo; + u32 packet_status; + u32 fifo_control; + u32 fifo_status; + u32 int_mask; + u32 int_status; +}; + +struct dvc_ctlr { + u32 ctrl1; /* 00: DVC_CTRL_REG1 */ + u32 ctrl2; /* 04: DVC_CTRL_REG2 */ + u32 ctrl3; /* 08: DVC_CTRL_REG3 */ + u32 status; /* 0C: DVC_STATUS_REG */ + u32 ctrl; /* 10: DVC_I2C_CTRL_REG */ + u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */ + u32 reserved_0[2]; /* 18: */ + u32 req; /* 20: DVC_REQ_REGISTER */ + u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */ + u32 reserved_1[6]; /* 28: */ + u32 cnfg; /* 40: DVC_I2C_CNFG */ + u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */ + u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */ + u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */ + u32 reserved_2[2]; /* 54: */ + u32 i2c_status; /* 5C: DVC_I2C_STATUS */ + struct i2c_control control; /* 60 ~ 78 */ +}; + +struct i2c_ctlr { + u32 cnfg; /* 00: I2C_I2C_CNFG */ + u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */ + u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */ + u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */ + u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */ + u32 reserved_0[2]; /* 14: */ + u32 status; /* 1C: I2C_I2C_STATUS */ + u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */ + u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */ + u32 sl_status; /* 28: I2C_I2C_SL_STATUS */ + u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */ + u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */ + u32 reserved_1[2]; /* 34: */ + u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */ + u32 reserved_2[4]; /* 40: */ + struct i2c_control control; /* 50 ~ 68 */ +}; + +/* bit fields definitions for IO Packet Header 1 format */ +#define PKT_HDR1_PROTOCOL_SHIFT 4 +#define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT) +#define PKT_HDR1_CTLR_ID_SHIFT 12 +#define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT) +#define PKT_HDR1_PKT_ID_SHIFT 16 +#define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT) +#define PROTOCOL_TYPE_I2C 1 + +/* bit fields definitions for IO Packet Header 2 format */ +#define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0 +#define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT) + +/* bit fields definitions for IO Packet Header 3 format */ +#define PKT_HDR3_READ_MODE_SHIFT 19 +#define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT) +#define PKT_HDR3_SLAVE_ADDR_SHIFT 0 +#define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT) + +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26 +#define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \ + (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT) + +/* I2C_CNFG */ +#define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11 +#define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT) +#define I2C_CNFG_PACKET_MODE_SHIFT 10 +#define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT) + +/* I2C_SL_CNFG */ +#define I2C_SL_CNFG_NEWSL_SHIFT 2 +#define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT) + +/* I2C_FIFO_STATUS */ +#define TX_FIFO_FULL_CNT_SHIFT 0 +#define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT) +#define TX_FIFO_EMPTY_CNT_SHIFT 4 +#define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT) + +/* I2C_INTERRUPT_STATUS */ +#define I2C_INT_XFER_COMPLETE_SHIFT 7 +#define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT) +#define I2C_INT_NO_ACK_SHIFT 3 +#define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT) +#define I2C_INT_ARBITRATION_LOST_SHIFT 2 +#define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT) + +#endif diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 504db03c711..f86e46c111f 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -41,6 +41,7 @@ COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o +COBJS-$(CONFIG_TEGRA_I2C) += tegra_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c new file mode 100644 index 00000000000..21f68972692 --- /dev/null +++ b/drivers/i2c/tegra_i2c.c @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. + * Copyright (c) 2010-2011 NVIDIA Corporation + * NVIDIA Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static unsigned int i2c_bus_num; + +/* Information about i2c controller */ +struct i2c_bus { + int id; + enum periph_id periph_id; + int speed; + int pinmux_config; + struct i2c_control *control; + struct i2c_ctlr *regs; + int is_dvc; /* DVC type, rather than I2C */ + int inited; /* bus is inited */ +}; + +static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; + +static void set_packet_mode(struct i2c_bus *i2c_bus) +{ + u32 config; + + config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; + + if (i2c_bus->is_dvc) { + struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; + + writel(config, &dvc->cnfg); + } else { + writel(config, &i2c_bus->regs->cnfg); + /* + * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe + * issues, i.e., some slaves may be wrongly detected. + */ + setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); + } +} + +static void i2c_reset_controller(struct i2c_bus *i2c_bus) +{ + /* Reset I2C controller. */ + reset_periph(i2c_bus->periph_id, 1); + + /* re-program config register to packet mode */ + set_packet_mode(i2c_bus); +} + +static void i2c_init_controller(struct i2c_bus *i2c_bus) +{ + /* + * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 + * here, in section 23.3.1, but in fact we seem to need a factor of + * 16 to get the right frequency. + */ + clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, + i2c_bus->speed * 2 * 8); + + /* Reset I2C controller. */ + i2c_reset_controller(i2c_bus); + + /* Configure I2C controller. */ + if (i2c_bus->is_dvc) { /* only for DVC I2C */ + struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; + + setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); + } + + funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); +} + +static void send_packet_headers( + struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans, + u32 packet_id) +{ + u32 data; + + /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ + data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; + data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; + data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 1 sent (0x%x)\n", data); + + /* prepare header2 */ + data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 2 sent (0x%x)\n", data); + + /* prepare IO specific header: configure the slave address */ + data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; + + /* Enable Read if it is not a write transaction */ + if (!(trans->flags & I2C_IS_WRITE)) + data |= PKT_HDR3_READ_MODE_MASK; + + /* Write I2C specific header */ + writel(data, &i2c_bus->control->tx_fifo); + debug("pkt header 3 sent (0x%x)\n", data); +} + +static int wait_for_tx_fifo_empty(struct i2c_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) + >> TX_FIFO_EMPTY_CNT_SHIFT; + if (count == I2C_FIFO_DEPTH) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_rx_fifo_notempty(struct i2c_control *control) +{ + u32 count; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) + >> TX_FIFO_FULL_CNT_SHIFT; + if (count) + return 1; + udelay(10); + timeout_us -= 10; + } + + return 0; +} + +static int wait_for_transfer_complete(struct i2c_control *control) +{ + int int_status; + int timeout_us = I2C_TIMEOUT_USEC; + + while (timeout_us >= 0) { + int_status = readl(&control->int_status); + if (int_status & I2C_INT_NO_ACK_MASK) + return -int_status; + if (int_status & I2C_INT_ARBITRATION_LOST_MASK) + return -int_status; + if (int_status & I2C_INT_XFER_COMPLETE_MASK) + return 0; + + udelay(10); + timeout_us -= 10; + } + + return -1; +} + +static int send_recv_packets(struct i2c_bus *i2c_bus, + struct i2c_trans_info *trans) +{ + struct i2c_control *control = i2c_bus->control; + u32 int_status; + u32 words; + u8 *dptr; + u32 local; + uchar last_bytes; + int error = 0; + int is_write = trans->flags & I2C_IS_WRITE; + + /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ + int_status = readl(&control->int_status); + writel(int_status, &control->int_status); + + send_packet_headers(i2c_bus, trans, 1); + + words = DIV_ROUND_UP(trans->num_bytes, 4); + last_bytes = trans->num_bytes & 3; + dptr = trans->buf; + + while (words) { + u32 *wptr = (u32 *)dptr; + + if (is_write) { + /* deal with word alignment */ + if ((unsigned)dptr & 3) { + memcpy(&local, dptr, sizeof(u32)); + writel(local, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", local); + } else { + writel(*wptr, &control->tx_fifo); + debug("pkt data sent (0x%x)\n", *wptr); + } + if (!wait_for_tx_fifo_empty(control)) { + error = -1; + goto exit; + } + } else { + if (!wait_for_rx_fifo_notempty(control)) { + error = -1; + goto exit; + } + /* + * for the last word, we read into our local buffer, + * in case that caller did not provide enough buffer. + */ + local = readl(&control->rx_fifo); + if ((words == 1) && last_bytes) + memcpy(dptr, (char *)&local, last_bytes); + else if ((unsigned)dptr & 3) + memcpy(dptr, &local, sizeof(u32)); + else + *wptr = local; + debug("pkt data received (0x%x)\n", local); + } + words--; + dptr += sizeof(u32); + } + + if (wait_for_transfer_complete(control)) { + error = -1; + goto exit; + } + return 0; +exit: + /* error, reset the controller. */ + i2c_reset_controller(i2c_bus); + + return error; +} + +static int tegra2_i2c_write_data(u32 addr, u8 *data, u32 len) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr; + trans_info.buf = data; + trans_info.flags = I2C_IS_WRITE; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); + if (error) + debug("tegra2_i2c_write_data: Error (%d) !!!\n", error); + + return error; +} + +static int tegra2_i2c_read_data(u32 addr, u8 *data, u32 len) +{ + int error; + struct i2c_trans_info trans_info; + + trans_info.address = addr | 1; + trans_info.buf = data; + trans_info.flags = 0; + trans_info.num_bytes = len; + trans_info.is_10bit_address = 0; + + error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); + if (error) + debug("tegra2_i2c_read_data: Error (%d) !!!\n", error); + + return error; +} + +#ifndef CONFIG_OF_CONTROL +#error "Please enable device tree support to use this driver" +#endif + +unsigned int i2c_get_bus_speed(void) +{ + return i2c_controllers[i2c_bus_num].speed; +} + +int i2c_set_bus_speed(unsigned int speed) +{ + struct i2c_bus *i2c_bus; + + i2c_bus = &i2c_controllers[i2c_bus_num]; + i2c_bus->speed = speed; + i2c_init_controller(i2c_bus); + + return 0; +} + +static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) +{ + i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); + + /* + * We don't have a binding for pinmux yet. Leave it out for now. So + * far no one needs anything other than the default. + */ + i2c_bus->pinmux_config = FUNCMUX_DEFAULT; + i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); + i2c_bus->periph_id = clock_decode_periph_id(blob, node); + + /* + * We can't specify the pinmux config in the fdt, so I2C2 will not + * work on Seaboard. It normally has no devices on it anyway. + * You could add in this little hack if you need to use it. + * The correct solution is a pinmux binding in the fdt. + * + * if (i2c_bus->periph_id == PERIPH_ID_I2C2) + * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; + */ + if (i2c_bus->periph_id == -1) + return -FDT_ERR_NOTFOUND; + + return 0; +} + +/* + * Process a list of nodes, adding them to our list of I2C ports. + * + * @param blob fdt blob + * @param node_list list of nodes to process (any <=0 are ignored) + * @param count number of nodes to process + * @param is_dvc 1 if these are DVC ports, 0 if standard I2C + * @return 0 if ok, -1 on error + */ +static int process_nodes(const void *blob, int node_list[], int count, + int is_dvc) +{ + struct i2c_bus *i2c_bus; + int i; + + /* build the i2c_controllers[] for each controller */ + for (i = 0; i < count; i++) { + int node = node_list[i]; + + if (node <= 0) + continue; + + i2c_bus = &i2c_controllers[i]; + i2c_bus->id = i; + + if (i2c_get_config(blob, node, i2c_bus)) { + printf("i2c_init_board: failed to decode bus %d\n", i); + return -1; + } + + i2c_bus->is_dvc = is_dvc; + if (is_dvc) { + i2c_bus->control = + &((struct dvc_ctlr *)i2c_bus->regs)->control; + } else { + i2c_bus->control = &i2c_bus->regs->control; + } + debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", + is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, + i2c_bus->periph_id, i2c_bus->speed); + i2c_init_controller(i2c_bus); + debug("ok\n"); + i2c_bus->inited = 1; + + /* Mark position as used */ + node_list[i] = -1; + } + + return 0; +} + +/* Sadly there is no error return from this function */ +void i2c_init_board(void) +{ + int node_list[TEGRA_I2C_NUM_CONTROLLERS]; + const void *blob = gd->fdt_blob; + int count; + + /* First get the normal i2c ports */ + count = fdtdec_find_aliases_for_id(blob, "i2c", + COMPAT_NVIDIA_TEGRA20_I2C, node_list, + TEGRA_I2C_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count, 0)) + return; + + /* Now look for dvc ports */ + count = fdtdec_add_aliases_for_id(blob, "i2c", + COMPAT_NVIDIA_TEGRA20_DVC, node_list, + TEGRA_I2C_NUM_CONTROLLERS); + if (process_nodes(blob, node_list, count, 1)) + return; +} + +void i2c_init(int speed, int slaveaddr) +{ + /* This will override the speed selected in the fdt for that port */ + debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); + i2c_set_bus_speed(speed); +} + +/* i2c write version without the register address */ +int i2c_write_data(uchar chip, uchar *buffer, int len) +{ + int rc; + + debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); + debug("write_data: "); + /* use rc for counter */ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra2_i2c_write_data(chip << 1, buffer, len); + if (rc) + debug("i2c_write_data(): rc=%d\n", rc); + + return rc; +} + +/* i2c read version without the register address */ +int i2c_read_data(uchar chip, uchar *buffer, int len) +{ + int rc; + + debug("inside i2c_read_data():\n"); + /* Shift 7-bit address over for lower-level i2c functions */ + rc = tegra2_i2c_read_data(chip << 1, buffer, len); + if (rc) { + debug("i2c_read_data(): rc=%d\n", rc); + return rc; + } + + debug("i2c_read_data: "); + /* reuse rc for counter*/ + for (rc = 0; rc < len; ++rc) + debug(" 0x%02x", buffer[rc]); + debug("\n"); + + return 0; +} + +/* Probe to see if a chip is present. */ +int i2c_probe(uchar chip) +{ + int rc; + uchar reg; + + debug("i2c_probe: addr=0x%x\n", chip); + reg = 0; + rc = i2c_write_data(chip, ®, 1); + if (rc) { + debug("Error probing 0x%x.\n", chip); + return 1; + } + return 0; +} + +static int i2c_addr_ok(const uint addr, const int alen) +{ + /* We support 7 or 10 bit addresses, so one or two bytes each */ + return alen == 1 || alen == 2; +} + +/* Read bytes */ +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + uint offset; + int i; + + debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", + chip, addr, len); + if (!i2c_addr_ok(addr, alen)) { + debug("i2c_read: Bad address %x.%d.\n", addr, alen); + return 1; + } + for (offset = 0; offset < len; offset++) { + if (alen) { + uchar data[alen]; + for (i = 0; i < alen; i++) { + data[alen - i - 1] = + (addr + offset) >> (8 * i); + } + if (i2c_write_data(chip, data, alen)) { + debug("i2c_read: error sending (0x%x)\n", + addr); + return 1; + } + } + if (i2c_read_data(chip, buffer + offset, 1)) { + debug("i2c_read: error reading (0x%x)\n", addr); + return 1; + } + } + + return 0; +} + +/* Write bytes */ +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + uint offset; + int i; + + debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", + chip, addr, len); + if (!i2c_addr_ok(addr, alen)) { + debug("i2c_write: Bad address %x.%d.\n", addr, alen); + return 1; + } + for (offset = 0; offset < len; offset++) { + uchar data[alen + 1]; + for (i = 0; i < alen; i++) + data[alen - i - 1] = (addr + offset) >> (8 * i); + data[alen] = buffer[offset]; + if (i2c_write_data(chip, data, alen + 1)) { + debug("i2c_write: error sending (0x%x)\n", addr); + return 1; + } + } + + return 0; +} + +#if defined(CONFIG_I2C_MULTI_BUS) +/* + * Functions for multiple I2C bus handling + */ +unsigned int i2c_get_bus_num(void) +{ + return i2c_bus_num; +} + +int i2c_set_bus_num(unsigned int bus) +{ + if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited) + return -1; + i2c_bus_num = bus; + + return 0; +} +#endif diff --git a/include/fdtdec.h b/include/fdtdec.h index 1e198f8c630..171c6284853 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -58,6 +58,8 @@ struct fdt_memory { enum fdt_compat_id { COMPAT_UNKNOWN, COMPAT_NVIDIA_TEGRA20_USB, /* Tegra2 USB port */ + COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra2 i2c */ + COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra2 dvc (really just i2c) */ COMPAT_COUNT, }; diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 2149bd70684..bdec1a0d962 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -38,6 +38,8 @@ DECLARE_GLOBAL_DATA_PTR; static const char * const compat_names[COMPAT_COUNT] = { COMPAT(UNKNOWN, ""), COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"), + COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"), + COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"), }; const char *fdtdec_get_compatible(enum fdt_compat_id id) -- cgit v1.3.1 From 76e2c169a525159d48dd005a371fb05e1943c64b Mon Sep 17 00:00:00 2001 From: Tom Rini Date: Wed, 28 Mar 2012 06:26:18 +0000 Subject: OMAP: Remove omap1610inn-based boards The CS_AUTOBOOT configurations have been broken for a long time. Kshitij Gupta is no longer at TI making these broken and orphaned boards, so remove. Signed-off-by: Tom Rini --- MAINTAINERS | 1 - board/ti/omap1610inn/Makefile | 45 --- board/ti/omap1610inn/config.mk | 26 -- board/ti/omap1610inn/flash.c | 495 ------------------------------- board/ti/omap1610inn/lowlevel_init.S | 452 ---------------------------- board/ti/omap1610inn/omap1610innovator.c | 309 ------------------- boards.cfg | 8 - include/configs/omap1610h2.h | 197 ------------ include/configs/omap1610inn.h | 202 ------------- 9 files changed, 1735 deletions(-) delete mode 100644 board/ti/omap1610inn/Makefile delete mode 100644 board/ti/omap1610inn/config.mk delete mode 100644 board/ti/omap1610inn/flash.c delete mode 100644 board/ti/omap1610inn/lowlevel_init.S delete mode 100644 board/ti/omap1610inn/omap1610innovator.c delete mode 100644 include/configs/omap1610h2.h delete mode 100644 include/configs/omap1610inn.h (limited to 'include') diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0dc9b..72f8b6453f8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -672,7 +672,6 @@ Igor Grinberg Kshitij Gupta omap1510inn ARM925T - omap1610inn ARM926EJS Stefan Herbrechtsmeier diff --git a/board/ti/omap1610inn/Makefile b/board/ti/omap1610inn/Makefile deleted file mode 100644 index 2b8641fdf90..00000000000 --- a/board/ti/omap1610inn/Makefile +++ /dev/null @@ -1,45 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := omap1610innovator.o flash.o -SOBJS := lowlevel_init.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(call cmd_link_o_target, $(OBJS) $(SOBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/ti/omap1610inn/config.mk b/board/ti/omap1610inn/config.mk deleted file mode 100644 index ee0aa0aec04..00000000000 --- a/board/ti/omap1610inn/config.mk +++ /dev/null @@ -1,26 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# David Mueller, ELSOFT AG, -# -# (C) Copyright 2003 -# Texas Instruments, -# Kshitij Gupta -# -# TI Innovator board with OMAP1610 (ARM925EJS) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# Innovator has 1 bank of 256 MB SDRAM -# Physical Address: -# 1000'0000 to 2000'0000 -# -# -# Linux-Kernel is expected to be at 1000'8000, entry 1000'8000 -# (mem base + reserved) -# -# we load ourself to 1108'0000 -# -# - - -CONFIG_SYS_TEXT_BASE = 0x11080000 diff --git a/board/ti/omap1610inn/flash.c b/board/ti/omap1610inn/flash.c deleted file mode 100644 index a99a91c4940..00000000000 --- a/board/ti/omap1610inn/flash.c +++ /dev/null @@ -1,495 +0,0 @@ -/* - * (C) Copyright 2001 - * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net - * - * (C) Copyright 2001-2004 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#define PHYS_FLASH_SECT_SIZE 0x00020000 /* 256 KB sectors (x2) */ -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* Board support for 1 or 2 flash devices */ -#undef FLASH_PORT_WIDTH32 -#define FLASH_PORT_WIDTH16 - -#ifdef FLASH_PORT_WIDTH16 -#define FLASH_PORT_WIDTH ushort -#define FLASH_PORT_WIDTHV vu_short -#define SWAP(x) __swab16(x) -#else -#define FLASH_PORT_WIDTH ulong -#define FLASH_PORT_WIDTHV vu_long -#define SWAP(x) __swab32(x) -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define mb() __asm__ __volatile__ ("" : : : "memory") - - -/* Flash Organization Structure */ -typedef struct OrgDef { - unsigned int sector_number; - unsigned int sector_size; -} OrgDef; - - -/* Flash Organizations */ -OrgDef OrgIntel_28F256L18T[] = { - {4, 32 * 1024}, /* 4 * 32kBytes sectors */ - {255, 128 * 1024}, /* 255 * 128kBytes sectors */ -}; - - -/*----------------------------------------------------------------------- - * Functions - */ -unsigned long flash_init (void); -static ulong flash_get_size (FPW * addr, flash_info_t * info); -static int write_data (flash_info_t * info, ulong dest, FPW data); -static void flash_get_offsets (ulong base, flash_info_t * info); -void inline spin_wheel (void); -void flash_print_info (flash_info_t * info); -void flash_unprotect_sectors (FPWV * addr); -int flash_erase (flash_info_t * info, int s_first, int s_last); -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -void flash_unlock(flash_info_t * info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ - int i; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - switch (i) { - case 0: - flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]); - /* to reset the lock bit */ - flash_unlock(&flash_info[i]); - break; - default: - panic ("configured too many flash banks!\n"); - break; - } - size += flash_info[i].size; - } - - /* Protect monitor and environment sectors - */ - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_unlock(flash_info_t * info) -{ - int j; - for (j=2;jstart[j]); - flash_unprotect_sectors (addr); - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - } -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - return; - } - - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { - for (i = 0; i < info->sector_count; i++) { - if (i > 255) { - info->start[i] = base + (i * 0x8000); - info->protect[i] = 0; - } else { - info->start[i] = base + - (i * PHYS_FLASH_SECT_SIZE); - info->protect[i] = 0; - } - } - } -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_INTEL: - printf ("INTEL "); - break; - default: - printf ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_28F256L18T: - printf ("FLASH 28F256L18T\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], info->protect[i] ? " (RO)" : " "); - } - printf ("\n"); - return; -} - -/* - * The following code cannot be run from FLASH! - */ -static ulong flash_get_size (FPW * addr, flash_info_t * info) -{ - volatile FPW value; - - /* Write auto select command: read Manufacturer ID */ - addr[0x5555] = (FPW) 0x00AA00AA; - addr[0x2AAA] = (FPW) 0x00550055; - addr[0x5555] = (FPW) 0x00900090; - - mb (); - value = addr[0]; - - switch (value) { - - case (FPW) INTEL_MANUFACT: - info->flash_id = FLASH_MAN_INTEL; - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - return (0); /* no or unknown flash */ - } - - mb (); - value = addr[1]; /* device ID */ - switch (value) { - - case (FPW) (INTEL_ID_28F256L18T): - info->flash_id += FLASH_28F256L18T; - info->sector_count = 259; - info->size = 0x02000000; - break; /* => 32 MB */ - - default: - info->flash_id = FLASH_UNKNOWN; - break; - } - - if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) { - printf ("** ERROR: sector count %d > max (%d) **\n", - info->sector_count, CONFIG_SYS_MAX_FLASH_SECT); - info->sector_count = CONFIG_SYS_MAX_FLASH_SECT; - } - - addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ - - return (info->size); -} - - -/* unprotects a sector for write and erase - * on some intel parts, this unprotects the entire chip, but it - * wont hurt to call this additional times per sector... - */ -void flash_unprotect_sectors (FPWV * addr) -{ -#define PD_FINTEL_WSMS_READY_MASK 0x0080 - - *addr = (FPW) 0x00500050; /* clear status register */ - - /* this sends the clear lock bit command */ - *addr = (FPW) 0x00600060; - *addr = (FPW) 0x00D000D0; -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int flag, prot, sect; - ulong type, start; - int rcode = 0; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - type = (info->flash_id & FLASH_VENDMASK); - if ((type != FLASH_MAN_INTEL)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - FPWV *addr = (FPWV *) (info->start[sect]); - FPW status; - - printf ("Erasing sector %2d ... ", sect); - - flash_unprotect_sectors (addr); - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - *addr = (FPW) 0x00500050;/* clear status register */ - *addr = (FPW) 0x00200020;/* erase setup */ - *addr = (FPW) 0x00D000D0;/* erase confirm */ - - while (((status = - *addr) & (FPW) 0x00800080) != - (FPW) 0x00800080) { - if (get_timer(start) > - CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - /* suspend erase */ - *addr = (FPW) 0x00B000B0; - /* reset to read mode */ - *addr = (FPW) 0x00FF00FF; - rcode = 1; - break; - } - } - - /* clear status register cmd. */ - *addr = (FPW) 0x00500050; - *addr = (FPW) 0x00FF00FF;/* resest to read mode */ - printf (" done\n"); - } - } - if (flag) - enable_interrupts(); - - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - * 4 - Flash not identified - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - FPW data; - int count, i, l, rc, port_width; - - if (info->flash_id == FLASH_UNKNOWN) { - return 4; - } -/* get lower word aligned address */ -#ifdef FLASH_PORT_WIDTH16 - wp = (addr & ~1); - port_width = 2; -#else - wp = (addr & ~3); - port_width = 4; -#endif - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - for (; i < port_width && cnt > 0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt == 0 && i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - } - - /* - * handle word aligned part - */ - count = 0; - while (cnt >= port_width) { - data = 0; - for (i = 0; i < port_width; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_data (info, wp, SWAP (data))) != 0) { - return (rc); - } - wp += port_width; - cnt -= port_width; - if (count++ > 0x800) { - spin_wheel (); - count = 0; - } - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i < port_width; ++i, ++cp) { - data = (data << 8) | (*(uchar *) cp); - } - - return (write_data (info, wp, SWAP (data))); -} - -/*----------------------------------------------------------------------- - * Write a word or halfword to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_data (flash_info_t * info, ulong dest, FPW data) -{ - FPWV *addr = (FPWV *) dest; - ulong status; - int flag, rc = 0; - ulong start; - - /* Check if Flash is (sufficiently) erased */ - if ((*addr & data) != data) { - printf("not erased at %08lx (%x)\n", (ulong) addr, *addr); - return 2; - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts (); - *addr = (FPW) 0x00400040; /* write setup */ - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait while polling the status register */ - while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - rc = 1; - goto done; - } - } -done: - if (flag) - enable_interrupts(); - - *addr = (FPW) 0x00FF00FF; /* restore read mode */ - return rc; -} - -void inline spin_wheel (void) -{ - static int p = 0; - static char w[] = "\\/-"; - - printf ("\010%c", w[p]); - (++p == 3) ? (p = 0) : 0; -} diff --git a/board/ti/omap1610inn/lowlevel_init.S b/board/ti/omap1610inn/lowlevel_init.S deleted file mode 100644 index b376ba5d0ee..00000000000 --- a/board/ti/omap1610inn/lowlevel_init.S +++ /dev/null @@ -1,452 +0,0 @@ -/* - * Board specific setup info - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include - -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - - -_TEXT_BASE: - .word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */ - -.globl lowlevel_init -lowlevel_init: - - - /*------------------------------------------------------* - *mask all IRQs by setting all bits in the INTMR default* - *------------------------------------------------------*/ - mov r1, #0xffffffff - ldr r0, =REG_IHL1_MIR - str r1, [r0] - ldr r0, =REG_IHL2_MIR - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT1) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT1 - ldr r1, VAL_ARM_IDLECT1 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT2) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT2 - ldr r1, VAL_ARM_IDLECT2 - str r1, [r0] - - /*------------------------------------------------------* - * Set up ARM CLM registers (IDLECT3) * - *------------------------------------------------------*/ - ldr r0, REG_ARM_IDLECT3 - ldr r1, VAL_ARM_IDLECT3 - str r1, [r0] - -#ifdef CONFIG_CS_AUTOBOOT /* do the setup depending on boot mode */ - ldr r0, CONF_STATUS - ldr r1, [r0] - tst r1, #0x02 - beq disable_wd /* booting from RAM, skip setup */ -#endif - - mov r1, #0x01 /* PER_EN bit */ - ldr r0, REG_ARM_RSTCT2 - strh r1, [r0] /* CLKM; Peripheral reset. */ - - /* Set CLKM to Sync-Scalable */ - /* I supposedly need to enable the dsp clock before switching */ - mov r1, #0x0000 - ldr r0, REG_ARM_SYSST - strh r1, [r0] - mov r0, #0x400 -1: - subs r0, r0, #0x1 /* wait for any bubbles to finish */ - bne 1b - ldr r1, VAL_ARM_CKCTL - ldr r0, REG_ARM_CKCTL - strh r1, [r0] - - /* a few nops to let settle */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - - /* setup DPLL 1 */ - /* Ramp up the clock to 96Mhz */ - ldr r1, VAL_DPLL1_CTL - ldr r0, REG_DPLL1_CTL - strh r1, [r0] - ands r1, r1, #0x10 /* Check if PLL is enabled. */ - beq lock_end /* Do not look for lock if BYPASS selected */ -2: - ldrh r1, [r0] - ands r1, r1, #0x01 /* Check the LOCK bit.*/ - beq 2b /* loop until bit goes hi. */ -lock_end: - - - /*------------------------------------------------------* - * Turn off the watchdog during init... * - *------------------------------------------------------*/ -disable_wd: - ldr r0, REG_WATCHDOG - ldr r1, WATCHDOG_VAL1 - str r1, [r0] - ldr r1, WATCHDOG_VAL2 - str r1, [r0] - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL1 - str r1, [r0] - ldr r0, REG_WWPSDOG - -watch1Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch1Wait - - ldr r0, REG_WSPRDOG - ldr r1, WSPRDOG_VAL2 - str r1, [r0] - ldr r0, REG_WWPSDOG -watch2Wait: - ldr r1, [r0] - tst r1, #0x10 - bne watch2Wait - - - /* Set memory timings corresponding to the new clock speed */ - - /* Check execution location to determine current execution location - * and branch to appropriate initialization code. - */ - /* Load physical SDRAM base. */ - mov r0, #0x10000000 - /* Get current execution location. */ - mov r1, pc - /* Compare. */ - cmp r1, r0 - /* Skip over EMIF-fast initialization if running from SDRAM. */ - bge skip_sdram - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 /* value should be checked */ -3: - subs r3, r3, #0x1 /* Decrement count */ - bne 3b - - - /* - * Set SDRAM control values. Disable refresh before MRS command. - */ - - /* mobile ddr operation */ - ldr r0, REG_SDRAM_OPERATION - mov r2, #07 - str r2, [r0] - - /* config register */ - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - - /* manual command register */ - ldr r0, REG_SDRAM_MANUAL_CMD - /* issue set cke high */ - mov r1, #CMD_SDRAM_CKE_SET_HIGH - str r1, [r0] - /* issue nop */ - mov r1, #CMD_SDRAM_NOP - str r1, [r0] - - mov r2, #0x0100 -waitMDDR1: - subs r2, r2, #1 - bne waitMDDR1 /* delay loop */ - - /* issue precharge */ - mov r1, #CMD_SDRAM_PRECHARGE - str r1, [r0] - - /* issue autorefresh x 2 */ - mov r1, #CMD_SDRAM_AUTOREFRESH - str r1, [r0] - str r1, [r0] - - /* mrs register ddr mobile */ - ldr r0, REG_SDRAM_MRS - mov r1, #0x33 - str r1, [r0] - - /* emrs1 low-power register */ - ldr r0, REG_SDRAM_EMRS1 - /* self refresh on all banks */ - mov r1, #0 - str r1, [r0] - - ldr r0, REG_DLL_URD_CONTROL - ldr r1, DLL_URD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_LRD_CONTROL - ldr r1, DLL_LRD_CONTROL_VAL - str r1, [r0] - - ldr r0, REG_DLL_WRT_CONTROL - ldr r1, DLL_WRT_CONTROL_VAL - str r1, [r0] - - /* delay loop */ - mov r2, #0x0100 -waitMDDR2: - subs r2, r2, #1 - bne waitMDDR2 - - /* - * Delay for SDRAM initialization. - */ - mov r3, #0x1800 -4: - subs r3, r3, #1 /* Decrement count. */ - bne 4b - b common_tc - -skip_sdram: - - ldr r0, REG_SDRAM_CONFIG - ldr r1, SDRAM_CONFIG_VAL - str r1, [r0] - -common_tc: - /* slow interface */ - ldr r1, VAL_TC_EMIFS_CS0_CONFIG - ldr r0, REG_TC_EMIFS_CS0_CONFIG - str r1, [r0] /* Chip Select 0 */ - - ldr r1, VAL_TC_EMIFS_CS1_CONFIG - ldr r0, REG_TC_EMIFS_CS1_CONFIG - str r1, [r0] /* Chip Select 1 */ - ldr r1, VAL_TC_EMIFS_CS3_CONFIG - ldr r0, REG_TC_EMIFS_CS3_CONFIG - str r1, [r0] /* Chip Select 3 */ - -#ifdef CONFIG_H2_OMAP1610 - /* inserting additional 2 clock cycle hold time for LAN */ - ldr r0, REG_TC_EMIFS_CS1_ADVANCED - ldr r1, VAL_TC_EMIFS_CS1_ADVANCED - str r1, [r0] -#endif - /* Start MPU Timer 1 */ - ldr r0, REG_MPU_LOAD_TIMER - ldr r1, VAL_MPU_LOAD_TIMER - str r1, [r0] - - ldr r0, REG_MPU_CNTL_TIMER - ldr r1, VAL_MPU_CNTL_TIMER - str r1, [r0] - - /* back to arch calling code */ - mov pc, lr - - /* the literal pools origin */ - .ltorg - -#ifdef CONFIG_CS_AUTOBOOT -CONF_STATUS: - .word 0xfffe1130 /* 32 bits */ -#endif - -REG_TC_EMIFS_CONFIG: /* 32 bits */ - .word 0xfffecc0c -REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */ - .word 0xfffecc10 -REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */ - .word 0xfffecc14 -REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */ - .word 0xfffecc18 -REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */ - .word 0xfffecc1c - -#ifdef CONFIG_H2_OMAP1610 -REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */ - .word 0xfffecc54 -#endif - -/* MPU clock/reset/power mode control registers */ -REG_ARM_CKCTL: /* 16 bits */ - .word 0xfffece00 - -REG_ARM_IDLECT3: /* 16 bits */ - .word 0xfffece24 -REG_ARM_IDLECT2: /* 16 bits */ - .word 0xfffece08 -REG_ARM_IDLECT1: /* 16 bits */ - .word 0xfffece04 - -REG_ARM_RSTCT2: /* 16 bits */ - .word 0xfffece14 -REG_ARM_SYSST: /* 16 bits */ - .word 0xfffece18 -/* DPLL control registers */ -REG_DPLL1_CTL: /* 16 bits */ - .word 0xfffecf00 - -/* Watch Dog register */ -/* secure watchdog stop */ -REG_WSPRDOG: - .word 0xfffeb048 -/* watchdog write pending */ -REG_WWPSDOG: - .word 0xfffeb034 - -WSPRDOG_VAL1: - .word 0x0000aaaa -WSPRDOG_VAL2: - .word 0x00005555 - -/* SDRAM config is: auto refresh enabled, 16 bit 4 bank, - counter @8192 rows, 10 ns, 8 burst */ -REG_SDRAM_CONFIG: - .word 0xfffecc20 - -/* Operation register */ -REG_SDRAM_OPERATION: - .word 0xfffecc80 - -/* Manual command register */ -REG_SDRAM_MANUAL_CMD: - .word 0xfffecc84 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_MRS: - .word 0xfffecc70 - -/* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */ -REG_SDRAM_EMRS1: - .word 0xfffecc78 - -/* WRT DLL register */ -REG_DLL_WRT_CONTROL: - .word 0xfffecc68 -DLL_WRT_CONTROL_VAL: - .word 0x03f00002 - -/* URD DLL register */ -REG_DLL_URD_CONTROL: - .word 0xfffeccc0 -DLL_URD_CONTROL_VAL: - .word 0x00800002 - -/* LRD DLL register */ -REG_DLL_LRD_CONTROL: - .word 0xfffecccc - -REG_WATCHDOG: - .word 0xfffec808 - -REG_MPU_LOAD_TIMER: - .word 0xfffec504 -REG_MPU_CNTL_TIMER: - .word 0xfffec500 - -/* 96 MHz Samsung Mobile DDR */ -SDRAM_CONFIG_VAL: - .word 0x001200f4 - -DLL_LRD_CONTROL_VAL: - .word 0x00800002 - -VAL_ARM_CKCTL: - .word 0x3000 -VAL_DPLL1_CTL: - .word 0x2830 - -#ifdef CONFIG_INNOVATOROMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x002130b0 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x00001131 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0x000055f0 -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -#endif - -#ifdef CONFIG_H2_OMAP1610 -VAL_TC_EMIFS_CS0_CONFIG: - .word 0x00203331 -VAL_TC_EMIFS_CS1_CONFIG: - .word 0x8180fff3 -VAL_TC_EMIFS_CS2_CONFIG: - .word 0xf800f22a -VAL_TC_EMIFS_CS3_CONFIG: - .word 0x88011131 -VAL_TC_EMIFS_CS1_ADVANCED: - .word 0x00000022 -#endif - -VAL_TC_EMIFF_SDRAM_CONFIG: - .word 0x010290fc -VAL_TC_EMIFF_MRS: - .word 0x00000027 - -VAL_ARM_IDLECT1: - .word 0x00000400 - -VAL_ARM_IDLECT2: - .word 0x00000886 -VAL_ARM_IDLECT3: - .word 0x00000015 - -WATCHDOG_VAL1: - .word 0x000000f5 -WATCHDOG_VAL2: - .word 0x000000a0 - -VAL_MPU_LOAD_TIMER: - .word 0xffffffff -VAL_MPU_CNTL_TIMER: - .word 0xffffffa1 - -/* command values */ -.equ CMD_SDRAM_NOP, 0x00000000 -.equ CMD_SDRAM_PRECHARGE, 0x00000001 -.equ CMD_SDRAM_AUTOREFRESH, 0x00000002 -.equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007 diff --git a/board/ti/omap1610inn/omap1610innovator.c b/board/ti/omap1610inn/omap1610innovator.c deleted file mode 100644 index 16e823766a9..00000000000 --- a/board/ti/omap1610inn/omap1610innovator.c +++ /dev/null @@ -1,309 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH - * Marius Groeger - * - * (C) Copyright 2002 - * David Mueller, ELSOFT AG, - * - * (C) Copyright 2003 - * Texas Instruments, - * Kshitij Gupta - * - * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004 - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#if defined(CONFIG_OMAP1610) -#include <./configs/omap1510.h> -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CS_AUTOBOOT -unsigned long omap_flash_base; -#endif - -void flash__init (void); -void ether__init (void); -void set_muxconf_regs (void); -void peripheral_power_enable (void); - -#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF) - -static inline void delay (unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - -/* - * Miscellaneous platform dependent initialisations - */ - -int board_init (void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x10000100; - - /* Configure MUX settings */ - set_muxconf_regs (); - peripheral_power_enable (); - -/* this speeds up your boot a quite a bit. However to make it - * work, you need make sure your kernel startup flush bug is fixed. - * ... rkw ... - */ - icache_enable (); - - flash__init (); - ether__init (); - return 0; -} - - -int misc_init_r (void) -{ - /* currently empty */ - return (0); -} - -/****************************** - Routine: - Description: -******************************/ -void flash__init (void) -{ -#define EMIFS_GlB_Config_REG 0xfffecc0c - unsigned int regval; - -#ifdef CONFIG_CS_AUTOBOOT - /* Check swapping of CS0 and CS3, set flash base accordingly */ - omap_flash_base = ((*((u32 *)OMAP_EMIFS_CONFIG_REG) & 0x02) == 0) ? - PHYS_FLASH_1_BM0 : PHYS_FLASH_1_BM1; -#endif - regval = *((volatile unsigned int *) EMIFS_GlB_Config_REG); - /* Turn off write protection for flash devices. */ - regval = regval | 0x0001; - *((volatile unsigned int *) EMIFS_GlB_Config_REG) = regval; -} -/************************************************************* - Routine:ether__init - Description: take the Ethernet controller out of reset and wait - for the EEPROM load to complete. -*************************************************************/ -void ether__init (void) -{ -#define ETH_CONTROL_REG 0x0400030b - -#ifdef CONFIG_H2_OMAP1610 - #define LAN_RESET_REGISTER 0x0400001c - - /* The debug board on which the lan chip resides may not be powered - * ON at the same time as the OMAP chip. So wait in a loop until the - * lan reset register (on the debug board) is available (powered on) - * and reset the lan chip. - */ - - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0001; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0001); - - do { - *((volatile unsigned short *) LAN_RESET_REGISTER) = 0x0000; - udelay (3); - } while (*((volatile unsigned short *) LAN_RESET_REGISTER) != 0x0000); -#endif - - *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; - udelay (3); -} - -/****************************** - Routine: - Description: -******************************/ -int dram_init (void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; -} - -/****************************************************** - Routine: set_muxconf_regs - Description: Setting up the configuration Mux registers - specific to the hardware -*******************************************************/ -void set_muxconf_regs (void) -{ - volatile unsigned int *MuxConfReg; - /* set each registers to its reset value; */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* setup for UART1 */ - *MuxConfReg &= ~(0x02000000); /* bit 25 */ - /* setup for UART2 */ - *MuxConfReg &= ~(0x01000000); /* bit 24 */ - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x08000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_5); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_6); - /*setup mux for UART3 */ - *MuxConfReg |= 0x00000001; /* bit3, 1, 0 (mux0 5,5,26) */ - *MuxConfReg &= ~0x0000003e; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_7); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_8); - /* Disable Uwire CS Hi-Z */ - *MuxConfReg |= 0x00001200; /*bit 9 for CS0 12 for CS3 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_9); - /* Need to turn on bits 21 and 12 in FUNC_MUX_CTRL_9 so the */ - /* hardware will actually use TX and RTS based on bit 25 in */ - /* FUNC_MUX_CTRL_0. I told you this thing was screwy! */ - *MuxConfReg |= 0x00201000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_A); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_B); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_C); - /* setup for UART2 */ - /* Need to turn on bits 27 and 24 in FUNC_MUX_CTRL_C so the */ - /* hardware will actually use TX and RTS based on bit 24 in */ - /* FUNC_MUX_CTRL_0. */ - *MuxConfReg |= 0x09000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_1); - *MuxConfReg = 0x00000000; - /* mux setup for SD/MMC driver */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_2); - *MuxConfReg &= 0xFFFE0FFF; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 13 for MMC2 XOR_CLK */ - *MuxConfReg &= ~(0x00002000); - /* bit 29 for UART 1 */ - *MuxConfReg &= ~(0x00002000); - MuxConfReg = - (volatile unsigned int *) ((unsigned int) FUNC_MUX_CTRL_0); - /* Configure for USB. Turn on VBUS_CTRL and VBUS_MODE. */ - *MuxConfReg |= 0x000C0000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int)USB_TRANSCEIVER_CTRL); - *MuxConfReg &= ~(0x00000070); - *MuxConfReg &= ~(0x00000008); - *MuxConfReg |= 0x00000003; - *MuxConfReg |= 0x00000180; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - /* bit 17, software controls VBUS */ - *MuxConfReg &= ~(0x00020000); - /* Enable USB 48 and 12M clocks */ - *MuxConfReg |= 0x00000200; - *MuxConfReg &= ~(0x00000180); - /*2.75V for MMCSDIO1 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) VOLTAGE_CTRL_0); - *MuxConfReg = 0x00001FE7; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_0); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_1); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_3); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_4); - *MuxConfReg = 0x00000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PULL_DWN_CTRL_4); - *MuxConfReg = 0x00000000; - /* Turn on UART2 48 MHZ clock */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) MOD_CONF_CTRL_0); - *MuxConfReg |= 0x40000000; - MuxConfReg = - (volatile unsigned int *) ((unsigned int) USB_OTG_CTRL); - /* setup for USB VBus detection OMAP161x */ - *MuxConfReg |= 0x00040000; /* bit 18 */ - MuxConfReg = - (volatile unsigned int *) ((unsigned int) PU_PD_SEL_2); - /* PullUps for SD/MMC driver */ - *MuxConfReg |= ~(0xFFFE0FFF); - MuxConfReg = - (volatile unsigned int *) ((unsigned int)COMP_MODE_CTRL_0); - *MuxConfReg = COMP_MODE_ENABLE; -} - -/****************************************************** - Routine: peripheral_power_enable - Description: Enable the power for UART1 -*******************************************************/ -void peripheral_power_enable (void) -{ -#define UART1_48MHZ_ENABLE ((unsigned short)0x0200) -#define SW_CLOCK_REQUEST ((volatile unsigned short *)0xFFFE0834) - - *SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE; -} - -#ifdef CONFIG_CMD_NET -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_LAN91C96 - rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); -#endif - return rc; -} -#endif diff --git a/boards.cfg b/boards.cfg index ade203488ca..c6090bab900 100644 --- a/boards.cfg +++ b/boards.cfg @@ -164,14 +164,6 @@ m28evk arm arm926ejs - denx mx28evk arm arm926ejs - freescale mx28 nhk8815 arm arm926ejs nhk8815 st nomadik nhk8815_onenand arm arm926ejs nhk8815 st nomadik nhk8815:BOOT_ONENAND -omap1610h2 arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610h2_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT -omap1610h2_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610h2_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT -omap1610inn arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610inn_cs0boot arm arm926ejs omap1610inn ti omap omap1610inn:CS0_BOOT -omap1610inn_cs3boot arm arm926ejs omap1610inn ti omap omap1610inn:CS3_BOOT -omap1610inn_cs_autoboot arm arm926ejs omap1610inn ti omap omap1610inn:CS_AUTOBOOT omap5912osk arm arm926ejs - ti omap omap730p2 arm arm926ejs omap730p2 ti omap omap730p2:CS3_BOOT omap730p2_cs0boot arm arm926ejs omap730p2 ti omap omap730p2:CS0_BOOT diff --git a/include/configs/omap1610h2.h b/include/configs/omap1610h2.h deleted file mode 100644 index d57e1a79bc0..00000000000 --- a/include/configs/omap1610h2.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2004 - * Texas Instruments. - * Kshitij Gupta - * Configuration settings for the TI OMAP 1610 H2 board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_H2_OMAP1610 1 /* on an H2 Board */ - -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_H2 - -/* input clock of PLL */ -/* the OMAP1610 H2 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 H2 */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "console=ttyS0,115200n8 noinitrd root=/dev/nfs ip=dhcp" -#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm" -#define CONFIG_SYS_AUTOLOAD "n" /* No autoload */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP1610 H2 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CONFIG_SYS_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap1610inn.h b/include/configs/omap1610inn.h deleted file mode 100644 index 7901b6c94e9..00000000000 --- a/include/configs/omap1610inn.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP1610 1 /* which is in a 1610 */ -#define CONFIG_INNOVATOROMAP1610 1 /* a Innovator Board */ - -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_INNOVATOR - -/* input clock of PLL */ -/* the OMAP1610 Innovator has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ - -#define CONFIG_MISC_INIT_R - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) - -/* - * Hardware drivers - */ -/* -*/ -#define CONFIG_LAN91C96 -#define CONFIG_LAN91C96_BASE 0x04000300 -#define CONFIG_LAN91C96_EXT_PHY - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ -#define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart on helen */ - -/* - * select serial console configuration - */ -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP1610 Innovator */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - - -/* - * Command line configuration. - */ -#include - -#define CONFIG_CMD_DHCP - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH - - -#include - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ - root=/dev/nfs rw nfsroot=157.87.82.48:\ - /home/a0875451/mwd/myfs/target ip=dhcp" -#define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ -#define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ -#define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ -#define CONFIG_BOOTFILE "uImage" /* file to load */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "OMAP1610 Innovator # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ - -/* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by - * DPLL1. This time is further subdivided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ -#define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ -#endif - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define PHYS_FLASH_1_BM1 0x00000000 /* Flash Bank #1 if booting from flash */ -#define PHYS_FLASH_1_BM0 0x0C000000 /* Flash Bank #1 if booting from RAM */ - -#ifdef CONFIG_CS_AUTOBOOT /* Determine CS assignment in runtime */ - -#ifndef __ASSEMBLY__ -extern unsigned long omap_flash_base; /* set in flash__init */ -#endif -#define CONFIG_SYS_FLASH_BASE omap_flash_base - -#elif defined(CONFIG_CS0_BOOT) - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM0 - -#else - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1_BM1 - -#endif - -#define PHYS_SRAM 0x20000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ -/* addr of environment */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM - -#endif /* __CONFIG_H */ -- cgit v1.3.1