From bcfb36537552441faeceb6b0089ab40a29b9dff3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Beno=C3=AEt=20Th=C3=A9baudeau?= Date: Sun, 29 Oct 2017 22:08:58 +0100 Subject: mmc: fsl_esdhc: Fix PIO timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following error has been observed on i.MX25 with a high-speed SDSC card: Data Write Failed in PIO Mode. It was caused by the timeout set on PRSSTAT.BWEN, which was triggered because this bit takes 15 ms to be set after writing the first block to DATPORT with this card. Without this timeout, all the blocks are properly written. This timeout was implemented by decrementing a variable, so it was depending on the CPU frequency. Fix this issue by setting this timeout to a long enough absolute duration (500 ms). Signed-off-by: Benoît Thébaudeau Cc: Stefano Babic Cc: Fabio Estevam Cc: Jaehoon Chung Reviewed-by: Fabio Estevam Reviewed-by: Jagan Teki --- include/fsl_esdhc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h index 02b362d5e36..de1f5e7d9f5 100644 --- a/include/fsl_esdhc.h +++ b/include/fsl_esdhc.h @@ -130,7 +130,7 @@ #define XFERTYP_DMAEN 0x00000001 #define CINS_TIMEOUT 1000 -#define PIO_TIMEOUT 100000 +#define PIO_TIMEOUT 500 #define DSADDR 0x2e004 -- cgit v1.2.3