From bf8dae5fcf400a593d56d5847d8ee62bc4c27855 Mon Sep 17 00:00:00 2001 From: T Karthik Reddy Date: Thu, 12 May 2022 04:05:33 -0600 Subject: spi: cadence-qspi: reset qspi flash for versal platform When flash operated at non default mode like DDR, flash need to be reset to operate in SDR mode to read flash ids by spi-nor framework. Reset the flash to the default state before using the flash. This reset is handled by a gpio driver, in case of mini U-Boot as gpio driver is disabled, we do raw read and write access by the registers. Versal platform utilizes spi calibration for read delay programming, so incase by default read delay property is set in DT. We make sure not to use read delay from DT by overwriting read_delay with -1. Signed-off-by: T Karthik Reddy Signed-off-by: Ashok Reddy Soma Link: https://lore.kernel.org/r/20220512100535.16364-4-ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek --- include/zynqmp_firmware.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index 76ec2141ff6..6a5f01c8391 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -428,6 +428,8 @@ enum pm_gem_config_type { #define PMUFW_V1_0 ((1 << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | 0) +#define PMIO_NODE_ID_BASE 0x1410801B + /* * Return payload size * Not every firmware call expects the same amount of return bytes, however the -- cgit v1.2.3