From ff6c6b2d6d9fc2cadd9bf171f106f8d53ba47496 Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Wed, 3 Jul 2019 12:11:39 +0300 Subject: include: configs: ls1028a: set SYS_RX_ETH_BUFFER to 8 LS1028A ethernet interfaces work with at least 8 BDs, set number of buffers to match that. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Acked-by: Joe Hershberger --- include/configs/ls1028a_common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 896d7a33b52..a6c7c3753d5 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -194,4 +194,8 @@ #include #endif +/* Ethernet */ +/* smallest ENETC BD ring has 8 entries */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + #endif /* __L1028A_COMMON_H */ -- cgit v1.3.1 From bca686a4f90de853f010ce76d6ab9ea95b528907 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 19 Jul 2019 00:29:54 +0300 Subject: net: tsec: Fix offset of MDIO registers for DM_ETH By convention, the eTSEC MDIO controller nodes are defined in DT at 0x2d24000 and 0x2d50000, but actually U-Boot does not touch the interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM, MDIO_EMAPM). That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM, MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at the 0x520 offset. So shift the DT-defined register map by the offset of MDIO_MIIMCFG when mapping the MDIO bus registers. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- drivers/net/tsec.c | 13 +++++++------ include/tsec.h | 4 +++- 2 files changed, 10 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 53eb5470f4c..576398676af 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -801,6 +801,7 @@ int tsec_probe(struct udevice *dev) u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE; ofnode parent; const char *phy_mode; + fdt_addr_t reg; int ret; pdata->iobase = (phys_addr_t)dev_read_addr(dev); @@ -817,15 +818,15 @@ int tsec_probe(struct udevice *dev) } parent = ofnode_get_parent(phandle_args.node); - if (ofnode_valid(parent)) { - int reg = ofnode_get_addr_index(parent, 0); - - priv->phyregs_sgmii = (struct tsec_mii_mng *)reg; - } else { - debug("No parent node for PHY?\n"); + if (!ofnode_valid(parent)) { + printf("No parent node for PHY?\n"); return -ENOENT; } + reg = ofnode_get_addr_index(parent, 0); + priv->phyregs_sgmii = (struct tsec_mii_mng *) + (reg + TSEC_MDIO_REGS_OFFSET); + ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0, &phandle_args); if (ret == 0) diff --git a/include/tsec.h b/include/tsec.h index e90095121bd..b17fa957df5 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -17,6 +17,8 @@ #include #include +#define TSEC_MDIO_REGS_OFFSET 0x520 + #ifndef CONFIG_DM_ETH #ifdef CONFIG_ARCH_LS1021A @@ -27,7 +29,7 @@ #define TSEC_MDIO_OFFSET 0x01000 #endif -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET) #define TSEC_GET_REGS(num, offset) \ (struct tsec __iomem *)\ -- cgit v1.3.1 From f588b4d205c209f54209e3aced62fa57c8fbe750 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 19 Jul 2019 00:29:59 +0300 Subject: arm: ls1021atwr: Convert to use driver model TSEC driver Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux --- arch/arm/cpu/armv7/ls102xa/cpu.c | 2 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 10 ++++++ arch/arm/dts/ls1021a-twr.dtsi | 32 ++++++++++++++++++ arch/arm/dts/ls1021a.dtsi | 30 +++++++++++++++-- board/freescale/ls1021atwr/ls1021atwr.c | 38 ---------------------- configs/ls1021atwr_nor_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_nor_defconfig | 2 ++ configs/ls1021atwr_nor_lpuart_defconfig | 2 ++ configs/ls1021atwr_qspi_defconfig | 2 ++ .../ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++ configs/ls1021atwr_sdcard_ifc_defconfig | 2 ++ configs/ls1021atwr_sdcard_qspi_defconfig | 2 ++ include/configs/ls1021atwr.h | 28 +--------------- 13 files changed, 85 insertions(+), 69 deletions(-) (limited to 'include') diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index ecf9e869855..9ccfe1042ce 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -296,7 +296,7 @@ int cpu_mmc_init(bd_t *bis) int cpu_eth_init(bd_t *bis) { -#ifdef CONFIG_TSEC_ENET +#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH) tsec_standard_init(bis); #endif diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index 8bf9c42b226..1aadffff599 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -16,12 +16,17 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; void ft_fixup_enet_phy_connect_type(void *fdt) { +#ifdef CONFIG_DM_ETH + struct udevice *dev; +#else struct eth_device *dev; +#endif struct tsec_private *priv; const char *enet_path, *phy_path; char enet[16]; @@ -29,7 +34,12 @@ void ft_fixup_enet_phy_connect_type(void *fdt) int phy_node; int i = 0; uint32_t ph; +#ifdef CONFIG_DM_ETH + char *name[3] = { "ethernet@2d10000", "ethernet@2d50000", + "ethernet@2d90000" }; +#else char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" }; +#endif for (; i < ARRAY_SIZE(name); i++) { dev = eth_get_dev_by_name(name[i]); diff --git a/arch/arm/dts/ls1021a-twr.dtsi b/arch/arm/dts/ls1021a-twr.dtsi index 5d3275ced91..27c96f95400 100644 --- a/arch/arm/dts/ls1021a-twr.dtsi +++ b/arch/arm/dts/ls1021a-twr.dtsi @@ -51,6 +51,26 @@ }; }; +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy0>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&enet2 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + &i2c0 { status = "okay"; }; @@ -84,12 +104,24 @@ sgmii_phy0: ethernet-phy@0 { reg = <0x0>; }; + rgmii_phy1: ethernet-phy@1 { reg = <0x1>; }; + sgmii_phy2: ethernet-phy@2 { reg = <0x2>; }; + + /* SGMII PCS for enet0 */ + tbi0: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + /* SGMII PCS for enet1 */ tbi1: tbi-phy@1f { reg = <0x1f>; device_type = "tbi-phy"; diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi index 7fb24ab6878..e419d9c44fc 100644 --- a/arch/arm/dts/ls1021a.dtsi +++ b/arch/arm/dts/ls1021a.dtsi @@ -350,12 +350,36 @@ <&platform_clk 1>; }; + enet0: ethernet@2d10000 { + compatible = "fsl,etsec2"; + reg = <0x2d10000 0x1000>; + status = "disabled"; + }; + + enet1: ethernet@2d50000 { + compatible = "fsl,etsec2"; + reg = <0x2d50000 0x1000>; + status = "disabled"; + }; + + enet2: ethernet@2d90000 { + compatible = "fsl,etsec2"; + reg = <0x2d90000 0x1000>; + status = "disabled"; + }; + mdio0: mdio@2d24000 { - compatible = "gianfar"; - device_type = "mdio"; + compatible = "fsl,etsec2-mdio"; + reg = <0x2d24000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + }; + + mdio1: mdio@2d64000 { + compatible = "fsl,etsec2-mdio"; + reg = <0x2d64000 0x4000>; #address-cells = <1>; #size-cells = <0>; - reg = <0x2d24000 0x4000>; }; usb@8600000 { diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 01ba1bc9621..fcf2ec97889 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -248,44 +248,6 @@ int board_mmc_init(bd_t *bis) int board_eth_init(bd_t *bis) { -#ifdef CONFIG_TSEC_ENET - struct fsl_pq_mdio_info mdio_info; - struct tsec_info_struct tsec_info[4]; - int num = 0; - -#ifdef CONFIG_TSEC1 - SET_STD_TSEC_INFO(tsec_info[num], 1); - if (is_serdes_configured(SGMII_TSEC1)) { - puts("eTSEC1 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC2 - SET_STD_TSEC_INFO(tsec_info[num], 2); - if (is_serdes_configured(SGMII_TSEC2)) { - puts("eTSEC2 is in sgmii mode.\n"); - tsec_info[num].flags |= TSEC_SGMII; - } - num++; -#endif -#ifdef CONFIG_TSEC3 - SET_STD_TSEC_INFO(tsec_info[num], 3); - tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID; - num++; -#endif - if (!num) { - printf("No TSECs initialized\n"); - return 0; - } - - mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; - mdio_info.name = DEFAULT_MII_NAME; - fsl_pq_mdio_init(bis, &mdio_info); - - tsec_eth_init(bis, tsec_info, num); -#endif - return pci_eth_init(bis); } diff --git a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig index 6c4bb9aaf66..830affc925b 100644 --- a/configs/ls1021atwr_nor_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_nor_SECURE_BOOT_defconfig @@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_nor_defconfig b/configs/ls1021atwr_nor_defconfig index 9d8c2024c04..c4d18c6f690 100644 --- a/configs/ls1021atwr_nor_defconfig +++ b/configs/ls1021atwr_nor_defconfig @@ -40,7 +40,9 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_nor_lpuart_defconfig b/configs/ls1021atwr_nor_lpuart_defconfig index b9cfdb6fd69..b74d58a3487 100644 --- a/configs/ls1021atwr_nor_lpuart_defconfig +++ b/configs/ls1021atwr_nor_lpuart_defconfig @@ -42,7 +42,9 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_qspi_defconfig b/configs/ls1021atwr_qspi_defconfig index 8c27c5908cb..911061a3788 100644 --- a/configs/ls1021atwr_qspi_defconfig +++ b/configs/ls1021atwr_qspi_defconfig @@ -42,7 +42,9 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 979878d560f..d8c26393cea 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -53,7 +53,9 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index 59af172cb8a..d23c87504c9 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -54,7 +54,9 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index d7fec5e365e..7b2c2900a06 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -53,7 +53,9 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_MII=y +CONFIG_DM_ETH=y CONFIG_TSEC_ENET=y +CONFIG_PHY_ATHEROS=y CONFIG_PCI=y CONFIG_DM_PCI=y CONFIG_DM_PCI_COMPAT=y diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index de0c9c7f26a..cbf7a496a56 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -260,33 +260,7 @@ */ #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 +#define CONFIG_ETHPRIME "ethernet@2d10000" #endif /* PCIe */ -- cgit v1.3.1 From c40e65eb16e4b57697bb90dae0f6ca0303e7dfe7 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 19 Jul 2019 00:30:00 +0300 Subject: configs: ls1021atwr: Fix distro_bootcmd for QSPI boot Due to a typo, "run qspi_bootcmd" and "env exists secureboot" got concatenated instead of being separated by a semicolon. Signed-off-by: Vladimir Oltean Reviewed-by: Bin Meng Acked-by: Joe Hershberger --- include/configs/ls1021atwr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index cbf7a496a56..31abee81edd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -418,7 +418,7 @@ #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt" #elif defined(CONFIG_SD_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ -- cgit v1.3.1 From 8782122052481f60638c2191a5512a644bb57abb Mon Sep 17 00:00:00 2001 From: Jianchao Wang Date: Fri, 19 Jul 2019 00:30:01 +0300 Subject: Add support for the NXP LS1021A-TSN board The LS1021A-TSN is a development board built by VVDN/Argonboards in partnership with NXP. It features the LS1021A SoC and the first-generation SJA1105T Ethernet switch for prototyping implementations of a subset of IEEE 802.1 TSN standards. Supported boot media: microSD card (via SPL), QSPI flash. Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which is 64 MB in size and has an erase sector size of 256KB (therefore, flashing the RCW would erase part of U-Boot). Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which is only 32 MB in size but has an erase sector size of 64KB (therefore the RCW image can be flashed without erasing U-Boot). To avoid the problems above, the U-Boot base address has been selected at 0x100000 (the start of the 5th 256KB erase sector), which works for all board revisions. Actually 0x40000 would have been enough, but 0x100000 is common for all Layerscape devices. eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is disabled. Signed-off-by: Xiaoliang Yang Signed-off-by: Mingkai Hu Signed-off-by: Jianchao Wang Signed-off-by: Changming Huang Signed-off-by: Vladimir Oltean [Vladimir] Code taken from https://github.com/openil/u-boot (which itself is mostly copied from ls1021a-iot) and adapted with the following changes: - Add a008850 errata workaround - Converted eTSEC, MMC to DM to avoid all build warnings - Plugged in distro boot feature, including support for extlinux.conf - Added defconfig for QSPI boot - Added the board/freescale/ls1021atsn/README.rst for initial setup - Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not get overwritten during copying of the u-boot.bin payload from MMC to DDR. Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- arch/arm/Kconfig | 14 ++ arch/arm/dts/Makefile | 2 +- arch/arm/dts/ls1021a-tsn.dts | 77 ++++++++ board/freescale/ls1021atsn/Kconfig | 18 ++ board/freescale/ls1021atsn/MAINTAINERS | 8 + board/freescale/ls1021atsn/Makefile | 3 + board/freescale/ls1021atsn/README.rst | 97 ++++++++++ board/freescale/ls1021atsn/ls1021atsn.c | 260 ++++++++++++++++++++++++++ board/freescale/ls1021atsn/ls102xa_pbi.cfg | 15 ++ board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg | 8 + configs/ls1021atsn_qspi_defconfig | 79 ++++++++ configs/ls1021atsn_sdcard_defconfig | 91 +++++++++ include/configs/ls1021atsn.h | 250 +++++++++++++++++++++++++ 13 files changed, 921 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/ls1021a-tsn.dts create mode 100644 board/freescale/ls1021atsn/Kconfig create mode 100644 board/freescale/ls1021atsn/MAINTAINERS create mode 100644 board/freescale/ls1021atsn/Makefile create mode 100644 board/freescale/ls1021atsn/README.rst create mode 100644 board/freescale/ls1021atsn/ls1021atsn.c create mode 100644 board/freescale/ls1021atsn/ls102xa_pbi.cfg create mode 100644 board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg create mode 100644 configs/ls1021atsn_qspi_defconfig create mode 100644 configs/ls1021atsn_sdcard_defconfig create mode 100644 include/configs/ls1021atsn.h (limited to 'include') diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 51d4acedac4..1cd7aeb7da7 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1352,6 +1352,19 @@ config TARGET_LS1021ATWR select SUPPORT_SPL imply SCSI +config TARGET_LS1021ATSN + bool "Support ls1021atsn" + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select LS1_DEEP_SLEEP + select SUPPORT_SPL + imply SCSI + config TARGET_LS1021AIOT bool "Support ls1021aiot" select ARCH_LS1021A @@ -1745,6 +1758,7 @@ source "board/freescale/ls1028a/Kconfig" source "board/freescale/ls1021aqds/Kconfig" source "board/freescale/ls1043aqds/Kconfig" source "board/freescale/ls1021atwr/Kconfig" +source "board/freescale/ls1021atsn/Kconfig" source "board/freescale/ls1021aiot/Kconfig" source "board/freescale/ls1046aqds/Kconfig" source "board/freescale/ls1043ardb/Kconfig" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f5535078c72..e985884d9ac 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -328,7 +328,7 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ - ls1021a-iot-duart.dtb + ls1021a-iot-duart.dtb ls1021a-tsn.dtb dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-rdb.dtb \ fsl-ls2081a-rdb.dtb \ diff --git a/arch/arm/dts/ls1021a-tsn.dts b/arch/arm/dts/ls1021a-tsn.dts new file mode 100644 index 00000000000..f633074099d --- /dev/null +++ b/arch/arm/dts/ls1021a-tsn.dts @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "NXP LS1021A-TSN Board"; + + aliases { + enet0-sgmii-phy = &sgmii_phy2; + enet1-sgmii-phy = &sgmii_phy1; + spi0 = &qspi; + spi1 = &dspi1; + }; +}; + +&enet0 { + tbi-handle = <&tbi0>; + phy-handle = <&sgmii_phy2>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&enet1 { + tbi-handle = <&tbi1>; + phy-handle = <&sgmii_phy1>; + phy-mode = "sgmii"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&mdio0 { + /* AR8031 */ + sgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + + /* AR8031 */ + sgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + + /* SGMII PCS for enet0 */ + tbi0: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + /* SGMII PCS for enet1 */ + tbi1: tbi-phy@1f { + reg = <0x1f>; + device_type = "tbi-phy"; + }; +}; + +&qspi { + bus-num = <0>; + status = "okay"; + + flash@0 { + compatible = "spi-flash"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/board/freescale/ls1021atsn/Kconfig b/board/freescale/ls1021atsn/Kconfig new file mode 100644 index 00000000000..d999fa46900 --- /dev/null +++ b/board/freescale/ls1021atsn/Kconfig @@ -0,0 +1,18 @@ +# SPDX-License-Identifier: GPL-2.0 +if TARGET_LS1021ATSN + +config SYS_BOARD + default "ls1021atsn" + +config SYS_VENDOR + default "freescale" + +config SYS_SOC + default "ls102xa" + +config SYS_CONFIG_NAME + default "ls1021atsn" + +source "board/freescale/common/Kconfig" + +endif diff --git a/board/freescale/ls1021atsn/MAINTAINERS b/board/freescale/ls1021atsn/MAINTAINERS new file mode 100644 index 00000000000..560bb615d2f --- /dev/null +++ b/board/freescale/ls1021atsn/MAINTAINERS @@ -0,0 +1,8 @@ +NXP LS1021A-TSN Board +M: Vladimir Oltean +S: Maintained +F: arch/arm/dts/ls1021a-tsn.dts +F: board/freescale/ls1021atsn/ +F: include/configs/ls1021atsn.h +F: configs/ls1021atsn_qspi_defconfig +F: configs/ls1021atsn_sdcard_defconfig diff --git a/board/freescale/ls1021atsn/Makefile b/board/freescale/ls1021atsn/Makefile new file mode 100644 index 00000000000..b4808f05e8e --- /dev/null +++ b/board/freescale/ls1021atsn/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +obj-y += ls1021atsn.o +obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o diff --git a/board/freescale/ls1021atsn/README.rst b/board/freescale/ls1021atsn/README.rst new file mode 100644 index 00000000000..cdec02f1a35 --- /dev/null +++ b/board/freescale/ls1021atsn/README.rst @@ -0,0 +1,97 @@ +.. SPDX-License-Identifier: GPL-2.0 + +LS1021A-TSN Board Overview +========================== + + - 1GB DDR3 at 800 MHz + - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash + - Ethernet + - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031) + - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R) + - One internal RGMII port connected to the switch + - SDHC + - microSDHC/SDXC connector + - Other I/O + - One Serial port + - Arduino and expansion headers + - mPCIE slot + - SATA port + - USB3.0 port + +LS1021A Memory map +================== + +The addresses in brackets are physical addresses. + +============== ============== ============================== ======= +Start Address End Address Description Size +============== ============== ============================== ======= +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB +============== ============== ============================== ======= + +Compiling and flashing +====================== + +The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that +can be used to update its internal QSPI flash (which is empty out of the +factory). + +To compile and flash an SD card image:: + + make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/ + => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100 + +For the QSPI flash, first obtain the Reset Configuration Word binary for +bootimg from the QSPI flash from the rcw project +(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw):: + + make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/ + +The above RCW binary takes care of swapping the QSPI AMBA memory, so that the +U-Boot binary does not need to be swapped when flashing it. + +To compile and flash a U-Boot image for QSPI:: + + make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/ + +Then optionally create a custom uboot-env.txt file (although the default +environment already supports distro boot) and convert it to binary format:: + + mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt + +To program the QSPI flash with the images:: + + => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize} + => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize} + => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize} + +The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC +addresses of the Ethernet interfaces, however the EEPROM comes blank out of +the factory, and the MAC addresses are printed on a label on the bottom of +the boards. + +To write the MAC addresses to the EEPROM, the following needs to be done once:: + + => mac id + => mac 0 00:1F:7B:xx:xx:xx + => mac 1 00:1F:7B:xx:xx:xx + => mac 2 00:1F:7B:xx:xx:xx + => mac save + +The switch ports do not have their own MAC address - they inherit it from the +master enet2 port. + +Known issues and limitations +============================ + +- The 4 SJA1105 switch ports are not functional in U-Boot for now. +- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is + no way to talk to the CPLD for e.g. running the "qixis_reset" command, or + turning the fan on, etc. diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c new file mode 100644 index 00000000000..39e825ca496 --- /dev/null +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright 2016-2019 NXP Semiconductors + */ +#include +#include +#include +#include +#include +#include +#include "../common/sleep.h" +#include +#include +#include +#include +#include +#ifdef CONFIG_U_QE +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void ddrmc_init(void) +{ +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + u32 temp_sdram_cfg, tmp; + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); + + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS); + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG); + + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0); + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1); + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2); + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3); + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4); + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + out_be32(&ddr->sdram_cfg_2, + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT); + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE); + out_be32(&ddr->init_ext_addr, (1 << 31)); + + /* DRAM VRef will not be trained */ + out_be32(&ddr->ddr_cdr2, + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN); + } else +#endif + { + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2); + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2); + } + + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE); + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2); + + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL); + + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL); + + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2); + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); + + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1); + + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL); + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL); + + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2); + + /* DDR erratum A-009942 */ + tmp = in_be32(&ddr->debug[28]); + out_be32(&ddr->debug[28], tmp | 0x0070006f); + + udelay(1); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* enter self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI); + } else +#endif + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI); + + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg); + +#ifdef CONFIG_DEEP_SLEEP + if (is_warm_boot()) { + /* exit self-refresh */ + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2); + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR; + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg); + } +#endif +#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */ +} + +int dram_init(void) +{ + ddrmc_init(); + + erratum_a008850_post(); + + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD) + fsl_dp_resume(); +#endif + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} + +int board_early_init_f(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + +#ifdef CONFIG_TSEC_ENET + /* + * Clear BD & FR bits for big endian BD's and frame data (aka set + * correct eTSEC endianness). This is crucial in ensuring that it does + * not report Data Parity Errors in its RX/TX FIFOs when attempting to + * send traffic. + */ + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */ + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); +#endif + + arch_soc_init(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) { + timer_init(); + dram_init(); + } +#endif + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void board_init_f(ulong dummy) +{ + void (*second_uboot)(void); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + get_clocks(); + +#if defined(CONFIG_DEEP_SLEEP) + if (is_warm_boot()) + fsl_dp_disable_console(); +#endif + + preloader_console_init(); + + dram_init(); + + /* Allow OCRAM access permission as R/W */ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); + enable_layerscape_ns_access(); +#endif + + /* + * if it is woken up from deep sleep, then jump to second + * stage U-Boot and continue executing without recopying + * it from SD since it has already been reserved in memory + * in last boot. + */ + if (is_warm_boot()) { + second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE; + second_uboot(); + } + + board_init_r(NULL, 0); +} +#endif + +int board_init(void) +{ +#ifndef CONFIG_SYS_FSL_NO_SERDES + fsl_serdes_init(); +#endif + ls102xa_smmu_stream_id_init(); + +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif + +#ifdef CONFIG_U_QE + u_qe_init(); +#endif + + return 0; +} + +#if defined(CONFIG_SPL_BUILD) +void spl_board_init(void) +{ + ls102xa_smmu_stream_id_init(); +} +#endif + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_CHAIN_OF_TRUST + fsl_setenv_chain_of_trust(); +#endif + + return 0; +} +#endif + +#if defined(CONFIG_MISC_INIT_R) +int misc_init_r(void) +{ +#ifdef CONFIG_FSL_DEVICE_DISABLE + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); +#endif + +#ifdef CONFIG_FSL_CAAM + return sec_init(); +#endif +} +#endif + +#if defined(CONFIG_DEEP_SLEEP) +void board_sleep_prepare(void) +{ +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS + enable_layerscape_ns_access(); +#endif +} +#endif + +int ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif + + return 0; +} diff --git a/board/freescale/ls1021atsn/ls102xa_pbi.cfg b/board/freescale/ls1021atsn/ls102xa_pbi.cfg new file mode 100644 index 00000000000..ba1499b2644 --- /dev/null +++ b/board/freescale/ls1021atsn/ls102xa_pbi.cfg @@ -0,0 +1,15 @@ +# PBI commands + +09570200 ffffffff +09570158 00000300 +8940007c 21f47300 + +# Configure Scratch register +09ee0200 10000000 +# Configure alternate space +09570158 00001000 +# Flush PBL data +096100c0 000FFFFF + +09ea085c 00502880 +09ea0560 80800000 diff --git a/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg new file mode 100644 index 00000000000..a6fc91436f2 --- /dev/null +++ b/board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg @@ -0,0 +1,8 @@ +# PBL preamble and RCW header +aa55aa55 01ee0100 + +# Disable IFC, enable QSPI and DSPI +0608000c 00000000 00000000 00000000 +30000000 08007900 40105a00 21046000 +00000000 00000000 00000000 10002000 +20124801 8804b340 00000000 00000000 diff --git a/configs/ls1021atsn_qspi_defconfig b/configs/ls1021atsn_qspi_defconfig new file mode 100644 index 00000000000..d1a6dad2d79 --- /dev/null +++ b/configs/ls1021atsn_qspi_defconfig @@ -0,0 +1,79 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATSN=y +CONFIG_SYS_TEXT_BASE=0x40100000 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_FAT=y +CONFIG_FSL_ESDHC=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +CONFIG_MII=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_CMD_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_CMD_MMC=y +CONFIG_DM_MMC=y +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_CMD_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_FSL=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_HAS_FSL_XHCI_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_EXT2=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_FIXED=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMDLINE_TAG=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_LONGHELP=y +CONFIG_FIT=y +CONFIG_CMD_DM=y +CONFIG_AHCI=y +CONFIG_CMD_I2C=y +CONFIG_BLK=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_SILENT_CONSOLE=y +CONFIG_DISTRO_DEFAULTS=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig new file mode 100644 index 00000000000..299b3003706 --- /dev/null +++ b/configs/ls1021atsn_sdcard_defconfig @@ -0,0 +1,91 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1021ATSN=y +CONFIG_SPL_TEXT_BASE=0x10000000 +CONFIG_SYS_TEXT_BASE=0x82000000 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_MISC_INIT_R=y +CONFIG_SPL=y +CONFIG_SPL_FRAMEWORK=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SPL_WATCHDOG_SUPPORT=y +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8 +CONFIG_HUSH_PARSER=y +CONFIG_CMD_GREPENV=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_FAT=y +CONFIG_CMD_MMC=y +CONFIG_FSL_ESDHC=y +CONFIG_CMD_SF=y +CONFIG_OF_CONTROL=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_DM=y +CONFIG_FSL_CAAM=y +CONFIG_SPI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_NETDEVICES=y +CONFIG_DM_ETH=y +CONFIG_TSEC_ENET=y +CONFIG_MII=y +CONFIG_SYS_NS16550=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_DATAFLASH=y +CONFIG_FSL_DSPI=y +CONFIG_FSL_QSPI=y +CONFIG_PCI=y +CONFIG_CMD_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_CMD_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_FSL=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_HAS_FSL_XHCI_USB=y +CONFIG_USB_STORAGE=y +CONFIG_CMD_EXT2=y +CONFIG_PCIE_LAYERSCAPE=y +CONFIG_PHYLIB=y +CONFIG_PHY_GIGE=y +CONFIG_PHY_ATHEROS=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_FIXED=y +CONFIG_CMD_PING=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMDLINE_TAG=y +CONFIG_CMDLINE_EDITING=y +CONFIG_AUTO_COMPLETE=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_LONGHELP=y +CONFIG_FIT=y +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_CMD_DM=y +CONFIG_AHCI=y +CONFIG_CMD_I2C=y +CONFIG_BLK=y +CONFIG_DM_MMC=y +CONFIG_CMD_PART=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_FS_UUID=y +CONFIG_SILENT_CONSOLE=y +CONFIG_DISTRO_DEFAULTS=y diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h new file mode 100644 index 00000000000..b011cb2a841 --- /dev/null +++ b/include/configs/ls1021atsn.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_DEEP_SLEEP + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + "board/freescale/ls1021atsn/ls102xa_pbi.cfg" +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_SECURE_BOOT */ + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw U-Boot image instead of FIT image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_BAUDRATE 115200 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* QSPI */ +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x80008000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x8f000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0x80008000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + BOOTENV \ + "boot_scripts=ls1021atsn_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "run scan_dev_for_extlinux; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo && mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* Environment */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif + +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ + +#endif -- cgit v1.3.1 From 53fd12cfe17d0b6df2cd924fe943cc8f8bee03b9 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Wed, 24 Jul 2019 04:09:44 +0000 Subject: riscv: sifive: fu540: Sync-up config header with RISC-V QEMU support We typically use same set of distro images (yocto, debian, fedora, etc.) on both QEMU RISC-V virt machine and SiFive Unleashed board. With growing kernel and ramdisk images, we need to re-adjust default U-Boot environment variables. The config header for QEMU RISC-V virt machine has been already updated to handle bigger kernel and ramdisk images hence this patch updates SiFive FU540 config header accordingly. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Joe Hershberger Reviewed-by: David Abdurachmanov Tested-by: David Abdurachmanov --- include/configs/sifive-fu540.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 7007b5f6af5..858b7a7da1d 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -18,12 +18,12 @@ #define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ func(DHCP, dhcp, na) @@ -33,11 +33,15 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x80600000\0" \ - "fdt_addr_r=0x82200000\0" \ - "scriptaddr=0x82300000\0" \ - "pxefile_addr_r=0x82400000\0" \ - "ramdisk_addr_r=0x82500000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" + #endif /* __CONFIG_H */ -- cgit v1.3.1 From e809285d4942cbd6c3efb381bd48dcf8294639a7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 24 Jul 2019 10:12:07 +0200 Subject: net: davinci_emac: convert to using the driver model Now that we removed all legacy boards selecting TI_EMAC we can completely convert the driver code to using the driver model. This patch also updates all remaining users of davinci_emac. Signed-off-by: Bartosz Golaszewski Tested-by: Adam Ford #am3517-evm & da850-evm Reviewed-by: Ramon Fried --- arch/arm/mach-davinci/cpu.c | 13 ------ arch/arm/mach-omap2/omap3/emac.c | 3 +- board/davinci/da8xxevm/da850evm.c | 6 --- board/davinci/da8xxevm/omapl138_lcdk.c | 14 ------- board/logicpd/am3517evm/am3517evm.c | 1 - board/ti/ti816x/evm.c | 3 +- configs/am3517_evm_defconfig | 1 + configs/da850_am18xxevm_defconfig | 1 + configs/da850evm_defconfig | 1 + configs/da850evm_direct_nor_defconfig | 1 + configs/da850evm_nand_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + configs/ti816x_evm_defconfig | 1 + drivers/net/ti/davinci_emac.c | 77 ++++++++++++++++++---------------- include/netdev.h | 1 - 15 files changed, 51 insertions(+), 74 deletions(-) (limited to 'include') diff --git a/arch/arm/mach-davinci/cpu.c b/arch/arm/mach-davinci/cpu.c index f97ad3fc740..9fd6564d044 100644 --- a/arch/arm/mach-davinci/cpu.c +++ b/arch/arm/mach-davinci/cpu.c @@ -5,7 +5,6 @@ */ #include -#include #include #include @@ -90,15 +89,3 @@ int set_cpu_clk_info(void) gd->bd->bi_dsp_freq = 0; return 0; } - -/* - * Initializes on-chip ethernet controllers. - * to override, implement board_eth_init() - */ -int cpu_eth_init(bd_t *bis) -{ -#if defined(CONFIG_DRIVER_TI_EMAC) - davinci_emac_initialize(); -#endif - return 0; -} diff --git a/arch/arm/mach-omap2/omap3/emac.c b/arch/arm/mach-omap2/omap3/emac.c index c79e870183e..fb0c9188f57 100644 --- a/arch/arm/mach-omap2/omap3/emac.c +++ b/arch/arm/mach-omap2/omap3/emac.c @@ -7,7 +7,6 @@ */ #include -#include #include #include @@ -24,5 +23,5 @@ int cpu_eth_init(bd_t *bis) reset &= ~CPGMACSS_SW_RST; writel(reset, &am35x_scm_general_regs->ip_sw_reset); - return davinci_emac_initialize(); + return 0; } diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c index 5180128db46..43483d526ad 100644 --- a/board/davinci/da8xxevm/da850evm.c +++ b/board/davinci/da8xxevm/da850evm.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -482,11 +481,6 @@ int board_eth_init(bd_t *bis) if (rmii_hw_init()) printf("RMII hardware init failed!!!\n"); #endif - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - return 0; } #endif /* CONFIG_DRIVER_TI_EMAC */ diff --git a/board/davinci/da8xxevm/omapl138_lcdk.c b/board/davinci/da8xxevm/omapl138_lcdk.c index fe1bf441014..dd115514283 100644 --- a/board/davinci/da8xxevm/omapl138_lcdk.c +++ b/board/davinci/da8xxevm/omapl138_lcdk.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -229,19 +228,6 @@ int board_init(void) #ifdef CONFIG_DRIVER_TI_EMAC -/* - * Initializes on-board ethernet controllers. - */ -int board_eth_init(bd_t *bis) -{ - if (!davinci_emac_initialize()) { - printf("Error: Ethernet init failed!\n"); - return -1; - } - - return 0; -} - #endif /* CONFIG_DRIVER_TI_EMAC */ #define CFG_MAC_ADDR_SPI_BUS 0 diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index 10031a48018..bfd4e782749 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -28,7 +28,6 @@ #include #include #include -#include #include "am3517evm.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c index 07a084bab8a..240df8cbe13 100644 --- a/board/ti/ti816x/evm.c +++ b/board/ti/ti816x/evm.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -56,7 +55,7 @@ int board_eth_init(bd_t *bis) printf("Unable to read MAC address. Set \n"); } - return davinci_emac_initialize(); + return 0; } #ifdef CONFIG_SPL_BUILD diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index b9f59f32918..5cb76322dfa 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -44,6 +44,7 @@ CONFIG_SYS_NAND_BUSWIDTH_16BIT=y CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000 CONFIG_SPL_NAND_SIMPLE=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_PINCTRL=y diff --git a/configs/da850_am18xxevm_defconfig b/configs/da850_am18xxevm_defconfig index 7ecdc361ce8..adcbe1d35d3 100644 --- a/configs/da850_am18xxevm_defconfig +++ b/configs/da850_am18xxevm_defconfig @@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_DM_SERIAL=y diff --git a/configs/da850evm_defconfig b/configs/da850evm_defconfig index c0950582825..f7c679d3b51 100644 --- a/configs/da850evm_defconfig +++ b/configs/da850evm_defconfig @@ -59,6 +59,7 @@ CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_PINCTRL=y diff --git a/configs/da850evm_direct_nor_defconfig b/configs/da850evm_direct_nor_defconfig index 166e77b8e3a..9b1da073845 100644 --- a/configs/da850evm_direct_nor_defconfig +++ b/configs/da850evm_direct_nor_defconfig @@ -50,6 +50,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_PINCTRL=y diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index 72710163467..8f06b8592b1 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -59,6 +59,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_DM_SERIAL=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index 48f251ebb80..466ae860cd8 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_DM_SERIAL=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig index 19519f80040..d341633fe10 100644 --- a/configs/ti816x_evm_defconfig +++ b/configs/ti816x_evm_defconfig @@ -47,6 +47,7 @@ CONFIG_SYS_I2C_OMAP24XX=y CONFIG_MMC_OMAP_HS=y CONFIG_NAND=y CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_ETH=y CONFIG_MII=y CONFIG_DRIVER_TI_EMAC=y CONFIG_SYS_NS16550=y diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 9d539849739..2bd9c51079d 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include @@ -107,8 +106,9 @@ static u_int8_t num_phy; phy_t phy[CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT]; -static int davinci_eth_set_mac_addr(struct eth_device *dev) +static int davinci_emac_write_hwaddr(struct udevice *dev) { + struct eth_pdata *pdata = dev_get_platdata(dev); unsigned long mac_hi; unsigned long mac_lo; @@ -118,12 +118,12 @@ static int davinci_eth_set_mac_addr(struct eth_device *dev) * Using channel 0 only - other channels are disabled * */ writel(0, &adap_emac->MACINDEX); - mac_hi = (dev->enetaddr[3] << 24) | - (dev->enetaddr[2] << 16) | - (dev->enetaddr[1] << 8) | - (dev->enetaddr[0]); - mac_lo = (dev->enetaddr[5] << 8) | - (dev->enetaddr[4]); + mac_hi = (pdata->enetaddr[3] << 24) | + (pdata->enetaddr[2] << 16) | + (pdata->enetaddr[1] << 8) | + (pdata->enetaddr[0]); + mac_lo = (pdata->enetaddr[5] << 8) | + (pdata->enetaddr[4]); writel(mac_hi, &adap_emac->MACADDRHI); #if defined(DAVINCI_EMAC_VERSION2) @@ -411,7 +411,7 @@ static void __attribute__((unused)) davinci_eth_gigabit_enable(int phy_addr) } /* Eth device open */ -static int davinci_eth_open(struct eth_device *dev, bd_t *bis) +static int davinci_emac_start(struct udevice *dev) { dv_reg_p addr; u_int32_t clkdiv, cnt, mac_control; @@ -447,7 +447,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) writel(1, &adap_emac->TXCONTROL); writel(1, &adap_emac->RXCONTROL); - davinci_eth_set_mac_addr(dev); + davinci_emac_write_hwaddr(dev); /* Set DMA 8 TX / 8 RX Head pointers to 0 */ addr = &adap_emac->TX0HDP; @@ -588,7 +588,7 @@ static void davinci_eth_ch_teardown(int ch) } /* Eth device close */ -static void davinci_eth_close(struct eth_device *dev) +static void davinci_emac_stop(struct udevice *dev) { debug_emac("+ emac_close\n"); @@ -619,8 +619,8 @@ static int tx_send_loop = 0; * This function sends a single packet on the network and returns * positive number (number of bytes transmitted) or negative for error */ -static int davinci_eth_send_packet (struct eth_device *dev, - void *packet, int length) +static int davinci_emac_send(struct udevice *dev, + void *packet, int length) { int ret_status = -1; int index; @@ -672,7 +672,7 @@ static int davinci_eth_send_packet (struct eth_device *dev, /* * This function handles receipt of a packet from the network */ -static int davinci_eth_rcv_packet (struct eth_device *dev) +static int davinci_emac_recv(struct udevice *dev, int flags, uchar **packetp) { volatile emac_desc *rx_curr_desc; volatile emac_desc *curr_desc; @@ -682,6 +682,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) rx_curr_desc = emac_rx_active_head; if (!rx_curr_desc) return 0; + *packetp = rx_curr_desc->buffer; status = rx_curr_desc->pkt_flag_len; if ((status & EMAC_CPPI_OWNERSHIP_BIT) == 0) { if (status & EMAC_CPPI_RX_ERROR_FRAME) { @@ -693,7 +694,6 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) rx_curr_desc->buff_off_len & 0xffff; invalidate_dcache_range(tmp, tmp + ALIGN(len, PKTALIGN)); - net_process_received_packet(rx_curr_desc->buffer, len); ret = len; } @@ -742,6 +742,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) } return (ret); } + return (0); } @@ -750,30 +751,12 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) * EMAC modules power or pin multiplexors, that is done by board_init() * much earlier in bootup process. Returns 1 on success, 0 otherwise. */ -int davinci_emac_initialize(void) +static int davinci_emac_probe(struct udevice *dev) { u_int32_t phy_id; u_int16_t tmp; int i; int ret; - struct eth_device *dev; - - dev = malloc(sizeof *dev); - - if (dev == NULL) - return -1; - - memset(dev, 0, sizeof *dev); - strcpy(dev->name, "DaVinci-EMAC"); - - dev->iobase = 0; - dev->init = davinci_eth_open; - dev->halt = davinci_eth_close; - dev->send = davinci_eth_send_packet; - dev->recv = davinci_eth_rcv_packet; - dev->write_hwaddr = davinci_eth_set_mac_addr; - - eth_register(dev); davinci_eth_mdio_enable(); @@ -854,5 +837,29 @@ int davinci_emac_initialize(void) phy[i].auto_negotiate(i); } #endif - return(1); + return 0; } + +static const struct eth_ops davinci_emac_ops = { + .start = davinci_emac_start, + .send = davinci_emac_send, + .recv = davinci_emac_recv, + .stop = davinci_emac_stop, + .write_hwaddr = davinci_emac_write_hwaddr, +}; + +static const struct udevice_id davinci_emac_ids[] = { + { .compatible = "ti,davinci-dm6467-emac" }, + { .compatible = "ti,am3517-emac", }, + { .compatible = "ti,dm816-emac", }, + { } +}; + +U_BOOT_DRIVER(davinci_emac) = { + .name = "davinci_emac", + .id = UCLASS_ETH, + .of_match = davinci_emac_ids, + .probe = davinci_emac_probe, + .ops = &davinci_emac_ops, + .platdata_auto_alloc_size = sizeof(struct eth_pdata), +}; diff --git a/include/netdev.h b/include/netdev.h index 0a1a3a2d8da..a40c4adaadd 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -30,7 +30,6 @@ int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); int bfin_EMAC_initialize(bd_t *bis); int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); -int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); -- cgit v1.3.1