From ff6c6b2d6d9fc2cadd9bf171f106f8d53ba47496 Mon Sep 17 00:00:00 2001 From: Alex Marginean Date: Wed, 3 Jul 2019 12:11:39 +0300 Subject: include: configs: ls1028a: set SYS_RX_ETH_BUFFER to 8 LS1028A ethernet interfaces work with at least 8 BDs, set number of buffers to match that. Signed-off-by: Alex Marginean Reviewed-by: Bin Meng Acked-by: Joe Hershberger --- include/configs/ls1028a_common.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 896d7a33b52..a6c7c3753d5 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -194,4 +194,8 @@ #include #endif +/* Ethernet */ +/* smallest ENETC BD ring has 8 entries */ +#define CONFIG_SYS_RX_ETH_BUFFER 8 + #endif /* __L1028A_COMMON_H */ -- cgit v1.2.3 From bca686a4f90de853f010ce76d6ab9ea95b528907 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 19 Jul 2019 00:29:54 +0300 Subject: net: tsec: Fix offset of MDIO registers for DM_ETH By convention, the eTSEC MDIO controller nodes are defined in DT at 0x2d24000 and 0x2d50000, but actually U-Boot does not touch the interrupt portion of the register map (MDIO_IEVENTM, MDIO_IMASKM, MDIO_EMAPM). That leaves only the MDIO bus registers (MDIO_MIIMCFG, MDIO_MIIMCOM, MDIO_MIIMADD, MDIO_MIIMADD, MDIO_MIIMCON, MDIO_MIIMSTAT) which start at the 0x520 offset. So shift the DT-defined register map by the offset of MDIO_MIIMCFG when mapping the MDIO bus registers. Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- include/tsec.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/tsec.h b/include/tsec.h index e90095121bd..b17fa957df5 100644 --- a/include/tsec.h +++ b/include/tsec.h @@ -17,6 +17,8 @@ #include #include +#define TSEC_MDIO_REGS_OFFSET 0x520 + #ifndef CONFIG_DM_ETH #ifdef CONFIG_ARCH_LS1021A @@ -27,7 +29,7 @@ #define TSEC_MDIO_OFFSET 0x01000 #endif -#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + 0x520) +#define CONFIG_SYS_MDIO_BASE_ADDR (MDIO_BASE_ADDR + TSEC_MDIO_REGS_OFFSET) #define TSEC_GET_REGS(num, offset) \ (struct tsec __iomem *)\ -- cgit v1.2.3 From f588b4d205c209f54209e3aced62fa57c8fbe750 Mon Sep 17 00:00:00 2001 From: Bin Meng Date: Fri, 19 Jul 2019 00:29:59 +0300 Subject: arm: ls1021atwr: Convert to use driver model TSEC driver Now that we have added driver model support to the TSEC driver, convert ls1021atwr board to use it. This depends on previous DM series for ls1021atwr: http://patchwork.ozlabs.org/patch/561855/ Signed-off-by: Bin Meng Signed-off-by: Vladimir Oltean Acked-by: Joe Hershberger [Vladimir] Made the following changes: - Added 'status = "disabled";' for all Ethernet ports in ls1021a.dtsi - Fixed the confusion between the SGMII/TBI PCS for enet0 and enet1 - a mistake ported over from Linux. Each SGMII PCS lies on the private MDIO bus of the interface (and the RGMII enet2 has no SGMII PCS). - Added CONFIG_DM_ETH to all ls1021atwr_* defconfigs - Completely removed non-DM_ETH support from ls1021atwr - Changed "compatible" string from "fsl,tsec-mdio" to "fsl,etsec2-mdio" and from "fsl,tsec" to "fsl,etsec2" to match Linux --- include/configs/ls1021atwr.h | 28 +--------------------------- 1 file changed, 1 insertion(+), 27 deletions(-) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index de0c9c7f26a..cbf7a496a56 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -260,33 +260,7 @@ */ #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 +#define CONFIG_ETHPRIME "ethernet@2d10000" #endif /* PCIe */ -- cgit v1.2.3 From c40e65eb16e4b57697bb90dae0f6ca0303e7dfe7 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Fri, 19 Jul 2019 00:30:00 +0300 Subject: configs: ls1021atwr: Fix distro_bootcmd for QSPI boot Due to a typo, "run qspi_bootcmd" and "env exists secureboot" got concatenated instead of being separated by a semicolon. Signed-off-by: Vladimir Oltean Reviewed-by: Bin Meng Acked-by: Joe Hershberger --- include/configs/ls1021atwr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index cbf7a496a56..31abee81edd 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -418,7 +418,7 @@ #undef CONFIG_BOOTCOMMAND #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd" \ +#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ "env exists secureboot && esbc_halt" #elif defined(CONFIG_SD_BOOT) #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ -- cgit v1.2.3 From 8782122052481f60638c2191a5512a644bb57abb Mon Sep 17 00:00:00 2001 From: Jianchao Wang Date: Fri, 19 Jul 2019 00:30:01 +0300 Subject: Add support for the NXP LS1021A-TSN board The LS1021A-TSN is a development board built by VVDN/Argonboards in partnership with NXP. It features the LS1021A SoC and the first-generation SJA1105T Ethernet switch for prototyping implementations of a subset of IEEE 802.1 TSN standards. Supported boot media: microSD card (via SPL), QSPI flash. Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which is 64 MB in size and has an erase sector size of 256KB (therefore, flashing the RCW would erase part of U-Boot). Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which is only 32 MB in size but has an erase sector size of 64KB (therefore the RCW image can be flashed without erasing U-Boot). To avoid the problems above, the U-Boot base address has been selected at 0x100000 (the start of the 5th 256KB erase sector), which works for all board revisions. Actually 0x40000 would have been enough, but 0x100000 is common for all Layerscape devices. eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is disabled. Signed-off-by: Xiaoliang Yang Signed-off-by: Mingkai Hu Signed-off-by: Jianchao Wang Signed-off-by: Changming Huang Signed-off-by: Vladimir Oltean [Vladimir] Code taken from https://github.com/openil/u-boot (which itself is mostly copied from ls1021a-iot) and adapted with the following changes: - Add a008850 errata workaround - Converted eTSEC, MMC to DM to avoid all build warnings - Plugged in distro boot feature, including support for extlinux.conf - Added defconfig for QSPI boot - Added the board/freescale/ls1021atsn/README.rst for initial setup - Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not get overwritten during copying of the u-boot.bin payload from MMC to DDR. Acked-by: Joe Hershberger Reviewed-by: Bin Meng --- include/configs/ls1021atsn.h | 250 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 250 insertions(+) create mode 100644 include/configs/ls1021atsn.h (limited to 'include') diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h new file mode 100644 index 00000000000..b011cb2a841 --- /dev/null +++ b/include/configs/ls1021atsn.h @@ -0,0 +1,250 @@ +/* SPDX-License-Identifier: GPL-2.0 + * Copyright 2016-2018 NXP Semiconductors + * Copyright 2019 Vladimir Oltean + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR + +#define CONFIG_SYS_FSL_CLK + +#define CONFIG_DEEP_SLEEP + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) + +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE + +/* XHCI Support - enabled by default */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 + +#define CONFIG_SYS_CLK_FREQ 100000000 +#define CONFIG_DDR_CLK_FREQ 100000000 + +#define DDR_SDRAM_CFG 0x470c0008 +#define DDR_CS0_BNDS 0x008000bf +#define DDR_CS0_CONFIG 0x80014302 +#define DDR_TIMING_CFG_0 0x50550004 +#define DDR_TIMING_CFG_1 0xbcb38c56 +#define DDR_TIMING_CFG_2 0x0040d120 +#define DDR_TIMING_CFG_3 0x010e1000 +#define DDR_TIMING_CFG_4 0x00000001 +#define DDR_TIMING_CFG_5 0x03401400 +#define DDR_SDRAM_CFG_2 0x00401010 +#define DDR_SDRAM_MODE 0x00061c60 +#define DDR_SDRAM_MODE_2 0x00180000 +#define DDR_SDRAM_INTERVAL 0x18600618 +#define DDR_DDR_WRLVL_CNTL 0x8655f605 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505 +#define DDR_DDR_CDR1 0x80040000 +#define DDR_DDR_CDR2 0x00000001 +#define DDR_SDRAM_CLK_CNTL 0x02000000 +#define DDR_DDR_ZQ_CNTL 0x89080600 +#define DDR_CS0_CONFIG_2 0 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000 +#define SDRAM_CFG2_D_INIT 0x00000010 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 +#define SDRAM_CFG2_FRC_SR 0x80000000 +#define SDRAM_CFG_BI 0x00000001 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_SYS_FSL_PBL_PBI \ + "board/freescale/ls1021atsn/ls102xa_pbi.cfg" +#endif + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_FSL_PBL_RCW \ + "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +#endif /* ifdef CONFIG_SECURE_BOOT */ + +#define CONFIG_SPL_MAX_SIZE 0x1a000 +#define CONFIG_SPL_STACK 0x1001d000 +#define CONFIG_SPL_PAD_TO 0x1c000 + +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#ifdef CONFIG_U_BOOT_HDR_SIZE +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw U-Boot image instead of FIT image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ +#endif + +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) + +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_CHIP_SELECTS_PER_CTRL 4 + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + +#define CONFIG_BAUDRATE 115200 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 + +/* QSPI */ +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 + +/* PCIe */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" +#ifdef CONFIG_PCI +#define CONFIG_PCI_SCAN_SHOW +#endif + +#define CONFIG_LAYERSCAPE_NS_ACCESS +#define COUNTER_FREQUENCY 12500000 + +#define CONFIG_HWCONFIG +#define HWCONFIG_BUFFER_SIZE 256 + +#define CONFIG_FSL_DEVICE_DISABLE + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(USB, usb, 0) \ + func(DHCP, dhcp, na) +#include + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_high=0xffffffff\0" \ + "fdt_addr=0x64f00000\0" \ + "kernel_addr=0x61000000\0" \ + "kernelheader_addr=0x60800000\0" \ + "scriptaddr=0x80000000\0" \ + "scripthdraddr=0x80080000\0" \ + "fdtheader_addr_r=0x80100000\0" \ + "kernelheader_addr_r=0x80200000\0" \ + "kernel_addr_r=0x80008000\0" \ + "kernelheader_size=0x40000\0" \ + "fdt_addr_r=0x8f000000\0" \ + "ramdisk_addr_r=0xa0000000\0" \ + "load_addr=0x80008000\0" \ + "kernel_size=0x2800000\0" \ + "kernel_addr_sd=0x8000\0" \ + "kernel_size_sd=0x14000\0" \ + "kernelhdr_addr_sd=0x4000\0" \ + "kernelhdr_size_sd=0x10\0" \ + BOOTENV \ + "boot_scripts=ls1021atsn_boot.scr\0" \ + "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "scan_dev_for_boot=" \ + "echo Scanning ${devtype} " \ + "${devnum}:${distro_bootpart}...; " \ + "for prefix in ${boot_prefixes}; do " \ + "run scan_dev_for_scripts; " \ + "run scan_dev_for_extlinux; " \ + "done;" \ + "\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "${scripthdraddr} ${prefix}${boot_script_hdr} " \ + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" \ + "qspi_bootcmd=echo Trying load from qspi..;" \ + "sf probe && sf read $load_addr " \ + "$kernel_addr $kernel_size; env exists secureboot " \ + "&& sf read $kernelheader_addr_r $kernelheader_addr " \ + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ + "bootm $load_addr#$board\0" \ + "sd_bootcmd=echo Trying load from SD ..;" \ + "mmcinfo && mmc read $load_addr " \ + "$kernel_addr_sd $kernel_size_sd && " \ + "env exists secureboot && mmc read $kernelheader_addr_r " \ + "$kernelhdr_addr_sd $kernelhdr_size_sd " \ + " && esbc_validate ${kernelheader_addr_r};" \ + "bootm $load_addr#$board\0" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x82000000 + +#define CONFIG_LS102XA_STREAM_ID + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE +#else +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* Environment */ +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_SD_BOOT) +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_SIZE 0x20000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_OFFSET 0x300000 +#define CONFIG_ENV_SECT_SIZE 0x40000 +#endif + +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ + +#endif -- cgit v1.2.3 From 53fd12cfe17d0b6df2cd924fe943cc8f8bee03b9 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Wed, 24 Jul 2019 04:09:44 +0000 Subject: riscv: sifive: fu540: Sync-up config header with RISC-V QEMU support We typically use same set of distro images (yocto, debian, fedora, etc.) on both QEMU RISC-V virt machine and SiFive Unleashed board. With growing kernel and ramdisk images, we need to re-adjust default U-Boot environment variables. The config header for QEMU RISC-V virt machine has been already updated to handle bigger kernel and ramdisk images hence this patch updates SiFive FU540 config header accordingly. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Reviewed-by: Joe Hershberger Reviewed-by: David Abdurachmanov Tested-by: David Abdurachmanov --- include/configs/sifive-fu540.h | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) (limited to 'include') diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h index 7007b5f6af5..858b7a7da1d 100644 --- a/include/configs/sifive-fu540.h +++ b/include/configs/sifive-fu540.h @@ -18,12 +18,12 @@ #define CONFIG_SYS_MALLOC_LEN SZ_8M -#define CONFIG_SYS_BOOTM_LEN SZ_16M +#define CONFIG_SYS_BOOTM_LEN SZ_64M #define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 /* Environment options */ -#define CONFIG_ENV_SIZE SZ_4K +#define CONFIG_ENV_SIZE SZ_128K #define BOOT_TARGET_DEVICES(func) \ func(DHCP, dhcp, na) @@ -33,11 +33,15 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "fdt_high=0xffffffffffffffff\0" \ "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x80600000\0" \ - "fdt_addr_r=0x82200000\0" \ - "scriptaddr=0x82300000\0" \ - "pxefile_addr_r=0x82400000\0" \ - "ramdisk_addr_r=0x82500000\0" \ + "kernel_addr_r=0x84000000\0" \ + "fdt_addr_r=0x88000000\0" \ + "scriptaddr=0x88100000\0" \ + "pxefile_addr_r=0x88200000\0" \ + "ramdisk_addr_r=0x88300000\0" \ BOOTENV +#define CONFIG_PREBOOT \ + "setenv fdt_addr ${fdtcontroladdr};" \ + "fdt addr ${fdtcontroladdr};" + #endif /* __CONFIG_H */ -- cgit v1.2.3 From e809285d4942cbd6c3efb381bd48dcf8294639a7 Mon Sep 17 00:00:00 2001 From: Bartosz Golaszewski Date: Wed, 24 Jul 2019 10:12:07 +0200 Subject: net: davinci_emac: convert to using the driver model Now that we removed all legacy boards selecting TI_EMAC we can completely convert the driver code to using the driver model. This patch also updates all remaining users of davinci_emac. Signed-off-by: Bartosz Golaszewski Tested-by: Adam Ford #am3517-evm & da850-evm Reviewed-by: Ramon Fried --- include/netdev.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/netdev.h b/include/netdev.h index 0a1a3a2d8da..a40c4adaadd 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -30,7 +30,6 @@ int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); int bfin_EMAC_initialize(bd_t *bis); int calxedaxgmac_initialize(u32 id, ulong base_addr); int cs8900_initialize(u8 dev_num, int base_addr); -int davinci_emac_initialize(void); int dc21x4x_initialize(bd_t *bis); int designware_initialize(ulong base_addr, u32 interface); int dm9000_initialize(bd_t *bis); -- cgit v1.2.3