From 25f5f0d49a3ae89bf4396f2557ce98debfef21da Mon Sep 17 00:00:00 2001 From: Anton Vorontsov Date: Tue, 8 Jul 2008 21:00:04 +0400 Subject: 83xx: mpc8315erdb: add support for switching between ULPI/UTMI USB PHYs Freescale ships MPC8315E-RDB boards either with TSEC1 and USB UTMI support, or without TSEC1 but with USB ULPI PHY support in addition. With this patch user can specify desired USB PHY. Also, it seems that we can't distinguish the two boards in software, so user have to set `mpc8315erdb' environment variable to either 'tsec1' (TSEC1 enabled) or `ulpi' (board with ULPI PHY, TSEC1 disabled), so that Linux will not probe for TSEC1. Signed-off-by: Anton Vorontsov Signed-off-by: Kim Phillips --- include/configs/MPC8315ERDB.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index 095f6658c1f..6b019f85adf 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -321,6 +321,8 @@ #define CONFIG_NET_MULTI 1 #endif +#define CONFIG_HAS_FSL_DR_USB + /* * TSEC */ -- cgit v1.3.1 From 162338e1fcde231ca4d562e5ebd7859456731691 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Fri, 22 Aug 2008 11:00:13 -0700 Subject: MPC8349EMDS: use 83XX_GENERIC_PCI setup code Change the MPC8349EMDS board to use the generic PCI initialization code for the mpc83xx cpu. Signed-off-by: Ira W. Snyder Signed-off-by: Kim Phillips --- board/freescale/mpc8349emds/pci.c | 377 ++++++-------------------------------- include/configs/MPC8349EMDS.h | 4 +- 2 files changed, 63 insertions(+), 318 deletions(-) (limited to 'include') diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index ecc67b66e52..a783bebad32 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -20,58 +20,62 @@ */ #include +#include #include -#include +#include #include -#include #include -#if defined(CONFIG_OF_LIBFDT) -#include -#include -#endif - +#include DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_PCI -/* System RAM mapped to PCI space */ -#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE -#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE - -#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc8349emds_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER - } +static struct pci_region pci1_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM }, - {} }; -#endif -static struct pci_controller pci_hose[] = { - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - }, - { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc8349emds_config_table, -#endif - } +#ifdef CONFIG_MPC83XX_PCI2 +static struct pci_region pci2_regions[] = { + { + bus_start: CFG_PCI2_MEM_BASE, + phys_start: CFG_PCI2_MEM_PHYS, + size: CFG_PCI2_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI2_IO_BASE, + phys_start: CFG_PCI2_IO_PHYS, + size: CFG_PCI2_IO_SIZE, + flags: PCI_REGION_IO + }, + { + bus_start: CFG_PCI2_MMIO_BASE, + phys_start: CFG_PCI2_MMIO_PHYS, + size: CFG_PCI2_MMIO_SIZE, + flags: PCI_REGION_MEM + }, }; +#endif -/************************************************************************** - * - * pib_init() -- initialize the PCA9555PW IO expander on the PIB board - * - */ -void -pib_init(void) +void pib_init(void) { u8 val8, orig_i2c_bus; /* @@ -128,299 +132,38 @@ pib_init(void) i2c_set_bus_num(orig_i2c_bus); } -/************************************************************************** - * pci_init_board() - * - * NOTICE: PCI2 is not currently supported - * - */ -void -pci_init_board(void) +void pci_init_board(void) { - volatile immap_t * immr; - volatile clk83xx_t * clk; - volatile law83xx_t * pci_law; - volatile pot83xx_t * pci_pot; - volatile pcictrl83xx_t * pci_ctrl; - volatile pciconf83xx_t * pci_conf; - u16 reg16; - u32 reg32; - u32 dev; - struct pci_controller * hose; - - immr = (immap_t *)CFG_IMMR; - clk = (clk83xx_t *)&immr->clk; - pci_law = immr->sysconf.pcilaw; - pci_pot = immr->ios.pot; - pci_ctrl = immr->pci_ctrl; - pci_conf = immr->pci_conf; - - hose = &pci_hose[0]; + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; +#ifndef CONFIG_MPC83XX_PCI2 + struct pci_region *reg[] = { pci1_regions }; +#else + struct pci_region *reg[] = { pci1_regions, pci2_regions }; +#endif + /* initialize the PCA9555PW IO expander on the PIB board */ pib_init(); - /* - * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode - */ - - reg32 = clk->occr; - udelay(2000); + /* Enable all 8 PCI_CLK_OUTPUTS */ clk->occr = 0xff000000; udelay(2000); - /* - * Release PCI RST Output signal - */ - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - -#ifdef CONFIG_MPC83XX_PCI2 - pci_ctrl[1].gcr = 0; - udelay(2000); - pci_ctrl[1].gcr = 1; -#endif - - /* We need to wait at least a 1sec based on PCI specs */ - { - int i; - - for (i = 0; i < 1000; ++i) - udelay (1000); - } - - /* - * Configure PCI Local Access Windows - */ + /* Configure PCI Local Access Windows */ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI1 mem space - prefetch */ - pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI1 IO space */ - pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI1 mmio - non-prefetch mem space */ - pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[0].pitar1 = 0x0; - pci_ctrl[0].pibar1 = 0x0; - pci_ctrl[0].piebar1 = 0x0; - pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI1_MEM_BASE, - CFG_PCI1_MEM_PHYS, - CFG_PCI1_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI1_MMIO_BASE, - CFG_PCI1_MMIO_PHYS, - CFG_PCI1_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI1_IO_BASE, - CFG_PCI1_IO_PHYS, - CFG_PCI1_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8300), - (CFG_IMMR+0x8304)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); - -#ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); -#endif - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); - -#ifdef CONFIG_MPC83XX_PCI2 - hose = &pci_hose[1]; - - /* - * Configure PCI Outbound Translation Windows - */ - - /* PCI2 mem space - prefetch */ - pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; - pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK); - - /* PCI2 IO space */ - pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK); - - /* PCI2 mmio - non-prefetch mem space */ - pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK; - pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK; - pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK); - - /* - * Configure PCI Inbound Translation Windows - */ - - /* we need RAM mapped to PCI space for the devices to - * access main memory */ - pci_ctrl[1].pitar1 = 0x0; - pci_ctrl[1].pibar1 = 0x0; - pci_ctrl[1].piebar1 = 0x0; - pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1); - - hose->first_busno = pci_hose[0].last_busno + 1; - hose->last_busno = 0xff; - - /* PCI memory prefetch space */ - pci_set_region(hose->regions + 0, - CFG_PCI2_MEM_BASE, - CFG_PCI2_MEM_PHYS, - CFG_PCI2_MEM_SIZE, - PCI_REGION_MEM|PCI_REGION_PREFETCH); - - /* PCI memory space */ - pci_set_region(hose->regions + 1, - CFG_PCI2_MMIO_BASE, - CFG_PCI2_MMIO_PHYS, - CFG_PCI2_MMIO_SIZE, - PCI_REGION_MEM); - - /* PCI IO space */ - pci_set_region(hose->regions + 2, - CFG_PCI2_IO_BASE, - CFG_PCI2_IO_PHYS, - CFG_PCI2_IO_SIZE, - PCI_REGION_IO); - - /* System memory space */ - pci_set_region(hose->regions + 3, - CONFIG_PCI_SYS_MEM_BUS, - CONFIG_PCI_SYS_MEM_PHYS, - gd->ram_size, - PCI_REGION_MEM | PCI_REGION_MEMORY); - - hose->region_count = 4; - - pci_setup_indirect(hose, - (CFG_IMMR+0x8380), - (CFG_IMMR+0x8384)); - - pci_register_hose(hose); - - /* - * Write to Command register - */ - reg16 = 0xff; - dev = PCI_BDF(hose->first_busno, 0, 0); - pci_hose_read_config_word (hose, dev, PCI_COMMAND, ®16); - reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16); - - /* - * Clear non-reserved bits in status register. - */ - pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff); - pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); - pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); + udelay(2000); - /* - * Hose scan. - */ - hose->last_busno = pci_hose_scan(hose); +#ifndef CONFIG_MPC83XX_PCI2 + mpc83xx_pci_init(1, reg, 0); +#else + mpc83xx_pci_init(2, reg, 0); #endif - } -#if defined(CONFIG_OF_LIBFDT) -void ft_pci_setup(void *blob, bd_t *bd) -{ - int nodeoffset; - int tmp[2]; - const char *path; - - nodeoffset = fdt_path_offset(blob, "/aliases"); - if (nodeoffset >= 0) { - path = fdt_getprop(blob, nodeoffset, "pci0", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#ifdef CONFIG_MPC83XX_PCI2 - path = fdt_getprop(blob, nodeoffset, "pci1", NULL); - if (path) { - tmp[0] = cpu_to_be32(pci_hose[0].first_busno); - tmp[1] = cpu_to_be32(pci_hose[0].last_busno); - do_fixup_by_path(blob, path, "bus-range", - &tmp, sizeof(tmp), 1); - - tmp[0] = cpu_to_be32(gd->pci_clk); - do_fixup_by_path(blob, path, "clock-frequency", - &tmp, sizeof(tmp[0]), 1); - } -#endif - } -} -#endif /* CONFIG_OF_LIBFDT */ #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index a53f5cd2612..d659a15b6d3 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -406,6 +406,8 @@ #define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_83XX_GENERIC_PCI +#define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -417,7 +419,7 @@ #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ +#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ -- cgit v1.3.1 From 447ad5768abda669ac0e7f46fcdb62fbe828d637 Mon Sep 17 00:00:00 2001 From: "Ira W. Snyder" Date: Fri, 22 Aug 2008 11:00:15 -0700 Subject: MPC8349EMDS: Add PCI Agent (PCISLAVE) support Add the ability for the MPC8349EMDS to run in PCI Agent mode, acting as a PCI card rather than a host computer. Signed-off-by: Ira W. Snyder Signed-off-by: Kim Phillips --- board/freescale/mpc8349emds/mpc8349emds.c | 9 ++++++ board/freescale/mpc8349emds/pci.c | 49 +++++++++++++++++++++++++++++++ include/configs/MPC8349EMDS.h | 22 +++++++++++++- 3 files changed, 79 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 9a312c37b67..4c04f2c4dda 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -165,6 +165,15 @@ int fixed_sdram(void) int checkboard (void) { + /* + * Warning: do not read the BCSR registers here + * + * There is a timing bug in the 8349E and 8349EA BCSR code + * version 1.2 (read from BCSR 11) that will cause the CFI + * flash initialization code to overwrite BCSR 0, disabling + * the serial ports and gigabit ethernet + */ + puts("Board: Freescale MPC8349EMDS\n"); return 0; } diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index a783bebad32..9c19e303f96 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -75,6 +75,7 @@ static struct pci_region pci2_regions[] = { }; #endif +#ifndef CONFIG_PCISLAVE void pib_init(void) { u8 val8, orig_i2c_bus; @@ -166,4 +167,52 @@ void pci_init_board(void) #endif } +#else +void pci_init_board(void) +{ + volatile immap_t *immr = (volatile immap_t *)CFG_IMMR; + volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; + volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0]; + struct pci_region *reg[] = { pci1_regions }; + + /* Enable all 8 PCI_CLK_OUTPUTS */ + clk->occr = 0xff000000; + udelay(2000); + + /* Configure PCI Local Access Windows */ + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; + + udelay(2000); + + mpc83xx_pci_init(1, reg, 0); + + /* Configure PCI Inbound Translation Windows (3 1MB windows) */ + pci_ctrl->pitar0 = 0x0; + pci_ctrl->pibar0 = 0x0; + pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + pci_ctrl->pitar1 = 0x0; + pci_ctrl->pibar1 = 0x0; + pci_ctrl->piebar1 = 0x0; + pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + pci_ctrl->pitar2 = 0x0; + pci_ctrl->pibar2 = 0x0; + pci_ctrl->piebar2 = 0x0; + pci_ctrl->piwar2 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | + PIWAR_WTT_SNOOP | PIWAR_IWS_1M; + + /* Unlock the configuration bit */ + mpc83xx_pcislave_unlock(0); + printf("PCI: Agent mode enabled\n"); +} +#endif /* CONFIG_PCISLAVE */ + #endif /* CONFIG_PCI */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index d659a15b6d3..c8870b54ae1 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -48,6 +48,11 @@ #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ #endif +#ifdef CONFIG_PCISLAVE +#define CONFIG_PCI +#define CONFIG_83XX_PCICLK 66666666 /* in Hz */ +#endif /* CONFIG_PCISLAVE */ + #ifndef CONFIG_SYS_CLK_FREQ #ifdef PCI_66M #define CONFIG_SYS_CLK_FREQ 66000000 @@ -575,6 +580,20 @@ HRCWL_CORE_TO_CSB_1X1) #endif +#ifdef CONFIG_PCISLAVE +#define CFG_HRCW_HIGH (\ + HRCWH_PCI_AGENT |\ + HRCWH_64_BIT_PCI |\ + HRCWH_PCI1_ARBITER_DISABLE |\ + HRCWH_PCI2_ARBITER_DISABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_TSEC1M_IN_GMII |\ + HRCWH_TSEC2M_IN_GMII ) +#else #if defined(PCI_64BIT) #define CFG_HRCW_HIGH (\ HRCWH_PCI_HOST |\ @@ -601,7 +620,8 @@ HRCWH_ROM_LOC_LOCAL_16BIT |\ HRCWH_TSEC1M_IN_GMII |\ HRCWH_TSEC2M_IN_GMII ) -#endif +#endif /* PCI_64BIT */ +#endif /* CONFIG_PCISLAVE */ /* * System performance -- cgit v1.3.1 From 002d27caf26e7eb913d474d3a91f67d56c8c31d5 Mon Sep 17 00:00:00 2001 From: Nick Spence Date: Fri, 22 Aug 2008 23:52:40 -0700 Subject: MPC83XX: Add miscellaneous registers and #defines to support MPC83xx family devices This patch adds elements to the 83xx sysconf structure and #define values that are used by mpc83xx family devices. Signed-off-by: Nick Spence Signed-off-by: Kim Phillips --- include/asm-ppc/immap_83xx.h | 4 +++- include/mpc83xx.h | 7 +++++++ 2 files changed, 10 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/include/asm-ppc/immap_83xx.h b/include/asm-ppc/immap_83xx.h index 5b215393eef..ff183033c9e 100644 --- a/include/asm-ppc/immap_83xx.h +++ b/include/asm-ppc/immap_83xx.h @@ -61,7 +61,9 @@ typedef struct sysconf83xx { u32 spcr; /* System Priority Configuration Register */ u32 sicrl; /* System I/O Configuration Register Low */ u32 sicrh; /* System I/O Configuration Register High */ - u8 res6[0x0C]; + u8 res6[0x04]; + u32 sidcr0; /* System I/O Delay Configuration Register 0 */ + u32 sidcr1; /* System I/O Delay Configuration Register 1 */ u32 ddrcdr; /* DDR Control Driver Register */ u32 ddrdsr; /* DDR Debug Status Register */ u32 obir; /* Output Buffer Impedance Register */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 70a4de70dfa..5d82bb46f9a 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -350,7 +350,9 @@ /* ATR - Arbiter Timers Register */ #define ATR_DTO 0x00FF0000 /* Data time out */ +#define ATR_DTO_SHIFT 16 #define ATR_ATO 0x000000FF /* Address time out */ +#define ATR_ATO_SHIFT 0 /* AER - Arbiter Event Register */ @@ -364,10 +366,15 @@ /* AEATR - Arbiter Event Address Register */ #define AEATR_EVENT 0x07000000 /* Event type */ +#define AEATR_EVENT_SHIFT 24 #define AEATR_MSTR_ID 0x001F0000 /* Master Id */ +#define AEATR_MSTR_ID_SHIFT 16 #define AEATR_TBST 0x00000800 /* Transfer burst */ +#define AEATR_TBST_SHIFT 11 #define AEATR_TSIZE 0x00000700 /* Transfer Size */ +#define AEATR_TSIZE_SHIFT 8 #define AEATR_TTYPE 0x0000001F /* Transfer Type */ +#define AEATR_TTYPE_SHIFT 0 /* HRCWL - Hard Reset Configuration Word Low */ -- cgit v1.3.1 From 1a9eeb78b825bfade31d7606a2fe3b9eca9e35be Mon Sep 17 00:00:00 2001 From: Andre Schwarz Date: Wed, 20 Aug 2008 11:11:52 +0200 Subject: change mvBL-M7 default env and move to vendor subdir fix mvBL-M7 config and move to matrix_vision subdir Signed-off-by: Andre Schwarz Signed-off-by: Kim Phillips --- Makefile | 2 +- board/matrix_vision/mvblm7/Makefile | 48 +++++++ board/matrix_vision/mvblm7/config.mk | 25 ++++ board/matrix_vision/mvblm7/fpga.c | 188 +++++++++++++++++++++++++++ board/matrix_vision/mvblm7/fpga.h | 34 +++++ board/matrix_vision/mvblm7/mvblm7.c | 157 ++++++++++++++++++++++ board/matrix_vision/mvblm7/mvblm7.h | 21 +++ board/matrix_vision/mvblm7/mvblm7_autoscript | 43 ++++++ board/matrix_vision/mvblm7/pci.c | 133 +++++++++++++++++++ board/mvblm7/Makefile | 48 ------- board/mvblm7/config.mk | 25 ---- board/mvblm7/fpga.c | 188 --------------------------- board/mvblm7/fpga.h | 34 ----- board/mvblm7/mvblm7.c | 157 ---------------------- board/mvblm7/mvblm7.h | 21 --- board/mvblm7/mvblm7_autoscript | 37 ------ board/mvblm7/pci.c | 133 ------------------- include/configs/MVBLM7.h | 56 ++++---- 18 files changed, 679 insertions(+), 671 deletions(-) create mode 100644 board/matrix_vision/mvblm7/Makefile create mode 100644 board/matrix_vision/mvblm7/config.mk create mode 100644 board/matrix_vision/mvblm7/fpga.c create mode 100644 board/matrix_vision/mvblm7/fpga.h create mode 100644 board/matrix_vision/mvblm7/mvblm7.c create mode 100644 board/matrix_vision/mvblm7/mvblm7.h create mode 100644 board/matrix_vision/mvblm7/mvblm7_autoscript create mode 100644 board/matrix_vision/mvblm7/pci.c delete mode 100644 board/mvblm7/Makefile delete mode 100644 board/mvblm7/config.mk delete mode 100644 board/mvblm7/fpga.c delete mode 100644 board/mvblm7/fpga.h delete mode 100644 board/mvblm7/mvblm7.c delete mode 100644 board/mvblm7/mvblm7.h delete mode 100644 board/mvblm7/mvblm7_autoscript delete mode 100644 board/mvblm7/pci.c (limited to 'include') diff --git a/Makefile b/Makefile index c30ef57583e..66d91046a35 100644 --- a/Makefile +++ b/Makefile @@ -2180,7 +2180,7 @@ MPC837XERDB_config: unconfig @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale MVBLM7_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 + @$(MKCONFIG) $(@:_config=) ppc mpc83xx mvblm7 matrix_vision sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 diff --git a/board/matrix_vision/mvblm7/Makefile b/board/matrix_vision/mvblm7/Makefile new file mode 100644 index 00000000000..cfbecfbe8f9 --- /dev/null +++ b/board/matrix_vision/mvblm7/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o pci.o fpga.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/mvblm7/config.mk b/board/matrix_vision/mvblm7/config.mk new file mode 100644 index 00000000000..1d85f4fd0e6 --- /dev/null +++ b/board/matrix_vision/mvblm7/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +TEXT_BASE = 0xFFF00000 diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c new file mode 100644 index 00000000000..a60af019a72 --- /dev/null +++ b/board/matrix_vision/mvblm7/fpga.c @@ -0,0 +1,188 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include +#include +#include +#include "fpga.h" +#include "mvblm7.h" + +#ifdef FPGA_DEBUG +#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) +#else +#define fpga_debug(fmt, args...) +#endif + +Altera_CYC2_Passive_Serial_fns altera_fns = { + fpga_null_fn, + fpga_config_fn, + fpga_status_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_null_fn, + fpga_null_fn, + 0 +}; + +Altera_desc cyclone2 = { + Altera_CYC2, + passive_serial, + Altera_EP2C20_SIZE, + (void *) &altera_fns, + NULL, + 0 +}; + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_init_fpga(void) +{ + fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", + gd->reloc_off); + fpga_init(gd->reloc_off); + fpga_add(fpga_altera, &cyclone2); + fpga_config_fn(0, 1, 0); + udelay(60); + + return 1; +} + +int fpga_null_fn(int cookie) +{ + return 0; +} + +int fpga_config_fn(int assert, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("SET config : %s\n", assert ? "low" : "high"); + if (assert) + dvo |= FPGA_CONFIG; + else + dvo &= ~FPGA_CONFIG; + + if (flush) + gpio->dat = dvo; + + return assert; +} + +int fpga_done_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + udelay(10); + fpga_debug("CONF_DONE check ... "); + if (gpio->dat & FPGA_CONF_DONE) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_status_fn(int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int result = 0; + + fpga_debug("STATUS check ... "); + if (gpio->dat & FPGA_STATUS) { + fpga_debug("high\n"); + result = 1; + } else + fpga_debug("low\n"); + + return result; +} + +int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + u32 dvo = gpio->dat; + + fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); + if (assert_clk) + dvo |= FPGA_CCLK; + else + dvo &= ~FPGA_CCLK; + + if (flush) + gpio->dat = dvo; + + return assert_clk; +} + +static inline int _write_fpga(u8 val, int dump) +{ + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; + int i; + u32 dvo = gpio->dat; + + if (dump) + fpga_debug(" %02x -> ", val); + for (i = 0; i < 8; i++) { + dvo &= ~FPGA_CCLK; + gpio->dat = dvo; + dvo &= ~FPGA_DIN; + if (dump) + fpga_debug("%d ", val&1); + if (val & 1) + dvo |= FPGA_DIN; + gpio->dat = dvo; + dvo |= FPGA_CCLK; + gpio->dat = dvo; + val >>= 1; + } + if (dump) + fpga_debug("\n"); + + return 0; +} + +int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) +{ + unsigned char *data = (unsigned char *) buf; + int i; + + fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); + for (i = 0; i < len; i++) + _write_fpga(data[i], 0); + fpga_debug("\n"); + + return FPGA_SUCCESS; +} diff --git a/board/matrix_vision/mvblm7/fpga.h b/board/matrix_vision/mvblm7/fpga.h new file mode 100644 index 00000000000..19277eb05f5 --- /dev/null +++ b/board/matrix_vision/mvblm7/fpga.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2002 + * Rich Ireland, Enterasys Networks, rireland@enterasys.com. + * Keith Outwater, keith_outwater@mvis.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +extern int mvblm7_init_fpga(void); + +extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); +extern int fpga_status_fn(int cookie); +extern int fpga_config_fn(int assert, int flush, int cookie); +extern int fpga_done_fn(int cookie); +extern int fpga_clk_fn(int assert_clk, int flush, int cookie); +extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); +extern int fpga_null_fn(int cookie); diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c new file mode 100644 index 00000000000..b07f91393c2 --- /dev/null +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -0,0 +1,157 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF_LIBFDT) +#include +#endif + +#include "mvblm7.h" + +int fixed_sdram(void) +{ + volatile immap_t *im = (immap_t *)CFG_IMMR; + u32 msize = 0; + u32 ddr_size; + u32 ddr_size_log2; + + msize = CFG_DDR_SIZE; + for (ddr_size = msize << 20, ddr_size_log2 = 0; + (ddr_size > 1); + ddr_size = ddr_size >> 1, ddr_size_log2++) { + if (ddr_size & 1) + return -1; + } + im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); + im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & + LAWAR_SIZE); + + im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; + im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; + im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; + im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; + im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; + im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; + im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; + im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; + im->ddr.sdram_mode = CFG_DDR_MODE; + im->ddr.sdram_interval = CFG_DDR_INTERVAL; + im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; + + udelay(300); + + im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; + + return CFG_DDR_SIZE; +} + +phys_size_t initdram(int board_type) +{ + volatile immap_t *im = (immap_t *) CFG_IMMR; + u32 msize = 0; + + if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) + return -1; + + im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; + msize = fixed_sdram(); + + /* return total bus RAM size(bytes) */ + return msize * 1024 * 1024; +} + +int checkboard(void) +{ + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + ptr = getenv("dhcp_vendor-class-identifier"); + if (ptr) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + ptr = getenv("dhcp_client_id"); + if (ptr) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} + +#ifdef CONFIG_HARD_SPI +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat &= ~MVBLM7_MMC_CS; +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + iopd->dat |= ~MVBLM7_MMC_CS; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +#ifdef CONFIG_PCI + ft_pci_setup(blob, bd); +#endif +} + +#endif diff --git a/board/matrix_vision/mvblm7/mvblm7.h b/board/matrix_vision/mvblm7/mvblm7.h new file mode 100644 index 00000000000..03e9f4170a5 --- /dev/null +++ b/board/matrix_vision/mvblm7/mvblm7.h @@ -0,0 +1,21 @@ +#ifndef __MVBC_H__ +#define __MVBC_H__ + +#define MV_GPIO + +#define FPGA_CONFIG 0x80000000 +#define FPGA_CCLK 0x40000000 +#define FPGA_DIN 0x20000000 +#define FPGA_STATUS 0x10000000 +#define FPGA_CONF_DONE 0x08000000 +#define MMC_CS 0x04000000 + +#define WD_WDI 0x00400000 +#define WD_TS 0x00200000 +#define MAN_RST 0x00100000 + +#define MV_GPIO_DAT (WD_TS) +#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) +#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) + +#endif diff --git a/board/matrix_vision/mvblm7/mvblm7_autoscript b/board/matrix_vision/mvblm7/mvblm7_autoscript new file mode 100644 index 00000000000..6f9357fd0db --- /dev/null +++ b/board/matrix_vision/mvblm7/mvblm7_autoscript @@ -0,0 +1,43 @@ +echo +echo "==== running autoscript ====" +echo +setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} +setenv ramkernel setenv kernel_boot \${loadaddr} +setenv flashkernel setenv kernel_boot \${mv_kernel_addr} +setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} +setenv bootfromflash run flashkernel cpird ramparam addcons bootdtb +setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} +setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 +setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup +setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel +if test ${console} = yes; +then +setenv addcons setenv bootargs \${bootargs} console=ttyS\${console_nr},\${baudrate}N8 +else +setenv addcons setenv bootargs \${bootargs} console=tty0 +fi +setenv set_static_ip setenv ipaddr \${static_ipaddr} +setenv set_static_nm setenv netmask \${static_netmask} +setenv set_static_gw setenv gatewayip \${static_gateway} +setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} +setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs +if test ${autoscr_boot} != no; +then + if test ${netboot} = yes; + then + bootp + if test $? = 0; + then + echo "=== bootp succeeded -> netboot ===" + run set_ip + run getdtb rundtb bootfromnet ramparam addcons bootdtb + else + echo "=== netboot failed ===" + fi + fi + run set_static_ip set_static_nm set_static_gw set_ip + echo "=== bootfromflash ===" + run cpdtb rundtb bootfromflash +else + echo "=== boot stopped with autoscr_boot no ===" +fi diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c new file mode 100644 index 00000000000..ef34a6b453e --- /dev/null +++ b/board/matrix_vision/mvblm7/pci.c @@ -0,0 +1,133 @@ +/* + * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. + * + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#if defined(CONFIG_OF_LIBFDT) +#include +#endif +#include +#include +#include +#include "mvblm7.h" +#include "fpga.h" + +DECLARE_GLOBAL_DATA_PTR; + +int mvblm7_load_fpga(void) +{ + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + + return fpga_load(0, fpga_data, data_size); +} + +static struct pci_region pci_regions[] = { + { + bus_start: CFG_PCI1_MEM_BASE, + phys_start: CFG_PCI1_MEM_PHYS, + size: CFG_PCI1_MEM_SIZE, + flags: PCI_REGION_MEM | PCI_REGION_PREFETCH + }, + { + bus_start: CFG_PCI1_MMIO_BASE, + phys_start: CFG_PCI1_MMIO_PHYS, + size: CFG_PCI1_MMIO_SIZE, + flags: PCI_REGION_MEM + }, + { + bus_start: CFG_PCI1_IO_BASE, + phys_start: CFG_PCI1_IO_PHYS, + size: CFG_PCI1_IO_SIZE, + flags: PCI_REGION_IO + } +}; + +void pci_init_board(void) +{ + char *s; + int i; + int warmboot; + int load_fpga; + volatile immap_t *immr; + volatile pcictrl83xx_t *pci_ctrl; + volatile gpio83xx_t *gpio; + volatile clk83xx_t *clk; + volatile law83xx_t *pci_law; + struct pci_region *reg[] = { pci_regions }; + + load_fpga = 1; + immr = (immap_t *) CFG_IMMR; + clk = (clk83xx_t *) &immr->clk; + pci_ctrl = immr->pci_ctrl; + pci_law = immr->sysconf.pcilaw; + gpio = (volatile gpio83xx_t *)&immr->gpio[0]; + + s = getenv("skip_fpga"); + if (s) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + load_fpga = 0; + } + + gpio->dat = MV_GPIO_DAT; + gpio->odr = MV_GPIO_ODE; + if (load_fpga) + gpio->dir = MV_GPIO_OUT; + else + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + + printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, + immr->sysconf.sicrl); + + mvblm7_init_fpga(); + if (load_fpga) + mvblm7_load_fpga(); + + /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ + clk->occr = 0xc0000000; + + pci_ctrl[0].gcr = 0; + udelay(2000); + pci_ctrl[0].gcr = 1; + + for (i = 0; i < 1000; ++i) + udelay(1000); + + pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; + pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; + + pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; + pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; + + warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; + + mpc83xx_pci_init(1, reg, warmboot); +} diff --git a/board/mvblm7/Makefile b/board/mvblm7/Makefile deleted file mode 100644 index cfbecfbe8f9..00000000000 --- a/board/mvblm7/Makefile +++ /dev/null @@ -1,48 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS := $(BOARD).o pci.o fpga.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -clean: - rm -f $(SOBJS) $(OBJS) - -distclean: clean - rm -f $(LIB) core *.bak $(obj).depend - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/mvblm7/config.mk b/board/mvblm7/config.mk deleted file mode 100644 index 1d85f4fd0e6..00000000000 --- a/board/mvblm7/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp - -TEXT_BASE = 0xFFF00000 diff --git a/board/mvblm7/fpga.c b/board/mvblm7/fpga.c deleted file mode 100644 index a60af019a72..00000000000 --- a/board/mvblm7/fpga.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#include -#include -#include -#include "fpga.h" -#include "mvblm7.h" - -#ifdef FPGA_DEBUG -#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args) -#else -#define fpga_debug(fmt, args...) -#endif - -Altera_CYC2_Passive_Serial_fns altera_fns = { - fpga_null_fn, - fpga_config_fn, - fpga_status_fn, - fpga_done_fn, - fpga_wr_fn, - fpga_null_fn, - fpga_null_fn, - 0 -}; - -Altera_desc cyclone2 = { - Altera_CYC2, - passive_serial, - Altera_EP2C20_SIZE, - (void *) &altera_fns, - NULL, - 0 -}; - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_init_fpga(void) -{ - fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", - gd->reloc_off); - fpga_init(gd->reloc_off); - fpga_add(fpga_altera, &cyclone2); - fpga_config_fn(0, 1, 0); - udelay(60); - - return 1; -} - -int fpga_null_fn(int cookie) -{ - return 0; -} - -int fpga_config_fn(int assert, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("SET config : %s\n", assert ? "low" : "high"); - if (assert) - dvo |= FPGA_CONFIG; - else - dvo &= ~FPGA_CONFIG; - - if (flush) - gpio->dat = dvo; - - return assert; -} - -int fpga_done_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - udelay(10); - fpga_debug("CONF_DONE check ... "); - if (gpio->dat & FPGA_CONF_DONE) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_status_fn(int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int result = 0; - - fpga_debug("STATUS check ... "); - if (gpio->dat & FPGA_STATUS) { - fpga_debug("high\n"); - result = 1; - } else - fpga_debug("low\n"); - - return result; -} - -int fpga_clk_fn(int assert_clk, int flush, int cookie) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - u32 dvo = gpio->dat; - - fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low"); - if (assert_clk) - dvo |= FPGA_CCLK; - else - dvo &= ~FPGA_CCLK; - - if (flush) - gpio->dat = dvo; - - return assert_clk; -} - -static inline int _write_fpga(u8 val, int dump) -{ - volatile immap_t *im = (volatile immap_t *)CFG_IMMR; - volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0]; - int i; - u32 dvo = gpio->dat; - - if (dump) - fpga_debug(" %02x -> ", val); - for (i = 0; i < 8; i++) { - dvo &= ~FPGA_CCLK; - gpio->dat = dvo; - dvo &= ~FPGA_DIN; - if (dump) - fpga_debug("%d ", val&1); - if (val & 1) - dvo |= FPGA_DIN; - gpio->dat = dvo; - dvo |= FPGA_CCLK; - gpio->dat = dvo; - val >>= 1; - } - if (dump) - fpga_debug("\n"); - - return 0; -} - -int fpga_wr_fn(void *buf, size_t len, int flush, int cookie) -{ - unsigned char *data = (unsigned char *) buf; - int i; - - fpga_debug("fpga_wr: buf %p / size %d\n", buf, len); - for (i = 0; i < len; i++) - _write_fpga(data[i], 0); - fpga_debug("\n"); - - return FPGA_SUCCESS; -} diff --git a/board/mvblm7/fpga.h b/board/mvblm7/fpga.h deleted file mode 100644 index 19277eb05f5..00000000000 --- a/board/mvblm7/fpga.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (C) Copyright 2002 - * Rich Ireland, Enterasys Networks, rireland@enterasys.com. - * Keith Outwater, keith_outwater@mvis.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -extern int mvblm7_init_fpga(void); - -extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie); -extern int fpga_status_fn(int cookie); -extern int fpga_config_fn(int assert, int flush, int cookie); -extern int fpga_done_fn(int cookie); -extern int fpga_clk_fn(int assert_clk, int flush, int cookie); -extern int fpga_wr_fn(void *buf, size_t len, int flush, int cookie); -extern int fpga_null_fn(int cookie); diff --git a/board/mvblm7/mvblm7.c b/board/mvblm7/mvblm7.c deleted file mode 100644 index b07f91393c2..00000000000 --- a/board/mvblm7/mvblm7.c +++ /dev/null @@ -1,157 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#include -#include -#include -#include -#include -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif - -#include "mvblm7.h" - -int fixed_sdram(void) -{ - volatile immap_t *im = (immap_t *)CFG_IMMR; - u32 msize = 0; - u32 ddr_size; - u32 ddr_size_log2; - - msize = CFG_DDR_SIZE; - for (ddr_size = msize << 20, ddr_size_log2 = 0; - (ddr_size > 1); - ddr_size = ddr_size >> 1, ddr_size_log2++) { - if (ddr_size & 1) - return -1; - } - im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff); - im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & - LAWAR_SIZE); - - im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS; - im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG; - im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0; - im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1; - im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2; - im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3; - im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG; - im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2; - im->ddr.sdram_mode = CFG_DDR_MODE; - im->ddr.sdram_interval = CFG_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL; - - udelay(300); - - im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN; - - return CFG_DDR_SIZE; -} - -phys_size_t initdram(int board_type) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - u32 msize = 0; - - if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im) - return -1; - - im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR; - msize = fixed_sdram(); - - /* return total bus RAM size(bytes) */ - return msize * 1024 * 1024; -} - -int checkboard(void) -{ - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} - -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - ptr = getenv("dhcp_vendor-class-identifier"); - if (ptr) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - ptr = getenv("dhcp_client_id"); - if (ptr) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - -u8 *dhcp_vendorex_proc(u8 *popt) -{ - return NULL; -} - -#ifdef CONFIG_HARD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) -{ - return bus == 0 && cs == 0; -} - -void spi_cs_activate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; - - iopd->dat &= ~MVBLM7_MMC_CS; -} - -void spi_cs_deactivate(struct spi_slave *slave) -{ - volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; - - iopd->dat |= ~MVBLM7_MMC_CS; -} -#endif - -#if defined(CONFIG_OF_BOARD_SETUP) -void ft_board_setup(void *blob, bd_t *bd) -{ - ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI - ft_pci_setup(blob, bd); -#endif -} - -#endif diff --git a/board/mvblm7/mvblm7.h b/board/mvblm7/mvblm7.h deleted file mode 100644 index 03e9f4170a5..00000000000 --- a/board/mvblm7/mvblm7.h +++ /dev/null @@ -1,21 +0,0 @@ -#ifndef __MVBC_H__ -#define __MVBC_H__ - -#define MV_GPIO - -#define FPGA_CONFIG 0x80000000 -#define FPGA_CCLK 0x40000000 -#define FPGA_DIN 0x20000000 -#define FPGA_STATUS 0x10000000 -#define FPGA_CONF_DONE 0x08000000 -#define MMC_CS 0x04000000 - -#define WD_WDI 0x00400000 -#define WD_TS 0x00200000 -#define MAN_RST 0x00100000 - -#define MV_GPIO_DAT (WD_TS) -#define MV_GPIO_OUT (FPGA_CONFIG|FPGA_DIN|FPGA_CCLK|WD_TS|WD_WDI|MMC_CS) -#define MV_GPIO_ODE (FPGA_CONFIG|MAN_RST) - -#endif diff --git a/board/mvblm7/mvblm7_autoscript b/board/mvblm7/mvblm7_autoscript deleted file mode 100644 index ec6e34ef05a..00000000000 --- a/board/mvblm7/mvblm7_autoscript +++ /dev/null @@ -1,37 +0,0 @@ -echo -echo "==== running autoscript ====" -echo -setenv bootdtb bootm \${kernel_boot} \${mv_initrd_addr_ram} \${mv_dtb_addr_ram} -setenv ramkernel setenv kernel_boot \${loadaddr} -setenv flashkernel setenv kernel_boot \${mv_kernel_addr} -setenv cpird cp \${mv_initrd_addr} \${mv_initrd_addr_ram} \${mv_initrd_length} -setenv bootfromflash run flashkernel cpird ramparam bootdtb -setenv getdtb tftp \${mv_dtb_addr_ram} \${dtb_name} -setenv cpdtb cp \${mv_dtb_addr} \${mv_dtb_addr_ram} 0x2000 -setenv rundtb fdt addr \${mv_dtb_addr_ram}\;fdt boardsetup -setenv bootfromnet tftp \${mv_initrd_addr_ram} \${initrd_name}\;run ramkernel -setenv set_static_ip setenv ipaddr \${static_ipaddr} -setenv set_static_nm setenv netmask \${static_netmask} -setenv set_static_gw setenv gatewayip \${static_gateway} -setenv set_ip setenv ip \${ipaddr}::\${gatewayip}:\${netmask} -setenv ramparam setenv bootargs root=/dev/ram0 ro rootfstype=squashfs -if test ${autoscr_boot} != no; -then - if test ${netboot} = yes; - then - bootp - if test $? = 0; - then - echo "=== bootp succeeded -> netboot ===" - run set_ip - run getdtb rundtb bootfromnet ramparam bootdtb - else - echo "=== netboot failed ===" - fi - fi - run set_static_ip set_static_nm set_static_gw set_ip - echo "=== bootfromflash ===" - run cpdtb rundtb bootfromflash -else - echo "=== boot stopped with autoscr_boot no ===" -fi diff --git a/board/mvblm7/pci.c b/board/mvblm7/pci.c deleted file mode 100644 index ef34a6b453e..00000000000 --- a/board/mvblm7/pci.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved. - * - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include -#if defined(CONFIG_OF_LIBFDT) -#include -#endif -#include -#include -#include -#include "mvblm7.h" -#include "fpga.h" - -DECLARE_GLOBAL_DATA_PTR; - -int mvblm7_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - -static struct pci_region pci_regions[] = { - { - bus_start: CFG_PCI1_MEM_BASE, - phys_start: CFG_PCI1_MEM_PHYS, - size: CFG_PCI1_MEM_SIZE, - flags: PCI_REGION_MEM | PCI_REGION_PREFETCH - }, - { - bus_start: CFG_PCI1_MMIO_BASE, - phys_start: CFG_PCI1_MMIO_PHYS, - size: CFG_PCI1_MMIO_SIZE, - flags: PCI_REGION_MEM - }, - { - bus_start: CFG_PCI1_IO_BASE, - phys_start: CFG_PCI1_IO_PHYS, - size: CFG_PCI1_IO_SIZE, - flags: PCI_REGION_IO - } -}; - -void pci_init_board(void) -{ - char *s; - int i; - int warmboot; - int load_fpga; - volatile immap_t *immr; - volatile pcictrl83xx_t *pci_ctrl; - volatile gpio83xx_t *gpio; - volatile clk83xx_t *clk; - volatile law83xx_t *pci_law; - struct pci_region *reg[] = { pci_regions }; - - load_fpga = 1; - immr = (immap_t *) CFG_IMMR; - clk = (clk83xx_t *) &immr->clk; - pci_ctrl = immr->pci_ctrl; - pci_law = immr->sysconf.pcilaw; - gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - - gpio->dat = MV_GPIO_DAT; - gpio->odr = MV_GPIO_ODE; - if (load_fpga) - gpio->dir = MV_GPIO_OUT; - else - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); - - printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, - immr->sysconf.sicrl); - - mvblm7_init_fpga(); - if (load_fpga) - mvblm7_load_fpga(); - - /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ - clk->occr = 0xc0000000; - - pci_ctrl[0].gcr = 0; - udelay(2000); - pci_ctrl[0].gcr = 1; - - for (i = 0; i < 1000; ++i) - udelay(1000); - - pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; - pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB; - - pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; - pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - - mpc83xx_pci_init(1, reg, warmboot); -} diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 0dce9b46d62..849350fd8a4 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -406,22 +406,22 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1000 -#define MV_CI "mvBL-M7" -#define MV_VCI "mvBL-M7" -#define MV_FPGA_DATA "0xfff80000" -#define MV_FPGA_SIZE "0x76ca2" -#define MV_KERNEL_ADDR "0xff810000" -#define MV_INITRD_ADDR "0xffc00000" -#define MV_AUTOSCR_ADDR "0xff804000" -#define MV_AUTOSCR_ADDR2 "0xff806000" -#define MV_DTB_ADDR "0xff808000" -#define MV_INITRD_LENGTH "0x00300000" +#define MV_CI mvBL-M7 +#define MV_VCI mvBL-M7 +#define MV_FPGA_DATA 0xfff80000 +#define MV_FPGA_SIZE 0x00076ca2 +#define MV_KERNEL_ADDR 0xff810000 +#define MV_INITRD_ADDR 0xffb00000 +#define MV_AUTOSCR_ADDR 0xff804000 +#define MV_AUTOSCR_ADDR2 0xff806000 +#define MV_DTB_ADDR 0xff808000 +#define MV_INITRD_LENGTH 0x00400000 #define CONFIG_SHOW_BOOT_PROGRESS 1 -#define MV_KERNEL_ADDR_RAM "0x00100000" -#define MV_DTB_ADDR_RAM "0x00600000" -#define MV_INITRD_ADDR_RAM "0x01000000" +#define MV_KERNEL_ADDR_RAM 0x00100000 +#define MV_DTB_ADDR_RAM 0x00600000 +#define MV_INITRD_ADDR_RAM 0x01000000 #define CONFIG_BOOTCOMMAND "if imi ${autoscr_addr}; \ then autoscr ${autoscr_addr}; \ @@ -431,25 +431,26 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "console_nr=0\0" \ + "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \ "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" \ "fpga=0\0" \ - "fpgadata=" MV_FPGA_DATA "\0" \ - "fpgadatasize=" MV_FPGA_SIZE "\0" \ - "autoscr_addr=" MV_AUTOSCR_ADDR "\0" \ - "autoscr_addr2=" MV_AUTOSCR_ADDR2 "\0" \ - "mv_kernel_addr=" MV_KERNEL_ADDR "\0" \ - "mv_kernel_addr_ram=" MV_KERNEL_ADDR_RAM "\0" \ - "mv_initrd_addr=" MV_INITRD_ADDR "\0" \ - "mv_initrd_addr_ram=" MV_INITRD_ADDR_RAM "\0" \ - "mv_initrd_length=" MV_INITRD_LENGTH "\0" \ - "mv_dtb_addr=" MV_DTB_ADDR "\0" \ - "mv_dtb_addr_ram=" MV_DTB_ADDR_RAM "\0" \ - "dtb_name=" MV_DTB_NAME "\0" \ + "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ + "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ + "autoscr_addr=" MK_STR(MV_AUTOSCR_ADDR) "\0" \ + "autoscr_addr2=" MK_STR(MV_AUTOSCR_ADDR2) "\0" \ + "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ + "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ + "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ + "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \ + "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \ + "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \ + "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \ + "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \ "mv_version=" U_BOOT_VERSION "\0" \ - "dhcp_client_id=" MV_CI "\0" \ - "dhcp_vendor-class-identifier=" MV_VCI "\0" \ + "dhcp_client_id=" MK_STR(MV_CI) "\0" \ + "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ "netretry=no\0" \ "use_static_ipaddr=no\0" \ "static_ipaddr=192.168.90.10\0" \ @@ -470,6 +471,7 @@ "gevss_debug=0\0" \ "watchdog=0\0" \ "usb_dr_mode=host\0" \ + "sensor_cnt=2\0" \ "" #define CONFIG_FPGA_COUNT 1 -- cgit v1.3.1