From 59a72caba907e55edf7458f83ea8f1f60dc12b6e Mon Sep 17 00:00:00 2001 From: Francesco Dolcini Date: Tue, 2 Jan 2024 13:12:07 +0100 Subject: verdin-imx8mm: Remove stale fdt_addr env variable fdt_addr variable is the location in flash of the device tree blob [1], it does not exist for verdin-imx8mm. Because of this the bootefi command fails unless the optional `[fdt address]` parameter is passed on the command line, bootefi.c:efi_install_fdt() assumes that `fdt_addr` is valid when present. Fix this removing fdt_addr from the U-Boot environment. [1] doc/usage/environment.rst Signed-off-by: Francesco Dolcini Reviewed-by: Fabio Estevam --- include/configs/verdin-imx8mm.h | 1 - 1 file changed, 1 deletion(-) (limited to 'include') diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 8072d5d503f..a7ea02807dd 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -40,7 +40,6 @@ "boot_file=Image\0" \ "boot_script_dhcp=boot.scr\0" \ "console=ttymxc0\0" \ - "fdt_addr=0x43000000\0" \ "fdt_board=dev\0" \ "initrd_addr=0x43800000\0" \ "initrd_high=0xffffffffffffffff\0" \ -- cgit v1.2.3 From 54e1aa236f7d934ea81d727fe27b6d05902643be Mon Sep 17 00:00:00 2001 From: Mathieu Othacehe Date: Fri, 29 Dec 2023 11:55:23 +0100 Subject: Add imx93-var-som support Add support for the Variscite VAR-SOM-IMX93 evaluation kit. The SoM consists of an NXP iMX93 dual A55 CPU. The SoM is mounted on a Variscite Symphony SBC. Signed-off-by: Mathieu Othacehe --- include/configs/imx93_var_som.h | 48 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) create mode 100644 include/configs/imx93_var_som.h (limited to 'include') diff --git a/include/configs/imx93_var_som.h b/include/configs/imx93_var_som.h new file mode 100644 index 00000000000..18a8ee5deed --- /dev/null +++ b/include/configs/imx93_var_som.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2022 NXP + * Copyright 2023 Variscite Ltd. + */ + +#ifndef __IMX93_VAR_SOM_H +#define __IMX93_VAR_SOM_H + +#include +#include +#include + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(MMC, mmc, 1) + +#include + +/* Initial environment variables */ +#define CFG_EXTRA_ENV_SETTINGS BOOTENV + +#define CFG_SYS_INIT_RAM_ADDR 0x80000000 +#define CFG_SYS_INIT_RAM_SIZE 0x200000 + +#define CFG_SYS_SDRAM_BASE 0x80000000 +#define PHYS_SDRAM 0x80000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ + +#define DEFAULT_SDRAM_SIZE (512 * SZ_1M) /* 512MB Minimum DDR4, see get_dram_size */ +#define VAR_EEPROM_DRAM_START (PHYS_SDRAM + (DEFAULT_SDRAM_SIZE >> 1)) +#define VAR_SOM_EEPROM_I2C_NAME "i2c@42530000" +#define VAR_CARRIER_EEPROM_I2C_NAME "i2c@44340000" + +#define CFG_SYS_FSL_USDHC_NUM 2 + +/* Using ULP WDOG for reset */ +#define WDOG_BASE_ADDR WDG3_BASE_ADDR + +#if defined(CONFIG_CMD_NET) +#define PHY_ANEG_TIMEOUT 20000 +#endif + +#endif -- cgit v1.2.3