From 3b8ac464f25581a7d22b303a9154c05e0c7f40a8 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Tue, 29 Jun 2010 11:47:48 +0200
Subject: FPGA: add support for downloading Lattice bitstream

The patch adds support to load a Lattice's bitstream
image (called VME file) into a Lattice FPGA. The code
containing the state machine delivered as part of
Lattice's ispVMtools is integrated.

The FPGA is programmed using the JTAG interface. The
board maintainer must provide accessors to drive the
JTAG signals TCK, TMS, TDI and to get the value of the
input signal TDO.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 include/fpga.h    |   1 +
 include/lattice.h | 319 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 320 insertions(+)
 create mode 100755 include/lattice.h

(limited to 'include')

diff --git a/include/fpga.h b/include/fpga.h
index 84d7b9fc1ad..ac24f2b2739 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -61,6 +61,7 @@ typedef enum {			/* typedef fpga_type */
 	fpga_min_type,		/* range check value */
 	fpga_xilinx,		/* Xilinx Family) */
 	fpga_altera,		/* unimplemented */
+	fpga_lattice,		/* Lattice family */
 	fpga_undefined		/* invalid range check value */
 } fpga_type;			/* end, typedef fpga_type */
 
diff --git a/include/lattice.h b/include/lattice.h
new file mode 100755
index 00000000000..33d2ac3df3e
--- /dev/null
+++ b/include/lattice.h
@@ -0,0 +1,319 @@
+/*
+ * Porting to U-Boot:
+ *
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
+ *
+ * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
+ *
+ * Lattice Semiconductor Corp. Copyright 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _VME_OPCODE_H
+#define _VME_OPCODE_H
+
+#define VME_VERSION_NUMBER "12.1"
+
+/* Maximum declarations. */
+
+#define VMEHEXMAX	60000L	/* The hex file is split 60K per file. */
+#define SCANMAX		64000L	/* The maximum SDR/SIR burst. */
+
+/*
+ *
+ * Supported JTAG state transitions.
+ *
+ */
+
+#define RESET		0x00
+#define IDLE		0x01
+#define IRPAUSE		0x02
+#define DRPAUSE		0x03
+#define SHIFTIR		0x04
+#define SHIFTDR		0x05
+/* 11/15/05 Nguyen changed to support DRCAPTURE*/
+#define DRCAPTURE	0x06
+
+/*
+ * Flow control register bit definitions.  A set bit indicates
+ * that the register currently exhibits the corresponding mode.
+ */
+
+#define INTEL_PRGM	0x0001	/* Intelligent programming is in effect. */
+#define CASCADE		0x0002	/* Currently splitting large SDR. */
+#define REPEATLOOP	0x0008	/* Currently executing a repeat loop. */
+#define SHIFTRIGHT	0x0080	/* The next data stream needs a right shift. */
+#define SHIFTLEFT	0x0100	/* The next data stream needs a left shift. */
+#define VERIFYUES	0x0200	/* Continue if fail is in effect. */
+
+/*
+ * DataType register bit definitions.  A set bit indicates
+ * that the register currently holds the corresponding type of data.
+ */
+
+#define EXPRESS		0x0001    /* Simultaneous program and verify. */
+#define SIR_DATA	0x0002    /* SIR is the active SVF command. */
+#define SDR_DATA	0x0004    /* SDR is the active SVF command. */
+#define COMPRESS	0x0008    /* Data is compressed. */
+#define TDI_DATA	0x0010    /* TDI data is present. */
+#define TDO_DATA	0x0020    /* TDO data is present. */
+#define MASK_DATA	0x0040    /* MASK data is present. */
+#define HEAP_IN		0x0080    /* Data is from the heap. */
+#define LHEAP_IN	0x0200    /* Data is from intel data buffer. */
+#define VARIABLE	0x0400    /* Data is from a declared variable. */
+#define CRC_DATA	0x0800	 /* CRC data is pressent. */
+#define CMASK_DATA	0x1000    /* CMASK data is pressent. */
+#define RMASK_DATA	0x2000	 /* RMASK data is pressent. */
+#define READ_DATA	0x4000    /* READ data is pressent. */
+#define DMASK_DATA	0x8000	 /* DMASK data is pressent. */
+
+/*
+ *
+ * Pin opcodes.
+ *
+ */
+
+#define signalENABLE	0x1C    /* ispENABLE pin. */
+#define signalTMS	0x1D    /* TMS pin. */
+#define signalTCK	0x1E    /* TCK pin. */
+#define signalTDI	0x1F    /* TDI pin. */
+#define signalTRST	0x20    /* TRST pin. */
+
+/*
+ *
+ * Supported vendors.
+ *
+ */
+
+#define VENDOR		0x56
+#define LATTICE		0x01
+#define ALTERA		0x02
+#define XILINX		0x03
+
+/*
+ * Opcode definitions.
+ *
+ * Note: opcodes must be unique.
+ */
+
+#define ENDDATA		0x00	/* The end of the current SDR data stream. */
+#define RUNTEST		0x01	/* The duration to stay at the stable state. */
+#define ENDDR		0x02	/* The stable state after SDR. */
+#define ENDIR		0x03	/* The stable state after SIR. */
+#define ENDSTATE	0x04	/* The stable state after RUNTEST. */
+#define TRST		0x05	/* Assert the TRST pin. */
+#define HIR		0x06	/*
+				 * The sum of the IR bits of the
+				 * leading devices.
+				 */
+#define TIR		0x07	/*
+				 * The sum of the IR bits of the trailing
+				 * devices.
+				 */
+#define HDR		0x08	/* The number of leading devices. */
+#define TDR		0x09	/* The number of trailing devices. */
+#define ispEN		0x0A	/* Assert the ispEN pin. */
+#define FREQUENCY	0x0B	/*
+				 * The maximum clock rate to run the JTAG state
+				 * machine.
+				 */
+#define STATE		0x10	/* Move to the next stable state. */
+#define SIR		0x11	/* The instruction stream follows. */
+#define SDR		0x12	/* The data stream follows. */
+#define TDI		0x13	/* The following data stream feeds into
+					the device. */
+#define TDO		0x14	/*
+				 * The following data stream is compared against
+				 * the device.
+				 */
+#define MASK		0x15	/* The following data stream is used as mask. */
+#define XSDR		0x16	/*
+				 * The following data stream is for simultaneous
+				 * program and verify.
+				 */
+#define XTDI		0x17	/* The following data stream is for shift in
+				 * only. It must be stored for the next
+				 * XSDR.
+				 */
+#define XTDO		0x18	/*
+				 * There is not data stream.  The data stream
+				 * was stored from the previous XTDI.
+				 */
+#define MEM		0x19	/*
+				 * The maximum memory needed to allocate in
+				 * order hold one row of data.
+				 */
+#define WAIT		0x1A	/* The duration of delay to observe. */
+#define TCK		0x1B	/* The number of TCK pulses. */
+#define SHR		0x23	/*
+				 * Set the flow control register for
+				 * right shift
+				 */
+#define SHL		0x24	/*
+				 * Set the flow control register for left shift.
+				 */
+#define HEAP		0x32	/* The memory size needed to hold one loop. */
+#define REPEAT		0x33	/* The beginning of the loop. */
+#define LEFTPAREN	0x35	/* The beginning of data following the loop. */
+#define VAR		0x55	/* Plac holder for loop data. */
+#define SEC		0x1C	/*
+				 * The delay time in seconds that must be
+				 * observed.
+				 */
+#define SMASK		0x1D	/* The mask for TDI data. */
+#define MAX_WAIT	0x1E	/* The absolute maximum wait time. */
+#define ON		0x1F	/* Assert the targeted pin. */
+#define OFF		0x20	/* Dis-assert the targeted pin. */
+#define SETFLOW		0x30	/* Change the flow control register. */
+#define RESETFLOW	0x31	/* Clear the flow control register. */
+
+#define CRC		0x47	/*
+				 * The following data stream is used for CRC
+				 * calculation.
+				 */
+#define CMASK		0x48	/*
+				 * The following data stream is used as mask
+				 * for CRC calculation.
+				 */
+#define RMASK		0x49	/*
+				 * The following data stream is used as mask
+				 * for read and save.
+				 */
+#define READ		0x50	/*
+				 * The following data stream is used for read
+				 * and save.
+				 */
+#define ENDLOOP		0x59	/* The end of the repeat loop. */
+#define SECUREHEAP	0x60	/* Used to secure the HEAP opcode. */
+#define VUES		0x61	/* Support continue if fail. */
+#define DMASK		0x62	/*
+				 * The following data stream is used for dynamic
+				 * I/O.
+				 */
+#define COMMENT		0x63	/* Support SVF comments in the VME file. */
+#define HEADER		0x64	/* Support header in VME file. */
+#define FILE_CRC	0x65	/* Support crc-protected VME file. */
+#define LCOUNT		0x66	/* Support intelligent programming. */
+#define LDELAY		0x67	/* Support intelligent programming. */
+#define LSDR		0x68	/* Support intelligent programming. */
+#define LHEAP		0x69	/*
+				 * Memory needed to hold intelligent data
+				 * buffer
+				 */
+#define CONTINUE	0x70	/* Allow continuation. */
+#define LVDS		0x71	/* Support LVDS. */
+#define ENDVME		0x7F	/* End of the VME file. */
+#define ENDFILE		0xFF	/* End of file. */
+
+/*
+ *
+ * ispVM Embedded Return Codes.
+ *
+ */
+
+#define VME_VERIFICATION_FAILURE	-1
+#define VME_FILE_READ_FAILURE		-2
+#define VME_VERSION_FAILURE		-3
+#define VME_INVALID_FILE		-4
+#define VME_ARGUMENT_FAILURE		-5
+#define VME_CRC_FAILURE			-6
+
+#define g_ucPinTDI	0x01
+#define g_ucPinTCK	0x02
+#define g_ucPinTMS	0x04
+#define g_ucPinENABLE	0x08
+#define g_ucPinTRST	0x10
+
+/*
+ *
+ * Type definitions.
+ *
+ */
+
+/* Support LVDS */
+typedef struct {
+	unsigned short usPositiveIndex;
+	unsigned short usNegativeIndex;
+	unsigned char  ucUpdate;
+} LVDSPair;
+
+typedef enum {
+	min_lattice_iface_type,		/* insert all new types after this */
+	lattice_jtag_mode,		/* jtag/tap  */
+	max_lattice_iface_type		/* insert all new types before this */
+} Lattice_iface;
+
+typedef enum {
+	min_lattice_type,
+	Lattice_XP2,			/* Lattice XP2 Family */
+	max_lattice_type		/* insert all new types before this */
+} Lattice_Family;
+
+typedef struct {
+	Lattice_Family	family;	/* part type */
+	Lattice_iface	iface;	/* interface type */
+	size_t		size;	/* bytes of data part can accept */
+	void		*iface_fns; /* interface function table */
+	void		*base;	/* base interface address */
+	int		cookie;	/* implementation specific cookie */
+	char		*desc;	/* description string */
+} Lattice_desc;			/* end, typedef Altera_desc */
+
+/* Lattice Model Type */
+#define CONFIG_SYS_XP2		CONFIG_SYS_FPGA_DEV(0x1)
+
+/* Board specific implementation specific function types */
+typedef void (*Lattice_jtag_init)(void);
+typedef void (*Lattice_jtag_set_tdi)(int v);
+typedef void (*Lattice_jtag_set_tms)(int v);
+typedef void (*Lattice_jtag_set_tck)(int v);
+typedef int (*Lattice_jtag_get_tdo)(void);
+
+typedef struct {
+	Lattice_jtag_init	jtag_init;
+	Lattice_jtag_set_tdi	jtag_set_tdi;
+	Lattice_jtag_set_tms	jtag_set_tms;
+	Lattice_jtag_set_tck	jtag_set_tck;
+	Lattice_jtag_get_tdo	jtag_get_tdo;
+} lattice_board_specific_func;
+
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void calibration(void);
+
+int lattice_load(Lattice_desc *desc, void *buf, size_t bsize);
+int lattice_dump(Lattice_desc *desc, void *buf, size_t bsize);
+int lattice_info(Lattice_desc *desc);
+
+void ispVMStart(void);
+void ispVMEnd(void);
+signed char ispVMCode(void);
+void ispVMDelay(unsigned short int a_usMicroSecondDelay);
+void ispVMCalculateCRC32(unsigned char a_ucData);
+unsigned char GetByte(void);
+void writePort(unsigned char pins, unsigned char value);
+unsigned char readPort(void);
+void sclock(void);
+#endif
+
-- 
cgit v1.3.1


From b9eb3fdf2f545626525b85953d322b2f8d67d319 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Tue, 29 Jun 2010 11:48:24 +0200
Subject: MX31: Add support to update FPGA bitstream

The patch adds the possibility to update the QONG
FPGA (a Lattice XP2-5E) with u-boot using some GPIOs
to drive the JTAG interface.

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 board/davedenx/qong/Makefile    |  2 +-
 board/davedenx/qong/fpga.c      | 95 +++++++++++++++++++++++++++++++++++++++++
 board/davedenx/qong/qong.c      | 11 +++++
 board/davedenx/qong/qong_fpga.h |  3 +-
 include/configs/qong.h          |  3 ++
 5 files changed, 111 insertions(+), 3 deletions(-)
 create mode 100644 board/davedenx/qong/fpga.c

(limited to 'include')

diff --git a/board/davedenx/qong/Makefile b/board/davedenx/qong/Makefile
index 93e198542ad..ada6e03a2ca 100644
--- a/board/davedenx/qong/Makefile
+++ b/board/davedenx/qong/Makefile
@@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= qong.o
+COBJS	:= qong.o fpga.o
 SOBJS	:= lowlevel_init.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/board/davedenx/qong/fpga.c b/board/davedenx/qong/fpga.c
new file mode 100644
index 00000000000..f865eb42256
--- /dev/null
+++ b/board/davedenx/qong/fpga.c
@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2010
+ * Stefano Babic, DENX Software Engineering, sbabic@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mx31-regs.h>
+#include <mxc_gpio.h>
+#include <fpga.h>
+#include <lattice.h>
+#include "qong_fpga.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if defined(CONFIG_FPGA)
+
+static void qong_jtag_init(void)
+{
+	return;
+}
+
+static void qong_fpga_jtag_set_tdi(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TDI_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tms(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TMS_PIN, value);
+}
+
+static void qong_fpga_jtag_set_tck(int value)
+{
+	mxc_gpio_set(QONG_FPGA_TCK_PIN, value);
+}
+
+static int qong_fpga_jtag_get_tdo(void)
+{
+	return mxc_gpio_get(QONG_FPGA_TDO_PIN);
+}
+
+lattice_board_specific_func qong_fpga_fns = {
+	qong_jtag_init,
+	qong_fpga_jtag_set_tdi,
+	qong_fpga_jtag_set_tms,
+	qong_fpga_jtag_set_tck,
+	qong_fpga_jtag_get_tdo
+};
+
+Lattice_desc qong_fpga[CONFIG_FPGA_COUNT] = {
+	{
+		Lattice_XP2,
+		lattice_jtag_mode,
+		356519,
+		(void *) &qong_fpga_fns,
+		NULL,
+		0,
+		"lfxp2_5e_ftbga256"
+	},
+};
+
+int qong_fpga_init(void)
+{
+	int i;
+
+	fpga_init();
+
+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
+		fpga_add(fpga_lattice, &qong_fpga[i]);
+	}
+	return 0;
+}
+
+#endif
+
diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index 9abc29c5f70..efeb0bb6bca 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -73,6 +73,15 @@ int board_early_init_f (void)
 	/* set interrupt pin as input */
 	mxc_gpio_direction(QONG_FPGA_IRQ_PIN, MXC_GPIO_DIRECTION_IN);
 
+	/* FPGA JTAG Interface */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO));
+	mxc_gpio_direction(QONG_FPGA_TCK_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TMS_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDI_PIN, MXC_GPIO_DIRECTION_OUT);
+	mxc_gpio_direction(QONG_FPGA_TDO_PIN, MXC_GPIO_DIRECTION_IN);
 #endif
 
 	/* setup pins for UART1 */
@@ -146,6 +155,8 @@ int board_init (void)
 	gd->bd->bi_arch_number = MACH_TYPE_QONG;
 	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */
 
+	qong_fpga_init();
+
 	return 0;
 }
 
diff --git a/board/davedenx/qong/qong_fpga.h b/board/davedenx/qong/qong_fpga.h
index 4e11f5a1cff..4e79ac2cfa8 100644
--- a/board/davedenx/qong/qong_fpga.h
+++ b/board/davedenx/qong/qong_fpga.h
@@ -24,7 +24,6 @@
 #ifndef QONG_FPGA_H
 #define QONG_FPGA_H
 
-#ifdef CONFIG_QONG_FPGA
 #define QONG_FPGA_CTRL_BASE		CONFIG_FPGA_BASE
 #define QONG_FPGA_CTRL_VERSION		(QONG_FPGA_CTRL_BASE + 0x00000000)
 #define QONG_FPGA_PERIPH_SIZE		(1 << 24)
@@ -35,6 +34,6 @@
 #define	QONG_FPGA_TDO_PIN		7
 #define	QONG_FPGA_RST_PIN		48
 #define	QONG_FPGA_IRQ_PIN		40
-#endif
 
+int qong_fpga_init(void);
 #endif /* QONG_FPGA_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
index cbb53dd3d28..0465ff4b882 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -66,8 +66,11 @@
 #define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 
 /* FPGA */
+#define CONFIG_FPGA
 #define CONFIG_QONG_FPGA	1
 #define CONFIG_FPGA_BASE	(CS1_BASE)
+#define CONFIG_FPGA_LATTICE
+#define CONFIG_FPGA_COUNT	1
 
 #ifdef CONFIG_QONG_FPGA
 /* Ethernet */
-- 
cgit v1.3.1


From d7dc464be4ee246ecab6c7934b322b5aaecfe5f6 Mon Sep 17 00:00:00 2001
From: Stefano Babic <sbabic@denx.de>
Date: Tue, 5 Oct 2010 14:05:11 +0200
Subject: MX31: Add USB Host support to the QONG board

Signed-off-by: Stefano Babic <sbabic@denx.de>
---
 board/davedenx/qong/qong.c | 33 +++++++++++++++++++++++++++++++++
 include/configs/qong.h     | 18 +++++++++++++++++-
 2 files changed, 50 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c
index efeb0bb6bca..8a81cfc6861 100644
--- a/board/davedenx/qong/qong.c
+++ b/board/davedenx/qong/qong.c
@@ -25,6 +25,7 @@
 #include <netdev.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
+#include <asm/io.h>
 #include <nand.h>
 #include <fsl_pmic.h>
 #include <mxc_gpio.h>
@@ -97,6 +98,38 @@ int board_early_init_f (void)
 	mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
 	mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
 
+	/* Setup pins for USB2 Host */
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
+	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+	mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+	mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+	mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+	mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG);	/* USBH2_DATA2 */
+	mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG);	/* USBH2_DATA3 */
+	mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG);	/* USBH2_DATA4 */
+	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
+	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
+	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
+
+	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
 	return 0;
 
 }
diff --git a/include/configs/qong.h b/include/configs/qong.h
index 0465ff4b882..b1aca93ddea 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -89,6 +89,22 @@
 #define CONFIG_BMP_16BPP
 #define CONFIG_DISPLAY_COM57H5M10XRC
 
+/* USB */
+#define CONFIG_CMD_USB
+#ifdef CONFIG_CMD_USB
+#define CONFIG_USB_EHCI			/* Enable EHCI USB support */
+#define CONFIG_USB_EHCI_MXC
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_MXC_USB_PORT	2
+#define CONFIG_MXC_USB_PORTSC	(MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT)
+#define CONFIG_MXC_USB_FLAGS	MXC_EHCI_POWER_PINS_ENABLED
+#define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_STORAGE
+#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_VFAT
+#define CONFIG_CMD_FAT
+#endif /* CONFIG_CMD_USB */
+
 /*
  * Reducing the ARP timeout from default 5 seconds to 200ms we speed up the
  * initial TFTP transfer, should the user wish one, significantly.
@@ -250,7 +266,7 @@ extern int qong_nand_rdy(void *chip);
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x20000
 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x60000)
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x80000)
 
 /* Address and size of Redundant Environment Sector	*/
 #define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
-- 
cgit v1.3.1


From 7b7903ec6a1c693c98e9dea512b91eb59cfd0cf6 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Mon, 27 Sep 2010 14:46:34 -0700
Subject: ARMV7: OMAP: Use default vendor/product ID for USB gadget

TI hasn't reserved a USB Product ID for gadgets, so use the default
vendor and product ID to avoid confusion.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 include/configs/omap3_beagle.h  | 5 -----
 include/configs/omap4_panda.h   | 5 -----
 include/configs/omap4_sdp4430.h | 5 -----
 3 files changed, 15 deletions(-)

(limited to 'include')

diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 1bd0f37add0..6f4ee28905c 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -111,11 +111,6 @@
 #define CONFIG_USB_DEVICE		1
 #define CONFIG_USB_TTY			1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"Beagle"
 
 /* commands to include */
 #include <config_cmd_default.h>
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index a0d27a437d5..d4a1d1c2348 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -120,11 +120,6 @@
 #define CONFIG_USB_DEVICE		1
 #define CONFIG_USB_TTY			1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"OMAP4 Panda"
 
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index d5439f988a3..98a86c3f5c3 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -121,11 +121,6 @@
 #define CONFIG_USB_DEVICE		1
 #define CONFIG_USB_TTY			1
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
-/* Change these to suit your needs */
-#define CONFIG_USBD_VENDORID		0x0451
-#define CONFIG_USBD_PRODUCTID		0x5678
-#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
-#define CONFIG_USBD_PRODUCT_NAME	"SDP4430"
 
 /* Flash */
 #define CONFIG_SYS_NO_FLASH	1
-- 
cgit v1.3.1


From 7e982c956d74614fc59cacf39016fad8bbb194ed Mon Sep 17 00:00:00 2001
From: Sukumar Ghorai <s-ghorai@ti.com>
Date: Sat, 18 Sep 2010 20:56:18 -0700
Subject: ARMV7: OMAP4: Use generic mmc driver on Panda

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
---
 board/ti/panda/panda.c        | 9 +++++++++
 include/configs/omap4_panda.h | 9 ++++-----
 2 files changed, 13 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/board/ti/panda/panda.c b/board/ti/panda/panda.c
index 1b8153ba825..78e19107978 100644
--- a/board/ti/panda/panda.c
+++ b/board/ti/panda/panda.c
@@ -23,6 +23,7 @@
  */
 #include <common.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 
 #include "panda.h"
 
@@ -87,3 +88,11 @@ void set_muxconf_regs(void)
 		   sizeof(wkup_padconf_array) /
 		   sizeof(struct pad_conf_entry));
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index d4a1d1c2348..2618f7df7cd 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -89,7 +89,6 @@
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE
 
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
@@ -107,8 +106,9 @@
 #define CONFIG_TWL6030_POWER		1
 
 /* MMC */
+#define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
@@ -150,7 +150,6 @@
 
 #define CONFIG_BOOTDELAY	3
 
-/* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -158,7 +157,7 @@
 	"console=ttyS2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
-	"mmcdev=1\0" \
+	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
@@ -174,7 +173,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init ${mmcdev}; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-- 
cgit v1.3.1


From 084c4c1bc10ef7abd64eebaf4c0a559409c82ddb Mon Sep 17 00:00:00 2001
From: Sukumar Ghorai <s-ghorai@ti.com>
Date: Sat, 18 Sep 2010 20:59:54 -0700
Subject: ARMV7: OMAP4: Use generic mmc driver on SDP4430

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
---
 board/ti/sdp4430/sdp.c          | 10 ++++++++++
 include/configs/omap4_sdp4430.h | 10 +++++-----
 2 files changed, 15 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/board/ti/sdp4430/sdp.c b/board/ti/sdp4430/sdp.c
index 7039bd559b3..01d5ce4f4fa 100644
--- a/board/ti/sdp4430/sdp.c
+++ b/board/ti/sdp4430/sdp.c
@@ -24,6 +24,7 @@
  */
 #include <common.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/mmc_host_def.h>
 
 #include "sdp.h"
 
@@ -88,3 +89,12 @@ void set_muxconf_regs(void)
 		   sizeof(wkup_padconf_array) /
 		   sizeof(struct pad_conf_entry));
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	omap_mmc_init(1);
+	return 0;
+}
+#endif
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 98a86c3f5c3..1241b1e3d8f 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -90,7 +90,7 @@
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE
 
 #define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_OVERWRITE
+
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
@@ -108,8 +108,9 @@
 #define CONFIG_TWL6030_POWER		1
 
 /* MMC */
+#define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
@@ -151,7 +152,6 @@
 
 #define CONFIG_BOOTDELAY	3
 
-/* allow overwriting serial config and ethaddr */
 #define CONFIG_ENV_OVERWRITE
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
@@ -159,7 +159,7 @@
 	"console=ttyS2,115200n8\0" \
 	"usbtty=cdc_acm\0" \
 	"vram=16M\0" \
-	"mmcdev=1\0" \
+	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"mmcargs=setenv bootargs console=${console} " \
@@ -175,7 +175,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init ${mmcdev}; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-- 
cgit v1.3.1


From 0cd31144240221a4f6b35615f1af9159fb20b266 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Sun, 19 Sep 2010 21:19:48 -0700
Subject: ARMV7: OMAP4: Use generic mmc driver on Beagle

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 board/ti/beagle/beagle.c       |  9 +++++++++
 include/configs/omap3_beagle.h | 10 ++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c
index 4647908052c..c5d6679f482 100644
--- a/board/ti/beagle/beagle.c
+++ b/board/ti/beagle/beagle.c
@@ -32,6 +32,7 @@
 #include <common.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/gpio.h>
@@ -169,3 +170,11 @@ void set_muxconf_regs(void)
 {
 	MUX_BEAGLE();
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h
index 6f4ee28905c..bbb1073a76c 100644
--- a/include/configs/omap3_beagle.h
+++ b/include/configs/omap3_beagle.h
@@ -95,8 +95,9 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
+#define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
 /* DDR - I use Micron DDR */
@@ -184,6 +185,7 @@
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
 	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"nandroot=/dev/mtdblock4 rw\0" \
@@ -204,10 +206,10 @@
 		"omapdss.def_disp=${defaultdisplay} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
@@ -217,7 +219,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-- 
cgit v1.3.1


From cd7c57262f929c3ce73bb68484989bc243752438 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Sun, 19 Sep 2010 21:21:07 -0700
Subject: ARMV7: OMAP4: Use generic mmc driver on Overo

This patch switches from the legacy mmc driver to the new generic mmc driver

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 board/overo/overo.c           |  9 +++++++++
 include/configs/omap3_overo.h | 10 ++++++----
 2 files changed, 15 insertions(+), 4 deletions(-)

(limited to 'include')

diff --git a/board/overo/overo.c b/board/overo/overo.c
index 1b67f1f5024..9c926938ba2 100644
--- a/board/overo/overo.c
+++ b/board/overo/overo.c
@@ -32,6 +32,7 @@
 #include <netdev.h>
 #include <twl4030.h>
 #include <asm/io.h>
+#include <asm/arch/mmc_host_def.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/mem.h>
 #include <asm/arch/sys_proto.h>
@@ -225,3 +226,11 @@ int board_eth_init(bd_t *bis)
 #endif
 	return rc;
 }
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bis)
+{
+	omap_mmc_init(0);
+	return 0;
+}
+#endif
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index a0e0f248b21..0d2ed44a49c 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -87,8 +87,9 @@
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
 					115200}
+#define CONFIG_GENERIC_MMC		1
 #define CONFIG_MMC			1
-#define CONFIG_OMAP3_MMC		1
+#define CONFIG_OMAP_HSMMC		1
 #define CONFIG_DOS_PARTITION		1
 
 /* DDR - I use Micron DDR */
@@ -158,6 +159,7 @@
 	"vram=12M\0" \
 	"dvimode=1024x768MR-16@60\0" \
 	"defaultdisplay=dvi\0" \
+	"mmcdev=0\0" \
 	"mmcroot=/dev/mmcblk0p2 rw\0" \
 	"mmcrootfstype=ext3 rootwait\0" \
 	"nandroot=/dev/mtdblock4 rw\0" \
@@ -178,10 +180,10 @@
 		"omapdss.def_disp=${defaultdisplay} " \
 		"root=${nandroot} " \
 		"rootfstype=${nandrootfstype}\0" \
-	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"bootm ${loadaddr}\0" \
@@ -191,7 +193,7 @@
 		"bootm ${loadaddr}\0" \
 
 #define CONFIG_BOOTCOMMAND \
-	"if mmc init; then " \
+	"if mmc rescan ${mmcdev}; then " \
 		"if run loadbootscript; then " \
 			"run bootscript; " \
 		"else " \
-- 
cgit v1.3.1


From 64455352ad0bf96570ea35e6b65e5b4f066a97e9 Mon Sep 17 00:00:00 2001
From: Sukumar Ghorai <s-ghorai@ti.com>
Date: Tue, 14 Sep 2010 13:52:34 +0530
Subject: ARMV7: OMAP4: Enable saveenv to eMMC for SDP4430

The SDP4430 does not have onboard NAND, it has eMMC on the second
MMC slot.  This patch adds support for saving the u-boot environment
to eMMC.

Signed-off-by: Aneesh V <aneesh@ti.com>
Signed-off-by: Sukumar Ghorai <s-ghorai@ti.com>
Tested-by: Steve Sakoman <steve@sakoman.com>
---
 include/configs/omap4_sdp4430.h | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

(limited to 'include')

diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 1241b1e3d8f..8274577ac8f 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -63,10 +63,10 @@
 
 /*
  * Size of malloc() pool
- * Total Size Environment - 256k
+ * Total Size Environment - 128k
  * Malloc - add 256k
  */
-#define CONFIG_ENV_SIZE			(256 << 10)
+#define CONFIG_ENV_SIZE			(128 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (256 << 10))
 #define CONFIG_SYS_GBL_DATA_SIZE	128	/* bytes reserved for */
 						/* initial data */
@@ -89,12 +89,9 @@
 #define CONFIG_CONS_INDEX		3
 #define CONFIG_SYS_NS16550_COM3		UART3_BASE
 
-#define CONFIG_ENV_IS_NOWHERE
-
 #define CONFIG_BAUDRATE			115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
 					115200}
-
 /* I2C  */
 #define CONFIG_HARD_I2C			1
 #define CONFIG_SYS_I2C_SPEED		100000
@@ -114,6 +111,11 @@
 #define CONFIG_SYS_MMC_SET_DEV		1
 #define CONFIG_DOS_PARTITION		1
 
+/* MMC ENV related defines */
+#define CONFIG_ENV_IS_IN_MMC		1
+#define CONFIG_SYS_MMC_ENV_DEV		1	/* SLOT2: eMMC(1) */
+#define CONFIG_ENV_OFFSET		0xE0000
+
 /* USB */
 #define CONFIG_MUSB_UDC			1
 #define CONFIG_USB_OMAP3		1
@@ -134,6 +136,7 @@
 #define CONFIG_CMD_FAT		/* FAT support                  */
 #define CONFIG_CMD_I2C		/* I2C serial bus support	*/
 #define CONFIG_CMD_MMC		/* MMC support                  */
+#define CONFIG_CMD_SAVEENV
 
 /* Disabled commands */
 #undef CONFIG_CMD_NET
-- 
cgit v1.3.1


From 4d7d7bc36d3ef71b4808731b345c8f68c8bed6a4 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Wed, 29 Sep 2010 13:54:19 -0700
Subject: ARMV7: OMAP3: Implement relocation for Overo

This patch fixes the build breakage introduced by the recent relocation
changes for ARMV7

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 board/overo/config.mk         | 2 +-
 include/configs/omap3_overo.h | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

(limited to 'include')

diff --git a/board/overo/config.mk b/board/overo/config.mk
index d372fd901fb..59b651f60ad 100644
--- a/board/overo/config.mk
+++ b/board/overo/config.mk
@@ -26,4 +26,4 @@
 # (mem base + reserved)
 
 # For use with external or internal boots.
-TEXT_BASE = 0x80e80000
+TEXT_BASE = 0x80008000
diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index 0d2ed44a49c..d7c7b0f0e4d 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -323,4 +323,7 @@ extern unsigned int boot_flash_type;
 
 #endif /* (CONFIG_CMD_NET) */
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
 #endif				/* __CONFIG_H */
-- 
cgit v1.3.1


From 68b0fbf08574ac2314919ce8fad9a1965041cc44 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Wed, 29 Sep 2010 13:58:34 -0700
Subject: ARMV7: OMAP3: Enable cache support on Overo

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 include/configs/omap3_overo.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'include')

diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h
index d7c7b0f0e4d..69f912679ea 100644
--- a/include/configs/omap3_overo.h
+++ b/include/configs/omap3_overo.h
@@ -98,6 +98,7 @@
 /* commands to include */
 #include <config_cmd_default.h>
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_EXT2		/* EXT2 Support			*/
 #define CONFIG_CMD_FAT		/* FAT support			*/
 #define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
-- 
cgit v1.3.1


From 57b512b2ecc9c7a6c8a39c5356ea80fc3164d9e4 Mon Sep 17 00:00:00 2001
From: Steve Sakoman <steve@sakoman.com>
Date: Wed, 29 Sep 2010 20:59:51 -0700
Subject: ARMV7: OMAP4: Implement relocation for Panda and OMAP4430SDP

This patch fixes the build breakage introduced by the recent relocation
changes for ARMV7

Signed-off-by: Steve Sakoman <steve@sakoman.com>
---
 arch/arm/cpu/armv7/omap4/board.c | 5 +++++
 board/ti/panda/config.mk         | 4 +---
 board/ti/sdp4430/config.mk       | 3 +--
 include/configs/omap4_panda.h    | 9 +++------
 include/configs/omap4_sdp4430.h  | 9 +++------
 5 files changed, 13 insertions(+), 17 deletions(-)

(limited to 'include')

diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c
index 8c1f3953edd..24a66f5b946 100644
--- a/arch/arm/cpu/armv7/omap4/board.c
+++ b/arch/arm/cpu/armv7/omap4/board.c
@@ -102,8 +102,13 @@ int dram_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 	gd->bd->bi_dram[0].start = 0x80000000;
 	gd->bd->bi_dram[0].size = sdram_size();
+#else
+	gd->ram_size = sdram_size();
+#endif
+
 	return 0;
 }
 
diff --git a/board/ti/panda/config.mk b/board/ti/panda/config.mk
index 73822637655..7176c14fcc1 100644
--- a/board/ti/panda/config.mk
+++ b/board/ti/panda/config.mk
@@ -27,6 +27,4 @@
 # 8000'0000 - 9fff'ffff (512 MB)
 # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
 # (mem base + reserved)
-
-# Let's place u-boot 1MB before the end of SDRAM.
-TEXT_BASE = 0x9ff00000
+TEXT_BASE = 0x80e80000
diff --git a/board/ti/sdp4430/config.mk b/board/ti/sdp4430/config.mk
index 73822637655..7bb94734990 100644
--- a/board/ti/sdp4430/config.mk
+++ b/board/ti/sdp4430/config.mk
@@ -28,5 +28,4 @@
 # Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
 # (mem base + reserved)
 
-# Let's place u-boot 1MB before the end of SDRAM.
-TEXT_BASE = 0x9ff00000
+TEXT_BASE = 0x80e80000
diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h
index 2618f7df7cd..b52ca19ae9a 100644
--- a/include/configs/omap4_panda.h
+++ b/include/configs/omap4_panda.h
@@ -138,12 +138,6 @@
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
 #undef CONFIG_CMD_IMLS		/* List all found images        */
 
-/*
- * Enabling relocation of u-boot by default
- * Relocation can be skipped if u-boot is copied to the TEXT_BASE
- */
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
 /*
  * Environment setup
  */
@@ -233,4 +227,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	1
 
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h
index 8274577ac8f..174d73f0668 100644
--- a/include/configs/omap4_sdp4430.h
+++ b/include/configs/omap4_sdp4430.h
@@ -143,12 +143,6 @@
 #undef CONFIG_CMD_FPGA		/* FPGA configuration Support   */
 #undef CONFIG_CMD_IMLS		/* List all found images        */
 
-/*
- * Enabling relocation of u-boot by default
- * Relocation can be skipped if u-boot is copied to the TEXT_BASE
- */
-#undef CONFIG_SKIP_RELOCATE_UBOOT
-
 /*
  * Environment setup
  */
@@ -238,4 +232,7 @@
  */
 #define CONFIG_NR_DRAM_BANKS	1
 
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 8a3f6bb6fb0d620dbad035e3d977a0b064f408d5 Mon Sep 17 00:00:00 2001
From: Enric Balletbo i Serra <eballetbo@gmail.com>
Date: Thu, 14 Oct 2010 16:54:59 -0400
Subject: OMAP3: Add support for the IGEP v2 board.

The IGEP v2 board is a low-cost, fan-less and industrial temperature
range single board computer that unleashes laptop-like performance and
expandability without the bulk, expense, or noise of typical desktop
machines. Its architecture shares much in common with other OMAP3 boards.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Acked-by: Steve Sakoman <steve.sakoman@linaro.org>
Tested-by: Steve Sakoman <steve.sakoman@linaro.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 MAINTAINERS                    |   4 +
 MAKEALL                        |   1 +
 board/isee/igep0020/Makefile   |  49 +++++++++
 board/isee/igep0020/config.mk  |  33 ++++++
 board/isee/igep0020/igep0020.c | 129 +++++++++++++++++++++++
 board/isee/igep0020/igep0020.h | 156 ++++++++++++++++++++++++++++
 boards.cfg                     |   1 +
 include/configs/igep0020.h     | 228 +++++++++++++++++++++++++++++++++++++++++
 8 files changed, 601 insertions(+)
 create mode 100644 board/isee/igep0020/Makefile
 create mode 100644 board/isee/igep0020/config.mk
 create mode 100644 board/isee/igep0020/igep0020.c
 create mode 100644 board/isee/igep0020/igep0020.h
 create mode 100644 include/configs/igep0020.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index aabd8713486..331377ef611 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -827,6 +827,10 @@ Alex Z
 	lart		SA1100
 	dnp1110		SA1110
 
+Enric Balletbo i Serra <eballetbo@iseebcn.com>
+
+	igep0020	ARM ARMV7 (OMAP3xx SoC)
+
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index abceccd8386..2af9a24724b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -491,6 +491,7 @@ LIST_ARMV7="		\
 	am3517_evm		\
 	ca9x4_ct_vxp		\
 	devkit8000		\
+	igep0020		\
 	mx51evk			\
 	omap3_beagle		\
 	omap3_overo		\
diff --git a/board/isee/igep0020/Makefile b/board/isee/igep0020/Makefile
new file mode 100644
index 00000000000..2f118792d11
--- /dev/null
+++ b/board/isee/igep0020/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= igep0020.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0020/config.mk b/board/isee/igep0020/config.mk
new file mode 100644
index 00000000000..b8812f94ab1
--- /dev/null
+++ b/board/isee/igep0020/config.mk
@@ -0,0 +1,33 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0020 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80008000
diff --git a/board/isee/igep0020/igep0020.c b/board/isee/igep0020/igep0020.c
new file mode 100644
index 00000000000..3f7eda1a6ba
--- /dev/null
+++ b/board/isee/igep0020/igep0020.c
@@ -0,0 +1,129 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <netdev.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0020.h"
+
+/* GPMC definitions for LAN9221 chips */
+static const u32 gpmc_lan_config[] = {
+    NET_LAN9221_GPMC_CONFIG1,
+    NET_LAN9221_GPMC_CONFIG2,
+    NET_LAN9221_GPMC_CONFIG3,
+    NET_LAN9221_GPMC_CONFIG4,
+    NET_LAN9221_GPMC_CONFIG5,
+    NET_LAN9221_GPMC_CONFIG6,
+};
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_IGEP0020;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: setup_net_chip
+ * Description: Setting up the configuration GPMC registers specific to the
+ *		Ethernet hardware.
+ */
+#if defined(CONFIG_CMD_NET)
+static void setup_net_chip(void)
+{
+	struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+	enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
+			GPMC_SIZE_16M);
+
+	/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+	writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+	/* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+	/* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+	writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+		&ctrl_base->gpmc_nadv_ale);
+
+	/* Make GPIO 64 as output pin and send a magic pulse through it */
+	if (!omap_request_gpio(64)) {
+		omap_set_gpio_direction(64, 0);
+		omap_set_gpio_dataout(64, 1);
+		udelay(1);
+		omap_set_gpio_dataout(64, 0);
+		udelay(1);
+		omap_set_gpio_dataout(64, 1);
+	}
+}
+#endif
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+
+#if defined(CONFIG_CMD_NET)
+	setup_net_chip();
+#endif
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT();
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_SMC911X
+	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+	return rc;
+}
diff --git a/board/isee/igep0020/igep0020.h b/board/isee/igep0020/igep0020.h
new file mode 100644
index 00000000000..c08d7583267
--- /dev/null
+++ b/board/isee/igep0020/igep0020.h
@@ -0,0 +1,156 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0020_H_
+#define _IGEP0020_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"IGEP v2 board",
+	"ONENAND",
+};
+
+/* GPMC CS 5 connected to an SMSC LAN9221 ethernet controller */
+#define NET_LAN9221_GPMC_CONFIG1    0x00001000
+#define NET_LAN9221_GPMC_CONFIG2    0x00080701
+#define NET_LAN9221_GPMC_CONFIG3    0x00020201
+#define NET_LAN9221_GPMC_CONFIG4    0x08030703
+#define NET_LAN9221_GPMC_CONFIG5    0x00060908
+#define NET_LAN9221_GPMC_CONFIG6    0x87030000
+#define NET_LAN9221_GPMC_CONFIG7    0x00000f6c
+
+static void setup_net_chip(void);
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_DEFAULT()\
+	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\
+	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\
+	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(GPMC_WAIT2),     (IEN  | PTU | DIS | M4)) /* GPIO_64-ETH_NRST */\
+	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
+	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
+	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
+	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
+	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
+	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
+	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/boards.cfg b/boards.cfg
index 132d178830a..e83197d951d 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -265,6 +265,7 @@ omap4_panda	arm	armv7		panda		ti		omap4
 omap4_sdp4430	arm	armv7		sdp4430		ti		omap4
 am3517_evm	arm	armv7		am3517evm	logicpd		omap3
 devkit8000	arm	armv7		devkit8000	timll		omap3
+igep0020	arm	armv7		igep0020	isee		omap3
 s5p_goni	arm	armv7		goni		samsung		s5pc1xx
 smdkc100	arm	armv7		smdkc100	samsung		s5pc1xx
 ixdpg425	arm	ixp
diff --git a/include/configs/igep0020.h b/include/configs/igep0020.h
new file mode 100644
index 00000000000..34e8a57b963
--- /dev/null
+++ b/include/configs/igep0020.h
@@ -0,0 +1,228 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0020	1	/* working with IGEP0020 */
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* DDR  */
+#define CONFIG_OMAP3_NUMONYX_DDR	1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+	"mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"U-Boot # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* bytes for initial data */
+
+/*
+ * SMSC911x Ethernet
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_32_BIT
+#define CONFIG_SMC911X_BASE	0x2C000000
+#endif /* (CONFIG_CMD_NET) */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 1a832dc4f8cd4cf899117ecab4821bdb9a4005bc Mon Sep 17 00:00:00 2001
From: Enric Balletbo i Serra <eballetbo@gmail.com>
Date: Thu, 14 Oct 2010 16:57:39 -0400
Subject: OMAP3: Add support for the OMAP3 IGEP module.

The IGEP module is a low-power, high performance production-ready
system-on-module (SOM) based on TI's OMAP3 family.The IGEP module
solution based upon TI OMAP3 provides a low-power/low-cost platform
for a variety of consumer/industrial/medical devices.

Signed-off-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 MAINTAINERS                    |   1 +
 MAKEALL                        |   1 +
 board/isee/igep0030/Makefile   |  49 ++++++++++
 board/isee/igep0030/config.mk  |  34 +++++++
 board/isee/igep0030/igep0030.c |  71 ++++++++++++++
 board/isee/igep0030/igep0030.h | 147 ++++++++++++++++++++++++++++
 boards.cfg                     |   1 +
 include/configs/igep0030.h     | 215 +++++++++++++++++++++++++++++++++++++++++
 8 files changed, 519 insertions(+)
 create mode 100644 board/isee/igep0030/Makefile
 create mode 100644 board/isee/igep0030/config.mk
 create mode 100644 board/isee/igep0030/igep0030.c
 create mode 100644 board/isee/igep0030/igep0030.h
 create mode 100644 include/configs/igep0030.h

(limited to 'include')

diff --git a/MAINTAINERS b/MAINTAINERS
index 331377ef611..5b526c00bbc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -830,6 +830,7 @@ Alex Z
 Enric Balletbo i Serra <eballetbo@iseebcn.com>
 
 	igep0020	ARM ARMV7 (OMAP3xx SoC)
+	igep0030	ARM ARMV7 (OMAP3xx SoC)
 
 -------------------------------------------------------------------------
 
diff --git a/MAKEALL b/MAKEALL
index 2af9a24724b..133810c8418 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -492,6 +492,7 @@ LIST_ARMV7="		\
 	ca9x4_ct_vxp		\
 	devkit8000		\
 	igep0020		\
+	igep0030		\
 	mx51evk			\
 	omap3_beagle		\
 	omap3_overo		\
diff --git a/board/isee/igep0030/Makefile b/board/isee/igep0030/Makefile
new file mode 100644
index 00000000000..cfc0411ed20
--- /dev/null
+++ b/board/isee/igep0030/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= igep0030.o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/isee/igep0030/config.mk b/board/isee/igep0030/config.mk
new file mode 100644
index 00000000000..35865e06a49
--- /dev/null
+++ b/board/isee/igep0030/config.mk
@@ -0,0 +1,34 @@
+#
+# (C) Copyright 2009
+# ISEE 2007 SL, <www.iseebcn.com>
+#
+# IGEP0030 uses OMAP3 (ARM-CortexA8) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# Physical Address:
+# 8000'0000 (bank0)
+# A000/0000 (bank1)
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+
+# For use with external or internal boots.
+TEXT_BASE = 0x80008000
+
diff --git a/board/isee/igep0030/igep0030.c b/board/isee/igep0030/igep0030.c
new file mode 100644
index 00000000000..92442591128
--- /dev/null
+++ b/board/isee/igep0030/igep0030.c
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <twl4030.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include "igep0030.h"
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* board id for Linux */
+	gd->bd->bi_arch_number = MACH_TYPE_IGEP0030;
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: Configure board specific parts
+ */
+int misc_init_r(void)
+{
+	twl4030_power_init();
+
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_DEFAULT();
+}
diff --git a/board/isee/igep0030/igep0030.h b/board/isee/igep0030/igep0030.h
new file mode 100644
index 00000000000..b7ce5aa6635
--- /dev/null
+++ b/board/isee/igep0030/igep0030.h
@@ -0,0 +1,147 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _IGEP0030_H_
+#define _IGEP0030_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_STACKED,
+	"OMAP3 IGEP module",
+	"ONENAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+
+#define MUX_DEFAULT()\
+	MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /* SDRC_D0 */\
+	MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /* SDRC_D1 */\
+	MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /* SDRC_D2 */\
+	MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /* SDRC_D3 */\
+	MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /* SDRC_D4 */\
+	MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /* SDRC_D5 */\
+	MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /* SDRC_D6 */\
+	MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /* SDRC_D7 */\
+	MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /* SDRC_D8 */\
+	MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /* SDRC_D9 */\
+	MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /* SDRC_D10 */\
+	MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /* SDRC_D11 */\
+	MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /* SDRC_D12 */\
+	MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /* SDRC_D13 */\
+	MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /* SDRC_D14 */\
+	MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /* SDRC_D15 */\
+	MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /* SDRC_D16 */\
+	MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /* SDRC_D17 */\
+	MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /* SDRC_D18 */\
+	MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /* SDRC_D19 */\
+	MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /* SDRC_D20 */\
+	MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /* SDRC_D21 */\
+	MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /* SDRC_D22 */\
+	MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /* SDRC_D23 */\
+	MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /* SDRC_D24 */\
+	MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /* SDRC_D25 */\
+	MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /* SDRC_D26 */\
+	MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /* SDRC_D27 */\
+	MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /* SDRC_D28 */\
+	MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /* SDRC_D29 */\
+	MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /* SDRC_D30 */\
+	MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /* SDRC_D31 */\
+	MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /* SDRC_CLK */\
+	MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS0 */\
+	MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS1 */\
+	MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS2 */\
+	MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /* SDRC_DQS3 */\
+	MUX_VAL(CP(GPMC_A1),        (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\
+	MUX_VAL(CP(GPMC_A2),        (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\
+	MUX_VAL(CP(GPMC_A3),        (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\
+	MUX_VAL(CP(GPMC_A4),        (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\
+	MUX_VAL(CP(GPMC_A5),        (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\
+	MUX_VAL(CP(GPMC_A6),        (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\
+	MUX_VAL(CP(GPMC_A7),        (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\
+	MUX_VAL(CP(GPMC_A8),        (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\
+	MUX_VAL(CP(GPMC_A9),        (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\
+	MUX_VAL(CP(GPMC_A10),       (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\
+	MUX_VAL(CP(GPMC_D0),        (IEN  | PTD | DIS | M0)) /* GPMC_D0 */\
+	MUX_VAL(CP(GPMC_D1),        (IEN  | PTD | DIS | M0)) /* GPMC_D1 */\
+	MUX_VAL(CP(GPMC_D2),        (IEN  | PTD | DIS | M0)) /* GPMC_D2 */\
+	MUX_VAL(CP(GPMC_D3),        (IEN  | PTD | DIS | M0)) /* GPMC_D3 */\
+	MUX_VAL(CP(GPMC_D4),        (IEN  | PTD | DIS | M0)) /* GPMC_D4 */\
+	MUX_VAL(CP(GPMC_D5),        (IEN  | PTD | DIS | M0)) /* GPMC_D5 */\
+	MUX_VAL(CP(GPMC_D6),        (IEN  | PTD | DIS | M0)) /* GPMC_D6 */\
+	MUX_VAL(CP(GPMC_D7),        (IEN  | PTD | DIS | M0)) /* GPMC_D7 */\
+	MUX_VAL(CP(GPMC_D8),        (IEN  | PTD | DIS | M0)) /* GPMC_D8 */\
+	MUX_VAL(CP(GPMC_D9),        (IEN  | PTD | DIS | M0)) /* GPMC_D9 */\
+	MUX_VAL(CP(GPMC_D10),       (IEN  | PTD | DIS | M0)) /* GPMC_D10 */\
+	MUX_VAL(CP(GPMC_D11),       (IEN  | PTD | DIS | M0)) /* GPMC_D11 */\
+	MUX_VAL(CP(GPMC_D12),       (IEN  | PTD | DIS | M0)) /* GPMC_D12 */\
+	MUX_VAL(CP(GPMC_D13),       (IEN  | PTD | DIS | M0)) /* GPMC_D13 */\
+	MUX_VAL(CP(GPMC_D14),       (IEN  | PTD | DIS | M0)) /* GPMC_D14 */\
+	MUX_VAL(CP(GPMC_D15),       (IEN  | PTD | DIS | M0)) /* GPMC_D15 */\
+	MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS0 */\
+	MUX_VAL(CP(GPMC_NCS1),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS1 */\
+	MUX_VAL(CP(GPMC_NCS2),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS2 */\
+	MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | EN  | M0)) /* GPIO_nCS3 */\
+	MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS4 */\
+	MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS5 */\
+	MUX_VAL(CP(GPMC_NCS6),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS6 */\
+	MUX_VAL(CP(GPMC_NCS7),      (IDIS | PTU | EN  | M0)) /* GPMC_nCS7 */\
+	MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\
+	MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE*/\
+	MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\
+	MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\
+	MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE*/\
+	MUX_VAL(CP(GPMC_NBE1),      (IEN  | PTD | DIS | M0)) /* GPMC_nBE1 */\
+	MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /* GPMC_nWP */\
+	MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /* GPMC_WAIT0 */\
+	MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /* MMC1_CLK */\
+	MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /* MMC1_CMD */\
+	MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT0 */\
+	MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT1 */\
+	MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT2 */\
+	MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /* MMC1_DAT3 */\
+	MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /* UART1_TX */\
+	MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /* UART1_RX */\
+	MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /* UART3_TX */\
+	MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /* UART3_RX */\
+	MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /* I2C1_SCL */\
+	MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /* I2C1_SDA */\
+	MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /* I2C4_SCL */\
+	MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /* I2C4_SDA */\
+	MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /* SYS_32K */\
+	MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /* GPIO_2 */\
+	MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /* GPIO_3 */\
+	MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /* GPIO_4 */\
+	MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /* GPIO_5 */\
+	MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /* GPIO_6 */\
+	MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /* GPIO_7 */\
+	MUX_VAL(CP(SYS_BOOT6),      (IEN  | PTD | DIS | M4)) /* GPIO_8 */\
+	MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE0 */\
+	MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | EN  | M0)) /* SDRC_CKE1 */
+#endif
diff --git a/boards.cfg b/boards.cfg
index e83197d951d..4c736802760 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -266,6 +266,7 @@ omap4_sdp4430	arm	armv7		sdp4430		ti		omap4
 am3517_evm	arm	armv7		am3517evm	logicpd		omap3
 devkit8000	arm	armv7		devkit8000	timll		omap3
 igep0020	arm	armv7		igep0020	isee		omap3
+igep0030	arm	armv7		igep0030	isee		omap3
 s5p_goni	arm	armv7		goni		samsung		s5pc1xx
 smdkc100	arm	armv7		smdkc100	samsung		s5pc1xx
 ixdpg425	arm	ixp
diff --git a/include/configs/igep0030.h b/include/configs/igep0030.h
new file mode 100644
index 00000000000..5e2e0ed7bf6
--- /dev/null
+++ b/include/configs/igep0030.h
@@ -0,0 +1,215 @@
+/*
+ * (C) Copyright 2010
+ * ISEE 2007 SL, <www.iseebcn.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+#include <asm/sizes.h>
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_ARMV7		1	/* This is an ARM V7 CPU core */
+#define CONFIG_OMAP		1	/* in a TI OMAP core */
+#define CONFIG_OMAP34XX		1	/* which is a 34XX */
+#define CONFIG_OMAP3430		1	/* which is in a 3430 */
+#define CONFIG_OMAP3_IGEP0030	1	/* working with IGEP0030 */
+
+#define CONFIG_SDRC	/* The chip has SDRC controller */
+
+#include <asm/arch/cpu.h>
+#include <asm/arch/omap3.h>
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO		1
+#define CONFIG_DISPLAY_BOARDINFO	1
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_REVISION_TAG		1
+
+/*
+ * NS16550 Configuration
+ */
+
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/* select serial console configuration */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_MMC			1
+#define CONFIG_OMAP3_MMC		1
+#define CONFIG_DOS_PARTITION		1
+
+/* DDR  */
+#define CONFIG_OMAP3_NUMONYX_DDR	1
+
+/* USB */
+#define CONFIG_MUSB_UDC			1
+#define CONFIG_USB_OMAP3		1
+#define CONFIG_TWL4030_USB		1
+
+/* USB device configuration */
+#define CONFIG_USB_DEVICE		1
+#define CONFIG_USB_TTY			1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+
+/* Change these to suit your needs */
+#define CONFIG_USBD_VENDORID		0x0451
+#define CONFIG_USBD_PRODUCTID		0x5678
+#define CONFIG_USBD_MANUFACTURER	"Texas Instruments"
+#define CONFIG_USBD_PRODUCT_NAME	"IGEP"
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_ONENAND	/* ONENAND support		*/
+#define CONFIG_CMD_MTDPARTS	/* Enable MTD parts commands	*/
+#define CONFIG_MTD_DEVICE
+
+#undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_SYS_I2C_BUS_SELECT	1
+#define CONFIG_DRIVER_OMAP34XX_I2C	1
+
+/*
+ * TWL4030
+ */
+#define CONFIG_TWL4030_POWER		1
+
+/* Environment information */
+#define CONFIG_BOOTCOMMAND \
+	"mmc init 0 ; fatload mmc 0 0x80000000 setup.ini ; source \0"
+
+#define CONFIG_BOOTDELAY		3
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"usbtty=cdc_acm\0"
+
+#define CONFIG_AUTO_COMPLETE		1
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"U-Boot # "
+#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)	/* memtest */
+								/* works on */
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0)	/* default */
+							/* load address */
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)
+
+/*
+ * OMAP3 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		(OMAP34XX_GPT2)
+#define CONFIG_SYS_PTV			2       /* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ *
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 meg */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/* SDRAM Bank Allocation method */
+#define SDRC_R_B_C		1
+
+/*
+ * FLASH and environment organization
+ */
+
+#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M /* Configure the PISMO */
+
+#define CONFIG_SYS_ONENAND_BASE		ONENAND_MAP
+
+#define ONENAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */
+#define CONFIG_ENV_ADDR			ONENAND_ENV_OFFSET
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
+#define CONFIG_SYS_GBL_DATA_SIZE	128 /* bytes for initial data */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_SP_ADDR		(LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE)
+
+#endif /* __CONFIG_H */
-- 
cgit v1.3.1


From 6b2c6468952749ec3a9acc5cd9ee4bc4e7a5a59b Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 14 Oct 2010 17:26:25 -0400
Subject: da850evm: setup NAND support under CONFIG_USE_NAND

The current da850evm config is missing the pieces for NAND support that can be
found in Sandeep's u-boot-davinci tree [1].

This patch adds NAND support in the spirit of the support in the u-boot-davinci
tree where NAND support for the da850evm can be enabled by putting a single
'#define CONFIG_USE_NAND' at the top of the include/configs/da850evm.h file.

[1] http://arago-project.org/git/people/?p=sandeep/u-boot-davinci.git;a=tree

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 include/configs/da850evm.h | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

(limited to 'include')

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index e0a3baee9e4..0320917dd80 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -78,6 +78,29 @@
 #define CONFIG_SYS_I2C_SPEED		25000
 #define CONFIG_SYS_I2C_SLAVE		10 /* Bogus, master-only in U-Boot */
 
+/*
+ * Flash & Environment
+ */
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_NAND_DAVINCI
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_IN_NAND		/* U-Boot env in NAND Flash  */
+#define CONFIG_ENV_OFFSET		0x0 /* Block 0--not used by bootcode */
+#define CONFIG_ENV_SIZE			(128 << 10)
+#define	CONFIG_SYS_NAND_USE_FLASH_BBT
+#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
+#define	CONFIG_SYS_NAND_PAGE_2K
+#define CONFIG_SYS_NAND_CS		3
+#define CONFIG_SYS_NAND_BASE		DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CONFIG_SYS_CLE_MASK		0x10
+#define CONFIG_SYS_ALE_MASK		0x8
+#undef CONFIG_SYS_NAND_HW_ECC
+#define CONFIG_SYS_MAX_NAND_DEVICE	1 /* Max number of NAND devices */
+#define NAND_MAX_CHIPS			1
+#define DEF_BOOTM			""
+#endif
+
 /*
  * U-Boot general configuration
  */
@@ -127,6 +150,12 @@
 #undef CONFIG_CMD_PING
 #endif
 
+#ifdef CONFIG_USE_NAND
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#define CONFIG_CMD_NAND
+#endif
+
 #if !defined(CONFIG_USE_NAND) && \
 	!defined(CONFIG_USE_NOR) && \
 	!defined(CONFIG_USE_SPIFLASH)
-- 
cgit v1.3.1


From 771d028afff6d223f2e9cf7ed8328eb2287f4303 Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 14 Oct 2010 17:26:27 -0400
Subject: da850evm: add mtdpart and ubi commands with NAND support

This patch enables also the mtdpart, ubi and ubifs commands when NAND support
is enabled.

Signed-off-by: Ben Gardiner<bengardiner@nanometrics.ca>
To: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 include/configs/da850evm.h | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'include')

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 0320917dd80..91dc0c68f0d 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -154,6 +154,14 @@
 #undef CONFIG_CMD_FLASH
 #undef CONFIG_CMD_IMLS
 #define CONFIG_CMD_NAND
+
+#define CONFIG_CMD_MTDPARTS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_LZO
+#define CONFIG_RBTREE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
 #endif
 
 #if !defined(CONFIG_USE_NAND) && \
-- 
cgit v1.3.1


From 3d248d37e1a176326ac8bf6a39144076707530e3 Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 14 Oct 2010 17:26:29 -0400
Subject: da850evm: basic MII EMAC support

The current da850evm support in u-boot/master omits any use of
the davinci EMAC. This patch adds basic support for the EMAC using
the MII PHY found on the baseboard of the EVM. The MAC address is
read from the environment variable 'ethadd'. Note that this is
different from the da850evm support in the u-boot omapl1 tree
where the MAC address is read from SPI flash.

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
CC: Sandeep Paulraj <s-paulraj@ti.com>
CC: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
CC: Ben Warren <biggerbadderben@gmail.com>
CC: Mike Frysinger <vapier@gentoo.org>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 board/davinci/da8xxevm/da850evm.c | 49 +++++++++++++++++++++++++++++++++++++++
 include/configs/da850evm.h        | 15 ++++++++++++
 2 files changed, 64 insertions(+)

(limited to 'include')

diff --git a/board/davinci/da8xxevm/da850evm.c b/board/davinci/da8xxevm/da850evm.c
index 0eb9e29ea35..c8c5e1b30ed 100644
--- a/board/davinci/da8xxevm/da850evm.c
+++ b/board/davinci/da8xxevm/da850evm.c
@@ -23,8 +23,11 @@
 
 #include <common.h>
 #include <i2c.h>
+#include <net.h>
+#include <netdev.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/emif_defs.h>
+#include <asm/arch/emac_defs.h>
 #include <asm/io.h>
 #include "../common/misc.h"
 #include "common.h"
@@ -49,6 +52,28 @@ static const struct pinmux_config uart_pins[] = {
 	{ pinmux(4), 2, 5 }
 };
 
+#ifdef CONFIG_DRIVER_TI_EMAC
+static const struct pinmux_config emac_pins[] = {
+	{ pinmux(2), 8, 1 },
+	{ pinmux(2), 8, 2 },
+	{ pinmux(2), 8, 3 },
+	{ pinmux(2), 8, 4 },
+	{ pinmux(2), 8, 5 },
+	{ pinmux(2), 8, 6 },
+	{ pinmux(2), 8, 7 },
+	{ pinmux(3), 8, 0 },
+	{ pinmux(3), 8, 1 },
+	{ pinmux(3), 8, 2 },
+	{ pinmux(3), 8, 3 },
+	{ pinmux(3), 8, 4 },
+	{ pinmux(3), 8, 5 },
+	{ pinmux(3), 8, 6 },
+	{ pinmux(3), 8, 7 },
+	{ pinmux(4), 8, 0 },
+	{ pinmux(4), 8, 1 }
+};
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
 /* I2C pin muxer settings */
 static const struct pinmux_config i2c_pins[] = {
 	{ pinmux(4), 2, 2 },
@@ -142,6 +167,14 @@ int board_init(void)
 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
 		return 1;
 
+#ifdef CONFIG_DRIVER_TI_EMAC
+	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
+		return 1;
+	/* set cfgchip3 to select MII */
+	writel(readl(&davinci_syscfg_regs->cfgchip3) & ~(1 << 8),
+			     &davinci_syscfg_regs->cfgchip3);
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
 	/* enable the console UART */
 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
 		DAVINCI_UART_PWREMU_MGMT_UTRST),
@@ -149,3 +182,19 @@ int board_init(void)
 
 	return 0;
 }
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+
+/*
+ * Initializes on-board ethernet controllers.
+ */
+int board_eth_init(bd_t *bis)
+{
+	if (!davinci_emac_initialize()) {
+		printf("Error: Ethernet init failed!\n");
+		return -1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_DRIVER_TI_EMAC */
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 91dc0c68f0d..d544c13a6c9 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -26,6 +26,7 @@
 /*
  * Board
  */
+#define CONFIG_DRIVER_TI_EMAC
 
 /*
  * SoC Configuration
@@ -101,6 +102,20 @@
 #define DEF_BOOTM			""
 #endif
 
+/*
+ * Network & Ethernet Configuration
+ */
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONFIG_EMAC_MDIO_PHY_NUM	0
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_NET_MULTI
+#endif
+
 /*
  * U-Boot general configuration
  */
-- 
cgit v1.3.1


From 59e0d611ad0418245e9600b50bf1374a725c95b6 Mon Sep 17 00:00:00 2001
From: Ben Gardiner <bengardiner@nanometrics.ca>
Date: Thu, 14 Oct 2010 17:26:32 -0400
Subject: da850evm: fix linux bootparam address

This patch fixes the LINUX_BOOT_PARAM_ADDR define to be based off of
PHYS_SDRAM_1 instead of CONFIG_SYS_MEMTEST_START. On da830 they are the same
thing but on da850 the CONFIG_SYS_MEMSTART define is offset from the
PHYS_SDRAM_1 start.

Without this patch it is not possible to boot linux on da850 -- bootm hangs
at "Uncompressing Linux... done, booting the kernel."

Signed-off-by: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
---
 include/configs/da850evm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'include')

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index d544c13a6c9..7bf6336b131 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -138,7 +138,7 @@
 /*
  * Linux Information
  */
-#define LINUX_BOOT_PARAM_ADDR	(CONFIG_SYS_MEMTEST_START + 0x100)
+#define LINUX_BOOT_PARAM_ADDR	(PHYS_SDRAM_1 + 0x100)
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_BOOTARGS		\
-- 
cgit v1.3.1