From 58e4ad1deee26425a6e0623481a0ced6a0c2db4e Mon Sep 17 00:00:00 2001 From: Shaohui Xie Date: Mon, 4 Jan 2016 11:03:44 +0800 Subject: armv8/ls1043aqds: Add support for >2GB memory This patch also exposes the complete DDR region(s) to Linux. Signed-off-by: Shaohui Xie Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 398f1c3f772..02247b3342b 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -33,7 +33,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_DIMM_SLOTS_PER_CTLR 1 /* Physical Memory Map */ #define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define CONFIG_DDR_SPD #define SPD_EEPROM_ADDRESS 0x51 -- cgit v1.2.3 From a4b7d68c647a14b62e400dc4e298794a3357bdd1 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Thu, 31 Dec 2015 18:29:03 +0800 Subject: armv8/ls1043aqds: fix qixis_reset command issue Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 02247b3342b..04b215c8abb 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -212,7 +212,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x44 +#define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -- cgit v1.2.3 From ee2a4eee8f7eb3128da3b9bcd72bd1de1e04e5b0 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Thu, 31 Dec 2015 18:29:04 +0800 Subject: armv8/ls1043aqds: enable qixis_reset command to boot from NAND/SD Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 04b215c8abb..12e845f6306 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -212,6 +212,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_SHIFT 0 #define QIXIS_LBMAP_DFLTBANK 0x00 #define QIXIS_LBMAP_ALTBANK 0x04 +#define QIXIS_LBMAP_NAND 0x09 +#define QIXIS_LBMAP_SD 0x00 +#define QIXIS_RCW_SRC_NAND 0x106 +#define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -- cgit v1.2.3 From a994b3deb00bf3177cdf9f92060baec4f640f466 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Wed, 16 Dec 2015 16:45:41 +0800 Subject: driver/ddr/fsl: Add workaround for A009663 Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu Reviewed-by: York Sun --- include/fsl_ddr_sdram.h | 1 + 1 file changed, 1 insertion(+) (limited to 'include') diff --git a/include/fsl_ddr_sdram.h b/include/fsl_ddr_sdram.h index 9ea8b637790..3699c0408a1 100644 --- a/include/fsl_ddr_sdram.h +++ b/include/fsl_ddr_sdram.h @@ -129,6 +129,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t; #define SDRAM_CFG2_ODT_ONLY_READ 2 #define SDRAM_CFG2_ODT_ALWAYS 3 +#define SDRAM_INTERVAL_BSTOPRE 0x3FFF #define TIMING_CFG_2_CPO_MASK 0x0F800000 #if defined(CONFIG_SYS_FSL_DDR_VER) && \ -- cgit v1.2.3 From bc71f926e35be8af1a9491ea0332871881c7eda5 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:12 +0530 Subject: SECURE BOOT: change prototype of fsl_secboot_validate function The prototype and defination of function fsl_secboot_validate has been changed to support calling this function from another function within u-boot. Only two aruments needed: 1) header address - Mandatory 2) SHA256 string - optional Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/fsl_validate.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/fsl_validate.h b/include/fsl_validate.h index a62dc74e694..bda802f1ec3 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -193,11 +193,10 @@ struct fsl_secboot_img_priv { */ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ - u32 ehdrloc; /* ESBC client location */ + ulong ehdrloc; /* ESBC client location */ }; -int fsl_secboot_validate(cmd_tbl_t *cmdtp, int flag, int argc, - char * const argv[]); +int fsl_secboot_validate(ulong haddr, char *arg_hash_str); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, -- cgit v1.2.3 From b055a0fd867b11e40944b3414026d37ea00e0840 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Tue, 8 Dec 2015 14:14:15 +0530 Subject: SECURE BOOT: support for validation of dynamic image Some images to be validated are relocated to a dynamic address at run time. So, these addresses cannot be known befor hand while signing the images and creating the header offline. So, support is required to pass the image address to the validate function as an argument. If an address is provided to the function, the address field in Header is not read and is treated as a reserved field. Signed-off-by: Saksham Jain Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/fsl_validate.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'include') diff --git a/include/fsl_validate.h b/include/fsl_validate.h index bda802f1ec3..ad14867eac8 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -193,10 +193,13 @@ struct fsl_secboot_img_priv { */ struct fsl_secboot_sg_table sgtbl[MAX_SG_ENTRIES]; /* SG table */ - ulong ehdrloc; /* ESBC client location */ + uintptr_t ehdrloc; /* ESBC Header location */ + uintptr_t img_addr; /* ESBC Image Location */ + uint32_t img_size; /* ESBC Image Size */ }; -int fsl_secboot_validate(ulong haddr, char *arg_hash_str); +int fsl_secboot_validate(uintptr_t haddr, char *arg_hash_str, + uintptr_t img_loc); int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, -- cgit v1.2.3 From 52c11d4f08ee3028688c1956718594cd47e2f0e2 Mon Sep 17 00:00:00 2001 From: Pratiyush Mohan Srivastava Date: Tue, 22 Dec 2015 16:49:34 +0530 Subject: armv8: ls2080a: Increase MC's DDR size to 512 MB Freescale's management complex (MC) uses System DDR for internal usage. Increase used System DDR size from 256MB to 512 MB. Signed-off-by: Pratiyush Mohan Srivastava Acked-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/configs/ls2080a_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'include') diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 4ae7d11685f..7323e10731d 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -196,7 +196,7 @@ unsigned long long get_qixis_addr(void); */ #if defined(CONFIG_FSL_MC_ENET) || defined(CONFIG_FSL_DEBUG_SERVER) #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE (254UL * 1024 * 1024) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) +#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024) #define CONFIG_SYS_MC_RSV_MEM_ALIGN (512UL * 1024 * 1024) #endif -- cgit v1.2.3 From ef6c55a240a0ce303617cde81b08ac96f56a89d7 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:22 +0530 Subject: secure_boot: include/configs: make secure boot header file uniform The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/configs/C29XPCIE.h | 4 ++++ include/configs/T102xQDS.h | 12 +++++++++++- include/configs/T102xRDB.h | 12 +++++++++++- include/configs/T1040QDS.h | 3 ++- include/configs/T104xRDB.h | 3 ++- include/configs/T208xQDS.h | 3 ++- include/configs/T208xRDB.h | 3 ++- include/configs/ls1021aqds.h | 5 ++++- include/configs/ls1021atwr.h | 5 ++++- include/configs/ls1043a_common.h | 8 ++++++++ include/configs/ls1043aqds.h | 2 ++ include/configs/ls1043ardb.h | 8 -------- 12 files changed, 52 insertions(+), 16 deletions(-) (limited to 'include') diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 16920c60320..890dcbb3e9c 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,4 +567,8 @@ #include +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB +#endif + #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index 951cbc4f57c..fb41a7dacc4 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -39,6 +39,8 @@ #define CONFIG_BOARD_EARLY_INIT_F #endif +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg #define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg @@ -936,8 +938,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 4a0f5b25245..113df37c5d1 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -33,6 +33,8 @@ #define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* support deep sleep */ #ifdef CONFIG_PPC_T1024 #define CONFIG_DEEP_SLEEP @@ -948,8 +950,16 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #include + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_CMD_BLOB #endif #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 9e151da16a4..5fd93a10f1e 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -835,8 +835,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index da65f567ea8..eec297188fb 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -938,8 +938,9 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #endif diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index a0cecc60cdc..019878a70f8 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -933,8 +933,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 312b0eb91f7..3665b7d1047 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -889,8 +889,9 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_BOOTCOMMAND CONFIG_LINUX -#ifdef CONFIG_SECURE_BOOT #include + +#ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB #undef CONFIG_CMD_USB #endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index e8b1ecaeb19..ee4494a8e06 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -659,12 +659,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif + +#include #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB -#include #endif #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 317ba62d3d0..d20062af5ea 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -517,12 +517,15 @@ #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL +#endif + +#include #ifdef CONFIG_SECURE_BOOT #define CONFIG_CMD_BLOB -#include #endif #endif diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 677d28113c1..e80ac271351 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -197,6 +197,8 @@ #define CONFIG_DOS_PARTITION #endif +#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ + /* FMan ucode */ #define CONFIG_SYS_DPAA_FMAN #ifdef CONFIG_SYS_DPAA_FMAN @@ -252,4 +254,10 @@ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ +/* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM +#define CONFIG_CMD_HASH +#define CONFIG_SHA_HW_ACCEL +#endif + #endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 12e845f6306..4929d981f17 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -405,4 +405,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_MII #define CONFIG_CMDLINE_TAG +#include + #endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 585114f3d58..dbdcc515ea4 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -291,14 +291,6 @@ #define CONFIG_CMD_EXT2 #endif -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL -#define CONFIG_CMD_BLOB -/* For LS1043 (ARMv8), ESBC image Address in Header is 64 bit */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #include #endif /* __LS1043ARDB_H__ */ -- cgit v1.2.3 From 74eecd820f251c6700c828d662a600c01651217f Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:23 +0530 Subject: secure_boot: include/configs: move definition of CONFIG_CMD_BLOB CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/configs/B4860QDS.h | 4 ---- include/configs/BSC9132QDS.h | 4 ---- include/configs/C29XPCIE.h | 4 ---- include/configs/P1010RDB.h | 4 ---- include/configs/P2041RDB.h | 4 ---- include/configs/T102xQDS.h | 4 ---- include/configs/T102xRDB.h | 4 ---- include/configs/T1040QDS.h | 4 ---- include/configs/T104xRDB.h | 4 ---- include/configs/T208xQDS.h | 5 ----- include/configs/T208xRDB.h | 5 ----- include/configs/T4240QDS.h | 4 ---- include/configs/T4240RDB.h | 9 --------- include/configs/corenet_ds.h | 4 ---- include/configs/ls1021aqds.h | 4 ---- include/configs/ls1021atwr.h | 4 ---- 16 files changed, 71 deletions(-) (limited to 'include') diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 9fb5cee711f..bcbae5099a7 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -924,8 +924,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h index d0e5a2565a9..89907dce4b1 100644 --- a/include/configs/BSC9132QDS.h +++ b/include/configs/BSC9132QDS.h @@ -722,8 +722,4 @@ combinations. this should be removed later #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 890dcbb3e9c..16920c60320 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -567,8 +567,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index f9776c03330..3c0faca1347 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -952,8 +952,4 @@ extern unsigned long get_sdram_size(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index b2e51b5b2f6..f250e7f88ec 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -756,8 +756,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h index fb41a7dacc4..e5df784ece9 100644 --- a/include/configs/T102xQDS.h +++ b/include/configs/T102xQDS.h @@ -946,8 +946,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 113df37c5d1..3cda3b1afdd 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -958,8 +958,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h index 5fd93a10f1e..2e7892f94ac 100644 --- a/include/configs/T1040QDS.h +++ b/include/configs/T1040QDS.h @@ -837,8 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index eec297188fb..5fc34976d74 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -940,8 +940,4 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_rcw.cfg #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 019878a70f8..a56208c6a6c 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -935,9 +935,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif - #endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 3665b7d1047..b5290a1a16e 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -891,9 +891,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#undef CONFIG_CMD_USB -#endif - #endif /* __T2080RDB_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 1b94f6436c8..91857d69970 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -644,8 +644,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 73279c899e8..eb4d52c6f5e 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -837,13 +837,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -/* Secure Boot target was not getting build for T4240 because of - * increased binary size. So the size is being reduced by removing USB - * which is anyways not used in Secure Environment. - */ -#undef CONFIG_CMD_USB -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index aef37dd670b..a099eee047c 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -765,8 +765,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */ diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ee4494a8e06..c90f5315fd5 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -666,8 +666,4 @@ unsigned long get_board_ddr_clk(void); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index d20062af5ea..f820de3b09e 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -524,8 +524,4 @@ #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif -- cgit v1.2.3 From bdc22074c511def222f93d1a9d94ec95c462c062 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:24 +0530 Subject: secure_boot: split the secure boot functionality in two parts There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/config_fsl_chain_trust.h | 101 ++++++++++++++++++++++++++++++++++ include/config_fsl_secboot.h | 116 --------------------------------------- 2 files changed, 101 insertions(+), 116 deletions(-) create mode 100644 include/config_fsl_chain_trust.h delete mode 100644 include/config_fsl_secboot.h (limited to 'include') diff --git a/include/config_fsl_chain_trust.h b/include/config_fsl_chain_trust.h new file mode 100644 index 00000000000..45dda56bc38 --- /dev/null +++ b/include/config_fsl_chain_trust.h @@ -0,0 +1,101 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_FSL_CHAIN_TRUST_H +#define __CONFIG_FSL_CHAIN_TRUST_H + +/* For secure boot, since ENVIRONMENT in flash/external memories is + * not verified, undef CONFIG_ENV_xxx and set default env + * (CONFIG_ENV_IS_NOWHERE) + */ +#ifdef CONFIG_SECURE_BOOT + +#undef CONFIG_ENV_IS_IN_EEPROM +#undef CONFIG_ENV_IS_IN_NAND +#undef CONFIG_ENV_IS_IN_MMC +#undef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_IS_IN_FLASH + +#define CONFIG_ENV_IS_NOWHERE + +#endif + +#ifdef CONFIG_CHAIN_OF_TRUST + +#ifndef CONFIG_EXTRA_ENV +#define CONFIG_EXTRA_ENV "" +#endif + +/* + * Control should not reach back to uboot after validation of images + * for secure boot flow and therefore bootscript should have + * the bootm command. If control reaches back to uboot anyhow + * after validating images, core should just spin. + */ + +/* + * Define the key hash for boot script here if public/private key pair used to + * sign bootscript are different from the SRK hash put in the fuse + * Example of defining KEY_HASH is + * #define CONFIG_BOOTSCRIPT_KEY_HASH \ + * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" + */ + +#ifdef CONFIG_BOOTSCRIPT_KEY_HASH +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr " \ + __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ + "source $img_addr;" \ + "esbc_halt\0" +#else +#define CONFIG_SECBOOT \ + "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ + "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ + "ramdisk_size=600000\';" \ + CONFIG_EXTRA_ENV \ + "esbc_validate $bs_hdraddr;" \ + "source $img_addr;" \ + "esbc_halt\0" +#endif + +/* For secure boot flow, default environment used will be used */ +#if defined(CONFIG_SYS_RAMBOOT) +#ifdef CONFIG_BOOTSCRIPT_COPY_RAM +#define CONFIG_BS_COPY_ENV \ + "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ + "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ + "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ + "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ + "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ + "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" + +#if defined(CONFIG_RAMBOOT_NAND) +#define CONFIG_BS_COPY_CMD \ + "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ + "nand read $bs_ram $bs_flash $bs_size ;" +#endif /* CONFIG_RAMBOOT_NAND */ +#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ + +#endif + +#ifndef CONFIG_BS_COPY_ENV +#define CONFIG_BS_COPY_ENV +#endif + +#ifndef CONFIG_BS_COPY_CMD +#define CONFIG_BS_COPY_CMD +#endif + +#define CONFIG_CHAIN_BOOT_CMD CONFIG_BS_COPY_ENV \ + CONFIG_BS_COPY_CMD \ + CONFIG_SECBOOT + +#endif +#endif diff --git a/include/config_fsl_secboot.h b/include/config_fsl_secboot.h deleted file mode 100644 index fc6788a7a61..00000000000 --- a/include/config_fsl_secboot.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_FSL_SECBOOT_H -#define __CONFIG_FSL_SECBOOT_H - -#ifdef CONFIG_SECURE_BOOT - -#ifndef CONFIG_CMD_ESBC_VALIDATE -#define CONFIG_CMD_ESBC_VALIDATE -#endif - -#ifndef CONFIG_EXTRA_ENV -#define CONFIG_EXTRA_ENV "" -#endif - -/* - * Control should not reach back to uboot after validation of images - * for secure boot flow and therefore bootscript should have - * the bootm command. If control reaches back to uboot anyhow - * after validating images, core should just spin. - */ - -/* - * Define the key hash for boot script here if public/private key pair used to - * sign bootscript are different from the SRK hash put in the fuse - * Example of defining KEY_HASH is - * #define CONFIG_BOOTSCRIPT_KEY_HASH \ - * "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b" - */ - -#ifdef CONFIG_BOOTSCRIPT_KEY_HASH -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000\';" \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr " \ - __stringify(CONFIG_BOOTSCRIPT_KEY_HASH)";" \ - "source $img_addr;" \ - "esbc_halt\0" -#else -#define CONFIG_SECBOOT \ - "setenv bs_hdraddr " __stringify(CONFIG_BOOTSCRIPT_HDR_ADDR)";" \ - "setenv bootargs \'root=/dev/ram rw console=ttyS0,115200 " \ - "ramdisk_size=600000\';" \ - CONFIG_EXTRA_ENV \ - "esbc_validate $bs_hdraddr;" \ - "source $img_addr;" \ - "esbc_halt\0" -#endif - -/* For secure boot flow, default environment used will be used */ -#if defined(CONFIG_SYS_RAMBOOT) -#ifdef CONFIG_BOOTSCRIPT_COPY_RAM -#define CONFIG_BS_COPY_ENV \ - "setenv bs_hdr_ram " __stringify(CONFIG_BS_HDR_ADDR_RAM)";" \ - "setenv bs_hdr_flash " __stringify(CONFIG_BS_HDR_ADDR_FLASH)";" \ - "setenv bs_hdr_size " __stringify(CONFIG_BS_HDR_SIZE)";" \ - "setenv bs_ram " __stringify(CONFIG_BS_ADDR_RAM)";" \ - "setenv bs_flash " __stringify(CONFIG_BS_ADDR_FLASH)";" \ - "setenv bs_size " __stringify(CONFIG_BS_SIZE)";" - -#if defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_BS_COPY_CMD \ - "nand read $bs_hdr_ram $bs_hdr_flash $bs_hdr_size ;" \ - "nand read $bs_ram $bs_flash $bs_size ;" -#endif /* CONFIG_RAMBOOT_NAND */ -#endif /* CONFIG_BOOTSCRIPT_COPY_RAM */ - -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#undef CONFIG_ENV_IS_IN_SPI_FLASH -#elif defined(CONFIG_RAMBOOT_NAND) -#undef CONFIG_ENV_IS_IN_NAND -#elif defined(CONFIG_RAMBOOT_SDCARD) -#undef CONFIG_ENV_IS_IN_MMC -#endif -#else /*CONFIG_SYS_RAMBOOT*/ -#undef CONFIG_ENV_IS_IN_FLASH -#endif - -#define CONFIG_ENV_IS_NOWHERE - -#ifndef CONFIG_BS_COPY_ENV -#define CONFIG_BS_COPY_ENV -#endif - -#ifndef CONFIG_BS_COPY_CMD -#define CONFIG_BS_COPY_CMD -#endif - -#define CONFIG_SECBOOT_CMD CONFIG_BS_COPY_ENV \ - CONFIG_BS_COPY_CMD \ - CONFIG_SECBOOT -/* - * We don't want boot delay for secure boot flow - * before autoboot starts - */ -#undef CONFIG_BOOTDELAY -#define CONFIG_BOOTDELAY 0 -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND CONFIG_SECBOOT_CMD - -/* - * CONFIG_ZERO_BOOTDELAY_CHECK should not be defined for - * secure boot flow as defining this would enable a user to - * reach uboot prompt by pressing some key before start of - * autoboot - */ -#undef CONFIG_ZERO_BOOTDELAY_CHECK - -#endif -#endif -- cgit v1.2.3 From d041288586b05164c84794a5956ddc5fb8939115 Mon Sep 17 00:00:00 2001 From: Aneesh Bansal Date: Fri, 22 Jan 2016 16:37:26 +0530 Subject: secure_boot: enable chain of trust for ARM platforms Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal Acked-by: Ruchika Gupta Reviewed-by: York Sun --- include/fsl_validate.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'include') diff --git a/include/fsl_validate.h b/include/fsl_validate.h index ad14867eac8..83efcf49ada 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -205,4 +205,6 @@ int fsl_secboot_blob_encap(cmd_tbl_t *cmdtp, int flag, int argc, int fsl_secboot_blob_decap(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +int fsl_check_boot_mode_secure(void); +int fsl_setenv_chain_of_trust(void); #endif -- cgit v1.2.3 From 53e353fc3e52ae8161d3977aac655f551a56a3a1 Mon Sep 17 00:00:00 2001 From: Prabhakar Kushwaha Date: Thu, 24 Dec 2015 15:32:49 +0530 Subject: driver: net: fsl-mc: flib changes for MC FW 9.0.0 MC firmware version 9.0.0 contains - Support of new APIs - Update in existing APIs - Change in Major and minor version of DPAA2 objects This patch contains modifications in FLIB files to support new MC firmware version. Signed-off-by: Prabhakar Kushwaha Reviewed-by: York Sun --- include/fsl-mc/fsl_dpbp.h | 2 +- include/fsl-mc/fsl_dpio.h | 5 +- include/fsl-mc/fsl_dpmac.h | 2 +- include/fsl-mc/fsl_dpmng.h | 2 +- include/fsl-mc/fsl_dpni.h | 539 +++++++++++++++++++++++++++++++------------- include/fsl-mc/fsl_dprc.h | 94 +++++++- include/fsl-mc/fsl_mc_cmd.h | 5 +- 7 files changed, 483 insertions(+), 166 deletions(-) (limited to 'include') diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 92c5437d891..b1ad46ee45e 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -15,7 +15,7 @@ /* DPBP Version */ #define DPBP_VER_MAJOR 2 -#define DPBP_VER_MINOR 1 +#define DPBP_VER_MINOR 2 /* Command IDs */ #define DPBP_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 0bc0b449c2b..d8c458fb4fc 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -9,7 +9,7 @@ /* DPIO Version */ #define DPIO_VER_MAJOR 3 -#define DPIO_VER_MINOR 1 +#define DPIO_VER_MINOR 2 /* Command IDs */ #define DPIO_CMDID_CLOSE 0x800 @@ -45,6 +45,7 @@ do { \ MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ MC_RSP_OP(cmd, 3, 0, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 3, 16, 16, uint16_t, attr->version.minor);\ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ } while (0) /* Data Path I/O Portal API @@ -195,6 +196,7 @@ int dpio_reset(struct fsl_mc_io *mc_io, * @channel_mode: Notification channel mode * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { int id; @@ -212,6 +214,7 @@ struct dpio_attr { uint16_t qbman_portal_id; enum dpio_channel_mode channel_mode; uint8_t num_priorities; + uint32_t qbman_version; }; /** diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 24f0b483aa5..296f3aed245 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -12,7 +12,7 @@ /* DPMAC Version */ #define DPMAC_VER_MAJOR 3 -#define DPMAC_VER_MINOR 1 +#define DPMAC_VER_MINOR 2 /* Command IDs */ #define DPMAC_CMDID_CLOSE 0x800 diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index b0a87a9082b..023b5bbdb46 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -14,7 +14,7 @@ struct fsl_mc_io; /** * Management Complex firmware version information */ -#define MC_VER_MAJOR 8 +#define MC_VER_MAJOR 9 #define MC_VER_MINOR 0 /** diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index 140a0091857..f396dc304fe 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -7,8 +7,8 @@ #define _FSL_DPNI_H /* DPNI Version */ -#define DPNI_VER_MAJOR 5 -#define DPNI_VER_MINOR 1 +#define DPNI_VER_MAJOR 6 +#define DPNI_VER_MINOR 0 /* Command IDs */ #define DPNI_CMDID_OPEN 0x801 @@ -28,6 +28,7 @@ #define DPNI_CMDID_SET_TX_BUFFER_LAYOUT 0x204 #define DPNI_CMDID_SET_TX_CONF_BUFFER_LAYOUT 0x205 #define DPNI_CMDID_GET_TX_CONF_BUFFER_LAYOUT 0x206 +#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B #define DPNI_CMDID_GET_QDID 0x210 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x212 @@ -45,11 +46,73 @@ #define DPNI_CMDID_GET_TX_FLOW 0x237 #define DPNI_CMDID_SET_RX_FLOW 0x238 #define DPNI_CMDID_GET_RX_FLOW 0x239 +#define DPNI_CMDID_SET_TX_CONF 0x257 +#define DPNI_CMDID_GET_TX_CONF 0x258 /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_OPEN(cmd, dpni_id) \ MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) +#define DPNI_PREP_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_PREP_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_PREP_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_PREP_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_PREP_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_PREP_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_PREP_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_PREP_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_PREP_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_PREP_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_PREP_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_PREP_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_PREP_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_PREP_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_PREP_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_PREP_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_PREP_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_PREP_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_PREP_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_PREP_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_PREP_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_PREP_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + +#define DPNI_EXT_EXTENDED_CFG(ext, cfg) \ +do { \ + MC_EXT_OP(ext, 0, 0, 16, uint16_t, cfg->tc_cfg[0].max_dist); \ + MC_EXT_OP(ext, 0, 16, 16, uint16_t, cfg->tc_cfg[0].max_fs_entries); \ + MC_EXT_OP(ext, 0, 32, 16, uint16_t, cfg->tc_cfg[1].max_dist); \ + MC_EXT_OP(ext, 0, 48, 16, uint16_t, cfg->tc_cfg[1].max_fs_entries); \ + MC_EXT_OP(ext, 1, 0, 16, uint16_t, cfg->tc_cfg[2].max_dist); \ + MC_EXT_OP(ext, 1, 16, 16, uint16_t, cfg->tc_cfg[2].max_fs_entries); \ + MC_EXT_OP(ext, 1, 32, 16, uint16_t, cfg->tc_cfg[3].max_dist); \ + MC_EXT_OP(ext, 1, 48, 16, uint16_t, cfg->tc_cfg[3].max_fs_entries); \ + MC_EXT_OP(ext, 2, 0, 16, uint16_t, cfg->tc_cfg[4].max_dist); \ + MC_EXT_OP(ext, 2, 16, 16, uint16_t, cfg->tc_cfg[4].max_fs_entries); \ + MC_EXT_OP(ext, 2, 32, 16, uint16_t, cfg->tc_cfg[5].max_dist); \ + MC_EXT_OP(ext, 2, 48, 16, uint16_t, cfg->tc_cfg[5].max_fs_entries); \ + MC_EXT_OP(ext, 3, 0, 16, uint16_t, cfg->tc_cfg[6].max_dist); \ + MC_EXT_OP(ext, 3, 16, 16, uint16_t, cfg->tc_cfg[6].max_fs_entries); \ + MC_EXT_OP(ext, 3, 32, 16, uint16_t, cfg->tc_cfg[7].max_dist); \ + MC_EXT_OP(ext, 3, 48, 16, uint16_t, cfg->tc_cfg[7].max_fs_entries); \ + MC_EXT_OP(ext, 4, 0, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv4); \ + MC_EXT_OP(ext, 4, 16, 16, uint16_t, \ + cfg->ipr_cfg.max_open_frames_ipv6); \ + MC_EXT_OP(ext, 4, 32, 16, uint16_t, \ + cfg->ipr_cfg.max_reass_frm_size); \ + MC_EXT_OP(ext, 5, 0, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv4); \ + MC_EXT_OP(ext, 5, 16, 16, uint16_t, \ + cfg->ipr_cfg.min_frag_size_ipv6); \ +} while (0) + /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_CREATE(cmd, cfg) \ do { \ @@ -69,32 +132,23 @@ do { \ MC_CMD_OP(cmd, 2, 32, 8, uint8_t, cfg->adv.max_qos_key_size); \ MC_CMD_OP(cmd, 2, 48, 8, uint8_t, cfg->adv.max_dist_key_size); \ MC_CMD_OP(cmd, 2, 56, 8, enum net_prot, cfg->adv.start_hdr); \ - MC_CMD_OP(cmd, 3, 0, 8, uint8_t, cfg->adv.max_dist_per_tc[0]); \ - MC_CMD_OP(cmd, 3, 8, 8, uint8_t, cfg->adv.max_dist_per_tc[1]); \ - MC_CMD_OP(cmd, 3, 16, 8, uint8_t, cfg->adv.max_dist_per_tc[2]); \ - MC_CMD_OP(cmd, 3, 24, 8, uint8_t, cfg->adv.max_dist_per_tc[3]); \ - MC_CMD_OP(cmd, 3, 32, 8, uint8_t, cfg->adv.max_dist_per_tc[4]); \ - MC_CMD_OP(cmd, 3, 40, 8, uint8_t, cfg->adv.max_dist_per_tc[5]); \ - MC_CMD_OP(cmd, 3, 48, 8, uint8_t, cfg->adv.max_dist_per_tc[6]); \ - MC_CMD_OP(cmd, 3, 56, 8, uint8_t, cfg->adv.max_dist_per_tc[7]); \ - MC_CMD_OP(cmd, 4, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_reass_frm_size); \ - MC_CMD_OP(cmd, 4, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv4); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, \ - cfg->adv.ipr_cfg.min_frag_size_ipv6); \ MC_CMD_OP(cmd, 4, 48, 8, uint8_t, cfg->adv.max_policers); \ MC_CMD_OP(cmd, 4, 56, 8, uint8_t, cfg->adv.max_congestion_ctrl); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv4); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, \ - cfg->adv.ipr_cfg.max_open_frames_ipv6); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, cfg->adv.ext_cfg_iova); \ } while (0) /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_POOLS(cmd, cfg) \ do { \ MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ + MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ + MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ + MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ + MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ + MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ + MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ + MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ + MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ @@ -113,6 +167,10 @@ do { \ MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ } while (0) +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_GET_ATTR(cmd, attr) \ + MC_CMD_OP(cmd, 6, 0, 64, uint64_t, attr->ext_cfg_iova) + /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_ATTR(cmd, attr) \ do { \ @@ -127,30 +185,20 @@ do { \ MC_RSP_OP(cmd, 2, 24, 8, uint8_t, attr->max_qos_entries); \ MC_RSP_OP(cmd, 2, 32, 8, uint8_t, attr->max_qos_key_size); \ MC_RSP_OP(cmd, 2, 40, 8, uint8_t, attr->max_dist_key_size); \ - MC_RSP_OP(cmd, 3, 0, 8, uint8_t, attr->max_dist_per_tc[0]); \ - MC_RSP_OP(cmd, 3, 8, 8, uint8_t, attr->max_dist_per_tc[1]); \ - MC_RSP_OP(cmd, 3, 16, 8, uint8_t, attr->max_dist_per_tc[2]); \ - MC_RSP_OP(cmd, 3, 24, 8, uint8_t, attr->max_dist_per_tc[3]); \ - MC_RSP_OP(cmd, 3, 32, 8, uint8_t, attr->max_dist_per_tc[4]); \ - MC_RSP_OP(cmd, 3, 40, 8, uint8_t, attr->max_dist_per_tc[5]); \ - MC_RSP_OP(cmd, 3, 48, 8, uint8_t, attr->max_dist_per_tc[6]); \ - MC_RSP_OP(cmd, 3, 56, 8, uint8_t, attr->max_dist_per_tc[7]); \ - MC_RSP_OP(cmd, 4, 0, 16, uint16_t, \ - attr->ipr_cfg.max_reass_frm_size); \ - MC_RSP_OP(cmd, 4, 16, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv4); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, \ - attr->ipr_cfg.min_frag_size_ipv6);\ - MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ - MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ - MC_RSP_OP(cmd, 5, 0, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv4); \ - MC_RSP_OP(cmd, 5, 16, 16, uint16_t, \ - attr->ipr_cfg.max_open_frames_ipv6); \ + MC_RSP_OP(cmd, 4, 48, 8, uint8_t, attr->max_policers); \ + MC_RSP_OP(cmd, 4, 56, 8, uint8_t, attr->max_congestion_ctrl); \ MC_RSP_OP(cmd, 5, 32, 16, uint16_t, attr->version.major);\ MC_RSP_OP(cmd, 5, 48, 16, uint16_t, attr->version.minor);\ } while (0) +/* cmd, param, offset, width, type, arg_name */ +#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ + MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ + MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ +} while (0) + /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_RX_BUFFER_LAYOUT(cmd, layout) \ do { \ @@ -313,23 +361,11 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_CMD_SET_TX_FLOW(cmd, flow_id, cfg) \ do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_id);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.priority);\ - MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ - cfg->conf_err_cfg.queue_cfg.dest_cfg.dest_type);\ - MC_CMD_OP(cmd, 0, 42, 1, int, cfg->conf_err_cfg.errors_only);\ MC_CMD_OP(cmd, 0, 43, 1, int, cfg->l3_chksum_gen);\ MC_CMD_OP(cmd, 0, 44, 1, int, cfg->l4_chksum_gen);\ - MC_CMD_OP(cmd, 0, 45, 1, int, \ - cfg->conf_err_cfg.use_default_queue);\ + MC_CMD_OP(cmd, 0, 45, 1, int, cfg->use_common_tx_conf_queue);\ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id);\ - MC_CMD_OP(cmd, 1, 0, 64, uint64_t, \ - cfg->conf_err_cfg.queue_cfg.user_ctx);\ MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->options);\ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, \ - cfg->conf_err_cfg.queue_cfg.options);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -343,21 +379,9 @@ do { \ /* cmd, param, offset, width, type, arg_name */ #define DPNI_RSP_GET_TX_FLOW(cmd, attr) \ do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_id);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ - attr->conf_err_attr.queue_attr.dest_cfg.priority);\ - MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ - attr->conf_err_attr.queue_attr.dest_cfg.dest_type);\ - MC_RSP_OP(cmd, 0, 42, 1, int, attr->conf_err_attr.errors_only);\ MC_RSP_OP(cmd, 0, 43, 1, int, attr->l3_chksum_gen);\ MC_RSP_OP(cmd, 0, 44, 1, int, attr->l4_chksum_gen);\ - MC_RSP_OP(cmd, 0, 45, 1, int, \ - attr->conf_err_attr.use_default_queue);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, \ - attr->conf_err_attr.queue_attr.user_ctx);\ - MC_RSP_OP(cmd, 2, 32, 32, uint32_t, \ - attr->conf_err_attr.queue_attr.fqid);\ + MC_RSP_OP(cmd, 0, 45, 1, int, attr->use_common_tx_conf_queue);\ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -370,7 +394,7 @@ do { \ MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->user_ctx); \ MC_CMD_OP(cmd, 2, 16, 8, uint8_t, tc_id); \ - MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ + MC_CMD_OP(cmd, 2, 32, 32, uint32_t, cfg->options); \ MC_CMD_OP(cmd, 3, 0, 4, enum dpni_flc_type, cfg->flc_cfg.flc_type); \ MC_CMD_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ cfg->flc_cfg.frame_data_size);\ @@ -378,6 +402,7 @@ do { \ cfg->flc_cfg.flow_context_size);\ MC_CMD_OP(cmd, 3, 32, 32, uint32_t, cfg->flc_cfg.options);\ MC_CMD_OP(cmd, 4, 0, 64, uint64_t, cfg->flc_cfg.flow_context);\ + MC_CMD_OP(cmd, 5, 0, 32, uint32_t, cfg->tail_drop_threshold); \ } while (0) /* cmd, param, offset, width, type, arg_name */ @@ -393,8 +418,9 @@ do { \ MC_RSP_OP(cmd, 0, 0, 32, int, attr->dest_cfg.dest_id); \ MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->dest_cfg.priority);\ MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, attr->dest_cfg.dest_type); \ - MC_CMD_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->order_preservation_en);\ MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->user_ctx); \ + MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->tail_drop_threshold); \ MC_RSP_OP(cmd, 2, 32, 32, uint32_t, attr->fqid); \ MC_RSP_OP(cmd, 3, 0, 4, enum dpni_flc_type, attr->flc_cfg.flc_type); \ MC_RSP_OP(cmd, 3, 4, 4, enum dpni_stash_size, \ @@ -405,6 +431,58 @@ do { \ MC_RSP_OP(cmd, 4, 0, 64, uint64_t, attr->flc_cfg.flow_context);\ } while (0) +#define DPNI_CMD_SET_TX_CONF(cmd, flow_id, cfg) \ +do { \ + MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->queue_cfg.dest_cfg.priority); \ + MC_CMD_OP(cmd, 0, 40, 2, enum dpni_dest, \ + cfg->queue_cfg.dest_cfg.dest_type); \ + MC_CMD_OP(cmd, 0, 42, 1, int, cfg->errors_only); \ + MC_CMD_OP(cmd, 0, 46, 1, int, cfg->queue_cfg.order_preservation_en); \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id); \ + MC_CMD_OP(cmd, 1, 0, 64, uint64_t, cfg->queue_cfg.user_ctx); \ + MC_CMD_OP(cmd, 2, 0, 32, uint32_t, cfg->queue_cfg.options); \ + MC_CMD_OP(cmd, 2, 32, 32, int, cfg->queue_cfg.dest_cfg.dest_id); \ + MC_CMD_OP(cmd, 3, 0, 32, uint32_t, \ + cfg->queue_cfg.tail_drop_threshold); \ + MC_CMD_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + cfg->queue_cfg.flc_cfg.flc_type); \ + MC_CMD_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.frame_data_size); \ + MC_CMD_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + cfg->queue_cfg.flc_cfg.flow_context_size); \ + MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->queue_cfg.flc_cfg.options); \ + MC_CMD_OP(cmd, 5, 0, 64, uint64_t, \ + cfg->queue_cfg.flc_cfg.flow_context); \ +} while (0) + +#define DPNI_CMD_GET_TX_CONF(cmd, flow_id) \ + MC_CMD_OP(cmd, 0, 48, 16, uint16_t, flow_id) + +#define DPNI_RSP_GET_TX_CONF(cmd, attr) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 8, uint8_t, \ + attr->queue_attr.dest_cfg.priority); \ + MC_RSP_OP(cmd, 0, 40, 2, enum dpni_dest, \ + attr->queue_attr.dest_cfg.dest_type); \ + MC_RSP_OP(cmd, 0, 42, 1, int, attr->errors_only); \ + MC_RSP_OP(cmd, 0, 46, 1, int, \ + attr->queue_attr.order_preservation_en); \ + MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->queue_attr.user_ctx); \ + MC_RSP_OP(cmd, 2, 32, 32, int, attr->queue_attr.dest_cfg.dest_id); \ + MC_RSP_OP(cmd, 3, 0, 32, uint32_t, \ + attr->queue_attr.tail_drop_threshold); \ + MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->queue_attr.fqid); \ + MC_RSP_OP(cmd, 4, 0, 4, enum dpni_flc_type, \ + attr->queue_attr.flc_cfg.flc_type); \ + MC_RSP_OP(cmd, 4, 4, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.frame_data_size); \ + MC_RSP_OP(cmd, 4, 8, 4, enum dpni_stash_size, \ + attr->queue_attr.flc_cfg.flow_context_size); \ + MC_RSP_OP(cmd, 4, 32, 32, uint32_t, attr->queue_attr.flc_cfg.options); \ + MC_RSP_OP(cmd, 5, 0, 64, uint64_t, \ + attr->queue_attr.flc_cfg.flow_context); \ +} while (0) + enum net_prot { NET_PROT_NONE = 0, NET_PROT_PAYLOAD, @@ -479,6 +557,8 @@ struct fsl_mc_io; #define DPNI_ALL_TC_FLOWS (uint16_t)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ #define DPNI_NEW_FLOW_ID (uint16_t)(-1) +/* use for common tx-conf queue; see dpni_set_tx_conf_() */ +#define DPNI_COMMON_TX_CONF (uint16_t)(-1) /** * dpni_open() - Open a control session for the specified object @@ -565,21 +645,55 @@ int dpni_close(struct fsl_mc_io *mc_io, #define DPNI_OPT_FS_MASK_SUPPORT 0x00040000 /** - * struct dpni_ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly process + * struct dpni_extended_cfg - Structure representing extended DPNI configuration + * @tc_cfg: TCs configuration + * @ipr_cfg: IP reassembly configuration */ -struct dpni_ipr_cfg { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; +struct dpni_extended_cfg { + /** + * struct tc_cfg - TC configuration + * @max_dist: Maximum distribution size for Rx traffic class; + * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, + * 112,128,192,224,256,384,448,512,768,896,1024; + * value '0' will be treated as '1'. + * other unsupported values will be round down to the nearest + * supported value. + * @max_fs_entries: Maximum FS entries for Rx traffic class; + * '0' means no support for this TC; + */ + struct { + uint16_t max_dist; + uint16_t max_fs_entries; + } tc_cfg[DPNI_MAX_TC]; + /** + * struct ipr_cfg - Structure representing IP reassembly configuration + * @max_reass_frm_size: Maximum size of the reassembled frame + * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments + * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments + * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly + * process + * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly + * process + */ + struct { + uint16_t max_reass_frm_size; + uint16_t min_frag_size_ipv4; + uint16_t min_frag_size_ipv6; + uint16_t max_open_frames_ipv4; + uint16_t max_open_frames_ipv6; + } ipr_cfg; }; +/** + * dpni_prepare_extended_cfg() - function prepare extended parameters + * @cfg: extended structure + * @ext_cfg_buf: Zeroed 256 bytes of memory before mapping it to DMA + * + * This function has to be called before dpni_create() + */ +int dpni_prepare_extended_cfg(const struct dpni_extended_cfg *cfg, + uint8_t *ext_cfg_buf); + /** * struct dpni_cfg - Structure representing DPNI configuration * @mac_addr: Primary MAC address @@ -599,11 +713,6 @@ struct dpni_cfg { * '0' will be treated as '1' * @max_tcs: Maximum number of traffic classes (for both Tx and Rx); * '0' will e treated as '1' - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Must be set to the required value minus 1; - * i.e. 0->1, 1->2, ... ,255->256; - * Non-power-of-2 values are rounded up to the next - * power-of-2 value as hardware demands it * @max_unicast_filters: Maximum number of unicast filters; * '0' is treated as '16' * @max_multicast_filters: Maximum number of multicast filters; @@ -619,16 +728,17 @@ struct dpni_cfg { * should be between '0' and max_tcs * @max_congestion_ctrl: Maximum number of congestion control groups * (CGs); covers early drop and congestion notification - * requirements for traffic classes; - * should be between '0' and max_tcs - * @ipr_cfg: IP reassembly configuration + * requirements; + * should be between '0' and ('max_tcs' + 'max_senders') + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory + * filled with the extended configuration by calling + * dpni_prepare_extended_cfg() */ struct { uint32_t options; enum net_prot start_hdr; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -637,7 +747,7 @@ struct dpni_cfg { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; } adv; }; @@ -765,8 +875,6 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_senders: Maximum number of different senders; used as the number * of dedicated Tx flows; * @max_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_dist_per_tc: Maximum distribution size per Rx traffic class; - * Set to the required value minus 1 * @max_unicast_filters: Maximum number of unicast filters * @max_multicast_filters: Maximum number of multicast filters * @max_vlan_filters: Maximum number of VLAN filters @@ -775,7 +883,8 @@ int dpni_reset(struct fsl_mc_io *mc_io, * @max_dist_key_size: Maximum key size for the distribution look-up * @max_policers: Maximum number of policers; * @max_congestion_ctrl: Maximum number of congestion control groups (CGs); - * @ipr_cfg: IP reassembly configuration + * @ext_cfg_iova: I/O virtual address of 256 bytes DMA-able memory; + * call dpni_extract_extended_cfg() to extract the extended configuration */ struct dpni_attr { int id; @@ -792,7 +901,6 @@ struct dpni_attr { uint32_t options; uint8_t max_senders; uint8_t max_tcs; - uint8_t max_dist_per_tc[DPNI_MAX_TC]; uint8_t max_unicast_filters; uint8_t max_multicast_filters; uint8_t max_vlan_filters; @@ -801,7 +909,7 @@ struct dpni_attr { uint8_t max_dist_key_size; uint8_t max_policers; uint8_t max_congestion_ctrl; - struct dpni_ipr_cfg ipr_cfg; + uint64_t ext_cfg_iova; }; /** @@ -809,7 +917,7 @@ struct dpni_attr { * @mc_io: Pointer to MC portal's I/O object * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object - * @attr: Returned object's attributes + * @attr: Object's attributes * * Return: '0' on Success; Error code otherwise. */ @@ -818,6 +926,87 @@ int dpni_get_attributes(struct fsl_mc_io *mc_io, uint16_t token, struct dpni_attr *attr); +/** + * dpni_extract_extended_cfg() - extract the extended parameters + * @cfg: extended structure + * @ext_cfg_buf: 256 bytes of DMA-able memory + * + * This function has to be called after dpni_get_attributes() + */ +int dpni_extract_extended_cfg(struct dpni_extended_cfg *cfg, + const uint8_t *ext_cfg_buf); + +/** + * DPNI errors + */ + +/** + * Extract out of frame header error + */ +#define DPNI_ERROR_EOFHE 0x00020000 +/** + * Frame length error + */ +#define DPNI_ERROR_FLE 0x00002000 +/** + * Frame physical error + */ +#define DPNI_ERROR_FPE 0x00001000 +/** + * Parsing header error + */ +#define DPNI_ERROR_PHE 0x00000020 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L3CE 0x00000004 +/** + * Parser L3 checksum error + */ +#define DPNI_ERROR_L4CE 0x00000001 + +/** + * enum dpni_error_action - Defines DPNI behavior for errors + * @DPNI_ERROR_ACTION_DISCARD: Discard the frame + * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow + * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue + */ +enum dpni_error_action { + DPNI_ERROR_ACTION_DISCARD = 0, + DPNI_ERROR_ACTION_CONTINUE = 1, + DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 +}; + +/** + * struct dpni_error_cfg - Structure representing DPNI errors treatment + * @errors: Errors mask; use 'DPNI_ERROR__ + * @error_action: The desired action for the errors mask + * @set_frame_annotation: Set to '1' to mark the errors in frame annotation + * status (FAS); relevant only for the non-discard action + */ +struct dpni_error_cfg { + uint32_t errors; + enum dpni_error_action error_action; + int set_frame_annotation; +}; + +/** + * dpni_set_errors_behavior() - Set errors behavior + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Errors configuration + * + * this function may be called numerous times with different + * error masks + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + struct dpni_error_cfg *cfg); + /* DPNI buffer layout modification options */ /* Select to modify the time-stamp setting */ @@ -1254,6 +1443,8 @@ struct dpni_flc_cfg { #define DPNI_QUEUE_OPT_FLC 0x00000004 /* Select to modify the queue's order preservation */ #define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 +/* Select to modify the queue's tail-drop threshold */ +#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 /** * struct dpni_queue_cfg - Structure representing queue configuration @@ -1272,6 +1463,10 @@ struct dpni_flc_cfg { * @order_preservation_en: enable/disable order preservation; * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained * in 'options' + * @tail_drop_threshold: set the queue's tail drop threshold in bytes; + * '0' value disable the threshold; maximum value is 0xE000000; + * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained + * in 'options' */ struct dpni_queue_cfg { uint32_t options; @@ -1279,6 +1474,7 @@ struct dpni_queue_cfg { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; }; /** @@ -1288,6 +1484,7 @@ struct dpni_queue_cfg { * @dest_cfg: Queue destination configuration * @flc_cfg: Flow context configuration * @order_preservation_en: enable/disable order preservation + * @tail_drop_threshold: queue's tail drop threshold in bytes; * @fqid: Virtual fqid value to be used for dequeue operations */ struct dpni_queue_attr { @@ -1295,6 +1492,7 @@ struct dpni_queue_attr { struct dpni_dest_cfg dest_cfg; struct dpni_flc_cfg flc_cfg; int order_preservation_en; + uint32_t tail_drop_threshold; uint32_t fqid; }; @@ -1302,10 +1500,6 @@ struct dpni_queue_attr { /* Select to modify the settings for dedicate Tx confirmation/error */ #define DPNI_TX_FLOW_OPT_TX_CONF_ERROR 0x00000001 -/*!< Select to modify the Tx confirmation and/or error setting */ -#define DPNI_TX_FLOW_OPT_ONLY_TX_ERROR 0x00000002 -/*!< Select to modify the queue configuration */ -#define DPNI_TX_FLOW_OPT_QUEUE 0x00000004 /*!< Select to modify the L3 checksum generation setting */ #define DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN 0x00000010 /*!< Select to modify the L4 checksum generation setting */ @@ -1314,41 +1508,22 @@ struct dpni_queue_attr { /** * struct dpni_tx_flow_cfg - Structure representing Tx flow configuration * @options: Flags representing the suggested modifications to the Tx flow; - * Use any combination 'DPNI_TX_FLOW_OPT_' flags - * @conf_err_cfg: Tx confirmation and error configuration; these settings are - * ignored if 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' was set at - * DPNI creation + * Use any combination 'DPNI_TX_FLOW_OPT_' flags + * @use_common_tx_conf_queue: Set to '1' to use the common (default) Tx + * confirmation and error queue; Set to '0' to use the private + * Tx confirmation and error queue; valid only if + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' wasn't set at DPNI creation + * and 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in 'options' * @l3_chksum_gen: Set to '1' to enable L3 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L3_CHKSUM_GEN' is contained in 'options' * @l4_chksum_gen: Set to '1' to enable L4 checksum generation; '0' to disable; - * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in - * 'options' + * valid only if 'DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN' is contained in 'options' */ struct dpni_tx_flow_cfg { - uint32_t options; - /** - * struct cnf_err_cfg - Tx confirmation and error configuration - * @use_default_queue: Set to '1' to use the common (default) Tx - * confirmation and error queue; Set to '0' to use the - * private Tx confirmation and error queue; valid only if - * 'DPNI_TX_FLOW_OPT_TX_CONF_ERROR' is contained in - * 'options' - * @errors_only: Set to '1' to report back only error frames; - * Set to '0' to confirm transmission/error for all - * transmitted frames; - * valid only if 'DPNI_TX_FLOW_OPT_ONLY_TX_ERROR' is - * contained in 'options' and 'use_default_queue = 0'; - * @queue_cfg: Queue configuration; valid only if - * 'DPNI_TX_FLOW_OPT_QUEUE' is contained in 'options' - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_cfg queue_cfg; - } conf_err_cfg; - int l3_chksum_gen; - int l4_chksum_gen; + uint32_t options; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1357,10 +1532,9 @@ struct dpni_tx_flow_cfg { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: Provides (or returns) the sender's flow ID; - * for each new sender set (*flow_id) to - * 'DPNI_NEW_FLOW_ID' to generate a new flow_id; - * this ID should be used as the QDBIN argument - * in enqueue operations + * for each new sender set (*flow_id) to 'DPNI_NEW_FLOW_ID' to generate + * a new flow_id; this ID should be used as the QDBIN argument + * in enqueue operations * @cfg: Tx flow configuration * * Return: '0' on Success; Error code otherwise. @@ -1373,28 +1547,15 @@ int dpni_set_tx_flow(struct fsl_mc_io *mc_io, /** * struct dpni_tx_flow_attr - Structure representing Tx flow attributes - * @conf_err_attr: Tx confirmation and error attributes + * @use_common_tx_conf_queue: '1' if using common (default) Tx confirmation and + * error queue; '0' if using private Tx confirmation and error queue * @l3_chksum_gen: '1' if L3 checksum generation is enabled; '0' if disabled * @l4_chksum_gen: '1' if L4 checksum generation is enabled; '0' if disabled */ struct dpni_tx_flow_attr { - /** - * struct conf_err_attr - Tx confirmation and error attributes - * @use_default_queue: '1' if using common (default) Tx confirmation and - * error queue; - * '0' if using private Tx confirmation and error - * queue - * @errors_only: '1' if only error frames are reported back; '0' if all - * transmitted frames are confirmed - * @queue_attr: Queue attributes - */ - struct { - int use_default_queue; - int errors_only; - struct dpni_queue_attr queue_attr; - } conf_err_attr; - int l3_chksum_gen; - int l4_chksum_gen; + int use_common_tx_conf_queue; + int l3_chksum_gen; + int l4_chksum_gen; }; /** @@ -1403,7 +1564,7 @@ struct dpni_tx_flow_attr { * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' * @token: Token of DPNI object * @flow_id: The sender's flow ID, as returned by the - * dpni_set_tx_flow() function + * dpni_set_tx_flow() function * @attr: Returned Tx flow attributes * * Return: '0' on Success; Error code otherwise. @@ -1414,6 +1575,76 @@ int dpni_get_tx_flow(struct fsl_mc_io *mc_io, uint16_t flow_id, struct dpni_tx_flow_attr *attr); +/** + * struct dpni_tx_conf_cfg - Structure representing Tx conf configuration + * @errors_only: Set to '1' to report back only error frames; + * Set to '0' to confirm transmission/error for all transmitted frames; + * @queue_cfg: Queue configuration + */ +struct dpni_tx_conf_cfg { + int errors_only; + struct dpni_queue_cfg queue_cfg; +}; + +/** + * dpni_set_tx_conf() - Set Tx confirmation and error queue configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @cfg: Queue configuration + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * if 'DPNI_OPT_TX_CONF_DISABLED' was selected, only error frames are reported + * back - successfully transmitted frames are not confirmed. Otherwise, all + * transmitted frames are sent for confirmation. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + const struct dpni_tx_conf_cfg *cfg); + +/** + * struct dpni_tx_conf_attr - Structure representing Tx conf attributes + * @errors_only: '1' if only error frames are reported back; '0' if all + * transmitted frames are confirmed + * @queue_attr: Queue attributes + */ +struct dpni_tx_conf_attr { + int errors_only; + struct dpni_queue_attr queue_attr; +}; + +/** + * dpni_get_tx_conf() - Get Tx confirmation and error queue attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @flow_id: The sender's flow ID, as returned by the + * dpni_set_tx_flow() function; + * use 'DPNI_COMMON_TX_CONF' for common tx-conf + * @attr: Returned tx-conf attributes + * + * If either 'DPNI_OPT_TX_CONF_DISABLED' or + * 'DPNI_OPT_PRIVATE_TX_CONF_ERROR_DISABLED' were selected at DPNI creation, + * this function can ONLY be used with 'flow_id == DPNI_COMMON_TX_CONF'; + * i.e. only serve the common tx-conf-err queue; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_conf(struct fsl_mc_io *mc_io, + uint32_t cmd_flags, + uint16_t token, + uint16_t flow_id, + struct dpni_tx_conf_attr *attr); /** * dpni_set_rx_flow() - Set Rx flow configuration * @mc_io: Pointer to MC portal's I/O object diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index a87179d6d55..535c789c95e 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -11,7 +11,7 @@ /* DPRC Version */ #define DPRC_VER_MAJOR 5 -#define DPRC_VER_MINOR 0 +#define DPRC_VER_MINOR 1 /* Command IDs */ #define DPRC_CMDID_CLOSE 0x800 @@ -110,6 +110,74 @@ do { \ MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ + MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ + MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ + MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ + MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ + MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ + MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ + MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ + MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ + MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ + MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ + MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ + MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ + MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ + MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ + MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ + MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ + MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ + MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ + MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ + MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ + MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ + MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ + MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ + MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ + MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ + MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ + MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ + MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ + MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ + MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ + MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ + MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ +do { \ + MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ + MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ + MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ + MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ + MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ + MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ + MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ + MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ + MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ + MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ + MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ + MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ + MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ + MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ + MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ + MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ + MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ +} while (0) + +/* cmd, param, offset, width, type, arg_name */ +#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ +do { \ + MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ + MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ + MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ + MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ + MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ + MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ + MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ + MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ @@ -480,14 +548,13 @@ int dprc_close(struct fsl_mc_io *mc_io, */ #define DPRC_CFG_OPT_TOPOLOGY_CHANGES_ALLOWED 0x00000008 -/* IOMMU bypass - indicates whether objects of this container are permitted - * to bypass the IOMMU. - */ -#define DPRC_CFG_OPT_IOMMU_BYPASS 0x00000010 -/* AIOP - Indicates that container belongs to AIOP. */ +/* AIOP - Indicates that container belongs to AIOP. */ #define DPRC_CFG_OPT_AIOP 0x00000020 +/* IRQ Config - Indicates that the container allowed to configure its IRQs.*/ +#define DPRC_CFG_OPT_IRQ_CFG_ALLOWED 0x00000040 + /** * struct dprc_cfg - Container configuration options * @icid: Container's ICID; if set to 'DPRC_GET_ICID_FROM_POOL', a free @@ -636,6 +703,14 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, /* Plugged state - Indicates that the object is plugged */ #define DPRC_OBJ_STATE_PLUGGED 0x00000002 +/** + * Shareability flag - Object flag indicating no memory shareability. + * the object generates memory accesses that are non coherent with other + * masters; + * user is responsible for proper memory handling through IOMMU configuration. + */ +#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 + /** * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() * @type: Type of object: NULL terminated string @@ -647,6 +722,7 @@ int dprc_get_obj_count(struct fsl_mc_io *mc_io, * @region_count: Number of mappable regions supported by the object * @state: Object state: combination of DPRC_OBJ_STATE_ states * @label: Object label + * @flags: Object's flags */ struct dprc_obj_desc { char type[16]; @@ -658,6 +734,7 @@ struct dprc_obj_desc { uint8_t region_count; uint32_t state; char label[16]; + uint16_t flags; }; /** @@ -859,7 +936,10 @@ int dprc_disconnect(struct fsl_mc_io *mc_io, * @token: Token of DPRC object * @endpoint1: Endpoint 1 configuration parameters * @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: 1 - link is up, 0 - link is down +* @state: Returned link state: +* 1 - link is up; +* 0 - link is down; +* -1 - no connection (endpoint2 information is irrelevant) * * Return: '0' on Success; -ENAVAIL if connection does not exist. */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 7f87d4e3021..f3d1498cc0f 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -68,8 +68,11 @@ enum mc_cmd_status { #define MC_CMD_HDR_READ_TOKEN(_hdr) \ ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) +#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ + ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) + #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= mc_enc((_offset), (_width), _arg)) + (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) -- cgit v1.2.3 From 2970e14f652db18f5353f26f84e21f7dac84576d Mon Sep 17 00:00:00 2001 From: Wenbin Song Date: Thu, 21 Jan 2016 17:14:55 +0800 Subject: armv8/ls1043aqds: Add lpuart support Add lpuart support using the driver model. Signed-off-by: Wenbin Song Reviewed-by: Bin Meng Reviewed-by: York Sun --- include/configs/ls1043aqds.h | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4929d981f17..e6725e3be8a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -88,6 +88,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +/* LPUART */ +#ifdef CONFIG_LPUART +#define CONFIG_LPUART_32B_REG +#endif + /* SATA */ #define CONFIG_LIBATA #define CONFIG_SCSI_AHCI -- cgit v1.2.3 From e0579a5852b3edb09f965dbbbd0b49507931be95 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Mon, 25 Jan 2016 15:16:05 +0800 Subject: armv8/ls1043aqds: add DSPI support Enable three DSPI flash memories on board. Commands: => sf probe 1:0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB => sf probe 1:1 SF: Detected SST25WF040B with page size 256 Bytes, erase size 4 KiB, total 512 KiB => sf probe 1:2 SF: Detected EN25S64 with page size 256 Bytes, erase size 64 KiB, total 8 MiB Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 12 ++++++++++++ include/configs/ls1043ardb.h | 10 ---------- 2 files changed, 12 insertions(+), 10 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index e80ac271351..35d97508a8b 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -197,6 +197,18 @@ #define CONFIG_DOS_PARTITION #endif +/* DSPI */ +#define CONFIG_FSL_DSPI +#ifdef CONFIG_FSL_DSPI +#define CONFIG_CMD_SF +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ +#define CONFIG_SPI_FLASH_SST /* cs1 */ +#define CONFIG_SPI_FLASH_EON /* cs2 */ +#define CONFIG_SF_DEFAULT_BUS 1 +#define CONFIG_SF_DEFAULT_CS 0 +#endif + #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ /* FMan ucode */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index dbdcc515ea4..506f50d8955 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -222,16 +222,6 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -/* DSPI */ -#define CONFIG_FSL_DSPI -#ifdef CONFIG_FSL_DSPI -#define CONFIG_CMD_SF -#define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SF_DEFAULT_BUS 1 -#define CONFIG_SF_DEFAULT_CS 0 -#endif - /* * Environment */ -- cgit v1.2.3 From 166ef1e90ce404a6470a1c4910a1e84404379b86 Mon Sep 17 00:00:00 2001 From: Gong Qianyu Date: Mon, 25 Jan 2016 15:16:06 +0800 Subject: armv8/ls1043aqds: add QSPI support in SD boot QSPI and IFC are pin-multiplexed on LS1043A. So we use ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 13 +++++++++++++ include/configs/ls1043aqds.h | 24 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 35d97508a8b..8900daee950 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -121,6 +121,7 @@ #endif /* IFC */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -139,6 +140,7 @@ #define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #endif +#endif /* I2C */ #define CONFIG_CMD_I2C @@ -205,9 +207,11 @@ #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 #endif +#endif #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ @@ -216,9 +220,18 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 1000000 +#define CONFIG_ENV_SPI_MODE 0x03 +#else #define CONFIG_SYS_QE_FMAN_FW_IN_NOR /* FMan fireware Pre-load address */ #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000 +#endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #endif diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index e6725e3be8a..60d189bf09c 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -85,8 +85,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg +#else #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg #endif +#endif /* LPUART */ #ifdef CONFIG_LPUART @@ -113,6 +118,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ +#ifndef CONFIG_SD_BOOT_QSPI #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ @@ -196,6 +202,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) +#endif #ifdef CONFIG_NAND_BOOT #define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ @@ -203,6 +210,12 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_QIXIS_I2C_ACCESS +#define CONFIG_SYS_NO_FLASH +#undef CONFIG_CMD_IMLS +#endif + /* * QIXIS Definitions */ @@ -219,6 +232,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_ALTBANK 0x04 #define QIXIS_LBMAP_NAND 0x09 #define QIXIS_LBMAP_SD 0x00 +#define QIXIS_LBMAP_SD_QSPI 0xff #define QIXIS_RCW_SRC_NAND 0x106 #define QIXIS_RCW_SRC_SD 0x040 #define QIXIS_RST_CTL_RESET 0x41 @@ -347,6 +361,16 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MIN 819 #define VDD_MV_MAX 1212 +/* QSPI device */ +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_FSL_QSPI +#ifdef CONFIG_FSL_QSPI +#define CONFIG_SPI_FLASH_SPANSION +#define FSL_QSPI_FLASH_SIZE (1 << 24) +#define FSL_QSPI_FLASH_NUM 2 +#endif +#endif + /* * Miscellaneous configurable options */ -- cgit v1.2.3 From b0f20caf6570fbc4d19c41dcedf9679784042860 Mon Sep 17 00:00:00 2001 From: Qianyu Gong Date: Mon, 25 Jan 2016 15:16:07 +0800 Subject: armv8/ls1043aqds: add QSPI boot support Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver. Signed-off-by: Gong Qianyu Reviewed-by: York Sun --- include/configs/ls1043a_common.h | 6 +++--- include/configs/ls1043aqds.h | 19 ++++++++++++++++--- 2 files changed, 19 insertions(+), 6 deletions(-) (limited to 'include') diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 8900daee950..6150bc1a74f 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -121,7 +121,7 @@ #endif /* IFC */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC /* * CONFIG_SYS_FLASH_BASE has the final address (core view) @@ -207,7 +207,7 @@ #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ #define CONFIG_SPI_FLASH_SST /* cs1 */ #define CONFIG_SPI_FLASH_EON /* cs2 */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SF_DEFAULT_BUS 1 #define CONFIG_SF_DEFAULT_CS 0 #endif @@ -220,7 +220,7 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 #define CONFIG_ENV_SPI_BUS 0 diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 60d189bf09c..4ab8e13ba1a 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -10,10 +10,16 @@ #include "ls1043a_common.h" #define CONFIG_DISPLAY_CPUINFO +#ifdef CONFIG_QSPI_BOOT +#define CONFIG_DISPLAY_BOARDINFO_LATE +#else #define CONFIG_DISPLAY_BOARDINFO +#endif #if defined(CONFIG_NAND_BOOT) || defined(CONFIG_SD_BOOT) #define CONFIG_SYS_TEXT_BASE 0x82000000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_SYS_TEXT_BASE 0x40010000 #else #define CONFIG_SYS_TEXT_BASE 0x60100000 #endif @@ -118,7 +124,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_SD_BOOT_QSPI +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NOR0_CSPR_EXT (0x0) #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ CSPR_PORT_SIZE_16 | \ @@ -210,7 +216,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) #endif -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_QIXIS_I2C_ACCESS #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS @@ -233,8 +239,10 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_LBMAP_NAND 0x09 #define QIXIS_LBMAP_SD 0x00 #define QIXIS_LBMAP_SD_QSPI 0xff +#define QIXIS_LBMAP_QSPI 0xff #define QIXIS_RCW_SRC_NAND 0x106 #define QIXIS_RCW_SRC_SD 0x040 +#define QIXIS_RCW_SRC_QSPI 0x045 #define QIXIS_RST_CTL_RESET 0x41 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 @@ -362,7 +370,7 @@ unsigned long get_board_ddr_clk(void); #define VDD_MV_MAX 1212 /* QSPI device */ -#ifdef CONFIG_SD_BOOT_QSPI +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_QSPI #ifdef CONFIG_FSL_QSPI #define CONFIG_SPI_FLASH_SPANSION @@ -421,6 +429,11 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_QSPI_BOOT) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000) -- cgit v1.2.3