From ef339cc2b68e4cbef3f9376a45315e1b974bbd8d Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 9 Feb 2009 15:53:31 +0100 Subject: Added nomadik.h header Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- include/configs/nmdk8815.h | 24 ++---------------------- include/nomadik.h | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 41 insertions(+), 22 deletions(-) create mode 100644 include/nomadik.h (limited to 'include') diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h index 01de08fab70..a370f6cc510 100644 --- a/include/configs/nmdk8815.h +++ b/include/configs/nmdk8815.h @@ -25,6 +25,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include + #define CONFIG_ARM926EJS #define CONFIG_NOMADIK #define CONFIG_NOMADIK_8815 @@ -163,26 +165,4 @@ #define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* base addresses of our peripherals */ -#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ -#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ -#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ -#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ -#define NOMADIK_1NAND_BASE 0x30000000 -#define NOMADIK_GPIO0_BASE 0x101E4000 -#define NOMADIK_GPIO1_BASE 0x101E5000 -#define NOMADIK_GPIO2_BASE 0x101E6000 -#define NOMADIK_GPIO3_BASE 0x101E7000 -#define NOMADIK_CPLD_BASE 0x36000000 -#define NOMADIK_UART0_BASE 0x101FD000 -#define NOMADIK_UART1_BASE 0x101FB000 -#define NOMADIK_UART2_BASE 0x101F2000 - -#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ -#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ - -#define NOMADIK_RTC_BASE 0x101E8000 -#define NOMADIK_ETH0_BASE 0x36800300 -#define NOMADIK_CPLD_UART_BASE 0x36480000 - #endif /* __CONFIG_H */ diff --git a/include/nomadik.h b/include/nomadik.h new file mode 100644 index 00000000000..d9405fd2875 --- /dev/null +++ b/include/nomadik.h @@ -0,0 +1,39 @@ +/* Collection of constants used to access Nomadik registers */ + +#ifndef __NOMADIK_H__ +#define __NOMADIK_H__ + +/* Base addresses of our peripherals */ +#define NOMADIK_SRC_BASE 0x101E0000 /* System and Reset Cnt */ +#define NOMADIK_PMU_BASE 0x101E9000 /* Power Management Unit */ +#define NOMADIK_MPMC_BASE 0x10110000 /* SDRAM Controller */ +#define NOMADIK_FSMC_BASE 0x10100000 /* FSMC Controller */ +#define NOMADIK_1NAND_BASE 0x30000000 +#define NOMADIK_GPIO0_BASE 0x101E4000 +#define NOMADIK_GPIO1_BASE 0x101E5000 +#define NOMADIK_GPIO2_BASE 0x101E6000 +#define NOMADIK_GPIO3_BASE 0x101E7000 +#define NOMADIK_CPLD_BASE 0x36000000 +#define NOMADIK_UART0_BASE 0x101FD000 +#define NOMADIK_UART1_BASE 0x101FB000 +#define NOMADIK_UART2_BASE 0x101F2000 + +#define NOMADIK_I2C1_BASE 0x101F7000 /* I2C1 interface */ +#define NOMADIK_I2C0_BASE 0x101F8000 /* I2C0 interface */ + +#define NOMADIK_RTC_BASE 0x101E8000 +#define NOMADIK_ETH0_BASE 0x36800300 +#define NOMADIK_CPLD_UART_BASE 0x36480000 + +/* Chip select registers ("Flexible Static Memory Controller") */ + +#define REG_FSMC_BCR0 (NOMADIK_FSMC_BASE + 0x00) +#define REG_FSMC_BTR0 (NOMADIK_FSMC_BASE + 0x04) +#define REG_FSMC_BCR1 (NOMADIK_FSMC_BASE + 0x08) +#define REG_FSMC_BTR1 (NOMADIK_FSMC_BASE + 0x0c) +#define REG_FSMC_PCR0 (NOMADIK_FSMC_BASE + 0x40) +#define REG_FSMC_PMEM0 (NOMADIK_FSMC_BASE + 0x48) +#define REG_FSMC_PATT0 (NOMADIK_FSMC_BASE + 0x4c) +#define REG_FSMC_ECCR0 (NOMADIK_FSMC_BASE + 0x54) + +#endif /* __NOMADIK_H__ */ -- cgit v1.3.1 From 0d8c6eab2481046e9446264bfe9402bb98ddf433 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 9 Feb 2009 15:53:31 +0100 Subject: Nand driver for Nomadik SoC This driver implements the ECC algorithm described in the CPU data sheet and uses the OOB layout chosen in already-released development systems (shipped with a custom-made u-boot 1.3.1). Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/nomadik.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ include/configs/nmdk8815.h | 18 ++-- 3 files changed, 230 insertions(+), 10 deletions(-) create mode 100644 drivers/mtd/nand/nomadik.c (limited to 'include') diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 24edb27cf13..5974d7768d4 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,6 +38,7 @@ endif COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o +COBJS-$(CONFIG_NAND_NOMADIK) += nomadik.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o endif diff --git a/drivers/mtd/nand/nomadik.c b/drivers/mtd/nand/nomadik.c new file mode 100644 index 00000000000..08944d1cfa1 --- /dev/null +++ b/drivers/mtd/nand/nomadik.c @@ -0,0 +1,221 @@ +/* + * (C) Copyright 2007 STMicroelectronics, + * (C) Copyright 2009 Alessandro Rubini + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include + +static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */ +{ + __asm__ __volatile__( + "eor %0, %0, %0, lsr #4\n\t" + "eor %0, %0, %0, lsr #2\n\t" + "eor %0, %0, %0, lsr #1\n\t" + "ands %0, %0, #1\n\t" + "subne %0, %0, #2\t" + : "=r" (b) : "0" (b)); + return b; +} + +/* + * This is the ECC routine used in hardware, according to the manual. + * HW claims to make the calculation but not the correction; so we must + * recalculate the bytes for a comparison. + */ +static int ecc512(unsigned char *data, unsigned char *ecc) +{ + int gpar = 0; + int i, val, par; + int pbits = 0; /* P8, P16, ... P2048 */ + int pprime = 0; /* P8', P16', ... P2048' */ + int lowbits; /* P1, P2, P4 and primes */ + + for (i = 0; i < 512; i++) { + par = parity((val = data[i])); + gpar ^= val; + pbits ^= (i & par); + } + /* + * Ok, now gpar is global parity (xor of all bytes) + * pbits are all the parity bits (non-prime ones) + */ + par = parity(gpar); + pprime = pbits ^ par; + /* Put low bits in the right position for ecc[2] (bits 7..2) */ + lowbits = 0 + | (parity(gpar & 0xf0) & 0x80) /* P4 */ + | (parity(gpar & 0x0f) & 0x40) /* P4' */ + | (parity(gpar & 0xcc) & 0x20) /* P2 */ + | (parity(gpar & 0x33) & 0x10) /* P2' */ + | (parity(gpar & 0xaa) & 0x08) /* P1 */ + | (parity(gpar & 0x55) & 0x04); /* P1' */ + + ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8)); + /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */ + ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1) + | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2) + | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3) + | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4)); + + ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3) + | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2) + | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1) + | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0)); + return 0; +} + +/* This is the method in the chip->ecc field */ +static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + return ecc512(dat, ecc_code); +} + +static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat, + uint8_t *r_ecc, uint8_t *c_ecc) +{ + struct nand_chip *chip = mtd->priv; + uint32_t r, c, d, diff; /*read, calculated, xor of them */ + + if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes)) + return 0; + + /* Reorder the bytes into ascending-order 24 bits -- see manual */ + r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2; + c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2; + diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */ + + /* If 12 bits are different, one per pair, it's correctable */ + if (((diff | (diff>>1)) & 0x555555) == 0x555555) { + int bit = ((diff & 2) >> 1) + | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3); + int byte; + + d = diff >> 6; /* remove bit-order info */ + byte = ((d & 2) >> 1) + | ((d & 0x8) >> 2) | ((d & 0x20) >> 3) + | ((d & 0x80) >> 4) | ((d & 0x200) >> 5) + | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7) + | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9); + /* correct the single bit */ + dat[byte] ^= 1<priv; + u32 pcr0 = readl(REG_FSMC_PCR0); + + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + if (ctrl & NAND_NCE) + writel(pcr0 | 0x4, REG_FSMC_PCR0); + else + writel(pcr0 & ~0x4, REG_FSMC_PCR0); + + this->IO_ADDR_W = (void *) IO_ADDR_W; + this->IO_ADDR_R = (void *) IO_ADDR_W; + } + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); +} + +/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */ +static int nomadik_nand_ready(struct mtd_info *mtd) +{ + return 1; /* The ready bit is handled in hardware */ +} + +/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */ +static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + int i; + struct nand_chip *chip = mtd->priv; + u32 *p = (u32 *) buf; + + len >>= 2; + writel(0, REG_FSMC_ECCR0); + for (i = 0; i < len; i++) + p[i] = readl(chip->IO_ADDR_R); +} + +int board_nand_init(struct nand_chip *chip) +{ + /* Set up the FSMC_PCR0 for nand access*/ + writel(0x0000004a, REG_FSMC_PCR0); + /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */ + writel(0x00020401, REG_FSMC_PMEM0); + writel(0x00020404, REG_FSMC_PATT0); + + chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; + chip->cmd_ctrl = nomadik_nand_hwcontrol; + chip->dev_ready = nomadik_nand_ready; + /* The chip allows 32bit reads, so avoid the default 8bit copy */ + chip->read_buf = nomadik_nand_read_buf; + + /* ECC: follow the hardware-defined rulse, but do it in sw */ + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.bytes = 3; + chip->ecc.size = 512; + chip->ecc.layout = &nomadik_ecc_layout; + chip->ecc.calculate = nomadik_ecc_calculate; + chip->ecc.hwctl = nomadik_ecc_hwctl; + chip->ecc.correct = nomadik_ecc_correct; + + return 0; +} diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h index a370f6cc510..0df989f325c 100644 --- a/include/configs/nmdk8815.h +++ b/include/configs/nmdk8815.h @@ -39,10 +39,14 @@ #include #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP -/* At this point there is no flash driver, so remove some commands */ -#undef CONFIG_CMD_ENV +/* There is no NOR flash, so undefine these commands */ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS +#define CONFIG_SYS_NO_FLASH +/* There is NAND storage */ +#define CONFIG_NAND_NOMADIK +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 /* user interface */ #define CONFIG_SYS_LONGHELP @@ -120,9 +124,7 @@ #define CONFIG_MTD_ONENAND_VERIFY_WRITE #define CONFIG_SYS_ONENAND_BASE 0x30000000 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 - -#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_NAND_BASE 0x40000000 /* SMPS0n */ #ifdef CONFIG_BOOT_ONENAND @@ -152,15 +154,11 @@ # define CONFIG_JFFS2_PART_OFFSET 0x00280000 # define CONFIG_ENV_IS_IN_NAND -# define CONFIG_ENV_SIZE 0x20000 /*128 Kb*/ +# define CONFIG_ENV_SIZE 0x20000 /* 128 Kb - one sector */ # define CONFIG_ENV_OFFSET (0x8000000 - CONFIG_ENV_SIZE) #endif /* CONFIG_BOOT_ONENAND */ -/* Temporarily, until we have no driver, env is not in nand */ -#undef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_IS_NOWHERE - /* this is needed to make hello_world.c and other stuff happy */ #define CONFIG_SYS_MAX_FLASH_SECT 512 #define CONFIG_SYS_MAX_FLASH_BANKS 1 -- cgit v1.3.1 From d3be1bcae7a8207e0a79ffd035d0e90f80378295 Mon Sep 17 00:00:00 2001 From: Alessandro Rubini Date: Mon, 9 Feb 2009 15:53:33 +0100 Subject: Enable Ethernet for Nomadik 8815 Evaluation Kit This trivially enables Ethernet support in the debug board by setting up the proper chip select. Signed-off-by: Alessandro Rubini Acked-by: Andrea Gallo --- board/st/nmdk8815/nmdk8815.c | 5 ++++- include/configs/nmdk8815.h | 3 +++ 2 files changed, 7 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/st/nmdk8815/nmdk8815.c b/board/st/nmdk8815/nmdk8815.c index c54eac12c7e..edf46262f5d 100644 --- a/board/st/nmdk8815/nmdk8815.c +++ b/board/st/nmdk8815/nmdk8815.c @@ -49,8 +49,11 @@ int board_init(void) writel(0x00000000, NOMADIK_GPIO1_BASE + 0x28); writel(readl(NOMADIK_SRC_BASE) | 0x8000, NOMADIK_SRC_BASE); - icache_enable(); + /* Set up SMCS1 for Ethernet: sram-like, enabled, timing values */ + writel(0x0000305b, REG_FSMC_BCR1); + writel(0x00033f33, REG_FSMC_BTR1); + icache_enable(); return 0; } diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h index 0df989f325c..b37352e0bcb 100644 --- a/include/configs/nmdk8815.h +++ b/include/configs/nmdk8815.h @@ -37,8 +37,11 @@ /* commands */ #include + +#define CONFIG_CMD_NET #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS /* There is no NOR flash, so undefine these commands */ #undef CONFIG_CMD_FLASH #undef CONFIG_CMD_IMLS -- cgit v1.3.1 From 4f5728987f4f9f7845688482aa2b7f2127768165 Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 22 Feb 2009 15:49:28 +0100 Subject: arm: add uart dcc support Serial driver via the EmbeddedICE macrocell's DCC channel using co-processor 14. It does include a timeout to ensure that the system does not totally freeze when there is nothing connected to read. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- common/devices.c | 3 + drivers/serial/Makefile | 1 + drivers/serial/arm_dcc.c | 226 +++++++++++++++++++++++++++++++++++++++++++++++ include/devices.h | 3 + lib_arm/board.c | 3 + 5 files changed, 236 insertions(+) create mode 100644 drivers/serial/arm_dcc.c (limited to 'include') diff --git a/common/devices.c b/common/devices.c index 38f1bbc6ae9..ba53c9bbec4 100644 --- a/common/devices.c +++ b/common/devices.c @@ -215,6 +215,9 @@ int devices_init (void) /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); +#ifdef CONFIG_ARM_DCC_MULTI + drv_arm_dcc_init (); +#endif #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index 0f980ab0a88..d0efd73c5bb 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libserial.a +COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o COBJS-$(CONFIG_ATMEL_USART) += atmel_usart.o COBJS-$(CONFIG_MCFUART) += mcfuart.o COBJS-$(CONFIG_NS9750_UART) += ns9750_serial.o diff --git a/drivers/serial/arm_dcc.c b/drivers/serial/arm_dcc.c new file mode 100644 index 00000000000..5a7fb6bc003 --- /dev/null +++ b/drivers/serial/arm_dcc.c @@ -0,0 +1,226 @@ +/* + * Copyright (C) 2004-2007 ARM Limited. + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version 2 + * as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * As a special exception, if other files instantiate templates or use macros + * or inline functions from this file, or you compile this file and link it + * with other works to produce a work based on this file, this file does not + * by itself cause the resulting work to be covered by the GNU General Public + * License. However the source code for this file must still be made available + * in accordance with section (3) of the GNU General Public License. + + * This exception does not invalidate any other reasons why a work based on + * this file might be covered by the GNU General Public License. + */ + +#include +#include + +#define DCC_ARM9_RBIT (1 << 0) +#define DCC_ARM9_WBIT (1 << 1) +#define DCC_ARM11_RBIT (1 << 30) +#define DCC_ARM11_WBIT (1 << 29) + +#define read_core_id(x) do { \ + __asm__ ("mrc p15, 0, %0, c0, c0, 0\n" : "=r" (x)); \ + x = (x >> 4) & 0xFFF; \ + } while (0); + +/* + * ARM9 + */ +#define write_arm9_dcc(x) \ + __asm__ volatile ("mcr p14, 0, %0, c1, c0, 0\n" : : "r" (x)) + +#define read_arm9_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c1, c0, 0\n" : "=r" (x)) + +#define status_arm9_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c0, 0\n" : "=r" (x)) + +#define can_read_arm9_dcc(x) do { \ + status_arm9_dcc(x); \ + x &= DCC_ARM9_RBIT; \ + } while (0); + +#define can_write_arm9_dcc(x) do { \ + status_arm9_dcc(x); \ + x &= DCC_ARM9_WBIT; \ + x = (x == 0); \ + } while (0); + +/* + * ARM11 + */ +#define write_arm11_dcc(x) \ + __asm__ volatile ("mcr p14, 0, %0, c0, c5, 0\n" : : "r" (x)) + +#define read_arm11_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c5, 0\n" : "=r" (x)) + +#define status_arm11_dcc(x) \ + __asm__ volatile ("mrc p14, 0, %0, c0, c1, 0\n" : "=r" (x)) + +#define can_read_arm11_dcc(x) do { \ + status_arm11_dcc(x); \ + x &= DCC_ARM11_RBIT; \ + } while (0); + +#define can_write_arm11_dcc(x) do { \ + status_arm11_dcc(x); \ + x &= DCC_ARM11_WBIT; \ + x = (x == 0); \ + } while (0); + +#define TIMEOUT_COUNT 0x4000000 + +static enum { + arm9_and_earlier, + arm11_and_later +} arm_type = arm9_and_earlier; + +#ifndef CONFIG_ARM_DCC_MULTI +#define arm_dcc_init serial_init +void serial_setbrg(void) {} +#define arm_dcc_getc serial_getc +#define arm_dcc_putc serial_putc +#define arm_dcc_puts serial_puts +#define arm_dcc_tstc serial_tstc +#endif + +int arm_dcc_init(void) +{ + register unsigned int id; + + read_core_id(id); + + if (id >= 0xb00) + arm_type = arm11_and_later; + else + arm_type = arm9_and_earlier; + + return 0; +} + +int arm_dcc_getc(void) +{ + int ch; + register unsigned int reg; + + switch (arm_type) { + case arm11_and_later: + do { + can_read_arm11_dcc(reg); + } while (!reg); + read_arm11_dcc(ch); + break; + + case arm9_and_earlier: + default: + do { + can_read_arm9_dcc(reg); + } while (!reg); + read_arm9_dcc(ch); + break; + } + + return ch; +} + +void arm_dcc_putc(char ch) +{ + register unsigned int reg; + unsigned int timeout_count = TIMEOUT_COUNT; + + switch (arm_type) { + case arm11_and_later: + while (--timeout_count) { + can_write_arm11_dcc(reg); + if (reg) + break; + } + if (timeout_count == 0) + return; + else + write_arm11_dcc(ch); + break; + + case arm9_and_earlier: + default: + while (--timeout_count) { + can_write_arm9_dcc(reg); + if (reg) + break; + } + if (timeout_count == 0) + return; + else + write_arm9_dcc(ch); + break; + } +} + +void arm_dcc_puts(const char *s) +{ + while (*s) + arm_dcc_putc(*s++); +} + +int arm_dcc_tstc(void) +{ + register unsigned int reg; + + switch (arm_type) { + case arm11_and_later: + can_read_arm11_dcc(reg); + break; + case arm9_and_earlier: + default: + can_read_arm9_dcc(reg); + break; + } + + return reg; +} + +#ifdef CONFIG_ARM_DCC_MULTI +static device_t arm_dcc_dev; + +int drv_arm_dcc_init(void) +{ + int rc; + + /* Device initialization */ + memset(&arm_dcc_dev, 0, sizeof(arm_dcc_dev)); + + strcpy(arm_dcc_dev.name, "dcc"); + arm_dcc_dev.ext = 0; /* No extensions */ + arm_dcc_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_OUTPUT; + arm_dcc_dev.tstc = arm_dcc_tstc; /* 'tstc' function */ + arm_dcc_dev.getc = arm_dcc_getc; /* 'getc' function */ + arm_dcc_dev.putc = arm_dcc_putc; /* 'putc' function */ + arm_dcc_dev.puts = arm_dcc_puts; /* 'puts' function */ + + rc = device_register(&arm_dcc_dev); + + if (rc == 0) { + arm_dcc_init(); + return 1; + } + + return 0; +} +#endif diff --git a/include/devices.h b/include/devices.h index 84c4514880e..3a9881bf049 100644 --- a/include/devices.h +++ b/include/devices.h @@ -98,6 +98,9 @@ struct list_head* device_get_list(void); device_t* device_get_by_name(char* name); device_t* device_clone(device_t *dev); +#ifdef CONFIG_ARM_DCC_MULTI +int drv_arm_dcc_init(void); +#endif #ifdef CONFIG_LCD int drv_lcd_init (void); #endif diff --git a/lib_arm/board.c b/lib_arm/board.c index f125d38b0b6..09eaaf25c41 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -145,6 +145,9 @@ void inline yellow_LED_off(void)__attribute__((weak, alias("__yellow_LED_off"))) * but let's get it working (again) first... */ +#if defined(CONFIG_ARM_DCC) && !defined(CONFIG_BAUDRATE) +#define CONFIG_BAUDRATE 115200 +#endif static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ -- cgit v1.3.1 From 2579019b8248e5f166e60e37065766efc8a49dbc Mon Sep 17 00:00:00 2001 From: Jean-Christophe PLAGNIOL-VILLARD Date: Sun, 22 Feb 2009 17:08:41 +0100 Subject: nmdk8815: fix onenand support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD --- include/configs/nmdk8815.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'include') diff --git a/include/configs/nmdk8815.h b/include/configs/nmdk8815.h index b37352e0bcb..543780d77f2 100644 --- a/include/configs/nmdk8815.h +++ b/include/configs/nmdk8815.h @@ -48,7 +48,6 @@ #define CONFIG_SYS_NO_FLASH /* There is NAND storage */ #define CONFIG_NAND_NOMADIK -#define CONFIG_CMD_NAND #define CONFIG_CMD_JFFS2 /* user interface */ @@ -131,7 +130,7 @@ #ifdef CONFIG_BOOT_ONENAND -# undef CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ +# define CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ /* Partition Size Start * XloaderTOC + X-Loader 256KB 0x00000000 * Memory init function 256KB 0x00040000 @@ -149,7 +148,7 @@ #else /* ! CONFIG_BOOT_ONENAND */ -# undef CONFIG_CMD_ONENAND /* Temporary: nand and onenand can't coexist */ +# define CONFIG_CMD_NAND /* Temporary: nand and onenand can't coexist */ # define CONFIG_JFFS2_DEV "nand0" # define CONFIG_JFFS2_NAND 1 /* For the jffs2 support*/ -- cgit v1.3.1 From f956fd0338f4990793a10f767929ba4963665261 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Thu, 12 Feb 2009 18:55:41 +0100 Subject: OMAP3: Beagle: Add board revision detection With BeagleBoard revision C some HW changes are introduced (e.g. PinMUX) which might need different software handling. For this, GPIO pin 171 (GPIO module 6, offset 11) can be used to check for board revision. If this pin is low, we have a rev C board. Else it must be a revision Ax or Bx board. To handle board differences you can call function beagle_get_revision(). E.g.: if (beagle_get_revision()) { /* do special revision C stuff here */ } Signed-off-by: Dirk Behme --- board/omap3/beagle/beagle.c | 41 ++++++++++++++++++++++++++++++++++++++ board/omap3/beagle/beagle.h | 2 ++ include/asm-arm/arch-omap3/omap3.h | 3 ++- 3 files changed, 45 insertions(+), 1 deletion(-) (limited to 'include') diff --git a/board/omap3/beagle/beagle.c b/board/omap3/beagle/beagle.c index ecdea09382a..7377058f794 100644 --- a/board/omap3/beagle/beagle.c +++ b/board/omap3/beagle/beagle.c @@ -36,6 +36,8 @@ #include #include "beagle.h" +static int beagle_revision_c; + /****************************************************************************** * Routine: board_init * Description: Early hardware init. @@ -53,6 +55,43 @@ int board_init(void) return 0; } +/****************************************************************************** + * Routine: beagle_get_revision + * Description: Return revision of the BeagleBoard this code is running on. + * If it is a revision Ax/Bx board, this function returns 0, + * on a revision C board you will get a 1. + *****************************************************************************/ +int beagle_get_revision(void) +{ + return beagle_revision_c; +} + +/****************************************************************************** + * Routine: beagle_identify + * Description: Detect if we are running on a Beagle revision Ax/Bx or + * Cx. This can be done by GPIO_171. If this is low, we are + * running on a revision C board. + *****************************************************************************/ +void beagle_identify(void) +{ + gpio_t *gpio6_base = (gpio_t *)OMAP34XX_GPIO6_BASE; + + /* Configure GPIO 171 as input */ + writel(readl(&gpio6_base->oe) | GPIO11, &gpio6_base->oe); + + /* Get value of GPIO 171 */ + beagle_revision_c = readl(&gpio6_base->datain) & BOARD_REVISION_MASK; + + printf("Board revision "); + if (beagle_revision_c) { + printf("Ax/Bx\n"); + beagle_revision_c = 0; + } else { + printf("C\n"); + beagle_revision_c = 1; + } +} + /****************************************************************************** * Routine: misc_init_r * Description: Configure board specific parts @@ -75,6 +114,8 @@ int misc_init_r(void) writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 | GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout); + beagle_identify(); + return 0; } diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h index 6511ffaaa72..3f2a4dc22d4 100644 --- a/board/omap3/beagle/beagle.h +++ b/board/omap3/beagle/beagle.h @@ -36,6 +36,8 @@ const omap3_sysinfo sysinfo = { #endif }; +#define BOARD_REVISION_MASK (0x1 << 11) + /* * IEN - Input Enable * IDIS - Input Disable diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index 7473656532e..0ddbd660ca1 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -97,7 +97,8 @@ typedef struct s32ktimer { typedef struct gpio { unsigned char res1[0x34]; unsigned int oe; /* 0x34 */ - unsigned char res2[0x58]; + unsigned int datain; /* 0x38 */ + unsigned char res2[0x54]; unsigned int cleardataout; /* 0x90 */ unsigned int setdataout; /* 0x94 */ } gpio_t; -- cgit v1.3.1 From 6530a8bf8a0274b9419141e4c2c5a235cce5380f Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Thu, 12 Feb 2009 18:55:42 +0100 Subject: OMAP3: Add OMAP3 auto detection This patch adds OMAP3 cpu type auto detection based on OMAP3 register and removes hardcoded values. Signed-off-by: Steve Sakoman Signed-off-by: Dirk Behme --- board/omap3/beagle/beagle.h | 1 - board/omap3/evm/evm.h | 1 - board/omap3/overo/overo.h | 1 - board/omap3/pandora/pandora.h | 1 - board/omap3/zoom1/zoom1.h | 1 - cpu/arm_cortexa8/omap3/sys_info.c | 31 +++++++++++++++++++++++++++++-- include/asm-arm/arch-omap3/cpu.h | 20 ++++++++++++++++++++ include/asm-arm/arch-omap3/sys_proto.h | 1 - 8 files changed, 49 insertions(+), 8 deletions(-) (limited to 'include') diff --git a/board/omap3/beagle/beagle.h b/board/omap3/beagle/beagle.h index 3f2a4dc22d4..d66f159d27b 100644 --- a/board/omap3/beagle/beagle.h +++ b/board/omap3/beagle/beagle.h @@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = { SDP_3430_V1, SDP_3430_V2, DDR_STACKED, - "3530", "OMAP3 Beagle board", #if defined(CONFIG_ENV_IS_IN_ONENAND) "OneNAND", diff --git a/board/omap3/evm/evm.h b/board/omap3/evm/evm.h index 4ecea7f42b3..199824f4c44 100644 --- a/board/omap3/evm/evm.h +++ b/board/omap3/evm/evm.h @@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = { OMAP3EVM_V1, OMAP3EVM_V2, DDR_DISCRETE, - "35X-Family", "OMAP3 EVM board", #if defined(CONFIG_ENV_IS_IN_ONENAND) "OneNAND", diff --git a/board/omap3/overo/overo.h b/board/omap3/overo/overo.h index f44b2ad0c89..71de3f10d3a 100644 --- a/board/omap3/overo/overo.h +++ b/board/omap3/overo/overo.h @@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = { SDP_3430_V1, SDP_3430_V2, DDR_STACKED, - "3503", "Gumstix Overo board", #if defined(CONFIG_ENV_IS_IN_ONENAND) "OneNAND", diff --git a/board/omap3/pandora/pandora.h b/board/omap3/pandora/pandora.h index 8525a03c5ff..f8455047cdc 100644 --- a/board/omap3/pandora/pandora.h +++ b/board/omap3/pandora/pandora.h @@ -27,7 +27,6 @@ const omap3_sysinfo sysinfo = { SDP_3430_V1, SDP_3430_V2, DDR_STACKED, - "3530", "OMAP3 Pandora", "NAND", }; diff --git a/board/omap3/zoom1/zoom1.h b/board/omap3/zoom1/zoom1.h index d3894928a5e..bc8fba89ebf 100644 --- a/board/omap3/zoom1/zoom1.h +++ b/board/omap3/zoom1/zoom1.h @@ -31,7 +31,6 @@ const omap3_sysinfo sysinfo = { SDP_3430_V1, SDP_3430_V2, DDR_STACKED, - "3430", "OMAP3 Zoom MDK Rev 1", "NAND", }; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index ab012b6a9b1..28a102091a8 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -36,6 +36,14 @@ static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE; static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE; static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE; +/****************************************** + * get_cpu_type(void) - extract cpu info + ******************************************/ +u32 get_cpu_type(void) +{ + return readl(&ctrl_base->ctrl_omap_stat); +} + /****************************************** * get_cpu_rev(void) - extract version info ******************************************/ @@ -156,7 +164,25 @@ u32 get_board_rev(void) *********************************************************************/ void display_board_info(u32 btype) { - char *mem_s, *sec_s; + char *cpu_s, *mem_s, *sec_s; + + switch (get_cpu_type()) { + case OMAP3503: + cpu_s = "3503"; + break; + case OMAP3515: + cpu_s = "3515"; + break; + case OMAP3525: + cpu_s = "3525"; + break; + case OMAP3530: + cpu_s = "3530"; + break; + default: + cpu_s = "35XX"; + break; + } if (is_mem_sdr()) mem_s = "mSDR"; @@ -180,7 +206,8 @@ void display_board_info(u32 btype) sec_s = "?"; } - printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", sysinfo.cpu_string, + + printf("OMAP%s-%s rev %d, CPU-OPP2 L3-165MHz\n", cpu_s, sec_s, get_cpu_rev()); printf("%s + %s/%s\n", sysinfo.board_string, mem_s, sysinfo.nand_string); diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 69c0b368d45..5b344f83782 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -35,11 +35,31 @@ typedef struct ctrl { unsigned short gpmc_nwe; /* 0xC4 */ unsigned char res2[0x22A]; unsigned int status; /* 0x2F0 */ + unsigned int gpstatus; /* 0x2F4 */ + unsigned char res3[0x08]; + unsigned int rpubkey_0; /* 0x300 */ + unsigned int rpubkey_1; /* 0x304 */ + unsigned int rpubkey_2; /* 0x308 */ + unsigned int rpubkey_3; /* 0x30C */ + unsigned int rpubkey_4; /* 0x310 */ + unsigned char res4[0x04]; + unsigned int randkey_0; /* 0x318 */ + unsigned int randkey_1; /* 0x31C */ + unsigned int randkey_2; /* 0x320 */ + unsigned int randkey_3; /* 0x324 */ + unsigned char res5[0x124]; + unsigned int ctrl_omap_stat; /* 0x44C */ } ctrl_t; #else /* __ASSEMBLY__ */ #define CONTROL_STATUS 0x2F0 #endif /* __ASSEMBLY__ */ +/* cpu type */ +#define OMAP3503 0x5c00 +#define OMAP3515 0x1c00 +#define OMAP3525 0x4c00 +#define OMAP3530 0x0c00 + /* device type */ #define DEVICE_MASK (0x7 << 8) #define SYSBOOT_MASK 0x1F diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 4c624e835ca..ab3e1683f6e 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -25,7 +25,6 @@ typedef struct { u32 board_type_v1; u32 board_type_v2; u32 mtype; - char *cpu_string; char *board_string; char *nand_string; } omap3_sysinfo; -- cgit v1.3.1 From aba45c85b22f8c57fc2fedba8e948e06c2e2f5b3 Mon Sep 17 00:00:00 2001 From: Dirk Behme Date: Fri, 20 Feb 2009 17:51:28 +0100 Subject: OMAP3: Clean up MMC code Clean up OMAP3 MMC code: * Convert register access to struct & readx/writex style * Replace hardcode values by macros * Remove macro defined twice Signed-off-by: Dirk Behme --- drivers/mmc/omap3_mmc.c | 137 +++++++++++++++--------------- include/asm-arm/arch-omap3/mmc_host_def.h | 64 +++++++++----- include/asm-arm/arch-omap3/omap3.h | 3 + 3 files changed, 114 insertions(+), 90 deletions(-) (limited to 'include') diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index 399c57b7054..e90db7ee337 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -28,6 +28,7 @@ #include #include #include +#include #include const unsigned short mmc_transspeed_val[15][4] = { @@ -50,6 +51,7 @@ const unsigned short mmc_transspeed_val[15][4] = { mmc_card_data cur_card_data; static block_dev_desc_t mmc_blk_dev; +static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE; block_dev_desc_t *mmc_get_dev(int dev) { @@ -60,55 +62,49 @@ void twl4030_mmc_config(void) { unsigned char data; - data = 0x20; - i2c_write(0x4B, 0x82, 1, &data, 1); - data = 0x2; - i2c_write(0x4B, 0x85, 1, &data, 1); + data = DEV_GRP_P1; + i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1); + data = VMMC1_VSEL_30; + i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEDICATED, 1, &data, 1); } unsigned char mmc_board_init(void) { - unsigned int value = 0; + t2_t *t2_base = (t2_t *)T2_BASE; twl4030_mmc_config(); - value = CONTROL_PBIAS_LITE; - CONTROL_PBIAS_LITE = value | (1 << 2) | (1 << 1) | (1 << 9); + writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 | + PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0, + &t2_base->pbias_lite); - value = CONTROL_DEV_CONF0; - CONTROL_DEV_CONF0 = value | (1 << 24); + writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL, + &t2_base->devconf0); return 1; } void mmc_init_stream(void) { - volatile unsigned int mmc_stat; + writel(readl(&mmc_base->con) | INIT_INITSTREAM, &mmc_base->con); - OMAP_HSMMC_CON |= INIT_INITSTREAM; + writel(MMC_CMD0, &mmc_base->cmd); + while (!(readl(&mmc_base->stat) & CC_MASK)); - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); - - OMAP_HSMMC_STAT = CC_MASK; + writel(CC_MASK, &mmc_base->stat); - OMAP_HSMMC_CMD = MMC_CMD0; - do { - mmc_stat = OMAP_HSMMC_STAT; - } while (!(mmc_stat & CC_MASK)); + writel(MMC_CMD0, &mmc_base->cmd); + while (!(readl(&mmc_base->stat) & CC_MASK)); - OMAP_HSMMC_STAT = OMAP_HSMMC_STAT; - OMAP_HSMMC_CON &= ~INIT_INITSTREAM; + writel(readl(&mmc_base->con) & ~INIT_INITSTREAM, &mmc_base->con); } unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) { unsigned int val; - mmc_reg_out(OMAP_HSMMC_SYSCTL, (ICE_MASK | DTO_MASK | CEN_MASK), - (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); + mmc_reg_out(&mmc_base->sysctl, (ICE_MASK | DTO_MASK | CEN_MASK), + (ICE_STOP | DTO_15THDTO | CEN_DISABLE)); switch (iclk) { case CLK_INITSEQ: @@ -123,12 +119,12 @@ unsigned char mmc_clock_config(unsigned int iclk, unsigned short clk_div) default: return 0; } - mmc_reg_out(OMAP_HSMMC_SYSCTL, - ICE_MASK | CLKD_MASK, (val << CLKD_OFFSET) | ICE_OSCILLATE); + mmc_reg_out(&mmc_base->sysctl, ICE_MASK | CLKD_MASK, + (val << CLKD_OFFSET) | ICE_OSCILLATE); - while ((OMAP_HSMMC_SYSCTL & ICS_MASK) == ICS_NOTREADY) ; + while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY); - OMAP_HSMMC_SYSCTL |= CEN_ENABLE; + writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl); return 1; } @@ -138,59 +134,63 @@ unsigned char mmc_init_setup(void) mmc_board_init(); - OMAP_HSMMC_SYSCONFIG |= MMC_SOFTRESET; - while ((OMAP_HSMMC_SYSSTATUS & RESETDONE) == 0) ; + writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET, + &mmc_base->sysconfig); + while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0); - OMAP_HSMMC_SYSCTL |= SOFTRESETALL; - while ((OMAP_HSMMC_SYSCTL & SOFTRESETALL) != 0x0) ; + writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl); + while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0); - OMAP_HSMMC_HCTL = DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0; - OMAP_HSMMC_CAPA |= VS30_3V0SUP | VS18_1V8SUP; + writel(DTW_1_BITMODE | SDBP_PWROFF | SDVS_3V0, &mmc_base->hctl); + writel(readl(&mmc_base->capa) | VS30_3V0SUP | VS18_1V8SUP, + &mmc_base->capa); - reg_val = OMAP_HSMMC_CON & RESERVED_MASK; + reg_val = readl(&mmc_base->con) & RESERVED_MASK; - OMAP_HSMMC_CON = CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | - CDP_ACTIVEHIGH | MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | - STR_BLOCK | HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN; + writel(CTPL_MMC_SD | reg_val | WPP_ACTIVEHIGH | CDP_ACTIVEHIGH | + MIT_CTO | DW8_1_4BITMODE | MODE_FUNC | STR_BLOCK | + HR_NOHOSTRESP | INIT_NOINIT | NOOPENDRAIN, &mmc_base->con); mmc_clock_config(CLK_INITSEQ, 0); - OMAP_HSMMC_HCTL |= SDBP_PWRON; + writel(readl(&mmc_base->hctl) | SDBP_PWRON, &mmc_base->hctl); - OMAP_HSMMC_IE = 0x307f0033; + writel(IE_BADA | IE_CERR | IE_DEB | IE_DCRC | IE_DTO | IE_CIE | + IE_CEB | IE_CCRC | IE_CTO | IE_BRR | IE_BWR | IE_TC | IE_CC, + &mmc_base->ie); mmc_init_stream(); return 1; } unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, - unsigned int *response) + unsigned int *response) { - volatile unsigned int mmc_stat; + unsigned int mmc_stat; - while ((OMAP_HSMMC_PSTATE & DATI_MASK) == DATI_CMDDIS) ; + while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS); - OMAP_HSMMC_BLK = BLEN_512BYTESLEN | NBLK_STPCNT; - OMAP_HSMMC_STAT = 0xFFFFFFFF; - OMAP_HSMMC_ARG = arg; - OMAP_HSMMC_CMD = cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | - CCCE_NOCHECK | MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | - DE_DISABLE; + writel(BLEN_512BYTESLEN | NBLK_STPCNT, &mmc_base->blk); + writel(0xFFFFFFFF, &mmc_base->stat); + writel(arg, &mmc_base->arg); + writel(cmd | CMD_TYPE_NORMAL | CICE_NOCHECK | CCCE_NOCHECK | + MSBS_SGLEBLK | ACEN_DISABLE | BCE_DISABLE | DE_DISABLE, + &mmc_base->cmd); while (1) { do { - mmc_stat = OMAP_HSMMC_STAT; + mmc_stat = readl(&mmc_base->stat); } while (mmc_stat == 0); if ((mmc_stat & ERRI_MASK) != 0) return (unsigned char) mmc_stat; if (mmc_stat & CC_MASK) { - OMAP_HSMMC_STAT = CC_MASK; - response[0] = OMAP_HSMMC_RSP10; + writel(CC_MASK, &mmc_base->stat); + response[0] = readl(&mmc_base->rsp10); if ((cmd & RSP_TYPE_MASK) == RSP_TYPE_LGHT136) { - response[1] = OMAP_HSMMC_RSP32; - response[2] = OMAP_HSMMC_RSP54; - response[3] = OMAP_HSMMC_RSP76; + response[1] = readl(&mmc_base->rsp32); + response[2] = readl(&mmc_base->rsp54); + response[3] = readl(&mmc_base->rsp76); } break; } @@ -200,7 +200,7 @@ unsigned char mmc_send_cmd(unsigned int cmd, unsigned int arg, unsigned char mmc_read_data(unsigned int *output_buf) { - volatile unsigned int mmc_stat; + unsigned int mmc_stat; unsigned int read_count = 0; /* @@ -208,7 +208,7 @@ unsigned char mmc_read_data(unsigned int *output_buf) */ while (1) { do { - mmc_stat = OMAP_HSMMC_STAT; + mmc_stat = readl(&mmc_base->stat); } while (mmc_stat == 0); if ((mmc_stat & ERRI_MASK) != 0) @@ -217,19 +217,22 @@ unsigned char mmc_read_data(unsigned int *output_buf) if (mmc_stat & BRR_MASK) { unsigned int k; - OMAP_HSMMC_STAT |= BRR_MASK; + writel(readl(&mmc_base->stat) | BRR_MASK, + &mmc_base->stat); for (k = 0; k < MMCSD_SECTOR_SIZE / 4; k++) { - *output_buf = OMAP_HSMMC_DATA; + *output_buf = readl(&mmc_base->data); output_buf++; read_count += 4; } } if (mmc_stat & BWR_MASK) - OMAP_HSMMC_STAT |= BWR_MASK; + writel(readl(&mmc_base->stat) | BWR_MASK, + &mmc_base->stat); if (mmc_stat & TC_MASK) { - OMAP_HSMMC_STAT |= TC_MASK; + writel(readl(&mmc_base->stat) | TC_MASK, + &mmc_base->stat); break; } } @@ -273,8 +276,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) mmc_card_cur->card_type = MMC_CARD; ocr_value |= MMC_OCR_REG_ACCESS_MODE_SECTOR; ret_cmd41 = MMC_CMD1; - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= OPENDRAIN; + writel(readl(&mmc_base->con) & ~OD, &mmc_base->con); + writel(readl(&mmc_base->con) | OPENDRAIN, &mmc_base->con); } argument = ocr_value; @@ -342,8 +345,8 @@ unsigned char mmc_detect_card(mmc_card_data *mmc_card_cur) mmc_card_cur->RCA = ((mmc_resp_r6 *) resp)->newpublishedrca; } - OMAP_HSMMC_CON &= ~OD; - OMAP_HSMMC_CON |= NOOPENDRAIN; + writel(readl(&mmc_base->con) & ~OD, &mmc_base->con); + writel(readl(&mmc_base->con) | NOOPENDRAIN, &mmc_base->con); return 1; } @@ -518,7 +521,7 @@ unsigned long mmc_bread(int dev_num, unsigned long blknr, lbaint_t blkcnt, void *dst) { omap_mmc_read_sect(blknr, (blkcnt * MMCSD_SECTOR_SIZE), &cur_card_data, - (unsigned long *) dst); + (unsigned long *) dst); return 1; } diff --git a/include/asm-arm/arch-omap3/mmc_host_def.h b/include/asm-arm/arch-omap3/mmc_host_def.h index dfb376a6c5c..aa751c9a346 100644 --- a/include/asm-arm/arch-omap3/mmc_host_def.h +++ b/include/asm-arm/arch-omap3/mmc_host_def.h @@ -25,30 +25,50 @@ #ifndef MMC_HOST_DEF_H #define MMC_HOST_DEF_H +/* T2 Register definitions */ +#define T2_BASE 0x48002000 + +typedef struct t2 { + unsigned char res1[0x274]; + unsigned int devconf0; /* 0x274 */ + unsigned char res2[0x2A8]; + unsigned int pbias_lite; /* 0x520 */ +} t2_t; + +#define MMCSDIO1ADPCLKISEL (1 << 24) + +#define PBIASLITEPWRDNZ0 (1 << 1) +#define PBIASSPEEDCTRL0 (1 << 2) +#define PBIASLITEPWRDNZ1 (1 << 9) + /* * OMAP HSMMC register definitions */ -#define OMAP_HSMMC_SYSCONFIG (*(unsigned int *) 0x4809C010) -#define OMAP_HSMMC_SYSSTATUS (*(unsigned int *) 0x4809C014) -#define OMAP_HSMMC_CON (*(unsigned int *) 0x4809C02C) -#define OMAP_HSMMC_BLK (*(unsigned int *) 0x4809C104) -#define OMAP_HSMMC_ARG (*(unsigned int *) 0x4809C108) -#define OMAP_HSMMC_CMD (*(unsigned int *) 0x4809C10C) -#define OMAP_HSMMC_RSP10 (*(unsigned int *) 0x4809C110) -#define OMAP_HSMMC_RSP32 (*(unsigned int *) 0x4809C114) -#define OMAP_HSMMC_RSP54 (*(unsigned int *) 0x4809C118) -#define OMAP_HSMMC_RSP76 (*(unsigned int *) 0x4809C11C) -#define OMAP_HSMMC_DATA (*(unsigned int *) 0x4809C120) -#define OMAP_HSMMC_PSTATE (*(unsigned int *) 0x4809C124) -#define OMAP_HSMMC_HCTL (*(unsigned int *) 0x4809C128) -#define OMAP_HSMMC_SYSCTL (*(unsigned int *) 0x4809C12C) -#define OMAP_HSMMC_STAT (*(unsigned int *) 0x4809C130) -#define OMAP_HSMMC_IE (*(unsigned int *) 0x4809C134) -#define OMAP_HSMMC_CAPA (*(unsigned int *) 0x4809C140) +#define OMAP_HSMMC_BASE 0x4809C000 -/* T2 Register definitions */ -#define CONTROL_DEV_CONF0 (*(unsigned int *) 0x48002274) -#define CONTROL_PBIAS_LITE (*(unsigned int *) 0x48002520) +typedef struct hsmmc { + unsigned char res1[0x10]; + unsigned int sysconfig; /* 0x10 */ + unsigned int sysstatus; /* 0x14 */ + unsigned char res2[0x14]; + unsigned int con; /* 0x2C */ + unsigned char res3[0xD4]; + unsigned int blk; /* 0x104 */ + unsigned int arg; /* 0x108 */ + unsigned int cmd; /* 0x10C */ + unsigned int rsp10; /* 0x110 */ + unsigned int rsp32; /* 0x114 */ + unsigned int rsp54; /* 0x118 */ + unsigned int rsp76; /* 0x11C */ + unsigned int data; /* 0x120 */ + unsigned int pstate; /* 0x124 */ + unsigned int hctl; /* 0x128 */ + unsigned int sysctl; /* 0x12C */ + unsigned int stat; /* 0x130 */ + unsigned int ie; /* 0x134 */ + unsigned char res4[0x8]; + unsigned int capa; /* 0x140 */ +} hsmmc_t; /* * OMAP HS MMC Bit definitions @@ -159,8 +179,6 @@ typedef struct { } mmc_card_data; #define mmc_reg_out(addr, mask, val)\ - (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); -#define mmc_reg_out(addr, mask, val)\ - (addr) = (((addr)) & (~(mask))) | ((val) & (mask)); + writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr)) #endif /* MMC_HOST_DEF_H */ diff --git a/include/asm-arm/arch-omap3/omap3.h b/include/asm-arm/arch-omap3/omap3.h index 0ddbd660ca1..02e36d7e3f6 100644 --- a/include/asm-arm/arch-omap3/omap3.h +++ b/include/asm-arm/arch-omap3/omap3.h @@ -203,6 +203,8 @@ typedef struct gpio { #define VAUX2_DEDICATED 0x79 #define VAUX3_DEV_GRP 0x7A #define VAUX3_DEDICATED 0x7D +#define VMMC1_DEV_GRP 0x82 +#define VMMC1_DEDICATED 0x85 #define VPLL2_DEV_GRP 0x8E #define VPLL2_DEDICATED 0x91 #define VDAC_DEV_GRP 0x96 @@ -215,5 +217,6 @@ typedef struct gpio { #define VAUX3_VSEL_28 0x03 #define VPLL2_VSEL_18 0x05 #define VDAC_VSEL_18 0x03 +#define VMMC1_VSEL_30 0x02 #endif -- cgit v1.3.1